diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/oprofile/nmi_int.c | 100 | ||||
-rw-r--r-- | arch/x86/oprofile/op_counter.h | 3 | ||||
-rw-r--r-- | arch/x86/oprofile/op_model_amd.c | 76 | ||||
-rw-r--r-- | arch/x86/oprofile/op_model_p4.c | 4 | ||||
-rw-r--r-- | arch/x86/oprofile/op_model_ppro.c | 2 | ||||
-rw-r--r-- | arch/x86/oprofile/op_x86_model.h | 3 |
6 files changed, 39 insertions, 149 deletions
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c index 4108d02c5292..287513a09819 100644 --- a/arch/x86/oprofile/nmi_int.c +++ b/arch/x86/oprofile/nmi_int.c | |||
@@ -23,18 +23,12 @@ | |||
23 | #include "op_counter.h" | 23 | #include "op_counter.h" |
24 | #include "op_x86_model.h" | 24 | #include "op_x86_model.h" |
25 | 25 | ||
26 | DEFINE_PER_CPU(int, switch_index); | ||
27 | |||
28 | static struct op_x86_model_spec const *model; | 26 | static struct op_x86_model_spec const *model; |
29 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); | 27 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
30 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); | 28 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); |
31 | 29 | ||
32 | static int nmi_start(void); | 30 | static int nmi_start(void); |
33 | static void nmi_stop(void); | 31 | static void nmi_stop(void); |
34 | static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs); | ||
35 | static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs); | ||
36 | static void nmi_cpu_stop(void *dummy); | ||
37 | static void nmi_cpu_start(void *dummy); | ||
38 | 32 | ||
39 | /* 0 == registered but off, 1 == registered and on */ | 33 | /* 0 == registered but off, 1 == registered and on */ |
40 | static int nmi_enabled = 0; | 34 | static int nmi_enabled = 0; |
@@ -87,47 +81,6 @@ static void exit_sysfs(void) | |||
87 | #define exit_sysfs() do { } while (0) | 81 | #define exit_sysfs() do { } while (0) |
88 | #endif /* CONFIG_PM */ | 82 | #endif /* CONFIG_PM */ |
89 | 83 | ||
90 | static void nmi_cpu_switch(void *dummy) | ||
91 | { | ||
92 | int cpu = smp_processor_id(); | ||
93 | int si = per_cpu(switch_index, cpu); | ||
94 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); | ||
95 | |||
96 | nmi_cpu_stop(NULL); | ||
97 | nmi_cpu_save_mpx_registers(msrs); | ||
98 | |||
99 | /* move to next set */ | ||
100 | si += model->num_hardware_counters; | ||
101 | if ((si > model->num_counters) || (counter_config[si].count == 0)) | ||
102 | per_cpu(switch_index, smp_processor_id()) = 0; | ||
103 | else | ||
104 | per_cpu(switch_index, smp_processor_id()) = si; | ||
105 | |||
106 | nmi_cpu_restore_mpx_registers(msrs); | ||
107 | model->setup_ctrs(msrs); | ||
108 | nmi_cpu_start(NULL); | ||
109 | } | ||
110 | |||
111 | /* | ||
112 | * Quick check to see if multiplexing is necessary. | ||
113 | * The check should be sufficient since counters are used | ||
114 | * in ordre. | ||
115 | */ | ||
116 | static int nmi_multiplex_on(void) | ||
117 | { | ||
118 | return counter_config[model->num_hardware_counters].count ? 0 : -EINVAL; | ||
119 | } | ||
120 | |||
121 | static int nmi_switch_event(void) | ||
122 | { | ||
123 | if (nmi_multiplex_on() < 0) | ||
124 | return -EINVAL; | ||
125 | |||
126 | on_each_cpu(nmi_cpu_switch, NULL, 1); | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static int profile_exceptions_notify(struct notifier_block *self, | 84 | static int profile_exceptions_notify(struct notifier_block *self, |
132 | unsigned long val, void *data) | 85 | unsigned long val, void *data) |
133 | { | 86 | { |
@@ -191,10 +144,11 @@ static void free_msrs(void) | |||
191 | 144 | ||
192 | static int allocate_msrs(void) | 145 | static int allocate_msrs(void) |
193 | { | 146 | { |
194 | int i, success = 1; | 147 | int success = 1; |
195 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; | 148 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
196 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; | 149 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; |
197 | 150 | ||
151 | int i; | ||
198 | for_each_possible_cpu(i) { | 152 | for_each_possible_cpu(i) { |
199 | per_cpu(cpu_msrs, i).counters = kmalloc(counters_size, | 153 | per_cpu(cpu_msrs, i).counters = kmalloc(counters_size, |
200 | GFP_KERNEL); | 154 | GFP_KERNEL); |
@@ -202,8 +156,8 @@ static int allocate_msrs(void) | |||
202 | success = 0; | 156 | success = 0; |
203 | break; | 157 | break; |
204 | } | 158 | } |
205 | per_cpu(cpu_msrs, i).controls = | 159 | per_cpu(cpu_msrs, i).controls = kmalloc(controls_size, |
206 | kmalloc(controls_size, GFP_KERNEL); | 160 | GFP_KERNEL); |
207 | if (!per_cpu(cpu_msrs, i).controls) { | 161 | if (!per_cpu(cpu_msrs, i).controls) { |
208 | success = 0; | 162 | success = 0; |
209 | break; | 163 | break; |
@@ -247,8 +201,7 @@ static int nmi_setup(void) | |||
247 | return err; | 201 | return err; |
248 | } | 202 | } |
249 | 203 | ||
250 | /* | 204 | /* We need to serialize save and setup for HT because the subset |
251 | * We need to serialize save and setup for HT because the subset | ||
252 | * of msrs are distinct for save and setup operations | 205 | * of msrs are distinct for save and setup operations |
253 | */ | 206 | */ |
254 | 207 | ||
@@ -264,6 +217,7 @@ static int nmi_setup(void) | |||
264 | per_cpu(cpu_msrs, 0).controls, | 217 | per_cpu(cpu_msrs, 0).controls, |
265 | sizeof(struct op_msr) * model->num_controls); | 218 | sizeof(struct op_msr) * model->num_controls); |
266 | } | 219 | } |
220 | |||
267 | } | 221 | } |
268 | on_each_cpu(nmi_save_registers, NULL, 1); | 222 | on_each_cpu(nmi_save_registers, NULL, 1); |
269 | on_each_cpu(nmi_cpu_setup, NULL, 1); | 223 | on_each_cpu(nmi_cpu_setup, NULL, 1); |
@@ -271,41 +225,7 @@ static int nmi_setup(void) | |||
271 | return 0; | 225 | return 0; |
272 | } | 226 | } |
273 | 227 | ||
274 | static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) | 228 | static void nmi_restore_registers(struct op_msrs *msrs) |
275 | { | ||
276 | unsigned int si = __get_cpu_var(switch_index); | ||
277 | unsigned int const nr_ctrs = model->num_hardware_counters; | ||
278 | struct op_msr *counters = &msrs->counters[si]; | ||
279 | unsigned int i; | ||
280 | |||
281 | for (i = 0; i < nr_ctrs; ++i) { | ||
282 | int offset = i + si; | ||
283 | if (counters[offset].addr) { | ||
284 | rdmsr(counters[offset].addr, | ||
285 | counters[offset].multiplex.low, | ||
286 | counters[offset].multiplex.high); | ||
287 | } | ||
288 | } | ||
289 | } | ||
290 | |||
291 | static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) | ||
292 | { | ||
293 | unsigned int si = __get_cpu_var(switch_index); | ||
294 | unsigned int const nr_ctrs = model->num_hardware_counters; | ||
295 | struct op_msr *counters = &msrs->counters[si]; | ||
296 | unsigned int i; | ||
297 | |||
298 | for (i = 0; i < nr_ctrs; ++i) { | ||
299 | int offset = i + si; | ||
300 | if (counters[offset].addr) { | ||
301 | wrmsr(counters[offset].addr, | ||
302 | counters[offset].multiplex.low, | ||
303 | counters[offset].multiplex.high); | ||
304 | } | ||
305 | } | ||
306 | } | ||
307 | |||
308 | static void nmi_cpu_restore_registers(struct op_msrs *msrs) | ||
309 | { | 229 | { |
310 | unsigned int const nr_ctrs = model->num_counters; | 230 | unsigned int const nr_ctrs = model->num_counters; |
311 | unsigned int const nr_ctrls = model->num_controls; | 231 | unsigned int const nr_ctrls = model->num_controls; |
@@ -345,8 +265,7 @@ static void nmi_cpu_shutdown(void *dummy) | |||
345 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | 265 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
346 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); | 266 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
347 | apic_write(APIC_LVTERR, v); | 267 | apic_write(APIC_LVTERR, v); |
348 | nmi_cpu_restore_registers(msrs); | 268 | nmi_restore_registers(msrs); |
349 | __get_cpu_var(switch_index) = 0; | ||
350 | } | 269 | } |
351 | 270 | ||
352 | static void nmi_shutdown(void) | 271 | static void nmi_shutdown(void) |
@@ -409,7 +328,6 @@ static int nmi_create_files(struct super_block *sb, struct dentry *root) | |||
409 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | 328 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); |
410 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | 329 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); |
411 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | 330 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); |
412 | counter_config[i].save_count_low = 0; | ||
413 | } | 331 | } |
414 | 332 | ||
415 | return 0; | 333 | return 0; |
@@ -551,14 +469,12 @@ int __init op_nmi_init(struct oprofile_operations *ops) | |||
551 | } | 469 | } |
552 | 470 | ||
553 | /* default values, can be overwritten by model */ | 471 | /* default values, can be overwritten by model */ |
554 | __raw_get_cpu_var(switch_index) = 0; | ||
555 | ops->create_files = nmi_create_files; | 472 | ops->create_files = nmi_create_files; |
556 | ops->setup = nmi_setup; | 473 | ops->setup = nmi_setup; |
557 | ops->shutdown = nmi_shutdown; | 474 | ops->shutdown = nmi_shutdown; |
558 | ops->start = nmi_start; | 475 | ops->start = nmi_start; |
559 | ops->stop = nmi_stop; | 476 | ops->stop = nmi_stop; |
560 | ops->cpu_type = cpu_type; | 477 | ops->cpu_type = cpu_type; |
561 | ops->switch_events = nmi_switch_event; | ||
562 | 478 | ||
563 | if (model->init) | 479 | if (model->init) |
564 | ret = model->init(ops); | 480 | ret = model->init(ops); |
diff --git a/arch/x86/oprofile/op_counter.h b/arch/x86/oprofile/op_counter.h index 786d6e01cf7f..2880b15c4675 100644 --- a/arch/x86/oprofile/op_counter.h +++ b/arch/x86/oprofile/op_counter.h | |||
@@ -10,14 +10,13 @@ | |||
10 | #ifndef OP_COUNTER_H | 10 | #ifndef OP_COUNTER_H |
11 | #define OP_COUNTER_H | 11 | #define OP_COUNTER_H |
12 | 12 | ||
13 | #define OP_MAX_COUNTER 32 | 13 | #define OP_MAX_COUNTER 8 |
14 | 14 | ||
15 | /* Per-perfctr configuration as set via | 15 | /* Per-perfctr configuration as set via |
16 | * oprofilefs. | 16 | * oprofilefs. |
17 | */ | 17 | */ |
18 | struct op_counter_config { | 18 | struct op_counter_config { |
19 | unsigned long count; | 19 | unsigned long count; |
20 | unsigned long save_count_low; | ||
21 | unsigned long enabled; | 20 | unsigned long enabled; |
22 | unsigned long event; | 21 | unsigned long event; |
23 | unsigned long kernel; | 22 | unsigned long kernel; |
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index bbf2b68bcc5d..d9faf607b3a6 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/oprofile.h> | 15 | #include <linux/oprofile.h> |
16 | #include <linux/device.h> | 16 | #include <linux/device.h> |
17 | #include <linux/pci.h> | 17 | #include <linux/pci.h> |
18 | #include <linux/percpu.h> | ||
19 | 18 | ||
20 | #include <asm/ptrace.h> | 19 | #include <asm/ptrace.h> |
21 | #include <asm/msr.h> | 20 | #include <asm/msr.h> |
@@ -24,10 +23,8 @@ | |||
24 | #include "op_x86_model.h" | 23 | #include "op_x86_model.h" |
25 | #include "op_counter.h" | 24 | #include "op_counter.h" |
26 | 25 | ||
27 | #define NUM_COUNTERS 32 | 26 | #define NUM_COUNTERS 4 |
28 | #define NUM_HARDWARE_COUNTERS 4 | 27 | #define NUM_CONTROLS 4 |
29 | #define NUM_CONTROLS 32 | ||
30 | #define NUM_HARDWARE_CONTROLS 4 | ||
31 | 28 | ||
32 | #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) | 29 | #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0) |
33 | #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0) | 30 | #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0) |
@@ -51,7 +48,6 @@ | |||
51 | #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8)) | 48 | #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8)) |
52 | 49 | ||
53 | static unsigned long reset_value[NUM_COUNTERS]; | 50 | static unsigned long reset_value[NUM_COUNTERS]; |
54 | DECLARE_PER_CPU(int, switch_index); | ||
55 | 51 | ||
56 | #ifdef CONFIG_OPROFILE_IBS | 52 | #ifdef CONFIG_OPROFILE_IBS |
57 | 53 | ||
@@ -134,17 +130,15 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs) | |||
134 | int i; | 130 | int i; |
135 | 131 | ||
136 | for (i = 0; i < NUM_COUNTERS; i++) { | 132 | for (i = 0; i < NUM_COUNTERS; i++) { |
137 | int hw_counter = i % NUM_HARDWARE_COUNTERS; | 133 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
138 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + hw_counter)) | 134 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; |
139 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + hw_counter; | ||
140 | else | 135 | else |
141 | msrs->counters[i].addr = 0; | 136 | msrs->counters[i].addr = 0; |
142 | } | 137 | } |
143 | 138 | ||
144 | for (i = 0; i < NUM_CONTROLS; i++) { | 139 | for (i = 0; i < NUM_CONTROLS; i++) { |
145 | int hw_control = i % NUM_HARDWARE_CONTROLS; | 140 | if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) |
146 | if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + hw_control)) | 141 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; |
147 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + hw_control; | ||
148 | else | 142 | else |
149 | msrs->controls[i].addr = 0; | 143 | msrs->controls[i].addr = 0; |
150 | } | 144 | } |
@@ -156,16 +150,8 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs) | |||
156 | unsigned int low, high; | 150 | unsigned int low, high; |
157 | int i; | 151 | int i; |
158 | 152 | ||
159 | for (i = 0; i < NUM_HARDWARE_CONTROLS; ++i) { | ||
160 | int offset = i + __get_cpu_var(switch_index); | ||
161 | if (counter_config[offset].enabled) | ||
162 | reset_value[offset] = counter_config[offset].count; | ||
163 | else | ||
164 | reset_value[offset] = 0; | ||
165 | } | ||
166 | |||
167 | /* clear all counters */ | 153 | /* clear all counters */ |
168 | for (i = 0 ; i < NUM_HARDWARE_CONTROLS; ++i) { | 154 | for (i = 0 ; i < NUM_CONTROLS; ++i) { |
169 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) | 155 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) |
170 | continue; | 156 | continue; |
171 | CTRL_READ(low, high, msrs, i); | 157 | CTRL_READ(low, high, msrs, i); |
@@ -175,31 +161,34 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs) | |||
175 | } | 161 | } |
176 | 162 | ||
177 | /* avoid a false detection of ctr overflows in NMI handler */ | 163 | /* avoid a false detection of ctr overflows in NMI handler */ |
178 | for (i = 0; i < NUM_HARDWARE_COUNTERS; ++i) { | 164 | for (i = 0; i < NUM_COUNTERS; ++i) { |
179 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) | 165 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) |
180 | continue; | 166 | continue; |
181 | CTR_WRITE(1, msrs, i); | 167 | CTR_WRITE(1, msrs, i); |
182 | } | 168 | } |
183 | 169 | ||
184 | /* enable active counters */ | 170 | /* enable active counters */ |
185 | for (i = 0; i < NUM_HARDWARE_COUNTERS; ++i) { | 171 | for (i = 0; i < NUM_COUNTERS; ++i) { |
186 | int offset = i + __get_cpu_var(switch_index); | 172 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) { |
187 | if ((counter_config[offset].enabled) && (CTR_IS_RESERVED(msrs, i))) { | 173 | reset_value[i] = counter_config[i].count; |
188 | CTR_WRITE(counter_config[offset].count, msrs, i); | 174 | |
175 | CTR_WRITE(counter_config[i].count, msrs, i); | ||
189 | 176 | ||
190 | CTRL_READ(low, high, msrs, i); | 177 | CTRL_READ(low, high, msrs, i); |
191 | CTRL_CLEAR_LO(low); | 178 | CTRL_CLEAR_LO(low); |
192 | CTRL_CLEAR_HI(high); | 179 | CTRL_CLEAR_HI(high); |
193 | CTRL_SET_ENABLE(low); | 180 | CTRL_SET_ENABLE(low); |
194 | CTRL_SET_USR(low, counter_config[offset].user); | 181 | CTRL_SET_USR(low, counter_config[i].user); |
195 | CTRL_SET_KERN(low, counter_config[offset].kernel); | 182 | CTRL_SET_KERN(low, counter_config[i].kernel); |
196 | CTRL_SET_UM(low, counter_config[offset].unit_mask); | 183 | CTRL_SET_UM(low, counter_config[i].unit_mask); |
197 | CTRL_SET_EVENT_LOW(low, counter_config[offset].event); | 184 | CTRL_SET_EVENT_LOW(low, counter_config[i].event); |
198 | CTRL_SET_EVENT_HIGH(high, counter_config[offset].event); | 185 | CTRL_SET_EVENT_HIGH(high, counter_config[i].event); |
199 | CTRL_SET_HOST_ONLY(high, 0); | 186 | CTRL_SET_HOST_ONLY(high, 0); |
200 | CTRL_SET_GUEST_ONLY(high, 0); | 187 | CTRL_SET_GUEST_ONLY(high, 0); |
201 | 188 | ||
202 | CTRL_WRITE(low, high, msrs, i); | 189 | CTRL_WRITE(low, high, msrs, i); |
190 | } else { | ||
191 | reset_value[i] = 0; | ||
203 | } | 192 | } |
204 | } | 193 | } |
205 | } | 194 | } |
@@ -287,14 +276,13 @@ static int op_amd_check_ctrs(struct pt_regs * const regs, | |||
287 | unsigned int low, high; | 276 | unsigned int low, high; |
288 | int i; | 277 | int i; |
289 | 278 | ||
290 | for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { | 279 | for (i = 0 ; i < NUM_COUNTERS; ++i) { |
291 | int offset = i + __get_cpu_var(switch_index); | 280 | if (!reset_value[i]) |
292 | if (!reset_value[offset]) | ||
293 | continue; | 281 | continue; |
294 | CTR_READ(low, high, msrs, i); | 282 | CTR_READ(low, high, msrs, i); |
295 | if (CTR_OVERFLOWED(low)) { | 283 | if (CTR_OVERFLOWED(low)) { |
296 | oprofile_add_sample(regs, offset); | 284 | oprofile_add_sample(regs, i); |
297 | CTR_WRITE(reset_value[offset], msrs, i); | 285 | CTR_WRITE(reset_value[i], msrs, i); |
298 | } | 286 | } |
299 | } | 287 | } |
300 | 288 | ||
@@ -310,10 +298,8 @@ static void op_amd_start(struct op_msrs const * const msrs) | |||
310 | { | 298 | { |
311 | unsigned int low, high; | 299 | unsigned int low, high; |
312 | int i; | 300 | int i; |
313 | 301 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { | |
314 | for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { | 302 | if (reset_value[i]) { |
315 | int offset = i + __get_cpu_var(switch_index); | ||
316 | if (reset_value[offset]) { | ||
317 | CTRL_READ(low, high, msrs, i); | 303 | CTRL_READ(low, high, msrs, i); |
318 | CTRL_SET_ACTIVE(low); | 304 | CTRL_SET_ACTIVE(low); |
319 | CTRL_WRITE(low, high, msrs, i); | 305 | CTRL_WRITE(low, high, msrs, i); |
@@ -343,8 +329,8 @@ static void op_amd_stop(struct op_msrs const * const msrs) | |||
343 | 329 | ||
344 | /* Subtle: stop on all counters to avoid race with | 330 | /* Subtle: stop on all counters to avoid race with |
345 | * setting our pm callback */ | 331 | * setting our pm callback */ |
346 | for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { | 332 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
347 | if (!reset_value[i + per_cpu(switch_index, smp_processor_id())]) | 333 | if (!reset_value[i]) |
348 | continue; | 334 | continue; |
349 | CTRL_READ(low, high, msrs, i); | 335 | CTRL_READ(low, high, msrs, i); |
350 | CTRL_SET_INACTIVE(low); | 336 | CTRL_SET_INACTIVE(low); |
@@ -370,11 +356,11 @@ static void op_amd_shutdown(struct op_msrs const * const msrs) | |||
370 | { | 356 | { |
371 | int i; | 357 | int i; |
372 | 358 | ||
373 | for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { | 359 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
374 | if (CTR_IS_RESERVED(msrs, i)) | 360 | if (CTR_IS_RESERVED(msrs, i)) |
375 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); | 361 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
376 | } | 362 | } |
377 | for (i = 0 ; i < NUM_HARDWARE_COUNTERS ; ++i) { | 363 | for (i = 0 ; i < NUM_CONTROLS ; ++i) { |
378 | if (CTRL_IS_RESERVED(msrs, i)) | 364 | if (CTRL_IS_RESERVED(msrs, i)) |
379 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); | 365 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); |
380 | } | 366 | } |
@@ -548,8 +534,6 @@ struct op_x86_model_spec const op_amd_spec = { | |||
548 | .exit = op_amd_exit, | 534 | .exit = op_amd_exit, |
549 | .num_counters = NUM_COUNTERS, | 535 | .num_counters = NUM_COUNTERS, |
550 | .num_controls = NUM_CONTROLS, | 536 | .num_controls = NUM_CONTROLS, |
551 | .num_hardware_counters = NUM_HARDWARE_COUNTERS, | ||
552 | .num_hardware_controls = NUM_HARDWARE_CONTROLS, | ||
553 | .fill_in_addresses = &op_amd_fill_in_addresses, | 537 | .fill_in_addresses = &op_amd_fill_in_addresses, |
554 | .setup_ctrs = &op_amd_setup_ctrs, | 538 | .setup_ctrs = &op_amd_setup_ctrs, |
555 | .check_ctrs = &op_amd_check_ctrs, | 539 | .check_ctrs = &op_amd_check_ctrs, |
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c index cacba61ffbac..43ac5af338d8 100644 --- a/arch/x86/oprofile/op_model_p4.c +++ b/arch/x86/oprofile/op_model_p4.c | |||
@@ -700,8 +700,6 @@ static void p4_shutdown(struct op_msrs const * const msrs) | |||
700 | struct op_x86_model_spec const op_p4_ht2_spec = { | 700 | struct op_x86_model_spec const op_p4_ht2_spec = { |
701 | .num_counters = NUM_COUNTERS_HT2, | 701 | .num_counters = NUM_COUNTERS_HT2, |
702 | .num_controls = NUM_CONTROLS_HT2, | 702 | .num_controls = NUM_CONTROLS_HT2, |
703 | .num_hardware_counters = NUM_COUNTERS_HT2, | ||
704 | .num_hardware_controls = NUM_CONTROLS_HT2, | ||
705 | .fill_in_addresses = &p4_fill_in_addresses, | 703 | .fill_in_addresses = &p4_fill_in_addresses, |
706 | .setup_ctrs = &p4_setup_ctrs, | 704 | .setup_ctrs = &p4_setup_ctrs, |
707 | .check_ctrs = &p4_check_ctrs, | 705 | .check_ctrs = &p4_check_ctrs, |
@@ -714,8 +712,6 @@ struct op_x86_model_spec const op_p4_ht2_spec = { | |||
714 | struct op_x86_model_spec const op_p4_spec = { | 712 | struct op_x86_model_spec const op_p4_spec = { |
715 | .num_counters = NUM_COUNTERS_NON_HT, | 713 | .num_counters = NUM_COUNTERS_NON_HT, |
716 | .num_controls = NUM_CONTROLS_NON_HT, | 714 | .num_controls = NUM_CONTROLS_NON_HT, |
717 | .num_hardware_counters = NUM_COUNTERS_NON_HT, | ||
718 | .num_hardware_controls = NUM_CONTROLS_NON_HT, | ||
719 | .fill_in_addresses = &p4_fill_in_addresses, | 715 | .fill_in_addresses = &p4_fill_in_addresses, |
720 | .setup_ctrs = &p4_setup_ctrs, | 716 | .setup_ctrs = &p4_setup_ctrs, |
721 | .check_ctrs = &p4_check_ctrs, | 717 | .check_ctrs = &p4_check_ctrs, |
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c index e5811aa480eb..eff431f6c57b 100644 --- a/arch/x86/oprofile/op_model_ppro.c +++ b/arch/x86/oprofile/op_model_ppro.c | |||
@@ -183,8 +183,6 @@ static void ppro_shutdown(struct op_msrs const * const msrs) | |||
183 | struct op_x86_model_spec const op_ppro_spec = { | 183 | struct op_x86_model_spec const op_ppro_spec = { |
184 | .num_counters = NUM_COUNTERS, | 184 | .num_counters = NUM_COUNTERS, |
185 | .num_controls = NUM_CONTROLS, | 185 | .num_controls = NUM_CONTROLS, |
186 | .num_hardware_counters = NUM_COUNTERS, | ||
187 | .num_hardware_controls = NUM_CONTROLS, | ||
188 | .fill_in_addresses = &ppro_fill_in_addresses, | 186 | .fill_in_addresses = &ppro_fill_in_addresses, |
189 | .setup_ctrs = &ppro_setup_ctrs, | 187 | .setup_ctrs = &ppro_setup_ctrs, |
190 | .check_ctrs = &ppro_check_ctrs, | 188 | .check_ctrs = &ppro_check_ctrs, |
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h index e07ba1076371..05a0261ba0c3 100644 --- a/arch/x86/oprofile/op_x86_model.h +++ b/arch/x86/oprofile/op_x86_model.h | |||
@@ -19,7 +19,6 @@ struct op_saved_msr { | |||
19 | struct op_msr { | 19 | struct op_msr { |
20 | unsigned long addr; | 20 | unsigned long addr; |
21 | struct op_saved_msr saved; | 21 | struct op_saved_msr saved; |
22 | struct op_saved_msr multiplex; | ||
23 | }; | 22 | }; |
24 | 23 | ||
25 | struct op_msrs { | 24 | struct op_msrs { |
@@ -35,8 +34,6 @@ struct pt_regs; | |||
35 | struct op_x86_model_spec { | 34 | struct op_x86_model_spec { |
36 | int (*init)(struct oprofile_operations *ops); | 35 | int (*init)(struct oprofile_operations *ops); |
37 | void (*exit)(void); | 36 | void (*exit)(void); |
38 | unsigned int const num_hardware_counters; | ||
39 | unsigned int const num_hardware_controls; | ||
40 | unsigned int const num_counters; | 37 | unsigned int const num_counters; |
41 | unsigned int const num_controls; | 38 | unsigned int const num_controls; |
42 | void (*fill_in_addresses)(struct op_msrs * const msrs); | 39 | void (*fill_in_addresses)(struct op_msrs * const msrs); |