aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c193
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c193
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c253
-rw-r--r--arch/arm/mach-omap2/prcm-common.h3
-rw-r--r--arch/arm/plat-omap/include/plat/dma.h2
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h2
6 files changed, 644 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 3cc768e8bc04..ba145f7d5896 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,6 +15,7 @@
15#include <mach/irqs.h> 15#include <mach/irqs.h>
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <plat/dma.h> 17#include <plat/dma.h>
18#include <plat/serial.h>
18 19
19#include "omap_hwmod_common_data.h" 20#include "omap_hwmod_common_data.h"
20 21
@@ -71,6 +72,9 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
71}; 72};
72 73
73static struct omap_hwmod omap2420_l4_wkup_hwmod; 74static struct omap_hwmod omap2420_l4_wkup_hwmod;
75static struct omap_hwmod omap2420_uart1_hwmod;
76static struct omap_hwmod omap2420_uart2_hwmod;
77static struct omap_hwmod omap2420_uart3_hwmod;
74 78
75/* L4_CORE -> L4_WKUP interface */ 79/* L4_CORE -> L4_WKUP interface */
76static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { 80static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -79,6 +83,60 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
79 .user = OCP_USER_MPU | OCP_USER_SDMA, 83 .user = OCP_USER_MPU | OCP_USER_SDMA,
80}; 84};
81 85
86/* L4 CORE -> UART1 interface */
87static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
88 {
89 .pa_start = OMAP2_UART1_BASE,
90 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
91 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
92 },
93};
94
95static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
96 .master = &omap2420_l4_core_hwmod,
97 .slave = &omap2420_uart1_hwmod,
98 .clk = "uart1_ick",
99 .addr = omap2420_uart1_addr_space,
100 .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
101 .user = OCP_USER_MPU | OCP_USER_SDMA,
102};
103
104/* L4 CORE -> UART2 interface */
105static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
106 {
107 .pa_start = OMAP2_UART2_BASE,
108 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
109 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
110 },
111};
112
113static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
114 .master = &omap2420_l4_core_hwmod,
115 .slave = &omap2420_uart2_hwmod,
116 .clk = "uart2_ick",
117 .addr = omap2420_uart2_addr_space,
118 .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
119 .user = OCP_USER_MPU | OCP_USER_SDMA,
120};
121
122/* L4 PER -> UART3 interface */
123static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
124 {
125 .pa_start = OMAP2_UART3_BASE,
126 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
127 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
128 },
129};
130
131static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
132 .master = &omap2420_l4_core_hwmod,
133 .slave = &omap2420_uart3_hwmod,
134 .clk = "uart3_ick",
135 .addr = omap2420_uart3_addr_space,
136 .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
137 .user = OCP_USER_MPU | OCP_USER_SDMA,
138};
139
82/* Slave interfaces on the L4_CORE interconnect */ 140/* Slave interfaces on the L4_CORE interconnect */
83static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { 141static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
84 &omap2420_l3_main__l4_core, 142 &omap2420_l3_main__l4_core,
@@ -87,6 +145,9 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
87/* Master interfaces on the L4_CORE interconnect */ 145/* Master interfaces on the L4_CORE interconnect */
88static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { 146static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
89 &omap2420_l4_core__l4_wkup, 147 &omap2420_l4_core__l4_wkup,
148 &omap2_l4_core__uart1,
149 &omap2_l4_core__uart2,
150 &omap2_l4_core__uart3,
90}; 151};
91 152
92/* L4 CORE */ 153/* L4 CORE */
@@ -165,12 +226,144 @@ static struct omap_hwmod omap2420_iva_hwmod = {
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
166}; 227};
167 228
229/* UART */
230
231static struct omap_hwmod_class_sysconfig uart_sysc = {
232 .rev_offs = 0x50,
233 .sysc_offs = 0x54,
234 .syss_offs = 0x58,
235 .sysc_flags = (SYSC_HAS_SIDLEMODE |
236 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
237 SYSC_HAS_AUTOIDLE),
238 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
239 .sysc_fields = &omap_hwmod_sysc_type1,
240};
241
242static struct omap_hwmod_class uart_class = {
243 .name = "uart",
244 .sysc = &uart_sysc,
245};
246
247/* UART1 */
248
249static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
250 { .irq = INT_24XX_UART1_IRQ, },
251};
252
253static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
254 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
255 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
256};
257
258static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
259 &omap2_l4_core__uart1,
260};
261
262static struct omap_hwmod omap2420_uart1_hwmod = {
263 .name = "uart1",
264 .mpu_irqs = uart1_mpu_irqs,
265 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
266 .sdma_reqs = uart1_sdma_reqs,
267 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
268 .main_clk = "uart1_fck",
269 .prcm = {
270 .omap2 = {
271 .module_offs = CORE_MOD,
272 .prcm_reg_id = 1,
273 .module_bit = OMAP24XX_EN_UART1_SHIFT,
274 .idlest_reg_id = 1,
275 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
276 },
277 },
278 .slaves = omap2420_uart1_slaves,
279 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
280 .class = &uart_class,
281 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
282};
283
284/* UART2 */
285
286static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
287 { .irq = INT_24XX_UART2_IRQ, },
288};
289
290static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
291 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
292 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
293};
294
295static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
296 &omap2_l4_core__uart2,
297};
298
299static struct omap_hwmod omap2420_uart2_hwmod = {
300 .name = "uart2",
301 .mpu_irqs = uart2_mpu_irqs,
302 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
303 .sdma_reqs = uart2_sdma_reqs,
304 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
305 .main_clk = "uart2_fck",
306 .prcm = {
307 .omap2 = {
308 .module_offs = CORE_MOD,
309 .prcm_reg_id = 1,
310 .module_bit = OMAP24XX_EN_UART2_SHIFT,
311 .idlest_reg_id = 1,
312 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
313 },
314 },
315 .slaves = omap2420_uart2_slaves,
316 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
317 .class = &uart_class,
318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
319};
320
321/* UART3 */
322
323static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
324 { .irq = INT_24XX_UART3_IRQ, },
325};
326
327static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
328 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
329 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
330};
331
332static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
333 &omap2_l4_core__uart3,
334};
335
336static struct omap_hwmod omap2420_uart3_hwmod = {
337 .name = "uart3",
338 .mpu_irqs = uart3_mpu_irqs,
339 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
340 .sdma_reqs = uart3_sdma_reqs,
341 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
342 .main_clk = "uart3_fck",
343 .prcm = {
344 .omap2 = {
345 .module_offs = CORE_MOD,
346 .prcm_reg_id = 2,
347 .module_bit = OMAP24XX_EN_UART3_SHIFT,
348 .idlest_reg_id = 2,
349 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
350 },
351 },
352 .slaves = omap2420_uart3_slaves,
353 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
354 .class = &uart_class,
355 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
356};
357
168static __initdata struct omap_hwmod *omap2420_hwmods[] = { 358static __initdata struct omap_hwmod *omap2420_hwmods[] = {
169 &omap2420_l3_main_hwmod, 359 &omap2420_l3_main_hwmod,
170 &omap2420_l4_core_hwmod, 360 &omap2420_l4_core_hwmod,
171 &omap2420_l4_wkup_hwmod, 361 &omap2420_l4_wkup_hwmod,
172 &omap2420_mpu_hwmod, 362 &omap2420_mpu_hwmod,
173 &omap2420_iva_hwmod, 363 &omap2420_iva_hwmod,
364 &omap2420_uart1_hwmod,
365 &omap2420_uart2_hwmod,
366 &omap2420_uart3_hwmod,
174 NULL, 367 NULL,
175}; 368};
176 369
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4526628ed287..d21073d7eb74 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,6 +15,7 @@
15#include <mach/irqs.h> 15#include <mach/irqs.h>
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <plat/dma.h> 17#include <plat/dma.h>
18#include <plat/serial.h>
18 19
19#include "omap_hwmod_common_data.h" 20#include "omap_hwmod_common_data.h"
20 21
@@ -71,6 +72,9 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
71}; 72};
72 73
73static struct omap_hwmod omap2430_l4_wkup_hwmod; 74static struct omap_hwmod omap2430_l4_wkup_hwmod;
75static struct omap_hwmod omap2430_uart1_hwmod;
76static struct omap_hwmod omap2430_uart2_hwmod;
77static struct omap_hwmod omap2430_uart3_hwmod;
74 78
75/* L4_CORE -> L4_WKUP interface */ 79/* L4_CORE -> L4_WKUP interface */
76static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { 80static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -79,6 +83,60 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
79 .user = OCP_USER_MPU | OCP_USER_SDMA, 83 .user = OCP_USER_MPU | OCP_USER_SDMA,
80}; 84};
81 85
86/* L4 CORE -> UART1 interface */
87static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
88 {
89 .pa_start = OMAP2_UART1_BASE,
90 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
91 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
92 },
93};
94
95static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
96 .master = &omap2430_l4_core_hwmod,
97 .slave = &omap2430_uart1_hwmod,
98 .clk = "uart1_ick",
99 .addr = omap2430_uart1_addr_space,
100 .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
101 .user = OCP_USER_MPU | OCP_USER_SDMA,
102};
103
104/* L4 CORE -> UART2 interface */
105static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
106 {
107 .pa_start = OMAP2_UART2_BASE,
108 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
109 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
110 },
111};
112
113static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
114 .master = &omap2430_l4_core_hwmod,
115 .slave = &omap2430_uart2_hwmod,
116 .clk = "uart2_ick",
117 .addr = omap2430_uart2_addr_space,
118 .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
119 .user = OCP_USER_MPU | OCP_USER_SDMA,
120};
121
122/* L4 PER -> UART3 interface */
123static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
124 {
125 .pa_start = OMAP2_UART3_BASE,
126 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
127 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
128 },
129};
130
131static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
132 .master = &omap2430_l4_core_hwmod,
133 .slave = &omap2430_uart3_hwmod,
134 .clk = "uart3_ick",
135 .addr = omap2430_uart3_addr_space,
136 .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
137 .user = OCP_USER_MPU | OCP_USER_SDMA,
138};
139
82/* Slave interfaces on the L4_CORE interconnect */ 140/* Slave interfaces on the L4_CORE interconnect */
83static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { 141static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
84 &omap2430_l3_main__l4_core, 142 &omap2430_l3_main__l4_core,
@@ -104,6 +162,9 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
104/* Slave interfaces on the L4_WKUP interconnect */ 162/* Slave interfaces on the L4_WKUP interconnect */
105static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { 163static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
106 &omap2430_l4_core__l4_wkup, 164 &omap2430_l4_core__l4_wkup,
165 &omap2_l4_core__uart1,
166 &omap2_l4_core__uart2,
167 &omap2_l4_core__uart3,
107}; 168};
108 169
109/* Master interfaces on the L4_WKUP interconnect */ 170/* Master interfaces on the L4_WKUP interconnect */
@@ -165,12 +226,144 @@ static struct omap_hwmod omap2430_iva_hwmod = {
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
166}; 227};
167 228
229/* UART */
230
231static struct omap_hwmod_class_sysconfig uart_sysc = {
232 .rev_offs = 0x50,
233 .sysc_offs = 0x54,
234 .syss_offs = 0x58,
235 .sysc_flags = (SYSC_HAS_SIDLEMODE |
236 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
237 SYSC_HAS_AUTOIDLE),
238 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
239 .sysc_fields = &omap_hwmod_sysc_type1,
240};
241
242static struct omap_hwmod_class uart_class = {
243 .name = "uart",
244 .sysc = &uart_sysc,
245};
246
247/* UART1 */
248
249static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
250 { .irq = INT_24XX_UART1_IRQ, },
251};
252
253static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
254 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
255 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
256};
257
258static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
259 &omap2_l4_core__uart1,
260};
261
262static struct omap_hwmod omap2430_uart1_hwmod = {
263 .name = "uart1",
264 .mpu_irqs = uart1_mpu_irqs,
265 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
266 .sdma_reqs = uart1_sdma_reqs,
267 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
268 .main_clk = "uart1_fck",
269 .prcm = {
270 .omap2 = {
271 .module_offs = CORE_MOD,
272 .prcm_reg_id = 1,
273 .module_bit = OMAP24XX_EN_UART1_SHIFT,
274 .idlest_reg_id = 1,
275 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
276 },
277 },
278 .slaves = omap2430_uart1_slaves,
279 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
280 .class = &uart_class,
281 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
282};
283
284/* UART2 */
285
286static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
287 { .irq = INT_24XX_UART2_IRQ, },
288};
289
290static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
291 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
292 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
293};
294
295static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
296 &omap2_l4_core__uart2,
297};
298
299static struct omap_hwmod omap2430_uart2_hwmod = {
300 .name = "uart2",
301 .mpu_irqs = uart2_mpu_irqs,
302 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
303 .sdma_reqs = uart2_sdma_reqs,
304 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
305 .main_clk = "uart2_fck",
306 .prcm = {
307 .omap2 = {
308 .module_offs = CORE_MOD,
309 .prcm_reg_id = 1,
310 .module_bit = OMAP24XX_EN_UART2_SHIFT,
311 .idlest_reg_id = 1,
312 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
313 },
314 },
315 .slaves = omap2430_uart2_slaves,
316 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
317 .class = &uart_class,
318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
319};
320
321/* UART3 */
322
323static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
324 { .irq = INT_24XX_UART3_IRQ, },
325};
326
327static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
328 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
329 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
330};
331
332static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
333 &omap2_l4_core__uart3,
334};
335
336static struct omap_hwmod omap2430_uart3_hwmod = {
337 .name = "uart3",
338 .mpu_irqs = uart3_mpu_irqs,
339 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
340 .sdma_reqs = uart3_sdma_reqs,
341 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
342 .main_clk = "uart3_fck",
343 .prcm = {
344 .omap2 = {
345 .module_offs = CORE_MOD,
346 .prcm_reg_id = 2,
347 .module_bit = OMAP24XX_EN_UART3_SHIFT,
348 .idlest_reg_id = 2,
349 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
350 },
351 },
352 .slaves = omap2430_uart3_slaves,
353 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
354 .class = &uart_class,
355 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
356};
357
168static __initdata struct omap_hwmod *omap2430_hwmods[] = { 358static __initdata struct omap_hwmod *omap2430_hwmods[] = {
169 &omap2430_l3_main_hwmod, 359 &omap2430_l3_main_hwmod,
170 &omap2430_l4_core_hwmod, 360 &omap2430_l4_core_hwmod,
171 &omap2430_l4_wkup_hwmod, 361 &omap2430_l4_wkup_hwmod,
172 &omap2430_mpu_hwmod, 362 &omap2430_mpu_hwmod,
173 &omap2430_iva_hwmod, 363 &omap2430_iva_hwmod,
364 &omap2430_uart1_hwmod,
365 &omap2430_uart2_hwmod,
366 &omap2430_uart3_hwmod,
174 NULL, 367 NULL,
175}; 368};
176 369
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58ba5e3..5c9cb255a052 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,6 +17,7 @@
17#include <mach/irqs.h> 17#include <mach/irqs.h>
18#include <plat/cpu.h> 18#include <plat/cpu.h>
19#include <plat/dma.h> 19#include <plat/dma.h>
20#include <plat/serial.h>
20 21
21#include "omap_hwmod_common_data.h" 22#include "omap_hwmod_common_data.h"
22 23
@@ -82,6 +83,10 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
82}; 83};
83 84
84static struct omap_hwmod omap3xxx_l4_wkup_hwmod; 85static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
86static struct omap_hwmod omap3xxx_uart1_hwmod;
87static struct omap_hwmod omap3xxx_uart2_hwmod;
88static struct omap_hwmod omap3xxx_uart3_hwmod;
89static struct omap_hwmod omap3xxx_uart4_hwmod;
85 90
86/* L4_CORE -> L4_WKUP interface */ 91/* L4_CORE -> L4_WKUP interface */
87static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 92static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
@@ -90,6 +95,78 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
90 .user = OCP_USER_MPU | OCP_USER_SDMA, 95 .user = OCP_USER_MPU | OCP_USER_SDMA,
91}; 96};
92 97
98/* L4 CORE -> UART1 interface */
99static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
100 {
101 .pa_start = OMAP3_UART1_BASE,
102 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
103 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
104 },
105};
106
107static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
108 .master = &omap3xxx_l4_core_hwmod,
109 .slave = &omap3xxx_uart1_hwmod,
110 .clk = "uart1_ick",
111 .addr = omap3xxx_uart1_addr_space,
112 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
113 .user = OCP_USER_MPU | OCP_USER_SDMA,
114};
115
116/* L4 CORE -> UART2 interface */
117static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
118 {
119 .pa_start = OMAP3_UART2_BASE,
120 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
121 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
122 },
123};
124
125static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
126 .master = &omap3xxx_l4_core_hwmod,
127 .slave = &omap3xxx_uart2_hwmod,
128 .clk = "uart2_ick",
129 .addr = omap3xxx_uart2_addr_space,
130 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
131 .user = OCP_USER_MPU | OCP_USER_SDMA,
132};
133
134/* L4 PER -> UART3 interface */
135static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
136 {
137 .pa_start = OMAP3_UART3_BASE,
138 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
139 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
140 },
141};
142
143static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
144 .master = &omap3xxx_l4_per_hwmod,
145 .slave = &omap3xxx_uart3_hwmod,
146 .clk = "uart3_ick",
147 .addr = omap3xxx_uart3_addr_space,
148 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
149 .user = OCP_USER_MPU | OCP_USER_SDMA,
150};
151
152/* L4 PER -> UART4 interface */
153static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
154 {
155 .pa_start = OMAP3_UART4_BASE,
156 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
157 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
158 },
159};
160
161static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
162 .master = &omap3xxx_l4_per_hwmod,
163 .slave = &omap3xxx_uart4_hwmod,
164 .clk = "uart4_ick",
165 .addr = omap3xxx_uart4_addr_space,
166 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
167 .user = OCP_USER_MPU | OCP_USER_SDMA,
168};
169
93/* Slave interfaces on the L4_CORE interconnect */ 170/* Slave interfaces on the L4_CORE interconnect */
94static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { 171static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
95 &omap3xxx_l3_main__l4_core, 172 &omap3xxx_l3_main__l4_core,
@@ -98,6 +175,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
98/* Master interfaces on the L4_CORE interconnect */ 175/* Master interfaces on the L4_CORE interconnect */
99static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { 176static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
100 &omap3xxx_l4_core__l4_wkup, 177 &omap3xxx_l4_core__l4_wkup,
178 &omap3_l4_core__uart1,
179 &omap3_l4_core__uart2,
101}; 180};
102 181
103/* L4 CORE */ 182/* L4 CORE */
@@ -119,6 +198,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
119 198
120/* Master interfaces on the L4_PER interconnect */ 199/* Master interfaces on the L4_PER interconnect */
121static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { 200static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
201 &omap3_l4_per__uart3,
202 &omap3_l4_per__uart4,
122}; 203};
123 204
124/* L4 PER */ 205/* L4 PER */
@@ -197,6 +278,172 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
197 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
198}; 279};
199 280
281/* UART common */
282
283static struct omap_hwmod_class_sysconfig uart_sysc = {
284 .rev_offs = 0x50,
285 .sysc_offs = 0x54,
286 .syss_offs = 0x58,
287 .sysc_flags = (SYSC_HAS_SIDLEMODE |
288 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
289 SYSC_HAS_AUTOIDLE),
290 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
291 .sysc_fields = &omap_hwmod_sysc_type1,
292};
293
294static struct omap_hwmod_class uart_class = {
295 .name = "uart",
296 .sysc = &uart_sysc,
297};
298
299/* UART1 */
300
301static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
302 { .irq = INT_24XX_UART1_IRQ, },
303};
304
305static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
306 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
307 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
308};
309
310static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
311 &omap3_l4_core__uart1,
312};
313
314static struct omap_hwmod omap3xxx_uart1_hwmod = {
315 .name = "uart1",
316 .mpu_irqs = uart1_mpu_irqs,
317 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
318 .sdma_reqs = uart1_sdma_reqs,
319 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
320 .main_clk = "uart1_fck",
321 .prcm = {
322 .omap2 = {
323 .module_offs = CORE_MOD,
324 .prcm_reg_id = 1,
325 .module_bit = OMAP3430_EN_UART1_SHIFT,
326 .idlest_reg_id = 1,
327 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
328 },
329 },
330 .slaves = omap3xxx_uart1_slaves,
331 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
332 .class = &uart_class,
333 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
334};
335
336/* UART2 */
337
338static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
339 { .irq = INT_24XX_UART2_IRQ, },
340};
341
342static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
343 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
344 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
345};
346
347static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
348 &omap3_l4_core__uart2,
349};
350
351static struct omap_hwmod omap3xxx_uart2_hwmod = {
352 .name = "uart2",
353 .mpu_irqs = uart2_mpu_irqs,
354 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
355 .sdma_reqs = uart2_sdma_reqs,
356 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
357 .main_clk = "uart2_fck",
358 .prcm = {
359 .omap2 = {
360 .module_offs = CORE_MOD,
361 .prcm_reg_id = 1,
362 .module_bit = OMAP3430_EN_UART2_SHIFT,
363 .idlest_reg_id = 1,
364 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
365 },
366 },
367 .slaves = omap3xxx_uart2_slaves,
368 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
369 .class = &uart_class,
370 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
371};
372
373/* UART3 */
374
375static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
376 { .irq = INT_24XX_UART3_IRQ, },
377};
378
379static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
380 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
381 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
382};
383
384static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
385 &omap3_l4_per__uart3,
386};
387
388static struct omap_hwmod omap3xxx_uart3_hwmod = {
389 .name = "uart3",
390 .mpu_irqs = uart3_mpu_irqs,
391 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
392 .sdma_reqs = uart3_sdma_reqs,
393 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
394 .main_clk = "uart3_fck",
395 .prcm = {
396 .omap2 = {
397 .module_offs = OMAP3430_PER_MOD,
398 .prcm_reg_id = 1,
399 .module_bit = OMAP3430_EN_UART3_SHIFT,
400 .idlest_reg_id = 1,
401 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
402 },
403 },
404 .slaves = omap3xxx_uart3_slaves,
405 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
406 .class = &uart_class,
407 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
408};
409
410/* UART4 */
411
412static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
413 { .irq = INT_36XX_UART4_IRQ, },
414};
415
416static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
417 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
418 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
419};
420
421static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
422 &omap3_l4_per__uart4,
423};
424
425static struct omap_hwmod omap3xxx_uart4_hwmod = {
426 .name = "uart4",
427 .mpu_irqs = uart4_mpu_irqs,
428 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
429 .sdma_reqs = uart4_sdma_reqs,
430 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
431 .main_clk = "uart4_fck",
432 .prcm = {
433 .omap2 = {
434 .module_offs = OMAP3430_PER_MOD,
435 .prcm_reg_id = 1,
436 .module_bit = OMAP3630_EN_UART4_SHIFT,
437 .idlest_reg_id = 1,
438 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
439 },
440 },
441 .slaves = omap3xxx_uart4_slaves,
442 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
443 .class = &uart_class,
444 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
445};
446
200static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 447static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
201 &omap3xxx_l3_main_hwmod, 448 &omap3xxx_l3_main_hwmod,
202 &omap3xxx_l4_core_hwmod, 449 &omap3xxx_l4_core_hwmod,
@@ -204,6 +451,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
204 &omap3xxx_l4_wkup_hwmod, 451 &omap3xxx_l4_wkup_hwmod,
205 &omap3xxx_mpu_hwmod, 452 &omap3xxx_mpu_hwmod,
206 &omap3xxx_iva_hwmod, 453 &omap3xxx_iva_hwmod,
454 &omap3xxx_uart1_hwmod,
455 &omap3xxx_uart2_hwmod,
456 &omap3xxx_uart3_hwmod,
457 &omap3xxx_uart4_hwmod,
207 NULL, 458 NULL,
208}; 459};
209 460
@@ -211,5 +462,3 @@ int __init omap3xxx_hwmod_init(void)
211{ 462{
212 return omap_hwmod_init(omap3xxx_hwmods); 463 return omap_hwmod_init(omap3xxx_hwmods);
213} 464}
214
215
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 995b7edbf18d..86edcf9ada7c 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -382,6 +382,9 @@
382#define OMAP3430_EN_MPU_SHIFT 1 382#define OMAP3430_EN_MPU_SHIFT 1
383 383
384/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 384/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
385
386#define OMAP3630_EN_UART4_MASK (1 << 18)
387#define OMAP3630_EN_UART4_SHIFT 18
385#define OMAP3430_EN_GPIO6_MASK (1 << 17) 388#define OMAP3430_EN_GPIO6_MASK (1 << 17)
386#define OMAP3430_EN_GPIO6_SHIFT 17 389#define OMAP3430_EN_GPIO6_SHIFT 17
387#define OMAP3430_EN_GPIO5_MASK (1 << 16) 390#define OMAP3430_EN_GPIO5_MASK (1 << 16)
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index af3a03941add..098f154f5d41 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -319,6 +319,8 @@
319#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ 319#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
320#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ 320#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
321 321
322#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
323#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */
322/*----------------------------------------------------------------------------*/ 324/*----------------------------------------------------------------------------*/
323 325
324#define OMAP1_DMA_TOUT_IRQ (1 << 0) 326#define OMAP1_DMA_TOUT_IRQ (1 << 0)
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index c01d9f08a198..65e20a686713 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -345,6 +345,8 @@
345#define INT_34XX_MMC3_IRQ 94 345#define INT_34XX_MMC3_IRQ 94
346#define INT_34XX_GPT12_IRQ 95 346#define INT_34XX_GPT12_IRQ 95
347 347
348#define INT_36XX_UART4_IRQ 80
349
348#define INT_35XX_HECC0_IRQ 24 350#define INT_35XX_HECC0_IRQ 24
349#define INT_35XX_HECC1_IRQ 28 351#define INT_35XX_HECC1_IRQ 28
350#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67 352#define INT_35XX_EMAC_C0_RXTHRESH_IRQ 67
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-04 22:24:02 -0500