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-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/prima2-cb.dts416
-rw-r--r--arch/arm/mach-prima2/Makefile5
-rw-r--r--arch/arm/mach-prima2/Makefile.boot3
-rw-r--r--arch/arm/mach-prima2/clock.c509
-rw-r--r--arch/arm/mach-prima2/common.h20
-rw-r--r--arch/arm/mach-prima2/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-prima2/include/mach/debug-macro.S29
-rw-r--r--arch/arm/mach-prima2/include/mach/entry-macro.S29
-rw-r--r--arch/arm/mach-prima2/include/mach/hardware.h15
-rw-r--r--arch/arm/mach-prima2/include/mach/io.h16
-rw-r--r--arch/arm/mach-prima2/include/mach/irqs.h17
-rw-r--r--arch/arm/mach-prima2/include/mach/map.h16
-rw-r--r--arch/arm/mach-prima2/include/mach/memory.h21
-rw-r--r--arch/arm/mach-prima2/include/mach/system.h29
-rw-r--r--arch/arm/mach-prima2/include/mach/timex.h14
-rw-r--r--arch/arm/mach-prima2/include/mach/uart.h23
-rw-r--r--arch/arm/mach-prima2/include/mach/uncompress.h40
-rw-r--r--arch/arm/mach-prima2/include/mach/vmalloc.h16
-rw-r--r--arch/arm/mach-prima2/irq.c71
-rw-r--r--arch/arm/mach-prima2/prima2.c40
-rw-r--r--arch/arm/mach-prima2/rstc.c69
-rw-r--r--arch/arm/mach-prima2/timer.c217
-rw-r--r--arch/arm/mm/Kconfig2
25 files changed, 1646 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9adc278a22ab..aa6c91d0d794 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -879,6 +879,20 @@ config ARCH_VT8500
879 select HAVE_PWM 879 select HAVE_PWM
880 help 880 help
881 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip. 881 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
882
883config ARCH_PRIMA2
884 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
885 select CPU_V7
886 select GENERIC_TIME
887 select NO_IOPORT
888 select GENERIC_CLOCKEVENTS
889 select CLKDEV_LOOKUP
890 select GENERIC_IRQ_CHIP
891 select USE_OF
892 select ZONE_DMA
893 help
894 Support for CSR SiRFSoC ARM Cortex A9 Platform
895
882endchoice 896endchoice
883 897
884# 898#
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f5b2b390c8f2..1d693d06257e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -169,6 +169,7 @@ machine-$(CONFIG_ARCH_OMAP3) := omap2
169machine-$(CONFIG_ARCH_OMAP4) := omap2 169machine-$(CONFIG_ARCH_OMAP4) := omap2
170machine-$(CONFIG_ARCH_ORION5X) := orion5x 170machine-$(CONFIG_ARCH_ORION5X) := orion5x
171machine-$(CONFIG_ARCH_PNX4008) := pnx4008 171machine-$(CONFIG_ARCH_PNX4008) := pnx4008
172machine-$(CONFIG_ARCH_PRIMA2) := prima2
172machine-$(CONFIG_ARCH_PXA) := pxa 173machine-$(CONFIG_ARCH_PXA) := pxa
173machine-$(CONFIG_ARCH_REALVIEW) := realview 174machine-$(CONFIG_ARCH_REALVIEW) := realview
174machine-$(CONFIG_ARCH_RPC) := rpc 175machine-$(CONFIG_ARCH_RPC) := rpc
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
new file mode 100644
index 000000000000..6fecc88065b2
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-cb.dts
@@ -0,0 +1,416 @@
1/dts-v1/;
2/ {
3 model = "SiRF Prima2 eVB";
4 compatible = "sirf,prima2-cb", "sirf,prima2";
5 #address-cells = <1>;
6 #size-cells = <1>;
7 interrupt-parent = <&intc>;
8
9 memory {
10 reg = <0x00000000 0x20000000>;
11 };
12
13 chosen {
14 bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
15 linux,stdout-path = &uart1;
16 };
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 reg = <0x0>;
24 d-cache-line-size = <32>;
25 i-cache-line-size = <32>;
26 d-cache-size = <32768>;
27 i-cache-size = <32768>;
28 /* from bootloader */
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
34
35 axi {
36 compatible = "simple-bus";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0x40000000 0x40000000 0x80000000>;
40
41 l2-cache-controller@80040000 {
42 compatible = "arm,pl310-cache";
43 reg = <0x80040000 0x1000>;
44 interrupts = <59>;
45 };
46
47 intc: interrupt-controller@80020000 {
48 #interrupt-cells = <1>;
49 interrupt-controller;
50 compatible = "sirf,prima2-intc";
51 reg = <0x80020000 0x1000>;
52 };
53
54 sys-iobg {
55 compatible = "simple-bus";
56 #address-cells = <1>;
57 #size-cells = <1>;
58 ranges = <0x88000000 0x88000000 0x40000>;
59
60 clock-controller@88000000 {
61 compatible = "sirf,prima2-clkc";
62 reg = <0x88000000 0x1000>;
63 interrupts = <3>;
64 };
65
66 reset-controller@88010000 {
67 compatible = "sirf,prima2-rstc";
68 reg = <0x88010000 0x1000>;
69 };
70 };
71
72 mem-iobg {
73 compatible = "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges = <0x90000000 0x90000000 0x10000>;
77
78 memory-controller@90000000 {
79 compatible = "sirf,prima2-memc";
80 reg = <0x90000000 0x10000>;
81 interrupts = <27>;
82 };
83 };
84
85 disp-iobg {
86 compatible = "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges = <0x90010000 0x90010000 0x30000>;
90
91 display@90010000 {
92 compatible = "sirf,prima2-lcd";
93 reg = <0x90010000 0x20000>;
94 interrupts = <30>;
95 };
96
97 vpp@90020000 {
98 compatible = "sirf,prima2-vpp";
99 reg = <0x90020000 0x10000>;
100 interrupts = <31>;
101 };
102 };
103
104 graphics-iobg {
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 ranges = <0x98000000 0x98000000 0x8000000>;
109
110 graphics@98000000 {
111 compatible = "powervr,sgx531";
112 reg = <0x98000000 0x8000000>;
113 interrupts = <6>;
114 };
115 };
116
117 multimedia-iobg {
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
121 ranges = <0xa0000000 0xa0000000 0x8000000>;
122
123 multimedia@a0000000 {
124 compatible = "sirf,prima2-video-codec";
125 reg = <0xa0000000 0x8000000>;
126 interrupts = <5>;
127 };
128 };
129
130 dsp-iobg {
131 compatible = "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges = <0xa8000000 0xa8000000 0x2000000>;
135
136 dspif@a8000000 {
137 compatible = "sirf,prima2-dspif";
138 reg = <0xa8000000 0x10000>;
139 interrupts = <9>;
140 };
141
142 gps@a8010000 {
143 compatible = "sirf,prima2-gps";
144 reg = <0xa8010000 0x10000>;
145 interrupts = <7>;
146 };
147
148 dsp@a9000000 {
149 compatible = "sirf,prima2-dsp";
150 reg = <0xa9000000 0x1000000>;
151 interrupts = <8>;
152 };
153 };
154
155 peri-iobg {
156 compatible = "simple-bus";
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges = <0xb0000000 0xb0000000 0x180000>;
160
161 timer@b0020000 {
162 compatible = "sirf,prima2-tick";
163 reg = <0xb0020000 0x1000>;
164 interrupts = <0>;
165 };
166
167 nand@b0030000 {
168 compatible = "sirf,prima2-nand";
169 reg = <0xb0030000 0x10000>;
170 interrupts = <41>;
171 };
172
173 audio@b0040000 {
174 compatible = "sirf,prima2-audio";
175 reg = <0xb0040000 0x10000>;
176 interrupts = <35>;
177 };
178
179 uart0: uart@b0050000 {
180 cell-index = <0>;
181 compatible = "sirf,prima2-uart";
182 reg = <0xb0050000 0x10000>;
183 interrupts = <17>;
184 };
185
186 uart1: uart@b0060000 {
187 cell-index = <1>;
188 compatible = "sirf,prima2-uart";
189 reg = <0xb0060000 0x10000>;
190 interrupts = <18>;
191 };
192
193 uart2: uart@b0070000 {
194 cell-index = <2>;
195 compatible = "sirf,prima2-uart";
196 reg = <0xb0070000 0x10000>;
197 interrupts = <19>;
198 };
199
200 usp0: usp@b0080000 {
201 cell-index = <0>;
202 compatible = "sirf,prima2-usp";
203 reg = <0xb0080000 0x10000>;
204 interrupts = <20>;
205 };
206
207 usp1: usp@b0090000 {
208 cell-index = <1>;
209 compatible = "sirf,prima2-usp";
210 reg = <0xb0090000 0x10000>;
211 interrupts = <21>;
212 };
213
214 usp2: usp@b00a0000 {
215 cell-index = <2>;
216 compatible = "sirf,prima2-usp";
217 reg = <0xb00a0000 0x10000>;
218 interrupts = <22>;
219 };
220
221 dmac0: dma-controller@b00b0000 {
222 cell-index = <0>;
223 compatible = "sirf,prima2-dmac";
224 reg = <0xb00b0000 0x10000>;
225 interrupts = <12>;
226 };
227
228 dmac1: dma-controller@b0160000 {
229 cell-index = <1>;
230 compatible = "sirf,prima2-dmac";
231 reg = <0xb0160000 0x10000>;
232 interrupts = <13>;
233 };
234
235 vip@b00C0000 {
236 compatible = "sirf,prima2-vip";
237 reg = <0xb00C0000 0x10000>;
238 };
239
240 spi0: spi@b00d0000 {
241 cell-index = <0>;
242 compatible = "sirf,prima2-spi";
243 reg = <0xb00d0000 0x10000>;
244 interrupts = <15>;
245 };
246
247 spi1: spi@b0170000 {
248 cell-index = <1>;
249 compatible = "sirf,prima2-spi";
250 reg = <0xb0170000 0x10000>;
251 interrupts = <16>;
252 };
253
254 i2c0: i2c@b00e0000 {
255 cell-index = <0>;
256 compatible = "sirf,prima2-i2c";
257 reg = <0xb00e0000 0x10000>;
258 interrupts = <24>;
259 };
260
261 i2c1: i2c@b00f0000 {
262 cell-index = <1>;
263 compatible = "sirf,prima2-i2c";
264 reg = <0xb00f0000 0x10000>;
265 interrupts = <25>;
266 };
267
268 tsc@b0110000 {
269 compatible = "sirf,prima2-tsc";
270 reg = <0xb0110000 0x10000>;
271 interrupts = <33>;
272 };
273
274 gpio: gpio-controller@b0120000 {
275 #gpio-cells = <2>;
276 #interrupt-cells = <2>;
277 compatible = "sirf,prima2-gpio";
278 reg = <0xb0120000 0x10000>;
279 gpio-controller;
280 interrupt-controller;
281 };
282
283 pwm@b0130000 {
284 compatible = "sirf,prima2-pwm";
285 reg = <0xb0130000 0x10000>;
286 };
287
288 efusesys@b0140000 {
289 compatible = "sirf,prima2-efuse";
290 reg = <0xb0140000 0x10000>;
291 };
292
293 pulsec@b0150000 {
294 compatible = "sirf,prima2-pulsec";
295 reg = <0xb0150000 0x10000>;
296 interrupts = <48>;
297 };
298
299 pci-iobg {
300 compatible = "sirf,prima2-pciiobg", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges = <0x56000000 0x56000000 0x1b00000>;
304
305 sd0: sdhci@56000000 {
306 cell-index = <0>;
307 compatible = "sirf,prima2-sdhc";
308 reg = <0x56000000 0x100000>;
309 interrupts = <38>;
310 };
311
312 sd1: sdhci@56100000 {
313 cell-index = <1>;
314 compatible = "sirf,prima2-sdhc";
315 reg = <0x56100000 0x100000>;
316 interrupts = <38>;
317 };
318
319 sd2: sdhci@56200000 {
320 cell-index = <2>;
321 compatible = "sirf,prima2-sdhc";
322 reg = <0x56200000 0x100000>;
323 interrupts = <23>;
324 };
325
326 sd3: sdhci@56300000 {
327 cell-index = <3>;
328 compatible = "sirf,prima2-sdhc";
329 reg = <0x56300000 0x100000>;
330 interrupts = <23>;
331 };
332
333 sd4: sdhci@56400000 {
334 cell-index = <4>;
335 compatible = "sirf,prima2-sdhc";
336 reg = <0x56400000 0x100000>;
337 interrupts = <39>;
338 };
339
340 sd5: sdhci@56500000 {
341 cell-index = <5>;
342 compatible = "sirf,prima2-sdhc";
343 reg = <0x56500000 0x100000>;
344 interrupts = <39>;
345 };
346
347 pci-copy@57900000 {
348 compatible = "sirf,prima2-pcicp";
349 reg = <0x57900000 0x100000>;
350 interrupts = <40>;
351 };
352
353 rom-interface@57a00000 {
354 compatible = "sirf,prima2-romif";
355 reg = <0x57a00000 0x100000>;
356 };
357 };
358 };
359
360 rtc-iobg {
361 compatible = "sirf,prima2-rtciobg", "simple-bus";
362 #address-cells = <1>;
363 #size-cells = <1>;
364 reg = <0x80030000 0x10000>;
365
366 gpsrtc@1000 {
367 compatible = "sirf,prima2-gpsrtc";
368 reg = <0x1000 0x1000>;
369 interrupts = <55 56 57>;
370 };
371
372 sysrtc@2000 {
373 compatible = "sirf,prima2-sysrtc";
374 reg = <0x2000 0x1000>;
375 interrupts = <52 53 54>;
376 };
377
378 pwrc@3000 {
379 compatible = "sirf,prima2-pwrc";
380 reg = <0x3000 0x1000>;
381 interrupts = <32>;
382 };
383 };
384
385 uus-iobg {
386 compatible = "simple-bus";
387 #address-cells = <1>;
388 #size-cells = <1>;
389 ranges = <0xb8000000 0xb8000000 0x40000>;
390
391 usb0: usb@b00e0000 {
392 compatible = "chipidea,ci13611a-prima2";
393 reg = <0xb8000000 0x10000>;
394 interrupts = <10>;
395 };
396
397 usb1: usb@b00f0000 {
398 compatible = "chipidea,ci13611a-prima2";
399 reg = <0xb8010000 0x10000>;
400 interrupts = <11>;
401 };
402
403 sata@b00f0000 {
404 compatible = "synopsys,dwc-ahsata";
405 reg = <0xb8020000 0x10000>;
406 interrupts = <37>;
407 };
408
409 security@b00f0000 {
410 compatible = "sirf,prima2-security";
411 reg = <0xb8030000 0x10000>;
412 interrupts = <42>;
413 };
414 };
415 };
416};
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
new file mode 100644
index 000000000000..d44f7aedda87
--- /dev/null
+++ b/arch/arm/mach-prima2/Makefile
@@ -0,0 +1,5 @@
1obj-y := timer.o
2obj-y += irq.o
3obj-y += clock.o
4obj-y += rstc.o
5obj-y += prima2.o
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot
new file mode 100644
index 000000000000..d023db3ae4ff
--- /dev/null
+++ b/arch/arm/mach-prima2/Makefile.boot
@@ -0,0 +1,3 @@
1zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
new file mode 100644
index 000000000000..f9a2aaf63f71
--- /dev/null
+++ b/arch/arm/mach-prima2/clock.c
@@ -0,0 +1,509 @@
1/*
2 * Clock tree for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/bitops.h>
11#include <linux/err.h>
12#include <linux/errno.h>
13#include <linux/io.h>
14#include <linux/clkdev.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <asm/mach/map.h>
20#include <mach/map.h>
21
22#define SIRFSOC_CLKC_CLK_EN0 0x0000
23#define SIRFSOC_CLKC_CLK_EN1 0x0004
24#define SIRFSOC_CLKC_REF_CFG 0x0014
25#define SIRFSOC_CLKC_CPU_CFG 0x0018
26#define SIRFSOC_CLKC_MEM_CFG 0x001c
27#define SIRFSOC_CLKC_SYS_CFG 0x0020
28#define SIRFSOC_CLKC_IO_CFG 0x0024
29#define SIRFSOC_CLKC_DSP_CFG 0x0028
30#define SIRFSOC_CLKC_GFX_CFG 0x002c
31#define SIRFSOC_CLKC_MM_CFG 0x0030
32#define SIRFSOC_LKC_LCD_CFG 0x0034
33#define SIRFSOC_CLKC_MMC_CFG 0x0038
34#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
35#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
36#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
37#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
38#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
39#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
40#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
41#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
42#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
43
44#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000)
45
46#define KHZ 1000
47#define MHZ (KHZ * KHZ)
48
49struct clk_ops {
50 unsigned long (*get_rate)(struct clk *clk);
51 long (*round_rate)(struct clk *clk, unsigned long rate);
52 int (*set_rate)(struct clk *clk, unsigned long rate);
53 int (*enable)(struct clk *clk);
54 int (*disable)(struct clk *clk);
55 struct clk *(*get_parent)(struct clk *clk);
56 int (*set_parent)(struct clk *clk, struct clk *parent);
57};
58
59struct clk {
60 struct clk *parent; /* parent clk */
61 unsigned long rate; /* clock rate in Hz */
62 signed char usage; /* clock enable count */
63 signed char enable_bit; /* enable bit: 0 ~ 63 */
64 unsigned short regofs; /* register offset */
65 struct clk_ops *ops; /* clock operation */
66};
67
68static DEFINE_SPINLOCK(clocks_lock);
69
70static inline unsigned long clkc_readl(unsigned reg)
71{
72 return readl(SIRFSOC_CLOCK_VA_BASE + reg);
73}
74
75static inline void clkc_writel(u32 val, unsigned reg)
76{
77 writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
78}
79
80/*
81 * osc_rtc - real time oscillator - 32.768KHz
82 * osc_sys - high speed oscillator - 26MHz
83 */
84
85static struct clk clk_rtc = {
86 .rate = 32768,
87};
88
89static struct clk clk_osc = {
90 .rate = 26 * MHZ,
91};
92
93/*
94 * std pll
95 */
96static unsigned long std_pll_get_rate(struct clk *clk)
97{
98 unsigned long fin = clk_get_rate(clk->parent);
99 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
100 SIRFSOC_CLKC_PLL1_CFG0;
101
102 if (clkc_readl(regcfg2) & BIT(2)) {
103 /* pll bypass mode */
104 clk->rate = fin;
105 } else {
106 /* fout = fin * nf / nr / od */
107 u32 cfg0 = clkc_readl(clk->regofs);
108 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
109 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
110 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
111 WARN_ON(fin % MHZ);
112 clk->rate = fin / MHZ * nf / nr / od * MHZ;
113 }
114
115 return clk->rate;
116}
117
118static int std_pll_set_rate(struct clk *clk, unsigned long rate)
119{
120 unsigned long fin, nf, nr, od, reg;
121
122 /*
123 * fout = fin * nf / (nr * od);
124 * set od = 1, nr = fin/MHz, so fout = nf * MHz
125 */
126
127 nf = rate / MHZ;
128 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
129 return -EINVAL;
130
131 fin = clk_get_rate(clk->parent);
132 BUG_ON(fin < MHZ);
133
134 nr = fin / MHZ;
135 BUG_ON((fin % MHZ) || nr > BIT(6));
136
137 od = 1;
138
139 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
140 clkc_writel(reg, clk->regofs);
141
142 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
143 clkc_writel((nf >> 1) - 1, reg);
144
145 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
146 while (!(clkc_readl(reg) & BIT(6)))
147 cpu_relax();
148
149 clk->rate = 0; /* set to zero will force recalculation */
150 return 0;
151}
152
153static struct clk_ops std_pll_ops = {
154 .get_rate = std_pll_get_rate,
155 .set_rate = std_pll_set_rate,
156};
157
158static struct clk clk_pll1 = {
159 .parent = &clk_osc,
160 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
161 .ops = &std_pll_ops,
162};
163
164static struct clk clk_pll2 = {
165 .parent = &clk_osc,
166 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
167 .ops = &std_pll_ops,
168};
169
170static struct clk clk_pll3 = {
171 .parent = &clk_osc,
172 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
173 .ops = &std_pll_ops,
174};
175
176/*
177 * clock domains - cpu, mem, sys/io
178 */
179
180static struct clk clk_mem;
181
182static struct clk *dmn_get_parent(struct clk *clk)
183{
184 struct clk *clks[] = {
185 &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
186 };
187 u32 cfg = clkc_readl(clk->regofs);
188 WARN_ON((cfg & (BIT(3) - 1)) > 4);
189 return clks[cfg & (BIT(3) - 1)];
190}
191
192static int dmn_set_parent(struct clk *clk, struct clk *parent)
193{
194 const struct clk *clks[] = {
195 &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
196 };
197 u32 cfg = clkc_readl(clk->regofs);
198 int i;
199 for (i = 0; i < ARRAY_SIZE(clks); i++) {
200 if (clks[i] == parent) {
201 cfg &= ~(BIT(3) - 1);
202 clkc_writel(cfg | i, clk->regofs);
203 /* BIT(3) - switching status: 1 - busy, 0 - done */
204 while (clkc_readl(clk->regofs) & BIT(3))
205 cpu_relax();
206 return 0;
207 }
208 }
209 return -EINVAL;
210}
211
212static unsigned long dmn_get_rate(struct clk *clk)
213{
214 unsigned long fin = clk_get_rate(clk->parent);
215 u32 cfg = clkc_readl(clk->regofs);
216 if (cfg & BIT(24)) {
217 /* fcd bypass mode */
218 clk->rate = fin;
219 } else {
220 /*
221 * wait count: bit[19:16], hold count: bit[23:20]
222 */
223 u32 wait = (cfg >> 16) & (BIT(4) - 1);
224 u32 hold = (cfg >> 20) & (BIT(4) - 1);
225
226 clk->rate = fin / (wait + hold + 2);
227 }
228
229 return clk->rate;
230}
231
232static int dmn_set_rate(struct clk *clk, unsigned long rate)
233{
234 unsigned long fin;
235 unsigned ratio, wait, hold, reg;
236 unsigned bits = (clk == &clk_mem) ? 3 : 4;
237
238 fin = clk_get_rate(clk->parent);
239 ratio = fin / rate;
240
241 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
242 return -EINVAL;
243
244 WARN_ON(fin % rate);
245
246 wait = (ratio >> 1) - 1;
247 hold = ratio - wait - 2;
248
249 reg = clkc_readl(clk->regofs);
250 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
251 reg |= (wait << 16) | (hold << 20) | BIT(25);
252 clkc_writel(reg, clk->regofs);
253
254 /* waiting FCD been effective */
255 while (clkc_readl(clk->regofs) & BIT(25))
256 cpu_relax();
257
258 clk->rate = 0; /* set to zero will force recalculation */
259
260 return 0;
261}
262
263/*
264 * cpu clock has no FCD register in Prima2, can only change pll
265 */
266static int cpu_set_rate(struct clk *clk, unsigned long rate)
267{
268 int ret1, ret2;
269 struct clk *cur_parent, *tmp_parent;
270
271 cur_parent = dmn_get_parent(clk);
272 BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
273
274 /* switch to tmp pll before setting parent clock's rate */
275 tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
276 ret1 = dmn_set_parent(clk, tmp_parent);
277 BUG_ON(ret1);
278
279 ret2 = clk_set_rate(cur_parent, rate);
280
281 ret1 = dmn_set_parent(clk, cur_parent);
282
283 clk->rate = 0; /* set to zero will force recalculation */
284
285 return ret2 ? ret2 : ret1;
286}
287
288static struct clk_ops cpu_ops = {
289 .get_parent = dmn_get_parent,
290 .set_parent = dmn_set_parent,
291 .set_rate = cpu_set_rate,
292};
293
294static struct clk clk_cpu = {
295 .parent = &clk_pll1,
296 .regofs = SIRFSOC_CLKC_CPU_CFG,
297 .ops = &cpu_ops,
298};
299
300
301static struct clk_ops msi_ops = {
302 .set_rate = dmn_set_rate,
303 .get_rate = dmn_get_rate,
304 .set_parent = dmn_set_parent,
305 .get_parent = dmn_get_parent,
306};
307
308static struct clk clk_mem = {
309 .parent = &clk_pll2,
310 .regofs = SIRFSOC_CLKC_MEM_CFG,
311 .ops = &msi_ops,
312};
313
314static struct clk clk_sys = {
315 .parent = &clk_pll3,
316 .regofs = SIRFSOC_CLKC_SYS_CFG,
317 .ops = &msi_ops,
318};
319
320static struct clk clk_io = {
321 .parent = &clk_pll3,
322 .regofs = SIRFSOC_CLKC_IO_CFG,
323 .ops = &msi_ops,
324};
325
326/*
327 * on-chip clock sets
328 */
329static struct clk_lookup onchip_clks[] = {
330 {
331 .dev_id = "rtc",
332 .clk = &clk_rtc,
333 }, {
334 .dev_id = "osc",
335 .clk = &clk_osc,
336 }, {
337 .dev_id = "pll1",
338 .clk = &clk_pll1,
339 }, {
340 .dev_id = "pll2",
341 .clk = &clk_pll2,
342 }, {
343 .dev_id = "pll3",
344 .clk = &clk_pll3,
345 }, {
346 .dev_id = "cpu",
347 .clk = &clk_cpu,
348 }, {
349 .dev_id = "mem",
350 .clk = &clk_mem,
351 }, {
352 .dev_id = "sys",
353 .clk = &clk_sys,
354 }, {
355 .dev_id = "io",
356 .clk = &clk_io,
357 },
358};
359
360int clk_enable(struct clk *clk)
361{
362 unsigned long flags;
363
364 if (unlikely(IS_ERR_OR_NULL(clk)))
365 return -EINVAL;
366
367 if (clk->parent)
368 clk_enable(clk->parent);
369
370 spin_lock_irqsave(&clocks_lock, flags);
371 if (!clk->usage++ && clk->ops && clk->ops->enable)
372 clk->ops->enable(clk);
373 spin_unlock_irqrestore(&clocks_lock, flags);
374 return 0;
375}
376EXPORT_SYMBOL(clk_enable);
377
378void clk_disable(struct clk *clk)
379{
380 unsigned long flags;
381
382 if (unlikely(IS_ERR_OR_NULL(clk)))
383 return;
384
385 WARN_ON(!clk->usage);
386
387 spin_lock_irqsave(&clocks_lock, flags);
388 if (--clk->usage == 0 && clk->ops && clk->ops->disable)
389 clk->ops->disable(clk);
390 spin_unlock_irqrestore(&clocks_lock, flags);
391
392 if (clk->parent)
393 clk_disable(clk->parent);
394}
395EXPORT_SYMBOL(clk_disable);
396
397unsigned long clk_get_rate(struct clk *clk)
398{
399 if (unlikely(IS_ERR_OR_NULL(clk)))
400 return 0;
401
402 if (clk->rate)
403 return clk->rate;
404
405 if (clk->ops && clk->ops->get_rate)
406 return clk->ops->get_rate(clk);
407
408 return clk_get_rate(clk->parent);
409}
410EXPORT_SYMBOL(clk_get_rate);
411
412long clk_round_rate(struct clk *clk, unsigned long rate)
413{
414 if (unlikely(IS_ERR_OR_NULL(clk)))
415 return 0;
416
417 if (clk->ops && clk->ops->round_rate)
418 return clk->ops->round_rate(clk, rate);
419
420 return 0;
421}
422EXPORT_SYMBOL(clk_round_rate);
423
424int clk_set_rate(struct clk *clk, unsigned long rate)
425{
426 if (unlikely(IS_ERR_OR_NULL(clk)))
427 return -EINVAL;
428
429 if (!clk->ops || !clk->ops->set_rate)
430 return -EINVAL;
431
432 return clk->ops->set_rate(clk, rate);
433}
434EXPORT_SYMBOL(clk_set_rate);
435
436int clk_set_parent(struct clk *clk, struct clk *parent)
437{
438 int ret;
439 unsigned long flags;
440
441 if (unlikely(IS_ERR_OR_NULL(clk)))
442 return -EINVAL;
443
444 if (!clk->ops || !clk->ops->set_parent)
445 return -EINVAL;
446
447 spin_lock_irqsave(&clocks_lock, flags);
448 ret = clk->ops->set_parent(clk, parent);
449 if (!ret) {
450 parent->usage += clk->usage;
451 clk->parent->usage -= clk->usage;
452 BUG_ON(clk->parent->usage < 0);
453 clk->parent = parent;
454 }
455 spin_unlock_irqrestore(&clocks_lock, flags);
456 return ret;
457}
458EXPORT_SYMBOL(clk_set_parent);
459
460struct clk *clk_get_parent(struct clk *clk)
461{
462 unsigned long flags;
463
464 if (unlikely(IS_ERR_OR_NULL(clk)))
465 return NULL;
466
467 if (!clk->ops || !clk->ops->get_parent)
468 return clk->parent;
469
470 spin_lock_irqsave(&clocks_lock, flags);
471 clk->parent = clk->ops->get_parent(clk);
472 spin_unlock_irqrestore(&clocks_lock, flags);
473 return clk->parent;
474}
475EXPORT_SYMBOL(clk_get_parent);
476
477static void __init sirfsoc_clk_init(void)
478{
479 clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
480}
481
482static struct of_device_id clkc_ids[] = {
483 { .compatible = "sirf,prima2-clkc" },
484};
485
486void __init sirfsoc_of_clk_init(void)
487{
488 struct device_node *np;
489 struct resource res;
490 struct map_desc sirfsoc_clkc_iodesc = {
491 .virtual = SIRFSOC_CLOCK_VA_BASE,
492 .type = MT_DEVICE,
493 };
494
495 np = of_find_matching_node(NULL, clkc_ids);
496 if (!np)
497 panic("unable to find compatible clkc node in dtb\n");
498
499 if (of_address_to_resource(np, 0, &res))
500 panic("unable to find clkc range in dtb");
501 of_node_put(np);
502
503 sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
504 sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
505
506 iotable_init(&sirfsoc_clkc_iodesc, 1);
507
508 sirfsoc_clk_init();
509}
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
new file mode 100644
index 000000000000..fa4a3b5c674a
--- /dev/null
+++ b/arch/arm/mach-prima2/common.h
@@ -0,0 +1,20 @@
1/*
2 * This file contains common function prototypes to avoid externs in the c files.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_COMMON_H__
10#define __MACH_PRIMA2_COMMON_H__
11
12#include <linux/init.h>
13#include <asm/mach/time.h>
14
15extern struct sys_timer sirfsoc_timer;
16
17extern void __init sirfsoc_of_irq_init(void);
18extern void __init sirfsoc_of_clk_init(void);
19
20#endif
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h
new file mode 100644
index 000000000000..66932518b1b7
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/clkdev.h
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-prima2/include/mach/clkdev.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_CLKDEV_H
10#define __MACH_CLKDEV_H
11
12#define __clk_get(clk) ({ 1; })
13#define __clk_put(clk) do { } while (0)
14
15#endif
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S
new file mode 100644
index 000000000000..bf75106333ff
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/debug-macro.S
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-prima2/include/mach/debug-macro.S
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <mach/hardware.h>
10#include <mach/uart.h>
11
12 .macro addruart, rp, rv
13 ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
14 ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
15 .endm
16
17 .macro senduart,rd,rx
18 str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
19 .endm
20
21 .macro busyuart,rd,rx
22 .endm
23
24 .macro waituart,rd,rx
251001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
26 tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
27 beq 1001b
28 .endm
29
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
new file mode 100644
index 000000000000..1c8a50f102a7
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/entry-macro.S
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-prima2/include/mach/entry-macro.S
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <mach/hardware.h>
10
11#define SIRFSOC_INT_ID 0x38
12
13 .macro get_irqnr_preamble, base, tmp
14 ldr \base, =sirfsoc_intc_base
15 ldr \base, [\base]
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq
20 cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f
21 movges \irqnr, #0
22 .endm
23
24 .macro disable_fiq
25 .endm
26
27 .macro arch_ret_to_user, tmp1, tmp2
28 .endm
29
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h
new file mode 100644
index 000000000000..105b96964f25
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/hardware.h
@@ -0,0 +1,15 @@
1/*
2 * arch/arm/mach-prima2/include/mach/hardware.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_HARDWARE_H__
10#define __MACH_HARDWARE_H__
11
12#include <asm/sizes.h>
13#include <mach/map.h>
14
15#endif
diff --git a/arch/arm/mach-prima2/include/mach/io.h b/arch/arm/mach-prima2/include/mach/io.h
new file mode 100644
index 000000000000..6c31e9ec279e
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/io.h
@@ -0,0 +1,16 @@
1/*
2 * arch/arm/mach-prima2/include/mach/io.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_IO_H
10#define __MACH_PRIMA2_IO_H
11
12#define IO_SPACE_LIMIT ((resource_size_t)0)
13
14#define __mem_pci(a) (a)
15
16#endif
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
new file mode 100644
index 000000000000..bb354f952fd6
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/irqs.h
@@ -0,0 +1,17 @@
1/*
2 * arch/arm/mach-prima2/include/mach/irqs.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_IRQS_H
10#define __ASM_ARCH_IRQS_H
11
12#define SIRFSOC_INTENAL_IRQ_START 0
13#define SIRFSOC_INTENAL_IRQ_END 59
14
15#define NR_IRQS 220
16
17#endif
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
new file mode 100644
index 000000000000..66b1ae2e553f
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/map.h
@@ -0,0 +1,16 @@
1/*
2 * memory & I/O static mapping definitions for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_MAP_H__
10#define __MACH_PRIMA2_MAP_H__
11
12#include <mach/vmalloc.h>
13
14#define SIRFSOC_VA(x) (VMALLOC_END + ((x) & 0x00FFF000))
15
16#endif
diff --git a/arch/arm/mach-prima2/include/mach/memory.h b/arch/arm/mach-prima2/include/mach/memory.h
new file mode 100644
index 000000000000..368cd5a0601a
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/memory.h
@@ -0,0 +1,21 @@
1/*
2 * arch/arm/mach-prima2/include/mach/memory.h
3 *
4 * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_MEMORY_H
10#define __ASM_ARCH_MEMORY_H
11
12#define PLAT_PHYS_OFFSET UL(0x00000000)
13
14/*
15 * Restrict DMA-able region to workaround silicon limitation.
16 * The limitation restricts buffers available for DMA to SD/MMC
17 * hardware to be below 256MB
18 */
19#define ARM_DMA_ZONE_SIZE (SZ_256M)
20
21#endif
diff --git a/arch/arm/mach-prima2/include/mach/system.h b/arch/arm/mach-prima2/include/mach/system.h
new file mode 100644
index 000000000000..0dbd257ad16d
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/system.h
@@ -0,0 +1,29 @@
1/*
2 * arch/arm/mach-prima2/include/mach/system.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_SYSTEM_H__
10#define __MACH_SYSTEM_H__
11
12#include <linux/bitops.h>
13#include <mach/hardware.h>
14
15#define SIRFSOC_SYS_RST_BIT BIT(31)
16
17extern void __iomem *sirfsoc_rstc_base;
18
19static inline void arch_idle(void)
20{
21 cpu_do_idle();
22}
23
24static inline void arch_reset(char mode, const char *cmd)
25{
26 writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
27}
28
29#endif
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h
new file mode 100644
index 000000000000..d6f98a75e562
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/timex.h
@@ -0,0 +1,14 @@
1/*
2 * arch/arm/mach-prima2/include/mach/timex.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_TIMEX_H__
10#define __MACH_TIMEX_H__
11
12#define CLOCK_TICK_RATE 1000000
13
14#endif
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h
new file mode 100644
index 000000000000..c98b4d5ac24a
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/uart.h
@@ -0,0 +1,23 @@
1/*
2 * arch/arm/mach-prima2/include/mach/uart.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
10#define __MACH_PRIMA2_SIRFSOC_UART_H
11
12/* UART-1: used as serial debug port */
13#define SIRFSOC_UART1_PA_BASE 0xb0060000
14#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
15#define SIRFSOC_UART1_SIZE SZ_4K
16
17#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
18#define SIRFSOC_UART_TXFIFO_DATA 0x0118
19
20#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
21#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
22
23#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
new file mode 100644
index 000000000000..83125c6a30b3
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -0,0 +1,40 @@
1/*
2 * arch/arm/mach-prima2/include/mach/uncompress.h
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_UNCOMPRESS_H
10#define __ASM_ARCH_UNCOMPRESS_H
11
12#include <linux/io.h>
13#include <mach/hardware.h>
14#include <mach/uart.h>
15
16void arch_decomp_setup(void)
17{
18}
19
20#define arch_decomp_wdog()
21
22static __inline__ void putc(char c)
23{
24 /*
25 * during kernel decompression, all mappings are flat:
26 * virt_addr == phys_addr
27 */
28 while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
29 & SIRFSOC_UART1_TXFIFO_FULL)
30 barrier();
31
32 __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
33}
34
35static inline void flush(void)
36{
37}
38
39#endif
40
diff --git a/arch/arm/mach-prima2/include/mach/vmalloc.h b/arch/arm/mach-prima2/include/mach/vmalloc.h
new file mode 100644
index 000000000000..c9f90fec78e3
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/vmalloc.h
@@ -0,0 +1,16 @@
1/*
2 * arch/arm/ach-prima2/include/mach/vmalloc.h
3 *
4 * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __MACH_VMALLOC_H
10#define __MACH_VMALLOC_H
11
12#include <linux/const.h>
13
14#define VMALLOC_END _AC(0xFEC00000, UL)
15
16#endif
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
new file mode 100644
index 000000000000..c3404cbb6ff7
--- /dev/null
+++ b/arch/arm/mach-prima2/irq.c
@@ -0,0 +1,71 @@
1/*
2 * interrupt controller support for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <mach/hardware.h>
13#include <asm/mach/irq.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17#define SIRFSOC_INT_RISC_MASK0 0x0018
18#define SIRFSOC_INT_RISC_MASK1 0x001C
19#define SIRFSOC_INT_RISC_LEVEL0 0x0020
20#define SIRFSOC_INT_RISC_LEVEL1 0x0024
21
22void __iomem *sirfsoc_intc_base;
23
24static __init void
25sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
26{
27 struct irq_chip_generic *gc;
28 struct irq_chip_type *ct;
29
30 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
31 ct = gc->chip_types;
32
33 ct->chip.irq_mask = irq_gc_mask_clr_bit;
34 ct->chip.irq_unmask = irq_gc_mask_set_bit;
35 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
36
37 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
38}
39
40static __init void sirfsoc_irq_init(void)
41{
42 sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
43 sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
44
45 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
46 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
47
48 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
49 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
50}
51
52static struct of_device_id intc_ids[] = {
53 { .compatible = "sirf,prima2-intc" },
54};
55
56void __init sirfsoc_of_irq_init(void)
57{
58 struct device_node *np;
59
60 np = of_find_matching_node(NULL, intc_ids);
61 if (!np)
62 panic("unable to find compatible intc node in dtb\n");
63
64 sirfsoc_intc_base = of_iomap(np, 0);
65 if (!sirfsoc_intc_base)
66 panic("unable to map intc cpu registers\n");
67
68 of_node_put(np);
69
70 sirfsoc_irq_init();
71}
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
new file mode 100644
index 000000000000..c26947d76e12
--- /dev/null
+++ b/arch/arm/mach-prima2/prima2.c
@@ -0,0 +1,40 @@
1/*
2 * Defines machines for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <asm/mach-types.h>
12#include <asm/mach/arch.h>
13#include <linux/of.h>
14#include <linux/of_platform.h>
15#include "common.h"
16
17static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
18 { .compatible = "simple-bus", },
19 {},
20};
21
22void __init sirfsoc_mach_init(void)
23{
24 of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
25}
26
27static const char *prima2cb_dt_match[] __initdata = {
28 "sirf,prima2-cb",
29 NULL
30};
31
32MACHINE_START(PRIMA2_EVB, "prima2cb")
33 /* Maintainer: Barry Song <baohua.song@csr.com> */
34 .boot_params = 0x00000100,
35 .init_early = sirfsoc_of_clk_init,
36 .init_irq = sirfsoc_of_irq_init,
37 .timer = &sirfsoc_timer,
38 .init_machine = sirfsoc_mach_init,
39 .dt_compat = prima2cb_dt_match,
40MACHINE_END
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
new file mode 100644
index 000000000000..d074786e83d4
--- /dev/null
+++ b/arch/arm/mach-prima2/rstc.c
@@ -0,0 +1,69 @@
1/*
2 * reset controller for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/mutex.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17void __iomem *sirfsoc_rstc_base;
18static DEFINE_MUTEX(rstc_lock);
19
20static struct of_device_id rstc_ids[] = {
21 { .compatible = "sirf,prima2-rstc" },
22};
23
24static int __init sirfsoc_of_rstc_init(void)
25{
26 struct device_node *np;
27
28 np = of_find_matching_node(NULL, rstc_ids);
29 if (!np)
30 panic("unable to find compatible rstc node in dtb\n");
31
32 sirfsoc_rstc_base = of_iomap(np, 0);
33 if (!sirfsoc_rstc_base)
34 panic("unable to map rstc cpu registers\n");
35
36 of_node_put(np);
37
38 return 0;
39}
40early_initcall(sirfsoc_of_rstc_init);
41
42int sirfsoc_reset_device(struct device *dev)
43{
44 const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
45 unsigned int reset_bit;
46
47 if (!prop)
48 return -ENODEV;
49
50 reset_bit = be32_to_cpup(prop);
51
52 mutex_lock(&rstc_lock);
53
54 /*
55 * Writing 1 to this bit resets corresponding block. Writing 0 to this
56 * bit de-asserts reset signal of the corresponding block.
57 * datasheet doesn't require explicit delay between the set and clear
58 * of reset bit. it could be shorter if tests pass.
59 */
60 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
61 sirfsoc_rstc_base + (reset_bit / 32) * 4);
62 msleep(10);
63 writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
64 sirfsoc_rstc_base + (reset_bit / 32) * 4);
65
66 mutex_unlock(&rstc_lock);
67
68 return 0;
69}
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
new file mode 100644
index 000000000000..44027f34a88a
--- /dev/null
+++ b/arch/arm/mach-prima2/timer.c
@@ -0,0 +1,217 @@
1/*
2 * System timer for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/kernel.h>
10#include <linux/interrupt.h>
11#include <linux/clockchips.h>
12#include <linux/clocksource.h>
13#include <linux/bitops.h>
14#include <linux/irq.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <mach/map.h>
21#include <asm/mach/time.h>
22
23#define SIRFSOC_TIMER_COUNTER_LO 0x0000
24#define SIRFSOC_TIMER_COUNTER_HI 0x0004
25#define SIRFSOC_TIMER_MATCH_0 0x0008
26#define SIRFSOC_TIMER_MATCH_1 0x000C
27#define SIRFSOC_TIMER_MATCH_2 0x0010
28#define SIRFSOC_TIMER_MATCH_3 0x0014
29#define SIRFSOC_TIMER_MATCH_4 0x0018
30#define SIRFSOC_TIMER_MATCH_5 0x001C
31#define SIRFSOC_TIMER_STATUS 0x0020
32#define SIRFSOC_TIMER_INT_EN 0x0024
33#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
34#define SIRFSOC_TIMER_DIV 0x002C
35#define SIRFSOC_TIMER_LATCH 0x0030
36#define SIRFSOC_TIMER_LATCHED_LO 0x0034
37#define SIRFSOC_TIMER_LATCHED_HI 0x0038
38
39#define SIRFSOC_TIMER_WDT_INDEX 5
40
41#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
42
43static void __iomem *sirfsoc_timer_base;
44static void __init sirfsoc_of_timer_map(void);
45
46/* timer0 interrupt handler */
47static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
48{
49 struct clock_event_device *ce = dev_id;
50
51 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
52
53 /* clear timer0 interrupt */
54 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
55
56 ce->event_handler(ce);
57
58 return IRQ_HANDLED;
59}
60
61/* read 64-bit timer counter */
62static cycle_t sirfsoc_timer_read(struct clocksource *cs)
63{
64 u64 cycles;
65
66 /* latch the 64-bit timer counter */
67 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
68 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
69 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
70
71 return cycles;
72}
73
74static int sirfsoc_timer_set_next_event(unsigned long delta,
75 struct clock_event_device *ce)
76{
77 unsigned long now, next;
78
79 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
80 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
81 next = now + delta;
82 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
83 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
84 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
85
86 return next - now > delta ? -ETIME : 0;
87}
88
89static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
90 struct clock_event_device *ce)
91{
92 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
93 switch (mode) {
94 case CLOCK_EVT_MODE_PERIODIC:
95 WARN_ON(1);
96 break;
97 case CLOCK_EVT_MODE_ONESHOT:
98 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
99 break;
100 case CLOCK_EVT_MODE_SHUTDOWN:
101 writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
102 break;
103 case CLOCK_EVT_MODE_UNUSED:
104 case CLOCK_EVT_MODE_RESUME:
105 break;
106 }
107}
108
109static struct clock_event_device sirfsoc_clockevent = {
110 .name = "sirfsoc_clockevent",
111 .rating = 200,
112 .features = CLOCK_EVT_FEAT_ONESHOT,
113 .set_mode = sirfsoc_timer_set_mode,
114 .set_next_event = sirfsoc_timer_set_next_event,
115};
116
117static struct clocksource sirfsoc_clocksource = {
118 .name = "sirfsoc_clocksource",
119 .rating = 200,
120 .mask = CLOCKSOURCE_MASK(64),
121 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
122 .read = sirfsoc_timer_read,
123};
124
125static struct irqaction sirfsoc_timer_irq = {
126 .name = "sirfsoc_timer0",
127 .flags = IRQF_TIMER,
128 .irq = 0,
129 .handler = sirfsoc_timer_interrupt,
130 .dev_id = &sirfsoc_clockevent,
131};
132
133/* Overwrite weak default sched_clock with more precise one */
134unsigned long long notrace sched_clock(void)
135{
136 static int is_mapped = 0;
137
138 /*
139 * sched_clock is called earlier than .init of sys_timer
140 * if we map timer memory in .init of sys_timer, system
141 * will panic due to illegal memory access
142 */
143 if(!is_mapped) {
144 sirfsoc_of_timer_map();
145 is_mapped = 1;
146 }
147
148 return sirfsoc_timer_read(NULL) * (NSEC_PER_SEC / CLOCK_TICK_RATE);
149}
150
151static void __init sirfsoc_clockevent_init(void)
152{
153 clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
154
155 sirfsoc_clockevent.max_delta_ns =
156 clockevent_delta2ns(-2, &sirfsoc_clockevent);
157 sirfsoc_clockevent.min_delta_ns =
158 clockevent_delta2ns(2, &sirfsoc_clockevent);
159
160 sirfsoc_clockevent.cpumask = cpumask_of(0);
161 clockevents_register_device(&sirfsoc_clockevent);
162}
163
164/* initialize the kernel jiffy timer source */
165static void __init sirfsoc_timer_init(void)
166{
167 unsigned long rate;
168
169 /* timer's input clock is io clock */
170 struct clk *clk = clk_get_sys("io", NULL);
171
172 BUG_ON(IS_ERR(clk));
173
174 rate = clk_get_rate(clk);
175
176 BUG_ON(rate < CLOCK_TICK_RATE);
177 BUG_ON(rate % CLOCK_TICK_RATE);
178
179 writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
180 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
181 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
182 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
183
184 BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
185
186 BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
187
188 sirfsoc_clockevent_init();
189}
190
191static struct of_device_id timer_ids[] = {
192 { .compatible = "sirf,prima2-tick" },
193};
194
195static void __init sirfsoc_of_timer_map(void)
196{
197 struct device_node *np;
198 const unsigned int *intspec;
199
200 np = of_find_matching_node(NULL, timer_ids);
201 if (!np)
202 panic("unable to find compatible timer node in dtb\n");
203 sirfsoc_timer_base = of_iomap(np, 0);
204 if (!sirfsoc_timer_base)
205 panic("unable to map timer cpu registers\n");
206
207 /* Get the interrupts property */
208 intspec = of_get_property(np, "interrupts", NULL);
209 BUG_ON(!intspec);
210 sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
211
212 of_node_put(np);
213}
214
215struct sys_timer sirfsoc_timer = {
216 .init = sirfsoc_timer_init,
217};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 0074b8dba793..edf0681c0e29 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,7 @@ config CACHE_L2X0
821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
822 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \ 822 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \ 823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE 824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || ARCH_PRIMA2
825 default y 825 default y
826 select OUTER_CACHE 826 select OUTER_CACHE
827 select OUTER_CACHE_SYNC 827 select OUTER_CACHE_SYNC
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 00:09:13 -0500