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-rw-r--r--arch/frv/include/asm/atomic.h68
-rw-r--r--arch/frv/include/asm/system.h2
-rw-r--r--arch/frv/kernel/frv_ksyms.c4
-rw-r--r--arch/frv/lib/Makefile2
-rw-r--r--arch/frv/lib/atomic-ops.S3
-rw-r--r--arch/frv/lib/atomic64-ops.S162
6 files changed, 236 insertions, 5 deletions
diff --git a/arch/frv/include/asm/atomic.h b/arch/frv/include/asm/atomic.h
index 0409d981fd39..00a57af79afc 100644
--- a/arch/frv/include/asm/atomic.h
+++ b/arch/frv/include/asm/atomic.h
@@ -121,10 +121,72 @@ static inline void atomic_dec(atomic_t *v)
121#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) 121#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
122#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0) 122#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
123 123
124/*
125 * 64-bit atomic ops
126 */
127typedef struct {
128 volatile long long counter;
129} atomic64_t;
130
131#define ATOMIC64_INIT(i) { (i) }
132
133static inline long long atomic64_read(atomic64_t *v)
134{
135 long long counter;
136
137 asm("ldd%I1 %M1,%0"
138 : "=e"(counter)
139 : "m"(v->counter));
140 return counter;
141}
142
143static inline void atomic64_set(atomic64_t *v, long long i)
144{
145 asm volatile("std%I0 %1,%M0"
146 : "=m"(v->counter)
147 : "e"(i));
148}
149
150extern long long atomic64_inc_return(atomic64_t *v);
151extern long long atomic64_dec_return(atomic64_t *v);
152extern long long atomic64_add_return(long long i, atomic64_t *v);
153extern long long atomic64_sub_return(long long i, atomic64_t *v);
154
155static inline long long atomic64_add_negative(long long i, atomic64_t *v)
156{
157 return atomic64_add_return(i, v) < 0;
158}
159
160static inline void atomic64_add(long long i, atomic64_t *v)
161{
162 atomic64_add_return(i, v);
163}
164
165static inline void atomic64_sub(long long i, atomic64_t *v)
166{
167 atomic64_sub_return(i, v);
168}
169
170static inline void atomic64_inc(atomic64_t *v)
171{
172 atomic64_inc_return(v);
173}
174
175static inline void atomic64_dec(atomic64_t *v)
176{
177 atomic64_dec_return(v);
178}
179
180#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
181#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
182#define atomic64_inc_and_test(v) (atomic64_inc_return((v)) == 0)
183
124/*****************************************************************************/ 184/*****************************************************************************/
125/* 185/*
126 * exchange value with memory 186 * exchange value with memory
127 */ 187 */
188extern uint64_t __xchg_64(uint64_t i, volatile void *v);
189
128#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS 190#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
129 191
130#define xchg(ptr, x) \ 192#define xchg(ptr, x) \
@@ -174,8 +236,10 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v);
174 236
175#define tas(ptr) (xchg((ptr), 1)) 237#define tas(ptr) (xchg((ptr), 1))
176 238
177#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new)) 239#define atomic_cmpxchg(v, old, new) (cmpxchg(&(v)->counter, old, new))
178#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 240#define atomic_xchg(v, new) (xchg(&(v)->counter, new))
241#define atomic64_cmpxchg(v, old, new) (__cmpxchg_64(old, new, &(v)->counter))
242#define atomic64_xchg(v, new) (__xchg_64(new, &(v)->counter))
179 243
180static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) 244static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
181{ 245{
diff --git a/arch/frv/include/asm/system.h b/arch/frv/include/asm/system.h
index 7742ec000cc4..efd22d9077ac 100644
--- a/arch/frv/include/asm/system.h
+++ b/arch/frv/include/asm/system.h
@@ -208,6 +208,8 @@ extern void free_initmem(void);
208 * - if (*ptr == test) then orig = *ptr; *ptr = test; 208 * - if (*ptr == test) then orig = *ptr; *ptr = test;
209 * - if (*ptr != test) then orig = *ptr; 209 * - if (*ptr != test) then orig = *ptr;
210 */ 210 */
211extern uint64_t __cmpxchg_64(uint64_t test, uint64_t new, volatile uint64_t *v);
212
211#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS 213#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
212 214
213#define cmpxchg(ptr, test, new) \ 215#define cmpxchg(ptr, test, new) \
diff --git a/arch/frv/kernel/frv_ksyms.c b/arch/frv/kernel/frv_ksyms.c
index 0316b3c50eff..a89803b58b9a 100644
--- a/arch/frv/kernel/frv_ksyms.c
+++ b/arch/frv/kernel/frv_ksyms.c
@@ -67,6 +67,10 @@ EXPORT_SYMBOL(atomic_sub_return);
67EXPORT_SYMBOL(__xchg_32); 67EXPORT_SYMBOL(__xchg_32);
68EXPORT_SYMBOL(__cmpxchg_32); 68EXPORT_SYMBOL(__cmpxchg_32);
69#endif 69#endif
70EXPORT_SYMBOL(atomic64_add_return);
71EXPORT_SYMBOL(atomic64_sub_return);
72EXPORT_SYMBOL(__xchg_64);
73EXPORT_SYMBOL(__cmpxchg_64);
70 74
71EXPORT_SYMBOL(__debug_bug_printk); 75EXPORT_SYMBOL(__debug_bug_printk);
72EXPORT_SYMBOL(__delay_loops_MHz); 76EXPORT_SYMBOL(__delay_loops_MHz);
diff --git a/arch/frv/lib/Makefile b/arch/frv/lib/Makefile
index 08be305c9f44..4ff2fb1e6b16 100644
--- a/arch/frv/lib/Makefile
+++ b/arch/frv/lib/Makefile
@@ -4,5 +4,5 @@
4 4
5lib-y := \ 5lib-y := \
6 __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \ 6 __ashldi3.o __lshrdi3.o __muldi3.o __ashrdi3.o __negdi2.o __ucmpdi2.o \
7 checksum.o memcpy.o memset.o atomic-ops.o \ 7 checksum.o memcpy.o memset.o atomic-ops.o atomic64-ops.o \
8 outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o 8 outsl_ns.o outsl_sw.o insl_ns.o insl_sw.o cache.o
diff --git a/arch/frv/lib/atomic-ops.S b/arch/frv/lib/atomic-ops.S
index ee0ac905fb08..5e9e6ab5dd0e 100644
--- a/arch/frv/lib/atomic-ops.S
+++ b/arch/frv/lib/atomic-ops.S
@@ -163,11 +163,10 @@ __cmpxchg_32:
163 ld.p @(gr11,gr0),gr8 163 ld.p @(gr11,gr0),gr8
164 orcr cc7,cc7,cc3 164 orcr cc7,cc7,cc3
165 subcc gr8,gr9,gr7,icc0 165 subcc gr8,gr9,gr7,icc0
166 bne icc0,#0,1f 166 bnelr icc0,#0
167 cst.p gr10,@(gr11,gr0) ,cc3,#1 167 cst.p gr10,@(gr11,gr0) ,cc3,#1
168 corcc gr29,gr29,gr0 ,cc3,#1 168 corcc gr29,gr29,gr0 ,cc3,#1
169 beq icc3,#0,0b 169 beq icc3,#0,0b
1701:
171 bralr 170 bralr
172 171
173 .size __cmpxchg_32, .-__cmpxchg_32 172 .size __cmpxchg_32, .-__cmpxchg_32
diff --git a/arch/frv/lib/atomic64-ops.S b/arch/frv/lib/atomic64-ops.S
new file mode 100644
index 000000000000..b6194eeac127
--- /dev/null
+++ b/arch/frv/lib/atomic64-ops.S
@@ -0,0 +1,162 @@
1/* kernel atomic64 operations
2 *
3 * For an explanation of how atomic ops work in this arch, see:
4 * Documentation/frv/atomic-ops.txt
5 *
6 * Copyright (C) 2009 Red Hat, Inc. All Rights Reserved.
7 * Written by David Howells (dhowells@redhat.com)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/spr-regs.h>
16
17 .text
18 .balign 4
19
20
21###############################################################################
22#
23# long long atomic64_inc_return(atomic64_t *v)
24#
25###############################################################################
26 .globl atomic64_inc_return
27 .type atomic64_inc_return,@function
28atomic64_inc_return:
29 or.p gr8,gr8,gr10
300:
31 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
32 ckeq icc3,cc7
33 ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
34 orcr cc7,cc7,cc3 /* set CC3 to true */
35 addicc gr9,#1,gr9,icc0
36 addxi gr8,#0,gr8,icc0
37 cstd.p gr8,@(gr10,gr0) ,cc3,#1
38 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
39 beq icc3,#0,0b
40 bralr
41
42 .size atomic64_inc_return, .-atomic64_inc_return
43
44###############################################################################
45#
46# long long atomic64_dec_return(atomic64_t *v)
47#
48###############################################################################
49 .globl atomic64_dec_return
50 .type atomic64_dec_return,@function
51atomic64_dec_return:
52 or.p gr8,gr8,gr10
530:
54 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
55 ckeq icc3,cc7
56 ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
57 orcr cc7,cc7,cc3 /* set CC3 to true */
58 subicc gr9,#1,gr9,icc0
59 subxi gr8,#0,gr8,icc0
60 cstd.p gr8,@(gr10,gr0) ,cc3,#1
61 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
62 beq icc3,#0,0b
63 bralr
64
65 .size atomic64_dec_return, .-atomic64_dec_return
66
67###############################################################################
68#
69# long long atomic64_add_return(long long i, atomic64_t *v)
70#
71###############################################################################
72 .globl atomic64_add_return
73 .type atomic64_add_return,@function
74atomic64_add_return:
75 or.p gr8,gr8,gr4
76 or gr9,gr9,gr5
770:
78 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
79 ckeq icc3,cc7
80 ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
81 orcr cc7,cc7,cc3 /* set CC3 to true */
82 addcc gr9,gr5,gr9,icc0
83 addx gr8,gr4,gr8,icc0
84 cstd.p gr8,@(gr10,gr0) ,cc3,#1
85 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
86 beq icc3,#0,0b
87 bralr
88
89 .size atomic64_add_return, .-atomic64_add_return
90
91###############################################################################
92#
93# long long atomic64_sub_return(long long i, atomic64_t *v)
94#
95###############################################################################
96 .globl atomic64_sub_return
97 .type atomic64_sub_return,@function
98atomic64_sub_return:
99 or.p gr8,gr8,gr4
100 or gr9,gr9,gr5
1010:
102 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
103 ckeq icc3,cc7
104 ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
105 orcr cc7,cc7,cc3 /* set CC3 to true */
106 subcc gr9,gr5,gr9,icc0
107 subx gr8,gr4,gr8,icc0
108 cstd.p gr8,@(gr10,gr0) ,cc3,#1
109 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
110 beq icc3,#0,0b
111 bralr
112
113 .size atomic64_sub_return, .-atomic64_sub_return
114
115###############################################################################
116#
117# uint64_t __xchg_64(uint64_t i, uint64_t *v)
118#
119###############################################################################
120 .globl __xchg_64
121 .type __xchg_64,@function
122__xchg_64:
123 or.p gr8,gr8,gr4
124 or gr9,gr9,gr5
1250:
126 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
127 ckeq icc3,cc7
128 ldd.p @(gr10,gr0),gr8 /* LDD.P/ORCR must be atomic */
129 orcr cc7,cc7,cc3 /* set CC3 to true */
130 cstd.p gr4,@(gr10,gr0) ,cc3,#1
131 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
132 beq icc3,#0,0b
133 bralr
134
135 .size __xchg_64, .-__xchg_64
136
137###############################################################################
138#
139# uint64_t __cmpxchg_64(uint64_t test, uint64_t new, uint64_t *v)
140#
141###############################################################################
142 .globl __cmpxchg_64
143 .type __cmpxchg_64,@function
144__cmpxchg_64:
145 or.p gr8,gr8,gr4
146 or gr9,gr9,gr5
1470:
148 orcc gr0,gr0,gr0,icc3 /* set ICC3.Z */
149 ckeq icc3,cc7
150 ldd.p @(gr12,gr0),gr8 /* LDD.P/ORCR must be atomic */
151 orcr cc7,cc7,cc3
152 subcc gr8,gr4,gr0,icc0
153 subcc.p gr9,gr5,gr0,icc1
154 bnelr icc0,#0
155 bnelr icc1,#0
156 cstd.p gr10,@(gr12,gr0) ,cc3,#1
157 corcc gr29,gr29,gr0 ,cc3,#1 /* clear ICC3.Z if store happens */
158 beq icc3,#0,0b
159 bralr
160
161 .size __cmpxchg_64, .-__cmpxchg_64
162
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