diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/anomaly.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 4c108c99cb6e..6a3499b02097 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h | |||
| @@ -181,7 +181,11 @@ | |||
| 181 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | 181 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ |
| 182 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 3) | 182 | #define ANOMALY_05000254 (__SILICON_REVISION__ > 3) |
| 183 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ | 183 | /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */ |
| 184 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 5) | 184 | /* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception |
| 185 | * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change | ||
| 186 | * after the behavior and the root cause are confirmed with hardware team. | ||
| 187 | */ | ||
| 188 | #define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP)) | ||
| 185 | /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ | 189 | /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */ |
| 186 | #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) | 190 | #define ANOMALY_05000258 (__SILICON_REVISION__ < 5) |
| 187 | /* ICPLB_STATUS MMR Register May Be Corrupted */ | 191 | /* ICPLB_STATUS MMR Register May Be Corrupted */ |