diff options
Diffstat (limited to 'arch')
47 files changed, 166 insertions, 166 deletions
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index c3c3a3339049..85579654d3b7 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c | |||
@@ -331,17 +331,17 @@ static int locomo_gpio_type(unsigned int irq, unsigned int type) | |||
331 | 331 | ||
332 | mask = 1 << (irq - LOCOMO_IRQ_GPIO_START); | 332 | mask = 1 << (irq - LOCOMO_IRQ_GPIO_START); |
333 | 333 | ||
334 | if (type == IRQT_PROBE) { | 334 | if (type == IRQ_TYPE_PROBE) { |
335 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) | 335 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) |
336 | return 0; | 336 | return 0; |
337 | type = __IRQT_RISEDGE | __IRQT_FALEDGE; | 337 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
338 | } | 338 | } |
339 | 339 | ||
340 | if (type & __IRQT_RISEDGE) | 340 | if (type & IRQ_TYPE_EDGE_RISING) |
341 | GPIO_IRQ_rising_edge |= mask; | 341 | GPIO_IRQ_rising_edge |= mask; |
342 | else | 342 | else |
343 | GPIO_IRQ_rising_edge &= ~mask; | 343 | GPIO_IRQ_rising_edge &= ~mask; |
344 | if (type & __IRQT_FALEDGE) | 344 | if (type & IRQ_TYPE_EDGE_FALLING) |
345 | GPIO_IRQ_falling_edge |= mask; | 345 | GPIO_IRQ_falling_edge |= mask; |
346 | else | 346 | else |
347 | GPIO_IRQ_falling_edge &= ~mask; | 347 | GPIO_IRQ_falling_edge &= ~mask; |
@@ -473,7 +473,7 @@ static void locomo_setup_irq(struct locomo *lchip) | |||
473 | /* | 473 | /* |
474 | * Install handler for IRQ_LOCOMO_HW. | 474 | * Install handler for IRQ_LOCOMO_HW. |
475 | */ | 475 | */ |
476 | set_irq_type(lchip->irq, IRQT_FALLING); | 476 | set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); |
477 | set_irq_chip_data(lchip->irq, irqbase); | 477 | set_irq_chip_data(lchip->irq, irqbase); |
478 | set_irq_chained_handler(lchip->irq, locomo_handler); | 478 | set_irq_chained_handler(lchip->irq, locomo_handler); |
479 | 479 | ||
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 0a8e1ff2af8a..f6d3fdda7067 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c | |||
@@ -241,14 +241,14 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) | |||
241 | void __iomem *mapbase = get_irq_chip_data(irq); | 241 | void __iomem *mapbase = get_irq_chip_data(irq); |
242 | unsigned long ip0; | 242 | unsigned long ip0; |
243 | 243 | ||
244 | if (flags == IRQT_PROBE) | 244 | if (flags == IRQ_TYPE_PROBE) |
245 | return 0; | 245 | return 0; |
246 | 246 | ||
247 | if ((!(flags & __IRQT_RISEDGE) ^ !(flags & __IRQT_FALEDGE)) == 0) | 247 | if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) |
248 | return -EINVAL; | 248 | return -EINVAL; |
249 | 249 | ||
250 | ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); | 250 | ip0 = sa1111_readl(mapbase + SA1111_INTPOL0); |
251 | if (flags & __IRQT_RISEDGE) | 251 | if (flags & IRQ_TYPE_EDGE_RISING) |
252 | ip0 &= ~mask; | 252 | ip0 &= ~mask; |
253 | else | 253 | else |
254 | ip0 |= mask; | 254 | ip0 |= mask; |
@@ -338,14 +338,14 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags) | |||
338 | void __iomem *mapbase = get_irq_chip_data(irq); | 338 | void __iomem *mapbase = get_irq_chip_data(irq); |
339 | unsigned long ip1; | 339 | unsigned long ip1; |
340 | 340 | ||
341 | if (flags == IRQT_PROBE) | 341 | if (flags == IRQ_TYPE_PROBE) |
342 | return 0; | 342 | return 0; |
343 | 343 | ||
344 | if ((!(flags & __IRQT_RISEDGE) ^ !(flags & __IRQT_FALEDGE)) == 0) | 344 | if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0) |
345 | return -EINVAL; | 345 | return -EINVAL; |
346 | 346 | ||
347 | ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); | 347 | ip1 = sa1111_readl(mapbase + SA1111_INTPOL1); |
348 | if (flags & __IRQT_RISEDGE) | 348 | if (flags & IRQ_TYPE_EDGE_RISING) |
349 | ip1 &= ~mask; | 349 | ip1 &= ~mask; |
350 | else | 350 | else |
351 | ip1 |= mask; | 351 | ip1 |= mask; |
@@ -427,7 +427,7 @@ static void sa1111_setup_irq(struct sa1111 *sachip) | |||
427 | /* | 427 | /* |
428 | * Register SA1111 interrupt | 428 | * Register SA1111 interrupt |
429 | */ | 429 | */ |
430 | set_irq_type(sachip->irq, IRQT_RISING); | 430 | set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); |
431 | set_irq_data(sachip->irq, irqbase); | 431 | set_irq_data(sachip->irq, irqbase); |
432 | set_irq_chained_handler(sachip->irq, sa1111_irq_handler); | 432 | set_irq_chained_handler(sachip->irq, sa1111_irq_handler); |
433 | } | 433 | } |
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c index 8a2a958639db..b4b67eb1cbcb 100644 --- a/arch/arm/mach-at91/board-cap9adk.c +++ b/arch/arm/mach-at91/board-cap9adk.c | |||
@@ -330,10 +330,10 @@ static void __init cap9adk_board_init(void) | |||
330 | /* Serial */ | 330 | /* Serial */ |
331 | at91_add_device_serial(); | 331 | at91_add_device_serial(); |
332 | /* USB Host */ | 332 | /* USB Host */ |
333 | set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH); | 333 | set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); |
334 | at91_add_device_usbh(&cap9adk_usbh_data); | 334 | at91_add_device_usbh(&cap9adk_usbh_data); |
335 | /* USB HS */ | 335 | /* USB HS */ |
336 | set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH); | 336 | set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); |
337 | at91_add_device_usba(&cap9adk_usba_udc_data); | 337 | at91_add_device_usba(&cap9adk_usba_udc_data); |
338 | /* SPI */ | 338 | /* SPI */ |
339 | at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices)); | 339 | at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices)); |
@@ -350,7 +350,7 @@ static void __init cap9adk_board_init(void) | |||
350 | /* I2C */ | 350 | /* I2C */ |
351 | at91_add_device_i2c(NULL, 0); | 351 | at91_add_device_i2c(NULL, 0); |
352 | /* LCD Controller */ | 352 | /* LCD Controller */ |
353 | set_irq_type(AT91CAP9_ID_LCDC, IRQT_HIGH); | 353 | set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); |
354 | at91_add_device_lcdc(&cap9adk_lcdc_data); | 354 | at91_add_device_lcdc(&cap9adk_lcdc_data); |
355 | /* AC97 */ | 355 | /* AC97 */ |
356 | at91_add_device_ac97(&cap9adk_ac97_data); | 356 | at91_add_device_ac97(&cap9adk_ac97_data); |
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index 78a5cdb746dc..ca87587b2b4b 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c | |||
@@ -56,19 +56,19 @@ static int at91_aic_set_type(unsigned irq, unsigned type) | |||
56 | unsigned int smr, srctype; | 56 | unsigned int smr, srctype; |
57 | 57 | ||
58 | switch (type) { | 58 | switch (type) { |
59 | case IRQT_HIGH: | 59 | case IRQ_TYPE_LEVEL_HIGH: |
60 | srctype = AT91_AIC_SRCTYPE_HIGH; | 60 | srctype = AT91_AIC_SRCTYPE_HIGH; |
61 | break; | 61 | break; |
62 | case IRQT_RISING: | 62 | case IRQ_TYPE_EDGE_RISING: |
63 | srctype = AT91_AIC_SRCTYPE_RISING; | 63 | srctype = AT91_AIC_SRCTYPE_RISING; |
64 | break; | 64 | break; |
65 | case IRQT_LOW: | 65 | case IRQ_TYPE_LEVEL_LOW: |
66 | if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ | 66 | if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ |
67 | srctype = AT91_AIC_SRCTYPE_LOW; | 67 | srctype = AT91_AIC_SRCTYPE_LOW; |
68 | else | 68 | else |
69 | return -EINVAL; | 69 | return -EINVAL; |
70 | break; | 70 | break; |
71 | case IRQT_FALLING: | 71 | case IRQ_TYPE_EDGE_FALLING: |
72 | if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ | 72 | if ((irq == AT91_ID_FIQ) || is_extern_irq(irq)) /* only supported on external interrupts */ |
73 | srctype = AT91_AIC_SRCTYPE_FALLING; | 73 | srctype = AT91_AIC_SRCTYPE_FALLING; |
74 | else | 74 | else |
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 1d7bca6aa441..5fed57608507 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
@@ -226,7 +226,7 @@ static void ep93xx_gpio_irq_ack(unsigned int irq) | |||
226 | int port = line >> 3; | 226 | int port = line >> 3; |
227 | int port_mask = 1 << (line & 7); | 227 | int port_mask = 1 << (line & 7); |
228 | 228 | ||
229 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { | 229 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
230 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 230 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
231 | ep93xx_gpio_update_int_params(port); | 231 | ep93xx_gpio_update_int_params(port); |
232 | } | 232 | } |
@@ -240,7 +240,7 @@ static void ep93xx_gpio_irq_mask_ack(unsigned int irq) | |||
240 | int port = line >> 3; | 240 | int port = line >> 3; |
241 | int port_mask = 1 << (line & 7); | 241 | int port_mask = 1 << (line & 7); |
242 | 242 | ||
243 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) | 243 | if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) |
244 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 244 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
245 | 245 | ||
246 | gpio_int_unmasked[port] &= ~port_mask; | 246 | gpio_int_unmasked[port] &= ~port_mask; |
@@ -283,27 +283,27 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type) | |||
283 | gpio_direction_input(gpio); | 283 | gpio_direction_input(gpio); |
284 | 284 | ||
285 | switch (type) { | 285 | switch (type) { |
286 | case IRQT_RISING: | 286 | case IRQ_TYPE_EDGE_RISING: |
287 | gpio_int_type1[port] |= port_mask; | 287 | gpio_int_type1[port] |= port_mask; |
288 | gpio_int_type2[port] |= port_mask; | 288 | gpio_int_type2[port] |= port_mask; |
289 | desc->handle_irq = handle_edge_irq; | 289 | desc->handle_irq = handle_edge_irq; |
290 | break; | 290 | break; |
291 | case IRQT_FALLING: | 291 | case IRQ_TYPE_EDGE_FALLING: |
292 | gpio_int_type1[port] |= port_mask; | 292 | gpio_int_type1[port] |= port_mask; |
293 | gpio_int_type2[port] &= ~port_mask; | 293 | gpio_int_type2[port] &= ~port_mask; |
294 | desc->handle_irq = handle_edge_irq; | 294 | desc->handle_irq = handle_edge_irq; |
295 | break; | 295 | break; |
296 | case IRQT_HIGH: | 296 | case IRQ_TYPE_LEVEL_HIGH: |
297 | gpio_int_type1[port] &= ~port_mask; | 297 | gpio_int_type1[port] &= ~port_mask; |
298 | gpio_int_type2[port] |= port_mask; | 298 | gpio_int_type2[port] |= port_mask; |
299 | desc->handle_irq = handle_level_irq; | 299 | desc->handle_irq = handle_level_irq; |
300 | break; | 300 | break; |
301 | case IRQT_LOW: | 301 | case IRQ_TYPE_LEVEL_LOW: |
302 | gpio_int_type1[port] &= ~port_mask; | 302 | gpio_int_type1[port] &= ~port_mask; |
303 | gpio_int_type2[port] &= ~port_mask; | 303 | gpio_int_type2[port] &= ~port_mask; |
304 | desc->handle_irq = handle_level_irq; | 304 | desc->handle_irq = handle_level_irq; |
305 | break; | 305 | break; |
306 | case IRQT_BOTHEDGE: | 306 | case IRQ_TYPE_EDGE_BOTH: |
307 | gpio_int_type1[port] |= port_mask; | 307 | gpio_int_type1[port] |= port_mask; |
308 | /* set initial polarity based on current input level */ | 308 | /* set initial polarity based on current input level */ |
309 | if (gpio_get_value(gpio)) | 309 | if (gpio_get_value(gpio)) |
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c index e6695c4e623b..e1b1f028b930 100644 --- a/arch/arm/mach-imx/irq.c +++ b/arch/arm/mach-imx/irq.c | |||
@@ -111,7 +111,7 @@ imx_gpio_irq_type(unsigned int _irq, unsigned int type) | |||
111 | reg = irq >> 5; | 111 | reg = irq >> 5; |
112 | bit = 1 << (irq % 32); | 112 | bit = 1 << (irq % 32); |
113 | 113 | ||
114 | if (type == IRQT_PROBE) { | 114 | if (type == IRQ_TYPE_PROBE) { |
115 | /* Don't mess with enabled GPIOs using preconfigured edges or | 115 | /* Don't mess with enabled GPIOs using preconfigured edges or |
116 | GPIOs set to alternate function during probe */ | 116 | GPIOs set to alternate function during probe */ |
117 | /* TODO: support probe */ | 117 | /* TODO: support probe */ |
@@ -120,7 +120,7 @@ imx_gpio_irq_type(unsigned int _irq, unsigned int type) | |||
120 | // return 0; | 120 | // return 0; |
121 | // if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) | 121 | // if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2))) |
122 | // return 0; | 122 | // return 0; |
123 | // type = __IRQT_RISEDGE | __IRQT_FALEDGE; | 123 | // type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
124 | } | 124 | } |
125 | 125 | ||
126 | GIUS(reg) |= bit; | 126 | GIUS(reg) |= bit; |
@@ -128,19 +128,19 @@ imx_gpio_irq_type(unsigned int _irq, unsigned int type) | |||
128 | 128 | ||
129 | DEBUG_IRQ("setting type of irq %d to ", _irq); | 129 | DEBUG_IRQ("setting type of irq %d to ", _irq); |
130 | 130 | ||
131 | if (type & __IRQT_RISEDGE) { | 131 | if (type & IRQ_TYPE_EDGE_RISING) { |
132 | DEBUG_IRQ("rising edges\n"); | 132 | DEBUG_IRQ("rising edges\n"); |
133 | irq_type = 0x0; | 133 | irq_type = 0x0; |
134 | } | 134 | } |
135 | if (type & __IRQT_FALEDGE) { | 135 | if (type & IRQ_TYPE_EDGE_FALLING) { |
136 | DEBUG_IRQ("falling edges\n"); | 136 | DEBUG_IRQ("falling edges\n"); |
137 | irq_type = 0x1; | 137 | irq_type = 0x1; |
138 | } | 138 | } |
139 | if (type & __IRQT_LOWLVL) { | 139 | if (type & IRQ_TYPE_LEVEL_LOW) { |
140 | DEBUG_IRQ("low level\n"); | 140 | DEBUG_IRQ("low level\n"); |
141 | irq_type = 0x3; | 141 | irq_type = 0x3; |
142 | } | 142 | } |
143 | if (type & __IRQT_HIGHLVL) { | 143 | if (type & IRQ_TYPE_LEVEL_HIGH) { |
144 | DEBUG_IRQ("high level\n"); | 144 | DEBUG_IRQ("high level\n"); |
145 | irq_type = 0x2; | 145 | irq_type = 0x2; |
146 | } | 146 | } |
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index 81cdc8267206..daf28074134b 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c | |||
@@ -329,19 +329,19 @@ static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type) | |||
329 | /* | 329 | /* |
330 | * Then, set the proper trigger type. | 330 | * Then, set the proper trigger type. |
331 | */ | 331 | */ |
332 | if (type & IRQT_FALLING) | 332 | if (type & IRQ_TYPE_EDGE_FALLING) |
333 | GPIO_IRQ_falling_edge |= 1 << line; | 333 | GPIO_IRQ_falling_edge |= 1 << line; |
334 | else | 334 | else |
335 | GPIO_IRQ_falling_edge &= ~(1 << line); | 335 | GPIO_IRQ_falling_edge &= ~(1 << line); |
336 | if (type & IRQT_RISING) | 336 | if (type & IRQ_TYPE_EDGE_RISING) |
337 | GPIO_IRQ_rising_edge |= 1 << line; | 337 | GPIO_IRQ_rising_edge |= 1 << line; |
338 | else | 338 | else |
339 | GPIO_IRQ_rising_edge &= ~(1 << line); | 339 | GPIO_IRQ_rising_edge &= ~(1 << line); |
340 | if (type & IRQT_LOW) | 340 | if (type & IRQ_TYPE_LEVEL_LOW) |
341 | GPIO_IRQ_level_low |= 1 << line; | 341 | GPIO_IRQ_level_low |= 1 << line; |
342 | else | 342 | else |
343 | GPIO_IRQ_level_low &= ~(1 << line); | 343 | GPIO_IRQ_level_low &= ~(1 << line); |
344 | if (type & IRQT_HIGH) | 344 | if (type & IRQ_TYPE_LEVEL_HIGH) |
345 | GPIO_IRQ_level_high |= 1 << line; | 345 | GPIO_IRQ_level_high |= 1 << line; |
346 | else | 346 | else |
347 | GPIO_IRQ_level_high &= ~(1 << line); | 347 | GPIO_IRQ_level_high &= ~(1 << line); |
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index 5fea5a132939..df16a4eac490 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c | |||
@@ -126,23 +126,23 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type) | |||
126 | return -EINVAL; | 126 | return -EINVAL; |
127 | 127 | ||
128 | switch (type) { | 128 | switch (type) { |
129 | case IRQT_BOTHEDGE: | 129 | case IRQ_TYPE_EDGE_BOTH: |
130 | int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL; | 130 | int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL; |
131 | irq_type = IXP23XX_IRQ_EDGE; | 131 | irq_type = IXP23XX_IRQ_EDGE; |
132 | break; | 132 | break; |
133 | case IRQT_RISING: | 133 | case IRQ_TYPE_EDGE_RISING: |
134 | int_style = IXP23XX_GPIO_STYLE_RISING_EDGE; | 134 | int_style = IXP23XX_GPIO_STYLE_RISING_EDGE; |
135 | irq_type = IXP23XX_IRQ_EDGE; | 135 | irq_type = IXP23XX_IRQ_EDGE; |
136 | break; | 136 | break; |
137 | case IRQT_FALLING: | 137 | case IRQ_TYPE_EDGE_FALLING: |
138 | int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE; | 138 | int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE; |
139 | irq_type = IXP23XX_IRQ_EDGE; | 139 | irq_type = IXP23XX_IRQ_EDGE; |
140 | break; | 140 | break; |
141 | case IRQT_HIGH: | 141 | case IRQ_TYPE_LEVEL_HIGH: |
142 | int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH; | 142 | int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH; |
143 | irq_type = IXP23XX_IRQ_LEVEL; | 143 | irq_type = IXP23XX_IRQ_LEVEL; |
144 | break; | 144 | break; |
145 | case IRQT_LOW: | 145 | case IRQ_TYPE_LEVEL_LOW: |
146 | int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW; | 146 | int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW; |
147 | irq_type = IXP23XX_IRQ_LEVEL; | 147 | irq_type = IXP23XX_IRQ_LEVEL; |
148 | break; | 148 | break; |
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index f0f70ba1e46d..896ff9f840d9 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c | |||
@@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) | |||
110 | 110 | ||
111 | static void __init roadrunner_pci_preinit(void) | 111 | static void __init roadrunner_pci_preinit(void) |
112 | { | 112 | { |
113 | set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW); | 113 | set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
114 | set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW); | 114 | set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); |
115 | 115 | ||
116 | ixp23xx_pci_preinit(); | 116 | ixp23xx_pci_preinit(); |
117 | } | 117 | } |
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 3f867691d9f2..c6e044befccb 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c | |||
@@ -30,10 +30,10 @@ | |||
30 | 30 | ||
31 | void __init avila_pci_preinit(void) | 31 | void __init avila_pci_preinit(void) |
32 | { | 32 | { |
33 | set_irq_type(IRQ_AVILA_PCI_INTA, IRQT_LOW); | 33 | set_irq_type(IRQ_AVILA_PCI_INTA, IRQ_TYPE_LEVEL_LOW); |
34 | set_irq_type(IRQ_AVILA_PCI_INTB, IRQT_LOW); | 34 | set_irq_type(IRQ_AVILA_PCI_INTB, IRQ_TYPE_LEVEL_LOW); |
35 | set_irq_type(IRQ_AVILA_PCI_INTC, IRQT_LOW); | 35 | set_irq_type(IRQ_AVILA_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IRQ_AVILA_PCI_INTD, IRQT_LOW); | 36 | set_irq_type(IRQ_AVILA_PCI_INTD, IRQ_TYPE_LEVEL_LOW); |
37 | 37 | ||
38 | ixp4xx_pci_preinit(); | 38 | ixp4xx_pci_preinit(); |
39 | } | 39 | } |
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 3781b3db9f49..3947c506b4f3 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
@@ -142,23 +142,23 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) | |||
142 | return -EINVAL; | 142 | return -EINVAL; |
143 | 143 | ||
144 | switch (type){ | 144 | switch (type){ |
145 | case IRQT_BOTHEDGE: | 145 | case IRQ_TYPE_EDGE_BOTH: |
146 | int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; | 146 | int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; |
147 | irq_type = IXP4XX_IRQ_EDGE; | 147 | irq_type = IXP4XX_IRQ_EDGE; |
148 | break; | 148 | break; |
149 | case IRQT_RISING: | 149 | case IRQ_TYPE_EDGE_RISING: |
150 | int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; | 150 | int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; |
151 | irq_type = IXP4XX_IRQ_EDGE; | 151 | irq_type = IXP4XX_IRQ_EDGE; |
152 | break; | 152 | break; |
153 | case IRQT_FALLING: | 153 | case IRQ_TYPE_EDGE_FALLING: |
154 | int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; | 154 | int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; |
155 | irq_type = IXP4XX_IRQ_EDGE; | 155 | irq_type = IXP4XX_IRQ_EDGE; |
156 | break; | 156 | break; |
157 | case IRQT_HIGH: | 157 | case IRQ_TYPE_LEVEL_HIGH: |
158 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; | 158 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; |
159 | irq_type = IXP4XX_IRQ_LEVEL; | 159 | irq_type = IXP4XX_IRQ_LEVEL; |
160 | break; | 160 | break; |
161 | case IRQT_LOW: | 161 | case IRQ_TYPE_LEVEL_LOW: |
162 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; | 162 | int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; |
163 | irq_type = IXP4XX_IRQ_LEVEL; | 163 | irq_type = IXP4XX_IRQ_LEVEL; |
164 | break; | 164 | break; |
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index ad2e5b97966e..be4f4a208b90 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c | |||
@@ -27,8 +27,8 @@ | |||
27 | 27 | ||
28 | void __init coyote_pci_preinit(void) | 28 | void __init coyote_pci_preinit(void) |
29 | { | 29 | { |
30 | set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQT_LOW); | 30 | set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQT_LOW); | 31 | set_irq_type(IRQ_COYOTE_PCI_SLOT1, IRQ_TYPE_LEVEL_LOW); |
32 | 32 | ||
33 | ixp4xx_pci_preinit(); | 33 | ixp4xx_pci_preinit(); |
34 | } | 34 | } |
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index 9db7e1f42011..926d15f885fb 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c | |||
@@ -25,12 +25,12 @@ | |||
25 | 25 | ||
26 | void __init dsmg600_pci_preinit(void) | 26 | void __init dsmg600_pci_preinit(void) |
27 | { | 27 | { |
28 | set_irq_type(IRQ_DSMG600_PCI_INTA, IRQT_LOW); | 28 | set_irq_type(IRQ_DSMG600_PCI_INTA, IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_DSMG600_PCI_INTB, IRQT_LOW); | 29 | set_irq_type(IRQ_DSMG600_PCI_INTB, IRQ_TYPE_LEVEL_LOW); |
30 | set_irq_type(IRQ_DSMG600_PCI_INTC, IRQT_LOW); | 30 | set_irq_type(IRQ_DSMG600_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_DSMG600_PCI_INTD, IRQT_LOW); | 31 | set_irq_type(IRQ_DSMG600_PCI_INTD, IRQ_TYPE_LEVEL_LOW); |
32 | set_irq_type(IRQ_DSMG600_PCI_INTE, IRQT_LOW); | 32 | set_irq_type(IRQ_DSMG600_PCI_INTE, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_DSMG600_PCI_INTF, IRQT_LOW); | 33 | set_irq_type(IRQ_DSMG600_PCI_INTF, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index f19f3f6feda1..ca12a9ca0830 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c | |||
@@ -25,9 +25,9 @@ | |||
25 | 25 | ||
26 | void __init fsg_pci_preinit(void) | 26 | void __init fsg_pci_preinit(void) |
27 | { | 27 | { |
28 | set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW); | 28 | set_irq_type(IRQ_FSG_PCI_INTA, IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW); | 29 | set_irq_type(IRQ_FSG_PCI_INTB, IRQ_TYPE_LEVEL_LOW); |
30 | set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW); | 30 | set_irq_type(IRQ_FSG_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
31 | 31 | ||
32 | ixp4xx_pci_preinit(); | 32 | ixp4xx_pci_preinit(); |
33 | } | 33 | } |
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 6abf568322d3..afd1dc14e597 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c | |||
@@ -29,8 +29,8 @@ | |||
29 | 29 | ||
30 | void __init gateway7001_pci_preinit(void) | 30 | void __init gateway7001_pci_preinit(void) |
31 | { | 31 | { |
32 | set_irq_type(IRQ_IXP4XX_GPIO10, IRQT_LOW); | 32 | set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXP4XX_GPIO11, IRQT_LOW); | 33 | set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 49dec7868807..20960704183b 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c | |||
@@ -41,10 +41,10 @@ | |||
41 | */ | 41 | */ |
42 | void __init gtwx5715_pci_preinit(void) | 42 | void __init gtwx5715_pci_preinit(void) |
43 | { | 43 | { |
44 | set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQT_LOW); | 44 | set_irq_type(GTWX5715_PCI_SLOT0_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); |
45 | set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQT_LOW); | 45 | set_irq_type(GTWX5715_PCI_SLOT0_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); |
46 | set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQT_LOW); | 46 | set_irq_type(GTWX5715_PCI_SLOT1_INTA_IRQ, IRQ_TYPE_LEVEL_LOW); |
47 | set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQT_LOW); | 47 | set_irq_type(GTWX5715_PCI_SLOT1_INTB_IRQ, IRQ_TYPE_LEVEL_LOW); |
48 | 48 | ||
49 | ixp4xx_pci_preinit(); | 49 | ixp4xx_pci_preinit(); |
50 | } | 50 | } |
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 408796004812..7d9bb4d23104 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c | |||
@@ -27,10 +27,10 @@ | |||
27 | 27 | ||
28 | void __init ixdp425_pci_preinit(void) | 28 | void __init ixdp425_pci_preinit(void) |
29 | { | 29 | { |
30 | set_irq_type(IRQ_IXDP425_PCI_INTA, IRQT_LOW); | 30 | set_irq_type(IRQ_IXDP425_PCI_INTA, IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_IXDP425_PCI_INTB, IRQT_LOW); | 31 | set_irq_type(IRQ_IXDP425_PCI_INTB, IRQ_TYPE_LEVEL_LOW); |
32 | set_irq_type(IRQ_IXDP425_PCI_INTC, IRQT_LOW); | 32 | set_irq_type(IRQ_IXDP425_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXDP425_PCI_INTD, IRQT_LOW); | 33 | set_irq_type(IRQ_IXDP425_PCI_INTD, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index d1e75b7dc3b1..37d9f2e8f602 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c | |||
@@ -25,8 +25,8 @@ | |||
25 | 25 | ||
26 | void __init ixdpg425_pci_preinit(void) | 26 | void __init ixdpg425_pci_preinit(void) |
27 | { | 27 | { |
28 | set_irq_type(IRQ_IXP4XX_GPIO6, IRQT_LOW); | 28 | set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_IXP4XX_GPIO7, IRQT_LOW); | 29 | set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); |
30 | 30 | ||
31 | ixp4xx_pci_preinit(); | 31 | ixp4xx_pci_preinit(); |
32 | } | 32 | } |
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index b8ebaf4a9c8e..1088426fdcee 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c | |||
@@ -24,11 +24,11 @@ | |||
24 | 24 | ||
25 | void __init nas100d_pci_preinit(void) | 25 | void __init nas100d_pci_preinit(void) |
26 | { | 26 | { |
27 | set_irq_type(IRQ_NAS100D_PCI_INTA, IRQT_LOW); | 27 | set_irq_type(IRQ_NAS100D_PCI_INTA, IRQ_TYPE_LEVEL_LOW); |
28 | set_irq_type(IRQ_NAS100D_PCI_INTB, IRQT_LOW); | 28 | set_irq_type(IRQ_NAS100D_PCI_INTB, IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_NAS100D_PCI_INTC, IRQT_LOW); | 29 | set_irq_type(IRQ_NAS100D_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
30 | set_irq_type(IRQ_NAS100D_PCI_INTD, IRQT_LOW); | 30 | set_irq_type(IRQ_NAS100D_PCI_INTD, IRQ_TYPE_LEVEL_LOW); |
31 | set_irq_type(IRQ_NAS100D_PCI_INTE, IRQT_LOW); | 31 | set_irq_type(IRQ_NAS100D_PCI_INTE, IRQ_TYPE_LEVEL_LOW); |
32 | 32 | ||
33 | ixp4xx_pci_preinit(); | 33 | ixp4xx_pci_preinit(); |
34 | } | 34 | } |
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 04661fef97f5..4429b8448b61 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c | |||
@@ -24,9 +24,9 @@ | |||
24 | 24 | ||
25 | void __init nslu2_pci_preinit(void) | 25 | void __init nslu2_pci_preinit(void) |
26 | { | 26 | { |
27 | set_irq_type(IRQ_NSLU2_PCI_INTA, IRQT_LOW); | 27 | set_irq_type(IRQ_NSLU2_PCI_INTA, IRQ_TYPE_LEVEL_LOW); |
28 | set_irq_type(IRQ_NSLU2_PCI_INTB, IRQT_LOW); | 28 | set_irq_type(IRQ_NSLU2_PCI_INTB, IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_NSLU2_PCI_INTC, IRQT_LOW); | 29 | set_irq_type(IRQ_NSLU2_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
30 | 30 | ||
31 | ixp4xx_pci_preinit(); | 31 | ixp4xx_pci_preinit(); |
32 | } | 32 | } |
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index 6588f2c758e2..0f00feab67f8 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c | |||
@@ -29,8 +29,8 @@ | |||
29 | 29 | ||
30 | void __init wg302v2_pci_preinit(void) | 30 | void __init wg302v2_pci_preinit(void) |
31 | { | 31 | { |
32 | set_irq_type(IRQ_IXP4XX_GPIO8, IRQT_LOW); | 32 | set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXP4XX_GPIO9, IRQT_LOW); | 33 | set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 4c3ab43e1046..0b06941a1eed 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c | |||
@@ -72,21 +72,21 @@ static int ks8695_irq_set_type(unsigned int irqno, unsigned int type) | |||
72 | ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); | 72 | ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); |
73 | 73 | ||
74 | switch (type) { | 74 | switch (type) { |
75 | case IRQT_HIGH: | 75 | case IRQ_TYPE_LEVEL_HIGH: |
76 | mode = IOPC_TM_HIGH; | 76 | mode = IOPC_TM_HIGH; |
77 | level_triggered = 1; | 77 | level_triggered = 1; |
78 | break; | 78 | break; |
79 | case IRQT_LOW: | 79 | case IRQ_TYPE_LEVEL_LOW: |
80 | mode = IOPC_TM_LOW; | 80 | mode = IOPC_TM_LOW; |
81 | level_triggered = 1; | 81 | level_triggered = 1; |
82 | break; | 82 | break; |
83 | case IRQT_RISING: | 83 | case IRQ_TYPE_EDGE_RISING: |
84 | mode = IOPC_TM_RISING; | 84 | mode = IOPC_TM_RISING; |
85 | break; | 85 | break; |
86 | case IRQT_FALLING: | 86 | case IRQ_TYPE_EDGE_FALLING: |
87 | mode = IOPC_TM_FALLING; | 87 | mode = IOPC_TM_FALLING; |
88 | break; | 88 | break; |
89 | case IRQT_BOTHEDGE: | 89 | case IRQ_TYPE_EDGE_BOTH: |
90 | mode = IOPC_TM_EDGE; | 90 | mode = IOPC_TM_EDGE; |
91 | break; | 91 | break; |
92 | default: | 92 | default: |
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index fd7537f7d11e..99d4fb19a08a 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c | |||
@@ -99,19 +99,19 @@ netx_hif_irq_type(unsigned int _irq, unsigned int type) | |||
99 | 99 | ||
100 | irq = _irq - NETX_IRQ_HIF_CHAINED(0); | 100 | irq = _irq - NETX_IRQ_HIF_CHAINED(0); |
101 | 101 | ||
102 | if (type & __IRQT_RISEDGE) { | 102 | if (type & IRQ_TYPE_EDGE_RISING) { |
103 | DEBUG_IRQ("rising edges\n"); | 103 | DEBUG_IRQ("rising edges\n"); |
104 | val |= (1 << 26) << irq; | 104 | val |= (1 << 26) << irq; |
105 | } | 105 | } |
106 | if (type & __IRQT_FALEDGE) { | 106 | if (type & IRQ_TYPE_EDGE_FALLING) { |
107 | DEBUG_IRQ("falling edges\n"); | 107 | DEBUG_IRQ("falling edges\n"); |
108 | val &= ~((1 << 26) << irq); | 108 | val &= ~((1 << 26) << irq); |
109 | } | 109 | } |
110 | if (type & __IRQT_LOWLVL) { | 110 | if (type & IRQ_TYPE_LEVEL_LOW) { |
111 | DEBUG_IRQ("low level\n"); | 111 | DEBUG_IRQ("low level\n"); |
112 | val &= ~((1 << 26) << irq); | 112 | val &= ~((1 << 26) << irq); |
113 | } | 113 | } |
114 | if (type & __IRQT_HIGHLVL) { | 114 | if (type & IRQ_TYPE_LEVEL_HIGH) { |
115 | DEBUG_IRQ("high level\n"); | 115 | DEBUG_IRQ("high level\n"); |
116 | val |= (1 << 26) << irq; | 116 | val |= (1 << 26) << irq; |
117 | } | 117 | } |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 845c66371ca3..41f94f6fc15c 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
@@ -288,7 +288,7 @@ static void __init osk_init_cf(void) | |||
288 | return; | 288 | return; |
289 | } | 289 | } |
290 | /* the CF I/O IRQ is really active-low */ | 290 | /* the CF I/O IRQ is really active-low */ |
291 | set_irq_type(OMAP_GPIO_IRQ(62), IRQT_FALLING); | 291 | set_irq_type(OMAP_GPIO_IRQ(62), IRQ_TYPE_EDGE_FALLING); |
292 | } | 292 | } |
293 | 293 | ||
294 | static void __init osk_init_irq(void) | 294 | static void __init osk_init_irq(void) |
@@ -483,7 +483,7 @@ static void __init osk_mistral_init(void) | |||
483 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ | 483 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ |
484 | gpio_request(4, "ts_int"); | 484 | gpio_request(4, "ts_int"); |
485 | gpio_direction_input(4); | 485 | gpio_direction_input(4); |
486 | set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING); | 486 | set_irq_type(OMAP_GPIO_IRQ(4), IRQ_TYPE_EDGE_FALLING); |
487 | 487 | ||
488 | spi_register_board_info(mistral_boardinfo, | 488 | spi_register_board_info(mistral_boardinfo, |
489 | ARRAY_SIZE(mistral_boardinfo)); | 489 | ARRAY_SIZE(mistral_boardinfo)); |
@@ -494,7 +494,7 @@ static void __init osk_mistral_init(void) | |||
494 | int ret = 0; | 494 | int ret = 0; |
495 | 495 | ||
496 | gpio_direction_input(OMAP_MPUIO(2)); | 496 | gpio_direction_input(OMAP_MPUIO(2)); |
497 | set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQT_RISING); | 497 | set_irq_type(OMAP_GPIO_IRQ(OMAP_MPUIO(2)), IRQ_TYPE_EDGE_RISING); |
498 | #ifdef CONFIG_PM | 498 | #ifdef CONFIG_PM |
499 | /* share the IRQ in case someone wants to use the | 499 | /* share the IRQ in case someone wants to use the |
500 | * button for more than wakeup from system sleep. | 500 | * button for more than wakeup from system sleep. |
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index e020c2774606..34389b63b0ec 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
@@ -298,11 +298,11 @@ palmz71_powercable(int irq, void *dev_id) | |||
298 | if (omap_get_gpio_datain(PALMZ71_USBDETECT_GPIO)) { | 298 | if (omap_get_gpio_datain(PALMZ71_USBDETECT_GPIO)) { |
299 | printk(KERN_INFO "PM: Power cable connected\n"); | 299 | printk(KERN_INFO "PM: Power cable connected\n"); |
300 | set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), | 300 | set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), |
301 | IRQT_FALLING); | 301 | IRQ_TYPE_EDGE_FALLING); |
302 | } else { | 302 | } else { |
303 | printk(KERN_INFO "PM: Power cable disconnected\n"); | 303 | printk(KERN_INFO "PM: Power cable disconnected\n"); |
304 | set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), | 304 | set_irq_type(OMAP_GPIO_IRQ(PALMZ71_USBDETECT_GPIO), |
305 | IRQT_RISING); | 305 | IRQ_TYPE_EDGE_RISING); |
306 | } | 306 | } |
307 | return IRQ_HANDLED; | 307 | return IRQ_HANDLED; |
308 | } | 308 | } |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index 5c00b3f39cdd..8948d45a2769 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
@@ -186,10 +186,10 @@ static void __init voiceblue_init(void) | |||
186 | omap_request_gpio(13); | 186 | omap_request_gpio(13); |
187 | omap_request_gpio(14); | 187 | omap_request_gpio(14); |
188 | omap_request_gpio(15); | 188 | omap_request_gpio(15); |
189 | set_irq_type(OMAP_GPIO_IRQ(12), IRQT_RISING); | 189 | set_irq_type(OMAP_GPIO_IRQ(12), IRQ_TYPE_EDGE_RISING); |
190 | set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING); | 190 | set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING); |
191 | set_irq_type(OMAP_GPIO_IRQ(14), IRQT_RISING); | 191 | set_irq_type(OMAP_GPIO_IRQ(14), IRQ_TYPE_EDGE_RISING); |
192 | set_irq_type(OMAP_GPIO_IRQ(15), IRQT_RISING); | 192 | set_irq_type(OMAP_GPIO_IRQ(15), IRQ_TYPE_EDGE_RISING); |
193 | 193 | ||
194 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); | 194 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); |
195 | omap_board_config = voiceblue_config; | 195 | omap_board_config = voiceblue_config; |
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 0cf62ef5ecb7..d963125ed755 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c | |||
@@ -181,7 +181,7 @@ void omap1510_fpga_init_irq(void) | |||
181 | */ | 181 | */ |
182 | omap_request_gpio(13); | 182 | omap_request_gpio(13); |
183 | omap_set_gpio_direction(13, 1); | 183 | omap_set_gpio_direction(13, 1); |
184 | set_irq_type(OMAP_GPIO_IRQ(13), IRQT_RISING); | 184 | set_irq_type(OMAP_GPIO_IRQ(13), IRQ_TYPE_EDGE_RISING); |
185 | set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); | 185 | set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); |
186 | } | 186 | } |
187 | 187 | ||
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 620fa0f120ee..870b34972d3b 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
@@ -337,17 +337,17 @@ static void __init apollon_sw_init(void) | |||
337 | omap_request_gpio(SW_DOWN_GPIO58); | 337 | omap_request_gpio(SW_DOWN_GPIO58); |
338 | omap_set_gpio_direction(SW_DOWN_GPIO58, 1); | 338 | omap_set_gpio_direction(SW_DOWN_GPIO58, 1); |
339 | 339 | ||
340 | set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQT_RISING); | 340 | set_irq_type(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), IRQ_TYPE_EDGE_RISING); |
341 | if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt, | 341 | if (request_irq(OMAP_GPIO_IRQ(SW_ENTER_GPIO16), &apollon_sw_interrupt, |
342 | IRQF_SHARED, "enter sw", | 342 | IRQF_SHARED, "enter sw", |
343 | &apollon_sw_interrupt)) | 343 | &apollon_sw_interrupt)) |
344 | return; | 344 | return; |
345 | set_irq_type(OMAP_GPIO_IRQ(SW_UP_GPIO17), IRQT_RISING); | 345 | set_irq_type(OMAP_GPIO_IRQ(SW_UP_GPIO17), IRQ_TYPE_EDGE_RISING); |
346 | if (request_irq(OMAP_GPIO_IRQ(SW_UP_GPIO17), &apollon_sw_interrupt, | 346 | if (request_irq(OMAP_GPIO_IRQ(SW_UP_GPIO17), &apollon_sw_interrupt, |
347 | IRQF_SHARED, "up sw", | 347 | IRQF_SHARED, "up sw", |
348 | &apollon_sw_interrupt)) | 348 | &apollon_sw_interrupt)) |
349 | return; | 349 | return; |
350 | set_irq_type(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), IRQT_RISING); | 350 | set_irq_type(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), IRQ_TYPE_EDGE_RISING); |
351 | if (request_irq(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), &apollon_sw_interrupt, | 351 | if (request_irq(OMAP_GPIO_IRQ(SW_DOWN_GPIO58), &apollon_sw_interrupt, |
352 | IRQF_SHARED, "down sw", | 352 | IRQF_SHARED, "down sw", |
353 | &apollon_sw_interrupt)) | 353 | &apollon_sw_interrupt)) |
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 88405e74e5e3..40a0bee4fbb3 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
@@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void) | |||
213 | pin = DB88F5281_PCI_SLOT0_IRQ_PIN; | 213 | pin = DB88F5281_PCI_SLOT0_IRQ_PIN; |
214 | if (gpio_request(pin, "PCI Int1") == 0) { | 214 | if (gpio_request(pin, "PCI Int1") == 0) { |
215 | if (gpio_direction_input(pin) == 0) { | 215 | if (gpio_direction_input(pin) == 0) { |
216 | set_irq_type(gpio_to_irq(pin), IRQT_LOW); | 216 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
217 | } else { | 217 | } else { |
218 | printk(KERN_ERR "db88f5281_pci_preinit faield to " | 218 | printk(KERN_ERR "db88f5281_pci_preinit faield to " |
219 | "set_irq_type pin %d\n", pin); | 219 | "set_irq_type pin %d\n", pin); |
@@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void) | |||
226 | pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; | 226 | pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; |
227 | if (gpio_request(pin, "PCI Int2") == 0) { | 227 | if (gpio_request(pin, "PCI Int2") == 0) { |
228 | if (gpio_direction_input(pin) == 0) { | 228 | if (gpio_direction_input(pin) == 0) { |
229 | set_irq_type(gpio_to_irq(pin), IRQT_LOW); | 229 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
230 | } else { | 230 | } else { |
231 | printk(KERN_ERR "db88f5281_pci_preinit faield " | 231 | printk(KERN_ERR "db88f5281_pci_preinit faield " |
232 | "to set_irq_type pin %d\n", pin); | 232 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index e2a0084ab4a3..9ae3f6dc7839 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
@@ -91,27 +91,27 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type) | |||
91 | desc = irq_desc + irq; | 91 | desc = irq_desc + irq; |
92 | 92 | ||
93 | switch (type) { | 93 | switch (type) { |
94 | case IRQT_HIGH: | 94 | case IRQ_TYPE_LEVEL_HIGH: |
95 | desc->handle_irq = handle_level_irq; | 95 | desc->handle_irq = handle_level_irq; |
96 | desc->status |= IRQ_LEVEL; | 96 | desc->status |= IRQ_LEVEL; |
97 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); | 97 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
98 | break; | 98 | break; |
99 | case IRQT_LOW: | 99 | case IRQ_TYPE_LEVEL_LOW: |
100 | desc->handle_irq = handle_level_irq; | 100 | desc->handle_irq = handle_level_irq; |
101 | desc->status |= IRQ_LEVEL; | 101 | desc->status |= IRQ_LEVEL; |
102 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); | 102 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
103 | break; | 103 | break; |
104 | case IRQT_RISING: | 104 | case IRQ_TYPE_EDGE_RISING: |
105 | desc->handle_irq = handle_edge_irq; | 105 | desc->handle_irq = handle_edge_irq; |
106 | desc->status &= ~IRQ_LEVEL; | 106 | desc->status &= ~IRQ_LEVEL; |
107 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); | 107 | orion5x_clrbits(GPIO_IN_POL, (1 << pin)); |
108 | break; | 108 | break; |
109 | case IRQT_FALLING: | 109 | case IRQ_TYPE_EDGE_FALLING: |
110 | desc->handle_irq = handle_edge_irq; | 110 | desc->handle_irq = handle_edge_irq; |
111 | desc->status &= ~IRQ_LEVEL; | 111 | desc->status &= ~IRQ_LEVEL; |
112 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); | 112 | orion5x_setbits(GPIO_IN_POL, (1 << pin)); |
113 | break; | 113 | break; |
114 | case IRQT_BOTHEDGE: | 114 | case IRQ_TYPE_EDGE_BOTH: |
115 | desc->handle_irq = handle_edge_irq; | 115 | desc->handle_irq = handle_edge_irq; |
116 | desc->status &= ~IRQ_LEVEL; | 116 | desc->status &= ~IRQ_LEVEL; |
117 | /* | 117 | /* |
@@ -156,7 +156,7 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
156 | if (cause & (1 << pin)) { | 156 | if (cause & (1 << pin)) { |
157 | irq = gpio_to_irq(pin); | 157 | irq = gpio_to_irq(pin); |
158 | desc = irq_desc + irq; | 158 | desc = irq_desc + irq; |
159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { | 159 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
160 | /* Swap polarity (race with GPIO line) */ | 160 | /* Swap polarity (race with GPIO line) */ |
161 | u32 polarity = readl(GPIO_IN_POL); | 161 | u32 polarity = readl(GPIO_IN_POL); |
162 | polarity ^= 1 << pin; | 162 | polarity ^= 1 << pin; |
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 10ae62864269..2a46d27209c1 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
@@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void) | |||
148 | pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; | 148 | pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; |
149 | if (gpio_request(pin, "PCI IntA") == 0) { | 149 | if (gpio_request(pin, "PCI IntA") == 0) { |
150 | if (gpio_direction_input(pin) == 0) { | 150 | if (gpio_direction_input(pin) == 0) { |
151 | set_irq_type(gpio_to_irq(pin), IRQT_LOW); | 151 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
152 | } else { | 152 | } else { |
153 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " | 153 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " |
154 | "set_irq_type pin %d\n", pin); | 154 | "set_irq_type pin %d\n", pin); |
@@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void) | |||
161 | pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; | 161 | pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; |
162 | if (gpio_request(pin, "PCI IntB") == 0) { | 162 | if (gpio_request(pin, "PCI IntB") == 0) { |
163 | if (gpio_direction_input(pin) == 0) { | 163 | if (gpio_direction_input(pin) == 0) { |
164 | set_irq_type(gpio_to_irq(pin), IRQT_LOW); | 164 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
165 | } else { | 165 | } else { |
166 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " | 166 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " |
167 | "set_irq_type pin %d\n", pin); | 167 | "set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index a9cef9703d5b..f270ada2def9 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
@@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void) | |||
117 | pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; | 117 | pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; |
118 | if (gpio_request(pin, "PCI Int1") == 0) { | 118 | if (gpio_request(pin, "PCI Int1") == 0) { |
119 | if (gpio_direction_input(pin) == 0) { | 119 | if (gpio_direction_input(pin) == 0) { |
120 | set_irq_type(gpio_to_irq(pin), IRQT_LOW); | 120 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
121 | } else { | 121 | } else { |
122 | printk(KERN_ERR "qnap_ts209_pci_preinit failed to " | 122 | printk(KERN_ERR "qnap_ts209_pci_preinit failed to " |
123 | "set_irq_type pin %d\n", pin); | 123 | "set_irq_type pin %d\n", pin); |
@@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void) | |||
131 | pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; | 131 | pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; |
132 | if (gpio_request(pin, "PCI Int2") == 0) { | 132 | if (gpio_request(pin, "PCI Int2") == 0) { |
133 | if (gpio_direction_input(pin) == 0) { | 133 | if (gpio_direction_input(pin) == 0) { |
134 | set_irq_type(gpio_to_irq(pin), IRQT_LOW); | 134 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
135 | } else { | 135 | } else { |
136 | printk(KERN_ERR "qnap_ts209_pci_preinit failed " | 136 | printk(KERN_ERR "qnap_ts209_pci_preinit failed " |
137 | "to set_irq_type pin %d\n", pin); | 137 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index 968d0b027597..5ed67e1947a8 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c | |||
@@ -56,28 +56,28 @@ static void pnx4008_mask_ack_irq(unsigned int irq) | |||
56 | static int pnx4008_set_irq_type(unsigned int irq, unsigned int type) | 56 | static int pnx4008_set_irq_type(unsigned int irq, unsigned int type) |
57 | { | 57 | { |
58 | switch (type) { | 58 | switch (type) { |
59 | case IRQT_RISING: | 59 | case IRQ_TYPE_EDGE_RISING: |
60 | __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ | 60 | __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ |
61 | __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ | 61 | __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ |
62 | set_irq_handler(irq, handle_edge_irq); | 62 | set_irq_handler(irq, handle_edge_irq); |
63 | break; | 63 | break; |
64 | case IRQT_FALLING: | 64 | case IRQ_TYPE_EDGE_FALLING: |
65 | __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ | 65 | __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ |
66 | __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ | 66 | __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ |
67 | set_irq_handler(irq, handle_edge_irq); | 67 | set_irq_handler(irq, handle_edge_irq); |
68 | break; | 68 | break; |
69 | case IRQT_LOW: | 69 | case IRQ_TYPE_LEVEL_LOW: |
70 | __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ | 70 | __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ |
71 | __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ | 71 | __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ |
72 | set_irq_handler(irq, handle_level_irq); | 72 | set_irq_handler(irq, handle_level_irq); |
73 | break; | 73 | break; |
74 | case IRQT_HIGH: | 74 | case IRQ_TYPE_LEVEL_HIGH: |
75 | __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ | 75 | __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ |
76 | __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ | 76 | __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ |
77 | set_irq_handler(irq, handle_level_irq); | 77 | set_irq_handler(irq, handle_level_irq); |
78 | break; | 78 | break; |
79 | 79 | ||
80 | /* IRQT_BOTHEDGE is not supported */ | 80 | /* IRQ_TYPE_EDGE_BOTH is not supported */ |
81 | default: | 81 | default: |
82 | printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type); | 82 | printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type); |
83 | return -1; | 83 | return -1; |
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c index bcf0cde6ccc9..31f5bd411ced 100644 --- a/arch/arm/mach-pxa/cm-x270-pci.c +++ b/arch/arm/mach-pxa/cm-x270-pci.c | |||
@@ -71,7 +71,7 @@ void __cmx270_pci_init_irq(int irq_gpio) | |||
71 | 71 | ||
72 | cmx270_it8152_irq_gpio = irq_gpio; | 72 | cmx270_it8152_irq_gpio = irq_gpio; |
73 | 73 | ||
74 | set_irq_type(gpio_to_irq(irq_gpio), IRQT_RISING); | 74 | set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); |
75 | 75 | ||
76 | set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux); | 76 | set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx270_it8152_irq_demux); |
77 | } | 77 | } |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index cc1c4fa06145..8d1ab54e7b20 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
@@ -113,7 +113,7 @@ static void __init lpd270_init_irq(void) | |||
113 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 113 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
114 | } | 114 | } |
115 | set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); | 115 | set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); |
116 | set_irq_type(IRQ_GPIO(0), IRQT_FALLING); | 116 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
117 | } | 117 | } |
118 | 118 | ||
119 | 119 | ||
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index ac26423cd20c..af7375bb46a4 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
@@ -152,7 +152,7 @@ static void __init lubbock_init_irq(void) | |||
152 | } | 152 | } |
153 | 153 | ||
154 | set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); | 154 | set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); |
155 | set_irq_type(IRQ_GPIO(0), IRQT_FALLING); | 155 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
156 | } | 156 | } |
157 | 157 | ||
158 | #ifdef CONFIG_PM | 158 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 851ec2d9b699..c8e38b5ff1c4 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
@@ -191,7 +191,7 @@ static void __init mainstone_init_irq(void) | |||
191 | MST_INTSETCLR = 0; | 191 | MST_INTSETCLR = 0; |
192 | 192 | ||
193 | set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); | 193 | set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); |
194 | set_irq_type(IRQ_GPIO(0), IRQT_FALLING); | 194 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
195 | } | 195 | } |
196 | 196 | ||
197 | #ifdef CONFIG_PM | 197 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 34cd585075b0..23e9b9283301 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c | |||
@@ -146,18 +146,18 @@ void sharpsl_pm_pxa_init(void) | |||
146 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED, "AC Input Detect", sharpsl_ac_isr)) { | 146 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED, "AC Input Detect", sharpsl_ac_isr)) { |
147 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin)); | 147 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin)); |
148 | } | 148 | } |
149 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQT_BOTHEDGE); | 149 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin),IRQ_TYPE_EDGE_BOTH); |
150 | 150 | ||
151 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED, "Battery Cover", sharpsl_fatal_isr)) { | 151 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED, "Battery Cover", sharpsl_fatal_isr)) { |
152 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock)); | 152 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock)); |
153 | } | 153 | } |
154 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQT_FALLING); | 154 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock),IRQ_TYPE_EDGE_FALLING); |
155 | 155 | ||
156 | if (sharpsl_pm.machinfo->gpio_fatal) { | 156 | if (sharpsl_pm.machinfo->gpio_fatal) { |
157 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED, "Fatal Battery", sharpsl_fatal_isr)) { | 157 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED, "Fatal Battery", sharpsl_fatal_isr)) { |
158 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal)); | 158 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal)); |
159 | } | 159 | } |
160 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQT_FALLING); | 160 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal),IRQ_TYPE_EDGE_FALLING); |
161 | } | 161 | } |
162 | 162 | ||
163 | if (sharpsl_pm.machinfo->batfull_irq) | 163 | if (sharpsl_pm.machinfo->batfull_irq) |
@@ -166,7 +166,7 @@ void sharpsl_pm_pxa_init(void) | |||
166 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED, "CO", sharpsl_chrg_full_isr)) { | 166 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED, "CO", sharpsl_chrg_full_isr)) { |
167 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull)); | 167 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull)); |
168 | } | 168 | } |
169 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQT_RISING); | 169 | else set_irq_type(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull),IRQ_TYPE_EDGE_RISING); |
170 | } | 170 | } |
171 | } | 171 | } |
172 | 172 | ||
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index dee7bf36f013..12811b7aea07 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
@@ -122,7 +122,7 @@ static struct resource dm9000_resources[] = { | |||
122 | [2] = { | 122 | [2] = { |
123 | .start = TRIZEPS4_ETH_IRQ, | 123 | .start = TRIZEPS4_ETH_IRQ, |
124 | .end = TRIZEPS4_ETH_IRQ, | 124 | .end = TRIZEPS4_ETH_IRQ, |
125 | .flags = (IORESOURCE_IRQ | IRQT_RISING), | 125 | .flags = (IORESOURCE_IRQ | IRQ_TYPE_EDGE_RISING), |
126 | }, | 126 | }, |
127 | }; | 127 | }; |
128 | 128 | ||
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 31afe50d7cd5..56d3ee01baae 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c | |||
@@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = { | |||
96 | static void __init cerf_init_irq(void) | 96 | static void __init cerf_init_irq(void) |
97 | { | 97 | { |
98 | sa1100_init_irq(); | 98 | sa1100_init_irq(); |
99 | set_irq_type(CERF_ETH_IRQ, IRQT_RISING); | 99 | set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); |
100 | } | 100 | } |
101 | 101 | ||
102 | static struct map_desc cerf_io_desc[] __initdata = { | 102 | static struct map_desc cerf_io_desc[] __initdata = { |
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index 8473c37b77d6..b34ff42bbd75 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c | |||
@@ -834,7 +834,7 @@ static void __init h3800_init_irq(void) | |||
834 | set_irq_chip(irq, &h3800_gpio_irqchip); | 834 | set_irq_chip(irq, &h3800_gpio_irqchip); |
835 | } | 835 | } |
836 | #endif | 836 | #endif |
837 | set_irq_type(IRQ_GPIO_H3800_ASIC, IRQT_RISING); | 837 | set_irq_type(IRQ_GPIO_H3800_ASIC, IRQ_TYPE_EDGE_RISING); |
838 | set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux); | 838 | set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux); |
839 | } | 839 | } |
840 | 840 | ||
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index fa0403af7eec..c5e438b12ec7 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c | |||
@@ -46,17 +46,17 @@ static int sa1100_gpio_type(unsigned int irq, unsigned int type) | |||
46 | else | 46 | else |
47 | mask = GPIO11_27_MASK(irq); | 47 | mask = GPIO11_27_MASK(irq); |
48 | 48 | ||
49 | if (type == IRQT_PROBE) { | 49 | if (type == IRQ_TYPE_PROBE) { |
50 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) | 50 | if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) |
51 | return 0; | 51 | return 0; |
52 | type = __IRQT_RISEDGE | __IRQT_FALEDGE; | 52 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
53 | } | 53 | } |
54 | 54 | ||
55 | if (type & __IRQT_RISEDGE) { | 55 | if (type & IRQ_TYPE_EDGE_RISING) { |
56 | GPIO_IRQ_rising_edge |= mask; | 56 | GPIO_IRQ_rising_edge |= mask; |
57 | } else | 57 | } else |
58 | GPIO_IRQ_rising_edge &= ~mask; | 58 | GPIO_IRQ_rising_edge &= ~mask; |
59 | if (type & __IRQT_FALEDGE) { | 59 | if (type & IRQ_TYPE_EDGE_FALLING) { |
60 | GPIO_IRQ_falling_edge |= mask; | 60 | GPIO_IRQ_falling_edge |= mask; |
61 | } else | 61 | } else |
62 | GPIO_IRQ_falling_edge &= ~mask; | 62 | GPIO_IRQ_falling_edge &= ~mask; |
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 9f1ed1509301..967a48454f6b 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c | |||
@@ -151,7 +151,7 @@ static int __devinit neponset_probe(struct platform_device *dev) | |||
151 | /* | 151 | /* |
152 | * Install handler for GPIO25. | 152 | * Install handler for GPIO25. |
153 | */ | 153 | */ |
154 | set_irq_type(IRQ_GPIO25, IRQT_RISING); | 154 | set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); |
155 | set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); | 155 | set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); |
156 | 156 | ||
157 | /* | 157 | /* |
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index c7bf7e0038f0..69a71f11625e 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c | |||
@@ -143,7 +143,7 @@ static void __init pleb_map_io(void) | |||
143 | 143 | ||
144 | GPDR &= ~GPIO_ETH0_IRQ; | 144 | GPDR &= ~GPIO_ETH0_IRQ; |
145 | 145 | ||
146 | set_irq_type(GPIO_ETH0_IRQ, IRQT_FALLING); | 146 | set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); |
147 | } | 147 | } |
148 | 148 | ||
149 | MACHINE_START(PLEB, "PLEB") | 149 | MACHINE_START(PLEB, "PLEB") |
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 4a7736717d86..318b268f938e 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
@@ -73,19 +73,19 @@ static int gpio_set_irq_type(u32 irq, u32 type) | |||
73 | void __iomem *reg = port->base; | 73 | void __iomem *reg = port->base; |
74 | 74 | ||
75 | switch (type) { | 75 | switch (type) { |
76 | case IRQT_RISING: | 76 | case IRQ_TYPE_EDGE_RISING: |
77 | edge = GPIO_INT_RISE_EDGE; | 77 | edge = GPIO_INT_RISE_EDGE; |
78 | break; | 78 | break; |
79 | case IRQT_FALLING: | 79 | case IRQ_TYPE_EDGE_FALLING: |
80 | edge = GPIO_INT_FALL_EDGE; | 80 | edge = GPIO_INT_FALL_EDGE; |
81 | break; | 81 | break; |
82 | case IRQT_LOW: | 82 | case IRQ_TYPE_LEVEL_LOW: |
83 | edge = GPIO_INT_LOW_LEV; | 83 | edge = GPIO_INT_LOW_LEV; |
84 | break; | 84 | break; |
85 | case IRQT_HIGH: | 85 | case IRQ_TYPE_LEVEL_HIGH: |
86 | edge = GPIO_INT_HIGH_LEV; | 86 | edge = GPIO_INT_HIGH_LEV; |
87 | break; | 87 | break; |
88 | default: /* this includes IRQT_BOTHEDGE */ | 88 | default: /* this includes IRQ_TYPE_EDGE_BOTH */ |
89 | return -EINVAL; | 89 | return -EINVAL; |
90 | } | 90 | } |
91 | 91 | ||
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index d8e9c2c3f0f6..63e094342ef6 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
@@ -517,13 +517,13 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, | |||
517 | u32 gpio_bit = 1 << gpio; | 517 | u32 gpio_bit = 1 << gpio; |
518 | 518 | ||
519 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, | 519 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, |
520 | trigger & __IRQT_LOWLVL); | 520 | trigger & IRQ_TYPE_LEVEL_LOW); |
521 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, | 521 | MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, |
522 | trigger & __IRQT_HIGHLVL); | 522 | trigger & IRQ_TYPE_LEVEL_HIGH); |
523 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, | 523 | MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, |
524 | trigger & __IRQT_RISEDGE); | 524 | trigger & IRQ_TYPE_EDGE_RISING); |
525 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, | 525 | MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, |
526 | trigger & __IRQT_FALEDGE); | 526 | trigger & IRQ_TYPE_EDGE_FALLING); |
527 | 527 | ||
528 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { | 528 | if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { |
529 | if (trigger != 0) | 529 | if (trigger != 0) |
@@ -555,9 +555,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
555 | case METHOD_MPUIO: | 555 | case METHOD_MPUIO: |
556 | reg += OMAP_MPUIO_GPIO_INT_EDGE; | 556 | reg += OMAP_MPUIO_GPIO_INT_EDGE; |
557 | l = __raw_readl(reg); | 557 | l = __raw_readl(reg); |
558 | if (trigger & __IRQT_RISEDGE) | 558 | if (trigger & IRQ_TYPE_EDGE_RISING) |
559 | l |= 1 << gpio; | 559 | l |= 1 << gpio; |
560 | else if (trigger & __IRQT_FALEDGE) | 560 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
561 | l &= ~(1 << gpio); | 561 | l &= ~(1 << gpio); |
562 | else | 562 | else |
563 | goto bad; | 563 | goto bad; |
@@ -567,9 +567,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
567 | case METHOD_GPIO_1510: | 567 | case METHOD_GPIO_1510: |
568 | reg += OMAP1510_GPIO_INT_CONTROL; | 568 | reg += OMAP1510_GPIO_INT_CONTROL; |
569 | l = __raw_readl(reg); | 569 | l = __raw_readl(reg); |
570 | if (trigger & __IRQT_RISEDGE) | 570 | if (trigger & IRQ_TYPE_EDGE_RISING) |
571 | l |= 1 << gpio; | 571 | l |= 1 << gpio; |
572 | else if (trigger & __IRQT_FALEDGE) | 572 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
573 | l &= ~(1 << gpio); | 573 | l &= ~(1 << gpio); |
574 | else | 574 | else |
575 | goto bad; | 575 | goto bad; |
@@ -584,9 +584,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
584 | gpio &= 0x07; | 584 | gpio &= 0x07; |
585 | l = __raw_readl(reg); | 585 | l = __raw_readl(reg); |
586 | l &= ~(3 << (gpio << 1)); | 586 | l &= ~(3 << (gpio << 1)); |
587 | if (trigger & __IRQT_RISEDGE) | 587 | if (trigger & IRQ_TYPE_EDGE_RISING) |
588 | l |= 2 << (gpio << 1); | 588 | l |= 2 << (gpio << 1); |
589 | if (trigger & __IRQT_FALEDGE) | 589 | if (trigger & IRQ_TYPE_EDGE_FALLING) |
590 | l |= 1 << (gpio << 1); | 590 | l |= 1 << (gpio << 1); |
591 | if (trigger) | 591 | if (trigger) |
592 | /* Enable wake-up during idle for dynamic tick */ | 592 | /* Enable wake-up during idle for dynamic tick */ |
@@ -599,9 +599,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
599 | case METHOD_GPIO_730: | 599 | case METHOD_GPIO_730: |
600 | reg += OMAP730_GPIO_INT_CONTROL; | 600 | reg += OMAP730_GPIO_INT_CONTROL; |
601 | l = __raw_readl(reg); | 601 | l = __raw_readl(reg); |
602 | if (trigger & __IRQT_RISEDGE) | 602 | if (trigger & IRQ_TYPE_EDGE_RISING) |
603 | l |= 1 << gpio; | 603 | l |= 1 << gpio; |
604 | else if (trigger & __IRQT_FALEDGE) | 604 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
605 | l &= ~(1 << gpio); | 605 | l &= ~(1 << gpio); |
606 | else | 606 | else |
607 | goto bad; | 607 | goto bad; |
@@ -887,7 +887,7 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio) | |||
887 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); | 887 | _set_gpio_direction(bank, get_gpio_index(gpio), 1); |
888 | _set_gpio_irqenable(bank, gpio, 0); | 888 | _set_gpio_irqenable(bank, gpio, 0); |
889 | _clear_gpio_irqstatus(bank, gpio); | 889 | _clear_gpio_irqstatus(bank, gpio); |
890 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); | 890 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
891 | } | 891 | } |
892 | 892 | ||
893 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ | 893 | /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ |
@@ -924,7 +924,7 @@ int omap_request_gpio(int gpio) | |||
924 | /* Set trigger to none. You need to enable the desired trigger with | 924 | /* Set trigger to none. You need to enable the desired trigger with |
925 | * request_irq() or set_irq_type(). | 925 | * request_irq() or set_irq_type(). |
926 | */ | 926 | */ |
927 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); | 927 | _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE); |
928 | 928 | ||
929 | #ifdef CONFIG_ARCH_OMAP15XX | 929 | #ifdef CONFIG_ARCH_OMAP15XX |
930 | if (bank->method == METHOD_GPIO_1510) { | 930 | if (bank->method == METHOD_GPIO_1510) { |
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index ae2c5d7efc9d..001436c04b13 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
@@ -292,27 +292,27 @@ s3c_irqext_type(unsigned int irq, unsigned int type) | |||
292 | /* Set the external interrupt to pointed trigger type */ | 292 | /* Set the external interrupt to pointed trigger type */ |
293 | switch (type) | 293 | switch (type) |
294 | { | 294 | { |
295 | case IRQT_NOEDGE: | 295 | case IRQ_TYPE_NONE: |
296 | printk(KERN_WARNING "No edge setting!\n"); | 296 | printk(KERN_WARNING "No edge setting!\n"); |
297 | break; | 297 | break; |
298 | 298 | ||
299 | case IRQT_RISING: | 299 | case IRQ_TYPE_EDGE_RISING: |
300 | newvalue = S3C2410_EXTINT_RISEEDGE; | 300 | newvalue = S3C2410_EXTINT_RISEEDGE; |
301 | break; | 301 | break; |
302 | 302 | ||
303 | case IRQT_FALLING: | 303 | case IRQ_TYPE_EDGE_FALLING: |
304 | newvalue = S3C2410_EXTINT_FALLEDGE; | 304 | newvalue = S3C2410_EXTINT_FALLEDGE; |
305 | break; | 305 | break; |
306 | 306 | ||
307 | case IRQT_BOTHEDGE: | 307 | case IRQ_TYPE_EDGE_BOTH: |
308 | newvalue = S3C2410_EXTINT_BOTHEDGE; | 308 | newvalue = S3C2410_EXTINT_BOTHEDGE; |
309 | break; | 309 | break; |
310 | 310 | ||
311 | case IRQT_LOW: | 311 | case IRQ_TYPE_LEVEL_LOW: |
312 | newvalue = S3C2410_EXTINT_LOWLEV; | 312 | newvalue = S3C2410_EXTINT_LOWLEV; |
313 | break; | 313 | break; |
314 | 314 | ||
315 | case IRQT_HIGH: | 315 | case IRQ_TYPE_LEVEL_HIGH: |
316 | newvalue = S3C2410_EXTINT_HILEV; | 316 | newvalue = S3C2410_EXTINT_HILEV; |
317 | break; | 317 | break; |
318 | 318 | ||