606 files changed, 20390 insertions, 7918 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 28f93a6c0fde..943fe6930f77 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -1,7 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
 config ALPHA
         bool
         default y
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf7273f3dc64..db524e75c4a2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux Kernel Configuration"
-
 config ARM
         bool
         default y
@@ -13,7 +6,7 @@ config ARM
         select HAVE_MEMBLOCK
         select RTC_LIB
         select SYS_SUPPORTS_APM_EMULATION
-        select GENERIC_ATOMIC64 if (!CPU_32v6K)
+        select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
         select HAVE_ARCH_KGDB
         select HAVE_KPROBES if (!XIP_KERNEL)
@@ -653,7 +646,7 @@ config ARCH_S3C2410
         select ARCH_HAS_CPUFREQ
         select HAVE_CLK
         select ARCH_USES_GETTIMEOFFSET
-        select HAVE_S3C2410_I2C
+        select HAVE_S3C2410_I2C if I2C
         help
           Samsung S3C2410X CPU based systems, such as the Simtec Electronics
           BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
@@ -683,8 +676,8 @@ config ARCH_S3C64XX
         select S3C_DEV_NAND
         select USB_ARCH_HAS_OHCI
         select SAMSUNG_GPIOLIB_4BIT
-        select HAVE_S3C2410_I2C
-        select HAVE_S3C2410_WATCHDOG
+        select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
           Samsung S3C64XX series based systems
 
@@ -693,10 +686,10 @@ config ARCH_S5P64X0
         select CPU_V6
         select GENERIC_GPIO
         select HAVE_CLK
-        select HAVE_S3C2410_WATCHDOG
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select ARCH_USES_GETTIMEOFFSET
-        select HAVE_S3C2410_I2C
-        select HAVE_S3C_RTC
+        select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C_RTC if RTC_CLASS
         help
           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
           SMDK6450.
@@ -707,7 +700,7 @@ config ARCH_S5P6442
         select GENERIC_GPIO
         select HAVE_CLK
         select ARCH_USES_GETTIMEOFFSET
-        select HAVE_S3C2410_WATCHDOG
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
           Samsung S5P6442 CPU based systems
 
@@ -718,31 +711,37 @@ config ARCH_S5PC100
         select CPU_V7
         select ARM_L1_CACHE_SHIFT_6
         select ARCH_USES_GETTIMEOFFSET
-        select HAVE_S3C2410_I2C
-        select HAVE_S3C_RTC
-        select HAVE_S3C2410_WATCHDOG
+        select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C_RTC if RTC_CLASS
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
           Samsung S5PC100 series based systems
 
 config ARCH_S5PV210
         bool "Samsung S5PV210/S5PC110"
         select CPU_V7
+        select ARCH_SPARSEMEM_ENABLE
         select GENERIC_GPIO
         select HAVE_CLK
         select ARM_L1_CACHE_SHIFT_6
+        select ARCH_HAS_CPUFREQ
         select ARCH_USES_GETTIMEOFFSET
-        select HAVE_S3C2410_I2C
-        select HAVE_S3C_RTC
-        select HAVE_S3C2410_WATCHDOG
+        select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C_RTC if RTC_CLASS
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
           Samsung S5PV210/S5PC110 series based systems
 
 config ARCH_S5PV310
         bool "Samsung S5PV310/S5PC210"
         select CPU_V7
+        select ARCH_SPARSEMEM_ENABLE
         select GENERIC_GPIO
         select HAVE_CLK
         select GENERIC_CLOCKEVENTS
+        select HAVE_S3C_RTC if RTC_CLASS
+        select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         help
           Samsung S5PV310 series based systems
 
@@ -1669,6 +1668,12 @@ if ARCH_HAS_CPUFREQ
 
 source "drivers/cpufreq/Kconfig"
 
+config CPU_FREQ_IMX
+        tristate "CPUfreq driver for i.MX CPUs"
+        depends on ARCH_MXC && CPU_FREQ
+        help
+          This enables the CPUfreq driver for i.MX CPUs.
+
 config CPU_FREQ_SA1100
         bool
 
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index ada6359160eb..772f95f1aecd 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -251,15 +251,16 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
                 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 
         /*
-         * Set priority on all interrupts.
+         * Set priority on all global interrupts.
          */
-        for (i = 0; i < max_irq; i += 4)
+        for (i = 32; i < max_irq; i += 4)
                 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 
         /*
-         * Disable all interrupts.
+         * Disable all interrupts.  Leave the PPI and SGIs alone
+         * as these enables are banked registers.
          */
-        for (i = 0; i < max_irq; i += 32)
+        for (i = 32; i < max_irq; i += 32)
                 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 
         /*
@@ -277,11 +278,30 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
 
 void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
 {
+        void __iomem *dist_base;
+        int i;
+
         if (gic_nr >= MAX_GIC_NR)
                 BUG();
 
+        dist_base = gic_data[gic_nr].dist_base;
+        BUG_ON(!dist_base);
+
         gic_data[gic_nr].cpu_base = base;
 
+        /*
+         * Deal with the banked PPI and SGI interrupts - disable all
+         * PPI interrupts, ensure all SGI interrupts are enabled.
+         */
+        writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+        writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+
+        /*
+         * Set priority on PPI and SGI interrupts
+         */
+        for (i = 0; i < 32; i += 4)
+                writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+
         writel(0xf0, base + GIC_CPU_PRIMASK);
         writel(1, base + GIC_CPU_CTRL);
 }
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index 163cfee7644c..5c7a87260fab 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -82,6 +82,7 @@ CONFIG_FEC=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_EVBUG=m
 CONFIG_MOUSE_PS2=m
 CONFIG_MOUSE_PS2_ELANTECH=y
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 6bcba48800fe..cc42d5fdee17 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -21,9 +21,6 @@
 #define __ASM_ARM_HARDWARE_L2X0_H
 
 #define L2X0_CACHE_ID                   0x000
-#define   L2X0_CACHE_ID_PART_MASK       (0xf << 6)
-#define   L2X0_CACHE_ID_PART_L210       (1 << 6)
-#define   L2X0_CACHE_ID_PART_L310       (3 << 6)
 #define L2X0_CACHE_TYPE                 0x004
 #define L2X0_CTRL                       0x100
 #define L2X0_AUX_CTRL                   0x104
@@ -53,6 +50,16 @@
 #define L2X0_LINE_DATA                  0xF10
 #define L2X0_LINE_TAG                   0xF30
 #define L2X0_DEBUG_CTRL                 0xF40
+#define L2X0_PREFETCH_CTRL              0xF60
+#define L2X0_POWER_CTRL                 0xF80
+#define   L2X0_DYNAMIC_CLK_GATING_EN    (1 << 1)
+#define   L2X0_STNDBY_MODE_EN           (1 << 0)
+
+/* Registers shifts and masks */
+#define L2X0_CACHE_ID_PART_MASK         (0xf << 6)
+#define L2X0_CACHE_ID_PART_L210         (1 << 6)
+#define L2X0_CACHE_ID_PART_L310         (3 << 6)
+#define L2X0_AUX_CTRL_WAY_SIZE_MASK     (0x3 << 17)
 
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index 6700c7fc7ebd..21fa272301f8 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -75,7 +75,7 @@ extern unsigned long it8152_base_address;
   IT8152_PD_IRQ(1)  USB (USBR)
   IT8152_PD_IRQ(0)  Audio controller (ACR)
  */
-#define IT8152_IRQ(x)   (IRQ_BOARD_END + (x))
+#define IT8152_IRQ(x)   (IRQ_BOARD_START + (x))
 
 /* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
 #define IT8152_LD_IRQ_COUNT     9
diff --git a/arch/arm/include/asm/kgdb.h b/arch/arm/include/asm/kgdb.h
index 08265993227f..48066ce9ea34 100644
--- a/arch/arm/include/asm/kgdb.h
+++ b/arch/arm/include/asm/kgdb.h
@@ -70,7 +70,8 @@ extern int kgdb_fault_expected;
 #define _GP_REGS                16
 #define _FP_REGS                8
 #define _EXTRA_REGS             2
-#define DBG_MAX_REG_NUM         (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+#define GDB_MAX_REGS            (_GP_REGS + (_FP_REGS * 3) + _EXTRA_REGS)
+#define DBG_MAX_REG_NUM         (_GP_REGS + _FP_REGS + _EXTRA_REGS)
 
 #define KGDB_MAX_NO_CPUS        1
 #define BUFMAX                  400
@@ -93,7 +94,7 @@ extern int kgdb_fault_expected;
 #define _SPT                    13
 #define _LR                     14
 #define _PC                     15
-#define _CPSR                   (DBG_MAX_REG_NUM - 1)
+#define _CPSR                   (GDB_MAX_REGS - 1)
 
 /*
  * So that we can denote the end of a frame for tracing,
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
index fdbc43b2e6c0..b8da2e415e4e 100644
--- a/arch/arm/include/asm/memblock.h
+++ b/arch/arm/include/asm/memblock.h
@@ -1,13 +1,6 @@
 #ifndef _ASM_ARM_MEMBLOCK_H
 #define _ASM_ARM_MEMBLOCK_H
 
-#ifdef CONFIG_MMU
-extern phys_addr_t lowmem_end_addr;
-#define MEMBLOCK_REAL_LIMIT     lowmem_end_addr
-#else
-#define MEMBLOCK_REAL_LIMIT     0
-#endif
-
 struct meminfo;
 struct machine_desc;
 
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 25f76bae57ab..fc1900925275 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -25,6 +25,9 @@ struct outer_cache_fns {
         void (*inv_range)(unsigned long, unsigned long);
         void (*clean_range)(unsigned long, unsigned long);
         void (*flush_range)(unsigned long, unsigned long);
+        void (*flush_all)(void);
+        void (*inv_all)(void);
+        void (*disable)(void);
 #ifdef CONFIG_OUTER_CACHE_SYNC
         void (*sync)(void);
 #endif
@@ -50,6 +53,24 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
                 outer_cache.flush_range(start, end);
 }
 
+static inline void outer_flush_all(void)
+{
+        if (outer_cache.flush_all)
+                outer_cache.flush_all();
+}
+
+static inline void outer_inv_all(void)
+{
+        if (outer_cache.inv_all)
+                outer_cache.inv_all();
+}
+
+static inline void outer_disable(void)
+{
+        if (outer_cache.disable)
+                outer_cache.disable();
+}
+
 #else
 
 static inline void outer_inv_range(unsigned long start, unsigned long end)
@@ -58,6 +79,9 @@ static inline void outer_clean_range(unsigned long start, unsigned long end)
 { }
 static inline void outer_flush_range(unsigned long start, unsigned long end)
 { }
+static inline void outer_flush_all(void) { }
+static inline void outer_inv_all(void) { }
+static inline void outer_disable(void) { }
 
 #endif
 
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 54593b0c241b..21e3a4ab3b8c 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -748,8 +748,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
                 breakpoint_handler(addr, regs);
                 break;
         case ARM_ENTRY_ASYNC_WATCHPOINT:
-                WARN_ON("Asynchronous watchpoint exception taken. "
-                        "Debugging results may be unreliable");
+                WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
         case ARM_ENTRY_SYNC_WATCHPOINT:
                 watchpoint_handler(addr, regs);
                 break;
diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c
index d6e8b4d2e60d..778c2f7024ff 100644
--- a/arch/arm/kernel/kgdb.c
+++ b/arch/arm/kernel/kgdb.c
@@ -79,7 +79,7 @@ sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *task)
                 return;
 
         /* Initialize to zero */
-        for (regno = 0; regno < DBG_MAX_REG_NUM; regno++)
+        for (regno = 0; regno < GDB_MAX_REGS; regno++)
                 gdb_regs[regno] = 0;
 
         /* Otherwise, we have only some registers from switch_to() */
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 1fc74cbd1a19..3a8fd5140d7a 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -78,7 +78,10 @@ void machine_kexec(struct kimage *image)
         local_fiq_disable();
         setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
         flush_cache_all();
+        outer_flush_all();
+        outer_disable();
         cpu_proc_fin();
+        outer_inv_all();
         flush_cache_all();
         cpu_reset(reboot_code_buffer_phys);
 }
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 49643b1467e6..07a50357492a 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -1749,7 +1749,7 @@ static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
 static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
                                         enum armv7_counters counter)
 {
-        int ret;
+        int ret = 0;
 
         if (counter == ARMV7_CYCLE_COUNTER)
                 ret = pmnc & ARMV7_FLAG_C;
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index 20b7411e47fd..c2e112e1a05f 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -28,7 +28,7 @@ int notrace unwind_frame(struct stackframe *frame)
 
         /* only go to a higher address on the stack */
         low = frame->sp;
-        high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
+        high = ALIGN(low, THREAD_SIZE);
 
         /* check current frame pointer is within bounds */
         if (fp < (low + 12) || fp + 4 >= high)
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index cda78d59aa31..446aee97436f 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -53,10 +53,7 @@ static void dump_mem(const char *, const char *, unsigned long, unsigned long);
 void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame)
 {
 #ifdef CONFIG_KALLSYMS
-        char sym1[KSYM_SYMBOL_LEN], sym2[KSYM_SYMBOL_LEN];
-        sprint_symbol(sym1, where);
-        sprint_symbol(sym2, from);
-        printk("[<%08lx>] (%s) from [<%08lx>] (%s)\n", where, sym1, from, sym2);
+        printk("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
 #else
         printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
 #endif
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 2a161765f6d5..d2cb0b3c9872 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -279,7 +279,7 @@ int unwind_frame(struct stackframe *frame)
 
         /* only go to a higher address on the stack */
         low = frame->sp;
-        high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
+        high = ALIGN(low, THREAD_SIZE);
 
         pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__,
                  frame->pc, frame->lr, frame->sp);
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 1953e3d21abf..cead8893b46b 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -113,6 +113,7 @@ SECTIONS
                         *(.rodata.*)
                         *(.glue_7)
                         *(.glue_7t)
+                . = ALIGN(4);
                 *(.got)                 /* Global offset table          */
                         ARM_CPU_KEEP(PROC_INFO)
         }
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index 3a5961d3f3b1..5e31b2b25da9 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -1,5 +1,13 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/dma.h
+/**
+ * DOC: EP93xx DMA M2P memory to peripheral and peripheral to memory engine
+ *
+ * The EP93xx DMA M2P subsystem handles DMA transfers between memory and
+ * peripherals. DMA M2P channels are available for audio, UARTs and IrDA.
+ * See chapter 10 of the EP93xx users guide for full details on the DMA M2P
+ * engine.
+ *
+ * See sound/soc/ep93xx/ep93xx-pcm.c for an example use of the DMA M2P code.
+ *
  */
 
 #ifndef __ASM_ARCH_DMA_H
@@ -8,12 +16,34 @@
 #include <linux/list.h>
 #include <linux/types.h>
 
+/**
+ * struct ep93xx_dma_buffer - Information about a buffer to be transferred
+ * using the DMA M2P engine
+ *
+ * @list: Entry in DMA buffer list
+ * @bus_addr: Physical address of the buffer
+ * @size: Size of the buffer in bytes
+ */
 struct ep93xx_dma_buffer {
         struct list_head        list;
         u32                     bus_addr;
         u16                     size;
 };
 
+/**
+ * struct ep93xx_dma_m2p_client - Information about a DMA M2P client
+ *
+ * @name: Unique name for this client
+ * @flags: Client flags
+ * @cookie: User data to pass to callback functions
+ * @buffer_started: Non NULL function to call when a transfer is started.
+ *                      The arguments are the user data cookie and the DMA
+ *                      buffer which is starting.
+ * @buffer_finished: Non NULL function to call when a transfer is completed.
+ *                      The arguments are the user data cookie, the DMA buffer
+ *                      which has completed, and a boolean flag indicating if
+ *                      the transfer had an error.
+ */
 struct ep93xx_dma_m2p_client {
         char                    *name;
         u8                      flags;
@@ -24,10 +54,11 @@ struct ep93xx_dma_m2p_client {
                                         struct ep93xx_dma_buffer *buf,
                                         int bytes, int error);
 
-        /* Internal to the DMA code.  */
+        /* private: Internal use only */
         void                    *channel;
 };
 
+/* DMA M2P ports */
 #define EP93XX_DMA_M2P_PORT_I2S1        0x00
 #define EP93XX_DMA_M2P_PORT_I2S2        0x01
 #define EP93XX_DMA_M2P_PORT_AAC1        0x02
@@ -39,18 +70,80 @@ struct ep93xx_dma_m2p_client {
 #define EP93XX_DMA_M2P_PORT_UART3       0x08
 #define EP93XX_DMA_M2P_PORT_IRDA        0x09
 #define EP93XX_DMA_M2P_PORT_MASK        0x0f
-#define EP93XX_DMA_M2P_TX               0x00
-#define EP93XX_DMA_M2P_RX               0x10
-#define EP93XX_DMA_M2P_ABORT_ON_ERROR   0x20
-#define EP93XX_DMA_M2P_IGNORE_ERROR     0x40
-#define EP93XX_DMA_M2P_ERROR_MASK       0x60
 
-int  ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
+/* DMA M2P client flags */
+#define EP93XX_DMA_M2P_TX               0x00    /* Memory to peripheral */
+#define EP93XX_DMA_M2P_RX               0x10    /* Peripheral to memory */
+
+/*
+ * DMA M2P client error handling flags. See the EP93xx users guide
+ * documentation on the DMA M2P CONTROL register for more details
+ */
+#define EP93XX_DMA_M2P_ABORT_ON_ERROR   0x20    /* Abort on peripheral error */
+#define EP93XX_DMA_M2P_IGNORE_ERROR     0x40    /* Ignore peripheral errors */
+#define EP93XX_DMA_M2P_ERROR_MASK       0x60    /* Mask of error bits */
+
+/**
+ * ep93xx_dma_m2p_client_register - Register a client with the DMA M2P
+ * subsystem
+ *
+ * @m2p: Client information to register
+ * returns 0 on success
+ *
+ * The DMA M2P subsystem allocates a channel and an interrupt line for the DMA
+ * client
+ */
+int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
+
+/**
+ * ep93xx_dma_m2p_client_unregister - Unregister a client from the DMA M2P
+ * subsystem
+ *
+ * @m2p: Client to unregister
+ *
+ * Any transfers currently in progress will be completed in hardware, but
+ * ignored in software.
+ */
 void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p);
+
+/**
+ * ep93xx_dma_m2p_submit - Submit a DMA M2P transfer
+ *
+ * @m2p: DMA Client to submit the transfer on
+ * @buf: DMA Buffer to submit
+ *
+ * If the current or next transfer positions are free on the M2P client then
+ * the transfer is started immediately. If not, the transfer is added to the
+ * list of pending transfers. This function must not be called from the
+ * buffer_finished callback for an M2P channel.
+ *
+ */
 void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
                            struct ep93xx_dma_buffer *buf);
+
+/**
+ * ep93xx_dma_m2p_submit_recursive - Put a DMA transfer on the pending list
+ * for an M2P channel
+ *
+ * @m2p: DMA Client to submit the transfer on
+ * @buf: DMA Buffer to submit
+ *
+ * This function must only be called from the buffer_finished callback for an
+ * M2P channel. It is commonly used to add the next transfer in a chained list
+ * of DMA transfers.
+ */
 void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p,
                                      struct ep93xx_dma_buffer *buf);
+
+/**
+ * ep93xx_dma_m2p_flush - Flush all pending transfers on a DMA M2P client
+ *
+ * @m2p: DMA client to flush transfers on
+ *
+ * Any transfers currently in progress will be completed in hardware, but
+ * ignored in software.
+ *
+ */
 void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
 
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index b8bbd31aa850..84a5ba03f1ba 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -23,16 +23,20 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/irq.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
+#include <mach/mmc.h>
 
 #include "devices-imx27.h"
 #include "devices.h"
 
+#define SD1_EN_GPIO (GPIO_PORTB + 25)
+
 static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
         PE12_PF_UART1_TXD,
@@ -58,6 +62,14 @@ static const int mx27pdk_pins[] __initconst = {
         PD15_AOUT_FEC_COL,
         PD16_AIN_FEC_TX_ER,
         PF23_AIN_FEC_TX_EN,
+        /* SDHC1 */
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -85,13 +97,39 @@ static struct matrix_keymap_data mx27_3ds_keymap_data = {
         .keymap_size    = ARRAY_SIZE(mx27_3ds_keymap),
 };
 
+static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+                                void *data)
+{
+        return request_irq(IRQ_GPIOB(26), detect_irq, IRQF_TRIGGER_FALLING |
+                        IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
+}
+
+static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIOB(26), data);
+}
+
+static struct imxmmc_platform_data sdhc1_pdata = {
+        .init = mx27_3ds_sdhc1_init,
+        .exit = mx27_3ds_sdhc1_exit,
+};
+
+static void mx27_3ds_sdhc1_enable_level_translator(void)
+{
+        /* Turn on TXB0108 OE pin */
+        gpio_request(SD1_EN_GPIO, "sd1_enable");
+        gpio_direction_output(SD1_EN_GPIO, 1);
+}
+
 static void __init mx27pdk_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
                 "mx27pdk");
+        mx27_3ds_sdhc1_enable_level_translator();
         imx27_add_imx_uart0(&uart_pdata);
         imx27_add_fec(NULL);
         mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
+        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index babb22597163..e24e3d05397f 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -197,7 +197,7 @@ unsigned long ixp2000_gettimeoffset (void)
         return offset / ticks_per_usec;
 }
 
-static int ixp2000_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
 {
         /* clear timer 1 */
         ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 51ff23b72d3a..3688123b5ad8 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -854,10 +854,9 @@ int __init kirkwood_find_tclk(void)
 
         kirkwood_pcie_id(&dev, &rev);
 
-        if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
-                                        rev == MV88F6281_REV_A1)) ||
-            (dev == MV88F6282_DEV_ID))
-                return 200000000;
+        if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
+                if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
+                        return 200000000;
 
         return 166666667;
 }
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index 4aa86e4a152c..a31c9499ab36 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -225,5 +225,5 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
         .init_machine   = d2net_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &lacie_v2_timer,
+        .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c
index d3ea1b6c8a02..285edab776e9 100644
--- a/arch/arm/mach-kirkwood/lacie_v2-common.c
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.c
@@ -111,17 +111,3 @@ void __init lacie_v2_hdd_power_init(int hdd_num)
                         pr_err("Failed to power up HDD%d\n", i + 1);
         }
 }
-
-/*****************************************************************************
- * Timer
- ****************************************************************************/
-
-static void lacie_v2_timer_init(void)
-{
-        kirkwood_tclk = 166666667;
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
-}
-
-struct sys_timer lacie_v2_timer = {
-        .init = lacie_v2_timer_init,
-};
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.h b/arch/arm/mach-kirkwood/lacie_v2-common.h
index af521315b87b..fc64f578536e 100644
--- a/arch/arm/mach-kirkwood/lacie_v2-common.h
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.h
@@ -13,6 +13,4 @@ void lacie_v2_register_flash(void);
 void lacie_v2_register_i2c_devices(void);
 void lacie_v2_hdd_power_init(int hdd_num);
 
-extern struct sys_timer lacie_v2_timer;
-
 #endif
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 065187d177c6..27901f702feb 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -59,7 +59,7 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
         }
         printk("\n");
 
-        while (*mpp_list) {
+        for ( ; *mpp_list; mpp_list++) {
                 unsigned int num = MPP_NUM(*mpp_list);
                 unsigned int sel = MPP_SEL(*mpp_list);
                 int shift, gpio_mode;
@@ -88,8 +88,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
                 if (sel != 0)
                         gpio_mode = 0;
                 orion_gpio_set_valid(num, gpio_mode);
-
-                mpp_list++;
         }
 
         printk(KERN_DEBUG "  final MPP regs:");
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 5ea66f1f4178..65ee21fd2f3b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -262,7 +262,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &lacie_v2_timer,
+        .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
 
@@ -272,7 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &lacie_v2_timer,
+        .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
 
@@ -282,6 +282,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &lacie_v2_timer,
+        .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index a1b45d501aef..93afd3c8bfd8 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -403,7 +403,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &lacie_v2_timer,
+        .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
 
@@ -413,6 +413,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
         .init_irq       = kirkwood_init_irq,
-        .timer          = &lacie_v2_timer,
+        .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 8be09a0ce4ac..3587a281d993 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -27,6 +27,10 @@
 #include "mpp.h"
 #include "tsx1x-common.h"
 
+/* for the PCIe reset workaround */
+#include <plat/pcie.h>
+
+
 #define QNAP_TS41X_JUMPER_JP1   45
 
 static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
@@ -140,8 +144,16 @@ static void __init qnap_ts41x_init(void)
 
 static int __init ts41x_pci_init(void)
 {
-        if (machine_is_ts41x())
+        if (machine_is_ts41x()) {
+                /*
+                 * Without this explicit reset, the PCIe SATA controller
+                 * (Marvell 88sx7042/sata_mv) is known to stop working
+                 * after a few minutes.
+                 */
+                orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
+
                 kirkwood_pcie_init(KW_PCIE0);
+        }
 
    return 0;
 }
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
index f43a68b213f1..8a3b56dfd35d 100644
--- a/arch/arm/mach-mmp/include/mach/cputype.h
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -46,7 +46,8 @@ static inline int cpu_is_pxa910(void)
 #ifdef CONFIG_CPU_MMP2
 static inline int cpu_is_mmp2(void)
 {
-        return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
+        return (((read_cpuid_id() >> 8) & 0xff) == 0x58);
+}
 #else
 #define cpu_is_mmp2()   (0)
 #endif
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 3115a29dec4e..dbbcfeb919db 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -6,6 +6,7 @@ choice
 
 config ARCH_MSM7X00A
         bool "MSM7x00A / MSM7x01A"
+        select MACH_TROUT if !MACH_HALIBUT
         select ARCH_MSM_ARM11
         select MSM_SMD
         select MSM_SMD_PKG3
@@ -15,34 +16,34 @@ config ARCH_MSM7X00A
 
 config ARCH_MSM7X30
         bool "MSM7x30"
+        select MACH_MSM7X30_SURF # if !
         select ARCH_MSM_SCORPION
         select MSM_SMD
         select MSM_VIC
         select CPU_V7
-        select MSM_REMOTE_SPINLOCK_DEKKERS
         select MSM_GPIOMUX
         select MSM_PROC_COMM
         select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_QSD8X50
         bool "QSD8X50"
+        select MACH_QSD8X50_SURF if !MACH_QSD8X50A_ST1_5
         select ARCH_MSM_SCORPION
         select MSM_SMD
         select MSM_VIC
         select CPU_V7
-        select MSM_REMOTE_SPINLOCK_LDREX
         select MSM_GPIOMUX
         select MSM_PROC_COMM
         select HAS_MSM_DEBUG_UART_PHYS
 
 config ARCH_MSM8X60
         bool "MSM8X60"
+        select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
+                                  && !MACH_MSM8X60_FFA)
         select ARM_GIC
         select CPU_V7
         select MSM_V2_TLMM
         select MSM_GPIOMUX
-        select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
-                                  && !MACH_MSM8X60_FFA)
 
 endchoice
 
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 59edecbe126c..75dabb16c802 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -83,7 +83,6 @@ static void __init halibut_fixup(struct machine_desc *desc, struct tag *tags,
 {
         mi->nr_banks=1;
         mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
         mi->bank[0].size = (101*1024*1024);
 }
 
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index fbd5d90dcc8c..646b99ebc773 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -19,7 +19,7 @@
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
 
-#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS
+#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
         .macro  addruart, rp, rv
         ldr     \rp, =MSM_DEBUG_UART_PHYS
         ldr     \rv, =MSM_DEBUG_UART_BASE
@@ -36,7 +36,18 @@
         tst     \rd, #0x04
         beq     1001b
         .endm
+#else
+        .macro  addruart, rp, rv
+        mov     \rv, #0xff000000
+        orr     \rv, \rv, #0x00f00000
+        .endm
 
-        .macro  busyuart,rd,rx
+        .macro  senduart,rd,rx
+        .endm
+
+        .macro  waituart,rd,rx
         .endm
 #endif
+
+        .macro  busyuart,rd,rx
+        .endm
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
index c33ae786c41f..9019cee2907b 100644
--- a/arch/arm/mach-msm/iommu_dev.c
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -128,7 +128,7 @@ static void msm_iommu_reset(void __iomem *base)
 
 static int msm_iommu_probe(struct platform_device *pdev)
 {
-        struct resource *r;
+        struct resource *r, *r2;
         struct clk *iommu_clk;
         struct msm_iommu_drvdata *drvdata;
         struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
@@ -183,27 +183,27 @@ static int msm_iommu_probe(struct platform_device *pdev)
 
                 len = r->end - r->start + 1;
 
-                r = request_mem_region(r->start, len, r->name);
-                if (!r) {
+                r2 = request_mem_region(r->start, len, r->name);
+                if (!r2) {
                         pr_err("Could not request memory region: "
                         "start=%p, len=%d\n", (void *) r->start, len);
                         ret = -EBUSY;
                         goto fail;
                 }
 
-                regs_base = ioremap(r->start, len);
+                regs_base = ioremap(r2->start, len);
 
                 if (!regs_base) {
                         pr_err("Could not ioremap: start=%p, len=%d\n",
-                                 (void *) r->start, len);
+                                 (void *) r2->start, len);
                         ret = -EBUSY;
-                        goto fail;
+                        goto fail_mem;
                 }
 
                 irq = platform_get_irq_byname(pdev, "secure_irq");
                 if (irq < 0) {
                         ret = -ENODEV;
-                        goto fail;
+                        goto fail_io;
                 }
 
                 mb();
@@ -211,14 +211,14 @@ static int msm_iommu_probe(struct platform_device *pdev)
                 if (GET_IDR(regs_base) == 0) {
                         pr_err("Invalid IDR value detected\n");
                         ret = -ENODEV;
-                        goto fail;
+                        goto fail_io;
                 }
 
                 ret = request_irq(irq, msm_iommu_fault_handler, 0,
                                 "msm_iommu_secure_irpt_handler", drvdata);
                 if (ret) {
                         pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
-                        goto fail;
+                        goto fail_io;
                 }
 
                 msm_iommu_reset(regs_base);
@@ -237,6 +237,10 @@ static int msm_iommu_probe(struct platform_device *pdev)
 
         return 0;
 
+fail_io:
+        iounmap(regs_base);
+fail_mem:
+        release_mem_region(r->start, len);
 fail:
         kfree(drvdata);
         return ret;
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 7689848ec680..950100f19d07 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -137,7 +137,7 @@ static struct msm_clock msm_clocks[] = {
                         .rating         = 200,
                         .read           = msm_gpt_read,
                         .mask           = CLOCKSOURCE_MASK(32),
-                        .shift          = 24,
+                        .shift          = 17,
                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
                 },
                 .irq = {
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 354ac514eb89..84db2dfc475c 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -54,7 +54,7 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
         }
         printk("\n");
 
-        while (*mpp_list) {
+        for ( ; *mpp_list; mpp_list++) {
                 unsigned int num = MPP_NUM(*mpp_list);
                 unsigned int sel = MPP_SEL(*mpp_list);
                 int shift, gpio_mode;
@@ -83,8 +83,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
                 if (sel != 0)
                         gpio_mode = 0;
                 orion_gpio_set_valid(num, gpio_mode);
-
-                mpp_list++;
         }
 
         printk(KERN_DEBUG "  final MPP regs:");
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index aa57e35ce3cd..38ca09a5df9d 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -6,6 +6,7 @@ config MACH_MX25_3DS
         bool "Support MX25PDK (3DS) Platform"
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_ESDHC
 
 config MACH_EUKREA_CPUIMX25
         bool "Support Eukrea CPUIMX25 Platform"
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 80805107a73e..f8be1eb0c062 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -96,6 +96,14 @@ static struct pad_desc mx25pdk_pads[] = {
         MX25_PAD_KPP_COL1__KPP_COL1,
         MX25_PAD_KPP_COL2__KPP_COL2,
         MX25_PAD_KPP_COL3__KPP_COL3,
+
+        /* SD1 */
+        MX25_PAD_SD1_CMD__SD1_CMD,
+        MX25_PAD_SD1_CLK__SD1_CLK,
+        MX25_PAD_SD1_DATA0__SD1_DATA0,
+        MX25_PAD_SD1_DATA1__SD1_DATA1,
+        MX25_PAD_SD1_DATA2__SD1_DATA2,
+        MX25_PAD_SD1_DATA3__SD1_DATA3,
 };
 
 static const struct fec_platform_data mx25_fec_pdata __initconst = {
@@ -193,6 +201,8 @@ static void __init mx25pdk_init(void)
         mx25pdk_fec_reset();
         imx25_add_fec(&mx25_fec_pdata);
         mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
+
+        imx25_add_esdhc(0, NULL);
 }
 
 static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 096fd33f8ab9..5000ac1f93e3 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -143,8 +143,10 @@ config MACH_ARMADILLO5X0
 config MACH_MX35_3DS
         bool "Support MX35PDK platform"
         select ARCH_MX35
+        select MXC_DEBUG_BOARD
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_ESDHC
         default n
         help
           Include support for MX35PDK platform. This includes specific
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index f4dff11aaee7..d4da9496089a 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -72,24 +72,24 @@ struct platform_device mxc_w1_master_device = {
 #ifdef CONFIG_ARCH_MX31
 static struct resource mxcsdhc0_resources[] = {
         {
-                .start = MMC_SDHC1_BASE_ADDR,
-                .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
+                .start = MX31_MMC_SDHC1_BASE_ADDR,
+                .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
                 .flags = IORESOURCE_MEM,
         }, {
-                .start = MXC_INT_MMC_SDHC1,
-                .end = MXC_INT_MMC_SDHC1,
+                .start = MX31_INT_MMC_SDHC1,
+                .end = MX31_INT_MMC_SDHC1,
                 .flags = IORESOURCE_IRQ,
         },
 };
 
 static struct resource mxcsdhc1_resources[] = {
         {
-                .start = MMC_SDHC2_BASE_ADDR,
-                .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
+                .start = MX31_MMC_SDHC2_BASE_ADDR,
+                .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
                 .flags = IORESOURCE_MEM,
         }, {
-                .start = MXC_INT_MMC_SDHC2,
-                .end = MXC_INT_MMC_SDHC2,
+                .start = MX31_INT_MMC_SDHC2,
+                .end = MX31_INT_MMC_SDHC2,
                 .flags = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 5c1d0e86c91e..0ad9e7821082 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -38,39 +38,9 @@
 #include "devices-imx31.h"
 #include "devices.h"
 
-/* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS              CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR               MX3x_CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR                       (DEBUG_BASE_ADDRESS + 0x20000)
-
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG             (CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG               (CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG              (CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG          (CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG          (CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG               (CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG          (CPLD_ADDR + 0x58)
-
 /* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET          (MXC_EXP_IO_BASE + 0)
-
-#define MXC_MAX_EXP_IO_LINES    16
-
 /*
  * This file contains the board-specific initialization routines.
  */
@@ -272,7 +242,7 @@ static void __init mxc_board_init(void)
         imx31_add_imx_uart0(&uart_pdata);
         imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
-        imx31_add_spi_imx0(&spi1_pdata);
+        imx31_add_spi_imx1(&spi1_pdata);
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
@@ -281,9 +251,9 @@ static void __init mxc_board_init(void)
         mx31_3ds_usbotg_init();
         mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-        if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
-                printk(KERN_WARNING "Init of the debugboard failed, all "
-                                    "devices on the board are unusable.\n");
+        if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+                printk(KERN_WARNING "Init of the debug board failed, all "
+                                    "devices on the debug board are unusable.\n");
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index 05f628d90725..b66a75aa2e88 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -38,11 +38,15 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+#include <mach/3ds_debugboard.h>
 #include <mach/mxc_ehci.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
 
+#define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
+
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -108,6 +112,13 @@ static struct pad_desc mx35pdk_pads[] = {
         /* USBH1 */
         MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
         MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
+        /* SDCARD */
+        MX35_PAD_SD1_CMD__ESDHC1_CMD,
+        MX35_PAD_SD1_CLK__ESDHC1_CLK,
+        MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
 };
 
 /* OTG config */
@@ -140,6 +151,11 @@ static void __init mxc_board_init(void)
         mxc_register_device(&mxc_usbh1, &usb_host_pdata);
 
         imx35_add_mxc_nand(&mx35pdk_nand_board_info);
+        imx35_add_esdhc(0, NULL);
+
+        if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+                pr_warn("Init of the debugboard failed, all "
+                                "devices on the debugboard are unusable.\n");
 }
 
 static void __init mx35pdk_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 86e86c1300d5..2ff3f661a48e 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -311,7 +311,6 @@ static struct soc_camera_link iclink_mt9v022 = {
         .bus_id         = 0,            /* Must match with the camera ID */
         .board_info     = &pcm037_i2c_camera[1],
         .i2c_adapter_id = 2,
-        .module_name    = "mt9v022",
 };
 
 static struct soc_camera_link iclink_mt9t031 = {
@@ -319,7 +318,6 @@ static struct soc_camera_link iclink_mt9t031 = {
         .power          = pcm037_camera_power,
         .board_info     = &pcm037_i2c_camera[0],
         .i2c_adapter_id = 2,
-        .module_name    = "mt9t031",
 };
 
 static struct i2c_board_info pcm037_i2c_devices[] = {
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 0551eb39d97e..18069cb7d068 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -179,7 +179,6 @@ static struct soc_camera_link base_iclink = {
         .reset          = marxbot_basecam_reset,
         .board_info     = &marxbot_i2c_devices[0],
         .i2c_adapter_id = 0,
-        .module_name    = "mt9t031",
 };
 
 static struct platform_device marxbot_camera[] = {
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 417757e78c65..04760a53005a 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -88,7 +88,6 @@ static struct soc_camera_link base_iclink = {
         .reset          = smartbot_cam_reset,
         .board_info     = &smartbot_i2c_devices[0],
         .i2c_adapter_id = 0,
-        .module_name    = "mt9t031",
 };
 
 static struct platform_device smartbot_camera[] = {
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index a2df9ac37996..3ec910a7a182 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -6,6 +6,7 @@ config ARCH_MX51
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
         select ARCH_MXC_AUDMUX_V2
+        select ARCH_HAS_CPUFREQ
 
 comment "MX5 platforms:"
 
@@ -13,6 +14,7 @@ config MACH_MX51_BABBAGE
         bool "Support MX51 BABBAGE platforms"
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_ESDHC
         help
           Include support for MX51 Babbage platform, also known as MX51EVK in
           u-boot. This includes specific configurations for the board and its
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 1769c161a60d..462f177eddfe 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -5,6 +5,7 @@
 # Object file lists.
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
+obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 0821fe9b3b27..acbe30df2e69 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
  *
  * The code contained herein is licensed under the GNU General Public
@@ -18,6 +18,8 @@
 #include <linux/io.h>
 #include <linux/fsl_devices.h>
 #include <linux/fec.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -32,11 +34,13 @@
 
 #include "devices-imx51.h"
 #include "devices.h"
+#include "cpu_op-mx51.h"
 
 #define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
 #define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
 #define BABBAGE_PHY_RESET       (1*32 + 5)      /* GPIO_2_5 */
 #define BABBAGE_FEC_PHY_RESET   (1*32 + 14)     /* GPIO_2_14 */
+#define BABBAGE_POWER_KEY       (1*32 + 21)     /* GPIO_2_21 */
 
 /* USB_CTRL_1 */
 #define MX51_USB_CTRL_1_OFFSET                  0x10
@@ -46,6 +50,21 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ 0x02
 
+static struct gpio_keys_button babbage_buttons[] = {
+        {
+                .gpio           = BABBAGE_POWER_KEY,
+                .code           = BTN_0,
+                .desc           = "PWR",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+};
+
+static const struct gpio_keys_platform_data imx_button_data __initconst = {
+        .buttons        = babbage_buttons,
+        .nbuttons       = ARRAY_SIZE(babbage_buttons),
+};
+
 static struct pad_desc mx51babbage_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
@@ -112,6 +131,22 @@ static struct pad_desc mx51babbage_pads[] = {
 
         /* FEC PHY reset line */
         MX51_PAD_EIM_A20__GPIO_2_14,
+
+        /* SD 1 */
+        MX51_PAD_SD1_CMD__SD1_CMD,
+        MX51_PAD_SD1_CLK__SD1_CLK,
+        MX51_PAD_SD1_DATA0__SD1_DATA0,
+        MX51_PAD_SD1_DATA1__SD1_DATA1,
+        MX51_PAD_SD1_DATA2__SD1_DATA2,
+        MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+        /* SD 2 */
+        MX51_PAD_SD2_CMD__SD2_CMD,
+        MX51_PAD_SD2_CLK__SD2_CLK,
+        MX51_PAD_SD2_DATA0__SD2_DATA0,
+        MX51_PAD_SD2_DATA1__SD2_DATA1,
+        MX51_PAD_SD2_DATA2__SD2_DATA2,
+        MX51_PAD_SD2_DATA3__SD2_DATA3,
 };
 
 /* Serial ports */
@@ -281,13 +316,22 @@ __setup("otg_mode=", babbage_otg_mode);
 static void __init mxc_board_init(void)
 {
         struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+        struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
 
+#if defined(CONFIG_CPU_FREQ_IMX)
+        get_cpu_op = mx51_get_cpu_op;
+#endif
         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                         ARRAY_SIZE(mx51babbage_pads));
         mxc_init_imx_uart();
         babbage_fec_reset();
         imx51_add_fec(NULL);
 
+        /* Set the PAD settings for the pwr key. */
+        power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
+        mxc_iomux_v3_setup_pad(&power_key);
+        imx51_add_gpio_keys(&imx_button_data);
+
         imx51_add_imx_i2c(0, &babbage_i2c_data);
         imx51_add_imx_i2c(1, &babbage_i2c_data);
         mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
@@ -304,6 +348,9 @@ static void __init mxc_board_init(void)
         /* setback USBH1_STP to be function */
         mxc_iomux_v3_setup_pad(&usbh1stp);
         babbage_usbhub_reset();
+
+        imx51_add_esdhc(0, NULL);
+        imx51_add_esdhc(1, NULL);
 }
 
 static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index f2aae92cf0e2..8ac36d882927 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -362,7 +362,7 @@ static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
         return 0;
 }
 
-static unsigned long clk_arm_get_rate(struct clk *clk)
+static unsigned long clk_cpu_get_rate(struct clk *clk)
 {
         u32 cacrr, div;
         unsigned long parent_rate;
@@ -374,6 +374,22 @@ static unsigned long clk_arm_get_rate(struct clk *clk)
         return parent_rate / div;
 }
 
+static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, cpu_podf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+        cpu_podf = parent_rate / rate - 1;
+        /* use post divider to change freq */
+        reg = __raw_readl(MXC_CCM_CACRR);
+        reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
+        reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
+        __raw_writel(reg, MXC_CCM_CACRR);
+
+        return 0;
+}
+
 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
 {
         u32 reg, mux;
@@ -736,7 +752,8 @@ static struct clk periph_apm_clk = {
 
 static struct clk cpu_clk = {
         .parent = &pll1_sw_clk,
-        .get_rate = clk_arm_get_rate,
+        .get_rate = clk_cpu_get_rate,
+        .set_rate = clk_cpu_set_rate,
 };
 
 static struct clk ahb_clk = {
@@ -1064,6 +1081,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-mx5/cpu_op-mx51.c
new file mode 100644
index 000000000000..9d34c3d4c024
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx51.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/types.h>
+#include <mach/hardware.h>
+#include <linux/kernel.h>
+
+static struct cpu_op mx51_cpu_op[] = {
+        {
+        .cpu_rate = 160000000,},
+        {
+        .cpu_rate = 800000000,},
+};
+
+struct cpu_op *mx51_get_cpu_op(int *op)
+{
+        *op = ARRAY_SIZE(mx51_cpu_op);
+        return mx51_cpu_op;
+}
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-mx5/cpu_op-mx51.h
new file mode 100644
index 000000000000..97477fecb469
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu_op-mx51.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index 5cc910e60538..8c50cb5d05f5 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -13,6 +13,8 @@ extern const struct imx_fec_data imx51_fec_data __initconst;
 #define imx51_add_fec(pdata)    \
         imx_add_fec(&imx51_fec_data, pdata)
 
+#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
+
 extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
 #define imx51_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index ea0d80a89da7..e7f9ee63dce5 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -321,10 +321,9 @@ static struct platform_device omap_wdt_device = {
 static int __init omap_init_wdt(void)
 {
         if (!cpu_is_omap16xx())
-                return;
+                return -ENODEV;
 
-        platform_device_register(&omap_wdt_device);
-        return 0;
+        return platform_device_register(&omap_wdt_device);
 }
 subsys_initcall(omap_init_wdt);
 #endif
diff --git a/arch/arm/mach-omap1/include/mach/camera.h b/arch/arm/mach-omap1/include/mach/camera.h
index fd54b452eb22..847d00f0bb0a 100644
--- a/arch/arm/mach-omap1/include/mach/camera.h
+++ b/arch/arm/mach-omap1/include/mach/camera.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_ARCH_CAMERA_H_
 #define __ASM_ARCH_CAMERA_H_
 
+#include <media/omap1_camera.h>
+
 void omap1_camera_init(void *);
 
 static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7352412e4917..60e51bcf53bd 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -108,6 +108,10 @@ obj-y					+= $(iommu-m) $(iommu-y)
 i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
 obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
 
+ifneq ($(CONFIG_TIDSPBRIDGE),)
+obj-y                                   += dsp.o
+endif
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 69a4ae971e41..df5a425a49d1 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -269,9 +269,14 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
         struct omap_mmc_platform_data *pdata = dev->platform_data;
 
         /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0)
+        if (pdev->id == 0) {
+                ret = twl6030_mmc_card_detect_config();
+                if (ret)
+                        pr_err("Failed configuring MMC1 card detect\n");
                 pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
                                                 MMCDETECT_INTR_OFFSET;
+                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+        }
         return ret;
 }
 
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 067f4379c87f..53ac762518bd 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -242,9 +242,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters */
-        devkit8000_vmmc1_supply.dev = mmc[0].dev;
-
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 702f2a63f2c1..1ecd0a6cefb7 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -160,10 +160,19 @@ static int omap4_twl6030_hsmmc_late_init(struct device *dev)
                                 struct platform_device, dev);
         struct omap_mmc_platform_data *pdata = dev->platform_data;
 
+        if (!pdata) {
+                dev_err(dev, "%s: NULL platform data\n", __func__);
+                return -EINVAL;
+        }
         /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0)
-                pdata->slots[0].card_detect_irq = TWL6030_IRQ_BASE +
-                                                MMCDETECT_INTR_OFFSET;
+        if (pdev->id == 0) {
+                ret = twl6030_mmc_card_detect_config();
+                 if (ret)
+                        dev_err(dev, "%s: Error card detect config(%d)\n",
+                                __func__, ret);
+                 else
+                        pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+        }
         return ret;
 }
 
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
new file mode 100644
index 000000000000..6feeeae6c21b
--- /dev/null
+++ b/arch/arm/mach-omap2/dsp.c
@@ -0,0 +1,85 @@
+/*
+ * TI's OMAP DSP platform device registration
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include "prm.h"
+#include "cm.h"
+#ifdef CONFIG_BRIDGE_DVFS
+#include <plat/omap-pm.h>
+#endif
+
+#include <plat/dsp.h>
+
+extern phys_addr_t omap_dsp_get_mempool_base(void);
+
+static struct platform_device *omap_dsp_pdev;
+
+static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
+#ifdef CONFIG_BRIDGE_DVFS
+        .dsp_set_min_opp = omap_pm_dsp_set_min_opp,
+        .dsp_get_opp = omap_pm_dsp_get_opp,
+        .cpu_set_freq = omap_pm_cpu_set_freq,
+        .cpu_get_freq = omap_pm_cpu_get_freq,
+#endif
+        .dsp_prm_read = prm_read_mod_reg,
+        .dsp_prm_write = prm_write_mod_reg,
+        .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits,
+        .dsp_cm_read = cm_read_mod_reg,
+        .dsp_cm_write = cm_write_mod_reg,
+        .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits,
+};
+
+static int __init omap_dsp_init(void)
+{
+        struct platform_device *pdev;
+        int err = -ENOMEM;
+        struct omap_dsp_platform_data *pdata = &omap_dsp_pdata;
+
+        pdata->phys_mempool_base = omap_dsp_get_mempool_base();
+
+        if (pdata->phys_mempool_base) {
+                pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
+                pr_info("%s: %x bytes @ %x\n", __func__,
+                        pdata->phys_mempool_size, pdata->phys_mempool_base);
+        }
+
+        pdev = platform_device_alloc("omap-dsp", -1);
+        if (!pdev)
+                goto err_out;
+
+        err = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+        if (err)
+                goto err_out;
+
+        err = platform_device_add(pdev);
+        if (err)
+                goto err_out;
+
+        omap_dsp_pdev = pdev;
+        return 0;
+
+err_out:
+        platform_device_put(pdev);
+        return err;
+}
+module_init(omap_dsp_init);
+
+static void __exit omap_dsp_exit(void)
+{
+        platform_device_unregister(omap_dsp_pdev);
+}
+module_exit(omap_dsp_exit);
+
+MODULE_AUTHOR("Hiroshi DOYU");
+MODULE_DESCRIPTION("TI's OMAP DSP platform device registration");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 923f9f5f91ce..2f895553e6a8 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -44,6 +44,13 @@ void __init gic_init_irq(void)
 }
 
 #ifdef CONFIG_CACHE_L2X0
+
+static void omap4_l2x0_disable(void)
+{
+        /* Disable PL310 L2 Cache controller */
+        omap_smc1(0x102, 0x0);
+}
+
 static int __init omap_l2_cache_init(void)
 {
         /*
@@ -70,6 +77,12 @@ static int __init omap_l2_cache_init(void)
         else
                 l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
 
+        /*
+         * Override default outer_cache.disable with a OMAP4
+         * specific one
+        */
+        outer_cache.disable = omap4_l2x0_disable;
+
         return 0;
 }
 early_initcall(omap_l2_cache_init);
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index bc4c3b9aaf83..db485d3b8144 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -127,7 +127,7 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
         /* Initialize gpiolib. */
         orion_gpio_init();
 
-        while (mode->mpp >= 0) {
+        for ( ; mode->mpp >= 0; mode++) {
                 u32 *reg;
                 int num_type;
                 int shift;
@@ -160,8 +160,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
                         orion_gpio_set_unused(mode->mpp);
 
                 orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
-
-                mode++;
         }
 
         writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 16f1bd5324be..c1c1cd04bdde 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -239,7 +239,7 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
 static struct resource ts78xx_ts_nand_resources = {
         .start          = TS_NAND_DATA,
         .end            = TS_NAND_DATA + 4,
-        .flags          = IORESOURCE_IO,
+        .flags          = IORESOURCE_MEM,
 };
 
 static struct platform_device ts78xx_ts_nand_device = {
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index ac5598ce9724..d34b99febeb9 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -476,8 +476,6 @@ static void __init cmx2xx_init(void)
 
 static void __init cmx2xx_init_irq(void)
 {
-        pxa27x_init_irq();
-
         if (cpu_is_pxa25x()) {
                 pxa25x_init_irq();
                 cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index ab48bb81b570..ed0dbfdb22ed 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1015,7 +1015,6 @@ static struct soc_camera_link iclink = {
         .power          = em_x270_sensor_power,
         .board_info     = &em_x270_i2c_cam_info[0],
         .i2c_adapter_id = 0,
-        .module_name    = "mt9m111",
 };
 
 static struct platform_device em_x270_camera = {
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 80a9352d43f3..142c711f4cda 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -755,7 +755,6 @@ static struct soc_camera_link a780_iclink = {
         .flags          = SOCAM_SENSOR_INVERT_PCLK,
         .i2c_adapter_id = 0,
         .board_info     = &a780_camera_i2c_board_info,
-        .module_name    = "mt9m111",
         .power          = a780_camera_power,
         .reset          = a780_camera_reset,
 };
@@ -1024,7 +1023,6 @@ static struct soc_camera_link a910_iclink = {
         .bus_id         = 0,
         .i2c_adapter_id = 0,
         .board_info     = &a910_camera_i2c_board_info,
-        .module_name    = "mt9m111",
         .power          = a910_camera_power,
         .reset          = a910_camera_reset,
 };
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 0c31fabfc7fd..f5fb915e1315 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -711,7 +711,6 @@ static struct soc_camera_link iclink = {
         .bus_id         = 0, /* Match id in pxa27x_device_camera in device.c */
         .board_info     = &mioa701_i2c_devices[0],
         .i2c_adapter_id = 0,
-        .module_name    = "mt9m111",
 };
 
 struct i2c_pxa_platform_data i2c_pdata = {
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index f56ae1008759..f33647a8e0b7 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -453,7 +453,6 @@ static struct soc_camera_link iclink[] = {
                 .query_bus_param        = pcm990_camera_query_bus_param,
                 .set_bus_param          = pcm990_camera_set_bus_param,
                 .free_bus               = pcm990_camera_free_bus,
-                .module_name            = "mt9v022",
         }, {
                 .bus_id                 = 0, /* Must match with the camera ID */
                 .board_info             = &pcm990_camera_i2c[1],
@@ -461,7 +460,6 @@ static struct soc_camera_link iclink[] = {
                 .query_bus_param        = pcm990_camera_query_bus_param,
                 .set_bus_param          = pcm990_camera_set_bus_param,
                 .free_bus               = pcm990_camera_free_bus,
-                .module_name            = "mt9m001",
         },
 };
 
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 4b521e045d75..ffa50e633ee6 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -116,7 +116,7 @@ static struct platform_device smc91x_device = {
         },
 };
 
-#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULE)
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static uint16_t lcd_power_on[] = {
         /* single frame */
         SMART_CMD_NOOP,
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 8cdeb14af592..8aa2f1902a94 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -30,7 +30,7 @@ static void h1940bt_enable(int on)
 {
         if (on) {
                 /* Power on the chip */
-                h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
+                gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 1);
                 /* Reset the chip */
                 mdelay(10);
 
@@ -43,7 +43,7 @@ static void h1940bt_enable(int on)
                 mdelay(10);
                 gpio_set_value(S3C2410_GPH(1), 0);
                 mdelay(10);
-                h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
+                gpio_set_value(H1940_LATCH_BLUETOOTH_POWER, 0);
         }
 }
 
@@ -64,7 +64,14 @@ static int __devinit h1940bt_probe(struct platform_device *pdev)
 
         ret = gpio_request(S3C2410_GPH(1), dev_name(&pdev->dev));
         if (ret) {
-                dev_err(&pdev->dev, "could not get GPH1\n");\
+                dev_err(&pdev->dev, "could not get GPH1\n");
+                return ret;
+        }
+
+        ret = gpio_request(H1940_LATCH_BLUETOOTH_POWER, dev_name(&pdev->dev));
+        if (ret) {
+                gpio_free(S3C2410_GPH(1));
+                dev_err(&pdev->dev, "could not get BT_POWER\n");
                 return ret;
         }
 
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index b649bf2ccd5c..f7f6b07df30e 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -22,6 +22,8 @@
 
 #ifdef CONFIG_CPU_S3C244X
 #define ARCH_NR_GPIOS   (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define ARCH_NR_GPIOS   (32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
 #else
 #define ARCH_NR_GPIOS   (256 + CONFIG_S3C24XX_GPIO_EXTRA)
 #endif
@@ -30,8 +32,10 @@
 #include <mach/gpio-nrs.h>
 #include <mach/gpio-fns.h>
 
-#ifdef CONFIG_CPU_S3C24XX
-#define S3C_GPIO_END    (S3C2410_GPIO_BANKJ + 32)
+#ifdef CONFIG_CPU_S3C244X
+#define S3C_GPIO_END    (S3C2410_GPJ(0) + 32)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define S3C_GPIO_END    (S3C2410_GPM(0) + 32)
 #else
-#define S3C_GPIO_END    (S3C2410_GPIO_BANKH + 32)
+#define S3C_GPIO_END    (S3C2410_GPH(0) + 32)
 #endif
diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
index d8a832729a8a..97e42bfce81e 100644
--- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+++ b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
@@ -14,51 +14,30 @@
 #ifndef __ASM_ARCH_H1940_LATCH_H
 #define __ASM_ARCH_H1940_LATCH_H
 
+#include <mach/gpio.h>
 
-#ifndef __ASSEMBLY__
-#define H1940_LATCH             ((void __force __iomem *)0xF8000000)
-#else
-#define H1940_LATCH             0xF8000000
-#endif
-
-#define H1940_PA_LATCH          (S3C2410_CS2)
+#define H1940_LATCH_GPIO(x)             (S3C_GPIO_END + (x))
 
 /* SD layer latch */
 
-#define H1940_LATCH_SDQ1                (1<<16)
-#define H1940_LATCH_LCD_P1              (1<<17)
-#define H1940_LATCH_LCD_P2              (1<<18)
-#define H1940_LATCH_LCD_P3              (1<<19)
-#define H1940_LATCH_MAX1698_nSHUTDOWN   (1<<20)         /* LCD backlight */
-#define H1940_LATCH_LED_RED             (1<<21)
-#define H1940_LATCH_SDQ7                (1<<22)
-#define H1940_LATCH_USB_DP              (1<<23)
+#define H1940_LATCH_LCD_P0              H1940_LATCH_GPIO(0)
+#define H1940_LATCH_LCD_P1              H1940_LATCH_GPIO(1)
+#define H1940_LATCH_LCD_P2              H1940_LATCH_GPIO(2)
+#define H1940_LATCH_LCD_P3              H1940_LATCH_GPIO(3)
+#define H1940_LATCH_MAX1698_nSHUTDOWN   H1940_LATCH_GPIO(4)
+#define H1940_LATCH_LED_RED             H1940_LATCH_GPIO(5)
+#define H1940_LATCH_SDQ7                H1940_LATCH_GPIO(6)
+#define H1940_LATCH_USB_DP              H1940_LATCH_GPIO(7)
 
 /* CPU layer latch */
 
-#define H1940_LATCH_UDA_POWER           (1<<24)
-#define H1940_LATCH_AUDIO_POWER         (1<<25)
-#define H1940_LATCH_SM803_ENABLE        (1<<26)
-#define H1940_LATCH_LCD_P4              (1<<27)
-#define H1940_LATCH_CPUQ5               (1<<28)         /* untraced */
-#define H1940_LATCH_BLUETOOTH_POWER     (1<<29)         /* active high */
-#define H1940_LATCH_LED_GREEN           (1<<30)
-#define H1940_LATCH_LED_FLASH           (1<<31)
-
-/* default settings */
-
-#define H1940_LATCH_DEFAULT             \
-        H1940_LATCH_LCD_P4              | \
-        H1940_LATCH_SM803_ENABLE        | \
-        H1940_LATCH_SDQ1                | \
-        H1940_LATCH_LCD_P1              | \
-        H1940_LATCH_LCD_P2              | \
-        H1940_LATCH_LCD_P3              | \
-        H1940_LATCH_MAX1698_nSHUTDOWN   | \
-        H1940_LATCH_CPUQ5
-
-/* control functions */
-
-extern void h1940_latch_control(unsigned int clear, unsigned int set);
+#define H1940_LATCH_UDA_POWER           H1940_LATCH_GPIO(8)
+#define H1940_LATCH_AUDIO_POWER         H1940_LATCH_GPIO(9)
+#define H1940_LATCH_SM803_ENABLE        H1940_LATCH_GPIO(10)
+#define H1940_LATCH_LCD_P4              H1940_LATCH_GPIO(11)
+#define H1940_LATCH_SD_POWER            H1940_LATCH_GPIO(12)
+#define H1940_LATCH_BLUETOOTH_POWER     H1940_LATCH_GPIO(13)
+#define H1940_LATCH_LED_GREEN           H1940_LATCH_GPIO(14)
+#define H1940_LATCH_LED_FLASH           H1940_LATCH_GPIO(15)
 
 #endif /* __ASM_ARCH_H1940_LATCH_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 08ab9dfb6ae6..101aeea22310 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -118,6 +118,8 @@
 #define S3C2443_SCLKCON_UARTCLK         (1<<8)
 #define S3C2443_SCLKCON_USBHOST         (1<<1)
 
+#define S3C2443_PWRCFG_SLEEP            (1<<15)
+
 #include <asm/div64.h>
 
 static inline unsigned int
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
index 54297eb0bf5e..7a311e8dddba 100644
--- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END     0xE0000000UL
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 98c5c9e81ee9..d7ada8c7e41f 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
+#include <linux/i2c.h>
 #include <video/platform_lcd.h>
 
 #include <linux/mmc/host.h>
@@ -59,6 +60,14 @@
 #include <plat/mci.h>
 #include <plat/ts.h>
 
+#include <sound/uda1380.h>
+
+#define H1940_LATCH             ((void __force __iomem *)0xF8000000)
+
+#define H1940_PA_LATCH          S3C2410_CS2
+
+#define H1940_LATCH_BIT(x)      (1 << ((x) + 16 - S3C_GPIO_END))
+
 static struct map_desc h1940_iodesc[] __initdata = {
         [0] = {
                 .virtual        = (unsigned long)H1940_LATCH,
@@ -100,9 +109,9 @@ static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = {
 
 /* Board control latch control */
 
-static unsigned int latch_state = H1940_LATCH_DEFAULT;
+static unsigned int latch_state;
 
-void h1940_latch_control(unsigned int clear, unsigned int set)
+static void h1940_latch_control(unsigned int clear, unsigned int set)
 {
         unsigned long flags;
 
@@ -116,7 +125,42 @@ void h1940_latch_control(unsigned int clear, unsigned int set)
         local_irq_restore(flags);
 }
 
-EXPORT_SYMBOL_GPL(h1940_latch_control);
+static inline int h1940_gpiolib_to_latch(int offset)
+{
+        return 1 << (offset + 16);
+}
+
+static void h1940_gpiolib_latch_set(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        int latch_bit = h1940_gpiolib_to_latch(offset);
+
+        h1940_latch_control(value ? 0 : latch_bit,
+                value ? latch_bit : 0);
+}
+
+static int h1940_gpiolib_latch_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        h1940_gpiolib_latch_set(chip, offset, value);
+        return 0;
+}
+
+static int h1940_gpiolib_latch_get(struct gpio_chip *chip,
+                                        unsigned offset)
+{
+        return (latch_state >> (offset + 16)) & 1;
+}
+
+struct gpio_chip h1940_latch_gpiochip = {
+        .base                   = H1940_LATCH_GPIO(0),
+        .owner                  = THIS_MODULE,
+        .label                  = "H1940_LATCH",
+        .ngpio                  = 16,
+        .direction_output       = h1940_gpiolib_latch_output,
+        .set                    = h1940_gpiolib_latch_set,
+        .get                    = h1940_gpiolib_latch_get,
+};
 
 static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
 {
@@ -125,10 +169,10 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
         switch (cmd)
         {
                 case S3C2410_UDC_P_ENABLE :
-                        h1940_latch_control(0, H1940_LATCH_USB_DP);
+                        gpio_set_value(H1940_LATCH_USB_DP, 1);
                         break;
                 case S3C2410_UDC_P_DISABLE :
-                        h1940_latch_control(H1940_LATCH_USB_DP, 0);
+                        gpio_set_value(H1940_LATCH_USB_DP, 0);
                         break;
                 case S3C2410_UDC_P_RESET :
                         break;
@@ -199,10 +243,25 @@ static struct platform_device h1940_device_bluetooth = {
         .id               = -1,
 };
 
+static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
+{
+        switch (power_mode) {
+        case MMC_POWER_OFF:
+                gpio_set_value(H1940_LATCH_SD_POWER, 0);
+                break;
+        case MMC_POWER_UP:
+        case MMC_POWER_ON:
+                gpio_set_value(H1940_LATCH_SD_POWER, 1);
+                break;
+        default:
+                break;
+        };
+}
+
 static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
         .gpio_detect   = S3C2410_GPF(5),
         .gpio_wprotect = S3C2410_GPH(8),
-        .set_power     = NULL,
+        .set_power     = h1940_set_mmc_power,
         .ocr_avail     = MMC_VDD_32_33,
 };
 
@@ -213,15 +272,32 @@ static int h1940_backlight_init(struct device *dev)
         gpio_direction_output(S3C2410_GPB(0), 0);
         s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
         s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+        gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
 
         return 0;
 }
 
+static int h1940_backlight_notify(struct device *dev, int brightness)
+{
+        if (!brightness) {
+                gpio_direction_output(S3C2410_GPB(0), 1);
+                gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
+        } else {
+                gpio_direction_output(S3C2410_GPB(0), 0);
+                s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE);
+                s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+                gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 1);
+        }
+        return brightness;
+}
+
 static void h1940_backlight_exit(struct device *dev)
 {
         gpio_direction_output(S3C2410_GPB(0), 1);
+        gpio_set_value(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
 }
 
+
 static struct platform_pwm_backlight_data backlight_data = {
         .pwm_id         = 0,
         .max_brightness = 100,
@@ -229,6 +305,7 @@ static struct platform_pwm_backlight_data backlight_data = {
         /* tcnt = 0x31 */
         .pwm_period_ns  = 36296,
         .init           = h1940_backlight_init,
+        .notify         = h1940_backlight_notify,
         .exit           = h1940_backlight_exit,
 };
 
@@ -247,19 +324,37 @@ static void h1940_lcd_power_set(struct plat_lcd_data *pd,
         int value;
 
         if (!power) {
-                /* set to 3ec */
-                gpio_direction_output(S3C2410_GPC(0), 0);
+                gpio_set_value(S3C2410_GPC(0), 0);
                 /* wait for 3ac */
                 do {
                         value = gpio_get_value(S3C2410_GPC(6));
                 } while (value);
-                /* set to 38c */
-                gpio_direction_output(S3C2410_GPC(5), 0);
+
+                gpio_set_value(H1940_LATCH_LCD_P2, 0);
+                gpio_set_value(H1940_LATCH_LCD_P3, 0);
+                gpio_set_value(H1940_LATCH_LCD_P4, 0);
+
+                gpio_direction_output(S3C2410_GPC(1), 0);
+                gpio_direction_output(S3C2410_GPC(4), 0);
+
+                gpio_set_value(H1940_LATCH_LCD_P1, 0);
+                gpio_set_value(H1940_LATCH_LCD_P0, 0);
+
+                gpio_set_value(S3C2410_GPC(5), 0);
+
         } else {
-                /* Set to 3ac */
-                gpio_direction_output(S3C2410_GPC(5), 1);
-                /* Set to 3ad */
-                gpio_direction_output(S3C2410_GPC(0), 1);
+                gpio_set_value(H1940_LATCH_LCD_P0, 1);
+                gpio_set_value(H1940_LATCH_LCD_P1, 1);
+
+                s3c_gpio_cfgpin(S3C2410_GPC(1), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin(S3C2410_GPC(4), S3C_GPIO_SFN(2));
+
+                gpio_set_value(S3C2410_GPC(5), 1);
+                gpio_set_value(S3C2410_GPC(0), 1);
+
+                gpio_set_value(H1940_LATCH_LCD_P3, 1);
+                gpio_set_value(H1940_LATCH_LCD_P2, 1);
+                gpio_set_value(H1940_LATCH_LCD_P4, 1);
         }
 }
 
@@ -273,12 +368,26 @@ static struct platform_device h1940_lcd_powerdev = {
         .dev.platform_data      = &h1940_lcd_power_data,
 };
 
+static struct uda1380_platform_data uda1380_info = {
+        .gpio_power     = H1940_LATCH_UDA_POWER,
+        .gpio_reset     = S3C2410_GPA(12),
+        .dac_clk        = UDA1380_DAC_CLK_SYSCLK,
+};
+
+static struct i2c_board_info h1940_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("uda1380", 0x1a),
+                .platform_data = &uda1380_info,
+        },
+};
+
 static struct platform_device *h1940_devices[] __initdata = {
         &s3c_device_ohci,
         &s3c_device_lcd,
         &s3c_device_wdt,
         &s3c_device_i2c0,
         &s3c_device_iis,
+        &s3c_device_pcm,
         &s3c_device_usbgadget,
         &h1940_device_leds,
         &h1940_device_bluetooth,
@@ -303,6 +412,10 @@ static void __init h1940_map_io(void)
         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
 #endif
         s3c_pm_init();
+
+        /* Add latch gpio chip, set latch initial value */
+        h1940_latch_control(0, 0);
+        WARN_ON(gpiochip_add(&h1940_latch_gpiochip));
 }
 
 /* H1940 and RX3715 need to reserve this for suspend */
@@ -340,12 +453,38 @@ static void __init h1940_init(void)
         writel(tmp, S3C2410_UPLLCON);
 
         gpio_request(S3C2410_GPC(0), "LCD power");
+        gpio_request(S3C2410_GPC(1), "LCD power");
+        gpio_request(S3C2410_GPC(4), "LCD power");
         gpio_request(S3C2410_GPC(5), "LCD power");
         gpio_request(S3C2410_GPC(6), "LCD power");
-
+        gpio_request(H1940_LATCH_LCD_P0, "LCD power");
+        gpio_request(H1940_LATCH_LCD_P1, "LCD power");
+        gpio_request(H1940_LATCH_LCD_P2, "LCD power");
+        gpio_request(H1940_LATCH_LCD_P3, "LCD power");
+        gpio_request(H1940_LATCH_LCD_P4, "LCD power");
+        gpio_request(H1940_LATCH_MAX1698_nSHUTDOWN, "LCD power");
+        gpio_direction_output(S3C2410_GPC(0), 0);
+        gpio_direction_output(S3C2410_GPC(1), 0);
+        gpio_direction_output(S3C2410_GPC(4), 0);
+        gpio_direction_output(S3C2410_GPC(5), 0);
         gpio_direction_input(S3C2410_GPC(6));
+        gpio_direction_output(H1940_LATCH_LCD_P0, 0);
+        gpio_direction_output(H1940_LATCH_LCD_P1, 0);
+        gpio_direction_output(H1940_LATCH_LCD_P2, 0);
+        gpio_direction_output(H1940_LATCH_LCD_P3, 0);
+        gpio_direction_output(H1940_LATCH_LCD_P4, 0);
+        gpio_direction_output(H1940_LATCH_MAX1698_nSHUTDOWN, 0);
+
+        gpio_request(H1940_LATCH_USB_DP, "USB pullup");
+        gpio_direction_output(H1940_LATCH_USB_DP, 0);
+
+        gpio_request(H1940_LATCH_SD_POWER, "SD power");
+        gpio_direction_output(H1940_LATCH_SD_POWER, 0);
 
         platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
+
+        i2c_register_board_info(0, h1940_i2c_devices,
+                ARRAY_SIZE(h1940_i2c_devices));
 }
 
 MACHINE_START(H1940, "IPAQ-H1940")
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index bef39f77729d..4c6df51ddf33 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -51,6 +51,7 @@
 #include <plat/clock.h>
 #include <plat/pm.h>
 #include <plat/pll.h>
+#include <plat/nand-core.h>
 
 #ifndef CONFIG_CPU_S3C2412_ONLY
 void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
@@ -92,7 +93,7 @@ void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
         /* rename devices that are s3c2412/s3c2413 specific */
         s3c_device_sdi.name  = "s3c2412-sdi";
         s3c_device_lcd.name  = "s3c2412-lcd";
-        s3c_device_nand.name = "s3c2412-nand";
+        s3c_nand_setname("s3c2412-nand");
 
         /* alter IRQ of SDI controller */
 
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 657e4fe17f39..87b9c9f003bd 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -25,6 +25,11 @@ config S3C2416_DMA
         help
           Internal config node for S3C2416 DMA support
 
+config S3C2416_PM
+        bool
+        help
+          Internal config node to apply S3C2416 power management
+
 menu "S3C2416 Machines"
 
 config MACH_SMDK2416
@@ -33,6 +38,7 @@ config MACH_SMDK2416
         select S3C_DEV_FB
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
+        select S3C2416_PM if PM
         help
           Say Y here if you are using an SMDK2416
 
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 6c12c7bf40ad..ef038d62ffdb 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -11,7 +11,7 @@ obj-				:=
 
 obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock.o
 obj-$(CONFIG_CPU_S3C2416)       += irq.o
-
+obj-$(CONFIG_S3C2416_PM)        += pm.o
 #obj-$(CONFIG_S3C2416_DMA)      += dma.o
 
 # Machine support
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 89f521d59d06..084d121f368c 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -243,6 +243,8 @@ static int __init s3c2416_irq_add(struct sys_device *sysdev)
 
 static struct sysdev_driver s3c2416_irq_driver = {
         .add            = s3c2416_irq_add,
+        .suspend        = s3c24xx_irq_suspend,
+        .resume         = s3c24xx_irq_resume,
 };
 
 static int __init s3c2416_irq_init(void)
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
new file mode 100644
index 000000000000..4a04205b04d5
--- /dev/null
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -0,0 +1,84 @@
+/* linux/arch/arm/mach-s3c2416/pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S3C2416 - PM support (Based on Ben Dooks' S3C2412 PM support)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/regs-power.h>
+#include <mach/regs-s3c2443-clock.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+
+extern void s3c2412_sleep_enter(void);
+
+static void s3c2416_cpu_suspend(void)
+{
+        flush_cache_all();
+
+        /* enable wakeup sources regardless of battery state */
+        __raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG);
+
+        /* set the mode as sleep, 2BED represents "Go to BED" */
+        __raw_writel(0x2BED, S3C2443_PWRMODE);
+
+        s3c2412_sleep_enter();
+}
+
+static void s3c2416_pm_prepare(void)
+{
+        /*
+         * write the magic value u-boot uses to check for resume into
+         * the INFORM0 register, and ensure INFORM1 is set to the
+         * correct address to resume from.
+         */
+        __raw_writel(0x2BED, S3C2412_INFORM0);
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+}
+
+static int s3c2416_pm_add(struct sys_device *sysdev)
+{
+        pm_cpu_prep = s3c2416_pm_prepare;
+        pm_cpu_sleep = s3c2416_cpu_suspend;
+
+        return 0;
+}
+
+static int s3c2416_pm_suspend(struct sys_device *dev, pm_message_t state)
+{
+        return 0;
+}
+
+static int s3c2416_pm_resume(struct sys_device *dev)
+{
+        /* unset the return-from-sleep amd inform flags */
+        __raw_writel(0x0, S3C2443_PWRMODE);
+        __raw_writel(0x0, S3C2412_INFORM0);
+        __raw_writel(0x0, S3C2412_INFORM1);
+
+        return 0;
+}
+
+static struct sysdev_driver s3c2416_pm_driver = {
+        .add            = s3c2416_pm_add,
+        .suspend        = s3c2416_pm_suspend,
+        .resume         = s3c2416_pm_resume,
+};
+
+static __init int s3c2416_pm_init(void)
+{
+        return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver);
+}
+
+arch_initcall(s3c2416_pm_init);
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index bc30245e133b..63f39cdc0972 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -56,6 +56,7 @@
 
 #include <plat/iic-core.h>
 #include <plat/fb-core.h>
+#include <plat/nand-core.h>
 
 static struct map_desc s3c2416_iodesc[] __initdata = {
         IODESC_ENT(WATCHDOG),
@@ -100,7 +101,7 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
         s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
 
-        s3c_device_nand.name = "s3c2416-nand";
+        s3c_nand_setname("s3c2412-nand");
 }
 
 /* s3c2416_map_io
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index cd8e7de388f0..ff024a6c0f85 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -4,7 +4,6 @@
 
 config CPU_S3C2440
         bool
-        depends on ARCH_S3C2410
         select CPU_ARM920T
         select S3C_GPIO_PULL_UP
         select S3C2410_CLOCK
@@ -18,7 +17,6 @@ config CPU_S3C2440
 
 config CPU_S3C2442
         bool
-        depends on ARCH_S3C2410
         select CPU_ARM920T
         select S3C2410_CLOCK
         select S3C2410_GPIO
@@ -30,7 +28,7 @@ config CPU_S3C2442
 
 config CPU_S3C244X
         bool
-        depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
+        depends on CPU_S3C2440 || CPU_S3C2442
         help
           Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
 
@@ -72,7 +70,7 @@ config S3C2440_PLL_16934400
 
 config S3C2440_DMA
         bool
-        depends on ARCH_S3C2410 && CPU_S3C24405B
+        depends on CPU_S3C2440
         help
           Support for S3C2440 specific DMA code5A
 
@@ -181,7 +179,6 @@ config MACH_MINI2440
         select CPU_S3C2440
         select EEPROM_AT24
         select LEDS_TRIGGER_BACKLIGHT
-        select SND_S3C24XX_SOC_S3C24XX_UDA134X
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
         help
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 32019bd9db3b..e0622bbb6dfa 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -25,8 +25,12 @@
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <linux/sysdev.h>
+#include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/pwm.h>
+#include <linux/s3c_adc_battery.h>
+#include <linux/leds.h>
+#include <linux/i2c.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -55,6 +59,8 @@
 #include <plat/irq.h>
 #include <plat/ts.h>
 
+#include <sound/uda1380.h>
+
 #define LCD_PWM_PERIOD 192960
 #define LCD_PWM_DUTY 127353
 
@@ -127,6 +133,193 @@ static struct s3c2410fb_display rx1950_display = {
 
 };
 
+static int power_supply_init(struct device *dev)
+{
+        return gpio_request(S3C2410_GPF(2), "cable plugged");
+}
+
+static int rx1950_is_ac_online(void)
+{
+        return !gpio_get_value(S3C2410_GPF(2));
+}
+
+static void power_supply_exit(struct device *dev)
+{
+        gpio_free(S3C2410_GPF(2));
+}
+
+static char *rx1950_supplicants[] = {
+        "main-battery"
+};
+
+static struct pda_power_pdata power_supply_info = {
+        .init                   = power_supply_init,
+        .is_ac_online           = rx1950_is_ac_online,
+        .exit                   = power_supply_exit,
+        .supplied_to            = rx1950_supplicants,
+        .num_supplicants        = ARRAY_SIZE(rx1950_supplicants),
+};
+
+static struct resource power_supply_resources[] = {
+        [0] = {
+                        .name   = "ac",
+                        .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE |
+                                          IORESOURCE_IRQ_HIGHEDGE,
+                        .start  = IRQ_EINT2,
+                        .end    = IRQ_EINT2,
+        },
+};
+
+static struct platform_device power_supply = {
+        .name                   = "pda-power",
+        .id                     = -1,
+        .dev                    = {
+                                        .platform_data =
+                                                &power_supply_info,
+        },
+        .resource               = power_supply_resources,
+        .num_resources          = ARRAY_SIZE(power_supply_resources),
+};
+
+static const struct s3c_adc_bat_thresh bat_lut_noac[] = {
+        { .volt = 4100, .cur = 156, .level = 100},
+        { .volt = 4050, .cur = 156, .level = 95},
+        { .volt = 4025, .cur = 141, .level = 90},
+        { .volt = 3995, .cur = 144, .level = 85},
+        { .volt = 3957, .cur = 162, .level = 80},
+        { .volt = 3931, .cur = 147, .level = 75},
+        { .volt = 3902, .cur = 147, .level = 70},
+        { .volt = 3863, .cur = 153, .level = 65},
+        { .volt = 3838, .cur = 150, .level = 60},
+        { .volt = 3800, .cur = 153, .level = 55},
+        { .volt = 3765, .cur = 153, .level = 50},
+        { .volt = 3748, .cur = 172, .level = 45},
+        { .volt = 3740, .cur = 153, .level = 40},
+        { .volt = 3714, .cur = 175, .level = 35},
+        { .volt = 3710, .cur = 156, .level = 30},
+        { .volt = 3963, .cur = 156, .level = 25},
+        { .volt = 3672, .cur = 178, .level = 20},
+        { .volt = 3651, .cur = 178, .level = 15},
+        { .volt = 3629, .cur = 178, .level = 10},
+        { .volt = 3612, .cur = 162, .level = 5},
+        { .volt = 3605, .cur = 162, .level = 0},
+};
+
+static const struct s3c_adc_bat_thresh bat_lut_acin[] = {
+        { .volt = 4200, .cur = 0, .level = 100},
+        { .volt = 4190, .cur = 0, .level = 99},
+        { .volt = 4178, .cur = 0, .level = 95},
+        { .volt = 4110, .cur = 0, .level = 70},
+        { .volt = 4076, .cur = 0, .level = 65},
+        { .volt = 4046, .cur = 0, .level = 60},
+        { .volt = 4021, .cur = 0, .level = 55},
+        { .volt = 3999, .cur = 0, .level = 50},
+        { .volt = 3982, .cur = 0, .level = 45},
+        { .volt = 3965, .cur = 0, .level = 40},
+        { .volt = 3957, .cur = 0, .level = 35},
+        { .volt = 3948, .cur = 0, .level = 30},
+        { .volt = 3936, .cur = 0, .level = 25},
+        { .volt = 3927, .cur = 0, .level = 20},
+        { .volt = 3906, .cur = 0, .level = 15},
+        { .volt = 3880, .cur = 0, .level = 10},
+        { .volt = 3829, .cur = 0, .level = 5},
+        { .volt = 3820, .cur = 0, .level = 0},
+};
+
+int rx1950_bat_init(void)
+{
+        int ret;
+
+        ret = gpio_request(S3C2410_GPJ(2), "rx1950-charger-enable-1");
+        if (ret)
+                goto err_gpio1;
+        ret = gpio_request(S3C2410_GPJ(3), "rx1950-charger-enable-2");
+        if (ret)
+                goto err_gpio2;
+
+        return 0;
+
+err_gpio2:
+        gpio_free(S3C2410_GPJ(2));
+err_gpio1:
+        return ret;
+}
+
+void rx1950_bat_exit(void)
+{
+        gpio_free(S3C2410_GPJ(2));
+        gpio_free(S3C2410_GPJ(3));
+}
+
+void rx1950_enable_charger(void)
+{
+        gpio_direction_output(S3C2410_GPJ(2), 1);
+        gpio_direction_output(S3C2410_GPJ(3), 1);
+}
+
+void rx1950_disable_charger(void)
+{
+        gpio_direction_output(S3C2410_GPJ(2), 0);
+        gpio_direction_output(S3C2410_GPJ(3), 0);
+}
+
+static struct gpio_led rx1950_leds_desc[] = {
+        {
+                .name                           = "Green",
+                .default_trigger        = "main-battery-charging-or-full",
+                .gpio                           = S3C2410_GPA(6),
+        },
+        {
+                .name                           = "Red",
+                .default_trigger        = "main-battery-full",
+                .gpio                           = S3C2410_GPA(7),
+        },
+        {
+                .name                           = "Blue",
+                .default_trigger        = "rx1950-acx-mem",
+                .gpio                           = S3C2410_GPA(11),
+        },
+};
+
+static struct gpio_led_platform_data rx1950_leds_pdata = {
+        .num_leds       = ARRAY_SIZE(rx1950_leds_desc),
+        .leds           = rx1950_leds_desc,
+};
+
+static struct platform_device rx1950_leds = {
+        .name   = "leds-gpio",
+        .id             = -1,
+        .dev    = {
+                                .platform_data = &rx1950_leds_pdata,
+        },
+};
+
+static struct s3c_adc_bat_pdata rx1950_bat_cfg = {
+        .init = rx1950_bat_init,
+        .exit = rx1950_bat_exit,
+        .enable_charger = rx1950_enable_charger,
+        .disable_charger = rx1950_disable_charger,
+        .gpio_charge_finished = S3C2410_GPF(3),
+        .lut_noac = bat_lut_noac,
+        .lut_noac_cnt = ARRAY_SIZE(bat_lut_noac),
+        .lut_acin = bat_lut_acin,
+        .lut_acin_cnt = ARRAY_SIZE(bat_lut_acin),
+        .volt_channel = 0,
+        .current_channel = 1,
+        .volt_mult = 4235,
+        .current_mult = 2900,
+        .internal_impedance = 200,
+};
+
+static struct platform_device rx1950_battery = {
+        .name             = "s3c-adc-battery",
+        .id               = -1,
+        .dev = {
+                .parent = &s3c_device_adc.dev,
+                .platform_data = &rx1950_bat_cfg,
+        },
+};
+
 static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
         .displays = &rx1950_display,
         .num_displays = 1,
@@ -481,11 +674,17 @@ static struct platform_device rx1950_device_gpiokeys = {
         .dev.platform_data = &rx1950_gpio_keys_data,
 };
 
-static struct s3c2410_platform_i2c rx1950_i2c_data = {
-        .flags = 0,
-        .slave_addr = 0x42,
-        .frequency = 400 * 1000,
-        .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+static struct uda1380_platform_data uda1380_info = {
+        .gpio_power     = S3C2410_GPJ(0),
+        .gpio_reset     = S3C2410_GPD(0),
+        .dac_clk        = UDA1380_DAC_CLK_SYSCLK,
+};
+
+static struct i2c_board_info rx1950_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("uda1380", 0x1a),
+                .platform_data = &uda1380_info,
+        },
 };
 
 static struct platform_device *rx1950_devices[] __initdata = {
@@ -493,6 +692,7 @@ static struct platform_device *rx1950_devices[] __initdata = {
         &s3c_device_wdt,
         &s3c_device_i2c0,
         &s3c_device_iis,
+        &s3c_device_pcm,
         &s3c_device_usbgadget,
         &s3c_device_rtc,
         &s3c_device_nand,
@@ -503,6 +703,9 @@ static struct platform_device *rx1950_devices[] __initdata = {
         &s3c_device_timer[1],
         &rx1950_backlight,
         &rx1950_device_gpiokeys,
+        &power_supply,
+        &rx1950_battery,
+        &rx1950_leds,
 };
 
 static struct clk *rx1950_clocks[] __initdata = {
@@ -538,7 +741,7 @@ static void __init rx1950_init_machine(void)
         s3c24xx_udc_set_platdata(&rx1950_udc_cfg);
         s3c24xx_ts_set_platdata(&rx1950_ts_cfg);
         s3c24xx_mci_set_platdata(&rx1950_mmc_cfg);
-        s3c_i2c0_set_platdata(&rx1950_i2c_data);
+        s3c_i2c0_set_platdata(NULL);
         s3c_nand_set_platdata(&rx1950_nand_info);
 
         /* Turn off suspend on both USB ports, and switch the
@@ -569,6 +772,9 @@ static void __init rx1950_init_machine(void)
         WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power"));
 
         platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
+
+        i2c_register_board_info(0, rx1950_i2c_devices,
+                ARRAY_SIZE(rx1950_i2c_devices));
 }
 
 /* H1940 and RX3715 need to reserve this for suspend */
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
index 5e4a97e76533..90c1707b9c95 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -44,6 +44,7 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
 #include <plat/pll.h>
+#include <plat/nand-core.h>
 
 static struct map_desc s3c244x_iodesc[] __initdata = {
         IODESC_ENT(CLKPWR),
@@ -68,7 +69,7 @@ void __init s3c244x_map_io(void)
 
         s3c_device_sdi.name  = "s3c2440-sdi";
         s3c_device_i2c0.name  = "s3c2440-i2c";
-        s3c_device_nand.name = "s3c2440-nand";
+        s3c_nand_setname("s3c2440-nand");
         s3c_device_ts.name = "s3c2440-ts";
         s3c_device_usbgadget.name = "s3c2440-usbgadget";
 }
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index 839b6b2ced74..33d18dd1ebd5 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -36,6 +36,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb-core.h>
+#include <plat/nand-core.h>
 
 static struct map_desc s3c2443_iodesc[] __initdata = {
         IODESC_ENT(WATCHDOG),
@@ -62,7 +63,7 @@ int __init s3c2443_init(void)
 
         s3c24xx_reset_hook = s3c2443_hard_reset;
 
-        s3c_device_nand.name = "s3c2412-nand";
+        s3c_nand_setname("s3c2412-nand");
         s3c_fb_setname("s3c2443-fb");
 
         /* change WDT IRQ number */
diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
index 914656820794..6480b15277f3 100644
--- a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xe0000000UL)
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 1e4d78af7d84..579d2f0f4dd0 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -98,12 +98,33 @@ config MACH_ANW6410
         help
           Machine support for the A&W6410
 
+config MACH_MINI6410
+        bool "MINI6410"
+        select CPU_S3C6410
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C64XX_SETUP_SDHCI
+        select S3C_DEV_USB_HOST
+        select S3C_DEV_NAND
+        select S3C_DEV_FB
+        select S3C64XX_SETUP_FB_24BPP
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        help
+          Machine support for the FriendlyARM MINI6410
+
 config MACH_REAL6410
         bool "REAL6410"
         select CPU_S3C6410
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C64XX_SETUP_SDHCI
+        select S3C_DEV_FB
+        select S3C64XX_SETUP_FB_24BPP
+        select S3C_DEV_NAND
+        select SAMSUNG_DEV_ADC
+        select SAMSUNG_DEV_TS
+        select S3C_DEV_USB_HOST
         help
           Machine support for the CoreWind REAL6410
 
@@ -122,7 +143,7 @@ config MACH_SMDK6410
         select S3C_DEV_USB_HSOTG
         select S3C_DEV_WDT
         select SAMSUNG_DEV_KEYPAD
-        select HAVE_S3C2410_WATCHDOG
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select S3C64XX_SETUP_SDHCI
         select S3C64XX_SETUP_I2C1
         select S3C64XX_SETUP_IDE
@@ -185,6 +206,7 @@ config SMDK6410_WM1192_EV1
         select REGULATOR_WM831X
         select S3C24XX_GPIO_EXTRA64
         select MFD_WM831X
+        select MFD_WM831X_I2C
         help
           The Wolfson Microelectronics 1192-EV1 is a WM831x based PMIC
           daughtercard for the Samsung SMDK6410 reference platform.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 90221a2e0c55..4657363f0674 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_MACH_ANW6410)	+= mach-anw6410.o
 obj-$(CONFIG_MACH_SMDK6400)     += mach-smdk6400.o
 obj-$(CONFIG_MACH_SMDK6410)     += mach-smdk6410.o
 obj-$(CONFIG_MACH_REAL6410)     += mach-real6410.o
+obj-$(CONFIG_MACH_MINI6410)     += mach-mini6410.o
 obj-$(CONFIG_MACH_NCP)          += mach-ncp.o
 obj-$(CONFIG_MACH_HMT)          += mach-hmt.o
 obj-$(CONFIG_MACH_SMARTQ)       += mach-smartq.o
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index 3838335f125b..76426a32c013 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -22,27 +22,16 @@
 #include <plat/audio.h>
 #include <plat/gpio-cfg.h>
 
-#include <mach/gpio-bank-c.h>
-#include <mach/gpio-bank-d.h>
-#include <mach/gpio-bank-e.h>
-#include <mach/gpio-bank-h.h>
-
 static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
 {
+        unsigned int base;
+
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
-                s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
-                s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
+                base = S3C64XX_GPD(0);
                 break;
         case 1:
-                s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
-                s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
-                s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
+                base = S3C64XX_GPE(0);
                 break;
         default:
                 printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
@@ -50,18 +39,17 @@ static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
+
         return 0;
 }
 
 static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
 {
-        s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
-        s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
-        s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
-        s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
-        s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
-        s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
-        s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
+        s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
+        s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
+        s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
+        s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
 
         return 0;
 }
@@ -170,20 +158,14 @@ EXPORT_SYMBOL(s3c64xx_device_iisv4);
 
 static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
 {
+        unsigned int base;
+
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_PCM0_SCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_PCM0_EXTCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_PCM0_FSYNC);
-                s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_PCM0_SIN);
-                s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_PCM0_SOUT);
+                base = S3C64XX_GPD(0);
                 break;
         case 1:
-                s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_PCM1_SCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_PCM1_EXTCLK);
-                s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_PCM1_FSYNC);
-                s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_PCM1_SIN);
-                s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
+                base = S3C64XX_GPE(0);
                 break;
         default:
                 printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
@@ -191,6 +173,7 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
         return 0;
 }
 
@@ -264,24 +247,12 @@ EXPORT_SYMBOL(s3c64xx_device_pcm1);
 
 static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
 {
-        s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_AC97_BITCLK);
-        s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_AC97_nRESET);
-        s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_AC97_SYNC);
-        s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_AC97_SDI);
-        s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_AC97_SDO);
-
-        return 0;
+        return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
 }
 
 static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
 {
-        s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_AC97_BITCLK);
-        s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_AC97_nRESET);
-        s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_AC97_SYNC);
-        s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_AC97_SDI);
-        s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_AC97_SDO);
-
-        return 0;
+        return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
 }
 
 static struct resource s3c64xx_ac97_resource[] = {
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c
index 300dee4a667b..fd99a82e82c4 100644
--- a/arch/arm/mach-s3c64xx/gpiolib.c
+++ b/arch/arm/mach-s3c64xx/gpiolib.c
@@ -195,11 +195,6 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
         .get_pull       = s3c_gpio_getpull_updown,
 };
 
-int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
-{
-        return IRQ_EINT(0) + pin;
-}
-
 static struct s3c_gpio_chip gpio_2bit[] = {
         {
                 .base   = S3C64XX_GPF_BASE,
@@ -227,12 +222,13 @@ static struct s3c_gpio_chip gpio_2bit[] = {
                 },
         }, {
                 .base   = S3C64XX_GPN_BASE,
+                .irq_base = IRQ_EINT(0),
                 .config = &gpio_2bit_cfg_eint10,
                 .chip   = {
                         .base   = S3C64XX_GPN(0),
                         .ngpio  = S3C64XX_GPIO_N_NR,
                         .label  = "GPN",
-                        .to_irq = s3c64xx_gpio2int_gpn,
+                        .to_irq = samsung_gpiolib_to_irq,
                 },
         }, {
                 .base   = S3C64XX_GPO_BASE,
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
index bc0e91389864..23f75e556a30 100644
--- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END     0xE0000000UL
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
new file mode 100644
index 000000000000..249c62956471
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -0,0 +1,357 @@
+/* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
+ *
+ * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/dm9000.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/serial_core.h>
+#include <linux/types.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-modem.h>
+#include <mach/regs-srom.h>
+#include <mach/s3c6410.h>
+
+#include <plat/adc.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/nand.h>
+#include <plat/regs-serial.h>
+#include <plat/ts.h>
+
+#include <video/platform_lcd.h>
+
+#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport = 0,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
+        },
+        [1] = {
+                .hwport = 1,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
+        },
+        [2] = {
+                .hwport = 2,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
+        },
+        [3] = {
+                .hwport = 3,
+                .flags  = 0,
+                .ucon   = UCON,
+                .ulcon  = ULCON,
+                .ufcon  = UFCON,
+        },
+};
+
+/* DM9000AEP 10/100 ethernet controller */
+
+static struct resource mini6410_dm9k_resource[] = {
+        [0] = {
+                .start  = S3C64XX_PA_XM0CSN1,
+                .end    = S3C64XX_PA_XM0CSN1 + 1,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start  = S3C64XX_PA_XM0CSN1 + 4,
+                .end    = S3C64XX_PA_XM0CSN1 + 5,
+                .flags  = IORESOURCE_MEM
+        },
+        [2] = {
+                .start  = S3C_EINT(7),
+                .end    = S3C_EINT(7),
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
+        }
+};
+
+static struct dm9000_plat_data mini6410_dm9k_pdata = {
+        .flags          = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
+};
+
+static struct platform_device mini6410_device_eth = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mini6410_dm9k_resource),
+        .resource       = mini6410_dm9k_resource,
+        .dev            = {
+                .platform_data  = &mini6410_dm9k_pdata,
+        },
+};
+
+static struct mtd_partition mini6410_nand_part[] = {
+        [0] = {
+                .name   = "uboot",
+                .size   = SZ_1M,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "kernel",
+                .size   = SZ_2M,
+                .offset = SZ_1M,
+        },
+        [2] = {
+                .name   = "rootfs",
+                .size   = MTDPART_SIZ_FULL,
+                .offset = SZ_1M + SZ_2M,
+        },
+};
+
+static struct s3c2410_nand_set mini6410_nand_sets[] = {
+        [0] = {
+                .name           = "nand",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(mini6410_nand_part),
+                .partitions     = mini6410_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand mini6410_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .nr_sets        = ARRAY_SIZE(mini6410_nand_sets),
+        .sets           = mini6410_nand_sets,
+};
+
+static struct s3c_fb_pd_win mini6410_fb_win[] = {
+        {
+                .win_mode       = {     /* 4.3" 480x272 */
+                        .left_margin    = 3,
+                        .right_margin   = 2,
+                        .upper_margin   = 1,
+                        .lower_margin   = 1,
+                        .hsync_len      = 40,
+                        .vsync_len      = 1,
+                        .xres           = 480,
+                        .yres           = 272,
+                },
+                .max_bpp        = 32,
+                .default_bpp    = 16,
+        }, {
+                .win_mode       = {     /* 7.0" 800x480 */
+                        .left_margin    = 8,
+                        .right_margin   = 13,
+                        .upper_margin   = 7,
+                        .lower_margin   = 5,
+                        .hsync_len      = 3,
+                        .vsync_len      = 1,
+                        .xres           = 800,
+                        .yres           = 480,
+                },
+                .max_bpp        = 32,
+                .default_bpp    = 16,
+        },
+};
+
+static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
+        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
+        .win[0]         = &mini6410_fb_win[0],
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(S3C64XX_GPE(0), 1);
+        else
+                gpio_direction_output(S3C64XX_GPE(0), 0);
+}
+
+static struct plat_lcd_data mini6410_lcd_power_data = {
+        .set_power      = mini6410_lcd_power_set,
+};
+
+static struct platform_device mini6410_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &mini6410_lcd_power_data,
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
+};
+
+static struct platform_device *mini6410_devices[] __initdata = {
+        &mini6410_device_eth,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_ohci,
+        &s3c_device_nand,
+        &s3c_device_fb,
+        &mini6410_lcd_powerdev,
+        &s3c_device_adc,
+        &s3c_device_ts,
+};
+
+static void __init mini6410_map_io(void)
+{
+        u32 tmp;
+
+        s3c64xx_init_io(NULL, 0);
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
+
+        /* set the LCD type */
+        tmp = __raw_readl(S3C64XX_SPCON);
+        tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+        tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+        __raw_writel(tmp, S3C64XX_SPCON);
+
+        /* remove the LCD bypass */
+        tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+        tmp &= ~MIFPCON_LCD_BYPASS;
+        __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+/*
+ * mini6410_features string
+ *
+ * 0-9 LCD configuration
+ *
+ */
+static char mini6410_features_str[12] __initdata = "0";
+
+static int __init mini6410_features_setup(char *str)
+{
+        if (str)
+                strlcpy(mini6410_features_str, str,
+                        sizeof(mini6410_features_str));
+        return 1;
+}
+
+__setup("mini6410=", mini6410_features_setup);
+
+#define FEATURE_SCREEN (1 << 0)
+
+struct mini6410_features_t {
+        int done;
+        int lcd_index;
+};
+
+static void mini6410_parse_features(
+                struct mini6410_features_t *features,
+                const char *features_str)
+{
+        const char *fp = features_str;
+
+        features->done = 0;
+        features->lcd_index = 0;
+
+        while (*fp) {
+                char f = *fp++;
+
+                switch (f) {
+                case '0'...'9': /* tft screen */
+                        if (features->done & FEATURE_SCREEN) {
+                                printk(KERN_INFO "MINI6410: '%c' ignored, "
+                                        "screen type already set\n", f);
+                        } else {
+                                int li = f - '0';
+                                if (li >= ARRAY_SIZE(mini6410_fb_win))
+                                        printk(KERN_INFO "MINI6410: '%c' out "
+                                                "of range LCD mode\n", f);
+                                else {
+                                        features->lcd_index = li;
+                                }
+                        }
+                        features->done |= FEATURE_SCREEN;
+                        break;
+                }
+        }
+}
+
+static void __init mini6410_machine_init(void)
+{
+        u32 cs1;
+        struct mini6410_features_t features = { 0 };
+
+        printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
+                        mini6410_features_str);
+
+        /* Parse the feature string */
+        mini6410_parse_features(&features, mini6410_features_str);
+
+        mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
+
+        printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
+                mini6410_lcd_pdata.win[0]->win_mode.xres,
+                mini6410_lcd_pdata.win[0]->win_mode.yres);
+
+        s3c_nand_set_platdata(&mini6410_nand_info);
+        s3c_fb_set_platdata(&mini6410_lcd_pdata);
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
+        /* configure nCS1 width to 16 bits */
+
+        cs1 = __raw_readl(S3C64XX_SROM_BW) &
+                ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
+        cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
+                (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
+                (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
+                        S3C64XX_SROM_BW__NCS1__SHIFT;
+        __raw_writel(cs1, S3C64XX_SROM_BW);
+
+        /* set timing for nCS1 suitable for ethernet chip */
+
+        __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
+                (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
+                (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
+                (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
+                (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
+                (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
+                (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
+
+        gpio_request(S3C64XX_GPF(15), "LCD power");
+        gpio_request(S3C64XX_GPE(0), "LCD power");
+
+        platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
+}
+
+MACHINE_START(MINI6410, "MINI6410")
+        /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6410_init_irq,
+        .map_io         = mini6410_map_io,
+        .init_machine   = mini6410_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 4b4475da8ec6..f9ef9b5c5f5a 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -12,23 +12,39 @@
  *
 */
 
-#include <linux/kernel.h>
-#include <linux/types.h>
+#include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
 #include <linux/list.h>
-#include <linux/init.h>
 #include <linux/dm9000.h>
-#include <linux/serial_core.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
 #include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/types.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+
 #include <mach/map.h>
-#include <mach/s3c6410.h>
+#include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-modem.h>
 #include <mach/regs-srom.h>
+#include <mach/s3c6410.h>
+
+#include <plat/adc.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
+#include <plat/nand.h>
 #include <plat/regs-serial.h>
+#include <plat/ts.h>
+
+#include <video/platform_lcd.h>
 
 #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -99,22 +115,192 @@ static struct platform_device real6410_device_eth = {
         },
 };
 
+static struct s3c_fb_pd_win real6410_fb_win[] = {
+        {
+                .win_mode       = {     /* 4.3" 480x272 */
+                        .left_margin    = 3,
+                        .right_margin   = 2,
+                        .upper_margin   = 1,
+                        .lower_margin   = 1,
+                        .hsync_len      = 40,
+                        .vsync_len      = 1,
+                        .xres           = 480,
+                        .yres           = 272,
+                },
+                .max_bpp        = 32,
+                .default_bpp    = 16,
+        }, {
+                .win_mode       = {     /* 7.0" 800x480 */
+                        .left_margin    = 8,
+                        .right_margin   = 13,
+                        .upper_margin   = 7,
+                        .lower_margin   = 5,
+                        .hsync_len      = 3,
+                        .vsync_len      = 1,
+                        .xres           = 800,
+                        .yres           = 480,
+                },
+                .max_bpp        = 32,
+                .default_bpp    = 16,
+        },
+};
+
+static struct s3c_fb_platdata real6410_lcd_pdata __initdata = {
+        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
+        .win[0]         = &real6410_fb_win[0],
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+static struct mtd_partition real6410_nand_part[] = {
+        [0] = {
+                .name   = "uboot",
+                .size   = SZ_1M,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "kernel",
+                .size   = SZ_2M,
+                .offset = SZ_1M,
+        },
+        [2] = {
+                .name   = "rootfs",
+                .size   = MTDPART_SIZ_FULL,
+                .offset = SZ_1M + SZ_2M,
+        },
+};
+
+static struct s3c2410_nand_set real6410_nand_sets[] = {
+        [0] = {
+                .name           = "nand",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(real6410_nand_part),
+                .partitions     = real6410_nand_part,
+        },
+};
+
+static struct s3c2410_platform_nand real6410_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .nr_sets        = ARRAY_SIZE(real6410_nand_sets),
+        .sets           = real6410_nand_sets,
+};
+
 static struct platform_device *real6410_devices[] __initdata = {
         &real6410_device_eth,
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
+        &s3c_device_fb,
+        &s3c_device_nand,
+        &s3c_device_adc,
+        &s3c_device_ts,
+        &s3c_device_ohci,
+};
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+        .delay                  = 10000,
+        .presc                  = 49,
+        .oversampling_shift     = 2,
 };
 
 static void __init real6410_map_io(void)
 {
+        u32 tmp;
+
         s3c64xx_init_io(NULL, 0);
         s3c24xx_init_clocks(12000000);
         s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
+
+        /* set the LCD type */
+        tmp = __raw_readl(S3C64XX_SPCON);
+        tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
+        tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
+        __raw_writel(tmp, S3C64XX_SPCON);
+
+        /* remove the LCD bypass */
+        tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
+        tmp &= ~MIFPCON_LCD_BYPASS;
+        __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
+}
+
+/*
+ * real6410_features string
+ *
+ * 0-9 LCD configuration
+ *
+ */
+static char real6410_features_str[12] __initdata = "0";
+
+static int __init real6410_features_setup(char *str)
+{
+        if (str)
+                strlcpy(real6410_features_str, str,
+                        sizeof(real6410_features_str));
+        return 1;
+}
+
+__setup("real6410=", real6410_features_setup);
+
+#define FEATURE_SCREEN (1 << 0)
+
+struct real6410_features_t {
+        int done;
+        int lcd_index;
+};
+
+static void real6410_parse_features(
+                struct real6410_features_t *features,
+                const char *features_str)
+{
+        const char *fp = features_str;
+
+        features->done = 0;
+        features->lcd_index = 0;
+
+        while (*fp) {
+                char f = *fp++;
+
+                switch (f) {
+                case '0'...'9': /* tft screen */
+                        if (features->done & FEATURE_SCREEN) {
+                                printk(KERN_INFO "REAL6410: '%c' ignored, "
+                                        "screen type already set\n", f);
+                        } else {
+                                int li = f - '0';
+                                if (li >= ARRAY_SIZE(real6410_fb_win))
+                                        printk(KERN_INFO "REAL6410: '%c' out "
+                                                "of range LCD mode\n", f);
+                                else {
+                                        features->lcd_index = li;
+                                }
+                        }
+                        features->done |= FEATURE_SCREEN;
+                        break;
+                }
+        }
 }
 
 static void __init real6410_machine_init(void)
 {
         u32 cs1;
+        struct real6410_features_t features = { 0 };
+
+        printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
+                        real6410_features_str);
+
+        /* Parse the feature string */
+        real6410_parse_features(&features, real6410_features_str);
+
+        real6410_lcd_pdata.win[0] = &real6410_fb_win[features.lcd_index];
+
+        printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
+                real6410_lcd_pdata.win[0]->win_mode.xres,
+                real6410_lcd_pdata.win[0]->win_mode.yres);
+
+        s3c_fb_set_platdata(&real6410_lcd_pdata);
+        s3c_nand_set_platdata(&real6410_nand_info);
+        s3c24xx_ts_set_platdata(&s3c_ts_platform);
 
         /* configure nCS1 width to 16 bits */
 
@@ -136,6 +322,8 @@ static void __init real6410_machine_init(void)
                 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
                 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
 
+        gpio_request(S3C64XX_GPF(15), "LCD power");
+
         platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
 }
 
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
index 000736877df2..8f3091182f9c 100644
--- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
+++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
@@ -23,15 +23,6 @@
 
 extern void s3c64xx_fb_gpio_setup_24bpp(void)
 {
-        unsigned int gpio;
-
-        for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
-
-        for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPI(0), 16, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPJ(0), 12, S3C_GPIO_SFN(2));
 }
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c
index c12c315f33bc..41b425602d88 100644
--- a/arch/arm/mach-s3c64xx/setup-ide.c
+++ b/arch/arm/mach-s3c64xx/setup-ide.c
@@ -17,11 +17,11 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
+#include <plat/ata.h>
 
 void s3c64xx_ide_setup_gpio(void)
 {
         u32 reg;
-        u32 gpio = 0;
 
         reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
 
@@ -32,15 +32,12 @@ void s3c64xx_ide_setup_gpio(void)
         s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
 
         /* Set XhiDATA[15:0] pins as CF Data[15:0] */
-        for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
+        s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
 
         /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
-        for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+        s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
 
         /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
         s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
-        for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+        s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
 }
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c
index abc34e4e1a93..f8ed0d22db70 100644
--- a/arch/arm/mach-s3c64xx/setup-keypad.c
+++ b/arch/arm/mach-s3c64xx/setup-keypad.c
@@ -12,23 +12,13 @@
 
 #include <linux/gpio.h>
 #include <plat/gpio-cfg.h>
+#include <plat/keypad.h>
 
 void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 {
-        unsigned int gpio;
-        unsigned int end;
-
         /* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
-        end = S3C64XX_GPK(8 + rows);
-        for (gpio = S3C64XX_GPK(8); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
 
         /* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
-        end = S3C64XX_GPL(0 + cols);
-        for (gpio = S3C64XX_GPL(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));
 }
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
index 322359591374..6eac071afae2 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
@@ -24,16 +24,9 @@
 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        unsigned int end;
 
-        end = S3C64XX_GPG(2 + width);
-
-        /* Set all the necessary GPG pins to special-function 0 */
-        for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        /* Set all the necessary GPG pins to special-function 2 */
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
                 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
@@ -44,16 +37,9 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        unsigned int end;
 
-        end = S3C64XX_GPH(2 + width);
-
-        /* Set all the necessary GPG pins to special-function 0 */
-        for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        /* Set all the necessary GPH pins to special-function 2 */
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2));
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
                 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
@@ -63,20 +49,9 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 
 void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
-        unsigned int gpio;
-        unsigned int end;
+        /* Set all the necessary GPH pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3));
 
-        end = S3C64XX_GPH(6 + width);
-
-        /* Set all the necessary GPH pins to special-function 1 */
-        for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
-
-        /* Set all the necessary GPC pins to special-function 1 */
-        for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        /* Set all the necessary GPC pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3));
 }
diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig
index 0fda0a5df968..33569e4007c4 100644
--- a/arch/arm/mach-s5p6442/Kconfig
+++ b/arch/arm/mach-s5p6442/Kconfig
@@ -11,7 +11,6 @@ if ARCH_S5P6442
 
 config CPU_S5P6442
         bool
-        select PLAT_S5P
         select S3C_PL330_DMA
         help
           Enable S5P6442 CPU support
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
index dcd20f17212a..16d6e7e61b50 100644
--- a/arch/arm/mach-s5p6442/clock.c
+++ b/arch/arm/mach-s5p6442/clock.c
@@ -192,6 +192,11 @@ static struct clk clk_pclkd1 = {
         .parent         = &clk_hclkd1,
 };
 
+int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
+}
+
 int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
@@ -335,6 +340,16 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
         clk_pclkd1.rate = pclkd1;
 }
 
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "pdma",
+                .id             = -1,
+                .parent         = &clk_pclkd1,
+                .enable         = s5p6442_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 3),
+        },
+};
+
 static struct clk init_clocks[] = {
         {
                 .name           = "systimer",
@@ -393,10 +408,23 @@ static struct clk *clks[] __initdata = {
 
 void __init s5p6442_register_clocks(void)
 {
+        struct clk *clkptr;
+        int i, ret;
+
         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 
         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
+        clkptr = init_clocks_disable;
+        for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {
+                ret = s3c24xx_register_clock(clkptr);
+                if (ret < 0) {
+                        printk(KERN_ERR "Fail to register clock %s (%d)\n",
+                                        clkptr->name, ret);
+                } else
+                        (clkptr->enable)(clkptr, 0);
+        }
+
         s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c
index 7a4e34720b7b..3462197ff352 100644
--- a/arch/arm/mach-s5p6442/dev-audio.c
+++ b/arch/arm/mach-s5p6442/dev-audio.c
@@ -21,22 +21,16 @@
 
 static int s5p6442_cfg_i2s(struct platform_device *pdev)
 {
+        unsigned int base;
+
         /* configure GPIO for i2s port */
         switch (pdev->id) {
         case 1:
-                s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2));
+                base = S5P6442_GPC1(0);
                 break;
 
         case -1:
-                s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2));
+                base = S5P6442_GPC0(0);
                 break;
 
         default:
@@ -44,6 +38,7 @@ static int s5p6442_cfg_i2s(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
         return 0;
 }
 
@@ -111,21 +106,15 @@ struct platform_device s5p6442_device_iis1 = {
 
 static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
 {
+        unsigned int base;
+
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3));
+                base = S5P6442_GPC0(0);
                 break;
 
         case 1:
-                s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3));
+                base = S5P6442_GPC1(0);
                 break;
 
         default:
@@ -133,6 +122,7 @@ static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
         return 0;
 }
 
diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c
index e894651a88bd..cce8c2470709 100644
--- a/arch/arm/mach-s5p6442/dev-spi.c
+++ b/arch/arm/mach-s5p6442/dev-spi.c
@@ -38,11 +38,9 @@ static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
         switch (pdev->id) {
         case 0:
                 s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2));
                 s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
+                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
                 break;
 
         default:
diff --git a/arch/arm/mach-s5p6442/dma.c b/arch/arm/mach-s5p6442/dma.c
index ad4f8704b93d..7dfb13654f8a 100644
--- a/arch/arm/mach-s5p6442/dma.c
+++ b/arch/arm/mach-s5p6442/dma.c
@@ -82,7 +82,7 @@ static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
 
 static struct platform_device s5p6442_device_pdma = {
         .name           = "s3c-pl330",
-        .id             = 1,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(s5p6442_pdma_resource),
         .resource       = s5p6442_pdma_resource,
         .dev            = {
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
index d8360b5d4ece..00828a336991 100644
--- a/arch/arm/mach-s5p6442/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
@@ -46,6 +46,7 @@
 #define S5P_CLK_DIV5            S5P_CLKREG(0x314)
 #define S5P_CLK_DIV6            S5P_CLKREG(0x318)
 
+#define S5P_CLKGATE_IP0         S5P_CLKREG(0x460)
 #define S5P_CLKGATE_IP3         S5P_CLKREG(0x46C)
 
 /* CLK_OUT */
diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
index f5c83f02c18e..4aa55e55ac47 100644
--- a/arch/arm/mach-s5p6442/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END     0xE0000000UL
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index fbcae9352022..164d2783d381 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -9,14 +9,12 @@ if ARCH_S5P64X0
 
 config CPU_S5P6440
         bool
-        select PLAT_S5P
         select S3C_PL330_DMA
         help
           Enable S5P6440 CPU support
 
 config CPU_S5P6450
         bool
-        select PLAT_S5P
         select S3C_PL330_DMA
         help
           Enable S5P6450 CPU support
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index f93dcd8b4d6a..e4883dc1c8d7 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -79,13 +79,16 @@ static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
         __raw_writel(epll_con, S5P64X0_EPLL_CON);
         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
 
+        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+                        clk->rate, rate);
+
         clk->rate = rate;
 
         return 0;
 }
 
 static struct clk_ops s5p6440_epll_ops = {
-        .get_rate = s5p64x0_epll_get_rate,
+        .get_rate = s5p_epll_get_rate,
         .set_rate = s5p6440_epll_set_rate,
 };
 
@@ -150,6 +153,12 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 8),
         }, {
+                .name           = "pdma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
                 .name           = "hsmmc",
                 .id             = 0,
                 .parent         = &clk_hclk_low.clk,
@@ -331,12 +340,6 @@ static struct clk init_clocks[] = {
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
-                .name           = "dma",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
                 .name           = "uart",
                 .id             = 0,
                 .parent         = &clk_pclk_low.clk,
@@ -548,7 +551,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
 
         /* Set S5P6440 functions for clk_fout_epll */
 
-        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.enable = s5p_epll_enable;
         clk_fout_epll.ops = &s5p6440_epll_ops;
 
         clk_48m.enable = s5p64x0_clk48m_ctrl;
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index f9afb05b217c..7dbf3c968f53 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -80,13 +80,16 @@ static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
         __raw_writel(epll_con, S5P64X0_EPLL_CON);
         __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
 
+        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+                        clk->rate, rate);
+
         clk->rate = rate;
 
         return 0;
 }
 
 static struct clk_ops s5p6450_epll_ops = {
-        .get_rate = s5p64x0_epll_get_rate,
+        .get_rate = s5p_epll_get_rate,
         .set_rate = s5p6450_epll_set_rate,
 };
 
@@ -186,6 +189,12 @@ static struct clk init_clocks_disable[] = {
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
+                .name           = "pdma",
+                .id             = -1,
+                .parent         = &clk_hclk_low.clk,
+                .enable         = s5p64x0_hclk0_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
                 .name           = "hsmmc",
                 .id             = 0,
                 .parent         = &clk_hclk_low.clk,
@@ -283,12 +292,6 @@ static struct clk init_clocks[] = {
                 .enable         = s5p64x0_hclk0_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
-                .name           = "dma",
-                .id             = -1,
-                .parent         = &clk_hclk_low.clk,
-                .enable         = s5p64x0_hclk0_ctrl,
-                .ctrlbit        = (1 << 12),
-        }, {
                 .name           = "uart",
                 .id             = 0,
                 .parent         = &clk_pclk_low.clk,
@@ -581,7 +584,7 @@ void __init_or_cpufreq s5p6450_setup_clocks(void)
 
         /* Set S5P6450 functions for clk_fout_epll */
 
-        clk_fout_epll.enable = s5p64x0_epll_enable;
+        clk_fout_epll.enable = s5p_epll_enable;
         clk_fout_epll.ops = &s5p6450_epll_ops;
 
         clk_48m.enable = s5p64x0_clk48m_ctrl;
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index 523ba8039ac2..b52c6e2f37a6 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -73,24 +73,6 @@ static const u32 clock_table[][3] = {
         {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
 };
 
-int s5p64x0_epll_enable(struct clk *clk, int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
-
-        if (enable)
-                __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
-        else
-                __raw_writel(epll_con, S5P64X0_EPLL_CON);
-
-        return 0;
-}
-
-unsigned long s5p64x0_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
 unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
 {
         unsigned long rate = clk_get_rate(clk->parent);
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
index fa097bd68ca4..396bacc0a39a 100644
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -24,13 +24,8 @@ static int s5p6440_cfg_i2s(struct platform_device *pdev)
         /* configure GPIO for i2s port */
         switch (pdev->id) {
         case -1:
-                s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6440_GPR(4), 5, S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(5));
                 break;
 
         default:
@@ -47,13 +42,9 @@ static int s5p6450_cfg_i2s(struct platform_device *pdev)
         switch (pdev->id) {
         case -1:
                 s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
+
                 break;
 
         default:
@@ -116,11 +107,8 @@ static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
 {
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2));
                 break;
 
         default:
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
index 5b69ec4c8af3..e78ee18c76e3 100644
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -39,23 +39,15 @@ static char *s5p64x0_spi_src_clks[] = {
  */
 static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
 {
+        unsigned int base;
+
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
+                base = S5P6440_GPC(0);
                 break;
 
         case 1:
-                s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
+                base = S5P6440_GPC(4);
                 break;
 
         default:
@@ -63,28 +55,23 @@ static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgall_range(base, 3,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
         return 0;
 }
 
 static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
 {
+        unsigned int base;
+
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
+                base = S5P6450_GPC(0);
                 break;
 
         case 1:
-                s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
+                base = S5P6450_GPC(4);
                 break;
 
         default:
@@ -92,6 +79,9 @@ static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgall_range(base, 3,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 29a8c2410049..d7ad944b3475 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -122,7 +122,7 @@ static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
 
 static struct platform_device s5p64x0_device_pdma = {
         .name           = "s3c-pl330",
-        .id             = 0,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(s5p64x0_pdma_resource),
         .resource       = s5p64x0_pdma_resource,
         .dev            = {
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
index 58e1bc813804..a133f22fa155 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -60,4 +60,6 @@
 #define ARM_DIV_RATIO_SHIFT             0
 #define ARM_DIV_MASK                    (0xF << ARM_DIV_RATIO_SHIFT)
 
+#define S5P_EPLL_CON                    S5P64X0_EPLL_CON
+
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
index 97a9df38f1cf..38dcc71a03cc 100644
--- a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END     0xE0000000UL
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index dc4cc65a5019..46b463917c54 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -25,18 +25,14 @@ struct platform_device; /* don't need the contents */
 
 void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5P6440_GPB(5), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
 
 void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5P6450_GPB(5), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index 2edd7912f8e4..6ad3b986021c 100644
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -25,18 +25,14 @@ struct platform_device; /* don't need the contents */
 
 void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
-        s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
-        s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5P6440_GPR(9), 2,
+                              S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
 }
 
 void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
-        s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
-        s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5P6450_GPR(9), 2,
+                              S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
 }
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 77ae4bfb74ba..b8fbf2fcba6f 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -9,7 +9,6 @@ if ARCH_S5PC100
 
 config CPU_S5PC100
         bool
-        select PLAT_S5P
         select S5P_EXT_INT
         select S3C_PL330_DMA
         help
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index a021ed1fb4b6..eecab57d2e5d 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,7 +11,7 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)       += cpu.o init.o clock.o gpiolib.o irq-gpio.o
+obj-$(CONFIG_CPU_S5PC100)       += cpu.o init.o clock.o gpiolib.o
 obj-$(CONFIG_CPU_S5PC100)       += setup-i2c0.o
 obj-$(CONFIG_CPU_S5PC100)       += dma.o
 
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 084abd13b0a5..2d4a761a5163 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -273,24 +273,6 @@ static struct clksrc_clk clk_div_hdmi = {
         .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
 };
 
-static int s5pc100_epll_enable(struct clk *clk, int enable)
-{
-        unsigned int ctrlbit = clk->ctrlbit;
-        unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
-
-        if (enable)
-                __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
-        else
-                __raw_writel(epll_con, S5P_EPLL_CON);
-
-        return 0;
-}
-
-static unsigned long s5pc100_epll_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
 static u32 epll_div[][4] = {
         { 32750000,     131, 3, 4 },
         { 32768000,     131, 3, 4 },
@@ -341,13 +323,16 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
 
         __raw_writel(epll_con, S5P_EPLL_CON);
 
+        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+                        clk->rate, rate);
+
         clk->rate = rate;
 
         return 0;
 }
 
 static struct clk_ops s5pc100_epll_ops = {
-        .get_rate = s5pc100_epll_get_rate,
+        .get_rate = s5p_epll_get_rate,
         .set_rate = s5pc100_epll_set_rate,
 };
 
@@ -691,55 +676,55 @@ static struct clk init_clocks_disable[] = {
         }, {
                 .name           = "iis",
                 .id             = 0,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 0),
         }, {
                 .name           = "iis",
                 .id             = 1,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 1),
         }, {
                 .name           = "iis",
                 .id             = 2,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 2),
         }, {
                 .name           = "ac97",
                 .id             = -1,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "pcm",
                 .id             = 0,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 4),
         }, {
                 .name           = "pcm",
                 .id             = 1,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 5),
         }, {
                 .name           = "spdif",
                 .id             = -1,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
                 .name           = "adc",
                 .id             = -1,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
                 .name           = "keypad",
                 .id             = -1,
-                .parent         = &clk_div_d1_bus.clk,
+                .parent         = &clk_div_pclkd1.clk,
                 .enable         = s5pc100_d1_5_ctrl,
                 .ctrlbit        = (1 << 8),
         }, {
@@ -848,6 +833,18 @@ struct clksrc_sources clk_src_group3 = {
         .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
 };
 
+static struct clksrc_clk clk_sclk_audio0 = {
+        .clk    = {
+                .name           = "sclk_audio",
+                .id             = 0,
+                .ctrlbit        = (1 << 8),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_group3,
+        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+
 static struct clk *clk_src_group4_list[] = {
         [0] = &clk_mout_epll.clk,
         [1] = &clk_div_mpll.clk,
@@ -862,6 +859,18 @@ struct clksrc_sources clk_src_group4 = {
         .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
 };
 
+static struct clksrc_clk clk_sclk_audio1 = {
+        .clk    = {
+                .name           = "sclk_audio",
+                .id             = 1,
+                .ctrlbit        = (1 << 9),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_group4,
+        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
+};
+
 static struct clk *clk_src_group5_list[] = {
         [0] = &clk_mout_epll.clk,
         [1] = &clk_div_mpll.clk,
@@ -875,6 +884,18 @@ struct clksrc_sources clk_src_group5 = {
         .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
 };
 
+static struct clksrc_clk clk_sclk_audio2 = {
+        .clk    = {
+                .name           = "sclk_audio",
+                .id             = 2,
+                .ctrlbit        = (1 << 10),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_group5,
+        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
+};
+
 static struct clk *clk_src_group6_list[] = {
         [0] = &s5p_clk_27m,
         [1] = &clk_vclk54m,
@@ -944,6 +965,64 @@ struct clksrc_sources clk_src_pwi = {
         .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
 };
 
+static struct clk *clk_sclk_spdif_list[] = {
+        [0] = &clk_sclk_audio0.clk,
+        [1] = &clk_sclk_audio1.clk,
+        [2] = &clk_sclk_audio2.clk,
+};
+
+struct clksrc_sources clk_src_sclk_spdif = {
+        .sources        = clk_sclk_spdif_list,
+        .nr_sources     = ARRAY_SIZE(clk_sclk_spdif_list),
+};
+
+static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct clk *pclk;
+        int ret;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        ret = pclk->ops->set_rate(pclk, rate);
+        clk_put(pclk);
+
+        return ret;
+}
+
+static unsigned long s5pc100_spdif_get_rate(struct clk *clk)
+{
+        struct clk *pclk;
+        int rate;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        rate = pclk->ops->get_rate(clk);
+        clk_put(pclk);
+
+        return rate;
+}
+
+static struct clk_ops s5pc100_sclk_spdif_ops = {
+        .set_rate       = s5pc100_spdif_set_rate,
+        .get_rate       = s5pc100_spdif_get_rate,
+};
+
+static struct clksrc_clk clk_sclk_spdif = {
+        .clk    = {
+                .name           = "sclk_spdif",
+                .id             = -1,
+                .ctrlbit        = (1 << 11),
+                .enable         = s5pc100_sclk1_ctrl,
+                .ops            = &s5pc100_sclk_spdif_ops,
+        },
+        .sources = &clk_src_sclk_spdif,
+        .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
+};
+
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
@@ -1001,39 +1080,6 @@ static struct clksrc_clk clksrcs[] = {
                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
         }, {
                 .clk    = {
-                        .name           = "sclk_audio",
-                        .id             = 0,
-                        .ctrlbit        = (1 << 8),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_group3,
-                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_audio",
-                        .id             = 1,
-                        .ctrlbit        = (1 << 9),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_group4,
-                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_audio",
-                        .id             = 2,
-                        .ctrlbit        = (1 << 10),
-                        .enable         = s5pc100_sclk1_ctrl,
-
-                },
-                .sources = &clk_src_group5,
-                .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_lcd",
                         .id             = -1,
                         .ctrlbit        = (1 << 0),
@@ -1179,6 +1225,10 @@ static struct clksrc_clk *sysclks[] = {
         &clk_div_pclkd1,
         &clk_div_cam,
         &clk_div_hdmi,
+        &clk_sclk_audio0,
+        &clk_sclk_audio1,
+        &clk_sclk_audio2,
+        &clk_sclk_spdif,
 };
 
 void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1196,7 +1246,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
         unsigned int ptr;
 
         /* Set S5PC100 functions for clk_fout_epll */
-        clk_fout_epll.enable = s5pc100_epll_enable;
+        clk_fout_epll.enable = s5p_epll_enable;
         clk_fout_epll.ops = &s5pc100_epll_ops;
 
         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
index a699ed6acc23..564e195ec493 100644
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -24,19 +24,11 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev)
         /* configure GPIO for i2s port */
         switch (pdev->id) {
         case 1:
-                s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
                 break;
 
         case 2:
-                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
                 break;
 
         case -1: /* Dedicated pins */
@@ -144,19 +136,11 @@ static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
 {
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5));
-                s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5));
+                s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
                 break;
 
         case 1:
-                s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
                 break;
 
         default:
@@ -231,13 +215,7 @@ struct platform_device s5pc100_device_pcm1 = {
 
 static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
 {
-        s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4));
-
-        return 0;
+        return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
 }
 
 static struct resource s5pc100_ac97_resource[] = {
@@ -285,3 +263,57 @@ struct platform_device s5pc100_device_ac97 = {
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
 };
+
+/* S/PDIF Controller platform_device */
+static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev)
+{
+        s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3));
+
+        return 0;
+}
+
+static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
+{
+        s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
+
+        return 0;
+}
+
+static struct resource s5pc100_spdif_resource[] = {
+        [0] = {
+                .start  = S5PC100_PA_SPDIF,
+                .end    = S5PC100_PA_SPDIF + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPDIF,
+                .end    = DMACH_SPDIF,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct s3c_audio_pdata s5p_spdif_pdata = {
+        .cfg_gpio = s5pc100_spdif_cfg_gpd,
+};
+
+static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pc100_device_spdif = {
+        .name           = "samsung-spdif",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5pc100_spdif_resource),
+        .resource       = s5pc100_spdif_resource,
+        .dev = {
+                .platform_data = &s5p_spdif_pdata,
+                .dma_mask = &s5pc100_spdif_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+void __init s5pc100_spdif_setup_gpio(int gpio)
+{
+        if (gpio == S5PC100_SPDIF_GPD)
+                s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd;
+        else
+                s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3;
+}
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
index a0ef7c302c16..57b19794d9bb 100644
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ b/arch/arm/mach-s5pc100/dev-spi.c
@@ -38,30 +38,20 @@ static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
 {
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
+                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
                 break;
 
         case 1:
-                s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
+                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
                 break;
 
         case 2:
                 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3));
                 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP);
+                s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
+                                      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
                 break;
 
         default:
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index 0f5517571e2c..bf4cd0fb97c6 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -81,7 +81,7 @@ static struct s3c_pl330_platdata s5pc100_pdma0_pdata = {
 
 static struct platform_device s5pc100_device_pdma0 = {
         .name           = "s3c-pl330",
-        .id             = 1,
+        .id             = 0,
         .num_resources  = ARRAY_SIZE(s5pc100_pdma0_resource),
         .resource       = s5pc100_pdma0_resource,
         .dev            = {
@@ -143,7 +143,7 @@ static struct s3c_pl330_platdata s5pc100_pdma1_pdata = {
 
 static struct platform_device s5pc100_device_pdma1 = {
         .name           = "s3c-pl330",
-        .id             = 2,
+        .id             = 1,
         .num_resources  = ARRAY_SIZE(s5pc100_pdma1_resource),
         .resource       = s5pc100_pdma1_resource,
         .dev            = {
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 0fab7f2cd8bf..20856eb7dd51 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -1,5 +1,7 @@
-/*
- * arch/arm/plat-s5pc100/gpiolib.c
+/* linux/arch/arm/mach-s5pc100/gpiolib.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
  *
  *  Copyright 2009 Samsung Electronics Co
  *  Kyungmin Park <kyungmin.park@samsung.com>
@@ -61,30 +63,6 @@
  * L3   8       4Bit    None
  */
 
-static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
-        return S3C_IRQ_GPIO(chip->base + offset);
-}
-
-static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
-{
-        int base;
-
-        base = chip->base - S5PC100_GPH0(0);
-        if (base == 0)
-                return IRQ_EINT(offset);
-        base = chip->base - S5PC100_GPH1(0);
-        if (base == 0)
-                return IRQ_EINT(8 + offset);
-        base = chip->base - S5PC100_GPH2(0);
-        if (base == 0)
-                return IRQ_EINT(16 + offset);
-        base = chip->base - S5PC100_GPH3(0);
-        if (base == 0)
-                return IRQ_EINT(24 + offset);
-        return -EINVAL;
-}
-
 static struct s3c_gpio_cfg gpio_cfg = {
         .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
         .set_pull       = s3c_gpio_setpull_updown,
@@ -104,209 +82,150 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
         .get_pull       = s3c_gpio_getpull_updown,
 };
 
+/*
+ * GPIO bank's base address given the index of the bank in the
+ * list of all gpio banks.
+ */
+#define S5PC100_BANK_BASE(bank_nr)      (S5P_VA_GPIO + ((bank_nr) * 0x20))
+
+/*
+ * Following are the gpio banks in S5PC100.
+ *
+ * The 'config' member when left to NULL, is initialized to the default
+ * structure gpio_cfg in the init function below.
+ *
+ * The 'base' member is also initialized in the init function below.
+ * Note: The initialization of 'base' member of s3c_gpio_chip structure
+ * uses the above macro and depends on the banks being listed in order here.
+ */
 static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
         {
-                .base   = S5PC100_GPA0_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPA0(0),
                         .ngpio  = S5PC100_GPIO_A0_NR,
                         .label  = "GPA0",
                 },
         }, {
-                .base   = S5PC100_GPA1_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPA1(0),
                         .ngpio  = S5PC100_GPIO_A1_NR,
                         .label  = "GPA1",
                 },
         }, {
-                .base   = S5PC100_GPB_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPB(0),
                         .ngpio  = S5PC100_GPIO_B_NR,
                         .label  = "GPB",
                 },
         }, {
-                .base   = S5PC100_GPC_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPC(0),
                         .ngpio  = S5PC100_GPIO_C_NR,
                         .label  = "GPC",
                 },
         }, {
-                .base   = S5PC100_GPD_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPD(0),
                         .ngpio  = S5PC100_GPIO_D_NR,
                         .label  = "GPD",
                 },
         }, {
-                .base   = S5PC100_GPE0_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPE0(0),
                         .ngpio  = S5PC100_GPIO_E0_NR,
                         .label  = "GPE0",
                 },
         }, {
-                .base   = S5PC100_GPE1_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPE1(0),
                         .ngpio  = S5PC100_GPIO_E1_NR,
                         .label  = "GPE1",
                 },
         }, {
-                .base   = S5PC100_GPF0_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPF0(0),
                         .ngpio  = S5PC100_GPIO_F0_NR,
                         .label  = "GPF0",
                 },
         }, {
-                .base   = S5PC100_GPF1_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPF1(0),
                         .ngpio  = S5PC100_GPIO_F1_NR,
                         .label  = "GPF1",
                 },
         }, {
-                .base   = S5PC100_GPF2_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPF2(0),
                         .ngpio  = S5PC100_GPIO_F2_NR,
                         .label  = "GPF2",
                 },
         }, {
-                .base   = S5PC100_GPF3_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPF3(0),
                         .ngpio  = S5PC100_GPIO_F3_NR,
                         .label  = "GPF3",
                 },
         }, {
-                .base   = S5PC100_GPG0_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPG0(0),
                         .ngpio  = S5PC100_GPIO_G0_NR,
                         .label  = "GPG0",
                 },
         }, {
-                .base   = S5PC100_GPG1_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPG1(0),
                         .ngpio  = S5PC100_GPIO_G1_NR,
                         .label  = "GPG1",
                 },
         }, {
-                .base   = S5PC100_GPG2_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPG2(0),
                         .ngpio  = S5PC100_GPIO_G2_NR,
                         .label  = "GPG2",
                 },
         }, {
-                .base   = S5PC100_GPG3_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPG3(0),
                         .ngpio  = S5PC100_GPIO_G3_NR,
                         .label  = "GPG3",
                 },
         }, {
-                .base   = S5PC100_GPH0_BASE,
-                .config = &gpio_cfg_eint,
-                .chip   = {
-                        .base   = S5PC100_GPH0(0),
-                        .ngpio  = S5PC100_GPIO_H0_NR,
-                        .label  = "GPH0",
-                },
-        }, {
-                .base   = S5PC100_GPH1_BASE,
-                .config = &gpio_cfg_eint,
-                .chip   = {
-                        .base   = S5PC100_GPH1(0),
-                        .ngpio  = S5PC100_GPIO_H1_NR,
-                        .label  = "GPH1",
-                },
-        }, {
-                .base   = S5PC100_GPH2_BASE,
-                .config = &gpio_cfg_eint,
-                .chip   = {
-                        .base   = S5PC100_GPH2(0),
-                        .ngpio  = S5PC100_GPIO_H2_NR,
-                        .label  = "GPH2",
-                },
-        }, {
-                .base   = S5PC100_GPH3_BASE,
-                .config = &gpio_cfg_eint,
-                .chip   = {
-                        .base   = S5PC100_GPH3(0),
-                        .ngpio  = S5PC100_GPIO_H3_NR,
-                        .label  = "GPH3",
-                },
-        }, {
-                .base   = S5PC100_GPI_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPI(0),
                         .ngpio  = S5PC100_GPIO_I_NR,
                         .label  = "GPI",
                 },
         }, {
-                .base   = S5PC100_GPJ0_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPJ0(0),
                         .ngpio  = S5PC100_GPIO_J0_NR,
                         .label  = "GPJ0",
                 },
         }, {
-                .base   = S5PC100_GPJ1_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPJ1(0),
                         .ngpio  = S5PC100_GPIO_J1_NR,
                         .label  = "GPJ1",
                 },
         }, {
-                .base   = S5PC100_GPJ2_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPJ2(0),
                         .ngpio  = S5PC100_GPIO_J2_NR,
                         .label  = "GPJ2",
                 },
         }, {
-                .base   = S5PC100_GPJ3_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPJ3(0),
                         .ngpio  = S5PC100_GPIO_J3_NR,
                         .label  = "GPJ3",
                 },
         }, {
-                .base   = S5PC100_GPJ4_BASE,
-                .config = &gpio_cfg,
                 .chip   = {
                         .base   = S5PC100_GPJ4(0),
                         .ngpio  = S5PC100_GPIO_J4_NR,
                         .label  = "GPJ4",
                 },
         }, {
-                .base   = S5PC100_GPK0_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPK0(0),
@@ -314,7 +233,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPK0",
                 },
         }, {
-                .base   = S5PC100_GPK1_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPK1(0),
@@ -322,7 +240,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPK1",
                 },
         }, {
-                .base   = S5PC100_GPK2_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPK2(0),
@@ -330,7 +247,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPK2",
                 },
         }, {
-                .base   = S5PC100_GPK3_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPK3(0),
@@ -338,7 +254,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPK3",
                 },
         }, {
-                .base   = S5PC100_GPL0_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPL0(0),
@@ -346,7 +261,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPL0",
                 },
         }, {
-                .base   = S5PC100_GPL1_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPL1(0),
@@ -354,7 +268,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPL1",
                 },
         }, {
-                .base   = S5PC100_GPL2_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPL2(0),
@@ -362,7 +275,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPL2",
                 },
         }, {
-                .base   = S5PC100_GPL3_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPL3(0),
@@ -370,56 +282,72 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
                         .label  = "GPL3",
                 },
         }, {
-                .base   = S5PC100_GPL4_BASE,
                 .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PC100_GPL4(0),
                         .ngpio  = S5PC100_GPIO_L4_NR,
                         .label  = "GPL4",
                 },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC00),
+                .config = &gpio_cfg_eint,
+                .irq_base = IRQ_EINT(0),
+                .chip   = {
+                        .base   = S5PC100_GPH0(0),
+                        .ngpio  = S5PC100_GPIO_H0_NR,
+                        .label  = "GPH0",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC20),
+                .config = &gpio_cfg_eint,
+                .irq_base = IRQ_EINT(8),
+                .chip   = {
+                        .base   = S5PC100_GPH1(0),
+                        .ngpio  = S5PC100_GPIO_H1_NR,
+                        .label  = "GPH1",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC40),
+                .config = &gpio_cfg_eint,
+                .irq_base = IRQ_EINT(16),
+                .chip   = {
+                        .base   = S5PC100_GPH2(0),
+                        .ngpio  = S5PC100_GPIO_H2_NR,
+                        .label  = "GPH2",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO + 0xC60),
+                .config = &gpio_cfg_eint,
+                .irq_base = IRQ_EINT(24),
+                .chip   = {
+                        .base   = S5PC100_GPH3(0),
+                        .ngpio  = S5PC100_GPIO_H3_NR,
+                        .label  = "GPH3",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
         },
 };
 
-/* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc100_gpioint;
-extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
-
-static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
+static __init int s5pc100_gpiolib_init(void)
 {
-        /* Interrupt */
-        if (chip->config == &gpio_cfg) {
-                int i, irq;
-
-                chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+        struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
+        int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+        int gpioint_group = 0;
+        int i;
 
-                for (i = 0;  i < chip->chip.ngpio; i++) {
-                        irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
-                        set_irq_chip(irq, &s5pc100_gpioint);
-                        set_irq_data(irq, &chip->chip);
-                        set_irq_handler(irq, handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID);
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL) {
+                        chip->config = &gpio_cfg;
+                        chip->group = gpioint_group++;
                 }
-        } else if (chip->config == &gpio_cfg_eint) {
-                chip->chip.to_irq = s5pc100_gpiolib_to_eint;
+                if (chip->base == NULL)
+                        chip->base = S5PC100_BANK_BASE(i);
         }
-}
-
-static __init int s5pc100_gpiolib_init(void)
-{
-        struct s3c_gpio_chip *chip;
-        int nr_chips;
-
-        chip = s5pc100_gpio_chips;
-        nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
-
-        for (; nr_chips > 0; nr_chips--, chip++)
-                s5pc100_gpiolib_link(chip);
-
-        samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
-                                       ARRAY_SIZE(s5pc100_gpio_chips));
 
-        /* Interrupt */
-        set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
+        samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 71ae1f52df1d..29a8a12d9b4f 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,13 +146,6 @@ enum s5p_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS           (S5PC100_GPIO_END + 1)
 
-#define EINT_MODE               S3C_GPIO_SFN(0x2)
-
-#define EINT_GPIO_0(x)          S5PC100_GPH0(x)
-#define EINT_GPIO_1(x)          S5PC100_GPH1(x)
-#define EINT_GPIO_2(x)          S5PC100_GPH2(x)
-#define EINT_GPIO_3(x)          S5PC100_GPH3(x)
-
 #include <asm-generic/gpio.h>
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 06513e647242..d2eb4757381f 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -48,8 +48,8 @@
 #define IRQ_SPI1                S5P_IRQ_VIC1(16)
 #define IRQ_SPI2                S5P_IRQ_VIC1(17)
 #define IRQ_IRDA                S5P_IRQ_VIC1(18)
-#define IRQ_CAN0                S5P_IRQ_VIC1(19)
-#define IRQ_CAN1                S5P_IRQ_VIC1(20)
+#define IRQ_IIC2                S5P_IRQ_VIC1(19)
+#define IRQ_IIC3                S5P_IRQ_VIC1(20)
 #define IRQ_HSIRX               S5P_IRQ_VIC1(21)
 #define IRQ_HSITX               S5P_IRQ_VIC1(22)
 #define IRQ_UHOST               S5P_IRQ_VIC1(23)
@@ -100,11 +100,12 @@
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
 
-#define S3C_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
-#define S3C_IRQ_GPIO(x)         (S3C_IRQ_GPIO_BASE + (x))
+/* GPIO interrupt */
+#define S5P_GPIOINT_BASE        (IRQ_EINT(31) + 1)
+#define S5P_GPIOINT_GROUP_MAXNR 21
 
-/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
-#define NR_IRQS         (S3C_IRQ_GPIO(320) + 1)
+/* Set the default NR_IRQS */
+#define NR_IRQS                 (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO            IRQ_LCD0
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 8751ef4a6804..32e9cab5c864 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -110,6 +110,8 @@
 #define S5PC100_PA_PCM0         0xF2400000
 #define S5PC100_PA_PCM1         0xF2500000
 
+#define S5PC100_PA_SPDIF        0xF2600000
+
 #define S5PC100_PA_TSADC        (0xF3000000)
 
 /* KEYPAD */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index dd6295e1251d..0bf73209ec7b 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -11,43 +11,6 @@
 
 #include <mach/map.h>
 
-/* S5PC100 */
-#define S5PC100_GPIO_BASE       S5P_VA_GPIO
-#define S5PC100_GPA0_BASE       (S5PC100_GPIO_BASE + 0x0000)
-#define S5PC100_GPA1_BASE       (S5PC100_GPIO_BASE + 0x0020)
-#define S5PC100_GPB_BASE        (S5PC100_GPIO_BASE + 0x0040)
-#define S5PC100_GPC_BASE        (S5PC100_GPIO_BASE + 0x0060)
-#define S5PC100_GPD_BASE        (S5PC100_GPIO_BASE + 0x0080)
-#define S5PC100_GPE0_BASE       (S5PC100_GPIO_BASE + 0x00A0)
-#define S5PC100_GPE1_BASE       (S5PC100_GPIO_BASE + 0x00C0)
-#define S5PC100_GPF0_BASE       (S5PC100_GPIO_BASE + 0x00E0)
-#define S5PC100_GPF1_BASE       (S5PC100_GPIO_BASE + 0x0100)
-#define S5PC100_GPF2_BASE       (S5PC100_GPIO_BASE + 0x0120)
-#define S5PC100_GPF3_BASE       (S5PC100_GPIO_BASE + 0x0140)
-#define S5PC100_GPG0_BASE       (S5PC100_GPIO_BASE + 0x0160)
-#define S5PC100_GPG1_BASE       (S5PC100_GPIO_BASE + 0x0180)
-#define S5PC100_GPG2_BASE       (S5PC100_GPIO_BASE + 0x01A0)
-#define S5PC100_GPG3_BASE       (S5PC100_GPIO_BASE + 0x01C0)
-#define S5PC100_GPH0_BASE       (S5PC100_GPIO_BASE + 0x0C00)
-#define S5PC100_GPH1_BASE       (S5PC100_GPIO_BASE + 0x0C20)
-#define S5PC100_GPH2_BASE       (S5PC100_GPIO_BASE + 0x0C40)
-#define S5PC100_GPH3_BASE       (S5PC100_GPIO_BASE + 0x0C60)
-#define S5PC100_GPI_BASE        (S5PC100_GPIO_BASE + 0x01E0)
-#define S5PC100_GPJ0_BASE       (S5PC100_GPIO_BASE + 0x0200)
-#define S5PC100_GPJ1_BASE       (S5PC100_GPIO_BASE + 0x0220)
-#define S5PC100_GPJ2_BASE       (S5PC100_GPIO_BASE + 0x0240)
-#define S5PC100_GPJ3_BASE       (S5PC100_GPIO_BASE + 0x0260)
-#define S5PC100_GPJ4_BASE       (S5PC100_GPIO_BASE + 0x0280)
-#define S5PC100_GPK0_BASE       (S5PC100_GPIO_BASE + 0x02A0)
-#define S5PC100_GPK1_BASE       (S5PC100_GPIO_BASE + 0x02C0)
-#define S5PC100_GPK2_BASE       (S5PC100_GPIO_BASE + 0x02E0)
-#define S5PC100_GPK3_BASE       (S5PC100_GPIO_BASE + 0x0300)
-#define S5PC100_GPL0_BASE       (S5PC100_GPIO_BASE + 0x0320)
-#define S5PC100_GPL1_BASE       (S5PC100_GPIO_BASE + 0x0340)
-#define S5PC100_GPL2_BASE       (S5PC100_GPIO_BASE + 0x0360)
-#define S5PC100_GPL3_BASE       (S5PC100_GPIO_BASE + 0x0380)
-#define S5PC100_GPL4_BASE       (S5PC100_GPIO_BASE + 0x03A0)
-
 #define S5PC100EINT30CON                (S5P_VA_GPIO + 0xE00)
 #define S5P_EINT_CON(x)                 (S5PC100EINT30CON + ((x) * 0x4))
 
@@ -64,12 +27,12 @@
 
 #define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
 
-/* values for S5P_EXTINT0 */
-#define S5P_EXTINT_LOWLEV               (0x00)
-#define S5P_EXTINT_HILEV                (0x01)
-#define S5P_EXTINT_FALLEDGE             (0x02)
-#define S5P_EXTINT_RISEEDGE             (0x03)
-#define S5P_EXTINT_BOTHEDGE             (0x04)
+#define EINT_MODE               S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x)          S5PC100_GPH0(x)
+#define EINT_GPIO_1(x)          S5PC100_GPH1(x)
+#define EINT_GPIO_2(x)          S5PC100_GPH2(x)
+#define EINT_GPIO_3(x)          S5PC100_GPH3(x)
 
 #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
 
diff --git a/arch/arm/mach-s5pc100/include/mach/vmalloc.h b/arch/arm/mach-s5pc100/include/mach/vmalloc.h
index be9df79903ed..44c8e5726d9d 100644
--- a/arch/arm/mach-s5pc100/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pc100/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xe0000000UL)
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pc100/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
deleted file mode 100644
index 2bf86c18bc73..000000000000
--- a/arch/arm/mach-s5pc100/irq-gpio.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * arch/arm/mach-s5pc100/irq-gpio.c
- *
- * Copyright (C) 2009 Samsung Electronics
- *
- * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-#include <plat/gpio-cfg.h>
-
-#define S5P_GPIOREG(x)          (S5P_VA_GPIO + (x))
-
-#define CON_OFFSET                      0x700
-#define MASK_OFFSET                     0x900
-#define PEND_OFFSET                     0xA00
-#define CON_OFFSET_2                    0xE00
-#define MASK_OFFSET_2                   0xF00
-#define PEND_OFFSET_2                   0xF40
-
-#define GPIOINT_LEVEL_LOW               0x0
-#define GPIOINT_LEVEL_HIGH              0x1
-#define GPIOINT_EDGE_FALLING            0x2
-#define GPIOINT_EDGE_RISING             0x3
-#define GPIOINT_EDGE_BOTH               0x4
-
-static int group_to_con_offset(int group)
-{
-        return group << 2;
-}
-
-static int group_to_mask_offset(int group)
-{
-        return group << 2;
-}
-
-static int group_to_pend_offset(int group)
-{
-        return group << 2;
-}
-
-static int s5pc100_get_start(unsigned int group)
-{
-        switch (group) {
-        case 0: return S5PC100_GPIO_A0_START;
-        case 1: return S5PC100_GPIO_A1_START;
-        case 2: return S5PC100_GPIO_B_START;
-        case 3: return S5PC100_GPIO_C_START;
-        case 4: return S5PC100_GPIO_D_START;
-        case 5: return S5PC100_GPIO_E0_START;
-        case 6: return S5PC100_GPIO_E1_START;
-        case 7: return S5PC100_GPIO_F0_START;
-        case 8: return S5PC100_GPIO_F1_START;
-        case 9: return S5PC100_GPIO_F2_START;
-        case 10: return S5PC100_GPIO_F3_START;
-        case 11: return S5PC100_GPIO_G0_START;
-        case 12: return S5PC100_GPIO_G1_START;
-        case 13: return S5PC100_GPIO_G2_START;
-        case 14: return S5PC100_GPIO_G3_START;
-        case 15: return S5PC100_GPIO_I_START;
-        case 16: return S5PC100_GPIO_J0_START;
-        case 17: return S5PC100_GPIO_J1_START;
-        case 18: return S5PC100_GPIO_J2_START;
-        case 19: return S5PC100_GPIO_J3_START;
-        case 20: return S5PC100_GPIO_J4_START;
-        default:
-                BUG();
-        }
-
-        return -EINVAL;
-}
-
-static int s5pc100_get_group(unsigned int irq)
-{
-        irq -= S3C_IRQ_GPIO(0);
-
-        switch (irq) {
-        case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
-                return 0;
-        case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
-                return 1;
-        case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
-                return 2;
-        case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
-                return 3;
-        case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
-                return 4;
-        case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
-                return 5;
-        case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
-                return 6;
-        case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
-                return 7;
-        case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
-                return 8;
-        case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
-                return 9;
-        case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
-                return 10;
-        case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
-                return 11;
-        case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
-                return 12;
-        case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
-                return 13;
-        case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
-                return 14;
-        case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
-                return 15;
-        case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
-                return 16;
-        case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
-                return 17;
-        case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
-                return 18;
-        case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
-                return 19;
-        case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
-                return 20;
-        default:
-                BUG();
-        }
-
-        return -EINVAL;
-}
-
-static int s5pc100_get_offset(unsigned int irq)
-{
-        struct gpio_chip *chip = get_irq_data(irq);
-        return irq - S3C_IRQ_GPIO(chip->base);
-}
-
-static void s5pc100_gpioint_ack(unsigned int irq)
-{
-        int group, offset, pend_offset;
-        unsigned int value;
-
-        group = s5pc100_get_group(irq);
-        offset = s5pc100_get_offset(irq);
-        pend_offset = group_to_pend_offset(group);
-
-        value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-        value |= 1 << offset;
-        __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-}
-
-static void s5pc100_gpioint_mask(unsigned int irq)
-{
-        int group, offset, mask_offset;
-        unsigned int value;
-
-        group = s5pc100_get_group(irq);
-        offset = s5pc100_get_offset(irq);
-        mask_offset = group_to_mask_offset(group);
-
-        value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-        value |= 1 << offset;
-        __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_unmask(unsigned int irq)
-{
-        int group, offset, mask_offset;
-        unsigned int value;
-
-        group = s5pc100_get_group(irq);
-        offset = s5pc100_get_offset(irq);
-        mask_offset = group_to_mask_offset(group);
-
-        value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-        value &= ~(1 << offset);
-        __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_mask_ack(unsigned int irq)
-{
-        s5pc100_gpioint_mask(irq);
-        s5pc100_gpioint_ack(irq);
-}
-
-static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
-{
-        int group, offset, con_offset;
-        unsigned int value;
-
-        group = s5pc100_get_group(irq);
-        offset = s5pc100_get_offset(irq);
-        con_offset = group_to_con_offset(group);
-
-        switch (type) {
-        case IRQ_TYPE_NONE:
-                printk(KERN_WARNING "No irq type\n");
-                return -EINVAL;
-        case IRQ_TYPE_EDGE_RISING:
-                type = GPIOINT_EDGE_RISING;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                type = GPIOINT_EDGE_FALLING;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                type = GPIOINT_EDGE_BOTH;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                type = GPIOINT_LEVEL_HIGH;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                type = GPIOINT_LEVEL_LOW;
-                break;
-        default:
-                BUG();
-        }
-
-
-        value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
-        value &= ~(0xf << (offset * 0x4));
-        value |= (type << (offset * 0x4));
-        __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
-
-        return 0;
-}
-
-struct irq_chip s5pc100_gpioint = {
-        .name           = "GPIO",
-        .ack            = s5pc100_gpioint_ack,
-        .mask           = s5pc100_gpioint_mask,
-        .mask_ack       = s5pc100_gpioint_mask_ack,
-        .unmask         = s5pc100_gpioint_unmask,
-        .set_type       = s5pc100_gpioint_set_type,
-};
-
-void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
-{
-        int group, offset, pend_offset, mask_offset;
-        int real_irq, group_end;
-        unsigned int pend, mask;
-
-        group_end = 21;
-
-        for (group = 0; group < group_end; group++) {
-                pend_offset = group_to_pend_offset(group);
-                pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-                if (!pend)
-                        continue;
-
-                mask_offset = group_to_mask_offset(group);
-                mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-                pend &= ~mask;
-
-                for (offset = 0; offset < 8; offset++) {
-                        if (pend & (1 << offset)) {
-                                real_irq = s5pc100_get_start(group) + offset;
-                                generic_handle_irq(S3C_IRQ_GPIO(real_irq));
-                        }
-                }
-        }
-}
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 880fb075092c..18b405d514d6 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -47,6 +47,7 @@
 #include <plat/adc.h>
 #include <plat/keypad.h>
 #include <plat/ts.h>
+#include <plat/audio.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKC100_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -196,6 +197,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
+        &s5pc100_device_spdif,
 };
 
 static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
@@ -226,6 +228,8 @@ static void __init smdkc100_machine_init(void)
 
         samsung_keypad_set_platdata(&smdkc100_keypad_data);
 
+        s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
+
         /* LCD init */
         gpio_request(S5PC100_GPD(0), "GPD");
         gpio_request(S5PC100_GPH0(6), "GPH0");
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
index 6eba6cb8e2f4..d31c0f3fe222 100644
--- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
@@ -22,27 +22,15 @@
 
 #define DISR_OFFSET     0x7008
 
-void s5pc100_fb_gpio_setup_24bpp(void)
+static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
 {
-        unsigned int gpio = 0;
-
-        for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
-
-        for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
-
-        for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
+}
 
-        for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+void s5pc100_fb_gpio_setup_24bpp(void)
+{
+        s5pc100_fb_setgpios(S5PC100_GPF0(0), 8);
+        s5pc100_fb_setgpios(S5PC100_GPF1(0), 8);
+        s5pc100_fb_setgpios(S5PC100_GPF2(0), 8);
+        s5pc100_fb_setgpios(S5PC100_GPF3(0), 4);
 }
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
index dd3174e6ecc5..eaef7a3bda49 100644
--- a/arch/arm/mach-s5pc100/setup-i2c0.c
+++ b/arch/arm/mach-s5pc100/setup-i2c0.c
@@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PC100_GPD(3), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
index d1fec26b69ee..aaff74a90dee 100644
--- a/arch/arm/mach-s5pc100/setup-i2c1.c
+++ b/arch/arm/mach-s5pc100/setup-i2c1.c
@@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PC100_GPD(5), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
index 83575671fb59..223aae044466 100644
--- a/arch/arm/mach-s5pc100/setup-ide.c
+++ b/arch/arm/mach-s5pc100/setup-ide.c
@@ -17,52 +17,39 @@
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
 
+static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
+{
+        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
+
+        for (; nr > 0; nr--, base++)
+                s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
+}
+
 void s5pc100_ide_setup_gpio(void)
 {
         u32 reg;
-        u32 gpio = 0;
 
         /* Independent CF interface, CF chip select configuration */
         reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
         writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
 
         /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
-        for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+        s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
 
         /*CF_Data[0 - 7] */
-        for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+        s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
 
         /* CF_Data[8 - 15] */
-        for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+        s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
 
         /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
-        for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+        s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
 
         /* EBI_OE, EBI_WE */
-        for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++)
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0));
+        s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
 
         /* CF_OE, CF_WE */
-        for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
 
         /* CF_CD */
         s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c
index d0837a72a58e..ada377f0c206 100644
--- a/arch/arm/mach-s5pc100/setup-keypad.c
+++ b/arch/arm/mach-s5pc100/setup-keypad.c
@@ -15,20 +15,9 @@
 
 void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 {
-        unsigned int gpio;
-        unsigned int end;
-
         /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
-        end = S5PC100_GPH3(rows);
-        for (gpio = S5PC100_GPH3(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
 
         /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
-        end = S5PC100_GPH2(cols);
-        for (gpio = S5PC100_GPH2(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
 }
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index dc7208c639ea..03c02d04c68c 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -25,8 +25,6 @@
 void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        unsigned int end;
         unsigned int num;
 
         num = width;
@@ -34,20 +32,11 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
         if (width == 8)
                 num = width - 2;
 
-        end = S5PC100_GPG0(2 + num);
-
         /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
-        for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2));
 
-        if (width == 8) {
-                for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                }
-        }
+        if (width == 8)
+                s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2));
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
                 s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
@@ -58,16 +47,9 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        unsigned int end;
-
-        end = S5PC100_GPG2(2 + width);
 
         /* Set all the necessary GPG2 pins to special-function 2 */
-        for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2));
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
                 s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
@@ -78,16 +60,9 @@ void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-        unsigned int end;
-
-        end = S5PC100_GPG3(2 + width);
 
         /* Set all the necessary GPG3 pins to special-function 2 */
-        for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2));
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
                 s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 5315fec3db86..862f239a0fdb 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -11,9 +11,9 @@ if ARCH_S5PV210
 
 config CPU_S5PV210
         bool
-        select PLAT_S5P
         select S3C_PL330_DMA
         select S5P_EXT_INT
+        select S5PV210_PM if PM
         help
           Enable S5PV210 CPU support
 
@@ -58,7 +58,6 @@ menu "S5PC110 Machines"
 config MACH_AQUILA
         bool "Aquila"
         select CPU_S5PV210
-        select ARCH_SPARSEMEM_ENABLE
         select S3C_DEV_FB
         select S5P_DEV_FIMC0
         select S5P_DEV_FIMC1
@@ -75,7 +74,7 @@ config MACH_AQUILA
 config MACH_GONI
         bool "GONI"
         select CPU_S5PV210
-        select ARCH_SPARSEMEM_ENABLE
+        select S5P_GPIO_INT
         select S3C_DEV_FB
         select S5P_DEV_FIMC0
         select S5P_DEV_FIMC1
@@ -83,8 +82,15 @@ config MACH_GONI
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
+        select S3C_DEV_I2C1
+        select S3C_DEV_I2C2
+        select S3C_DEV_USB_HSOTG
         select S5P_DEV_ONENAND
+        select SAMSUNG_DEV_KEYPAD
         select S5PV210_SETUP_FB_24BPP
+        select S5PV210_SETUP_I2C1
+        select S5PV210_SETUP_I2C2
+        select S5PV210_SETUP_KEYPAD
         select S5PV210_SETUP_SDHCI
         help
           Machine support for Samsung GONI board
@@ -93,7 +99,6 @@ config MACH_GONI
 config MACH_SMDKC110
         bool "SMDKC110"
         select CPU_S5PV210
-        select ARCH_SPARSEMEM_ENABLE
         select S3C_DEV_I2C1
         select S3C_DEV_I2C2
         select S3C_DEV_RTC
@@ -113,7 +118,6 @@ menu "S5PV210 Machines"
 config MACH_SMDKV210
         bool "SMDKV210"
         select CPU_S5PV210
-        select ARCH_SPARSEMEM_ENABLE
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
@@ -134,6 +138,29 @@ config MACH_SMDKV210
         help
           Machine support for Samsung SMDKV210
 
+config MACH_TORBRECK
+        bool "Torbreck"
+        select CPU_S5PV210
+        select ARCH_SPARSEMEM_ENABLE
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S3C_DEV_I2C1
+        select S3C_DEV_I2C2
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S5PV210_SETUP_I2C1
+        select S5PV210_SETUP_I2C2
+        select S5PV210_SETUP_SDHCI
+        help
+          Machine support for aESOP Torbreck
+
 endmenu
 
+config S5PV210_PM
+        bool
+        help
+          Power Management code common to S5PV210
+
 endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 704548912408..ff1a0db57a2f 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -14,6 +14,8 @@ obj-				:=
 
 obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o gpiolib.o
 obj-$(CONFIG_CPU_S5PV210)       += setup-i2c0.o
+obj-$(CONFIG_S5PV210_PM)        += pm.o sleep.o
+obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
 
 # machine support
 
@@ -21,6 +23,7 @@ obj-$(CONFIG_MACH_AQUILA)	+= mach-aquila.o
 obj-$(CONFIG_MACH_SMDKV210)     += mach-smdkv210.o
 obj-$(CONFIG_MACH_SMDKC110)     += mach-smdkc110.o
 obj-$(CONFIG_MACH_GONI)         += mach-goni.o
+obj-$(CONFIG_MACH_TORBRECK)     += mach-torbreck.o
 
 # device support
 
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index d562670e1b0b..019c3a69b0e4 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -31,6 +31,8 @@
 #include <plat/clock-clksrc.h>
 #include <plat/s5pv210.h>
 
+static unsigned long xtal;
+
 static struct clksrc_clk clk_mout_apll = {
         .clk    = {
                 .name           = "mout_apll",
@@ -259,6 +261,36 @@ static struct clksrc_clk clk_sclk_vpll = {
         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 };
 
+static struct clk *clkset_moutdmc0src_list[] = {
+        [0] = &clk_sclk_a2m.clk,
+        [1] = &clk_mout_mpll.clk,
+        [2] = NULL,
+        [3] = NULL,
+};
+
+static struct clksrc_sources clkset_moutdmc0src = {
+        .sources        = clkset_moutdmc0src_list,
+        .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
+};
+
+static struct clksrc_clk clk_mout_dmc0 = {
+        .clk    = {
+                .name           = "mout_dmc0",
+                .id             = -1,
+        },
+        .sources        = &clkset_moutdmc0src,
+        .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
+};
+
+static struct clksrc_clk clk_sclk_dmc0 = {
+        .clk    = {
+                .name           = "sclk_dmc0",
+                .id             = -1,
+                .parent         = &clk_mout_dmc0.clk,
+        },
+        .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
+};
+
 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 {
         return clk_get_rate(clk->parent) / 2;
@@ -268,8 +300,29 @@ static struct clk_ops clk_hclk_imem_ops = {
         .get_rate       = s5pv210_clk_imem_get_rate,
 };
 
+static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
+{
+        return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
+}
+
+static struct clk_ops clk_fout_apll_ops = {
+        .get_rate       = s5pv210_clk_fout_apll_get_rate,
+};
+
 static struct clk init_clocks_disable[] = {
         {
+                .name           = "pdma",
+                .id             = 0,
+                .parent         = &clk_hclk_psys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "pdma",
+                .id             = 1,
+                .parent         = &clk_hclk_psys.clk,
+                .enable         = s5pv210_clk_ip0_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
                 .name           = "rot",
                 .id             = -1,
                 .parent         = &clk_hclk_dsys.clk,
@@ -431,6 +484,12 @@ static struct clk init_clocks_disable[] = {
                 .parent         = &clk_p,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "spdif",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pv210_clk_ip3_ctrl,
+                .ctrlbit        = (1 << 0),
         },
 };
 
@@ -660,6 +719,53 @@ static struct clksrc_sources clkset_sclk_spdif = {
         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 };
 
+static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+        struct clk *pclk;
+        int ret;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        ret = pclk->ops->set_rate(pclk, rate);
+        clk_put(pclk);
+
+        return ret;
+}
+
+static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
+{
+        struct clk *pclk;
+        int rate;
+
+        pclk = clk_get_parent(clk);
+        if (IS_ERR(pclk))
+                return -EINVAL;
+
+        rate = pclk->ops->get_rate(clk);
+        clk_put(pclk);
+
+        return rate;
+}
+
+static struct clk_ops s5pv210_sclk_spdif_ops = {
+        .set_rate       = s5pv210_spdif_set_rate,
+        .get_rate       = s5pv210_spdif_get_rate,
+};
+
+static struct clksrc_clk clk_sclk_spdif = {
+        .clk            = {
+                .name           = "sclk_spdif",
+                .id             = -1,
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 27),
+                .ops            = &s5pv210_sclk_spdif_ops,
+        },
+        .sources = &clkset_sclk_spdif,
+        .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
+};
+
 static struct clk *clkset_group2_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = &clk_xusbxti,
@@ -744,15 +850,6 @@ static struct clksrc_clk clksrcs[] = {
                 .sources = &clkset_sclk_mixer,
                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
         }, {
-                .clk            = {
-                        .name           = "sclk_spdif",
-                        .id             = -1,
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 27),
-                },
-                .sources = &clkset_sclk_spdif,
-                .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
-        }, {
                 .clk    = {
                         .name           = "sclk_fimc",
                         .id             = 0,
@@ -953,12 +1050,93 @@ static struct clksrc_clk *sysclks[] = {
         &clk_sclk_dac,
         &clk_sclk_pixel,
         &clk_sclk_hdmi,
+        &clk_mout_dmc0,
+        &clk_sclk_dmc0,
+        &clk_sclk_audio0,
+        &clk_sclk_audio1,
+        &clk_sclk_audio2,
+        &clk_sclk_spdif,
+};
+
+static u32 epll_div[][6] = {
+        {  48000000, 0, 48, 3, 3, 0 },
+        {  96000000, 0, 48, 3, 2, 0 },
+        { 144000000, 1, 72, 3, 2, 0 },
+        { 192000000, 0, 48, 3, 1, 0 },
+        { 288000000, 1, 72, 3, 1, 0 },
+        {  32750000, 1, 65, 3, 4, 35127 },
+        {  32768000, 1, 65, 3, 4, 35127 },
+        {  45158400, 0, 45, 3, 3, 10355 },
+        {  45000000, 0, 45, 3, 3, 10355 },
+        {  45158000, 0, 45, 3, 3, 10355 },
+        {  49125000, 0, 49, 3, 3, 9961 },
+        {  49152000, 0, 49, 3, 3, 9961 },
+        {  67737600, 1, 67, 3, 3, 48366 },
+        {  67738000, 1, 67, 3, 3, 48366 },
+        {  73800000, 1, 73, 3, 3, 47710 },
+        {  73728000, 1, 73, 3, 3, 47710 },
+        {  36000000, 1, 32, 3, 4, 0 },
+        {  60000000, 1, 60, 3, 3, 0 },
+        {  72000000, 1, 72, 3, 3, 0 },
+        {  80000000, 1, 80, 3, 3, 0 },
+        {  84000000, 0, 42, 3, 2, 0 },
+        {  50000000, 0, 50, 3, 3, 0 },
+};
+
+static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int epll_con, epll_con_k;
+        unsigned int i;
+
+        /* Return if nothing changed */
+        if (clk->rate == rate)
+                return 0;
+
+        epll_con = __raw_readl(S5P_EPLL_CON);
+        epll_con_k = __raw_readl(S5P_EPLL_CON1);
+
+        epll_con_k &= ~PLL46XX_KDIV_MASK;
+        epll_con &= ~(1 << 27 |
+                        PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
+                        PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
+                        PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+        for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+                if (epll_div[i][0] == rate) {
+                        epll_con_k |= epll_div[i][5] << 0;
+                        epll_con |= (epll_div[i][1] << 27 |
+                                        epll_div[i][2] << PLL46XX_MDIV_SHIFT |
+                                        epll_div[i][3] << PLL46XX_PDIV_SHIFT |
+                                        epll_div[i][4] << PLL46XX_SDIV_SHIFT);
+                        break;
+                }
+        }
+
+        if (i == ARRAY_SIZE(epll_div)) {
+                printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        __raw_writel(epll_con, S5P_EPLL_CON);
+        __raw_writel(epll_con_k, S5P_EPLL_CON1);
+
+        printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+                        clk->rate, rate);
+
+        clk->rate = rate;
+
+        return 0;
+}
+
+static struct clk_ops s5pv210_epll_ops = {
+        .set_rate = s5pv210_epll_set_rate,
+        .get_rate = s5p_epll_get_rate,
 };
 
 void __init_or_cpufreq s5pv210_setup_clocks(void)
 {
         struct clk *xtal_clk;
-        unsigned long xtal;
         unsigned long vpllsrc;
         unsigned long armclk;
         unsigned long hclk_msys;
@@ -974,6 +1152,10 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
         unsigned int ptr;
         u32 clkdiv0, clkdiv1;
 
+        /* Set functions for clk_fout_epll */
+        clk_fout_epll.enable = s5p_epll_enable;
+        clk_fout_epll.ops = &s5pv210_epll_ops;
+
         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 
         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
@@ -992,11 +1174,12 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
 
         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
-        epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
+        epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
+                                __raw_readl(S5P_EPLL_CON1), pll_4600);
         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
 
-        clk_fout_apll.rate = apll;
+        clk_fout_apll.ops = &clk_fout_apll_ops;
         clk_fout_mpll.rate = mpll;
         clk_fout_epll.rate = epll;
         clk_fout_vpll.rate = vpll;
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 2f16bfc0a116..8eb480e201b0 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -85,6 +85,21 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_DMC0,
+                .pfn            = __phys_to_pfn(S5PV210_PA_DMC0),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_DMC1,
+                .pfn            = __phys_to_pfn(S5PV210_PA_DMC1),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+                .pfn            =__phys_to_pfn(S5PV210_PA_HSPHY),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
         }
 };
 
diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c
new file mode 100644
index 000000000000..a6f22920a2c2
--- /dev/null
+++ b/arch/arm/mach-s5pv210/cpufreq.c
@@ -0,0 +1,484 @@
+/* linux/arch/arm/mach-s5pv210/cpufreq.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * CPU frequency scaling for S5PC110/S5PV210
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+static struct clk *cpu_clk;
+static struct clk *dmc0_clk;
+static struct clk *dmc1_clk;
+static struct cpufreq_freqs freqs;
+
+/* APLL M,P,S values for 1G/800Mhz */
+#define APLL_VAL_1000   ((1 << 31) | (125 << 16) | (3 << 8) | 1)
+#define APLL_VAL_800    ((1 << 31) | (100 << 16) | (3 << 8) | 1)
+
+/*
+ * DRAM configurations to calculate refresh counter for changing
+ * frequency of memory.
+ */
+struct dram_conf {
+        unsigned long freq;     /* HZ */
+        unsigned long refresh;  /* DRAM refresh counter * 1000 */
+};
+
+/* DRAM configuration (DMC0 and DMC1) */
+static struct dram_conf s5pv210_dram_conf[2];
+
+enum perf_level {
+        L0, L1, L2, L3, L4,
+};
+
+enum s5pv210_mem_type {
+        LPDDR   = 0x1,
+        LPDDR2  = 0x2,
+        DDR2    = 0x4,
+};
+
+enum s5pv210_dmc_port {
+        DMC0 = 0,
+        DMC1,
+};
+
+static struct cpufreq_frequency_table s5pv210_freq_table[] = {
+        {L0, 1000*1000},
+        {L1, 800*1000},
+        {L2, 400*1000},
+        {L3, 200*1000},
+        {L4, 100*1000},
+        {0, CPUFREQ_TABLE_END},
+};
+
+static u32 clkdiv_val[5][11] = {
+        /*
+         * Clock divider value for following
+         * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
+         *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
+         *   ONEDRAM, MFC, G3D }
+         */
+
+        /* L0 : [1000/200/100][166/83][133/66][200/200] */
+        {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
+
+        /* L1 : [800/200/100][166/83][133/66][200/200] */
+        {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
+
+        /* L2 : [400/200/100][166/83][133/66][200/200] */
+        {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
+
+        /* L3 : [200/200/100][166/83][133/66][200/200] */
+        {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
+
+        /* L4 : [100/100/100][83/83][66/66][100/100] */
+        {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
+};
+
+/*
+ * This function set DRAM refresh counter
+ * accoriding to operating frequency of DRAM
+ * ch: DMC port number 0 or 1
+ * freq: Operating frequency of DRAM(KHz)
+ */
+static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
+{
+        unsigned long tmp, tmp1;
+        void __iomem *reg = NULL;
+
+        if (ch == DMC0)
+                reg = (S5P_VA_DMC0 + 0x30);
+        else if (ch == DMC1)
+                reg = (S5P_VA_DMC1 + 0x30);
+        else
+                printk(KERN_ERR "Cannot find DMC port\n");
+
+        /* Find current DRAM frequency */
+        tmp = s5pv210_dram_conf[ch].freq;
+
+        do_div(tmp, freq);
+
+        tmp1 = s5pv210_dram_conf[ch].refresh;
+
+        do_div(tmp1, tmp);
+
+        __raw_writel(tmp1, reg);
+}
+
+int s5pv210_verify_speed(struct cpufreq_policy *policy)
+{
+        if (policy->cpu)
+                return -EINVAL;
+
+        return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
+}
+
+unsigned int s5pv210_getspeed(unsigned int cpu)
+{
+        if (cpu)
+                return 0;
+
+        return clk_get_rate(cpu_clk) / 1000;
+}
+
+static int s5pv210_target(struct cpufreq_policy *policy,
+                          unsigned int target_freq,
+                          unsigned int relation)
+{
+        unsigned long reg;
+        unsigned int index, priv_index;
+        unsigned int pll_changing = 0;
+        unsigned int bus_speed_changing = 0;
+
+        freqs.old = s5pv210_getspeed(0);
+
+        if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
+                                           target_freq, relation, &index))
+                return -EINVAL;
+
+        freqs.new = s5pv210_freq_table[index].frequency;
+        freqs.cpu = 0;
+
+        if (freqs.new == freqs.old)
+                return 0;
+
+        /* Finding current running level index */
+        if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
+                                           freqs.old, relation, &priv_index))
+                return -EINVAL;
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        if (freqs.new > freqs.old) {
+                /* Voltage up: will be implemented */
+        }
+
+        /* Check if there need to change PLL */
+        if ((index == L0) || (priv_index == L0))
+                pll_changing = 1;
+
+        /* Check if there need to change System bus clock */
+        if ((index == L4) || (priv_index == L4))
+                bus_speed_changing = 1;
+
+        if (bus_speed_changing) {
+                /*
+                 * Reconfigure DRAM refresh counter value for minimum
+                 * temporary clock while changing divider.
+                 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
+                 */
+                if (pll_changing)
+                        s5pv210_set_refresh(DMC1, 83000);
+                else
+                        s5pv210_set_refresh(DMC1, 100000);
+
+                s5pv210_set_refresh(DMC0, 83000);
+        }
+
+        /*
+         * APLL should be changed in this level
+         * APLL -> MPLL(for stable transition) -> APLL
+         * Some clock source's clock API are not prepared.
+         * Do not use clock API in below code.
+         */
+        if (pll_changing) {
+                /*
+                 * 1. Temporary Change divider for MFC and G3D
+                 * SCLKA2M(200/1=200)->(200/4=50)Mhz
+                 */
+                reg = __raw_readl(S5P_CLK_DIV2);
+                reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
+                reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
+                        (3 << S5P_CLKDIV2_MFC_SHIFT);
+                __raw_writel(reg, S5P_CLK_DIV2);
+
+                /* For MFC, G3D dividing */
+                do {
+                        reg = __raw_readl(S5P_CLKDIV_STAT0);
+                } while (reg & ((1 << 16) | (1 << 17)));
+
+                /*
+                 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
+                 * (200/4=50)->(667/4=166)Mhz
+                 */
+                reg = __raw_readl(S5P_CLK_SRC2);
+                reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
+                reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
+                        (1 << S5P_CLKSRC2_MFC_SHIFT);
+                __raw_writel(reg, S5P_CLK_SRC2);
+
+                do {
+                        reg = __raw_readl(S5P_CLKMUX_STAT1);
+                } while (reg & ((1 << 7) | (1 << 3)));
+
+                /*
+                 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
+                 * true refresh counter is already programed in upper
+                 * code. 0x287@83Mhz
+                 */
+                if (!bus_speed_changing)
+                        s5pv210_set_refresh(DMC1, 133000);
+
+                /* 4. SCLKAPLL -> SCLKMPLL */
+                reg = __raw_readl(S5P_CLK_SRC0);
+                reg &= ~(S5P_CLKSRC0_MUX200_MASK);
+                reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
+                __raw_writel(reg, S5P_CLK_SRC0);
+
+                do {
+                        reg = __raw_readl(S5P_CLKMUX_STAT0);
+                } while (reg & (0x1 << 18));
+
+        }
+
+        /* Change divider */
+        reg = __raw_readl(S5P_CLK_DIV0);
+
+        reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
+                S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
+                S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
+                S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
+
+        reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
+                (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
+                (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
+                (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
+                (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
+                (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
+                (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
+                (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
+
+        __raw_writel(reg, S5P_CLK_DIV0);
+
+        do {
+                reg = __raw_readl(S5P_CLKDIV_STAT0);
+        } while (reg & 0xff);
+
+        /* ARM MCS value changed */
+        reg = __raw_readl(S5P_ARM_MCS_CON);
+        reg &= ~0x3;
+        if (index >= L3)
+                reg |= 0x3;
+        else
+                reg |= 0x1;
+
+        __raw_writel(reg, S5P_ARM_MCS_CON);
+
+        if (pll_changing) {
+                /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
+                __raw_writel(0x2cf, S5P_APLL_LOCK);
+
+                /*
+                 * 6. Turn on APLL
+                 * 6-1. Set PMS values
+                 * 6-2. Wait untile the PLL is locked
+                 */
+                if (index == L0)
+                        __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
+                else
+                        __raw_writel(APLL_VAL_800, S5P_APLL_CON);
+
+                do {
+                        reg = __raw_readl(S5P_APLL_CON);
+                } while (!(reg & (0x1 << 29)));
+
+                /*
+                 * 7. Change souce clock from SCLKMPLL(667Mhz)
+                 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
+                 * (667/4=166)->(200/4=50)Mhz
+                 */
+                reg = __raw_readl(S5P_CLK_SRC2);
+                reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
+                reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
+                        (0 << S5P_CLKSRC2_MFC_SHIFT);
+                __raw_writel(reg, S5P_CLK_SRC2);
+
+                do {
+                        reg = __raw_readl(S5P_CLKMUX_STAT1);
+                } while (reg & ((1 << 7) | (1 << 3)));
+
+                /*
+                 * 8. Change divider for MFC and G3D
+                 * (200/4=50)->(200/1=200)Mhz
+                 */
+                reg = __raw_readl(S5P_CLK_DIV2);
+                reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
+                reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
+                        (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
+                __raw_writel(reg, S5P_CLK_DIV2);
+
+                /* For MFC, G3D dividing */
+                do {
+                        reg = __raw_readl(S5P_CLKDIV_STAT0);
+                } while (reg & ((1 << 16) | (1 << 17)));
+
+                /* 9. Change MPLL to APLL in MSYS_MUX */
+                reg = __raw_readl(S5P_CLK_SRC0);
+                reg &= ~(S5P_CLKSRC0_MUX200_MASK);
+                reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
+                __raw_writel(reg, S5P_CLK_SRC0);
+
+                do {
+                        reg = __raw_readl(S5P_CLKMUX_STAT0);
+                } while (reg & (0x1 << 18));
+
+                /*
+                 * 10. DMC1 refresh counter
+                 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
+                 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
+                 */
+                if (!bus_speed_changing)
+                        s5pv210_set_refresh(DMC1, 200000);
+        }
+
+        /*
+         * L4 level need to change memory bus speed, hence onedram clock divier
+         * and memory refresh parameter should be changed
+         */
+        if (bus_speed_changing) {
+                reg = __raw_readl(S5P_CLK_DIV6);
+                reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
+                reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
+                __raw_writel(reg, S5P_CLK_DIV6);
+
+                do {
+                        reg = __raw_readl(S5P_CLKDIV_STAT1);
+                } while (reg & (1 << 15));
+
+                /* Reconfigure DRAM refresh counter value */
+                if (index != L4) {
+                        /*
+                         * DMC0 : 166Mhz
+                         * DMC1 : 200Mhz
+                         */
+                        s5pv210_set_refresh(DMC0, 166000);
+                        s5pv210_set_refresh(DMC1, 200000);
+                } else {
+                        /*
+                         * DMC0 : 83Mhz
+                         * DMC1 : 100Mhz
+                         */
+                        s5pv210_set_refresh(DMC0, 83000);
+                        s5pv210_set_refresh(DMC1, 100000);
+                }
+        }
+
+        if (freqs.new < freqs.old) {
+                /* Voltage down: will be implemented */
+        }
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        printk(KERN_DEBUG "Perf changed[L%d]\n", index);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy,
+                                   pm_message_t pmsg)
+{
+        return 0;
+}
+
+static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
+{
+        return 0;
+}
+#endif
+
+static int check_mem_type(void __iomem *dmc_reg)
+{
+        unsigned long val;
+
+        val = __raw_readl(dmc_reg + 0x4);
+        val = (val & (0xf << 8));
+
+        return val >> 8;
+}
+
+static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
+{
+        unsigned long mem_type;
+
+        cpu_clk = clk_get(NULL, "armclk");
+        if (IS_ERR(cpu_clk))
+                return PTR_ERR(cpu_clk);
+
+        dmc0_clk = clk_get(NULL, "sclk_dmc0");
+        if (IS_ERR(dmc0_clk)) {
+                clk_put(cpu_clk);
+                return PTR_ERR(dmc0_clk);
+        }
+
+        dmc1_clk = clk_get(NULL, "hclk_msys");
+        if (IS_ERR(dmc1_clk)) {
+                clk_put(dmc0_clk);
+                clk_put(cpu_clk);
+                return PTR_ERR(dmc1_clk);
+        }
+
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        /*
+         * check_mem_type : This driver only support LPDDR & LPDDR2.
+         * other memory type is not supported.
+         */
+        mem_type = check_mem_type(S5P_VA_DMC0);
+
+        if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
+                printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
+                return -EINVAL;
+        }
+
+        /* Find current refresh counter and frequency each DMC */
+        s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
+        s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
+
+        s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
+        s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
+
+        policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
+
+        cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
+
+        policy->cpuinfo.transition_latency = 40000;
+
+        return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
+}
+
+static struct cpufreq_driver s5pv210_driver = {
+        .flags          = CPUFREQ_STICKY,
+        .verify         = s5pv210_verify_speed,
+        .target         = s5pv210_target,
+        .get            = s5pv210_getspeed,
+        .init           = s5pv210_cpu_init,
+        .name           = "s5pv210",
+#ifdef CONFIG_PM
+        .suspend        = s5pv210_cpufreq_suspend,
+        .resume         = s5pv210_cpufreq_resume,
+#endif
+};
+
+static int __init s5pv210_cpufreq_init(void)
+{
+        return cpufreq_register_driver(&s5pv210_driver);
+}
+
+late_initcall(s5pv210_cpufreq_init);
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 21dc6cf955c3..1303fcb12b51 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -24,29 +24,15 @@ static int s5pv210_cfg_i2s(struct platform_device *pdev)
         /* configure GPIO for i2s port */
         switch (pdev->id) {
         case 1:
-                s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(2));
                 break;
 
         case 2:
-                s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4));
-                s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4));
+                s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(4));
                 break;
 
         case -1:
-                s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(S5PV210_GPI(0), 7, S3C_GPIO_SFN(2));
                 break;
 
         default:
@@ -151,25 +137,13 @@ static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev)
 {
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin_range(S5PV210_GPI(0), 5, S3C_GPIO_SFN(3));
                 break;
         case 1:
-                s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3));
-                s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3));
+                s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(3));
                 break;
         case 2:
-                s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2));
+                s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 5, S3C_GPIO_SFN(2));
                 break;
         default:
                 printk(KERN_DEBUG "Invalid PCM Controller number!");
@@ -271,13 +245,7 @@ struct platform_device s5pv210_device_pcm2 = {
 
 static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
 {
-        s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4));
-        s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4));
-
-        return 0;
+        return s3c_gpio_cfgpin_range(S5PV210_GPC0(0), 5, S3C_GPIO_SFN(4));
 }
 
 static struct resource s5pv210_ac97_resource[] = {
@@ -325,3 +293,43 @@ struct platform_device s5pv210_device_ac97 = {
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
 };
+
+/* S/PDIF Controller platform_device */
+
+static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
+{
+        s3c_gpio_cfgpin_range(S5PV210_GPC1(0), 2, S3C_GPIO_SFN(3));
+
+        return 0;
+}
+
+static struct resource s5pv210_spdif_resource[] = {
+        [0] = {
+                .start  = S5PV210_PA_SPDIF,
+                .end    = S5PV210_PA_SPDIF + 0x100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DMACH_SPDIF,
+                .end    = DMACH_SPDIF,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct s3c_audio_pdata samsung_spdif_pdata = {
+        .cfg_gpio = s5pv210_spdif_cfg_gpio,
+};
+
+static u64 s5pv210_spdif_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5pv210_device_spdif = {
+        .name           = "samsung-spdif",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(s5pv210_spdif_resource),
+        .resource       = s5pv210_spdif_resource,
+        .dev = {
+                .platform_data = &samsung_spdif_pdata,
+                .dma_mask = &s5pv210_spdif_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
index 826cdbc43e20..e3249a47e3b1 100644
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ b/arch/arm/mach-s5pv210/dev-spi.c
@@ -35,23 +35,15 @@ static char *spi_src_clks[] = {
  */
 static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
 {
+        unsigned int base;
+
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP);
+                base = S5PV210_GPB(0);
                 break;
 
         case 1:
-                s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2));
-                s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP);
+                base = S5PV210_GPB(4);
                 break;
 
         default:
@@ -59,6 +51,9 @@ static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgall_range(base, 3,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 778ad5fe231a..497d3439a142 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -82,7 +82,7 @@ static struct s3c_pl330_platdata s5pv210_pdma0_pdata = {
 
 static struct platform_device s5pv210_device_pdma0 = {
         .name           = "s3c-pl330",
-        .id             = 1,
+        .id             = 0,
         .num_resources  = ARRAY_SIZE(s5pv210_pdma0_resource),
         .resource       = s5pv210_pdma0_resource,
         .dev            = {
@@ -144,7 +144,7 @@ static struct s3c_pl330_platdata s5pv210_pdma1_pdata = {
 
 static struct platform_device s5pv210_device_pdma1 = {
         .name           = "s3c-pl330",
-        .id             = 2,
+        .id             = 1,
         .num_resources  = ARRAY_SIZE(s5pv210_pdma1_resource),
         .resource       = s5pv210_pdma1_resource,
         .dev            = {
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index 0d459112d039..ab673effd767 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -150,6 +150,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
                         .label  = "GPG3",
                 },
         }, {
+                .config = &gpio_cfg_noint,
                 .chip   = {
                         .base   = S5PV210_GPI(0),
                         .ngpio  = S5PV210_GPIO_I_NR,
@@ -223,34 +224,42 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
         }, {
                 .base   = (S5P_VA_GPIO + 0xC00),
                 .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(0),
                 .chip   = {
                         .base   = S5PV210_GPH0(0),
                         .ngpio  = S5PV210_GPIO_H0_NR,
                         .label  = "GPH0",
+                        .to_irq = samsung_gpiolib_to_irq,
                 },
         }, {
                 .base   = (S5P_VA_GPIO + 0xC20),
                 .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(8),
                 .chip   = {
                         .base   = S5PV210_GPH1(0),
                         .ngpio  = S5PV210_GPIO_H1_NR,
                         .label  = "GPH1",
+                        .to_irq = samsung_gpiolib_to_irq,
                 },
         }, {
                 .base   = (S5P_VA_GPIO + 0xC40),
                 .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(16),
                 .chip   = {
                         .base   = S5PV210_GPH2(0),
                         .ngpio  = S5PV210_GPIO_H2_NR,
                         .label  = "GPH2",
+                        .to_irq = samsung_gpiolib_to_irq,
                 },
         }, {
                 .base   = (S5P_VA_GPIO + 0xC60),
                 .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(24),
                 .chip   = {
                         .base   = S5PV210_GPH3(0),
                         .ngpio  = S5PV210_GPIO_H3_NR,
                         .label  = "GPH3",
+                        .to_irq = samsung_gpiolib_to_irq,
                 },
         },
 };
@@ -259,11 +268,14 @@ static __init int s5pv210_gpiolib_init(void)
 {
         struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
         int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
+        int gpioint_group = 0;
         int i = 0;
 
         for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL)
+                if (chip->config == NULL) {
                         chip->config = &gpio_cfg;
+                        chip->group = gpioint_group++;
+                }
                 if (chip->base == NULL)
                         chip->base = S5PV210_BANK_BASE(i);
         }
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index e1c020e5a49b..119b95fdc3ce 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -55,8 +55,8 @@
 #define IRQ_SPI1                S5P_IRQ_VIC1(16)
 #define IRQ_SPI2                S5P_IRQ_VIC1(17)
 #define IRQ_IRDA                S5P_IRQ_VIC1(18)
-#define IRQ_CAN0                S5P_IRQ_VIC1(19)
-#define IRQ_CAN1                S5P_IRQ_VIC1(20)
+#define IRQ_IIC2                S5P_IRQ_VIC1(19)
+#define IRQ_IIC3                S5P_IRQ_VIC1(20)
 #define IRQ_HSIRX               S5P_IRQ_VIC1(21)
 #define IRQ_HSITX               S5P_IRQ_VIC1(22)
 #define IRQ_UHOST               S5P_IRQ_VIC1(23)
@@ -109,7 +109,7 @@
 
 #define IRQ_IPC                 S5P_IRQ_VIC3(0)
 #define IRQ_HOSTIF              S5P_IRQ_VIC3(1)
-#define IRQ_MMC3                S5P_IRQ_VIC3(2)
+#define IRQ_HSMMC3              S5P_IRQ_VIC3(2)
 #define IRQ_CEC                 S5P_IRQ_VIC3(3)
 #define IRQ_TSI                 S5P_IRQ_VIC3(4)
 #define IRQ_MDNIE0              S5P_IRQ_VIC3(5)
@@ -121,8 +121,12 @@
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
 
+/* GPIO interrupt */
+#define S5P_GPIOINT_BASE        (IRQ_EINT(31) + 1)
+#define S5P_GPIOINT_GROUP_MAXNR 22
+
 /* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_EINT(31) + 1)
+#define NR_IRQS                 (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO            IRQ_LCD0
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index bd9afd52466a..861d7fe11fc9 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -57,6 +57,8 @@
 
 #define S5P_SZ_UART             SZ_256
 
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+
 #define S5PV210_PA_SROMC        (0xE8000000)
 
 #define S5PV210_PA_CFCON        (0xE8200000)
@@ -73,6 +75,9 @@
 
 #define S5PV210_PA_HSMMC(x)     (0xEB000000 + ((x) * 0x100000))
 
+#define S5PV210_PA_HSOTG        (0xEC000000)
+#define S5PV210_PA_HSPHY        (0xEC100000)
+
 #define S5PV210_PA_VIC0         (0xF2000000)
 #define S5PV210_PA_VIC1         (0xF2100000)
 #define S5PV210_PA_VIC2         (0xF2200000)
@@ -81,6 +86,9 @@
 #define S5PV210_PA_SDRAM        (0x20000000)
 #define S5P_PA_SDRAM            S5PV210_PA_SDRAM
 
+/* S/PDIF */
+#define S5PV210_PA_SPDIF        0xE1100000
+
 /* I2S */
 #define S5PV210_PA_IIS0         0xEEE30000
 #define S5PV210_PA_IIS1         0xE2100000
@@ -96,6 +104,9 @@
 
 #define S5PV210_PA_ADC          (0xE1700000)
 
+#define S5PV210_PA_DMC0         (0xF0000000)
+#define S5PV210_PA_DMC1         (0xF1400000)
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART             S5PV210_PA_UART
 #define S3C_PA_HSMMC0           S5PV210_PA_HSMMC(0)
@@ -108,6 +119,7 @@
 #define S3C_PA_FB               S5PV210_PA_FB
 #define S3C_PA_RTC              S5PV210_PA_RTC
 #define S3C_PA_WDT              S5PV210_PA_WATCHDOG
+#define S3C_PA_USB_HSOTG        S5PV210_PA_HSOTG
 #define S5P_PA_FIMC0            S5PV210_PA_FIMC0
 #define S5P_PA_FIMC1            S5PV210_PA_FIMC1
 #define S5P_PA_FIMC2            S5PV210_PA_FIMC2
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
new file mode 100644
index 000000000000..e8d394f8b057
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -0,0 +1,43 @@
+/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+        /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+        __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
+        __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+        /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+        /* nothing here yet */
+}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+                                           struct pm_uart_save *save)
+{
+        /* nothing here yet */
+}
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 499aef737476..ebaabe021af9 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -25,6 +25,7 @@
 #define S5P_APLL_CON            S5P_CLKREG(0x100)
 #define S5P_MPLL_CON            S5P_CLKREG(0x108)
 #define S5P_EPLL_CON            S5P_CLKREG(0x110)
+#define S5P_EPLL_CON1           S5P_CLKREG(0x114)
 #define S5P_VPLL_CON            S5P_CLKREG(0x120)
 
 #define S5P_CLK_SRC0            S5P_CLKREG(0x200)
@@ -67,11 +68,28 @@
 #define S5P_CLKGATE_BUS1        S5P_CLKREG(0x488)
 #define S5P_CLK_OUT             S5P_CLKREG(0x500)
 
+/* DIV/MUX STATUS */
+#define S5P_CLKDIV_STAT0        S5P_CLKREG(0x1000)
+#define S5P_CLKDIV_STAT1        S5P_CLKREG(0x1004)
+#define S5P_CLKMUX_STAT0        S5P_CLKREG(0x1100)
+#define S5P_CLKMUX_STAT1        S5P_CLKREG(0x1104)
+
 /* CLKSRC0 */
-#define S5P_CLKSRC0_MUX200_MASK         (0x1<<16)
+#define S5P_CLKSRC0_MUX200_SHIFT        (16)
+#define S5P_CLKSRC0_MUX200_MASK         (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
 #define S5P_CLKSRC0_MUX166_MASK         (0x1<<20)
 #define S5P_CLKSRC0_MUX133_MASK         (0x1<<24)
 
+/* CLKSRC2 */
+#define S5P_CLKSRC2_G3D_SHIFT           (0)
+#define S5P_CLKSRC2_G3D_MASK            (0x3 << S5P_CLKSRC2_G3D_SHIFT)
+#define S5P_CLKSRC2_MFC_SHIFT           (4)
+#define S5P_CLKSRC2_MFC_MASK            (0x3 << S5P_CLKSRC2_MFC_SHIFT)
+
+/* CLKSRC6*/
+#define S5P_CLKSRC6_ONEDRAM_SHIFT       (24)
+#define S5P_CLKSRC6_ONEDRAM_MASK        (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
+
 /* CLKDIV0 */
 #define S5P_CLKDIV0_APLL_SHIFT          (0)
 #define S5P_CLKDIV0_APLL_MASK           (0x7 << S5P_CLKDIV0_APLL_SHIFT)
@@ -90,12 +108,24 @@
 #define S5P_CLKDIV0_PCLK66_SHIFT        (28)
 #define S5P_CLKDIV0_PCLK66_MASK         (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
 
+/* CLKDIV2 */
+#define S5P_CLKDIV2_G3D_SHIFT           (0)
+#define S5P_CLKDIV2_G3D_MASK            (0xF << S5P_CLKDIV2_G3D_SHIFT)
+#define S5P_CLKDIV2_MFC_SHIFT           (4)
+#define S5P_CLKDIV2_MFC_MASK            (0xF << S5P_CLKDIV2_MFC_SHIFT)
+
+/* CLKDIV6 */
+#define S5P_CLKDIV6_ONEDRAM_SHIFT       (28)
+#define S5P_CLKDIV6_ONEDRAM_MASK        (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
+
 #define S5P_SWRESET             S5P_CLKREG(0x2000)
 
+#define S5P_ARM_MCS_CON         S5P_CLKREG(0x6100)
+
 /* Registers related to power management */
 #define S5P_PWR_CFG             S5P_CLKREG(0xC000)
 #define S5P_EINT_WAKEUP_MASK    S5P_CLKREG(0xC004)
-#define S5P_WAKEUP_MASK         S5P_CLKREG(0xC008)
+#define S5P_WAKEUP_MASK         S5P_CLKREG(0xC008)
 #define S5P_PWR_MODE            S5P_CLKREG(0xC00C)
 #define S5P_NORMAL_CFG          S5P_CLKREG(0xC010)
 #define S5P_IDLE_CFG            S5P_CLKREG(0xC020)
@@ -159,8 +189,11 @@
 #define S5P_SLEEP_CFG_USBOSC_EN         (1 << 1)
 
 /* OTHERS Resgister */
+#define S5P_OTHERS_RET_IO               (1 << 31)
+#define S5P_OTHERS_RET_CF               (1 << 30)
+#define S5P_OTHERS_RET_MMC              (1 << 29)
+#define S5P_OTHERS_RET_UART             (1 << 28)
 #define S5P_OTHERS_USB_SIG_MASK         (1 << 16)
-#define S5P_OTHERS_MIPI_DPHY_EN         (1 << 28)
 
 /* MIPI */
 #define S5P_MIPI_DPHY_EN                (3)
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
index 49e029b4978a..de0c89976078 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
@@ -31,13 +31,6 @@
 
 #define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
 
-/* values for S5P_EXTINT0 */
-#define S5P_EXTINT_LOWLEV               (0x00)
-#define S5P_EXTINT_HILEV                (0x01)
-#define S5P_EXTINT_FALLEDGE             (0x02)
-#define S5P_EXTINT_RISEEDGE             (0x03)
-#define S5P_EXTINT_BOTHEDGE             (0x04)
-
 #define EINT_MODE               S3C_GPIO_SFN(0xf)
 
 #define EINT_GPIO_0(x)          S5PV210_GPH0(x)
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-sys.h b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
new file mode 100644
index 000000000000..26691d39d0f4
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-sys.h
@@ -0,0 +1,19 @@
+/* arch/arm/mach-s5pv210/include/mach/regs-sys.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PV210 - System registers definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S5PV210_USB_PHY_CON     (S3C_VA_SYS + 0xE80C)
+#define S5PV210_USB_PHY0_EN     (1 << 0)
+#define S5PV210_USB_PHY1_EN     (1 << 1)
+
+/* compatibility defines for s3c-hsotg driver */
+#define S3C64XX_OTHERS          S5PV210_USB_PHY_CON
+#define S3C64XX_OTHERS_USBMASK  S5PV210_USB_PHY0_EN
diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
index df9a28808323..a6c659d68a5d 100644
--- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H __FILE__
 
-#define VMALLOC_END     (0xE0000000UL)
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 00883087363c..28677caf3613 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -16,6 +16,8 @@
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/mfd/max8998.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/regulator/fixed.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
@@ -379,6 +381,119 @@ static struct max8998_platform_data aquila_max8998_pdata = {
 };
 #endif
 
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+        {
+                .dev_name       = "5-001a",
+                .supply         = "DBVDD",
+        }, {
+                .dev_name       = "5-001a",
+                .supply         = "AVDD2",
+        }, {
+                .dev_name       = "5-001a",
+                .supply         = "CPVDD",
+        },
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+        {
+                .dev_name       = "5-001a",
+                .supply         = "SPKVDD1",
+        }, {
+                .dev_name       = "5-001a",
+                .supply         = "SPKVDD2",
+        },
+};
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+        .constraints = {
+                .always_on = 1,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+        .consumer_supplies      = wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+        .constraints = {
+                .always_on = 1,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+        .consumer_supplies      = wm8994_fixed_voltage1_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+        .supply_name    = "VCC_1.8V_PDA",
+        .microvolts     = 1800000,
+        .gpio           = -EINVAL,
+        .init_data      = &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+        .supply_name    = "V_BAT",
+        .microvolts     = 3700000,
+        .gpio           = -EINVAL,
+        .init_data      = &wm8994_fixed_voltage1_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+        .name           = "reg-fixed-voltage",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &wm8994_fixed_voltage0_config,
+        },
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &wm8994_fixed_voltage1_config,
+        },
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply = {
+        .dev_name       = "5-001a",
+        .supply         = "AVDD1",
+};
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply = {
+        .dev_name       = "5-001a",
+        .supply         = "DCVDD",
+};
+
+static struct regulator_init_data wm8994_ldo1_data = {
+        .constraints    = {
+                .name           = "AVDD1_3.0V",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+        .constraints    = {
+                .name           = "DCVDD_1.0V",
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+        /* configure gpio1 function: 0x0001(Logic level input/output) */
+        .gpio_defaults[0] = 0x0001,
+        /* configure gpio3/4/5/7 function for AIF2 voice */
+        .gpio_defaults[2] = 0x8100,
+        .gpio_defaults[3] = 0x8100,
+        .gpio_defaults[4] = 0x8100,
+        .gpio_defaults[6] = 0x0100,
+        /* configure gpio8/9/10/11 function for AIF3 BT */
+        .gpio_defaults[7] = 0x8100,
+        .gpio_defaults[8] = 0x0100,
+        .gpio_defaults[9] = 0x0100,
+        .gpio_defaults[10] = 0x0100,
+        .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
+        .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
 /* GPIO I2C PMIC */
 #define AP_I2C_GPIO_PMIC_BUS_4  4
 static struct i2c_gpio_platform_data aquila_i2c_gpio_pmic_data = {
@@ -404,6 +519,29 @@ static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
 #endif
 };
 
+/* GPIO I2C AP 1.8V */
+#define AP_I2C_GPIO_BUS_5       5
+static struct i2c_gpio_platform_data aquila_i2c_gpio5_data = {
+        .sda_pin        = S5PV210_MP05(3),      /* XM0ADDR_11 */
+        .scl_pin        = S5PV210_MP05(2),      /* XM0ADDR_10 */
+};
+
+static struct platform_device aquila_i2c_gpio5 = {
+        .name           = "i2c-gpio",
+        .id             = AP_I2C_GPIO_BUS_5,
+        .dev            = {
+                .platform_data  = &aquila_i2c_gpio5_data,
+        },
+};
+
+static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
+        {
+                /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
+                I2C_BOARD_INFO("wm8994", 0x1a),
+                .platform_data  = &wm8994_platform_data,
+        },
+};
+
 /* PMIC Power button */
 static struct gpio_keys_button aquila_gpio_keys_table[] = {
         {
@@ -475,6 +613,7 @@ static void aquila_setup_sdhci(void)
 
 static struct platform_device *aquila_devices[] __initdata = {
         &aquila_i2c_gpio_pmic,
+        &aquila_i2c_gpio5,
         &aquila_device_gpiokeys,
         &s3c_device_fb,
         &s5p_device_onenand,
@@ -484,8 +623,33 @@ static struct platform_device *aquila_devices[] __initdata = {
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
+        &s5pv210_device_iis0,
+        &wm8994_fixed_voltage0,
+        &wm8994_fixed_voltage1,
 };
 
+static void __init aquila_sound_init(void)
+{
+        unsigned int gpio;
+
+        /* CODEC_XTAL_EN
+         *
+         * The Aquila board have a oscillator which provide main clock
+         * to WM8994 codec. The oscillator provide 24MHz clock to WM8994
+         * clock. Set gpio setting of "CODEC_XTAL_EN" to enable a oscillator.
+         * */
+        gpio = S5PV210_GPH3(2);         /* XEINT_26 */
+        gpio_request(gpio, "CODEC_XTAL_EN");
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_OUTPUT);
+        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+        /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
+         * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
+         * because it needs 24MHz clock to operate WM8994 codec.
+         */
+        __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
+}
+
 static void __init aquila_map_io(void)
 {
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -506,6 +670,11 @@ static void __init aquila_machine_init(void)
         s3c_fimc_setname(1, "s5p-fimc");
         s3c_fimc_setname(2, "s5p-fimc");
 
+        /* SOUND */
+        aquila_sound_init();
+        i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
+                        ARRAY_SIZE(i2c_gpio5_devs));
+
         /* FB */
         s3c_fb_set_platdata(&aquila_lcd_pdata);
 
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index d9ecf57fc2a5..b1dcf964a768 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -15,7 +15,13 @@
 #include <linux/fb.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
+#include <linux/i2c/qt602240_ts.h>
 #include <linux/mfd/max8998.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <linux/regulator/fixed.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi_gpio.h>
+#include <linux/lcd.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
@@ -35,7 +41,10 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
+#include <plat/iic.h>
+#include <plat/keypad.h>
 #include <plat/sdhci.h>
+#include <plat/clock.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define GONI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
@@ -87,13 +96,12 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 /* Frame Buffer */
 static struct s3c_fb_pd_win goni_fb_win0 = {
         .win_mode = {
-                .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*55),
                 .left_margin    = 16,
                 .right_margin   = 16,
-                .upper_margin   = 3,
+                .upper_margin   = 2,
                 .lower_margin   = 28,
                 .hsync_len      = 2,
-                .vsync_len      = 2,
+                .vsync_len      = 1,
                 .xres           = 480,
                 .yres           = 800,
                 .refresh        = 55,
@@ -111,9 +119,160 @@ static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
         .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
 };
 
+static int lcd_power_on(struct lcd_device *ld, int enable)
+{
+        return 1;
+}
+
+static int reset_lcd(struct lcd_device *ld)
+{
+        static unsigned int first = 1;
+        int reset_gpio = -1;
+
+        reset_gpio = S5PV210_MP05(5);
+
+        if (first) {
+                gpio_request(reset_gpio, "MLCD_RST");
+                first = 0;
+        }
+
+        gpio_direction_output(reset_gpio, 1);
+        return 1;
+}
+
+static struct lcd_platform_data goni_lcd_platform_data = {
+        .reset                  = reset_lcd,
+        .power_on               = lcd_power_on,
+        .lcd_enabled            = 0,
+        .reset_delay            = 120,  /* 120ms */
+        .power_on_delay         = 25,   /* 25ms */
+        .power_off_delay        = 200,  /* 200ms */
+};
+
+#define LCD_BUS_NUM     3
+static struct spi_board_info spi_board_info[] __initdata = {
+        {
+                .modalias       = "s6e63m0",
+                .platform_data  = &goni_lcd_platform_data,
+                .max_speed_hz   = 1200000,
+                .bus_num        = LCD_BUS_NUM,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_3,
+                .controller_data = (void *)S5PV210_MP01(1), /* DISPLAY_CS */
+        },
+};
+
+static struct spi_gpio_platform_data lcd_spi_gpio_data = {
+        .sck    = S5PV210_MP04(1), /* DISPLAY_CLK */
+        .mosi   = S5PV210_MP04(3), /* DISPLAY_SI */
+        .miso   = SPI_GPIO_NO_MISO,
+        .num_chipselect = 1,
+};
+
+static struct platform_device goni_spi_gpio = {
+        .name   = "spi_gpio",
+        .id     = LCD_BUS_NUM,
+        .dev    = {
+                .parent         = &s3c_device_fb.dev,
+                .platform_data  = &lcd_spi_gpio_data,
+        },
+};
+
+/* KEYPAD */
+static uint32_t keymap[] __initdata = {
+        /* KEY(row, col, keycode) */
+        KEY(0, 1, KEY_MENU),            /* Send */
+        KEY(0, 2, KEY_BACK),            /* End */
+        KEY(1, 1, KEY_CONFIG),          /* Half shot */
+        KEY(1, 2, KEY_VOLUMEUP),
+        KEY(2, 1, KEY_CAMERA),          /* Full shot */
+        KEY(2, 2, KEY_VOLUMEDOWN),
+};
+
+static struct matrix_keymap_data keymap_data __initdata = {
+        .keymap         = keymap,
+        .keymap_size    = ARRAY_SIZE(keymap),
+};
+
+static struct samsung_keypad_platdata keypad_data __initdata = {
+        .keymap_data    = &keymap_data,
+        .rows           = 3,
+        .cols           = 3,
+};
+
+/* Radio */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("si470x", 0x10),
+        },
+};
+
+static void __init goni_radio_init(void)
+{
+        int gpio;
+
+        gpio = S5PV210_GPJ2(4);                 /* XMSMDATA_4 */
+        gpio_request(gpio, "FM_INT");
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        i2c1_devs[0].irq = gpio_to_irq(gpio);
+
+        gpio = S5PV210_GPJ2(5);                 /* XMSMDATA_5 */
+        gpio_request(gpio, "FM_RST");
+        gpio_direction_output(gpio, 1);
+}
+
+/* TSP */
+static struct qt602240_platform_data qt602240_platform_data = {
+        .x_line         = 17,
+        .y_line         = 11,
+        .x_size         = 800,
+        .y_size         = 480,
+        .blen           = 0x21,
+        .threshold      = 0x28,
+        .voltage        = 2800000,              /* 2.8V */
+        .orient         = QT602240_DIAGONAL,
+};
+
+static struct s3c2410_platform_i2c i2c2_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 2,
+        .slave_addr     = 0x10,
+        .frequency      = 400 * 1000,
+        .sda_delay      = 100,
+};
+
+static struct i2c_board_info i2c2_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("qt602240_ts", 0x4a),
+                .platform_data = &qt602240_platform_data,
+        },
+};
+
+static void __init goni_tsp_init(void)
+{
+        int gpio;
+
+        gpio = S5PV210_GPJ1(3);         /* XMSMADDR_11 */
+        gpio_request(gpio, "TSP_LDO_ON");
+        gpio_direction_output(gpio, 1);
+        gpio_export(gpio, 0);
+
+        gpio = S5PV210_GPJ0(5);         /* XMSMADDR_5 */
+        gpio_request(gpio, "TSP_INT");
+
+        s5p_register_gpio_interrupt(gpio);
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+        i2c2_devs[0].irq = gpio_to_irq(gpio);
+}
+
 /* MAX8998 regulators */
 #if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
 
+static struct regulator_consumer_supply goni_ldo5_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+};
+
 static struct regulator_init_data goni_ldo2_data = {
         .constraints    = {
                 .name           = "VALIVE_1.1V",
@@ -153,6 +312,8 @@ static struct regulator_init_data goni_ldo5_data = {
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
         },
+        .num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
+        .consumer_supplies = goni_ldo5_consumers,
 };
 
 static struct regulator_init_data goni_ldo6_data = {
@@ -360,6 +521,119 @@ static struct max8998_platform_data goni_max8998_pdata = {
 };
 #endif
 
+static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
+        {
+                .dev_name       = "5-001a",
+                .supply         = "DBVDD",
+        }, {
+                .dev_name       = "5-001a",
+                .supply         = "AVDD2",
+        }, {
+                .dev_name       = "5-001a",
+                .supply         = "CPVDD",
+        },
+};
+
+static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
+        {
+                .dev_name       = "5-001a",
+                .supply         = "SPKVDD1",
+        }, {
+                .dev_name       = "5-001a",
+                .supply         = "SPKVDD2",
+        },
+};
+
+static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
+        .constraints = {
+                .always_on = 1,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage0_supplies),
+        .consumer_supplies      = wm8994_fixed_voltage0_supplies,
+};
+
+static struct regulator_init_data wm8994_fixed_voltage1_init_data = {
+        .constraints = {
+                .always_on = 1,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(wm8994_fixed_voltage1_supplies),
+        .consumer_supplies      = wm8994_fixed_voltage1_supplies,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage0_config = {
+        .supply_name    = "VCC_1.8V_PDA",
+        .microvolts     = 1800000,
+        .gpio           = -EINVAL,
+        .init_data      = &wm8994_fixed_voltage0_init_data,
+};
+
+static struct fixed_voltage_config wm8994_fixed_voltage1_config = {
+        .supply_name    = "V_BAT",
+        .microvolts     = 3700000,
+        .gpio           = -EINVAL,
+        .init_data      = &wm8994_fixed_voltage1_init_data,
+};
+
+static struct platform_device wm8994_fixed_voltage0 = {
+        .name           = "reg-fixed-voltage",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &wm8994_fixed_voltage0_config,
+        },
+};
+
+static struct platform_device wm8994_fixed_voltage1 = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &wm8994_fixed_voltage1_config,
+        },
+};
+
+static struct regulator_consumer_supply wm8994_avdd1_supply = {
+        .dev_name       = "5-001a",
+        .supply         = "AVDD1",
+};
+
+static struct regulator_consumer_supply wm8994_dcvdd_supply = {
+        .dev_name       = "5-001a",
+        .supply         = "DCVDD",
+};
+
+static struct regulator_init_data wm8994_ldo1_data = {
+        .constraints    = {
+                .name           = "AVDD1_3.0V",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &wm8994_avdd1_supply,
+};
+
+static struct regulator_init_data wm8994_ldo2_data = {
+        .constraints    = {
+                .name           = "DCVDD_1.0V",
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &wm8994_dcvdd_supply,
+};
+
+static struct wm8994_pdata wm8994_platform_data = {
+        /* configure gpio1 function: 0x0001(Logic level input/output) */
+        .gpio_defaults[0] = 0x0001,
+        /* configure gpio3/4/5/7 function for AIF2 voice */
+        .gpio_defaults[2] = 0x8100,
+        .gpio_defaults[3] = 0x8100,
+        .gpio_defaults[4] = 0x8100,
+        .gpio_defaults[6] = 0x0100,
+        /* configure gpio8/9/10/11 function for AIF3 BT */
+        .gpio_defaults[7] = 0x8100,
+        .gpio_defaults[8] = 0x0100,
+        .gpio_defaults[9] = 0x0100,
+        .gpio_defaults[10] = 0x0100,
+        .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
+        .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+};
+
 /* GPIO I2C PMIC */
 #define AP_I2C_GPIO_PMIC_BUS_4  4
 static struct i2c_gpio_platform_data goni_i2c_gpio_pmic_data = {
@@ -385,6 +659,29 @@ static struct i2c_board_info i2c_gpio_pmic_devs[] __initdata = {
 #endif
 };
 
+/* GPIO I2C AP 1.8V */
+#define AP_I2C_GPIO_BUS_5       5
+static struct i2c_gpio_platform_data goni_i2c_gpio5_data = {
+        .sda_pin        = S5PV210_MP05(3),      /* XM0ADDR_11 */
+        .scl_pin        = S5PV210_MP05(2),      /* XM0ADDR_10 */
+};
+
+static struct platform_device goni_i2c_gpio5 = {
+        .name           = "i2c-gpio",
+        .id             = AP_I2C_GPIO_BUS_5,
+        .dev            = {
+                .platform_data  = &goni_i2c_gpio5_data,
+        },
+};
+
+static struct i2c_board_info i2c_gpio5_devs[] __initdata = {
+        {
+                /* CS/ADDR = low 0x34 (FYI: high = 0x36) */
+                I2C_BOARD_INFO("wm8994", 0x1a),
+                .platform_data  = &wm8994_platform_data,
+        },
+};
+
 /* PMIC Power button */
 static struct gpio_keys_button goni_gpio_keys_table[] = {
         {
@@ -444,11 +741,37 @@ static struct s3c_sdhci_platdata goni_hsmmc2_data __initdata = {
         .ext_cd_gpio_invert     = 1,
 };
 
+static struct regulator_consumer_supply mmc2_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
+};
+
+static struct regulator_init_data mmc2_fixed_voltage_init_data = {
+        .constraints            = {
+                .name           = "V_TF_2.8V",
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(mmc2_supplies),
+        .consumer_supplies      = mmc2_supplies,
+};
+
+static struct fixed_voltage_config mmc2_fixed_voltage_config = {
+        .supply_name            = "EXT_FLASH_EN",
+        .microvolts             = 2800000,
+        .gpio                   = GONI_EXT_FLASH_EN,
+        .enable_high            = true,
+        .init_data              = &mmc2_fixed_voltage_init_data,
+};
+
+static struct platform_device mmc2_fixed_voltage = {
+        .name           = "reg-fixed-voltage",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &mmc2_fixed_voltage_config,
+        },
+};
+
 static void goni_setup_sdhci(void)
 {
-        gpio_request(GONI_EXT_FLASH_EN, "FLASH_EN");
-        gpio_direction_output(GONI_EXT_FLASH_EN, 1);
-
         s3c_sdhci0_set_platdata(&goni_hsmmc0_data);
         s3c_sdhci1_set_platdata(&goni_hsmmc1_data);
         s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
@@ -457,7 +780,10 @@ static void goni_setup_sdhci(void)
 static struct platform_device *goni_devices[] __initdata = {
         &s3c_device_fb,
         &s5p_device_onenand,
+        &goni_spi_gpio,
         &goni_i2c_gpio_pmic,
+        &goni_i2c_gpio5,
+        &mmc2_fixed_voltage,
         &goni_device_gpiokeys,
         &s5p_device_fimc0,
         &s5p_device_fimc1,
@@ -465,8 +791,24 @@ static struct platform_device *goni_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
         &s3c_device_hsmmc2,
+        &s5pv210_device_iis0,
+        &s3c_device_usb_hsotg,
+        &samsung_device_keypad,
+        &s3c_device_i2c1,
+        &s3c_device_i2c2,
+        &wm8994_fixed_voltage0,
+        &wm8994_fixed_voltage1,
 };
 
+static void __init goni_sound_init(void)
+{
+        /* Ths main clock of WM8994 codec uses the output of CLKOUT pin.
+         * The CLKOUT[9:8] set to 0x3(XUSBXTI) of 0xE010E000(OTHERS)
+         * because it needs 24MHz clock to operate WM8994 codec.
+         */
+        __raw_writel(__raw_readl(S5P_OTHERS) | (0x3 << 8), S5P_OTHERS);
+}
+
 static void __init goni_map_io(void)
 {
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -476,6 +818,20 @@ static void __init goni_map_io(void)
 
 static void __init goni_machine_init(void)
 {
+        /* Radio: call before I2C 1 registeration */
+        goni_radio_init();
+
+        /* I2C1 */
+        s3c_i2c1_set_platdata(NULL);
+        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+
+        /* TSP: call before I2C 2 registeration */
+        goni_tsp_init();
+
+        /* I2C2 */
+        s3c_i2c2_set_platdata(&i2c2_data);
+        i2c_register_board_info(2, i2c2_devs, ARRAY_SIZE(i2c2_devs));
+
         /* PMIC */
         goni_pmic_init();
         i2c_register_board_info(AP_I2C_GPIO_PMIC_BUS_4, i2c_gpio_pmic_devs,
@@ -483,9 +839,22 @@ static void __init goni_machine_init(void)
         /* SDHCI */
         goni_setup_sdhci();
 
+        /* SOUND */
+        goni_sound_init();
+        i2c_register_board_info(AP_I2C_GPIO_BUS_5, i2c_gpio5_devs,
+                        ARRAY_SIZE(i2c_gpio5_devs));
+
         /* FB */
         s3c_fb_set_platdata(&goni_lcd_pdata);
 
+        /* SPI */
+        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+        /* KEYPAD */
+        samsung_keypad_set_platdata(&keypad_data);
+
+        clk_xusbxti.rate = 24000000;
+
         platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
 }
 
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index cea9bca79d88..0ad7924fe62e 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -28,6 +28,7 @@
 #include <plat/cpu.h>
 #include <plat/ata.h>
 #include <plat/iic.h>
+#include <plat/pm.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKC110_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -81,6 +82,7 @@ static struct s3c_ide_platdata smdkc110_ide_pdata __initdata = {
 static struct platform_device *smdkc110_devices[] __initdata = {
         &s5pv210_device_iis0,
         &s5pv210_device_ac97,
+        &s5pv210_device_spdif,
         &s3c_device_cfcon,
         &s3c_device_i2c0,
         &s3c_device_i2c1,
@@ -110,6 +112,8 @@ static void __init smdkc110_map_io(void)
 
 static void __init smdkc110_machine_init(void)
 {
+        s3c_pm_init();
+
         s3c_i2c0_set_platdata(NULL);
         s3c_i2c1_set_platdata(NULL);
         s3c_i2c2_set_platdata(NULL);
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 83189ae9da9a..bcd7a5d53401 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -31,6 +31,7 @@
 #include <plat/ata.h>
 #include <plat/iic.h>
 #include <plat/keypad.h>
+#include <plat/pm.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -103,6 +104,7 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
 static struct platform_device *smdkv210_devices[] __initdata = {
         &s5pv210_device_iis0,
         &s5pv210_device_ac97,
+        &s5pv210_device_spdif,
         &s3c_device_adc,
         &s3c_device_cfcon,
         &s3c_device_hsmmc0,
@@ -145,6 +147,8 @@ static void __init smdkv210_map_io(void)
 
 static void __init smdkv210_machine_init(void)
 {
+        s3c_pm_init();
+
         samsung_keypad_set_platdata(&smdkv210_keypad_data);
         s3c24xx_ts_set_platdata(&s3c_ts_platform);
 
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
new file mode 100644
index 000000000000..043c938806b0
--- /dev/null
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -0,0 +1,131 @@
+/* linux/arch/arm/mach-s5pv210/mach-torbreck.c
+ *
+ * Copyright (c) 2010 aESOP Community
+ *              http://www.aesop.or.kr/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/regs-serial.h>
+#include <plat/s5pv210.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/iic.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define TORBRECK_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define TORBRECK_ULCON_DEFAULT  S3C2410_LCON_CS8
+
+#define TORBRECK_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = TORBRECK_UCON_DEFAULT,
+                .ulcon          = TORBRECK_ULCON_DEFAULT,
+                .ufcon          = TORBRECK_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = TORBRECK_UCON_DEFAULT,
+                .ulcon          = TORBRECK_ULCON_DEFAULT,
+                .ufcon          = TORBRECK_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = TORBRECK_UCON_DEFAULT,
+                .ulcon          = TORBRECK_ULCON_DEFAULT,
+                .ufcon          = TORBRECK_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = TORBRECK_UCON_DEFAULT,
+                .ulcon          = TORBRECK_ULCON_DEFAULT,
+                .ufcon          = TORBRECK_UFCON_DEFAULT,
+        },
+};
+
+static struct platform_device *torbreck_devices[] __initdata = {
+        &s5pv210_device_iis0,
+        &s3c_device_cfcon,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_i2c2,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+};
+
+static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
+        /* To Be Updated */
+};
+
+static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
+        /* To Be Updated */
+};
+
+static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
+        /* To Be Updated */
+};
+
+static void __init torbreck_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
+}
+
+static void __init torbreck_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        s3c_i2c1_set_platdata(NULL);
+        s3c_i2c2_set_platdata(NULL);
+        i2c_register_board_info(0, torbreck_i2c_devs0,
+                        ARRAY_SIZE(torbreck_i2c_devs0));
+        i2c_register_board_info(1, torbreck_i2c_devs1,
+                        ARRAY_SIZE(torbreck_i2c_devs1));
+        i2c_register_board_info(2, torbreck_i2c_devs2,
+                        ARRAY_SIZE(torbreck_i2c_devs2));
+
+        platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
+}
+
+MACHINE_START(TORBRECK, "TORBRECK")
+        /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
+        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .init_irq       = s5pv210_init_irq,
+        .map_io         = torbreck_map_io,
+        .init_machine   = torbreck_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
new file mode 100644
index 000000000000..549d7924fd4c
--- /dev/null
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -0,0 +1,166 @@
+/* linux/arch/arm/mach-s5pv210/pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV210 - Power Management support
+ *
+ * Based on arch/arm/mach-s3c2410/pm.c
+ * Copyright (c) 2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-timer.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-clock.h>
+
+static struct sleep_save s5pv210_core_save[] = {
+        /* Clock source */
+        SAVE_ITEM(S5P_CLK_SRC0),
+        SAVE_ITEM(S5P_CLK_SRC1),
+        SAVE_ITEM(S5P_CLK_SRC2),
+        SAVE_ITEM(S5P_CLK_SRC3),
+        SAVE_ITEM(S5P_CLK_SRC4),
+        SAVE_ITEM(S5P_CLK_SRC5),
+        SAVE_ITEM(S5P_CLK_SRC6),
+
+        /* Clock source Mask */
+        SAVE_ITEM(S5P_CLK_SRC_MASK0),
+        SAVE_ITEM(S5P_CLK_SRC_MASK1),
+
+        /* Clock Divider */
+        SAVE_ITEM(S5P_CLK_DIV0),
+        SAVE_ITEM(S5P_CLK_DIV1),
+        SAVE_ITEM(S5P_CLK_DIV2),
+        SAVE_ITEM(S5P_CLK_DIV3),
+        SAVE_ITEM(S5P_CLK_DIV4),
+        SAVE_ITEM(S5P_CLK_DIV5),
+        SAVE_ITEM(S5P_CLK_DIV6),
+        SAVE_ITEM(S5P_CLK_DIV7),
+
+        /* Clock Main Gate */
+        SAVE_ITEM(S5P_CLKGATE_MAIN0),
+        SAVE_ITEM(S5P_CLKGATE_MAIN1),
+        SAVE_ITEM(S5P_CLKGATE_MAIN2),
+
+        /* Clock source Peri Gate */
+        SAVE_ITEM(S5P_CLKGATE_PERI0),
+        SAVE_ITEM(S5P_CLKGATE_PERI1),
+
+        /* Clock source SCLK Gate */
+        SAVE_ITEM(S5P_CLKGATE_SCLK0),
+        SAVE_ITEM(S5P_CLKGATE_SCLK1),
+
+        /* Clock IP Clock gate */
+        SAVE_ITEM(S5P_CLKGATE_IP0),
+        SAVE_ITEM(S5P_CLKGATE_IP1),
+        SAVE_ITEM(S5P_CLKGATE_IP2),
+        SAVE_ITEM(S5P_CLKGATE_IP3),
+        SAVE_ITEM(S5P_CLKGATE_IP4),
+
+        /* Clock Blcok and Bus gate */
+        SAVE_ITEM(S5P_CLKGATE_BLOCK),
+        SAVE_ITEM(S5P_CLKGATE_BUS0),
+
+        /* Clock ETC */
+        SAVE_ITEM(S5P_CLK_OUT),
+        SAVE_ITEM(S5P_MDNIE_SEL),
+
+        /* PWM Register */
+        SAVE_ITEM(S3C2410_TCFG0),
+        SAVE_ITEM(S3C2410_TCFG1),
+        SAVE_ITEM(S3C64XX_TINT_CSTAT),
+        SAVE_ITEM(S3C2410_TCON),
+        SAVE_ITEM(S3C2410_TCNTB(0)),
+        SAVE_ITEM(S3C2410_TCMPB(0)),
+        SAVE_ITEM(S3C2410_TCNTO(0)),
+};
+
+void s5pv210_cpu_suspend(void)
+{
+        unsigned long tmp;
+
+        /* issue the standby signal into the pm unit. Note, we
+         * issue a write-buffer drain just in case */
+
+        tmp = 0;
+
+        asm("b 1f\n\t"
+            ".align 5\n\t"
+            "1:\n\t"
+            "mcr p15, 0, %0, c7, c10, 5\n\t"
+            "mcr p15, 0, %0, c7, c10, 4\n\t"
+            "wfi" : : "r" (tmp));
+
+        /* we should never get past here */
+        panic("sleep resumed to originator?");
+}
+
+static void s5pv210_pm_prepare(void)
+{
+        unsigned int tmp;
+
+        /* ensure at least INFORM0 has the resume address */
+        __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+
+        tmp = __raw_readl(S5P_SLEEP_CFG);
+        tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
+        __raw_writel(tmp, S5P_SLEEP_CFG);
+
+        /* WFI for SLEEP mode configuration by SYSCON */
+        tmp = __raw_readl(S5P_PWR_CFG);
+        tmp &= S5P_CFG_WFI_CLEAN;
+        tmp |= S5P_CFG_WFI_SLEEP;
+        __raw_writel(tmp, S5P_PWR_CFG);
+
+        /* SYSCON interrupt handling disable */
+        tmp = __raw_readl(S5P_OTHERS);
+        tmp |= S5P_OTHER_SYSC_INTOFF;
+        __raw_writel(tmp, S5P_OTHERS);
+
+        s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
+}
+
+static int s5pv210_pm_add(struct sys_device *sysdev)
+{
+        pm_cpu_prep = s5pv210_pm_prepare;
+        pm_cpu_sleep = s5pv210_cpu_suspend;
+
+        return 0;
+}
+
+static int s5pv210_pm_resume(struct sys_device *dev)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(S5P_OTHERS);
+        tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |\
+                S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
+        __raw_writel(tmp , S5P_OTHERS);
+
+        s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
+
+        return 0;
+}
+
+static struct sysdev_driver s5pv210_pm_driver = {
+        .add            = s5pv210_pm_add,
+        .resume         = s5pv210_pm_resume,
+};
+
+static __init int s5pv210_pm_drvinit(void)
+{
+        return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
+}
+arch_initcall(s5pv210_pm_drvinit);
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
index 928cf1f125fa..e932ebfac56d 100644
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -21,33 +21,21 @@
 #include <mach/regs-clock.h>
 #include <plat/gpio-cfg.h>
 
-void s5pv210_fb_gpio_setup_24bpp(void)
+static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr)
 {
-        unsigned int gpio = 0;
-
-        for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
 
-        for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+        for (; nr > 0; nr--, base++)
+                s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
+}
 
-        for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
 
-        for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+void s5pv210_fb_gpio_setup_24bpp(void)
+{
+        s5pv210_fb_cfg_gpios(S5PV210_GPF0(0), 8);
+        s5pv210_fb_cfg_gpios(S5PV210_GPF1(0), 8);
+        s5pv210_fb_cfg_gpios(S5PV210_GPF2(0), 8);
+        s5pv210_fb_cfg_gpios(S5PV210_GPF3(0), 4);
 
         /* Set DISPLAY_CONTROL register for Display path selection.
          *
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c
index d38f7cb7e662..0f1cc3a1c1e8 100644
--- a/arch/arm/mach-s5pv210/setup-i2c0.c
+++ b/arch/arm/mach-s5pv210/setup-i2c0.c
@@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PV210_GPD1(0), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPD1(0), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PV210_GPD1(1), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPD1(1), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV210_GPD1(0), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c
index 148bb7857d89..f61365a34c56 100644
--- a/arch/arm/mach-s5pv210/setup-i2c1.c
+++ b/arch/arm/mach-s5pv210/setup-i2c1.c
@@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PV210_GPD1(2), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPD1(2), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PV210_GPD1(3), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPD1(3), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV210_GPD1(2), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c
index 2396cb8c373e..2f91b5cefbc6 100644
--- a/arch/arm/mach-s5pv210/setup-i2c2.c
+++ b/arch/arm/mach-s5pv210/setup-i2c2.c
@@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PV210_GPD1(4), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPD1(4), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PV210_GPD1(5), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV210_GPD1(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV210_GPD1(4), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c
index b558b1cc8d60..ea123d546bd2 100644
--- a/arch/arm/mach-s5pv210/setup-ide.c
+++ b/arch/arm/mach-s5pv210/setup-ide.c
@@ -15,36 +15,25 @@
 
 #include <plat/gpio-cfg.h>
 
+static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr)
+{
+        s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
+
+        for (; nr > 0; nr--, base++)
+                s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
+}
+
 void s5pv210_ide_setup_gpio(void)
 {
-        unsigned int gpio = 0;
-
-        for (gpio = S5PV210_GPJ0(0); gpio <= S5PV210_GPJ0(7); gpio++) {
-                /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST,
-                        CF_DMACK */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        for (gpio = S5PV210_GPJ2(0); gpio <= S5PV210_GPJ2(7); gpio++) {
-                /*CF_Data[0 - 7] */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        for (gpio = S5PV210_GPJ3(0); gpio <= S5PV210_GPJ3(7); gpio++) {
-                /* CF_Data[8 - 15] */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        for (gpio = S5PV210_GPJ4(0); gpio <= S5PV210_GPJ4(3); gpio++) {
-                /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
+        /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
+        s5pv210_ide_cfg_gpios(S5PV210_GPJ0(0), 8);
+
+        /* CF_Data[0 - 7] */
+        s5pv210_ide_cfg_gpios(S5PV210_GPJ2(0), 8);
+
+        /* CF_Data[8 - 15] */
+        s5pv210_ide_cfg_gpios(S5PV210_GPJ3(0), 8);
+
+        /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
+        s5pv210_ide_cfg_gpios(S5PV210_GPJ4(0), 4);
 }
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
index 37b2790aafc3..c56420a52f48 100644
--- a/arch/arm/mach-s5pv210/setup-keypad.c
+++ b/arch/arm/mach-s5pv210/setup-keypad.c
@@ -16,19 +16,9 @@
 
 void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
 {
-        unsigned int gpio, end;
-
         /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
-        end = S5PV210_GPH3(rows);
-        for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PV210_GPH3(0), rows, S3C_GPIO_SFN(3));
 
         /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
-        end = S5PV210_GPH2(cols);
-        for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PV210_GPH2(0), cols, S3C_GPIO_SFN(3));
 }
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index b18587b1ec58..746777d56df9 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -26,26 +26,17 @@
 void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
 
         /* Set all the necessary GPG0/GPG1 pins to special-function 2 */
-        for (gpio = S5PV210_GPG0(0); gpio < S5PV210_GPG0(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PV210_GPG0(0), 2, S3C_GPIO_SFN(2));
+
         switch (width) {
         case 8:
                 /* GPG1[3:6] special-funtion 3 */
-                for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) {
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                }
+                s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(3));
         case 4:
                 /* GPG0[3:6] special-funtion 2 */
-                for (gpio = S5PV210_GPG0(3); gpio <= S5PV210_GPG0(6); gpio++) {
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                }
+                s3c_gpio_cfgrange_nopull(S5PV210_GPG0(3), 4, S3C_GPIO_SFN(2));
         default:
                 break;
         }
@@ -59,19 +50,12 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
 
         /* Set all the necessary GPG1[0:1] pins to special-function 2 */
-        for (gpio = S5PV210_GPG1(0); gpio < S5PV210_GPG1(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PV210_GPG1(0), 2, S3C_GPIO_SFN(2));
 
         /* Data pin GPG1[3:6] to special-function 2 */
-        for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PV210_GPG1(3), 4, S3C_GPIO_SFN(2));
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
                 s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
@@ -82,27 +66,17 @@ void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
 
         /* Set all the necessary GPG2[0:1] pins to special-function 2 */
-        for (gpio = S5PV210_GPG2(0); gpio < S5PV210_GPG2(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PV210_GPG2(0), 2, S3C_GPIO_SFN(2));
 
         switch (width) {
         case 8:
                 /* Data pin GPG3[3:6] to special-function 3 */
-                for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                }
+                s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(3));
         case 4:
                 /* Data pin GPG2[3:6] to special-function 2 */
-                for (gpio = S5PV210_GPG2(3); gpio <= S5PV210_GPG2(6); gpio++) {
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                }
+                s3c_gpio_cfgrange_nopull(S5PV210_GPG2(3), 4, S3C_GPIO_SFN(2));
         default:
                 break;
         }
@@ -116,19 +90,12 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
 {
         struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
 
-        /* Set all the necessary GPG3[0:2] pins to special-function 2 */
-        for (gpio = S5PV210_GPG3(0); gpio < S5PV210_GPG3(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        /* Set all the necessary GPG3[0:1] pins to special-function 2 */
+        s3c_gpio_cfgrange_nopull(S5PV210_GPG3(0), 2, S3C_GPIO_SFN(2));
 
         /* Data pin GPG3[3:6] to special-function 2 */
-        for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        }
+        s3c_gpio_cfgrange_nopull(S5PV210_GPG3(3), 4, S3C_GPIO_SFN(2));
 
         if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
                 s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
new file mode 100644
index 000000000000..d4d222b716b4
--- /dev/null
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -0,0 +1,170 @@
+/* linux/arch/arm/plat-s5p/sleep.S
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV210 power Manager (Suspend-To-RAM) support
+ * Based on S3C2410 sleep code by:
+ *      Ben Dooks, (c) 2004 Simtec Electronics
+ *
+ * Based on PXA/SA1100 sleep code by:
+ *      Nicolas Pitre, (c) 2002 Monta Vista Software Inc
+ *      Cliff Brake, (c) 2001
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/memory.h>
+
+        .text
+
+        /* s3c_cpu_save
+         *
+         * entry:
+         *      r0 = save address (virtual addr of s3c_sleep_save_phys)
+        */
+
+ENTRY(s3c_cpu_save)
+
+        stmfd   sp!, { r3 - r12, lr }
+
+        mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
+        mrc     p15, 0, r6, c2, c0, 0   @ Translation Table BASE0
+        mrc     p15, 0, r7, c2, c0, 1   @ Translation Table BASE1
+        mrc     p15, 0, r8, c2, c0, 2   @ Translation Table Control
+        mrc     p15, 0, r9, c1, c0, 0   @ Control register
+        mrc     p15, 0, r10, c1, c0, 1  @ Auxiliary control register
+        mrc     p15, 0, r11, c1, c0, 2  @ Co-processor access controls
+        mrc     p15, 0, r12, c10, c2, 0 @ Read PRRR
+        mrc     p15, 0, r3, c10, c2, 1  @ READ NMRR
+
+        stmia   r0, { r3 - r13 }
+
+        bl      s3c_pm_cb_flushcache
+
+        ldr     r0, =pm_cpu_sleep
+        ldr     r0, [ r0 ]
+        mov     pc, r0
+
+resume_with_mmu:
+        /*
+         * After MMU is turned on, restore the previous MMU table.
+         */
+        ldr     r9 , =(PAGE_OFFSET - PHYS_OFFSET)
+        add     r4, r4, r9
+        str     r12, [r4]
+
+        ldmfd   sp!, { r3 - r12, pc }
+
+        .ltorg
+
+        .data
+
+        .global s3c_sleep_save_phys
+s3c_sleep_save_phys:
+        .word   0
+
+        /* sleep magic, to allow the bootloader to check for an valid
+         * image to resume to. Must be the first word before the
+         * s3c_cpu_resume entry.
+        */
+
+        .word   0x2bedf00d
+
+        /* s3c_cpu_resume
+         *
+         * resume code entry for bootloader to call
+         *
+         * we must put this code here in the data segment as we have no
+         * other way of restoring the stack pointer after sleep, and we
+         * must not write to the code segment (code is read-only)
+        */
+
+ENTRY(s3c_cpu_resume)
+        mov     r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+        msr     cpsr_c, r0
+
+        mov     r1, #0
+        mcr     p15, 0, r1, c8, c7, 0           @ invalidate TLBs
+        mcr     p15, 0, r1, c7, c5, 0           @ invalidate I Cache
+
+        ldr     r0, s3c_sleep_save_phys         @ address of restore block
+        ldmia   r0, { r3 - r13 }
+
+        mcr     p15, 0, r4, c13, c0, 0          @ FCSE/PID
+        mcr     p15, 0, r5, c3, c0, 0           @ Domain ID
+
+        mcr     p15, 0, r8, c2, c0, 2           @ Translation Table Control
+        mcr     p15, 0, r7, c2, c0, 1           @ Translation Table BASE1
+        mcr     p15, 0, r6, c2, c0, 0           @ Translation Table BASE0
+
+        mcr     p15, 0, r10, c1, c0, 1          @ Auxiliary control register
+
+        mov     r0, #0
+        mcr     p15, 0, r0, c8, c7, 0           @ Invalidate I & D TLB
+
+        mov     r0, #0                          @ restore copro access
+        mcr     p15, 0, r11, c1, c0, 2          @ Co-processor access
+        mcr     p15, 0, r0, c7, c5, 4
+
+        mcr     p15, 0, r12, c10, c2, 0         @ write PRRR
+        mcr     p15, 0, r3, c10, c2, 1          @ write NMRR
+
+        /*
+         * In Cortex-A8, when MMU is turned on, the pipeline is flushed.
+         * And there are no valid entries in the MMU table at this point.
+         * So before turning on the MMU, the MMU entry for the DRAM address
+         * range is added. After the MMU is turned on, the other entries
+         * in the MMU table will be restored.
+        */
+
+        /* r6 = Translation Table BASE0 */
+        mov     r4, r6
+        mov     r4, r4, LSR #14
+        mov     r4, r4, LSL #14
+
+        /* Load address for adding to MMU table list */
+        ldr     r11, =0xE010F000                @ INFORM0 reg.
+        ldr     r10, [r11, #0]
+        mov     r10, r10, LSR #18
+        bic     r10, r10, #0x3
+        orr     r4, r4, r10
+
+        /* Calculate MMU table entry */
+        mov     r10, r10, LSL #18
+        ldr     r5, =0x40E
+        orr     r10, r10, r5
+
+        /* Back up originally data */
+        ldr     r12, [r4]
+
+        /* Add calculated MMU table entry into MMU table list */
+        str     r10, [r4]
+
+        ldr     r2, =resume_with_mmu
+        mcr     p15, 0, r9, c1, c0, 0           @ turn on MMU, etc
+
+        nop
+        nop
+        nop
+        nop
+        nop                                     @ second-to-last before mmu
+
+        mov     pc, r2                          @ go back to virtual address
+
+        .ltorg
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index 331b5bd97aba..1150b360f38c 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -11,7 +11,6 @@ if ARCH_S5PV310
 
 config CPU_S5PV310
         bool
-        select PLAT_S5P
         help
           Enable S5PV310 CPU support
 
@@ -25,21 +24,105 @@ config S5PV310_SETUP_I2C2
         help
           Common setup code for i2c bus 2.
 
+config S5PV310_SETUP_I2C3
+        bool
+        help
+          Common setup code for i2c bus 3.
+
+config S5PV310_SETUP_I2C4
+        bool
+        help
+          Common setup code for i2c bus 4.
+
+config S5PV310_SETUP_I2C5
+        bool
+        help
+          Common setup code for i2c bus 5.
+
+config S5PV310_SETUP_I2C6
+        bool
+        help
+          Common setup code for i2c bus 6.
+
+config S5PV310_SETUP_I2C7
+        bool
+        help
+          Common setup code for i2c bus 7.
+
+config S5PV310_SETUP_SDHCI
+        bool
+        select S5PV310_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PV310 based SDHCI systems.
+
+config S5PV310_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
+
 # machine support
 
-config MACH_SMDKV310
-        bool "SMDKV310"
+menu "S5PC210 Machines"
+
+config MACH_SMDKC210
+        bool "SMDKC210"
         select CPU_S5PV310
-        select ARCH_SPARSEMEM_ENABLE
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S5PV310_SETUP_SDHCI
         help
-          Machine support for Samsung SMDKV310
+          Machine support for Samsung SMDKC210
+          S5PC210(MCP) is one of package option of S5PV310
 
 config MACH_UNIVERSAL_C210
         bool "Mobile UNIVERSAL_C210 Board"
         select CPU_S5PV310
-        select ARCH_SPARSEMEM_ENABLE
+        select S5P_DEV_ONENAND
+        select S3C_DEV_I2C1
+        select S5PV310_SETUP_I2C1
         help
           Machine support for Samsung Mobile Universal S5PC210 Reference
           Board. S5PC210(MCP) is one of package option of S5PV310
 
+endmenu
+
+menu "S5PV310 Machines"
+
+config MACH_SMDKV310
+        bool "SMDKV310"
+        select CPU_S5PV310
+        select S3C_DEV_RTC
+        select S3C_DEV_WDT
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S3C_DEV_HSMMC3
+        select S5PV310_SETUP_SDHCI
+        help
+          Machine support for Samsung SMDKV310
+
+endmenu
+
+comment "Configuration for HSMMC bus width"
+
+menu "Use 8-bit bus width"
+
+config S5PV310_SDHCI_CH0_8BIT
+        bool "Channel 0 with 8-bit bus"
+        help
+          Support HSMMC Channel 0 8-bit bus.
+          If selected, Channel 1 is disabled.
+
+config S5PV310_SDHCI_CH2_8BIT
+        bool "Channel 2 with 8-bit bus"
+        help
+          Support HSMMC Channel 2 8-bit bus.
+          If selected, Channel 3 is disabled.
+
+endmenu
+
 endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index d5b51c72340f..84afc64e7c01 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -13,7 +13,7 @@ obj-				:=
 # Core support for S5PV310 system
 
 obj-$(CONFIG_CPU_S5PV310)       += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_S5PV310)       += setup-i2c0.o time.o
+obj-$(CONFIG_CPU_S5PV310)       += setup-i2c0.o time.o gpiolib.o irq-eint.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
@@ -21,6 +21,7 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 
 # machine support
 
+obj-$(CONFIG_MACH_SMDKC210)     += mach-smdkc210.o
 obj-$(CONFIG_MACH_SMDKV310)     += mach-smdkv310.o
 obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
 
@@ -28,3 +29,10 @@ obj-$(CONFIG_MACH_UNIVERSAL_C210)	+= mach-universal_c210.o
 
 obj-$(CONFIG_S5PV310_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S5PV310_SETUP_I2C2)        += setup-i2c2.o
+obj-$(CONFIG_S5PV310_SETUP_I2C3)        += setup-i2c3.o
+obj-$(CONFIG_S5PV310_SETUP_I2C4)        += setup-i2c4.o
+obj-$(CONFIG_S5PV310_SETUP_I2C5)        += setup-i2c5.o
+obj-$(CONFIG_S5PV310_SETUP_I2C6)        += setup-i2c6.o
+obj-$(CONFIG_S5PV310_SETUP_I2C7)        += setup-i2c7.o
+obj-$(CONFIG_S5PV310_SETUP_SDHCI)       += setup-sdhci.o
+obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 26a0f03df8ea..58c9d33f36fe 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,16 +30,92 @@ static struct clk clk_sclk_hdmi27m = {
         .rate           = 27000000,
 };
 
+static struct clk clk_sclk_hdmiphy = {
+        .name           = "sclk_hdmiphy",
+        .id             = -1,
+};
+
+static struct clk clk_sclk_usbphy0 = {
+        .name           = "sclk_usbphy0",
+        .id             = -1,
+        .rate           = 27000000,
+};
+
+static struct clk clk_sclk_usbphy1 = {
+        .name           = "sclk_usbphy1",
+        .id             = -1,
+};
+
+static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
+}
+
 static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 }
 
+static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
+}
+
+static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
+}
+
+static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
+}
+
 static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
 }
 
+static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk clk_mout_apll = {
@@ -79,7 +155,7 @@ static struct clksrc_clk clk_mout_mpll = {
 };
 
 static struct clk *clkset_moutcore_list[] = {
-        [0] = &clk_sclk_apll.clk,
+        [0] = &clk_mout_apll.clk,
         [1] = &clk_mout_mpll.clk,
 };
 
@@ -150,24 +226,6 @@ static struct clksrc_clk clk_periphclk = {
         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
 };
 
-static struct clksrc_clk clk_atclk = {
-        .clk    = {
-                .name           = "atclk",
-                .id             = -1,
-                .parent         = &clk_moutcore.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
-};
-
-static struct clksrc_clk clk_pclk_dbg = {
-        .clk    = {
-                .name           = "pclk_dbg",
-                .id             = -1,
-                .parent         = &clk_atclk.clk,
-        },
-        .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
-};
-
 /* Core list of CMU_CORE side */
 
 static struct clk *clkset_corebus_list[] = {
@@ -241,7 +299,7 @@ static struct clk *clkset_aclk_top_list[] = {
         [1] = &clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources clkset_aclk_200 = {
+static struct clksrc_sources clkset_aclk = {
         .sources        = clkset_aclk_top_list,
         .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
 };
@@ -251,52 +309,37 @@ static struct clksrc_clk clk_aclk_200 = {
                 .name           = "aclk_200",
                 .id             = -1,
         },
-        .sources        = &clkset_aclk_200,
+        .sources        = &clkset_aclk,
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
 };
 
-static struct clksrc_sources clkset_aclk_100 = {
-        .sources        = clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
 static struct clksrc_clk clk_aclk_100 = {
         .clk    = {
                 .name           = "aclk_100",
                 .id             = -1,
         },
-        .sources        = &clkset_aclk_100,
+        .sources        = &clkset_aclk,
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
 };
 
-static struct clksrc_sources clkset_aclk_160 = {
-        .sources        = clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
 static struct clksrc_clk clk_aclk_160 = {
         .clk    = {
                 .name           = "aclk_160",
                 .id             = -1,
         },
-        .sources        = &clkset_aclk_160,
+        .sources        = &clkset_aclk,
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
 };
 
-static struct clksrc_sources clkset_aclk_133 = {
-        .sources        = clkset_aclk_top_list,
-        .nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
-};
-
 static struct clksrc_clk clk_aclk_133 = {
         .clk    = {
                 .name           = "aclk_133",
                 .id             = -1,
         },
-        .sources        = &clkset_aclk_133,
+        .sources        = &clkset_aclk,
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
         .reg_div        = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
 };
@@ -315,6 +358,8 @@ static struct clksrc_clk clk_vpllsrc = {
         .clk    = {
                 .name           = "vpll_src",
                 .id             = -1,
+                .enable         = s5pv310_clksrc_mask_top_ctrl,
+                .ctrlbit        = (1 << 0),
         },
         .sources        = &clkset_vpllsrc,
         .reg_src        = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
@@ -346,7 +391,175 @@ static struct clk init_clocks_disable[] = {
                 .parent         = &clk_aclk_100.clk,
                 .enable         = s5pv310_clk_ip_peril_ctrl,
                 .ctrlbit        = (1<<24),
-        }
+        }, {
+                .name           = "csis",
+                .id             = 0,
+                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "csis",
+                .id             = 1,
+                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "fimc",
+                .id             = 0,
+                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "fimc",
+                .id             = 1,
+                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "fimc",
+                .id             = 2,
+                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "fimc",
+                .id             = 3,
+                .enable         = s5pv310_clk_ip_cam_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "fimd",
+                .id             = 0,
+                .enable         = s5pv310_clk_ip_lcd0_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "fimd",
+                .id             = 1,
+                .enable         = s5pv310_clk_ip_lcd1_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 5),
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "hsmmc",
+                .id             = 3,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "hsmmc",
+                .id             = 4,
+                .parent         = &clk_aclk_133.clk,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "sata",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 15),
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_perir_ctrl,
+                .ctrlbit        = (1 << 14),
+        }, {
+                .name           = "usbhost",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_fsys_ctrl ,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_fsys_ctrl,
+                .ctrlbit        = (1 << 13),
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .id             = 2,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
+                .name           = "fimg2d",
+                .id             = -1,
+                .enable         = s5pv310_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "i2c",
+                .id             = 0,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 6),
+        }, {
+                .name           = "i2c",
+                .id             = 1,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 7),
+        }, {
+                .name           = "i2c",
+                .id             = 2,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 8),
+        }, {
+                .name           = "i2c",
+                .id             = 3,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 9),
+        }, {
+                .name           = "i2c",
+                .id             = 4,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 10),
+        }, {
+                .name           = "i2c",
+                .id             = 5,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 11),
+        }, {
+                .name           = "i2c",
+                .id             = 6,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 12),
+        }, {
+                .name           = "i2c",
+                .id             = 7,
+                .parent         = &clk_aclk_100.clk,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 13),
+        },
 };
 
 static struct clk init_clocks[] = {
@@ -387,6 +600,9 @@ static struct clk *clkset_group_list[] = {
         [0] = &clk_ext_xtal_mux,
         [1] = &clk_xusbxti,
         [2] = &clk_sclk_hdmi27m,
+        [3] = &clk_sclk_usbphy0,
+        [4] = &clk_sclk_usbphy1,
+        [5] = &clk_sclk_hdmiphy,
         [6] = &clk_mout_mpll.clk,
         [7] = &clk_mout_epll.clk,
         [8] = &clk_sclk_vpll.clk,
@@ -397,6 +613,104 @@ static struct clksrc_sources clkset_group = {
         .nr_sources     = ARRAY_SIZE(clkset_group_list),
 };
 
+static struct clk *clkset_mout_g2d0_list[] = {
+        [0] = &clk_mout_mpll.clk,
+        [1] = &clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d0 = {
+        .sources        = clkset_mout_g2d0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d0_list),
+};
+
+static struct clksrc_clk clk_mout_g2d0 = {
+        .clk    = {
+                .name           = "mout_g2d0",
+                .id             = -1,
+        },
+        .sources        = &clkset_mout_g2d0,
+        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d1_list[] = {
+        [0] = &clk_mout_epll.clk,
+        [1] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d1 = {
+        .sources        = clkset_mout_g2d1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d1_list),
+};
+
+static struct clksrc_clk clk_mout_g2d1 = {
+        .clk    = {
+                .name           = "mout_g2d1",
+                .id             = -1,
+        },
+        .sources        = &clkset_mout_g2d1,
+        .reg_src        = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_mout_g2d_list[] = {
+        [0] = &clk_mout_g2d0.clk,
+        [1] = &clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources clkset_mout_g2d = {
+        .sources        = clkset_mout_g2d_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mout_g2d_list),
+};
+
+static struct clksrc_clk clk_dout_mmc0 = {
+        .clk            = {
+                .name           = "dout_mmc0",
+                .id             = -1,
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc1 = {
+        .clk            = {
+                .name           = "dout_mmc1",
+                .id             = -1,
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc2 = {
+        .clk            = {
+                .name           = "dout_mmc2",
+                .id             = -1,
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc3 = {
+        .clk            = {
+                .name           = "dout_mmc3",
+                .id             = -1,
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_dout_mmc4 = {
+        .clk            = {
+                .name           = "dout_mmc4",
+                .id             = -1,
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
 static struct clksrc_clk clksrcs[] = {
         {
                 .clk    = {
@@ -448,7 +762,200 @@ static struct clksrc_clk clksrcs[] = {
                 .sources = &clkset_group,
                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
                 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
-        },
+        }, {
+                .clk            = {
+                        .name           = "sclk_csis",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_csis",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 28),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_cam",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_cam",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 4),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 2,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 8),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 3,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimd",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_lcd0_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimd",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_lcd1_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_sata",
+                        .id             = -1,
+                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_mout_corebus,
+                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 2,
+                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimg2d",
+                        .id             = -1,
+                },
+                .sources = &clkset_mout_g2d,
+                .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+                .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 0,
+                        .parent         = &clk_dout_mmc0.clk,
+                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 1,
+                        .parent         = &clk_dout_mmc1.clk,
+                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 4),
+                },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 2,
+                        .parent         = &clk_dout_mmc2.clk,
+                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 8),
+                },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 3,
+                        .parent         = &clk_dout_mmc3.clk,
+                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_mmc",
+                        .id             = 4,
+                        .parent         = &clk_dout_mmc4.clk,
+                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+        }
 };
 
 /* Clock initialization code */
@@ -464,8 +971,6 @@ static struct clksrc_clk *sysclks[] = {
         &clk_aclk_cores,
         &clk_aclk_corem1,
         &clk_periphclk,
-        &clk_atclk,
-        &clk_pclk_dbg,
         &clk_mout_corebus,
         &clk_sclk_dmc,
         &clk_aclk_cored,
@@ -478,6 +983,11 @@ static struct clksrc_clk *sysclks[] = {
         &clk_aclk_100,
         &clk_aclk_160,
         &clk_aclk_133,
+        &clk_dout_mmc0,
+        &clk_dout_mmc1,
+        &clk_dout_mmc2,
+        &clk_dout_mmc3,
+        &clk_dout_mmc4,
 };
 
 void __init_or_cpufreq s5pv310_setup_clocks(void)
@@ -490,15 +1000,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
         unsigned long vpllsrc;
         unsigned long xtal;
         unsigned long armclk;
-        unsigned long aclk_corem0;
-        unsigned long aclk_cores;
-        unsigned long aclk_corem1;
-        unsigned long periphclk;
         unsigned long sclk_dmc;
-        unsigned long aclk_cored;
-        unsigned long aclk_corep;
-        unsigned long aclk_acp;
-        unsigned long pclk_acp;
+        unsigned long aclk_200;
+        unsigned long aclk_100;
+        unsigned long aclk_160;
+        unsigned long aclk_133;
         unsigned int ptr;
 
         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
@@ -529,26 +1035,21 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
                         apll, mpll, epll, vpll);
 
         armclk = clk_get_rate(&clk_armclk.clk);
-        aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
-        aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
-        aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
-        periphclk = clk_get_rate(&clk_periphclk.clk);
         sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
-        aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
-        aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
-        aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
-        pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
-
-        printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
-                         "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
-                         "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
-                        armclk, aclk_corem0, aclk_cores, aclk_corem1,
-                        periphclk, sclk_dmc, aclk_cored, aclk_corep,
-                        aclk_acp, pclk_acp);
+
+        aclk_200 = clk_get_rate(&clk_aclk_200.clk);
+        aclk_100 = clk_get_rate(&clk_aclk_100.clk);
+        aclk_160 = clk_get_rate(&clk_aclk_160.clk);
+        aclk_133 = clk_get_rate(&clk_aclk_133.clk);
+
+        printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+                         "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+                        armclk, sclk_dmc, aclk_200,
+                        aclk_100, aclk_160, aclk_133);
 
         clk_f.rate = armclk;
         clk_h.rate = sclk_dmc;
-        clk_p.rate = periphclk;
+        clk_p.rate = aclk_100;
 
         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
                 s3c_set_clksrc(&clksrcs[ptr], true);
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 4add39853ff9..82ce4aa6d61a 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -15,10 +15,12 @@
 #include <asm/mach/irq.h>
 
 #include <asm/proc-fns.h>
+#include <asm/hardware/cache-l2x0.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
 #include <plat/s5pv310.h>
+#include <plat/sdhci.h>
 
 #include <mach/regs-irq.h>
 
@@ -56,15 +58,30 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .virtual        = (unsigned long)S5P_VA_GPIO1,
                 .pfn            = __phys_to_pfn(S5PV310_PA_GPIO1),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO2,
+                .pfn            = __phys_to_pfn(S5PV310_PA_GPIO2),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO3,
+                .pfn            = __phys_to_pfn(S5PV310_PA_GPIO3),
+                .length         = SZ_256,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = (unsigned long)S3C_VA_UART,
                 .pfn            = __phys_to_pfn(S3C_PA_UART),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(S5PV310_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
         },
 };
 
@@ -83,6 +100,12 @@ static void s5pv310_idle(void)
 void __init s5pv310_map_io(void)
 {
         iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
+
+        /* initialize device information early */
+        s5pv310_default_sdhci0();
+        s5pv310_default_sdhci1();
+        s5pv310_default_sdhci2();
+        s5pv310_default_sdhci3();
 }
 
 void __init s5pv310_init_clocks(int xtal)
@@ -131,6 +154,28 @@ static int __init s5pv310_core_init(void)
 
 core_initcall(s5pv310_core_init);
 
+#ifdef CONFIG_CACHE_L2X0
+static int __init s5pv310_l2x0_cache_init(void)
+{
+        /* TAG, Data Latency Control: 2cycle */
+        __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+        __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+
+        /* L2X0 Prefetch Control */
+        __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+
+        /* L2X0 Power Control */
+        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+                     S5P_VA_L2CC + L2X0_POWER_CTRL);
+
+        l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+
+        return 0;
+}
+
+early_initcall(s5pv310_l2x0_cache_init);
+#endif
+
 int __init s5pv310_init(void)
 {
         printk(KERN_INFO "S5PV310: Initializing architecture\n");
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-s5pv310/gpiolib.c
new file mode 100644
index 000000000000..55217b8923ec
--- /dev/null
+++ b/arch/arm/mach-s5pv310/gpiolib.c
@@ -0,0 +1,304 @@
+/* linux/arch/arm/mach-s5pv310/gpiolib.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+
+static struct s3c_gpio_cfg gpio_cfg = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+
+/*
+ * Following are the gpio banks in v310.
+ *
+ * The 'config' member when left to NULL, is initialized to the default
+ * structure gpio_cfg in the init function below.
+ *
+ * The 'base' member is also initialized in the init function below.
+ * Note: The initialization of 'base' member of s3c_gpio_chip structure
+ * uses the above macro and depends on the banks being listed in order here.
+ */
+static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
+        {
+                .chip   = {
+                        .base   = S5PV310_GPA0(0),
+                        .ngpio  = S5PV310_GPIO_A0_NR,
+                        .label  = "GPA0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPA1(0),
+                        .ngpio  = S5PV310_GPIO_A1_NR,
+                        .label  = "GPA1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPB(0),
+                        .ngpio  = S5PV310_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPC0(0),
+                        .ngpio  = S5PV310_GPIO_C0_NR,
+                        .label  = "GPC0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPC1(0),
+                        .ngpio  = S5PV310_GPIO_C1_NR,
+                        .label  = "GPC1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPD0(0),
+                        .ngpio  = S5PV310_GPIO_D0_NR,
+                        .label  = "GPD0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPD1(0),
+                        .ngpio  = S5PV310_GPIO_D1_NR,
+                        .label  = "GPD1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPE0(0),
+                        .ngpio  = S5PV310_GPIO_E0_NR,
+                        .label  = "GPE0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPE1(0),
+                        .ngpio  = S5PV310_GPIO_E1_NR,
+                        .label  = "GPE1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPE2(0),
+                        .ngpio  = S5PV310_GPIO_E2_NR,
+                        .label  = "GPE2",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPE3(0),
+                        .ngpio  = S5PV310_GPIO_E3_NR,
+                        .label  = "GPE3",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPE4(0),
+                        .ngpio  = S5PV310_GPIO_E4_NR,
+                        .label  = "GPE4",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPF0(0),
+                        .ngpio  = S5PV310_GPIO_F0_NR,
+                        .label  = "GPF0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPF1(0),
+                        .ngpio  = S5PV310_GPIO_F1_NR,
+                        .label  = "GPF1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPF2(0),
+                        .ngpio  = S5PV310_GPIO_F2_NR,
+                        .label  = "GPF2",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPF3(0),
+                        .ngpio  = S5PV310_GPIO_F3_NR,
+                        .label  = "GPF3",
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
+        {
+                .chip   = {
+                        .base   = S5PV310_GPJ0(0),
+                        .ngpio  = S5PV310_GPIO_J0_NR,
+                        .label  = "GPJ0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPJ1(0),
+                        .ngpio  = S5PV310_GPIO_J1_NR,
+                        .label  = "GPJ1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPK0(0),
+                        .ngpio  = S5PV310_GPIO_K0_NR,
+                        .label  = "GPK0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPK1(0),
+                        .ngpio  = S5PV310_GPIO_K1_NR,
+                        .label  = "GPK1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPK2(0),
+                        .ngpio  = S5PV310_GPIO_K2_NR,
+                        .label  = "GPK2",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPK3(0),
+                        .ngpio  = S5PV310_GPIO_K3_NR,
+                        .label  = "GPK3",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPL0(0),
+                        .ngpio  = S5PV310_GPIO_L0_NR,
+                        .label  = "GPL0",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPL1(0),
+                        .ngpio  = S5PV310_GPIO_L1_NR,
+                        .label  = "GPL1",
+                },
+        }, {
+                .chip   = {
+                        .base   = S5PV310_GPL2(0),
+                        .ngpio  = S5PV310_GPIO_L2_NR,
+                        .label  = "GPL2",
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC00),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(0),
+                .chip   = {
+                        .base   = S5PV310_GPX0(0),
+                        .ngpio  = S5PV310_GPIO_X0_NR,
+                        .label  = "GPX0",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC20),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(8),
+                .chip   = {
+                        .base   = S5PV310_GPX1(0),
+                        .ngpio  = S5PV310_GPIO_X1_NR,
+                        .label  = "GPX1",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC40),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(16),
+                .chip   = {
+                        .base   = S5PV310_GPX2(0),
+                        .ngpio  = S5PV310_GPIO_X2_NR,
+                        .label  = "GPX2",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        }, {
+                .base   = (S5P_VA_GPIO2 + 0xC60),
+                .config = &gpio_cfg_noint,
+                .irq_base = IRQ_EINT(24),
+                .chip   = {
+                        .base   = S5PV310_GPX3(0),
+                        .ngpio  = S5PV310_GPIO_X3_NR,
+                        .label  = "GPX3",
+                        .to_irq = samsung_gpiolib_to_irq,
+                },
+        },
+};
+
+static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
+        {
+                .chip   = {
+                        .base   = S5PV310_GPZ(0),
+                        .ngpio  = S5PV310_GPIO_Z_NR,
+                        .label  = "GPZ",
+                },
+        },
+};
+
+static __init int s5pv310_gpiolib_init(void)
+{
+        struct s3c_gpio_chip *chip;
+        int i;
+        int nr_chips;
+
+        /* GPIO part 1 */
+
+        chip = s5pv310_gpio_part1_4bit;
+        nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
+
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL)
+                        chip->config = &gpio_cfg;
+                if (chip->base == NULL)
+                        chip->base = S5P_VA_GPIO1 + (i) * 0x20;
+        }
+
+        samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
+
+        /* GPIO part 2 */
+
+        chip = s5pv310_gpio_part2_4bit;
+        nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
+
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL)
+                        chip->config = &gpio_cfg;
+                if (chip->base == NULL)
+                        chip->base = S5P_VA_GPIO2 + (i) * 0x20;
+        }
+
+        samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
+
+        /* GPIO part 3 */
+
+        chip = s5pv310_gpio_part3_4bit;
+        nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
+
+        for (i = 0; i < nr_chips; i++, chip++) {
+                if (chip->config == NULL)
+                        chip->config = &gpio_cfg;
+                if (chip->base == NULL)
+                        chip->base = S5P_VA_GPIO3 + (i) * 0x20;
+        }
+
+        samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
+
+        return 0;
+}
+core_initcall(s5pv310_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c
new file mode 100644
index 000000000000..03652c3605f6
--- /dev/null
+++ b/arch/arm/mach-s5pv310/hotplug.c
@@ -0,0 +1,144 @@
+/* linux arch/arm/mach-s5pv310/hotplug.c
+ *
+ *  Cloned from linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+#include <asm/cacheflush.h>
+
+extern volatile int pen_release;
+
+static DECLARE_COMPLETION(cpu_killed);
+
+static inline void cpu_enter_lowpower(void)
+{
+        unsigned int v;
+
+        flush_cache_all();
+        asm volatile(
+        "       mcr     p15, 0, %1, c7, c5, 0\n"
+        "       mcr     p15, 0, %1, c7, c10, 4\n"
+        /*
+         * Turn off coherency
+         */
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, #0x04\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+          : "=&r" (v)
+          : "r" (0)
+          : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile(
+        "mrc    p15, 0, %0, c1, c0, 0\n"
+        "       orr     %0, %0, #0x04\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       orr     %0, %0, #0x20\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+          : "=&r" (v)
+          :
+          : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+        /*
+         * there is no power-control hardware on this platform, so all
+         * we can do is put the core into WFI; this is safe as the calling
+         * code will have already disabled interrupts
+         */
+        for (;;) {
+                /*
+                 * here's the WFI
+                 */
+                asm(".word      0xe320f003\n"
+                    :
+                    :
+                    : "memory", "cc");
+
+                if (pen_release == cpu) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+
+                /*
+                 * getting here, means that we have come out of WFI without
+                 * having been woken up - this shouldn't happen
+                 *
+                 * The trouble is, letting people know about this is not really
+                 * possible, since we are currently running incoherently, and
+                 * therefore cannot safely call printk() or anything else
+                 */
+#ifdef DEBUG
+                printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
+#endif
+        }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+#ifdef DEBUG
+        unsigned int this_cpu = hard_smp_processor_id();
+
+        if (cpu != this_cpu) {
+                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
+                           this_cpu, cpu);
+                BUG();
+        }
+#endif
+
+        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+        complete(&cpu_killed);
+
+        /*
+         * we're ready for shutdown now, so do it
+         */
+        cpu_enter_lowpower();
+        platform_do_lowpower(cpu);
+
+        /*
+         * bring this CPU back into the world of cache
+         * coherency, and then restore interrupts
+         */
+        cpu_leave_lowpower();
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 471fc3bb199a..99e7dad8a85a 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -3,7 +3,7 @@
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
- * S5PV210 - IRQ definitions
+ * S5PV310 - IRQ definitions
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -60,6 +60,9 @@
 #define IRQ_TIMER3_VIC          COMBINER_IRQ(22, 3)
 #define IRQ_TIMER4_VIC          COMBINER_IRQ(22, 4)
 
+#define IRQ_RTC_ALARM           COMBINER_IRQ(23, 0)
+#define IRQ_RTC_TIC             COMBINER_IRQ(23, 1)
+
 #define IRQ_UART0               COMBINER_IRQ(26, 0)
 #define IRQ_UART1               COMBINER_IRQ(26, 1)
 #define IRQ_UART2               COMBINER_IRQ(26, 2)
@@ -67,13 +70,46 @@
 #define IRQ_UART4               COMBINER_IRQ(26, 4)
 
 #define IRQ_IIC                 COMBINER_IRQ(27, 0)
+#define IRQ_IIC1                COMBINER_IRQ(27, 1)
+#define IRQ_IIC2                COMBINER_IRQ(27, 2)
+#define IRQ_IIC3                COMBINER_IRQ(27, 3)
+#define IRQ_IIC4                COMBINER_IRQ(27, 4)
+#define IRQ_IIC5                COMBINER_IRQ(27, 5)
+#define IRQ_IIC6                COMBINER_IRQ(27, 6)
+#define IRQ_IIC7                COMBINER_IRQ(27, 7)
+
+#define IRQ_HSMMC0              COMBINER_IRQ(29, 0)
+#define IRQ_HSMMC1              COMBINER_IRQ(29, 1)
+#define IRQ_HSMMC2              COMBINER_IRQ(29, 2)
+#define IRQ_HSMMC3              COMBINER_IRQ(29, 3)
 
 #define IRQ_ONENAND_AUDI        COMBINER_IRQ(34, 0)
 
-/* Set the default NR_IRQS */
+#define IRQ_EINT4               COMBINER_IRQ(37, 0)
+#define IRQ_EINT5               COMBINER_IRQ(37, 1)
+#define IRQ_EINT6               COMBINER_IRQ(37, 2)
+#define IRQ_EINT7               COMBINER_IRQ(37, 3)
+#define IRQ_EINT8               COMBINER_IRQ(38, 0)
+
+#define IRQ_EINT9               COMBINER_IRQ(38, 1)
+#define IRQ_EINT10              COMBINER_IRQ(38, 2)
+#define IRQ_EINT11              COMBINER_IRQ(38, 3)
+#define IRQ_EINT12              COMBINER_IRQ(38, 4)
+#define IRQ_EINT13              COMBINER_IRQ(38, 5)
+#define IRQ_EINT14              COMBINER_IRQ(38, 6)
+#define IRQ_EINT15              COMBINER_IRQ(38, 7)
+
+#define IRQ_EINT16_31           COMBINER_IRQ(39, 0)
 
-#define NR_IRQS                 COMBINER_IRQ(MAX_COMBINER_NR, 0)
+#define MAX_COMBINER_NR         40
+
+#define S5P_IRQ_EINT_BASE       COMBINER_IRQ(MAX_COMBINER_NR, 0)
+
+#define S5P_EINT_BASE1          (S5P_IRQ_EINT_BASE + 0)
+#define S5P_EINT_BASE2          (S5P_IRQ_EINT_BASE + 16)
+
+/* Set the default NR_IRQS */
 
-#define MAX_COMBINER_NR         39
+#define NR_IRQS                 (S5P_IRQ_EINT_BASE + 32)
 
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index aff6d23624bb..7acf4e77e92e 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -25,6 +25,8 @@
 
 #define S5PV310_PA_SYSRAM               (0x02025000)
 
+#define S5PV310_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
+
 #define S5PC210_PA_ONENAND              (0x0C000000)
 #define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
 
@@ -34,12 +36,13 @@
 #define S5PV310_PA_CHIPID               (0x10000000)
 #define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
 
-#define S5PV310_PA_SYSCON               (0x10020000)
+#define S5PV310_PA_SYSCON               (0x10010000)
 #define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
 
 #define S5PV310_PA_CMU                  (0x10030000)
 
 #define S5PV310_PA_WATCHDOG             (0x10060000)
+#define S5PV310_PA_RTC                  (0x10070000)
 
 #define S5PV310_PA_COMBINER             (0x10448000)
 
@@ -55,6 +58,8 @@
 
 #define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 
+#define S5PV310_PA_SROMC                (0x12570000)
+
 #define S5PV310_PA_UART                 (0x13800000)
 
 #define S5P_PA_UART(x)                  (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
@@ -66,7 +71,7 @@
 
 #define S5P_SZ_UART                     SZ_256
 
-#define S5PV310_PA_IIC0                 (0x13860000)
+#define S5PV310_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
 
 #define S5PV310_PA_TIMER                (0x139D0000)
 #define S5P_PA_TIMER                    S5PV310_PA_TIMER
@@ -80,7 +85,15 @@
 #define S3C_PA_HSMMC1                   S5PV310_PA_HSMMC(1)
 #define S3C_PA_HSMMC2                   S5PV310_PA_HSMMC(2)
 #define S3C_PA_HSMMC3                   S5PV310_PA_HSMMC(3)
-#define S3C_PA_IIC                      S5PV310_PA_IIC0
+#define S3C_PA_IIC                      S5PV310_PA_IIC(0)
+#define S3C_PA_IIC1                     S5PV310_PA_IIC(1)
+#define S3C_PA_IIC2                     S5PV310_PA_IIC(2)
+#define S3C_PA_IIC3                     S5PV310_PA_IIC(3)
+#define S3C_PA_IIC4                     S5PV310_PA_IIC(4)
+#define S3C_PA_IIC5                     S5PV310_PA_IIC(5)
+#define S3C_PA_IIC6                     S5PV310_PA_IIC(6)
+#define S3C_PA_IIC7                     S5PV310_PA_IIC(7)
+#define S3C_PA_RTC                      S5PV310_PA_RTC
 #define S3C_PA_WDT                      S5PV310_PA_WATCHDOG
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 4013553cd9be..f1028cad9788 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -26,11 +26,23 @@
 
 #define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
 #define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
-
+#define S5P_CLKSRC_CAM                  S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_IMAGE                S5P_CLKREG(0x0C230)
+#define S5P_CLKSRC_LCD0                 S5P_CLKREG(0x0C234)
+#define S5P_CLKSRC_LCD1                 S5P_CLKREG(0x0C238)
+#define S5P_CLKSRC_FSYS                 S5P_CLKREG(0x0C240)
 #define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
+#define S5P_CLKSRC_PERIL1               S5P_CLKREG(0x0C254)
 
 #define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
-
+#define S5P_CLKDIV_CAM                  S5P_CLKREG(0x0C520)
+#define S5P_CLKDIV_IMAGE                S5P_CLKREG(0x0C530)
+#define S5P_CLKDIV_LCD0                 S5P_CLKREG(0x0C534)
+#define S5P_CLKDIV_LCD1                 S5P_CLKREG(0x0C538)
+#define S5P_CLKDIV_FSYS0                S5P_CLKREG(0x0C540)
+#define S5P_CLKDIV_FSYS1                S5P_CLKREG(0x0C544)
+#define S5P_CLKDIV_FSYS2                S5P_CLKREG(0x0C548)
+#define S5P_CLKDIV_FSYS3                S5P_CLKREG(0x0C54C)
 #define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x0C550)
 #define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x0C554)
 #define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x0C558)
@@ -38,9 +50,21 @@
 #define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
 #define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
 
+#define S5P_CLKSRC_MASK_TOP             S5P_CLKREG(0x0C310)
+#define S5P_CLKSRC_MASK_CAM             S5P_CLKREG(0x0C320)
+#define S5P_CLKSRC_MASK_LCD0            S5P_CLKREG(0x0C334)
+#define S5P_CLKSRC_MASK_LCD1            S5P_CLKREG(0x0C338)
+#define S5P_CLKSRC_MASK_FSYS            S5P_CLKREG(0x0C340)
 #define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
+#define S5P_CLKSRC_MASK_PERIL1          S5P_CLKREG(0x0C354)
 
+#define S5P_CLKGATE_IP_CAM              S5P_CLKREG(0x0C920)
+#define S5P_CLKGATE_IP_IMAGE            S5P_CLKREG(0x0C930)
+#define S5P_CLKGATE_IP_LCD0             S5P_CLKREG(0x0C934)
+#define S5P_CLKGATE_IP_LCD1             S5P_CLKREG(0x0C938)
+#define S5P_CLKGATE_IP_FSYS             S5P_CLKREG(0x0C940)
 #define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
+#define S5P_CLKGATE_IP_PERIR            S5P_CLKREG(0x0C960)
 
 #define S5P_CLKSRC_CORE                 S5P_CLKREG(0x10200)
 #define S5P_CLKDIV_CORE0                S5P_CLKREG(0x10500)
@@ -60,4 +84,8 @@
 
 #define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
 
+/* Compatibility defines */
+
+#define S5P_EPLL_CON                    S5P_EPLL_CON0
+
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..82e9e0c9d452
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - GPIO (including EINT) register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H __FILE__
+
+#include <mach/map.h>
+#include <mach/irqs.h>
+
+#define S5PV310_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
+#define S5P_EINT_CON(x)                 (S5PV310_EINT40CON + ((x) * 0x4))
+
+#define S5PV310_EINT40FLTCON0           (S5P_VA_GPIO2 + 0xE80)
+#define S5P_EINT_FLTCON(x)              (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
+
+#define S5PV310_EINT40MASK              (S5P_VA_GPIO2 + 0xF00)
+#define S5P_EINT_MASK(x)                (S5PV310_EINT40MASK + ((x) * 0x4))
+
+#define S5PV310_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
+#define S5P_EINT_PEND(x)                (S5PV310_EINT40PEND + ((x) * 0x4))
+
+#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
+
+#define eint_irq_to_bit(irq)            (1 << (EINT_OFFSET(irq) & 0x7))
+
+#define EINT_MODE                       S3C_GPIO_SFN(0xf)
+
+#define EINT_GPIO_0(x)                  S5PV310_GPX0(x)
+#define EINT_GPIO_1(x)                  S5PV310_GPX1(x)
+#define EINT_GPIO_2(x)                  S5PV310_GPX2(x)
+#define EINT_GPIO_3(x)                  S5PV310_GPX3(x)
+
+#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
new file mode 100644
index 000000000000..1898b3e10550
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-srom.h
@@ -0,0 +1,50 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - SROMC register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_SROM_H
+#define __ASM_ARCH_REGS_SROM_H __FILE__
+
+#include <mach/map.h>
+
+#define S5PV310_SROMREG(x)      (S5P_VA_SROMC + (x))
+
+#define S5PV310_SROM_BW         S5PV310_SROMREG(0x0)
+#define S5PV310_SROM_BC0        S5PV310_SROMREG(0x4)
+#define S5PV310_SROM_BC1        S5PV310_SROMREG(0x8)
+#define S5PV310_SROM_BC2        S5PV310_SROMREG(0xc)
+#define S5PV310_SROM_BC3        S5PV310_SROMREG(0x10)
+
+/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
+
+#define S5PV310_SROM_BW__DATAWIDTH__SHIFT       0
+#define S5PV310_SROM_BW__ADDRMODE__SHIFT        1
+#define S5PV310_SROM_BW__WAITENABLE__SHIFT      2
+#define S5PV310_SROM_BW__BYTEENABLE__SHIFT      3
+
+#define S5PV310_SROM_BW__CS_MASK                0xf
+
+#define S5PV310_SROM_BW__NCS0__SHIFT            0
+#define S5PV310_SROM_BW__NCS1__SHIFT            4
+#define S5PV310_SROM_BW__NCS2__SHIFT            8
+#define S5PV310_SROM_BW__NCS3__SHIFT            12
+
+/* applies to same to BCS0 - BCS3 */
+
+#define S5PV310_SROM_BCX__PMC__SHIFT            0
+#define S5PV310_SROM_BCX__TACP__SHIFT           4
+#define S5PV310_SROM_BCX__TCAH__SHIFT           8
+#define S5PV310_SROM_BCX__TCOH__SHIFT           12
+#define S5PV310_SROM_BCX__TACC__SHIFT           16
+#define S5PV310_SROM_BCX__TCOS__SHIFT           24
+#define S5PV310_SROM_BCX__TACS__SHIFT           28
+
+#endif /* __ASM_ARCH_REGS_SROM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
index 256f221edf3a..65759fb97581 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H __FILE__
 
-#define VMALLOC_END     (0xF0000000UL)
+#define VMALLOC_END     0xF6000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index 0f7052164f23..c3f88c3faf6c 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -66,11 +66,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
         if (status == 0)
                 goto out;
 
-        for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) {
-                if (status & 0x1)
-                        break;
-                status >>= 1;
-        }
+        combiner_irq = __ffs(status);
 
         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
         if (unlikely(cascade_irq >= NR_IRQS))
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
new file mode 100644
index 000000000000..5877503e92c3
--- /dev/null
+++ b/arch/arm/mach-s5pv310/irq-eint.c
@@ -0,0 +1,228 @@
+/* linux/arch/arm/mach-s5pv310/irq-eint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5PV310 - IRQ EINT support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/gpio.h>
+
+#include <plat/pm.h>
+#include <plat/cpu.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+
+static DEFINE_SPINLOCK(eint_lock);
+
+static unsigned int eint0_15_data[16];
+
+static unsigned int s5pv310_get_irq_nr(unsigned int number)
+{
+        u32 ret = 0;
+
+        switch (number) {
+        case 0 ... 3:
+                ret = (number + IRQ_EINT0);
+                break;
+        case 4 ... 7:
+                ret = (number + (IRQ_EINT4 - 4));
+                break;
+        case 8 ... 15:
+                ret = (number + (IRQ_EINT8 - 8));
+                break;
+        default:
+                printk(KERN_ERR "number available : %d\n", number);
+        }
+
+        return ret;
+}
+
+static inline void s5pv310_irq_eint_mask(unsigned int irq)
+{
+        u32 mask;
+
+        spin_lock(&eint_lock);
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask |= eint_irq_to_bit(irq);
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+        spin_unlock(&eint_lock);
+}
+
+static void s5pv310_irq_eint_unmask(unsigned int irq)
+{
+        u32 mask;
+
+        spin_lock(&eint_lock);
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq)));
+        mask &= ~(eint_irq_to_bit(irq));
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq)));
+        spin_unlock(&eint_lock);
+}
+
+static inline void s5pv310_irq_eint_ack(unsigned int irq)
+{
+        __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq)));
+}
+
+static void s5pv310_irq_eint_maskack(unsigned int irq)
+{
+        s5pv310_irq_eint_mask(irq);
+        s5pv310_irq_eint_ack(irq);
+}
+
+static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
+{
+        int offs = EINT_OFFSET(irq);
+        int shift;
+        u32 ctrl, mask;
+        u32 newvalue = 0;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+                break;
+
+        case IRQ_TYPE_EDGE_FALLING:
+                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+                break;
+
+        case IRQ_TYPE_EDGE_BOTH:
+                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+                break;
+
+        case IRQ_TYPE_LEVEL_LOW:
+                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+                break;
+
+        case IRQ_TYPE_LEVEL_HIGH:
+                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+                break;
+
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+
+        shift = (offs & 0x7) * 4;
+        mask = 0x7 << shift;
+
+        spin_lock(&eint_lock);
+        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq)));
+        ctrl &= ~mask;
+        ctrl |= newvalue << shift;
+        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq)));
+        spin_unlock(&eint_lock);
+
+        switch (offs) {
+        case 0 ... 7:
+                s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+                break;
+        case 8 ... 15:
+                s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+                break;
+        case 16 ... 23:
+                s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+                break;
+        case 24 ... 31:
+                s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+                break;
+        default:
+                printk(KERN_ERR "No such irq number %d", offs);
+        }
+
+        return 0;
+}
+
+static struct irq_chip s5pv310_irq_eint = {
+        .name           = "s5pv310-eint",
+        .mask           = s5pv310_irq_eint_mask,
+        .unmask         = s5pv310_irq_eint_unmask,
+        .mask_ack       = s5pv310_irq_eint_maskack,
+        .ack            = s5pv310_irq_eint_ack,
+        .set_type       = s5pv310_irq_eint_set_type,
+#ifdef CONFIG_PM
+        .set_wake       = s3c_irqext_wake,
+#endif
+};
+
+/* s5pv310_irq_demux_eint
+ *
+ * This function demuxes the IRQ from from EINTs 16 to 31.
+ * It is designed to be inlined into the specific handler
+ * s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline void s5pv310_irq_demux_eint(unsigned int start)
+{
+        unsigned int irq;
+
+        u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+        u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+
+        status &= ~mask;
+        status &= 0xff;
+
+        while (status) {
+                irq = fls(status) - 1;
+                generic_handle_irq(irq + start);
+                status &= ~(1 << irq);
+        }
+}
+
+static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+        s5pv310_irq_demux_eint(IRQ_EINT(16));
+        s5pv310_irq_demux_eint(IRQ_EINT(24));
+}
+
+static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+        u32 *irq_data = get_irq_data(irq);
+        struct irq_chip *chip = get_irq_chip(irq);
+
+        chip->mask(irq);
+
+        if (chip->ack)
+                chip->ack(irq);
+
+        generic_handle_irq(*irq_data);
+
+        chip->unmask(irq);
+}
+
+int __init s5pv310_init_irq_eint(void)
+{
+        int irq;
+
+        for (irq = 0 ; irq <= 31 ; irq++) {
+                set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
+                set_irq_handler(IRQ_EINT(irq), handle_level_irq);
+                set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+        }
+
+        set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
+
+        for (irq = 0 ; irq <= 15 ; irq++) {
+                eint0_15_data[irq] = IRQ_EINT(irq);
+
+                set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
+                set_irq_chained_handler(s5pv310_get_irq_nr(irq),
+                                        s5pv310_irq_eint0_15);
+        }
+
+        return 0;
+}
+
+arch_initcall(s5pv310_init_irq_eint);
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c
new file mode 100644
index 000000000000..2b8d4fc52d7c
--- /dev/null
+++ b/arch/arm/mach-s5pv310/mach-smdkc210.c
@@ -0,0 +1,202 @@
+/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/regs-serial.h>
+#include <plat/s5pv310.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+
+#include <mach/map.h>
+#include <mach/regs-srom.h>
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKC210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
+                                 S3C2410_UCON_RXILEVEL |        \
+                                 S3C2410_UCON_TXIRQMODE |       \
+                                 S3C2410_UCON_RXIRQMODE |       \
+                                 S3C2410_UCON_RXFIFO_TOI |      \
+                                 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKC210_ULCON_DEFAULT  S3C2410_LCON_CS8
+
+#define SMDKC210_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
+                                 S5PV210_UFCON_TXTRIG4 |        \
+                                 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport         = 0,
+                .flags          = 0,
+                .ucon           = SMDKC210_UCON_DEFAULT,
+                .ulcon          = SMDKC210_ULCON_DEFAULT,
+                .ufcon          = SMDKC210_UFCON_DEFAULT,
+        },
+        [1] = {
+                .hwport         = 1,
+                .flags          = 0,
+                .ucon           = SMDKC210_UCON_DEFAULT,
+                .ulcon          = SMDKC210_ULCON_DEFAULT,
+                .ufcon          = SMDKC210_UFCON_DEFAULT,
+        },
+        [2] = {
+                .hwport         = 2,
+                .flags          = 0,
+                .ucon           = SMDKC210_UCON_DEFAULT,
+                .ulcon          = SMDKC210_ULCON_DEFAULT,
+                .ufcon          = SMDKC210_UFCON_DEFAULT,
+        },
+        [3] = {
+                .hwport         = 3,
+                .flags          = 0,
+                .ucon           = SMDKC210_UCON_DEFAULT,
+                .ulcon          = SMDKC210_ULCON_DEFAULT,
+                .ufcon          = SMDKC210_UFCON_DEFAULT,
+        },
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+        .max_width              = 8,
+        .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+        .max_width              = 8,
+        .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct resource smdkc210_smsc911x_resources[] = {
+        [0] = {
+                .start  = S5PV310_PA_SROM_BANK(1),
+                .end    = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_EINT(5),
+                .end    = IRQ_EINT(5),
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+        },
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdkc210_smsc911x = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smdkc210_smsc911x_resources),
+        .resource       = smdkc210_smsc911x_resources,
+        .dev            = {
+                .platform_data  = &smsc9215_config,
+        },
+};
+
+static struct platform_device *smdkc210_devices[] __initdata = {
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &smdkc210_smsc911x,
+};
+
+static void __init smdkc210_smsc911x_init(void)
+{
+        u32 cs1;
+
+        /* configure nCS1 width to 16 bits */
+        cs1 = __raw_readl(S5PV310_SROM_BW) &
+                    ~(S5PV310_SROM_BW__CS_MASK <<
+                                    S5PV310_SROM_BW__NCS1__SHIFT);
+        cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
+                (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
+                (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
+                S5PV310_SROM_BW__NCS1__SHIFT;
+        __raw_writel(cs1, S5PV310_SROM_BW);
+
+        /* set timing for nCS1 suitable for ethernet chip */
+        __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
+                     (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
+                     (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
+                     (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
+                     (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
+                     (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
+                     (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+}
+
+static void __init smdkc210_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
+}
+
+static void __init smdkc210_machine_init(void)
+{
+        smdkc210_smsc911x_init();
+
+        s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
+        s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
+
+        platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
+}
+
+MACHINE_START(SMDKC210, "SMDKC210")
+        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .boot_params    = S5P_PA_SDRAM + 0x100,
+        .init_irq       = s5pv310_init_irq,
+        .map_io         = smdkc210_map_io,
+        .init_machine   = smdkc210_machine_init,
+        .timer          = &s5pv310_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 46215a14b3bb..35826d66632c 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -9,16 +9,23 @@
 */
 
 #include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/io.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-#include <asm/hardware/cache-l2x0.h>
 
 #include <plat/regs-serial.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
 
 #include <mach/map.h>
+#include <mach/regs-srom.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -65,6 +72,107 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
         },
 };
 
+static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
+        .max_width              = 8,
+        .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK0(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
+        .max_width              = 8,
+        .host_caps              = MMC_CAP_8_BIT_DATA,
+#endif
+};
+
+static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
+        .cd_type                = S3C_SDHCI_CD_GPIO,
+        .ext_cd_gpio            = S5PV310_GPK2(2),
+        .ext_cd_gpio_invert     = 1,
+        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
+};
+
+static struct resource smdkv310_smsc911x_resources[] = {
+        [0] = {
+                .start  = S5PV310_PA_SROM_BANK(1),
+                .end    = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_EINT(5),
+                .end    = IRQ_EINT(5),
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+        },
+};
+
+static struct smsc911x_platform_config smsc9215_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
+};
+
+static struct platform_device smdkv310_smsc911x = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smdkv310_smsc911x_resources),
+        .resource       = smdkv310_smsc911x_resources,
+        .dev            = {
+                .platform_data  = &smsc9215_config,
+        },
+};
+
+static struct platform_device *smdkv310_devices[] __initdata = {
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+        &s3c_device_hsmmc3,
+        &s3c_device_rtc,
+        &s3c_device_wdt,
+        &smdkv310_smsc911x,
+};
+
+static void __init smdkv310_smsc911x_init(void)
+{
+        u32 cs1;
+
+        /* configure nCS1 width to 16 bits */
+        cs1 = __raw_readl(S5PV310_SROM_BW) &
+                    ~(S5PV310_SROM_BW__CS_MASK <<
+                                    S5PV310_SROM_BW__NCS1__SHIFT);
+        cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) |
+                (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) |
+                (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) <<
+                S5PV310_SROM_BW__NCS1__SHIFT;
+        __raw_writel(cs1, S5PV310_SROM_BW);
+
+        /* set timing for nCS1 suitable for ethernet chip */
+        __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) |
+                     (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) |
+                     (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) |
+                     (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) |
+                     (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) |
+                     (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) |
+                     (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1);
+}
+
 static void __init smdkv310_map_io(void)
 {
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -74,9 +182,14 @@ static void __init smdkv310_map_io(void)
 
 static void __init smdkv310_machine_init(void)
 {
-#ifdef CONFIG_CACHE_L2X0
-        l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
-#endif
+        smdkv310_smsc911x_init();
+
+        s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
+        s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
+
+        platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
 }
 
 MACHINE_START(SMDKV310, "SMDKV310")
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
index d7c2ec770f88..16d8fc00cafd 100644
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ b/arch/arm/mach-s5pv310/mach-universal_c210.c
@@ -7,15 +7,20 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/platform_device.h>
 #include <linux/serial_core.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-#include <asm/hardware/cache-l2x0.h>
 
 #include <plat/regs-serial.h>
 #include <plat/s5pv310.h>
 #include <plat/cpu.h>
+#include <plat/devs.h>
 
 #include <mach/map.h>
 
@@ -60,6 +65,72 @@ static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
         },
 };
 
+static struct gpio_keys_button universal_gpio_keys_tables[] = {
+        {
+                .code                   = KEY_VOLUMEUP,
+                .gpio                   = S5PV310_GPX2(0),      /* XEINT16 */
+                .desc                   = "gpio-keys: KEY_VOLUMEUP",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_VOLUMEDOWN,
+                .gpio                   = S5PV310_GPX2(1),      /* XEINT17 */
+                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_CONFIG,
+                .gpio                   = S5PV310_GPX2(2),      /* XEINT18 */
+                .desc                   = "gpio-keys: KEY_CONFIG",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_CAMERA,
+                .gpio                   = S5PV310_GPX2(3),      /* XEINT19 */
+                .desc                   = "gpio-keys: KEY_CAMERA",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        }, {
+                .code                   = KEY_OK,
+                .gpio                   = S5PV310_GPX3(5),      /* XEINT29 */
+                .desc                   = "gpio-keys: KEY_OK",
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .debounce_interval      = 1,
+        },
+};
+
+static struct gpio_keys_platform_data universal_gpio_keys_data = {
+        .buttons        = universal_gpio_keys_tables,
+        .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
+};
+
+static struct platform_device universal_gpio_keys = {
+        .name                   = "gpio-keys",
+        .dev                    = {
+                .platform_data  = &universal_gpio_keys_data,
+        },
+};
+
+/* I2C0 */
+static struct i2c_board_info i2c0_devs[] __initdata = {
+        /* Camera, To be updated */
+};
+
+/* I2C1 */
+static struct i2c_board_info i2c1_devs[] __initdata = {
+        /* Gyro, To be updated */
+};
+
+static struct platform_device *universal_devices[] __initdata = {
+        &universal_gpio_keys,
+        &s5p_device_onenand,
+};
+
 static void __init universal_map_io(void)
 {
         s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -69,9 +140,11 @@ static void __init universal_map_io(void)
 
 static void __init universal_machine_init(void)
 {
-#ifdef CONFIG_CACHE_L2X0
-        l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
-#endif
+        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
+        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+
+        /* Last */
+        platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
 }
 
 MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c
index 436712807383..f47f8f3152ec 100644
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ b/arch/arm/mach-s5pv310/setup-i2c0.c
@@ -21,8 +21,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PV310_GPD1(0), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV310_GPD1(0), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PV310_GPD1(1), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV310_GPD1(1), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-s5pv310/setup-i2c1.c
index 1ecd5bc35b5a..9d07e4e2f14c 100644
--- a/arch/arm/mach-s5pv310/setup-i2c1.c
+++ b/arch/arm/mach-s5pv310/setup-i2c1.c
@@ -18,8 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PV310_GPD1(2), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV310_GPD1(2), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PV310_GPD1(3), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(S5PV310_GPD1(3), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-s5pv310/setup-i2c2.c
index 4c0d8def660a..4163b1233daf 100644
--- a/arch/arm/mach-s5pv310/setup-i2c2.c
+++ b/arch/arm/mach-s5pv310/setup-i2c2.c
@@ -18,8 +18,6 @@ struct platform_device; /* don't need the contents */
 
 void s3c_i2c2_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S5PV310_GPA0(6), S3C_GPIO_SFN(3));
-        s3c_gpio_setpull(S5PV310_GPA0(6), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgpin(S5PV310_GPA0(7), S3C_GPIO_SFN(3));
-        s3c_gpio_setpull(S5PV310_GPA0(7), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2,
+                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-s5pv310/setup-i2c3.c
new file mode 100644
index 000000000000..180f153d2a20
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c3.c
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C3 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c3_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2,
+                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-s5pv310/setup-i2c4.c
new file mode 100644
index 000000000000..909e8dfc5316
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c4.c
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c4.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C4 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c4_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PV310_GPB(2), 2,
+                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-s5pv310/setup-i2c5.c
new file mode 100644
index 000000000000..5d0fa4ac0283
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c5.c
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c5.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C5 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c5_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PV310_GPB(6), 2,
+                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-s5pv310/setup-i2c6.c
new file mode 100644
index 000000000000..34aafab92ac4
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c6.c
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c6.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C6 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c6_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2,
+                              S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-s5pv310/setup-i2c7.c
new file mode 100644
index 000000000000..9b25b8d18920
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c7.c
@@ -0,0 +1,23 @@
+/*
+ * linux/arch/arm/mach-s5pv310/setup-i2c7.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *
+ * I2C7 GPIO configuration.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+#include <linux/gpio.h>
+#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+
+void s3c_i2c7_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2,
+                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..86d38cc49135
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
@@ -0,0 +1,152 @@
+/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+        unsigned int gpio;
+
+        /* Set all the necessary GPK0[0:1] pins to special-function 2 */
+        for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        switch (width) {
+        case 8:
+                for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+                        /* Data pin GPK1[3:6] to special-funtion 3 */
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+                }
+        case 4:
+                for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
+                        /* Data pin GPK0[3:6] to special-funtion 2 */
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+                }
+        default:
+                break;
+        }
+
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+}
+
+void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+        unsigned int gpio;
+
+        /* Set all the necessary GPK1[0:1] pins to special-function 2 */
+        for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
+                /* Data pin GPK1[3:6] to special-function 2 */
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+}
+
+void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+        unsigned int gpio;
+
+        /* Set all the necessary GPK2[0:1] pins to special-function 2 */
+        for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        switch (width) {
+        case 8:
+                for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+                        /* Data pin GPK3[3:6] to special-function 3 */
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+                }
+        case 4:
+                for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
+                        /* Data pin GPK2[3:6] to special-function 2 */
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+                }
+        default:
+                break;
+        }
+
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+}
+
+void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+        unsigned int gpio;
+
+        /* Set all the necessary GPK3[0:1] pins to special-function 2 */
+        for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
+                /* Data pin GPK3[3:6] to special-function 2 */
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
+                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+        }
+}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-s5pv310/setup-sdhci.c
new file mode 100644
index 000000000000..db8358fc4662
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-sdhci.c
@@ -0,0 +1,69 @@
+/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s5pv310_hsmmc_clksrcs[4] = {
+        [0] = NULL,
+        [1] = NULL,
+        [2] = "sclk_mmc",       /* mmc_bus */
+        [3] = NULL,
+};
+
+void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
+                                  struct mmc_ios *ios, struct mmc_card *card)
+{
+        u32 ctrl2, ctrl3;
+
+        /* don't need to alter anything acording to card-type */
+
+        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+
+        /* select base clock source to HCLK */
+
+        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+
+        /*
+         * clear async mode, enable conflict mask, rx feedback ctrl, SD
+         * clk hold and no use debounce count
+         */
+
+        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+                  S3C_SDHCI_CTRL2_ENFBCLKRX |
+                  S3C_SDHCI_CTRL2_DFCNT_NONE |
+                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+        /* Tx and Rx feedback clock delay control */
+
+        if (ios->clock < 25 * 1000000)
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+                         S3C_SDHCI_CTRL3_FCSEL2 |
+                         S3C_SDHCI_CTRL3_FCSEL1 |
+                         S3C_SDHCI_CTRL3_FCSEL0);
+        else
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index c0a13ef5436f..96f7dc103b59 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -184,16 +184,15 @@ static int sa1100_target(struct cpufreq_policy *policy,
 {
         unsigned int cur = sa11x0_getspeed(0);
         unsigned int new_ppcr;
-
         struct cpufreq_freqs freqs;
+
+        new_ppcr = sa11x0_freq_to_ppcr(target_freq);
         switch(relation){
         case CPUFREQ_RELATION_L:
-                new_ppcr = sa11x0_freq_to_ppcr(target_freq);
                 if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
                         new_ppcr--;
                 break;
         case CPUFREQ_RELATION_H:
-                new_ppcr = sa11x0_freq_to_ppcr(target_freq);
                 if ((sa11x0_ppcr_to_freq(new_ppcr) > target_freq) &&
                     (sa11x0_ppcr_to_freq(new_ppcr - 1) >= policy->min))
                         new_ppcr--;
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 54b479c35ee0..51dcd59eda6a 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -116,4 +116,6 @@ endmenu
 config SH_CLK_CPG
         bool
 
+source "drivers/sh/Kconfig"
+
 endif
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 14923989ea05..d3260542b943 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -30,7 +30,6 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
-#include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/i2c.h>
 #include <linux/i2c/tsc2007.h>
@@ -44,6 +43,10 @@
 #include <linux/input/sh_keysc.h>
 #include <linux/usb/r8a66597.h>
 
+#include <media/sh_mobile_ceu.h>
+#include <media/sh_mobile_csi2.h>
+#include <media/soc_camera.h>
+
 #include <sound/sh_fsi.h>
 
 #include <video/sh_mobile_hdmi.h>
@@ -160,11 +163,13 @@ static struct mtd_partition nor_flash_partitions[] = {
                 .name           = "loader",
                 .offset         = 0x00000000,
                 .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
         },
         {
                 .name           = "bootenv",
                 .offset         = MTDPART_OFS_APPEND,
                 .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
         },
         {
                 .name           = "kernel_ro",
@@ -235,10 +240,22 @@ static struct platform_device smc911x_device = {
         },
 };
 
+/*
+ * The card detect pin of the top SD/MMC slot (CN7) is active low and is
+ * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ */
+static int slot_cn7_get_cd(struct platform_device *pdev)
+{
+        if (gpio_is_valid(GPIO_PORT41))
+                return !gpio_get_value(GPIO_PORT41);
+        else
+                return -ENXIO;
+}
+
 /* SH_MMCIF */
 static struct resource sh_mmcif_resources[] = {
         [0] = {
-                .name   = "SH_MMCIF",
+                .name   = "MMCIF",
                 .start  = 0xE6BD0000,
                 .end    = 0xE6BD00FF,
                 .flags  = IORESOURCE_MEM,
@@ -261,6 +278,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
         .caps           = MMC_CAP_4_BIT_DATA |
                           MMC_CAP_8_BIT_DATA |
                           MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
 };
 
 static struct platform_device sh_mmcif_device = {
@@ -310,6 +328,8 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
         .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
         .tmio_ocr_mask  = MMC_VDD_165_195,
         .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -375,10 +395,40 @@ static struct platform_device usb1_host_device = {
         .resource       = usb1_host_resources,
 };
 
+const static struct fb_videomode ap4evb_lcdc_modes[] = {
+        {
+#ifdef CONFIG_AP4EVB_QHD
+                .name           = "R63302(QHD)",
+                .xres           = 544,
+                .yres           = 961,
+                .left_margin    = 72,
+                .right_margin   = 600,
+                .hsync_len      = 16,
+                .upper_margin   = 8,
+                .lower_margin   = 8,
+                .vsync_len      = 2,
+                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+#else
+                .name           = "WVGA Panel",
+                .xres           = 800,
+                .yres           = 480,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 70,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync           = 0,
+#endif
+        },
+};
+
 static struct sh_mobile_lcdc_info lcdc_info = {
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
+                .lcd_cfg = ap4evb_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
         }
 };
 
@@ -517,26 +567,41 @@ static struct platform_device *qhd_devices[] __initdata = {
 
 /* FSI */
 #define IRQ_FSI         evt2irq(0x1840)
-#define FSIACKCR        0xE6150018
-static void fsiackcr_init(struct clk *clk)
+
+static int fsi_set_rate(int is_porta, int rate)
 {
-        u32 status = __raw_readl(clk->enable_reg);
+        struct clk *fsib_clk;
+        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        int ret;
 
-        /* use external clock */
-        status &= ~0x000000ff;
-        status |= 0x00000080;
-        __raw_writel(status, clk->enable_reg);
-}
+        /* set_rate is not needed if port A */
+        if (is_porta)
+                return 0;
+
+        fsib_clk = clk_get(NULL, "fsib_clk");
+        if (IS_ERR(fsib_clk))
+                return -EINVAL;
+
+        switch (rate) {
+        case 44100:
+                clk_set_rate(fsib_clk, clk_round_rate(fsib_clk, 11283000));
+                ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        case 48000:
+                clk_set_rate(fsib_clk, clk_round_rate(fsib_clk, 85428000));
+                clk_set_rate(fdiv_clk, clk_round_rate(fdiv_clk, 12204000));
+                ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        default:
+                pr_err("unsupported rate in FSI2 port B\n");
+                ret = -EINVAL;
+                break;
+        }
 
-static struct clk_ops fsiackcr_clk_ops = {
-        .init = fsiackcr_init,
-};
+        clk_put(fsib_clk);
 
-static struct clk fsiackcr_clk = {
-        .ops            = &fsiackcr_clk_ops,
-        .enable_reg     = (void __iomem *)FSIACKCR,
-        .rate           = 0, /* unknown */
-};
+        return ret;
+}
 
 static struct sh_fsi_platform_info fsi_info = {
         .porta_flags = SH_FSI_BRS_INV |
@@ -544,6 +609,12 @@ static struct sh_fsi_platform_info fsi_info = {
                        SH_FSI_IN_SLAVE_MODE |
                        SH_FSI_OFMT(PCM) |
                        SH_FSI_IFMT(PCM),
+
+        .portb_flags = SH_FSI_BRS_INV |
+                       SH_FSI_BRM_INV |
+                       SH_FSI_LRS_INV |
+                       SH_FSI_OFMT(SPDIF),
+        .set_rate = fsi_set_rate,
 };
 
 static struct resource fsi_resources[] = {
@@ -577,26 +648,6 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
                 .interface_type = RGB24,
                 .clock_divider = 1,
                 .flags = LCDC_FLAGS_DWPOL,
-                .lcd_cfg = {
-                        .name = "HDMI",
-                        /* So far only 720p is supported */
-                        .xres = 1280,
-                        .yres = 720,
-                        /*
-                         * If left and right margins are not multiples of 8,
-                         * LDHAJR will be adjusted accordingly by the LCDC
-                         * driver. Until we start using EDID, these values
-                         * might have to be adjusted for different monitors.
-                         */
-                        .left_margin = 200,
-                        .right_margin = 88,
-                        .hsync_len = 48,
-                        .upper_margin = 20,
-                        .lower_margin = 5,
-                        .vsync_len = 5,
-                        .pixclock = 13468,
-                        .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
-                },
         }
 };
 
@@ -608,7 +659,7 @@ static struct resource lcdc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = intcs_evt2irq(0x17a0),
+                .start  = intcs_evt2irq(0x1780),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -627,6 +678,7 @@ static struct platform_device lcdc1_device = {
 static struct sh_mobile_hdmi_info hdmi_info = {
         .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
         .lcd_dev = &lcdc1_device.dev,
+        .flags = HDMI_SND_SRC_SPDIF,
 };
 
 static struct resource hdmi_resources[] = {
@@ -689,6 +741,95 @@ static struct platform_device leds_device = {
         },
 };
 
+static struct i2c_board_info imx074_info = {
+        I2C_BOARD_INFO("imx074", 0x1a),
+};
+
+struct soc_camera_link imx074_link = {
+        .bus_id         = 0,
+        .board_info     = &imx074_info,
+        .i2c_adapter_id = 0,
+        .module_name    = "imx074",
+};
+
+static struct platform_device ap4evb_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &imx074_link,
+        },
+};
+
+static struct sh_csi2_client_config csi2_clients[] = {
+        {
+                .phy            = SH_CSI2_PHY_MAIN,
+                .lanes          = 3,
+                .channel        = 0,
+                .pdev           = &ap4evb_camera,
+        },
+};
+
+static struct sh_csi2_pdata csi2_info = {
+        .type           = SH_CSI2C,
+        .clients        = csi2_clients,
+        .num_clients    = ARRAY_SIZE(csi2_clients),
+        .flags          = SH_CSI2_ECC | SH_CSI2_CRC,
+};
+
+static struct resource csi2_resources[] = {
+        [0] = {
+                .name   = "CSI2",
+                .start  = 0xffc90000,
+                .end    = 0xffc90fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x17a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device csi2_device = {
+        .name   = "sh-mobile-csi2",
+        .id     = 0,
+        .num_resources  = ARRAY_SIZE(csi2_resources),
+        .resource       = csi2_resources,
+        .dev    = {
+                .platform_data = &csi2_info,
+        },
+};
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+        .csi2_dev = &csi2_device.dev,
+};
+
+static struct resource ceu_resources[] = {
+        [0] = {
+                .name   = "CEU",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x880),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu_device = {
+        .name           = "sh_mobile_ceu",
+        .id             = 0, /* "ceu0" clock */
+        .num_resources  = ARRAY_SIZE(ceu_resources),
+        .resource       = ceu_resources,
+        .dev    = {
+                .platform_data  = &sh_mobile_ceu_info,
+        },
+};
+
 static struct platform_device *ap4evb_devices[] __initdata = {
         &leds_device,
         &nor_flash_device,
@@ -701,6 +842,9 @@ static struct platform_device *ap4evb_devices[] __initdata = {
         &lcdc1_device,
         &lcdc_device,
         &hdmi_device,
+        &csi2_device,
+        &ceu_device,
+        &ap4evb_camera,
 };
 
 static int __init hdmi_init_pm_clock(void)
@@ -715,22 +859,22 @@ static int __init hdmi_init_pm_clock(void)
                 goto out;
         }
 
-        ret = clk_set_parent(&pllc2_clk, &dv_clki_div2_clk);
+        ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
         if (ret < 0) {
-                pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, pllc2_clk.usecount);
+                pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
                 goto out;
         }
 
-        pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&pllc2_clk));
+        pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
 
-        rate = clk_round_rate(&pllc2_clk, 594000000);
+        rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
         if (rate < 0) {
                 pr_err("Cannot get suitable rate: %ld\n", rate);
                 ret = rate;
                 goto out;
         }
 
-        ret = clk_set_rate(&pllc2_clk, rate);
+        ret = clk_set_rate(&sh7372_pllc2_clk, rate);
         if (ret < 0) {
                 pr_err("Cannot set rate %ld: %d\n", rate, ret);
                 goto out;
@@ -738,7 +882,7 @@ static int __init hdmi_init_pm_clock(void)
 
         pr_debug("PLLC2 set frequency %lu\n", rate);
 
-        ret = clk_set_parent(hdmi_ick, &pllc2_clk);
+        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
         if (ret < 0) {
                 pr_err("Cannot set HDMI parent: %d\n", ret);
                 goto out;
@@ -752,11 +896,51 @@ out:
 
 device_initcall(hdmi_init_pm_clock);
 
+#define FSIACK_DUMMY_RATE 48000
+static int __init fsi_init_pm_clock(void)
+{
+        struct clk *fsia_ick;
+        int ret;
+
+        /*
+         * FSIACK is connected to AK4642,
+         * and the rate is depend on playing sound rate.
+         * So, set dummy rate (= 48k) here
+         */
+        ret = clk_set_rate(&sh7372_fsiack_clk, FSIACK_DUMMY_RATE);
+        if (ret < 0) {
+                pr_err("Cannot set FSIACK dummy rate: %d\n", ret);
+                return ret;
+        }
+
+        fsia_ick = clk_get(&fsi_device.dev, "icka");
+        if (IS_ERR(fsia_ick)) {
+                ret = PTR_ERR(fsia_ick);
+                pr_err("Cannot get FSI ICK: %d\n", ret);
+                return ret;
+        }
+
+        ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
+        if (ret < 0) {
+                pr_err("Cannot set FSI-A parent: %d\n", ret);
+                goto out;
+        }
+
+        ret = clk_set_rate(fsia_ick, FSIACK_DUMMY_RATE);
+        if (ret < 0)
+                pr_err("Cannot set FSI-A rate: %d\n", ret);
+
+out:
+        clk_put(fsia_ick);
+
+        return ret;
+}
+device_initcall(fsi_init_pm_clock);
+
 /*
  * FIXME !!
  *
  * gpio_no_direction
- * gpio_pull_up
  * are quick_hack.
  *
  * current gpio frame work doesn't have
@@ -768,49 +952,37 @@ static void __init gpio_no_direction(u32 addr)
         __raw_writeb(0x00, addr);
 }
 
-static void __init gpio_pull_up(u32 addr)
-{
-        u8 data = __raw_readb(addr);
-
-        data &= 0x0F;
-        data |= 0xC0;
-        __raw_writeb(data, addr);
-}
-
 /* TouchScreen */
+#ifdef CONFIG_AP4EVB_QHD
+# define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
+# define GPIO_TSC_PORT  GPIO_PORT123
+#else /* WVGA */
+# define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
+# define GPIO_TSC_PORT  GPIO_PORT40
+#endif
+
 #define IRQ28   evt2irq(0x3380) /* IRQ28A */
 #define IRQ7    evt2irq(0x02e0) /* IRQ7A */
 static int ts_get_pendown_state(void)
 {
-        int val1, val2;
+        int val;
 
-        gpio_free(GPIO_FN_IRQ28_123);
-        gpio_free(GPIO_FN_IRQ7_40);
+        gpio_free(GPIO_TSC_IRQ);
 
-        gpio_request(GPIO_PORT123, NULL);
-        gpio_request(GPIO_PORT40, NULL);
+        gpio_request(GPIO_TSC_PORT, NULL);
 
-        gpio_direction_input(GPIO_PORT123);
-        gpio_direction_input(GPIO_PORT40);
+        gpio_direction_input(GPIO_TSC_PORT);
 
-        val1 = gpio_get_value(GPIO_PORT123);
-        val2 = gpio_get_value(GPIO_PORT40);
+        val = gpio_get_value(GPIO_TSC_PORT);
 
-        gpio_request(GPIO_FN_IRQ28_123, NULL);  /* for QHD */
-        gpio_request(GPIO_FN_IRQ7_40, NULL);    /* for WVGA */
+        gpio_request(GPIO_TSC_IRQ, NULL);
 
-        return val1 ^ val2;
+        return !val;
 }
 
-#define PORT40CR        0xE6051028
-#define PORT123CR       0xE605007B
 static int ts_init(void)
 {
-        gpio_request(GPIO_FN_IRQ28_123, NULL);  /* for QHD */
-        gpio_request(GPIO_FN_IRQ7_40, NULL);    /* for WVGA */
-
-        gpio_pull_up(PORT40CR);
-        gpio_pull_up(PORT123CR);
+        gpio_request(GPIO_TSC_IRQ, NULL);
 
         return 0;
 }
@@ -865,6 +1037,7 @@ static void __init ap4evb_map_io(void)
 
 #define GPIO_PORT9CR    0xE6051009
 #define GPIO_PORT10CR   0xE605100A
+#define USCCR1          0xE6058144
 static void __init ap4evb_init(void)
 {
         u32 srcr4;
@@ -935,7 +1108,7 @@ static void __init ap4evb_init(void)
         /* setup USB phy */
         __raw_writew(0x8a0a, 0xE6058130);       /* USBCR2 */
 
-        /* enable FSI2 */
+        /* enable FSI2 port A (ak4643) */
         gpio_request(GPIO_FN_FSIAIBT,   NULL);
         gpio_request(GPIO_FN_FSIAILR,   NULL);
         gpio_request(GPIO_FN_FSIAISLD,  NULL);
@@ -948,6 +1121,14 @@ static void __init ap4evb_init(void)
         gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
         gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
 
+        /* card detect pin for MMC slot (CN7) */
+        gpio_request(GPIO_PORT41, NULL);
+        gpio_direction_input(GPIO_PORT41);
+
+        /* setup FSI2 port B (HDMI) */
+        gpio_request(GPIO_FN_FSIBCK, NULL);
+        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
+
         /* set SPU2 clock to 119.6 MHz */
         clk = clk_get(NULL, "spu_clk");
         if (!IS_ERR(clk)) {
@@ -955,14 +1136,6 @@ static void __init ap4evb_init(void)
                 clk_put(clk);
         }
 
-        /* change parent of FSI A */
-        clk = clk_get(NULL, "fsia_clk");
-        if (!IS_ERR(clk)) {
-                clk_register(&fsiackcr_clk);
-                clk_set_parent(clk, &fsiackcr_clk);
-                clk_put(clk);
-        }
-
         /*
          * set irq priority, to avoid sound chopping
          * when NFS rootfs is used
@@ -977,8 +1150,10 @@ static void __init ap4evb_init(void)
                                 ARRAY_SIZE(i2c1_devices));
 
 #ifdef CONFIG_AP4EVB_QHD
+
         /*
-         * QHD
+         * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
+         * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
          */
 
         /* enable KEYSC */
@@ -1004,17 +1179,6 @@ static void __init ap4evb_init(void)
         lcdc_info.ch[0].interface_type          = RGB24;
         lcdc_info.ch[0].clock_divider           = 1;
         lcdc_info.ch[0].flags                   = LCDC_FLAGS_DWPOL;
-        lcdc_info.ch[0].lcd_cfg.name            = "R63302(QHD)";
-        lcdc_info.ch[0].lcd_cfg.xres            = 544;
-        lcdc_info.ch[0].lcd_cfg.yres            = 961;
-        lcdc_info.ch[0].lcd_cfg.left_margin     = 72;
-        lcdc_info.ch[0].lcd_cfg.right_margin    = 600;
-        lcdc_info.ch[0].lcd_cfg.hsync_len       = 16;
-        lcdc_info.ch[0].lcd_cfg.upper_margin    = 8;
-        lcdc_info.ch[0].lcd_cfg.lower_margin    = 8;
-        lcdc_info.ch[0].lcd_cfg.vsync_len       = 2;
-        lcdc_info.ch[0].lcd_cfg.sync            = FB_SYNC_VERT_HIGH_ACT |
-                                                  FB_SYNC_HOR_HIGH_ACT;
         lcdc_info.ch[0].lcd_size_cfg.width      = 44;
         lcdc_info.ch[0].lcd_size_cfg.height     = 79;
 
@@ -1022,8 +1186,10 @@ static void __init ap4evb_init(void)
 
 #else
         /*
-         * WVGA
+         * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
+         * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
          */
+
         gpio_request(GPIO_FN_LCDD17,   NULL);
         gpio_request(GPIO_FN_LCDD16,   NULL);
         gpio_request(GPIO_FN_LCDD15,   NULL);
@@ -1055,16 +1221,6 @@ static void __init ap4evb_init(void)
         lcdc_info.ch[0].interface_type          = RGB18;
         lcdc_info.ch[0].clock_divider           = 2;
         lcdc_info.ch[0].flags                   = 0;
-        lcdc_info.ch[0].lcd_cfg.name            = "WVGA Panel";
-        lcdc_info.ch[0].lcd_cfg.xres            = 800;
-        lcdc_info.ch[0].lcd_cfg.yres            = 480;
-        lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
-        lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
-        lcdc_info.ch[0].lcd_cfg.hsync_len       = 70;
-        lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
-        lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
-        lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
-        lcdc_info.ch[0].lcd_cfg.sync            = 0;
         lcdc_info.ch[0].lcd_size_cfg.width      = 152;
         lcdc_info.ch[0].lcd_size_cfg.height     = 91;
 
@@ -1075,6 +1231,23 @@ static void __init ap4evb_init(void)
         i2c_register_board_info(0, &tsc_device, 1);
 #endif /* CONFIG_AP4EVB_QHD */
 
+        /* CEU */
+
+        /*
+         * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
+         * becomes available
+         */
+
+        /* MIPI-CSI stuff */
+        gpio_request(GPIO_FN_VIO_CKO, NULL);
+
+        clk = clk_get(NULL, "vck1_clk");
+        if (!IS_ERR(clk)) {
+                clk_set_rate(clk, clk_round_rate(clk, 13000000));
+                clk_enable(clk);
+                clk_put(clk);
+        }
+
         sh7372_add_standard_devices();
 
         /* HDMI */
@@ -1097,7 +1270,7 @@ static void __init ap4evb_timer_init(void)
         shmobile_timer.init();
 
         /* External clock source */
-        clk_set_rate(&dv_clki_clk, 27000000);
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
 }
 
 static struct sys_timer ap4evb_timer = {
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index b6454c9f2abb..9f78729098f2 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -321,7 +321,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
-        CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
         CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
         CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 759468992ad2..7db31e6c6bf2 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -50,8 +50,11 @@
 #define SMSTPCR3        0xe615013c
 #define SMSTPCR4        0xe6150140
 
+#define FSIDIVA         0xFE1F8000
+#define FSIDIVB         0xFE1F8008
+
 /* Platforms must set frequency on their DV_CLKI pin */
-struct clk dv_clki_clk = {
+struct clk sh7372_dv_clki_clk = {
 };
 
 /* Fixed 32 KHz root clock from EXTALR pin */
@@ -86,9 +89,9 @@ static struct clk_ops div2_clk_ops = {
 };
 
 /* Divide dv_clki by two */
-struct clk dv_clki_div2_clk = {
+struct clk sh7372_dv_clki_div2_clk = {
         .ops            = &div2_clk_ops,
-        .parent         = &dv_clki_clk,
+        .parent         = &sh7372_dv_clki_clk,
 };
 
 /* Divide extal1 by two */
@@ -150,7 +153,7 @@ static struct clk pllc1_div2_clk = {
 static struct clk *pllc2_parent[] = {
         [0] = &extal1_div2_clk,
         [1] = &extal2_div2_clk,
-        [2] = &dv_clki_div2_clk,
+        [2] = &sh7372_dv_clki_div2_clk,
 };
 
 /* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
@@ -284,27 +287,37 @@ static struct clk_ops pllc2_clk_ops = {
         .set_parent     = pllc2_set_parent,
 };
 
-struct clk pllc2_clk = {
+struct clk sh7372_pllc2_clk = {
         .ops            = &pllc2_clk_ops,
         .parent         = &extal1_div2_clk,
         .freq_table     = pllc2_freq_table,
+        .nr_freqs       = ARRAY_SIZE(pllc2_freq_table) - 1,
         .parent_table   = pllc2_parent,
         .parent_num     = ARRAY_SIZE(pllc2_parent),
 };
 
+/* External input clock (pin name: FSIACK/FSIBCK ) */
+struct clk sh7372_fsiack_clk = {
+};
+
+struct clk sh7372_fsibck_clk = {
+};
+
 static struct clk *main_clks[] = {
-        &dv_clki_clk,
+        &sh7372_dv_clki_clk,
         &r_clk,
         &sh7372_extal1_clk,
         &sh7372_extal2_clk,
-        &dv_clki_div2_clk,
+        &sh7372_dv_clki_div2_clk,
         &extal1_div2_clk,
         &extal2_div2_clk,
         &extal2_div4_clk,
         &pllc0_clk,
         &pllc1_clk,
         &pllc1_div2_clk,
-        &pllc2_clk,
+        &sh7372_pllc2_clk,
+        &sh7372_fsiack_clk,
+        &sh7372_fsibck_clk,
 };
 
 static void div4_kick(struct clk *clk)
@@ -357,7 +370,7 @@ static struct clk div4_clks[DIV4_NR] = {
 };
 
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
-       DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
+       DIV6_SUB, DIV6_SPU,
        DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
        DIV6_NR };
 
@@ -367,8 +380,6 @@ static struct clk div6_clks[DIV6_NR] = {
         [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
         [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
         [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
-        [DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
-        [DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
         [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
         [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
         [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
@@ -377,24 +388,137 @@ static struct clk div6_clks[DIV6_NR] = {
         [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
 };
 
-enum { DIV6_HDMI, DIV6_REPARENT_NR };
+enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
 
 /* Indices are important - they are the actual src selecting values */
 static struct clk *hdmi_parent[] = {
         [0] = &pllc1_div2_clk,
-        [1] = &pllc2_clk,
-        [2] = &dv_clki_clk,
+        [1] = &sh7372_pllc2_clk,
+        [2] = &sh7372_dv_clki_clk,
         [3] = NULL,     /* pllc2_div4 not implemented yet */
 };
 
+static struct clk *fsiackcr_parent[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &sh7372_pllc2_clk,
+        [2] = &sh7372_fsiack_clk, /* external input for FSI A */
+        [3] = NULL,     /* setting prohibited */
+};
+
+static struct clk *fsibckcr_parent[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &sh7372_pllc2_clk,
+        [2] = &sh7372_fsibck_clk, /* external input for FSI B */
+        [3] = NULL,     /* setting prohibited */
+};
+
 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
         [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
                                       hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
+        [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
+                                      fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
+        [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
+                                      fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
+};
+
+/* FSI DIV */
+static unsigned long fsidiv_recalc(struct clk *clk)
+{
+        unsigned long value;
+
+        value = __raw_readl(clk->mapping->base);
+
+        if ((value & 0x3) != 0x3)
+                return 0;
+
+        value >>= 16;
+        if (value < 2)
+                return 0;
+
+        return clk->parent->rate / value;
+}
+
+static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_rate_div_range_round(clk, 2, 0xffff, rate);
+}
+
+static void fsidiv_disable(struct clk *clk)
+{
+        __raw_writel(0, clk->mapping->base);
+}
+
+static int fsidiv_enable(struct clk *clk)
+{
+        unsigned long value;
+
+        value  = __raw_readl(clk->mapping->base) >> 16;
+        if (value < 2) {
+                fsidiv_disable(clk);
+                return -ENOENT;
+        }
+
+        __raw_writel((value << 16) | 0x3, clk->mapping->base);
+
+        return 0;
+}
+
+static int fsidiv_set_rate(struct clk *clk,
+                           unsigned long rate, int algo_id)
+{
+        int idx;
+
+        if (clk->parent->rate == rate) {
+                fsidiv_disable(clk);
+                return 0;
+        }
+
+        idx = (clk->parent->rate / rate) & 0xffff;
+        if (idx < 2)
+                return -ENOENT;
+
+        __raw_writel(idx << 16, clk->mapping->base);
+        return fsidiv_enable(clk);
+}
+
+static struct clk_ops fsidiv_clk_ops = {
+        .recalc         = fsidiv_recalc,
+        .round_rate     = fsidiv_round_rate,
+        .set_rate       = fsidiv_set_rate,
+        .enable         = fsidiv_enable,
+        .disable        = fsidiv_disable,
+};
+
+static struct clk_mapping sh7372_fsidiva_clk_mapping = {
+        .phys   = FSIDIVA,
+        .len    = 8,
+};
+
+struct clk sh7372_fsidiva_clk = {
+        .ops            = &fsidiv_clk_ops,
+        .parent         = &div6_reparent_clks[DIV6_FSIA], /* late install */
+        .mapping        = &sh7372_fsidiva_clk_mapping,
+};
+
+static struct clk_mapping sh7372_fsidivb_clk_mapping = {
+        .phys   = FSIDIVB,
+        .len    = 8,
+};
+
+struct clk sh7372_fsidivb_clk = {
+        .ops            = &fsidiv_clk_ops,
+        .parent         = &div6_reparent_clks[DIV6_FSIB],  /* late install */
+        .mapping        = &sh7372_fsidivb_clk_mapping,
+};
+
+static struct clk *late_main_clks[] = {
+        &sh7372_fsidiva_clk,
+        &sh7372_fsidivb_clk,
 };
 
 enum { MSTP001,
        MSTP131, MSTP130,
-       MSTP129, MSTP128, MSTP127, MSTP126,
+       MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
        MSTP118, MSTP117, MSTP116,
        MSTP106, MSTP101, MSTP100,
        MSTP223,
@@ -414,6 +538,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
         [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
         [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
+        [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
         [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
         [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
@@ -429,7 +554,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
         [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
         [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
-        [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */
+        [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
         [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
         [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
         [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
@@ -445,10 +570,11 @@ static struct clk mstp_clks[MSTP_NR] = {
 
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
 
 static struct clk_lookup lookups[] = {
         /* main clocks */
-        CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk),
+        CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
         CLKDEV_CON_ID("r_clk", &r_clk),
         CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
         CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
@@ -458,7 +584,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
         CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
         CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
-        CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
+        CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
 
         /* DIV4 clocks */
         CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -483,8 +609,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
         CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
         CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
-        CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]),
-        CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]),
+        CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FSIA]),
+        CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FSIB]),
         CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
         CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
@@ -501,6 +627,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
         CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
         CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
+        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
+        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
         CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
@@ -516,7 +644,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
-        CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
         CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
         CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
@@ -531,7 +659,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
         CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
-        {.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
+
+        CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
+        CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
+        CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
 };
 
 void __init sh7372_clock_init(void)
@@ -548,11 +679,14 @@ void __init sh7372_clock_init(void)
                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR);
+                ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
 
         if (!ret)
                 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
+        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
+                ret = clk_register(late_main_clks[k]);
+
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index e007c28cf0a8..f91395aeb9ab 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -333,7 +333,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
-        CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
         CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
         CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
index 5bc6bd444d72..2b1bb9e43dda 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -35,12 +35,12 @@ static inline int gpio_cansleep(unsigned gpio)
 
 static inline int gpio_to_irq(unsigned gpio)
 {
-        return -ENOSYS;
+        return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned int irq)
 {
-        return -EINVAL;
+        return -ENOSYS;
 }
 
 #endif /* CONFIG_GPIOLIB */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 33e9700ded7e..e4f9004e7103 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -457,8 +457,14 @@ enum {
         SHDMA_SLAVE_SDHI2_TX,
 };
 
-extern struct clk dv_clki_clk;
-extern struct clk dv_clki_div2_clk;
-extern struct clk pllc2_clk;
+extern struct clk sh7372_extal1_clk;
+extern struct clk sh7372_extal2_clk;
+extern struct clk sh7372_dv_clki_clk;
+extern struct clk sh7372_dv_clki_div2_clk;
+extern struct clk sh7372_pllc2_clk;
+extern struct clk sh7372_fsiack_clk;
+extern struct clk sh7372_fsibck_clk;
+extern struct clk sh7372_fsidiva_clk;
+extern struct clk sh7372_fsidivb_clk;
 
 #endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index e3551b56cd03..30b2f400666a 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -98,7 +98,7 @@ static struct intc_vect intca_vectors[] __initdata = {
         INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
         INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
         INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
-        INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
+        INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0),
         INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
         INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
         INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
@@ -369,9 +369,13 @@ enum {
         INTCS,
 
         /* interrupt sources INTCS */
+
+        /* IRQ0S - IRQ31S */
         VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
         RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
         CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
+        /* MFI */
+        /* BBIF2 */
         VPU,
         TSIF1,
         _3DG_SGX530,
@@ -379,13 +383,17 @@ enum {
         IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
         IPMMU_IPMMUR, IPMMU_IPMMUR2,
         RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
+        /* KEYSC */
+        /* TTI20 */
         MSIOF,
         IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
         TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
         CMT0,
         TSIF0,
+        /* CMT2 */
         LMB,
         CTI,
+        /* RWDT0 */
         ICB,
         JPU_JPEG,
         LCDC,
@@ -397,11 +405,17 @@ enum {
         CSIRX,
         DSITX_DSITX0,
         DSITX_DSITX1,
+        /* SPU2 */
+        /* FSI */
+        /* FMSI */
+        /* HDMI */
         TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
         CMT4,
         DSITX1_DSITX1_0,
         DSITX1_DSITX1_1,
+        /* MFIS2 */
         CPORTS2R,
+        /* CEC */
         JPU6E,
 
         /* interrupt groups INTCS */
@@ -410,12 +424,15 @@ enum {
 };
 
 static struct intc_vect intcs_vectors[] = {
+        /* IRQ0S - IRQ31S */
         INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
         INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
         INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
         INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
         INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
         INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
+        /* MFI */
+        /* BBIF2 */
         INTCS_VECT(VPU, 0x980),
         INTCS_VECT(TSIF1, 0x9a0),
         INTCS_VECT(_3DG_SGX530, 0x9e0),
@@ -425,14 +442,19 @@ static struct intc_vect intcs_vectors[] = {
         INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
         INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
         INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
+        /* KEYSC */
+        /* TTI20 */
+        INTCS_VECT(MSIOF, 0x0d20),
         INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
         INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
         INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
         INTCS_VECT(TMU_TUNI2, 0xec0),
         INTCS_VECT(CMT0, 0xf00),
         INTCS_VECT(TSIF0, 0xf20),
+        /* CMT2 */
         INTCS_VECT(LMB, 0xf60),
         INTCS_VECT(CTI, 0x400),
+        /* RWDT0 */
         INTCS_VECT(ICB, 0x480),
         INTCS_VECT(JPU_JPEG, 0x560),
         INTCS_VECT(LCDC, 0x580),
@@ -446,12 +468,18 @@ static struct intc_vect intcs_vectors[] = {
         INTCS_VECT(CSIRX, 0x17a0),
         INTCS_VECT(DSITX_DSITX0, 0x17c0),
         INTCS_VECT(DSITX_DSITX1, 0x17e0),
+        /* SPU2 */
+        /* FSI */
+        /* FMSI */
+        /* HDMI */
         INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
         INTCS_VECT(TMU1_TUNI2, 0x1940),
         INTCS_VECT(CMT4, 0x1980),
         INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
         INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
+        /* MFIS2 */
         INTCS_VECT(CPORTS2R, 0x1a20),
+        /* CEC */
         INTCS_VECT(JPU6E, 0x1a80),
 
         INTC_VECT(INTCS, 0xf80),
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index ec420353f8e3..9c265dae138a 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -166,12 +166,12 @@ enum {
         MSIOF2_TSYNC_MARK,      MSIOF2_TSCK_MARK,       MSIOF2_RXD_MARK,
         MSIOF2_TXD_MARK,
 
-        /* MSIOF3 */
+        /* BBIF1 */
         BBIF1_RXD_MARK,         BBIF1_TSYNC_MARK,       BBIF1_TSCK_MARK,
         BBIF1_TXD_MARK,         BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
         BBIF1_FLOW_MARK,        BB_RX_FLOW_N_MARK,
 
-        /* MSIOF4 */
+        /* BBIF2 */
         BBIF2_TSCK1_MARK,       BBIF2_TSYNC1_MARK,
         BBIF2_TXD1_MARK,        BBIF2_RXD_MARK,
 
@@ -976,12 +976,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
         GPIO_FN(MSIOF2_TXD),
 
-        /* MSIOF3 */
+        /* BBIF1 */
         GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
         GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
         GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
 
-        /* MSIOF4 */
+        /* BBIF2 */
         GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
         GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
 
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index 3148c11a550e..003008c18360 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -154,7 +154,6 @@ static struct sh_timer_config cmt10_platform_data = {
         .name = "CMT10",
         .channel_offset = 0x10,
         .timer_bit = 0,
-        .clk = "r_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 125,
 };
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index e26686c9d0b6..564a6d0be473 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -158,7 +158,6 @@ static struct sh_timer_config cmt10_platform_data = {
         .name = "CMT10",
         .channel_offset = 0x10,
         .timer_bit = 0,
-        .clk = "cmt1",
         .clockevent_rating = 125,
         .clocksource_rating = 125,
 };
@@ -186,6 +185,67 @@ static struct platform_device cmt10_device = {
         .num_resources  = ARRAY_SIZE(cmt10_resources),
 };
 
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+        .name = "TMU00",
+        .channel_offset = 0x4,
+        .timer_bit = 0,
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu00_resources[] = {
+        [0] = {
+                .name   = "TMU00",
+                .start  = 0xfff60008,
+                .end    = 0xfff60013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu00_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu00_platform_data,
+        },
+        .resource       = tmu00_resources,
+        .num_resources  = ARRAY_SIZE(tmu00_resources),
+};
+
+static struct sh_timer_config tmu01_platform_data = {
+        .name = "TMU01",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu01_resources[] = {
+        [0] = {
+                .name   = "TMU01",
+                .start  = 0xfff60014,
+                .end    = 0xfff6001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu01_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu01_platform_data,
+        },
+        .resource       = tmu01_resources,
+        .num_resources  = ARRAY_SIZE(tmu01_resources),
+};
+
 /* I2C */
 static struct resource iic0_resources[] = {
         [0] = {
@@ -419,14 +479,14 @@ static struct resource sh7372_dmae0_resources[] = {
         },
         {
                 /* DMA error IRQ */
-                .start  = 246,
-                .end    = 246,
+                .start  = evt2irq(0x20c0),
+                .end    = evt2irq(0x20c0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 /* IRQ for channels 0-5 */
-                .start  = 240,
-                .end    = 245,
+                .start  = evt2irq(0x2000),
+                .end    = evt2irq(0x20a0),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -447,14 +507,14 @@ static struct resource sh7372_dmae1_resources[] = {
         },
         {
                 /* DMA error IRQ */
-                .start  = 254,
-                .end    = 254,
+                .start  = evt2irq(0x21c0),
+                .end    = evt2irq(0x21c0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 /* IRQ for channels 0-5 */
-                .start  = 248,
-                .end    = 253,
+                .start  = evt2irq(0x2100),
+                .end    = evt2irq(0x21a0),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -475,14 +535,14 @@ static struct resource sh7372_dmae2_resources[] = {
         },
         {
                 /* DMA error IRQ */
-                .start  = 262,
-                .end    = 262,
+                .start  = evt2irq(0x22c0),
+                .end    = evt2irq(0x22c0),
                 .flags  = IORESOURCE_IRQ,
         },
         {
                 /* IRQ for channels 0-5 */
-                .start  = 256,
-                .end    = 261,
+                .start  = evt2irq(0x2200),
+                .end    = evt2irq(0x22a0),
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -526,6 +586,11 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
         &scif5_device,
         &scif6_device,
         &cmt10_device,
+        &tmu00_device,
+        &tmu01_device,
+};
+
+static struct platform_device *sh7372_late_devices[] __initdata = {
         &iic0_device,
         &iic1_device,
         &dma0_device,
@@ -537,6 +602,9 @@ void __init sh7372_add_standard_devices(void)
 {
         platform_add_devices(sh7372_early_devices,
                             ARRAY_SIZE(sh7372_early_devices));
+
+        platform_add_devices(sh7372_late_devices,
+                            ARRAY_SIZE(sh7372_late_devices));
 }
 
 void __init sh7372_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index bb4adf17dbf4..575dbd6c2f1d 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -172,7 +172,6 @@ static struct sh_timer_config cmt10_platform_data = {
         .name = "CMT10",
         .channel_offset = 0x10,
         .timer_bit = 0,
-        .clk = "r_clk",
         .clockevent_rating = 125,
         .clocksource_rating = 125,
 };
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 60acf9e708ae..7458fc6df5c6 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -66,7 +66,7 @@ static DEFINE_SPINLOCK(syscon_resetreg_lock);
  *  AMBA bus
  *  |
  *  +- CPU
- *  +- NANDIF NAND Flash interface
+ *  +- FSMC NANDIF NAND Flash interface
  *  +- SEMI Shared Memory interface
  *  +- ISP Image Signal Processor (U335 only)
  *  +- CDS (U335 only)
@@ -726,7 +726,7 @@ static struct clk cpu_clk = {
 };
 
 static struct clk nandif_clk = {
-        .name       = "NANDIF",
+        .name       = "FSMC",
         .parent     = &amba_clk,
         .hw_ctrld   = false,
         .reset      = true,
@@ -1259,7 +1259,7 @@ static struct clk_lookup lookups[] = {
         /* Connected directly to the AMBA bus */
         DEF_LOOKUP("amba",      &amba_clk),
         DEF_LOOKUP("cpu",       &cpu_clk),
-        DEF_LOOKUP("fsmc",      &nandif_clk),
+        DEF_LOOKUP("fsmc-nand", &nandif_clk),
         DEF_LOOKUP("semi",      &semi_clk),
 #ifdef CONFIG_MACH_U300_BS335
         DEF_LOOKUP("isp",       &isp_clk),
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index ea41c236be0f..aa53ee22438f 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -21,7 +21,8 @@
 #include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <mach/coh901318.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/fsmc.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -30,6 +31,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 
+#include <mach/coh901318.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 #include <mach/dma_channels.h>
@@ -285,6 +287,13 @@ static struct resource rtc_resources[] = {
  */
 static struct resource fsmc_resources[] = {
         {
+                .name  = "nand_data",
+                .start = U300_NAND_CS0_PHYS_BASE,
+                .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name  = "fsmc_regs",
                 .start = U300_NAND_IF_PHYS_BASE,
                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
@@ -1429,11 +1438,39 @@ static struct platform_device rtc_device = {
         .resource = rtc_resources,
 };
 
-static struct platform_device fsmc_device = {
-        .name = "nandif",
+static struct mtd_partition u300_partitions[] = {
+        {
+                .name = "bootrecords",
+                .offset = 0,
+                .size = SZ_128K,
+        },
+        {
+                .name = "free",
+                .offset = SZ_128K,
+                .size = 8064 * SZ_1K,
+        },
+        {
+                .name = "platform",
+                .offset = 8192 * SZ_1K,
+                .size = 253952 * SZ_1K,
+        },
+};
+
+static struct fsmc_nand_platform_data nand_platform_data = {
+        .partitions = u300_partitions,
+        .nr_partitions = ARRAY_SIZE(u300_partitions),
+        .options = NAND_SKIP_BBTSCAN,
+        .width = FSMC_NAND_BW8,
+};
+
+static struct platform_device nand_device = {
+        .name = "fsmc-nand",
         .id = -1,
-        .num_resources = ARRAY_SIZE(fsmc_resources),
         .resource = fsmc_resources,
+        .num_resources = ARRAY_SIZE(fsmc_resources),
+        .dev = {
+                .platform_data = &nand_platform_data,
+        },
 };
 
 static struct platform_device ave_device = {
@@ -1465,7 +1502,7 @@ static struct platform_device *platform_devs[] __initdata = {
         &keypad_device,
         &rtc_device,
         &gpio_device,
-        &fsmc_device,
+        &nand_device,
         &wdog_device,
         &ave_device
 };
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 56721a0cd2af..8b85df4c8d8f 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -20,11 +20,9 @@
 
 /* NAND Flash CS0 */
 #define U300_NAND_CS0_PHYS_BASE         0x80000000
-#define U300_NAND_CS0_VIRT_BASE         0xff040000
 
 /* NFIF */
 #define U300_NAND_IF_PHYS_BASE          0x9f800000
-#define U300_NAND_IF_VIRT_BASE          0xff030000
 
 /* AHB Peripherals */
 #define U300_AHB_PER_PHYS_BASE          0xa0000000
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index edb2c0d255c2..00869def5420 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -67,7 +67,7 @@ static struct spi_board_info u300_spi_devices[] = {
                 .bus_num        = 0, /* Only one bus on this chip */
                 .chip_select    = 0,
                 /* Means SPI_CS_HIGH, change if e.g low CS */
-                .mode           = SPI_MODE_1 | SPI_LSB_FIRST | SPI_LOOP,
+                .mode           = SPI_MODE_1 | SPI_LOOP,
         },
 #endif
 };
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e0fd747e447a..73fb1a551ec6 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -10,6 +10,7 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 
+#include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/map.h>
@@ -71,6 +72,46 @@ void __init ux500_init_irq(void)
 }
 
 #ifdef CONFIG_CACHE_L2X0
+static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
+{
+        /* wait for the operation to complete */
+        while (readl(reg) & mask)
+                ;
+}
+
+static inline void ux500_cache_sync(void)
+{
+        void __iomem *base = __io_address(UX500_L2CC_BASE);
+        writel(0, base + L2X0_CACHE_SYNC);
+        ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
+}
+
+/*
+ * The L2 cache cannot be turned off in the non-secure world.
+ * Dummy until a secure service is in place.
+ */
+static void ux500_l2x0_disable(void)
+{
+}
+
+/*
+ * This is only called when doing a kexec, just after turning off the L2
+ * and L1 cache, and it is surrounded by a spinlock in the generic version.
+ * However, we're not really turning off the L2 cache right now and the
+ * PL310 does not support exclusive accesses (used to implement the spinlock).
+ * So, the invalidation needs to be done without the spinlock.
+ */
+static void ux500_l2x0_inv_all(void)
+{
+        void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE);
+        uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
+
+        /* invalidate all ways */
+        writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+        ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+        ux500_cache_sync();
+}
+
 static int ux500_l2x0_init(void)
 {
         void __iomem *l2x0_base;
@@ -80,6 +121,10 @@ static int ux500_l2x0_init(void)
         /* 64KB way size, 8 way associativity, force WA */
         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
 
+        /* Override invalidate function */
+        outer_cache.disable = ux500_l2x0_disable;
+        outer_cache.inv_all = ux500_l2x0_inv_all;
+
         return 0;
 }
 early_initcall(ux500_l2x0_init);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index c2e405a9e025..fd25ccd7272f 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -54,7 +54,9 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = {
 
 static void __init ct_ca9x4_map_io(void)
 {
+#ifdef CONFIG_LOCAL_TIMERS
         twd_base = MMIO_P2V(A9_MPCORE_TWD);
+#endif
         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index a0a2928ae4dd..4414a01e1e8a 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -779,6 +779,14 @@ config CACHE_L2X0
         help
           This option enables the L2x0 PrimeCell.
 
+config CACHE_PL310
+        bool
+        depends on CACHE_L2X0
+        default y if CPU_V7 && !CPU_V6
+        help
+          This option enables optimisations for the PL310 cache
+          controller.
+
 config CACHE_TAUROS2
         bool "Enable the Tauros2 L2 cache controller"
         depends on (ARCH_DOVE || ARCH_MMP)
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 7148e53e6078..1fa6f71470de 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -38,6 +38,17 @@
 #define CACHE_DLIMIT    (CACHE_DSIZE * 2)
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(fa_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(fa_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Clean and invalidate all cache entries in a particular address
@@ -233,6 +244,7 @@ ENDPROC(fa_dma_unmap_area)
 
         .type   fa_cache_fns, #object
 ENTRY(fa_cache_fns)
+        .long   fa_flush_icache_all
         .long   fa_flush_kern_cache_all
         .long   fa_flush_user_cache_all
         .long   fa_flush_user_cache_range
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9982eb385c0f..170c9bb95866 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -28,14 +28,24 @@
 static void __iomem *l2x0_base;
 static DEFINE_SPINLOCK(l2x0_lock);
 static uint32_t l2x0_way_mask;  /* Bitmask of active ways */
+static uint32_t l2x0_size;
 
-static inline void cache_wait(void __iomem *reg, unsigned long mask)
+static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
-        /* wait for the operation to complete */
+        /* wait for cache operation by line or way to complete */
         while (readl_relaxed(reg) & mask)
                 ;
 }
 
+#ifdef CONFIG_CACHE_PL310
+static inline void cache_wait(void __iomem *reg, unsigned long mask)
+{
+        /* cache operations by line are atomic on PL310 */
+}
+#else
+#define cache_wait      cache_wait_way
+#endif
+
 static inline void cache_sync(void)
 {
         void __iomem *base = l2x0_base;
@@ -103,14 +113,40 @@ static void l2x0_cache_sync(void)
         spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
-static inline void l2x0_inv_all(void)
+static void l2x0_flush_all(void)
+{
+        unsigned long flags;
+
+        /* clean all ways */
+        spin_lock_irqsave(&l2x0_lock, flags);
+        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
+        cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
+        cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
+static void l2x0_clean_all(void)
+{
+        unsigned long flags;
+
+        /* clean all ways */
+        spin_lock_irqsave(&l2x0_lock, flags);
+        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
+        cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
+        cache_sync();
+        spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
+static void l2x0_inv_all(void)
 {
         unsigned long flags;
 
         /* invalidate all ways */
         spin_lock_irqsave(&l2x0_lock, flags);
+        /* Invalidating when L2 is enabled is a nono */
+        BUG_ON(readl(l2x0_base + L2X0_CTRL) & 1);
         writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
-        cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+        cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
         cache_sync();
         spin_unlock_irqrestore(&l2x0_lock, flags);
 }
@@ -159,6 +195,11 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
         void __iomem *base = l2x0_base;
         unsigned long flags;
 
+        if ((end - start) >= l2x0_size) {
+                l2x0_clean_all();
+                return;
+        }
+
         spin_lock_irqsave(&l2x0_lock, flags);
         start &= ~(CACHE_LINE_SIZE - 1);
         while (start < end) {
@@ -184,6 +225,11 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
         void __iomem *base = l2x0_base;
         unsigned long flags;
 
+        if ((end - start) >= l2x0_size) {
+                l2x0_flush_all();
+                return;
+        }
+
         spin_lock_irqsave(&l2x0_lock, flags);
         start &= ~(CACHE_LINE_SIZE - 1);
         while (start < end) {
@@ -206,10 +252,20 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
         spin_unlock_irqrestore(&l2x0_lock, flags);
 }
 
+static void l2x0_disable(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&l2x0_lock, flags);
+        writel(0, l2x0_base + L2X0_CTRL);
+        spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 {
         __u32 aux;
         __u32 cache_id;
+        __u32 way_size = 0;
         int ways;
         const char *type;
 
@@ -244,6 +300,13 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
         l2x0_way_mask = (1 << ways) - 1;
 
         /*
+         * L2 cache Size =  Way size * Number of ways
+         */
+        way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
+        way_size = 1 << (way_size + 3);
+        l2x0_size = ways * way_size * SZ_1K;
+
+        /*
          * Check if l2x0 controller is already enabled.
          * If you are booting from non-secure mode
          * accessing the below registers will fault.
@@ -263,8 +326,11 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
         outer_cache.clean_range = l2x0_clean_range;
         outer_cache.flush_range = l2x0_flush_range;
         outer_cache.sync = l2x0_cache_sync;
+        outer_cache.flush_all = l2x0_flush_all;
+        outer_cache.inv_all = l2x0_inv_all;
+        outer_cache.disable = l2x0_disable;
 
         printk(KERN_INFO "%s cache controller enabled\n", type);
-        printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
-                         ways, cache_id, aux);
+        printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
+                        ways, cache_id, aux, l2x0_size);
 }
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index c2ff3c599fee..2e2bc406a18d 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -13,6 +13,15 @@
 #include "proc-macros.S"
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v3_flush_icache_all)
+        mov     pc, lr
+ENDPROC(v3_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Invalidate all cache entries in a particular address
@@ -122,6 +131,7 @@ ENDPROC(v3_dma_map_area)
 
         .type   v3_cache_fns, #object
 ENTRY(v3_cache_fns)
+        .long   v3_flush_icache_all
         .long   v3_flush_kern_cache_all
         .long   v3_flush_user_cache_all
         .long   v3_flush_user_cache_range
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 4810f7e3e813..a8fefb523f19 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -13,6 +13,15 @@
 #include "proc-macros.S"
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v4_flush_icache_all)
+        mov     pc, lr
+ENDPROC(v4_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Invalidate all cache entries in a particular address
@@ -134,6 +143,7 @@ ENDPROC(v4_dma_map_area)
 
         .type   v4_cache_fns, #object
 ENTRY(v4_cache_fns)
+        .long   v4_flush_icache_all
         .long   v4_flush_kern_cache_all
         .long   v4_flush_user_cache_all
         .long   v4_flush_user_cache_range
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index df8368afa102..d3644db467b7 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -51,6 +51,17 @@ flush_base:
         .text
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v4wb_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(v4wb_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Clean and invalidate all cache entries in a particular address
@@ -244,6 +255,7 @@ ENDPROC(v4wb_dma_unmap_area)
 
         .type   v4wb_cache_fns, #object
 ENTRY(v4wb_cache_fns)
+        .long   v4wb_flush_icache_all
         .long   v4wb_flush_kern_cache_all
         .long   v4wb_flush_user_cache_all
         .long   v4wb_flush_user_cache_range
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 45c70312f43b..49c2b66cf3dd 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -41,6 +41,17 @@
 #define CACHE_DLIMIT    16384
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(v4wt_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(v4wt_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Invalidate all cache entries in a particular address
@@ -188,6 +199,7 @@ ENDPROC(v4wt_dma_map_area)
 
         .type   v4wt_cache_fns, #object
 ENTRY(v4wt_cache_fns)
+        .long   v4wt_flush_icache_all
         .long   v4wt_flush_kern_cache_all
         .long   v4wt_flush_user_cache_all
         .long   v4wt_flush_user_cache_range
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index e4dd0646e859..ac6a36142fcd 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -198,7 +198,7 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
          * fragmentation of the DMA space, and also prevents allocations
          * smaller than a section from crossing a section boundary.
          */
-        bit = fls(size - 1) + 1;
+        bit = fls(size - 1);
         if (bit > SECTION_SHIFT)
                 bit = SECTION_SHIFT;
         align = 1 << bit;
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index c493d7244d3d..83e59f870426 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -66,6 +66,30 @@ static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
         return ret;
 }
 
+#if USE_SPLIT_PTLOCKS
+/*
+ * If we are using split PTE locks, then we need to take the page
+ * lock here.  Otherwise we are using shared mm->page_table_lock
+ * which is already locked, thus cannot take it.
+ */
+static inline void do_pte_lock(spinlock_t *ptl)
+{
+        /*
+         * Use nested version here to indicate that we are already
+         * holding one similar spinlock.
+         */
+        spin_lock_nested(ptl, SINGLE_DEPTH_NESTING);
+}
+
+static inline void do_pte_unlock(spinlock_t *ptl)
+{
+        spin_unlock(ptl);
+}
+#else /* !USE_SPLIT_PTLOCKS */
+static inline void do_pte_lock(spinlock_t *ptl) {}
+static inline void do_pte_unlock(spinlock_t *ptl) {}
+#endif /* USE_SPLIT_PTLOCKS */
+
 static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
         unsigned long pfn)
 {
@@ -90,11 +114,11 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
          */
         ptl = pte_lockptr(vma->vm_mm, pmd);
         pte = pte_offset_map(pmd, address);
-        spin_lock(ptl);
+        do_pte_lock(ptl);
 
         ret = do_adjust_pte(vma, address, pfn, pte);
 
-        spin_unlock(ptl);
+        do_pte_unlock(ptl);
         pte_unmap(pte);
 
         return ret;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 7fd9b5eb177f..5164069ced42 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -18,6 +18,7 @@
 #include <linux/highmem.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
+#include <linux/sort.h>
 
 #include <asm/mach-types.h>
 #include <asm/sections.h>
@@ -121,9 +122,10 @@ void show_mem(void)
         printk("%d pages swap cached\n", cached);
 }
 
-static void __init find_limits(struct meminfo *mi,
-        unsigned long *min, unsigned long *max_low, unsigned long *max_high)
+static void __init find_limits(unsigned long *min, unsigned long *max_low,
+        unsigned long *max_high)
 {
+        struct meminfo *mi = &meminfo;
         int i;
 
         *min = -1UL;
@@ -147,14 +149,13 @@ static void __init find_limits(struct meminfo *mi,
         }
 }
 
-static void __init arm_bootmem_init(struct meminfo *mi,
-        unsigned long start_pfn, unsigned long end_pfn)
+static void __init arm_bootmem_init(unsigned long start_pfn,
+        unsigned long end_pfn)
 {
         struct memblock_region *reg;
         unsigned int boot_pages;
         phys_addr_t bitmap;
         pg_data_t *pgdat;
-        int i;
 
         /*
          * Allocate the bootmem bitmap page.  This must be in a region
@@ -172,30 +173,39 @@ static void __init arm_bootmem_init(struct meminfo *mi,
         pgdat = NODE_DATA(0);
         init_bootmem_node(pgdat, __phys_to_pfn(bitmap), start_pfn, end_pfn);
 
-        for_each_bank(i, mi) {
-                struct membank *bank = &mi->bank[i];
-                if (!bank->highmem)
-                        free_bootmem(bank_phys_start(bank), bank_phys_size(bank));
+        /* Free the lowmem regions from memblock into bootmem. */
+        for_each_memblock(memory, reg) {
+                unsigned long start = memblock_region_memory_base_pfn(reg);
+                unsigned long end = memblock_region_memory_end_pfn(reg);
+
+                if (end >= end_pfn)
+                        end = end_pfn;
+                if (start >= end)
+                        break;
+
+                free_bootmem(__pfn_to_phys(start), (end - start) << PAGE_SHIFT);
         }
 
-        /*
-         * Reserve the memblock reserved regions in bootmem.
-         */
+        /* Reserve the lowmem memblock reserved regions in bootmem. */
         for_each_memblock(reserved, reg) {
-                phys_addr_t start = memblock_region_reserved_base_pfn(reg);
-                phys_addr_t end = memblock_region_reserved_end_pfn(reg);
-                if (start >= start_pfn && end <= end_pfn)
-                        reserve_bootmem_node(pgdat, __pfn_to_phys(start),
-                                             (end - start) << PAGE_SHIFT,
-                                             BOOTMEM_DEFAULT);
+                unsigned long start = memblock_region_reserved_base_pfn(reg);
+                unsigned long end = memblock_region_reserved_end_pfn(reg);
+
+                if (end >= end_pfn)
+                        end = end_pfn;
+                if (start >= end)
+                        break;
+
+                reserve_bootmem(__pfn_to_phys(start),
+                                (end - start) << PAGE_SHIFT, BOOTMEM_DEFAULT);
         }
 }
 
-static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min,
-        unsigned long max_low, unsigned long max_high)
+static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
+        unsigned long max_high)
 {
         unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
-        int i;
+        struct memblock_region *reg;
 
         /*
          * initialise the zones.
@@ -217,13 +227,20 @@ static void __init arm_bootmem_free(struct meminfo *mi, unsigned long min,
          *  holes = node_size - sum(bank_sizes)
          */
         memcpy(zhole_size, zone_size, sizeof(zhole_size));
-        for_each_bank(i, mi) {
-                int idx = 0;
+        for_each_memblock(memory, reg) {
+                unsigned long start = memblock_region_memory_base_pfn(reg);
+                unsigned long end = memblock_region_memory_end_pfn(reg);
+
+                if (start < max_low) {
+                        unsigned long low_end = min(end, max_low);
+                        zhole_size[0] -= low_end - start;
+                }
 #ifdef CONFIG_HIGHMEM
-                if (mi->bank[i].highmem)
-                        idx = ZONE_HIGHMEM;
+                if (end > max_low) {
+                        unsigned long high_start = max(start, max_low);
+                        zhole_size[ZONE_HIGHMEM] -= end - high_start;
+                }
 #endif
-                zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
         }
 
         /*
@@ -256,10 +273,19 @@ static void arm_memory_present(void)
 }
 #endif
 
+static int __init meminfo_cmp(const void *_a, const void *_b)
+{
+        const struct membank *a = _a, *b = _b;
+        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
+        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+}
+
 void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 {
         int i;
 
+        sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
+
         memblock_init();
         for (i = 0; i < mi->nr_banks; i++)
                 memblock_add(mi->bank[i].start, mi->bank[i].size);
@@ -292,14 +318,13 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 
 void __init bootmem_init(void)
 {
-        struct meminfo *mi = &meminfo;
         unsigned long min, max_low, max_high;
 
         max_low = max_high = 0;
 
-        find_limits(mi, &min, &max_low, &max_high);
+        find_limits(&min, &max_low, &max_high);
 
-        arm_bootmem_init(mi, min, max_low);
+        arm_bootmem_init(min, max_low);
 
         /*
          * Sparsemem tries to allocate bootmem in memory_present(),
@@ -317,7 +342,7 @@ void __init bootmem_init(void)
          * the sparse mem_map arrays initialized by sparse_init()
          * for memmap_init_zone(), otherwise all PFNs are invalid.
          */
-        arm_bootmem_free(mi, min, max_low, max_high);
+        arm_bootmem_free(min, max_low, max_high);
 
         high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
 
@@ -411,6 +436,56 @@ static void __init free_unused_memmap(struct meminfo *mi)
         }
 }
 
+static void __init free_highpages(void)
+{
+#ifdef CONFIG_HIGHMEM
+        unsigned long max_low = max_low_pfn + PHYS_PFN_OFFSET;
+        struct memblock_region *mem, *res;
+
+        /* set highmem page free */
+        for_each_memblock(memory, mem) {
+                unsigned long start = memblock_region_memory_base_pfn(mem);
+                unsigned long end = memblock_region_memory_end_pfn(mem);
+
+                /* Ignore complete lowmem entries */
+                if (end <= max_low)
+                        continue;
+
+                /* Truncate partial highmem entries */
+                if (start < max_low)
+                        start = max_low;
+
+                /* Find and exclude any reserved regions */
+                for_each_memblock(reserved, res) {
+                        unsigned long res_start, res_end;
+
+                        res_start = memblock_region_reserved_base_pfn(res);
+                        res_end = memblock_region_reserved_end_pfn(res);
+
+                        if (res_end < start)
+                                continue;
+                        if (res_start < start)
+                                res_start = start;
+                        if (res_start > end)
+                                res_start = end;
+                        if (res_end > end)
+                                res_end = end;
+                        if (res_start != start)
+                                totalhigh_pages += free_area(start, res_start,
+                                                             NULL);
+                        start = res_end;
+                        if (start == end)
+                                break;
+                }
+
+                /* And now free anything which remains */
+                if (start < end)
+                        totalhigh_pages += free_area(start, end, NULL);
+        }
+        totalram_pages += totalhigh_pages;
+#endif
+}
+
 /*
  * mem_init() marks the free areas in the mem_map and tells us how much
  * memory is free.  This is done after various parts of the system have
@@ -419,6 +494,7 @@ static void __init free_unused_memmap(struct meminfo *mi)
 void __init mem_init(void)
 {
         unsigned long reserved_pages, free_pages;
+        struct memblock_region *reg;
         int i;
 #ifdef CONFIG_HAVE_TCM
         /* These pointers are filled in on TCM detection */
@@ -439,16 +515,7 @@ void __init mem_init(void)
                                     __phys_to_pfn(__pa(swapper_pg_dir)), NULL);
 #endif
 
-#ifdef CONFIG_HIGHMEM
-        /* set highmem page free */
-        for_each_bank (i, &meminfo) {
-                unsigned long start = bank_pfn_start(&meminfo.bank[i]);
-                unsigned long end = bank_pfn_end(&meminfo.bank[i]);
-                if (start >= max_low_pfn + PHYS_PFN_OFFSET)
-                        totalhigh_pages += free_area(start, end, NULL);
-        }
-        totalram_pages += totalhigh_pages;
-#endif
+        free_highpages();
 
         reserved_pages = free_pages = 0;
 
@@ -478,9 +545,11 @@ void __init mem_init(void)
          */
         printk(KERN_INFO "Memory:");
         num_physpages = 0;
-        for (i = 0; i < meminfo.nr_banks; i++) {
-                num_physpages += bank_pfn_size(&meminfo.bank[i]);
-                printk(" %ldMB", bank_phys_size(&meminfo.bank[i]) >> 20);
+        for_each_memblock(memory, reg) {
+                unsigned long pages = memblock_region_memory_end_pfn(reg) -
+                        memblock_region_memory_base_pfn(reg);
+                num_physpages += pages;
+                printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
         }
         printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index c32f731d56d3..72ad3e1f56cf 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -14,7 +14,6 @@
 #include <linux/mman.h>
 #include <linux/nodemask.h>
 #include <linux/memblock.h>
-#include <linux/sort.h>
 #include <linux/fs.h>
 
 #include <asm/cputype.h>
@@ -265,17 +264,17 @@ static struct mem_type mem_types[] = {
                 .domain    = DOMAIN_KERNEL,
         },
         [MT_MEMORY_DTCM] = {
-                .prot_pte       = L_PTE_PRESENT | L_PTE_YOUNG |
-                                  L_PTE_DIRTY | L_PTE_WRITE,
-                .prot_l1        = PMD_TYPE_TABLE,
-                .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
-                .domain         = DOMAIN_KERNEL,
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+                                L_PTE_WRITE,
+                .prot_l1   = PMD_TYPE_TABLE,
+                .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
+                .domain    = DOMAIN_KERNEL,
         },
         [MT_MEMORY_ITCM] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_USER | L_PTE_EXEC,
+                                L_PTE_WRITE | L_PTE_EXEC,
                 .prot_l1   = PMD_TYPE_TABLE,
-                .domain    = DOMAIN_IO,
+                .domain    = DOMAIN_KERNEL,
         },
 };
 
@@ -745,13 +744,14 @@ static int __init early_vmalloc(char *arg)
 }
 early_param("vmalloc", early_vmalloc);
 
-phys_addr_t lowmem_end_addr;
+static phys_addr_t lowmem_limit __initdata = 0;
 
 static void __init sanity_check_meminfo(void)
 {
         int i, j, highmem = 0;
 
-        lowmem_end_addr = __pa(vmalloc_min - 1) + 1;
+        lowmem_limit = __pa(vmalloc_min - 1) + 1;
+        memblock_set_current_limit(lowmem_limit);
 
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
@@ -852,6 +852,7 @@ static void __init sanity_check_meminfo(void)
 static inline void prepare_page_table(void)
 {
         unsigned long addr;
+        phys_addr_t end;
 
         /*
          * Clear out all the mappings below the kernel image.
@@ -867,10 +868,17 @@ static inline void prepare_page_table(void)
                 pmd_clear(pmd_off_k(addr));
 
         /*
+         * Find the end of the first block of lowmem.
+         */
+        end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
+        if (end >= lowmem_limit)
+                end = lowmem_limit;
+
+        /*
          * Clear out all the kernel space mappings, except for the first
          * memory bank, up to the end of the vmalloc region.
          */
-        for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
+        for (addr = __phys_to_virt(end);
              addr < VMALLOC_END; addr += PGDIR_SIZE)
                 pmd_clear(pmd_off_k(addr));
 }
@@ -987,37 +995,28 @@ static void __init kmap_init(void)
 #endif
 }
 
-static inline void map_memory_bank(struct membank *bank)
-{
-        struct map_desc map;
-
-        map.pfn = bank_pfn_start(bank);
-        map.virtual = __phys_to_virt(bank_phys_start(bank));
-        map.length = bank_phys_size(bank);
-        map.type = MT_MEMORY;
-
-        create_mapping(&map);
-}
-
 static void __init map_lowmem(void)
 {
-        struct meminfo *mi = &meminfo;
-        int i;
+        struct memblock_region *reg;
 
         /* Map all the lowmem memory banks. */
-        for (i = 0; i < mi->nr_banks; i++) {
-                struct membank *bank = &mi->bank[i];
+        for_each_memblock(memory, reg) {
+                phys_addr_t start = reg->base;
+                phys_addr_t end = start + reg->size;
+                struct map_desc map;
+
+                if (end > lowmem_limit)
+                        end = lowmem_limit;
+                if (start >= end)
+                        break;
 
-                if (!bank->highmem)
-                        map_memory_bank(bank);
-        }
-}
+                map.pfn = __phys_to_pfn(start);
+                map.virtual = __phys_to_virt(start);
+                map.length = end - start;
+                map.type = MT_MEMORY;
 
-static int __init meminfo_cmp(const void *_a, const void *_b)
-{
-        const struct membank *a = _a, *b = _b;
-        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
-        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+                create_mapping(&map);
+        }
 }
 
 /*
@@ -1028,8 +1027,6 @@ void __init paging_init(struct machine_desc *mdesc)
 {
         void *zero_page;
 
-        sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
-
         build_mem_type_table();
         sanity_check_meminfo();
         prepare_page_table();
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index a6f5f8475b96..bcf748d9f4e2 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -119,6 +119,20 @@ ENTRY(cpu_arm1020_do_idle)
 /* ================================= CACHE ================================ */
 
         .align  5
+
+/*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1020_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+#endif
+        mov     pc, lr
+ENDPROC(arm1020_flush_icache_all)
+
 /*
  *      flush_user_cache_all()
  *
@@ -351,6 +365,7 @@ ENTRY(arm1020_dma_unmap_area)
 ENDPROC(arm1020_dma_unmap_area)
 
 ENTRY(arm1020_cache_fns)
+        .long   arm1020_flush_icache_all
         .long   arm1020_flush_kern_cache_all
         .long   arm1020_flush_user_cache_all
         .long   arm1020_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index afc06b9c3133..ab7ec26657ea 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -119,6 +119,20 @@ ENTRY(cpu_arm1020e_do_idle)
 /* ================================= CACHE ================================ */
 
         .align  5
+
+/*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1020e_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+#endif
+        mov     pc, lr
+ENDPROC(arm1020e_flush_icache_all)
+
 /*
  *      flush_user_cache_all()
  *
@@ -337,6 +351,7 @@ ENTRY(arm1020e_dma_unmap_area)
 ENDPROC(arm1020e_dma_unmap_area)
 
 ENTRY(arm1020e_cache_fns)
+        .long   arm1020e_flush_icache_all
         .long   arm1020e_flush_kern_cache_all
         .long   arm1020e_flush_user_cache_all
         .long   arm1020e_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 8915e0ba3fe5..831c5e54e22f 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -108,6 +108,20 @@ ENTRY(cpu_arm1022_do_idle)
 /* ================================= CACHE ================================ */
 
         .align  5
+
+/*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1022_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+#endif
+        mov     pc, lr
+ENDPROC(arm1022_flush_icache_all)
+
 /*
  *      flush_user_cache_all()
  *
@@ -326,6 +340,7 @@ ENTRY(arm1022_dma_unmap_area)
 ENDPROC(arm1022_dma_unmap_area)
 
 ENTRY(arm1022_cache_fns)
+        .long   arm1022_flush_icache_all
         .long   arm1022_flush_kern_cache_all
         .long   arm1022_flush_user_cache_all
         .long   arm1022_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index ff446c5d476f..e3f7e9a166bf 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -108,6 +108,20 @@ ENTRY(cpu_arm1026_do_idle)
 /* ================================= CACHE ================================ */
 
         .align  5
+
+/*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm1026_flush_icache_all)
+#ifndef CONFIG_CPU_ICACHE_DISABLE
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+#endif
+        mov     pc, lr
+ENDPROC(arm1026_flush_icache_all)
+
 /*
  *      flush_user_cache_all()
  *
@@ -320,6 +334,7 @@ ENTRY(arm1026_dma_unmap_area)
 ENDPROC(arm1026_dma_unmap_area)
 
 ENTRY(arm1026_cache_fns)
+        .long   arm1026_flush_icache_all
         .long   arm1026_flush_kern_cache_all
         .long   arm1026_flush_user_cache_all
         .long   arm1026_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index fecf570939f3..6109f278a904 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -110,6 +110,17 @@ ENTRY(cpu_arm920_do_idle)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm920_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(arm920_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Invalidate all cache entries in a particular address
@@ -305,6 +316,7 @@ ENTRY(arm920_dma_unmap_area)
 ENDPROC(arm920_dma_unmap_area)
 
 ENTRY(arm920_cache_fns)
+        .long   arm920_flush_icache_all
         .long   arm920_flush_kern_cache_all
         .long   arm920_flush_user_cache_all
         .long   arm920_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index e3cbf87c9480..bb2f0f46a5e6 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -112,6 +112,17 @@ ENTRY(cpu_arm922_do_idle)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm922_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(arm922_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Clean and invalidate all cache entries in a particular
@@ -307,6 +318,7 @@ ENTRY(arm922_dma_unmap_area)
 ENDPROC(arm922_dma_unmap_area)
 
 ENTRY(arm922_cache_fns)
+        .long   arm922_flush_icache_all
         .long   arm922_flush_kern_cache_all
         .long   arm922_flush_user_cache_all
         .long   arm922_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 572424c867b5..c13e01accfe2 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -145,6 +145,17 @@ ENTRY(cpu_arm925_do_idle)
         mov     pc, lr
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm925_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(arm925_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Clean and invalidate all cache entries in a particular
@@ -362,6 +373,7 @@ ENTRY(arm925_dma_unmap_area)
 ENDPROC(arm925_dma_unmap_area)
 
 ENTRY(arm925_cache_fns)
+        .long   arm925_flush_icache_all
         .long   arm925_flush_kern_cache_all
         .long   arm925_flush_user_cache_all
         .long   arm925_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 63d168b4ebe6..42eb4315740b 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -111,6 +111,17 @@ ENTRY(cpu_arm926_do_idle)
         mov     pc, lr
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm926_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(arm926_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Clean and invalidate all cache entries in a particular
@@ -325,6 +336,7 @@ ENTRY(arm926_dma_unmap_area)
 ENDPROC(arm926_dma_unmap_area)
 
 ENTRY(arm926_cache_fns)
+        .long   arm926_flush_icache_all
         .long   arm926_flush_kern_cache_all
         .long   arm926_flush_user_cache_all
         .long   arm926_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index f6a62822418e..7b11cdb9935f 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -68,6 +68,17 @@ ENTRY(cpu_arm940_do_idle)
         mov     pc, lr
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm940_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(arm940_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  */
 ENTRY(arm940_flush_user_cache_all)
@@ -254,6 +265,7 @@ ENTRY(arm940_dma_unmap_area)
 ENDPROC(arm940_dma_unmap_area)
 
 ENTRY(arm940_cache_fns)
+        .long   arm940_flush_icache_all
         .long   arm940_flush_kern_cache_all
         .long   arm940_flush_user_cache_all
         .long   arm940_flush_user_cache_range
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index ea2e7f2eb95b..1a5bbf080342 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -75,6 +75,17 @@ ENTRY(cpu_arm946_do_idle)
         mov     pc, lr
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(arm946_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(arm946_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  */
 ENTRY(arm946_flush_user_cache_all)
@@ -296,6 +307,7 @@ ENTRY(arm946_dma_unmap_area)
 ENDPROC(arm946_dma_unmap_area)
 
 ENTRY(arm946_cache_fns)
+        .long   arm946_flush_icache_all
         .long   arm946_flush_kern_cache_all
         .long   arm946_flush_user_cache_all
         .long   arm946_flush_user_cache_range
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 578da69200cf..b4597edbff97 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -124,6 +124,17 @@ ENTRY(cpu_feroceon_do_idle)
         mov     pc, lr
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(feroceon_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(feroceon_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Clean and invalidate all cache entries in a particular
@@ -401,6 +412,7 @@ ENTRY(feroceon_dma_unmap_area)
 ENDPROC(feroceon_dma_unmap_area)
 
 ENTRY(feroceon_cache_fns)
+        .long   feroceon_flush_icache_all
         .long   feroceon_flush_kern_cache_all
         .long   feroceon_flush_user_cache_all
         .long   feroceon_flush_user_cache_range
@@ -412,6 +424,7 @@ ENTRY(feroceon_cache_fns)
         .long   feroceon_dma_flush_range
 
 ENTRY(feroceon_range_cache_fns)
+        .long   feroceon_flush_icache_all
         .long   feroceon_flush_kern_cache_all
         .long   feroceon_flush_user_cache_all
         .long   feroceon_flush_user_cache_range
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index cad07e403044..ec26355cb7c2 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -141,6 +141,17 @@ ENTRY(cpu_xsc3_do_idle)
 /* ================================= CACHE ================================ */
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(xsc3_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(xsc3_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Invalidate all cache entries in a particular address
@@ -325,6 +336,7 @@ ENTRY(xsc3_dma_unmap_area)
 ENDPROC(xsc3_dma_unmap_area)
 
 ENTRY(xsc3_cache_fns)
+        .long   xsc3_flush_icache_all
         .long   xsc3_flush_kern_cache_all
         .long   xsc3_flush_user_cache_all
         .long   xsc3_flush_user_cache_range
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index cb245edb2c2b..523408c0bb38 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -181,6 +181,17 @@ ENTRY(cpu_xscale_do_idle)
 /* ================================= CACHE ================================ */
 
 /*
+ *      flush_icache_all()
+ *
+ *      Unconditionally clean and invalidate the entire icache.
+ */
+ENTRY(xscale_flush_icache_all)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
+        mov     pc, lr
+ENDPROC(xscale_flush_icache_all)
+
+/*
  *      flush_user_cache_all()
  *
  *      Invalidate all cache entries in a particular address
@@ -397,6 +408,7 @@ ENTRY(xscale_dma_unmap_area)
 ENDPROC(xscale_dma_unmap_area)
 
 ENTRY(xscale_cache_fns)
+        .long   xscale_flush_icache_all
         .long   xscale_flush_kern_cache_all
         .long   xscale_flush_user_cache_all
         .long   xscale_flush_user_cache_range
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 06875b4dd70f..372670952789 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
+obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
new file mode 100644
index 000000000000..039538e68793
--- /dev/null
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
+ * The CPUFREQ driver is for controling CPU frequency. It allows you to change
+ * the CPU clock speed on the fly.
+ */
+
+#include <linux/cpufreq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <mach/hardware.h>
+#include <mach/clock.h>
+
+#define CLK32_FREQ      32768
+#define NANOSECOND      (1000 * 1000 * 1000)
+
+struct cpu_op *(*get_cpu_op)(int *op);
+
+static int cpu_freq_khz_min;
+static int cpu_freq_khz_max;
+
+static struct clk *cpu_clk;
+static struct cpufreq_frequency_table *imx_freq_table;
+
+static int cpu_op_nr;
+static struct cpu_op *cpu_op_tbl;
+
+static int set_cpu_freq(int freq)
+{
+        int ret = 0;
+        int org_cpu_rate;
+
+        org_cpu_rate = clk_get_rate(cpu_clk);
+        if (org_cpu_rate == freq)
+                return ret;
+
+        ret = clk_set_rate(cpu_clk, freq);
+        if (ret != 0) {
+                printk(KERN_DEBUG "cannot set CPU clock rate\n");
+                return ret;
+        }
+
+        return ret;
+}
+
+static int mxc_verify_speed(struct cpufreq_policy *policy)
+{
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        return cpufreq_frequency_table_verify(policy, imx_freq_table);
+}
+
+static unsigned int mxc_get_speed(unsigned int cpu)
+{
+        if (cpu)
+                return 0;
+
+        return clk_get_rate(cpu_clk) / 1000;
+}
+
+static int mxc_set_target(struct cpufreq_policy *policy,
+                          unsigned int target_freq, unsigned int relation)
+{
+        struct cpufreq_freqs freqs;
+        int freq_Hz;
+        int ret = 0;
+        unsigned int index;
+
+        cpufreq_frequency_table_target(policy, imx_freq_table,
+                        target_freq, relation, &index);
+        freq_Hz = imx_freq_table[index].frequency * 1000;
+
+        freqs.old = clk_get_rate(cpu_clk) / 1000;
+        freqs.new = freq_Hz / 1000;
+        freqs.cpu = 0;
+        freqs.flags = 0;
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        ret = set_cpu_freq(freq_Hz);
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        return ret;
+}
+
+static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
+{
+        int ret;
+        int i;
+
+        printk(KERN_INFO "i.MXC CPU frequency driver\n");
+
+        if (policy->cpu != 0)
+                return -EINVAL;
+
+        if (!get_cpu_op)
+                return -EINVAL;
+
+        cpu_clk = clk_get(NULL, "cpu_clk");
+        if (IS_ERR(cpu_clk)) {
+                printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
+                return PTR_ERR(cpu_clk);
+        }
+
+        cpu_op_tbl = get_cpu_op(&cpu_op_nr);
+
+        cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
+        cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
+
+        imx_freq_table = kmalloc(
+                sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
+                        GFP_KERNEL);
+        if (!imx_freq_table) {
+                ret = -ENOMEM;
+                goto err1;
+        }
+
+        for (i = 0; i < cpu_op_nr; i++) {
+                imx_freq_table[i].index = i;
+                imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
+
+                if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
+                        cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
+
+                if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
+                        cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
+        }
+
+        imx_freq_table[i].index = i;
+        imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+        policy->cur = clk_get_rate(cpu_clk) / 1000;
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+        policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
+        policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
+
+        /* Manual states, that PLL stabilizes in two CLK32 periods */
+        policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
+
+        ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
+
+        if (ret < 0) {
+                printk(KERN_ERR "%s: failed to register i.MXC CPUfreq \
+                                with error code %d\n", __func__, ret);
+                goto err;
+        }
+
+        cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
+        return 0;
+err:
+        kfree(imx_freq_table);
+err1:
+        clk_put(cpu_clk);
+        return ret;
+}
+
+static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
+{
+        cpufreq_frequency_table_put_attr(policy->cpu);
+
+        set_cpu_freq(cpu_freq_khz_max * 1000);
+        clk_put(cpu_clk);
+        kfree(imx_freq_table);
+        return 0;
+}
+
+static struct cpufreq_driver mxc_driver = {
+        .flags = CPUFREQ_STICKY,
+        .verify = mxc_verify_speed,
+        .target = mxc_set_target,
+        .get = mxc_get_speed,
+        .init = mxc_cpufreq_init,
+        .exit = mxc_cpufreq_exit,
+        .name = "imx",
+};
+
+static int __devinit mxc_cpufreq_driver_init(void)
+{
+        return cpufreq_register_driver(&mxc_driver);
+}
+
+static void mxc_cpufreq_driver_exit(void)
+{
+        cpufreq_unregister_driver(&mxc_driver);
+}
+
+module_init(mxc_cpufreq_driver_init);
+module_exit(mxc_cpufreq_driver_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
+MODULE_DESCRIPTION("CPUfreq driver for i.MX");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 404799487f17..9aa6f3ea9012 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -6,9 +6,13 @@ config IMX_HAVE_PLATFORM_FEC
         default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
 
 config IMX_HAVE_PLATFORM_FLEXCAN
-        select HAVE_CAN_FLEXCAN
+        select HAVE_CAN_FLEXCAN if CAN
         bool
 
+config IMX_HAVE_PLATFORM_GPIO_KEYS
+        bool
+        default y if ARCH_MX51
+        
 config IMX_HAVE_PLATFORM_IMX_I2C
         bool
 
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 0a3c1f089413..45aefeb283ba 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,6 +1,7 @@
 obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
 obj-y += platform-imx-dma.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
diff --git a/arch/arm/plat-mxc/devices/platform-gpio_keys.c b/arch/arm/plat-mxc/devices/platform-gpio_keys.c
new file mode 100644
index 000000000000..1c53a532ea0e
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-gpio_keys.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_gpio_keys(
+                const struct gpio_keys_platform_data *pdata)
+{
+        return imx_add_platform_device("gpio-keys", -1, NULL,
+                 0, pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 9d38da077edb..9c3e36232b5b 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -20,6 +20,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
@@ -201,11 +202,42 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
         }
 }
 
+/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param  irq          interrupt source number
+ * @param  enable       enable as wake-up if equal to non-zero
+ * @return       This function returns 0 on success.
+ */
+static int gpio_set_wake_irq(u32 irq, u32 enable)
+{
+        u32 gpio = irq_to_gpio(irq);
+        u32 gpio_idx = gpio & 0x1F;
+        struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
+
+        if (enable) {
+                if (port->irq_high && (gpio_idx >= 16))
+                        enable_irq_wake(port->irq_high);
+                else
+                        enable_irq_wake(port->irq);
+        } else {
+                if (port->irq_high && (gpio_idx >= 16))
+                        disable_irq_wake(port->irq_high);
+                else
+                        disable_irq_wake(port->irq);
+        }
+
+        return 0;
+}
+
 static struct irq_chip gpio_irq_chip = {
         .ack = gpio_ack_irq,
         .mask = gpio_mask_irq,
         .unmask = gpio_unmask_irq,
         .set_type = gpio_set_irq_type,
+        .set_wake = gpio_set_wake_irq,
 };
 
 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 86d7575a564d..8c6896fd1e5f 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -29,6 +29,10 @@ struct platform_device *__init imx_add_flexcan(int id,
                 resource_size_t irq,
                 const struct flexcan_platform_data *pdata);
 
+#include <linux/gpio_keys.h>
+struct platform_device *__init imx_add_gpio_keys(
+                const struct gpio_keys_platform_data *pdata);
+
 #include <mach/i2c.h>
 struct imx_imx_i2c_data {
         int id;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index e46b1c2836d4..d7a41e9a2605 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -45,6 +45,8 @@ typedef enum iomux_config {
                                 PAD_CTL_PKE | PAD_CTL_HYS)
 #define MX51_GPIO_PAD_CTRL              (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
                                 PAD_CTL_SRE_FAST)
+#define MX51_GPIO_PAD_CTRL_2    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+                                        PAD_CTL_PUS_100K_UP)
 #define MX51_ECSPI_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
                                 PAD_CTL_SRE_FAST)
 #define MX51_SDHCI_PAD_CTRL     (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 03e2afabc9fc..61cfe827498b 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -240,7 +240,6 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
 #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
 #define MXC_INT_FIRI MX31_INT_FIRI
-#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
 #define MXC_INT_MBX MX31_INT_MBX
 #define MXC_INT_CSPI3 MX31_INT_CSPI3
 #define MXC_INT_SIM2 MX31_INT_SIM2
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index ff905cb32458..6267cff6035d 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -197,8 +197,6 @@
 /* these should go away */
 #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
 #define MXC_INT_OWIRE MX35_INT_OWIRE
-#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
-#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
 #define MXC_INT_GPU2D MX35_INT_GPU2D
 #define MXC_INT_ASRC MX35_INT_ASRC
 #define MXC_INT_USBHS MX35_INT_USBHS
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a790bf212972..a42c7207082d 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
  * This program is free software; you can redistribute it and/or
@@ -20,6 +20,8 @@
 #ifndef __ASM_ARCH_MXC_H__
 #define __ASM_ARCH_MXC_H__
 
+#include <linux/types.h>
+
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #error "Do not include directly."
 #endif
@@ -133,6 +135,15 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mxc91231()      (0)
 #endif
 
+#ifndef __ASSEMBLY__
+
+struct cpu_op {
+        u32 cpu_rate;
+};
+
+extern struct cpu_op *(*get_cpu_op)(int *op);
+#endif
+
 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
 /* These are deprecated, use mx[23][157]_setup_weimcs instead. */
 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 221a675ebbae..f04731820301 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -19,6 +19,7 @@
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/vram.h>
+#include <plat/dsp.h>
 
 
 #define NO_LENGTH_CHECK 0xffffffff
@@ -64,4 +65,5 @@ void __init omap_reserve(void)
 {
         omapfb_reserve_sdram_memblock();
         omap_vram_reserve_sdram_memblock();
+        omap_dsp_reserve_sdram_memblock();
 }
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 1e2383eae638..fc819120978d 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/memblock.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -231,6 +232,77 @@ static void omap_init_uwire(void)
 static inline void omap_init_uwire(void) {}
 #endif
 
+/*-------------------------------------------------------------------------*/
+
+#if     defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
+
+static struct resource wdt_resources[] = {
+        {
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap_wdt_device = {
+        .name      = "omap_wdt",
+        .id          = -1,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
+        .resource       = wdt_resources,
+};
+
+static void omap_init_wdt(void)
+{
+        if (cpu_is_omap16xx())
+                wdt_resources[0].start = 0xfffeb000;
+        else if (cpu_is_omap2420())
+                wdt_resources[0].start = 0x48022000; /* WDT2 */
+        else if (cpu_is_omap2430())
+                wdt_resources[0].start = 0x49016000; /* WDT2 */
+        else if (cpu_is_omap343x())
+                wdt_resources[0].start = 0x48314000; /* WDT2 */
+        else if (cpu_is_omap44xx())
+                wdt_resources[0].start = 0x4a314000;
+        else
+                return;
+
+        wdt_resources[0].end = wdt_resources[0].start + 0x4f;
+
+        (void) platform_device_register(&omap_wdt_device);
+}
+#else
+static inline void omap_init_wdt(void) {}
+#endif
+
+#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
+
+static phys_addr_t omap_dsp_phys_mempool_base;
+
+void __init omap_dsp_reserve_sdram_memblock(void)
+{
+        phys_addr_t size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
+        phys_addr_t paddr;
+
+        if (!size)
+                return;
+
+        paddr = memblock_alloc(size, SZ_1M);
+        if (!paddr) {
+                pr_err("%s: failed to reserve %x bytes\n",
+                                __func__, size);
+                return;
+        }
+        memblock_free(paddr, size);
+        memblock_remove(paddr, size);
+
+        omap_dsp_phys_mempool_base = paddr;
+}
+
+phys_addr_t omap_dsp_get_mempool_base(void)
+{
+        return omap_dsp_phys_mempool_base;
+}
+EXPORT_SYMBOL(omap_dsp_get_mempool_base);
+#endif
+
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index f5c5b8da9a87..2c2826571d45 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1983,6 +1983,8 @@ static int omap2_dma_handle_ch(int ch)
 
         dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
         dma_write(1 << ch, IRQSTATUS_L0);
+        /* read back the register to flush the write */
+        dma_read(IRQSTATUS_L0);
 
         /* If the ch is not chained then chain_id will be -1 */
         if (dma_chan[ch].chain_id != -1) {
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
new file mode 100644
index 000000000000..9c604b390f9f
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -0,0 +1,31 @@
+#ifndef __OMAP_DSP_H__
+#define __OMAP_DSP_H__
+
+#include <linux/types.h>
+
+struct omap_dsp_platform_data {
+        void (*dsp_set_min_opp) (u8 opp_id);
+        u8 (*dsp_get_opp) (void);
+        void (*cpu_set_freq) (unsigned long f);
+        unsigned long (*cpu_get_freq) (void);
+        unsigned long mpu_speed[6];
+
+        /* functions to write and read PRCM registers */
+        void (*dsp_prm_write)(u32, s16 , u16);
+        u32 (*dsp_prm_read)(s16 , u16);
+        u32 (*dsp_prm_rmw_bits)(u32, u32, s16, s16);
+        void (*dsp_cm_write)(u32, s16 , u16);
+        u32 (*dsp_cm_read)(s16 , u16);
+        u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
+
+        phys_addr_t phys_mempool_base;
+        phys_addr_t phys_mempool_size;
+};
+
+#if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
+extern void omap_dsp_reserve_sdram_memblock(void);
+#else
+static inline void omap_dsp_reserve_sdram_memblock(void) { }
+#endif
+
+#endif
diff --git a/arch/arm/plat-orion/include/plat/pcie.h b/arch/arm/plat-orion/include/plat/pcie.h
index 3ebfef72b4e7..cc99163e73fd 100644
--- a/arch/arm/plat-orion/include/plat/pcie.h
+++ b/arch/arm/plat-orion/include/plat/pcie.h
@@ -11,12 +11,15 @@
 #ifndef __PLAT_PCIE_H
 #define __PLAT_PCIE_H
 
+struct pci_bus;
+
 u32 orion_pcie_dev_id(void __iomem *base);
 u32 orion_pcie_rev(void __iomem *base);
 int orion_pcie_link_up(void __iomem *base);
 int orion_pcie_x4_mode(void __iomem *base);
 int orion_pcie_get_local_bus_nr(void __iomem *base);
 void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
+void orion_pcie_reset(void __iomem *base);
 void orion_pcie_setup(void __iomem *base,
                       struct mbus_dram_target_info *dram);
 int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 779553a1595e..af2d733c50b5 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -182,11 +182,6 @@ void __init orion_pcie_setup(void __iomem *base,
         u32 mask;
 
         /*
-         * soft reset PCIe unit
-         */
-        orion_pcie_reset(base);
-
-        /*
          * Point PCIe unit MBUS decode windows to DRAM space.
          */
         orion_pcie_setup_wins(base, dram);
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 3478eae32d8a..01a8448e471c 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -30,15 +30,15 @@ struct pxa3xx_nand_cmdset {
 };
 
 struct pxa3xx_nand_flash {
-        const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
-        const struct pxa3xx_nand_cmdset *cmdset;
-
-        uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
-        uint32_t page_size;     /* Page size in bytes (PAGE_SZ) */
-        uint32_t flash_width;   /* Width of Flash memory (DWIDTH_M) */
-        uint32_t dfc_width;     /* Width of flash controller(DWIDTH_C) */
-        uint32_t num_blocks;    /* Number of physical blocks in Flash */
-        uint32_t chip_id;
+        uint32_t        chip_id;
+        unsigned int    page_per_block; /* Pages per block (PG_PER_BLK) */
+        unsigned int    page_size;      /* Page size in bytes (PAGE_SZ) */
+        unsigned int    flash_width;    /* Width of Flash memory (DWIDTH_M) */
+        unsigned int    dfc_width;      /* Width of flash controller(DWIDTH_C) */
+        unsigned int    num_blocks;     /* Number of physical blocks in Flash */
+
+        struct pxa3xx_nand_cmdset *cmdset;      /* NAND command set */
+        struct pxa3xx_nand_timing *timing;      /* NAND Flash timing */
 };
 
 struct pxa3xx_nand_platform_data {
diff --git a/arch/arm/plat-pxa/include/plat/sdhci.h b/arch/arm/plat-pxa/include/plat/sdhci.h
new file mode 100644
index 000000000000..e49c5b6fc4e2
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/sdhci.h
@@ -0,0 +1,32 @@
+/* linux/arch/arm/plat-pxa/include/plat/sdhci.h
+ *
+ * Copyright 2010 Marvell
+ *      Zhangfei Gao <zhangfei.gao@marvell.com>
+ *
+ * PXA Platform - SDHCI platform data definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PLAT_PXA_SDHCI_H
+#define __PLAT_PXA_SDHCI_H
+
+/* pxa specific flag */
+/* Require clock free running */
+#define PXA_FLAG_DISABLE_CLOCK_GATING (1<<0)
+
+/*
+ * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
+ * @max_speed: the maximum speed supported
+ * @quirks: quirks of specific device
+ * @flags: flags for platform requirement
+ */
+struct sdhci_pxa_platdata {
+        unsigned int    max_speed;
+        unsigned int    quirks;
+        unsigned int    flags;
+};
+
+#endif /* __PLAT_PXA_SDHCI_H */
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 984bf66826d2..5a27b1b538f2 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -69,6 +69,7 @@ config S3C24XX_GPIO_EXTRA
         int
         default 128 if S3C24XX_GPIO_EXTRA128
         default 64 if S3C24XX_GPIO_EXTRA64
+        default 16 if ARCH_H1940
         default 0
 
 config S3C24XX_GPIO_EXTRA64
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 7b44d0c592b5..bcc43f346272 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -147,7 +147,7 @@ static struct mtd_partition smdk_default_nand_part[] = {
         [7] = {
                 .name   = "S3C2410 flash partition 7",
                 .offset = SZ_1M * 48,
-                .size   = SZ_16M,
+                .size   = MTDPART_SIZ_FULL,
         }
 };
 
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 4c0896f2572d..24c6f5a30596 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -74,11 +74,6 @@ static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
         return -EINVAL;
 }
 
-static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
-{
-        return IRQ_EINT8 + offset;
-}
-
 static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
         .set_config     = s3c_gpio_setcfg_s3c24xx_a,
         .get_config     = s3c_gpio_getcfg_s3c24xx_a,
@@ -87,6 +82,8 @@ static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
 struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
         .set_config     = s3c_gpio_setcfg_s3c24xx,
         .get_config     = s3c_gpio_getcfg_s3c24xx,
+        .set_pull       = s3c_gpio_setpull_1up,
+        .get_pull       = s3c_gpio_getpull_1up,
 };
 
 struct s3c_gpio_chip s3c24xx_gpios[] = {
@@ -157,12 +154,13 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
         [6] = {
                 .base   = S3C2410_GPGCON,
                 .pm     = __gpio_pm(&s3c_gpio_pm_2bit),
+                .irq_base = IRQ_EINT8,
                 .chip   = {
                         .base                   = S3C2410_GPG(0),
                         .owner                  = THIS_MODULE,
                         .label                  = "GPIOG",
                         .ngpio                  = 16,
-                        .to_irq                 = s3c24xx_gpiolib_bankg_toirq,
+                        .to_irq                 = samsung_gpiolib_to_irq,
                 },
         }, {
                 .base   = S3C2410_GPHCON,
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 25960966af7c..65dbfa8e0a86 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -32,6 +32,11 @@ config S5P_EXT_INT
           Use the external interrupts (other than GPIO interrupts.)
           Note: Do not choose this for S5P6440 and S5P6450.
 
+config S5P_GPIO_INT
+        bool
+        help
+          Common code for the GPIO interrupts (other than external interrupts.)
+
 config S5P_DEV_FIMC0
         bool
         help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index f3e917e27da8..de65238a7aef 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -18,6 +18,9 @@ obj-y				+= cpu.o
 obj-y                           += clock.o
 obj-y                           += irq.o
 obj-$(CONFIG_S5P_EXT_INT)       += irq-eint.o
+obj-$(CONFIG_S5P_GPIO_INT)      += irq-gpioint.o
+obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_PM)                += irq-pm.o
 
 # devices
 
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 8aaf4e6b60c3..8d081d968c58 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 #include <asm/div64.h>
 
+#include <mach/regs-clock.h>
+
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/s5p-clock.h>
@@ -88,14 +90,6 @@ struct clk clk_fout_vpll = {
         .ctrlbit        = (1 << 31),
 };
 
-/* ARM clock */
-struct clk clk_arm = {
-        .name           = "armclk",
-        .id             = -1,
-        .rate           = 0,
-        .ctrlbit        = 0,
-};
-
 /* Possible clock sources for APLL Mux */
 static struct clk *clk_src_apll_list[] = {
         [0] = &clk_fin_apll,
@@ -156,6 +150,24 @@ int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
         return 0;
 }
 
+int s5p_epll_enable(struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
+
+        if (enable)
+                __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
+        else
+                __raw_writel(epll_con, S5P_EPLL_CON);
+
+        return 0;
+}
+
+unsigned long s5p_epll_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+
 static struct clk *s5p_clks[] __initdata = {
         &clk_ext_xtal_mux,
         &clk_48m,
@@ -165,7 +177,6 @@ static struct clk *s5p_clks[] __initdata = {
         &clk_fout_epll,
         &clk_fout_dpll,
         &clk_fout_vpll,
-        &clk_arm,
         &clk_vpll,
         &clk_xusbxti,
 };
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index 3fb3a3a17465..ba9121c60a2a 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -94,4 +94,22 @@
                                                 ((irq) - S5P_EINT_BASE1) : \
                                                 ((irq) + 16 - S5P_EINT_BASE2))
 
+#define IRQ_EINT_BIT(x)         EINT_OFFSET(x)
+
+/* Typically only a few gpio chips require gpio interrupt support.
+   To avoid memory waste irq descriptors are allocated only for
+   S5P_GPIOINT_GROUP_COUNT chips, each with total number of
+   S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
+   to any gpio chip with the s5p_register_gpio_interrupt() function */
+#define S5P_GPIOINT_GROUP_COUNT 4
+#define S5P_GPIOINT_GROUP_SIZE  8
+#define S5P_GPIOINT_COUNT       (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
+
+/* IRQ types common for all s5p platforms */
+#define S5P_IRQ_TYPE_LEVEL_LOW          (0x00)
+#define S5P_IRQ_TYPE_LEVEL_HIGH         (0x01)
+#define S5P_IRQ_TYPE_EDGE_FALLING       (0x02)
+#define S5P_IRQ_TYPE_EDGE_RISING        (0x03)
+#define S5P_IRQ_TYPE_EDGE_BOTH          (0x04)
+
 #endif /* __ASM_PLAT_S5P_IRQS_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index c4ff88bf6477..fef353d44513 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -13,24 +13,38 @@
 #ifndef __ASM_PLAT_MAP_S5P_H
 #define __ASM_PLAT_MAP_S5P_H __FILE__
 
-#define S5P_VA_CHIPID           S3C_ADDR(0x00700000)
-#define S5P_VA_GPIO             S3C_ADDR(0x00500000)
-#define S5P_VA_SYSTIMER         S3C_ADDR(0x01200000)
-#define S5P_VA_SROMC            S3C_ADDR(0x01100000)
-#define S5P_VA_SYSRAM           S3C_ADDR(0x01180000)
-
-#define S5P_VA_COMBINER_BASE    S3C_ADDR(0x00600000)
+#define S5P_VA_CHIPID           S3C_ADDR(0x02000000)
+#define S5P_VA_CMU              S3C_ADDR(0x02100000)
+#define S5P_VA_GPIO             S3C_ADDR(0x02200000)
+#define S5P_VA_GPIO1            S5P_VA_GPIO
+#define S5P_VA_GPIO2            S3C_ADDR(0x02240000)
+#define S5P_VA_GPIO3            S3C_ADDR(0x02280000)
+
+#define S5P_VA_SYSRAM           S3C_ADDR(0x02400000)
+#define S5P_VA_DMC0             S3C_ADDR(0x02440000)
+#define S5P_VA_DMC1             S3C_ADDR(0x02480000)
+#define S5P_VA_SROMC            S3C_ADDR(0x024C0000)
+
+#define S5P_VA_SYSTIMER         S3C_ADDR(0x02500000)
+#define S5P_VA_L2CC             S3C_ADDR(0x02600000)
+
+#define S5P_VA_COMBINER_BASE    S3C_ADDR(0x02700000)
 #define S5P_VA_COMBINER(x)      (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
 
-#define S5P_VA_COREPERI_BASE    S3C_ADDR(0x00800000)
+#define S5P_VA_COREPERI_BASE    S3C_ADDR(0x02800000)
 #define S5P_VA_COREPERI(x)      (S5P_VA_COREPERI_BASE + (x))
 #define S5P_VA_SCU              S5P_VA_COREPERI(0x0)
 #define S5P_VA_GIC_CPU          S5P_VA_COREPERI(0x100)
 #define S5P_VA_TWD              S5P_VA_COREPERI(0x600)
 #define S5P_VA_GIC_DIST         S5P_VA_COREPERI(0x1000)
 
-#define S5P_VA_L2CC             S3C_ADDR(0x00900000)
-#define S5P_VA_CMU              S3C_ADDR(0x00920000)
+#define S3C_VA_USB_HSPHY        S3C_ADDR(0x02900000)
+
+#define VA_VIC(x)               (S3C_VA_IRQ + ((x) * 0x10000))
+#define VA_VIC0                 VA_VIC(0)
+#define VA_VIC1                 VA_VIC(1)
+#define VA_VIC2                 VA_VIC(2)
+#define VA_VIC3                 VA_VIC(3)
 
 #define S5P_VA_UART(x)          (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 #define S5P_VA_UART0            S5P_VA_UART(0)
@@ -42,10 +56,4 @@
 #define S3C_UART_OFFSET         (0x400)
 #endif
 
-#define VA_VIC(x)               (S3C_VA_IRQ + ((x) * 0x10000))
-#define VA_VIC0                 VA_VIC(0)
-#define VA_VIC1                 VA_VIC(1)
-#define VA_VIC2                 VA_VIC(2)
-#define VA_VIC3                 VA_VIC(3)
-
 #endif /* __ASM_PLAT_MAP_S5P_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 17036c898409..2b6dcff8ab2b 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -43,4 +43,8 @@ extern struct clksrc_sources clk_src_dpll;
 
 extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
 
+/* Common EPLL operations for S5P platform */
+extern int s5p_epll_enable(struct clk *clk, int enable);
+extern unsigned long s5p_epll_get_rate(struct clk *clk);
+
 #endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index f36cd3327025..752f1a645f9d 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -67,23 +67,23 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
 
         switch (type) {
         case IRQ_TYPE_EDGE_RISING:
-                newvalue = S5P_EXTINT_RISEEDGE;
+                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
                 break;
 
         case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S5P_EXTINT_FALLEDGE;
+                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
                 break;
 
         case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S5P_EXTINT_BOTHEDGE;
+                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
                 break;
 
         case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S5P_EXTINT_LOWLEV;
+                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
                 break;
 
         case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S5P_EXTINT_HILEV;
+                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
                 break;
 
         default:
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
new file mode 100644
index 000000000000..0e5dc8cbf5e3
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -0,0 +1,237 @@
+/* linux/arch/arm/plat-s5p/irq-gpioint.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Author: Kyungmin Park <kyungmin.park@samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ * Author: Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+
+#define S5P_GPIOREG(x)                  (S5P_VA_GPIO + (x))
+
+#define GPIOINT_CON_OFFSET              0x700
+#define GPIOINT_MASK_OFFSET             0x900
+#define GPIOINT_PEND_OFFSET             0xA00
+
+static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
+
+static int s5p_gpioint_get_group(unsigned int irq)
+{
+        struct gpio_chip *chip = get_irq_data(irq);
+        struct s3c_gpio_chip *s3c_chip = container_of(chip,
+                        struct s3c_gpio_chip, chip);
+        int group;
+
+        for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++)
+                if (s3c_chip == irq_chips[group])
+                        break;
+
+        return group;
+}
+
+static int s5p_gpioint_get_offset(unsigned int irq)
+{
+        struct gpio_chip *chip = get_irq_data(irq);
+        struct s3c_gpio_chip *s3c_chip = container_of(chip,
+                        struct s3c_gpio_chip, chip);
+
+        return irq - s3c_chip->irq_base;
+}
+
+static void s5p_gpioint_ack(unsigned int irq)
+{
+        int group, offset, pend_offset;
+        unsigned int value;
+
+        group = s5p_gpioint_get_group(irq);
+        offset = s5p_gpioint_get_offset(irq);
+        pend_offset = group << 2;
+
+        value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+}
+
+static void s5p_gpioint_mask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+
+        group = s5p_gpioint_get_group(irq);
+        offset = s5p_gpioint_get_offset(irq);
+        mask_offset = group << 2;
+
+        value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_unmask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+
+        group = s5p_gpioint_get_group(irq);
+        offset = s5p_gpioint_get_offset(irq);
+        mask_offset = group << 2;
+
+        value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+        value &= ~(1 << offset);
+        __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_mask_ack(unsigned int irq)
+{
+        s5p_gpioint_mask(irq);
+        s5p_gpioint_ack(irq);
+}
+
+static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
+{
+        int group, offset, con_offset;
+        unsigned int value;
+
+        group = s5p_gpioint_get_group(irq);
+        offset = s5p_gpioint_get_offset(irq);
+        con_offset = group << 2;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                type = S5P_IRQ_TYPE_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                type = S5P_IRQ_TYPE_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                type = S5P_IRQ_TYPE_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                type = S5P_IRQ_TYPE_LEVEL_HIGH;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                type = S5P_IRQ_TYPE_LEVEL_LOW;
+                break;
+        case IRQ_TYPE_NONE:
+        default:
+                printk(KERN_WARNING "No irq type\n");
+                return -EINVAL;
+        }
+
+        value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+        value &= ~(0x7 << (offset * 0x4));
+        value |= (type << (offset * 0x4));
+        __raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+
+        return 0;
+}
+
+struct irq_chip s5p_gpioint = {
+        .name           = "s5p_gpioint",
+        .ack            = s5p_gpioint_ack,
+        .mask           = s5p_gpioint_mask,
+        .mask_ack       = s5p_gpioint_mask_ack,
+        .unmask         = s5p_gpioint_unmask,
+        .set_type       = s5p_gpioint_set_type,
+};
+
+static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int group, offset, pend_offset, mask_offset;
+        int real_irq;
+        unsigned int pend, mask;
+
+        for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) {
+                pend_offset = group << 2;
+                pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) +
+                                pend_offset);
+                if (!pend)
+                        continue;
+
+                mask_offset = group << 2;
+                mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) +
+                                mask_offset);
+                pend &= ~mask;
+
+                for (offset = 0; offset < 8; offset++) {
+                        if (pend & (1 << offset)) {
+                                struct s3c_gpio_chip *chip = irq_chips[group];
+                                if (chip) {
+                                        real_irq = chip->irq_base + offset;
+                                        generic_handle_irq(real_irq);
+                                }
+                        }
+                }
+        }
+}
+
+static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
+{
+        static int used_gpioint_groups = 0;
+        static bool handler_registered = 0;
+        int irq, group = chip->group;
+        int i;
+
+        if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
+                return -ENOMEM;
+
+        chip->irq_base = S5P_GPIOINT_BASE +
+                         used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
+        used_gpioint_groups++;
+
+        if (!handler_registered) {
+                set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
+                handler_registered = 1;
+        }
+
+        irq_chips[group] = chip;
+        for (i = 0; i < chip->chip.ngpio; i++) {
+                irq = chip->irq_base + i;
+                set_irq_chip(irq, &s5p_gpioint);
+                set_irq_data(irq, &chip->chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        return 0;
+}
+
+int __init s5p_register_gpio_interrupt(int pin)
+{
+        struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
+        int offset, group;
+        int ret;
+
+        if (!my_chip)
+                return -EINVAL;
+
+        offset = pin - my_chip->chip.base;
+        group = my_chip->group;
+
+        /* check if the group has been already registered */
+        if (my_chip->irq_base)
+                return my_chip->irq_base + offset;
+
+        /* register gpio group */
+        ret = s5p_gpioint_add(my_chip);
+        if (ret == 0) {
+                my_chip->chip.to_irq = samsung_gpiolib_to_irq;
+                printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
+                       group);
+                return my_chip->irq_base + offset;
+        }
+        return ret;
+}
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
new file mode 100644
index 000000000000..dc33b9ecda45
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -0,0 +1,93 @@
+/* linux/arch/arm/plat-s5p/irq-pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Based on arch/arm/plat-s3c24xx/irq-pm.c,
+ * Copyright (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/sysdev.h>
+
+#include <plat/cpu.h>
+#include <plat/irqs.h>
+#include <plat/pm.h>
+#include <mach/map.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-irq.h>
+
+/* state for IRQs over sleep */
+
+/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
+ * as wakeup sources
+ *
+ * set bit to 1 in allow bitfield to enable the wakeup settings on it
+*/
+
+unsigned long s3c_irqwake_intallow      = 0x00000006L;
+unsigned long s3c_irqwake_eintallow     = 0xffffffffL;
+
+int s3c_irq_wake(unsigned int irqno, unsigned int state)
+{
+        unsigned long irqbit;
+
+        switch (irqno) {
+        case IRQ_RTC_TIC:
+        case IRQ_RTC_ALARM:
+                irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
+                if (!state)
+                        s3c_irqwake_intmask |= irqbit;
+                else
+                        s3c_irqwake_intmask &= ~irqbit;
+                break;
+        default:
+                return -ENOENT;
+        }
+        return 0;
+}
+
+static struct sleep_save eint_save[] = {
+        SAVE_ITEM(S5P_EINT_CON(0)),
+        SAVE_ITEM(S5P_EINT_CON(1)),
+        SAVE_ITEM(S5P_EINT_CON(2)),
+        SAVE_ITEM(S5P_EINT_CON(3)),
+
+        SAVE_ITEM(S5P_EINT_FLTCON(0)),
+        SAVE_ITEM(S5P_EINT_FLTCON(1)),
+        SAVE_ITEM(S5P_EINT_FLTCON(2)),
+        SAVE_ITEM(S5P_EINT_FLTCON(3)),
+        SAVE_ITEM(S5P_EINT_FLTCON(4)),
+        SAVE_ITEM(S5P_EINT_FLTCON(5)),
+        SAVE_ITEM(S5P_EINT_FLTCON(6)),
+        SAVE_ITEM(S5P_EINT_FLTCON(7)),
+
+        SAVE_ITEM(S5P_EINT_MASK(0)),
+        SAVE_ITEM(S5P_EINT_MASK(1)),
+        SAVE_ITEM(S5P_EINT_MASK(2)),
+        SAVE_ITEM(S5P_EINT_MASK(3)),
+};
+
+int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
+{
+        s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
+
+        return 0;
+}
+
+int s3c24xx_irq_resume(struct sys_device *dev)
+{
+        s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
+
+        return 0;
+}
+
diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
new file mode 100644
index 000000000000..d592b6304b48
--- /dev/null
+++ b/arch/arm/plat-s5p/pm.c
@@ -0,0 +1,52 @@
+/* linux/arch/arm/plat-s5p/pm.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * S5P Power Manager (Suspend-To-RAM) support
+ *
+ * Based on arch/arm/plat-s3c24xx/pm.c
+ * Copyright (c) 2004,2006 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/suspend.h>
+#include <plat/pm.h>
+
+#define PFX "s5p pm: "
+
+/* s3c_pm_check_resume_pin
+ *
+ * check to see if the pin is configured correctly for sleep mode, and
+ * make any necessary adjustments if it is not
+*/
+
+static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
+{
+        /* nothing here yet */
+}
+
+/* s3c_pm_configure_extint
+ *
+ * configure all external interrupt pins
+*/
+
+void s3c_pm_configure_extint(void)
+{
+        /* nothing here yet */
+}
+
+void s3c_pm_restore_core(void)
+{
+        /* nothing here yet */
+}
+
+void s3c_pm_save_core(void)
+{
+        /* nothing here yet */
+}
+
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 7c0bde781167..dcd6eff4ee53 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -180,6 +180,31 @@ config S3C_DEV_I2C2
         help
           Compile in platform device definitions for I2C channel 2
 
+config S3C_DEV_I2C3
+        bool
+        help
+          Compile in platform device definition for I2C controller 3
+
+config S3C_DEV_I2C4
+        bool
+        help
+          Compile in platform device definition for I2C controller 4
+
+config S3C_DEV_I2C5
+        bool
+        help
+          Compile in platform device definition for I2C controller 5
+
+config S3C_DEV_I2C6
+        bool
+        help
+          Compile in platform device definition for I2C controller 6
+
+config S3C_DEV_I2C7
+        bool
+        help
+          Compile in platform device definition for I2C controller 7
+
 config S3C_DEV_FB
         bool
         help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 4d8ff923207a..afcce474af8e 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -40,6 +40,11 @@ obj-$(CONFIG_S3C_DEV_HWMON)	+= dev-hwmon.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
 obj-$(CONFIG_S3C_DEV_I2C2)      += dev-i2c2.o
+obj-$(CONFIG_S3C_DEV_I2C3)      += dev-i2c3.o
+obj-$(CONFIG_S3C_DEV_I2C4)      += dev-i2c4.o
+obj-$(CONFIG_S3C_DEV_I2C5)      += dev-i2c5.o
+obj-$(CONFIG_S3C_DEV_I2C6)      += dev-i2c6.o
+obj-$(CONFIG_S3C_DEV_I2C7)      += dev-i2c7.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
 obj-y                           += dev-uart.o
 obj-$(CONFIG_S3C_DEV_USB_HOST)  += dev-usb.o
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 9d2be0941410..db7a65c7f127 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -41,6 +41,7 @@ struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
         .max_width      = 4,
         .host_caps      = (MMC_CAP_4_BIT_DATA |
                            MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc0 = {
@@ -59,17 +60,20 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 {
         struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
 
-        set->max_width = pd->max_width;
         set->cd_type = pd->cd_type;
         set->ext_cd_init = pd->ext_cd_init;
         set->ext_cd_cleanup = pd->ext_cd_cleanup;
         set->ext_cd_gpio = pd->ext_cd_gpio;
         set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+        if (pd->max_width)
+                set->max_width = pd->max_width;
         if (pd->cfg_gpio)
                 set->cfg_gpio = pd->cfg_gpio;
         if (pd->cfg_card)
                 set->cfg_card = pd->cfg_card;
         if (pd->host_caps)
-                set->host_caps = pd->host_caps;
+                set->host_caps |= pd->host_caps;
+        if (pd->clk_type)
+                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index a6c8295840af..2497321f08d7 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -41,6 +41,7 @@ struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
         .max_width      = 4,
         .host_caps      = (MMC_CAP_4_BIT_DATA |
                            MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc1 = {
@@ -59,17 +60,20 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 {
         struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
 
-        set->max_width = pd->max_width;
         set->cd_type = pd->cd_type;
         set->ext_cd_init = pd->ext_cd_init;
         set->ext_cd_cleanup = pd->ext_cd_cleanup;
         set->ext_cd_gpio = pd->ext_cd_gpio;
         set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+        if (pd->max_width)
+                set->max_width = pd->max_width;
         if (pd->cfg_gpio)
                 set->cfg_gpio = pd->cfg_gpio;
         if (pd->cfg_card)
                 set->cfg_card = pd->cfg_card;
         if (pd->host_caps)
-                set->host_caps = pd->host_caps;
+                set->host_caps |= pd->host_caps;
+        if (pd->clk_type)
+                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index cb0d7143381a..f60aedba417c 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -42,6 +42,7 @@ struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
         .max_width      = 4,
         .host_caps      = (MMC_CAP_4_BIT_DATA |
                            MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc2 = {
@@ -60,17 +61,20 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 {
         struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
 
-        set->max_width = pd->max_width;
         set->cd_type = pd->cd_type;
         set->ext_cd_init = pd->ext_cd_init;
         set->ext_cd_cleanup = pd->ext_cd_cleanup;
         set->ext_cd_gpio = pd->ext_cd_gpio;
         set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+        if (pd->max_width)
+                set->max_width = pd->max_width;
         if (pd->cfg_gpio)
                 set->cfg_gpio = pd->cfg_gpio;
         if (pd->cfg_card)
                 set->cfg_card = pd->cfg_card;
         if (pd->host_caps)
-                set->host_caps = pd->host_caps;
+                set->host_caps |= pd->host_caps;
+        if (pd->clk_type)
+                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index 85aaf0f2842f..ede776f20e62 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -33,8 +33,8 @@ static struct resource s3c_hsmmc3_resource[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_MMC3,
-                .end    = IRQ_MMC3,
+                .start  = IRQ_HSMMC3,
+                .end    = IRQ_HSMMC3,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -45,6 +45,7 @@ struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
         .max_width      = 4,
         .host_caps      = (MMC_CAP_4_BIT_DATA |
                            MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 
 struct platform_device s3c_device_hsmmc3 = {
@@ -63,15 +64,20 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 {
         struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata;
 
-        set->max_width = pd->max_width;
         set->cd_type = pd->cd_type;
         set->ext_cd_init = pd->ext_cd_init;
         set->ext_cd_cleanup = pd->ext_cd_cleanup;
         set->ext_cd_gpio = pd->ext_cd_gpio;
         set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
+        if (pd->max_width)
+                set->max_width = pd->max_width;
         if (pd->cfg_gpio)
                 set->cfg_gpio = pd->cfg_gpio;
         if (pd->cfg_card)
                 set->cfg_card = pd->cfg_card;
+        if (pd->host_caps)
+                set->host_caps |= pd->host_caps;
+        if (pd->clk_type)
+                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c
index 07036dee09e7..ff4ba69b6830 100644
--- a/arch/arm/plat-samsung/dev-i2c2.c
+++ b/arch/arm/plat-samsung/dev-i2c2.c
@@ -32,8 +32,8 @@ static struct resource s3c_i2c_resource[] = {
                 .flags = IORESOURCE_MEM,
         },
         [1] = {
-                .start = IRQ_CAN0,
-                .end   = IRQ_CAN0,
+                .start = IRQ_IIC2,
+                .end   = IRQ_IIC2,
                 .flags = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/plat-samsung/dev-i2c3.c b/arch/arm/plat-samsung/dev-i2c3.c
new file mode 100644
index 000000000000..8586a10014b7
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c3.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-samsung/dev-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start  = S3C_PA_IIC3,
+                .end    = S3C_PA_IIC3 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_IIC3,
+                .end    = IRQ_IIC3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c3 = {
+        .name           = "s3c2440-i2c",
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(s3c_i2c_resource),
+        .resource       = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data3 __initdata = {
+        .flags          = 0,
+        .bus_num        = 3,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data3;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c3_cfg_gpio;
+
+        s3c_device_i2c3.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-i2c4.c b/arch/arm/plat-samsung/dev-i2c4.c
new file mode 100644
index 000000000000..df2159e2daa6
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c4.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-samsung/dev-i2c4.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start  = S3C_PA_IIC4,
+                .end    = S3C_PA_IIC4 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_IIC4,
+                .end    = IRQ_IIC4,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c4 = {
+        .name           = "s3c2440-i2c",
+        .id             = 4,
+        .num_resources  = ARRAY_SIZE(s3c_i2c_resource),
+        .resource       = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data4 __initdata = {
+        .flags          = 0,
+        .bus_num        = 4,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data4;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c4_cfg_gpio;
+
+        s3c_device_i2c4.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-i2c5.c b/arch/arm/plat-samsung/dev-i2c5.c
new file mode 100644
index 000000000000..0499c2c3877b
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c5.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-samsung/dev-i2c3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start  = S3C_PA_IIC5,
+                .end    = S3C_PA_IIC5 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_IIC5,
+                .end    = IRQ_IIC5,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c5 = {
+        .name           = "s3c2440-i2c",
+        .id             = 5,
+        .num_resources  = ARRAY_SIZE(s3c_i2c_resource),
+        .resource       = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data5 __initdata = {
+        .flags          = 0,
+        .bus_num        = 5,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data5;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c5_cfg_gpio;
+
+        s3c_device_i2c5.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-i2c6.c b/arch/arm/plat-samsung/dev-i2c6.c
new file mode 100644
index 000000000000..4083108908a8
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c6.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-samsung/dev-i2c6.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 6
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start  = S3C_PA_IIC6,
+                .end    = S3C_PA_IIC6 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_IIC6,
+                .end    = IRQ_IIC6,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c6 = {
+        .name           = "s3c2440-i2c",
+        .id             = 6,
+        .num_resources  = ARRAY_SIZE(s3c_i2c_resource),
+        .resource       = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data6 __initdata = {
+        .flags          = 0,
+        .bus_num        = 6,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data6;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c6_cfg_gpio;
+
+        s3c_device_i2c6.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/dev-i2c7.c b/arch/arm/plat-samsung/dev-i2c7.c
new file mode 100644
index 000000000000..1182451d7dce
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-i2c7.c
@@ -0,0 +1,68 @@
+/* linux/arch/arm/plat-samsung/dev-i2c7.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P series device definition for i2c device 7
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gfp.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s3c_i2c_resource[] = {
+        [0] = {
+                .start  = S3C_PA_IIC7,
+                .end    = S3C_PA_IIC7 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_IIC7,
+                .end    = IRQ_IIC7,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device s3c_device_i2c7 = {
+        .name           = "s3c2440-i2c",
+        .id             = 7,
+        .num_resources  = ARRAY_SIZE(s3c_i2c_resource),
+        .resource       = s3c_i2c_resource,
+};
+
+static struct s3c2410_platform_i2c default_i2c_data7 __initdata = {
+        .flags          = 0,
+        .bus_num        = 7,
+        .slave_addr     = 0x10,
+        .frequency      = 100*1000,
+        .sda_delay      = 100,
+};
+
+void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
+{
+        struct s3c2410_platform_i2c *npd;
+
+        if (!pd)
+                pd = &default_i2c_data7;
+
+        npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
+        if (!npd)
+                printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+        else if (!npd->cfg_gpio)
+                npd->cfg_gpio = s3c_i2c7_cfg_gpio;
+
+        s3c_device_i2c7.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index e3d41eaed1ff..b732b773b9af 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -41,6 +41,37 @@ int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
 }
 EXPORT_SYMBOL(s3c_gpio_cfgpin);
 
+int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
+                          unsigned int cfg)
+{
+        int ret;
+
+        for (; nr > 0; nr--, start++) {
+                ret = s3c_gpio_cfgpin(start, cfg);
+                if (ret != 0)
+                        return ret;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
+
+int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
+                          unsigned int cfg, s3c_gpio_pull_t pull)
+{
+        int ret;
+
+        for (; nr > 0; nr--, start++) {
+                s3c_gpio_setpull(start, pull);
+                ret = s3c_gpio_cfgpin(start, cfg);
+                if (ret != 0)
+                        return ret;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
+
 unsigned s3c_gpio_getcfg(unsigned int pin)
 {
         struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
@@ -80,6 +111,25 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
 }
 EXPORT_SYMBOL(s3c_gpio_setpull);
 
+s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        unsigned long flags;
+        int offset;
+        u32 pup = 0;
+
+        if (chip) {
+                offset = pin - chip->chip.base;
+
+                s3c_gpio_lock(chip, flags);
+                pup = s3c_gpio_do_getpull(chip, offset);
+                s3c_gpio_unlock(chip, flags);
+        }
+
+        return (__force s3c_gpio_pull_t)pup;
+}
+EXPORT_SYMBOL(s3c_gpio_getpull);
+
 #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
 int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
                               unsigned int off, unsigned int cfg)
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c
index b83a83351cea..7743c4b8b2fb 100644
--- a/arch/arm/plat-samsung/gpio.c
+++ b/arch/arm/plat-samsung/gpio.c
@@ -157,3 +157,11 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
         if (ret >= 0)
                 s3c_gpiolib_track(chip);
 }
+
+int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+        struct s3c_gpio_chip *s3c_chip = container_of(chip,
+                        struct s3c_gpio_chip, chip);
+
+        return s3c_chip->irq_base + offset;
+}
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
index e32f9edfd4b7..7712ff6336f4 100644
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -16,6 +16,15 @@
 #define S3C64XX_AC97_GPE  1
 extern void s3c64xx_ac97_setup_gpio(int);
 
+/*
+ * The machine init code calls s5p*_spdif_setup_gpio with
+ * one of these defines in order to select appropriate bank
+ * of GPIO for S/PDIF pins
+ */
+#define S5PC100_SPDIF_GPD  0
+#define S5PC100_SPDIF_GPG3 1
+extern void s5pc100_spdif_setup_gpio(int);
+
 /**
  * struct s3c_audio_pdata - common platform data for audio device drivers
  * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index c8b94279bad1..2d82a6cb1444 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -48,6 +48,11 @@ extern struct platform_device s3c_device_wdt;
 extern struct platform_device s3c_device_i2c0;
 extern struct platform_device s3c_device_i2c1;
 extern struct platform_device s3c_device_i2c2;
+extern struct platform_device s3c_device_i2c3;
+extern struct platform_device s3c_device_i2c4;
+extern struct platform_device s3c_device_i2c5;
+extern struct platform_device s3c_device_i2c6;
+extern struct platform_device s3c_device_i2c7;
 extern struct platform_device s3c_device_rtc;
 extern struct platform_device s3c_device_adc;
 extern struct platform_device s3c_device_sdi;
@@ -89,6 +94,7 @@ extern struct platform_device s5pv210_device_pcm2;
 extern struct platform_device s5pv210_device_iis0;
 extern struct platform_device s5pv210_device_iis1;
 extern struct platform_device s5pv210_device_iis2;
+extern struct platform_device s5pv210_device_spdif;
 
 extern struct platform_device s5p6442_device_pcm0;
 extern struct platform_device s5p6442_device_pcm1;
@@ -108,6 +114,7 @@ extern struct platform_device s5pc100_device_pcm1;
 extern struct platform_device s5pc100_device_iis0;
 extern struct platform_device s5pc100_device_iis1;
 extern struct platform_device s5pc100_device_iis2;
+extern struct platform_device s5pc100_device_spdif;
 
 extern struct platform_device samsung_device_keypad;
 
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 3e21c75feefa..8fd65d8b5863 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -42,6 +42,12 @@ static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
         return (chip->config->set_pull)(chip, off, pull);
 }
 
+static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip,
+                                                  unsigned int off)
+{
+        return chip->config->get_pull(chip, off);
+}
+
 /**
  * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
  * @chip: The gpio chip that is being configured.
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 1c6b92947c5d..e4b5cf126fa9 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -108,6 +108,19 @@ extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
  */
 extern unsigned s3c_gpio_getcfg(unsigned int pin);
 
+/**
+ * s3c_gpio_cfgpin_range() - Change the GPIO function for configuring pin range
+ * @start: The pin number to start at
+ * @nr: The number of pins to configure from @start.
+ * @cfg: The configuration for the pin's function
+ *
+ * Call s3c_gpio_cfgpin() for the @nr pins starting at @start.
+ *
+ * @sa s3c_gpio_cfgpin.
+ */
+extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
+                                 unsigned int cfg);
+
 /* Define values for the pull-{up,down} available for each gpio pin.
  *
  * These values control the state of the weak pull-{up,down} resistors
@@ -140,6 +153,31 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
 */
 extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
 
+/* configure `all` aspects of an gpio */
+
+/**
+ * s3c_gpio_cfgall_range() - configure range of gpio functtion and pull.
+ * @start: The gpio number to start at.
+ * @nr: The number of gpio to configure from @start.
+ * @cfg: The configuration to use
+ * @pull: The pull setting to use.
+ *
+ * Run s3c_gpio_cfgpin() and s3c_gpio_setpull() over the gpio range starting
+ * @gpio and running for @size.
+ *
+ * @sa s3c_gpio_cfgpin
+ * @sa s3c_gpio_setpull
+ * @sa s3c_gpio_cfgpin_range
+ */
+extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
+                                 unsigned int cfg, s3c_gpio_pull_t pull);
+
+static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size,
+                                           unsigned int cfg)
+{
+        return s3c_gpio_cfgall_range(pin, size, cfg, S3C_GPIO_PULL_NONE);
+}
+
 /* Define values for the drvstr available for each gpio pin.
  *
  * These values control the value of the output signal driver strength,
@@ -169,4 +207,22 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
 */
 extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
 
+/**
+ * s5p_register_gpio_interrupt() - register interrupt support for a gpio group
+ * @pin: The pin number from the group to be registered
+ *
+ * This function registers gpio interrupt support for the group that the
+ * specified pin belongs to.
+ *
+ * The total number of gpio pins is quite large ob s5p series. Registering
+ * irq support for all of them would be a resource waste. Because of that the
+ * interrupt support for standard gpio pins is registered dynamically.
+ *
+ * It will return the irq number of the interrupt that has been registered
+ * or -ENOMEM if no more gpio interrupts can be registered. It is allowed
+ * to call this function more than once for the same gpio group (the group
+ * will be registered only once).
+ */
+extern int s5p_register_gpio_interrupt(int pin);
+
 #endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index e358c7da8480..13a22b8861ef 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -43,6 +43,8 @@ struct s3c_gpio_cfg;
  * struct s3c_gpio_chip - wrapper for specific implementation of gpio
  * @chip: The chip structure to be exported via gpiolib.
  * @base: The base pointer to the gpio configuration registers.
+ * @group: The group register number for gpio interrupt support.
+ * @irq_base: The base irq number.
  * @config: special function and pull-resistor control information.
  * @lock: Lock for exclusive access to this gpio bank.
  * @pm_save: Save information for suspend/resume support.
@@ -63,6 +65,8 @@ struct s3c_gpio_chip {
         struct s3c_gpio_cfg     *config;
         struct s3c_gpio_pm      *pm;
         void __iomem            *base;
+        int                     irq_base;
+        int                     group;
         spinlock_t               lock;
 #ifdef CONFIG_PM
         u32                     pm_save[4];
@@ -118,6 +122,17 @@ extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
 extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
 extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 
+
+/**
+ * samsung_gpiolib_to_irq - convert gpio pin to irq number
+ * @chip: The gpio chip that the pin belongs to.
+ * @offset: The offset of the pin in the chip.
+ *
+ * This helper returns the irq number calculated from the chip->irq_base and
+ * the provided offset.
+ */
+extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset);
+
 /* exported for core SoC support to change */
 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
index 133308bf595d..1543da8f85c1 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -55,10 +55,20 @@ struct s3c2410_platform_i2c {
 extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
 extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
+extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
 
 /* defined by architecture to configure gpio */
 extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
 extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
 extern void s3c_i2c2_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c3_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c4_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c5_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c6_cfg_gpio(struct platform_device *dev);
+extern void s3c_i2c7_cfg_gpio(struct platform_device *dev);
 
 #endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/plat-samsung/include/plat/map-base.h
index 250be311c85b..3ffac4d2e4f0 100644
--- a/arch/arm/plat-samsung/include/plat/map-base.h
+++ b/arch/arm/plat-samsung/include/plat/map-base.h
@@ -14,7 +14,7 @@
 #ifndef __ASM_PLAT_MAP_H
 #define __ASM_PLAT_MAP_H __FILE__
 
-/* Fit all our registers in at 0xF4000000 upwards, trying to use as
+/* Fit all our registers in at 0xF6000000 upwards, trying to use as
  * little of the VA space as possible so vmalloc and friends have a
  * better chance of getting memory.
  *
@@ -22,7 +22,7 @@
  * an single MOVS instruction (ie, only 8 bits of set data)
  */
 
-#define S3C_ADDR_BASE   (0xF4000000)
+#define S3C_ADDR_BASE   0xF6000000
 
 #ifndef __ASSEMBLY__
 #define S3C_ADDR(x)     ((void __iomem __force *)S3C_ADDR_BASE + (x))
diff --git a/arch/arm/plat-samsung/include/plat/nand-core.h b/arch/arm/plat-samsung/include/plat/nand-core.h
new file mode 100644
index 000000000000..6de20789a95e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/nand-core.h
@@ -0,0 +1,28 @@
+/* arch/arm/plat-samsung/include/plat/nand-core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S3C -  Nand Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_NAND_CORE_H
+#define __ASM_ARCH_NAND_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_nand_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_NAND
+        s3c_device_nand.name = name;
+#endif
+}
+
+#endif /* __ASM_ARCH_NAND_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 30844c263d03..85853f8c4c5d 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -28,11 +28,17 @@ enum cd_types {
         S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
 };
 
+enum clk_types {
+        S3C_SDHCI_CLK_DIV_INTERNAL,     /* use mmc internal clock divider */
+        S3C_SDHCI_CLK_DIV_EXTERNAL,     /* use external clock divider */
+};
+
 /**
  * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
  * @max_width: The maximum number of data bits supported.
  * @host_caps: Standard MMC host capabilities bit field.
  * @cd_type: Type of Card Detection method (see cd_types enum above)
+ * @clk_type: Type of clock divider method (see clk_types enum above)
  * @ext_cd_init: Initialize external card detect subsystem. Called on
  *               sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
  *               notify_func argument is a callback to the sdhci-s3c driver
@@ -59,6 +65,7 @@ struct s3c_sdhci_platdata {
         unsigned int    max_width;
         unsigned int    host_caps;
         enum cd_types   cd_type;
+        enum clk_types  clk_type;
 
         char            **clocks;       /* set of clock sources */
 
@@ -110,6 +117,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
 /* S3C64XX SDHCI setup */
 
@@ -288,4 +299,57 @@ static inline void s5pv210_default_sdhci3(void) { }
 
 #endif /* CONFIG_S5PV210_SETUP_SDHCI */
 
+/* S5PV310 SDHCI setup */
+#ifdef CONFIG_S5PV310_SETUP_SDHCI
+extern char *s5pv310_hsmmc_clksrcs[4];
+
+extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev,
+                                           void __iomem *r,
+                                           struct mmc_ios *ios,
+                                           struct mmc_card *card);
+
+static inline void s5pv310_default_sdhci0(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC
+        s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci1(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC1
+        s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci2(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC2
+        s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+static inline void s5pv310_default_sdhci3(void)
+{
+#ifdef CONFIG_S3C_DEV_HSMMC3
+        s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
+        s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio;
+        s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
+#endif
+}
+
+#else
+static inline void s5pv310_default_sdhci0(void) { }
+static inline void s5pv310_default_sdhci1(void) { }
+static inline void s5pv310_default_sdhci2(void) { }
+static inline void s5pv310_default_sdhci3(void) { }
+
+#endif /* CONFIG_S5PV310_SETUP_SDHCI */
+
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index 7df03f87fbfa..96528200eb79 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
         .resume = s3c_gpio_pm_2bit_resume,
 };
 
-#ifdef CONFIG_ARCH_S3C64XX
+#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
 static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
 {
         chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
         .save   = s3c_gpio_pm_4bit_save,
         .resume = s3c_gpio_pm_4bit_resume,
 };
-#endif /* CONFIG_ARCH_S3C64XX */
+#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
 
 /**
  * s3c_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c
index a91305a60aed..b4ff8d74ac40 100644
--- a/arch/arm/plat-samsung/s3c-pl330.c
+++ b/arch/arm/plat-samsung/s3c-pl330.c
@@ -15,6 +15,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 
 #include <asm/hardware/pl330.h>
 
@@ -27,6 +29,7 @@
  * @node: To attach to the global list of DMACs.
  * @pi: PL330 configuration info for the DMAC.
  * @kmcache: Pool to quickly allocate xfers for all channels in the dmac.
+ * @clk: Pointer of DMAC operation clock.
  */
 struct s3c_pl330_dmac {
         unsigned                busy_chan;
@@ -34,6 +37,7 @@ struct s3c_pl330_dmac {
         struct list_head        node;
         struct pl330_info       *pi;
         struct kmem_cache       *kmcache;
+        struct clk              *clk;
 };
 
 /**
@@ -1072,16 +1076,25 @@ static int pl330_probe(struct platform_device *pdev)
         if (ret)
                 goto probe_err4;
 
-        ret = pl330_add(pl330_info);
-        if (ret)
-                goto probe_err5;
-
         /* Allocate a new DMAC */
         s3c_pl330_dmac = kmalloc(sizeof(*s3c_pl330_dmac), GFP_KERNEL);
         if (!s3c_pl330_dmac) {
                 ret = -ENOMEM;
+                goto probe_err5;
+        }
+
+        /* Get operation clock and enable it */
+        s3c_pl330_dmac->clk = clk_get(&pdev->dev, "pdma");
+        if (IS_ERR(s3c_pl330_dmac->clk)) {
+                dev_err(&pdev->dev, "Cannot get operation clock.\n");
+                ret = -EINVAL;
                 goto probe_err6;
         }
+        clk_enable(s3c_pl330_dmac->clk);
+
+        ret = pl330_add(pl330_info);
+        if (ret)
+                goto probe_err7;
 
         /* Hook the info */
         s3c_pl330_dmac->pi = pl330_info;
@@ -1094,7 +1107,7 @@ static int pl330_probe(struct platform_device *pdev)
 
         if (!s3c_pl330_dmac->kmcache) {
                 ret = -ENOMEM;
-                goto probe_err7;
+                goto probe_err8;
         }
 
         /* Get the list of peripherals */
@@ -1120,10 +1133,13 @@ static int pl330_probe(struct platform_device *pdev)
 
         return 0;
 
+probe_err8:
+        pl330_del(pl330_info);
 probe_err7:
-        kfree(s3c_pl330_dmac);
+        clk_disable(s3c_pl330_dmac->clk);
+        clk_put(s3c_pl330_dmac->clk);
 probe_err6:
-        pl330_del(pl330_info);
+        kfree(s3c_pl330_dmac);
 probe_err5:
         free_irq(irq, pl330_info);
 probe_err4:
@@ -1188,6 +1204,10 @@ static int pl330_remove(struct platform_device *pdev)
                 }
         }
 
+        /* Disable operation clock */
+        clk_disable(dmac->clk);
+        clk_put(dmac->clk);
+
         /* Remove the DMAC */
         list_del(&dmac->node);
         kfree(dmac);
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index f0dc5b8075a7..313b13073c54 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux Kernel Configuration"
-
 config AVR32
         def_bool y
         # With EMBEDDED=n, we get lots of stuff automatically selected
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index d9a1cb7ec30a..0a221d48152d 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Blackfin Kernel Configuration"
-
 config SYMBOL_PREFIX
         string
         default "_"
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index 08bc44ea6883..edae461b1c54 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -320,7 +320,7 @@ static void bfin_correct_hw_break(void)
         }
 }
 
-void kgdb_disable_hw_debug(struct pt_regs *regs)
+static void bfin_disable_hw_debug(struct pt_regs *regs)
 {
         /* Disable hardware debugging while we are in kgdb */
         bfin_write_WPIACTL(0);
@@ -406,6 +406,7 @@ struct kgdb_arch arch_kgdb_ops = {
 #endif
         .set_hw_breakpoint = bfin_set_hw_break,
         .remove_hw_breakpoint = bfin_remove_hw_break,
+        .disable_hw_break = bfin_disable_hw_debug,
         .remove_all_hw_break = bfin_remove_all_hw_break,
         .correct_hw_break = bfin_correct_hw_break,
 };
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index aefe3b18a074..613e62831c55 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see the Configure script.
-#
-
-mainmenu "Linux/CRIS Kernel Configuration"
-
 config MMU
         bool
         default y
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index 0f2417df6323..f6bcb039cd6d 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -1,7 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
 config FRV
         bool
         default y
@@ -61,8 +57,6 @@ config HZ
         int
         default 1000
 
-mainmenu "Fujitsu FR-V Kernel Configuration"
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 988b6ff34cc4..65f897d8c1e9 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "uClinux/h8300 (w/o MMU) Kernel Configuration"
-
 config H8300
         bool
         default y
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 7c82fa1fc911..e0f5b6d7f849 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "IA-64 Linux Kernel Configuration"
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 6b1852f7f972..39e534f5a3b0 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -618,16 +618,15 @@ pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len,
 }
 
 
-static int
-pfmfs_get_sb(struct file_system_type *fs_type, int flags, const char *dev_name, void *data,
-             struct vfsmount *mnt)
+static struct dentry *
+pfmfs_mount(struct file_system_type *fs_type, int flags, const char *dev_name, void *data)
 {
-        return get_sb_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC, mnt);
+        return mount_pseudo(fs_type, "pfm:", NULL, PFMFS_MAGIC);
 }
 
 static struct file_system_type pfm_fs_type = {
         .name     = "pfmfs",
-        .get_sb   = pfmfs_get_sb,
+        .mount    = pfmfs_mount,
         .kill_sb  = kill_anon_super,
 };
 
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 3867fd21f333..5c291d65196b 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux/M32R Kernel Configuration"
-
 config M32R
         bool
         default y
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 77bb0d6baa62..bc9271b85759 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -1,7 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
 config M68K
         bool
         default y
@@ -62,8 +58,6 @@ config HZ
 config ARCH_USES_GETTIMEOFFSET
         def_bool y
 
-mainmenu "Linux/68k Kernel Configuration"
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/m68k/include/asm/irqflags.h b/arch/m68k/include/asm/irqflags.h
index 4a5b284a1550..7ef4115b8c4a 100644
--- a/arch/m68k/include/asm/irqflags.h
+++ b/arch/m68k/include/asm/irqflags.h
@@ -2,7 +2,9 @@
 #define _M68K_IRQFLAGS_H
 
 #include <linux/types.h>
+#ifdef CONFIG_MMU
 #include <linux/hardirq.h>
+#endif
 #include <linux/preempt.h>
 #include <asm/thread_info.h>
 #include <asm/entry.h>
diff --git a/arch/m68k/include/asm/machdep.h b/arch/m68k/include/asm/machdep.h
index 789f3b2de0e9..415d5484916c 100644
--- a/arch/m68k/include/asm/machdep.h
+++ b/arch/m68k/include/asm/machdep.h
@@ -40,5 +40,6 @@ extern unsigned long hw_timer_offset(void);
 extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
 
 extern void config_BSP(char *command, int len);
+extern void do_IRQ(int irq, struct pt_regs *fp);
 
 #endif /* _M68K_MACHDEP_H */
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 9287150e5fb0..fa9f746cf4ae 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "uClinux/68k (w/o MMU) Kernel Configuration"
-
 config M68K
         bool
         default y
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index dad40fc2bef8..387d5ffdfd3a 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -1,8 +1,3 @@
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-
-mainmenu "Linux/Microblaze Kernel Configuration"
-
 config MICROBLAZE
         def_bool y
         select HAVE_MEMBLOCK
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 46cae2b163e4..67a2fa2caa49 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,18 +4,21 @@ config MIPS
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_IDE
         select HAVE_OPROFILE
+        select HAVE_PERF_EVENTS
+        select PERF_USE_VMALLOC
         select HAVE_ARCH_KGDB
         select HAVE_FUNCTION_TRACER
         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FTRACE_MCOUNT_RECORD
+        select HAVE_C_RECORDMCOUNT
         select HAVE_FUNCTION_GRAPH_TRACER
         select HAVE_KPROBES
         select HAVE_KRETPROBES
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
-
-mainmenu "Linux/MIPS Kernel Configuration"
+        select HAVE_DMA_ATTRS
+        select HAVE_DMA_API_DEBUG
 
 menu "Machine selection"
 
@@ -693,6 +696,9 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
         select SWAP_IO_SPACE
         select HW_HAS_PCI
         select ARCH_SUPPORTS_MSI
+        select ZONE_DMA32
+        select USB_ARCH_HAS_OHCI
+        select USB_ARCH_HAS_EHCI
         help
           This option supports all of the Octeon reference boards from Cavium
           Networks. It builds a kernel that dynamically determines the Octeon
@@ -1336,6 +1342,57 @@ config CPU_CAVIUM_OCTEON
           can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
           Full details can be found at http://www.caviumnetworks.com.
 
+config CPU_BMIPS3300
+        bool "BMIPS3300"
+        depends on SYS_HAS_CPU_BMIPS3300
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS3300 processors.
+
+config CPU_BMIPS4350
+        bool "BMIPS4350"
+        depends on SYS_HAS_CPU_BMIPS4350
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS4350 ("VIPER") processors.
+
+config CPU_BMIPS4380
+        bool "BMIPS4380"
+        depends on SYS_HAS_CPU_BMIPS4380
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS4380 processors.
+
+config CPU_BMIPS5000
+        bool "BMIPS5000"
+        depends on SYS_HAS_CPU_BMIPS5000
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
+        select DMA_NONCOHERENT
+        select IRQ_CPU
+        select SWAP_IO_SPACE
+        select SYS_SUPPORTS_SMP
+        select SYS_SUPPORTS_HOTPLUG_CPU
+        select WEAK_ORDERING
+        help
+          Broadcom BMIPS5000 processors.
+
 endchoice
 
 if CPU_LOONGSON2F
@@ -1454,6 +1511,18 @@ config SYS_HAS_CPU_SB1
 config SYS_HAS_CPU_CAVIUM_OCTEON
         bool
 
+config SYS_HAS_CPU_BMIPS3300
+        bool
+
+config SYS_HAS_CPU_BMIPS4350
+        bool
+
+config SYS_HAS_CPU_BMIPS4380
+        bool
+
+config SYS_HAS_CPU_BMIPS5000
+        bool
+
 #
 # CPU may reorder R->R, R->W, W->R, W->W
 # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1930,6 +1999,14 @@ config NODES_SHIFT
         default "6"
         depends on NEED_MULTIPLE_NODES
 
+config HW_PERF_EVENTS
+        bool "Enable hardware performance counter support for perf events"
+        depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
+        default y
+        help
+          Enable hardware performance counter support for perf events. If
+          disabled, perf events will use software events only.
+
 source "mm/Kconfig"
 
 config SMP
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 43dc27997730..f437cd1fafb8 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -67,6 +67,15 @@ config CMDLINE_OVERRIDE
 
           Normally, you will choose 'N' here.
 
+config DEBUG_STACKOVERFLOW
+        bool "Check for stack overflows"
+        depends on DEBUG_KERNEL
+        help
+          This option will cause messages to be printed if free stack space
+          drops below a certain limit(2GB on MIPS). The debugging option
+          provides another way to check stack overflow happened on kernel mode
+          stack usually caused by nested interruption.
+
 config DEBUG_STACK_USAGE
         bool "Enable stack utilization instrumentation"
         depends on DEBUG_KERNEL
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index f4a4b663ebb3..7c1102e41fe2 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -48,9 +48,6 @@ ifneq ($(SUBARCH),$(ARCH))
   endif
 endif
 
-ifndef CONFIG_FUNCTION_TRACER
-cflags-y := -ffunction-sections
-endif
 ifdef CONFIG_FUNCTION_GRAPH_TRACER
   ifndef KBUILD_MCOUNT_RA_ADDRESS
     ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
@@ -159,6 +156,7 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
 ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
 cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
 endif
+cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
 
 cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)  += $(call cc-option,-mfix-r4000,)
 cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)  += $(call cc-option,-mfix-r4400,)
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index c32fbb57441a..425dfa5d6e12 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
- * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -37,6 +37,16 @@ static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
         return readl(gpio_in) & (1 << gpio);
 }
 
+static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;
+        void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;
+
+        return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
+}
+
 static void ar7_gpio_set_value(struct gpio_chip *chip,
                                 unsigned gpio, int value)
 {
@@ -51,6 +61,21 @@ static void ar7_gpio_set_value(struct gpio_chip *chip,
         writel(tmp, gpio_out);
 }
 
+static void titan_gpio_set_value(struct gpio_chip *chip,
+                                unsigned gpio, int value)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;
+        void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;
+        unsigned tmp;
+
+        tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
+        if (value)
+                tmp |= 1 << (gpio & 0x1f);
+        writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
+}
+
 static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 {
         struct ar7_gpio_chip *gpch =
@@ -62,6 +87,21 @@ static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
         return 0;
 }
 
+static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+        void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+        if (gpio >= TITAN_GPIO_MAX)
+                return -EINVAL;
+
+        writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
+                        gpio >> 5 ? gpio_dir1 : gpio_dir0);
+        return 0;
+}
+
 static int ar7_gpio_direction_output(struct gpio_chip *chip,
                                         unsigned gpio, int value)
 {
@@ -75,6 +115,24 @@ static int ar7_gpio_direction_output(struct gpio_chip *chip,
         return 0;
 }
 
+static int titan_gpio_direction_output(struct gpio_chip *chip,
+                                        unsigned gpio, int value)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;
+        void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;
+
+        if (gpio >= TITAN_GPIO_MAX)
+                return -EINVAL;
+
+        titan_gpio_set_value(chip, gpio, value);
+        writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
+                (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+        return 0;
+}
+
 static struct ar7_gpio_chip ar7_gpio_chip = {
         .chip = {
                 .label                  = "ar7-gpio",
@@ -87,7 +145,19 @@ static struct ar7_gpio_chip ar7_gpio_chip = {
         }
 };
 
-int ar7_gpio_enable(unsigned gpio)
+static struct ar7_gpio_chip titan_gpio_chip = {
+        .chip = {
+                .label                  = "titan-gpio",
+                .direction_input        = titan_gpio_direction_input,
+                .direction_output       = titan_gpio_direction_output,
+                .set                    = titan_gpio_set_value,
+                .get                    = titan_gpio_get_value,
+                .base                   = 0,
+                .ngpio                  = TITAN_GPIO_MAX,
+        }
+};
+
+static inline int ar7_gpio_enable_ar7(unsigned gpio)
 {
         void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
 
@@ -95,9 +165,26 @@ int ar7_gpio_enable(unsigned gpio)
 
         return 0;
 }
+
+static inline int ar7_gpio_enable_titan(unsigned gpio)
+{
+        void __iomem *gpio_en0 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_0;
+        void __iomem *gpio_en1 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_1;
+
+        writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
+                gpio >> 5 ? gpio_en1 : gpio_en0);
+
+        return 0;
+}
+
+int ar7_gpio_enable(unsigned gpio)
+{
+        return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
+                                ar7_gpio_enable_ar7(gpio);
+}
 EXPORT_SYMBOL(ar7_gpio_enable);
 
-int ar7_gpio_disable(unsigned gpio)
+static inline int ar7_gpio_disable_ar7(unsigned gpio)
 {
         void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
 
@@ -105,27 +192,159 @@ int ar7_gpio_disable(unsigned gpio)
 
         return 0;
 }
+
+static inline int ar7_gpio_disable_titan(unsigned gpio)
+{
+        void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;
+        void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;
+
+        writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
+                        gpio >> 5 ? gpio_en1 : gpio_en0);
+
+        return 0;
+}
+
+int ar7_gpio_disable(unsigned gpio)
+{
+        return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
+                                ar7_gpio_disable_ar7(gpio);
+}
 EXPORT_SYMBOL(ar7_gpio_disable);
 
-static int __init ar7_gpio_init(void)
+struct titan_gpio_cfg {
+        u32 reg;
+        u32 shift;
+        u32 func;
+};
+
+static struct titan_gpio_cfg titan_gpio_table[] = {
+        /* reg, start bit, mux value */
+        {4, 24, 1},
+        {4, 26, 1},
+        {4, 28, 1},
+        {4, 30, 1},
+        {5, 6, 1},
+        {5, 8, 1},
+        {5, 10, 1},
+        {5, 12, 1},
+        {7, 14, 3},
+        {7, 16, 3},
+        {7, 18, 3},
+        {7, 20, 3},
+        {7, 22, 3},
+        {7, 26, 3},
+        {7, 28, 3},
+        {7, 30, 3},
+        {8, 0, 3},
+        {8, 2, 3},
+        {8, 4, 3},
+        {8, 10, 3},
+        {8, 14, 3},
+        {8, 16, 3},
+        {8, 18, 3},
+        {8, 20, 3},
+        {9, 8, 3},
+        {9, 10, 3},
+        {9, 12, 3},
+        {9, 14, 3},
+        {9, 18, 3},
+        {9, 20, 3},
+        {9, 24, 3},
+        {9, 26, 3},
+        {9, 28, 3},
+        {9, 30, 3},
+        {10, 0, 3},
+        {10, 2, 3},
+        {10, 8, 3},
+        {10, 10, 3},
+        {10, 12, 3},
+        {10, 14, 3},
+        {13, 12, 3},
+        {13, 14, 3},
+        {13, 16, 3},
+        {13, 18, 3},
+        {13, 24, 3},
+        {13, 26, 3},
+        {13, 28, 3},
+        {13, 30, 3},
+        {14, 2, 3},
+        {14, 6, 3},
+        {14, 8, 3},
+        {14, 12, 3}
+};
+
+static int titan_gpio_pinsel(unsigned gpio)
+{
+        struct titan_gpio_cfg gpio_cfg;
+        u32 mux_status, pin_sel_reg, tmp;
+        void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);
+
+        if (gpio >= ARRAY_SIZE(titan_gpio_table))
+                return -EINVAL;
+
+        gpio_cfg = titan_gpio_table[gpio];
+        pin_sel_reg = gpio_cfg.reg - 1;
+
+        mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;
+
+        /* Check the mux status */
+        if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))
+                return 0;
+
+        /* Set the pin sel value */
+        tmp = readl(pin_sel + pin_sel_reg);
+        tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
+        writel(tmp, pin_sel + pin_sel_reg);
+
+        return 0;
+}
+
+/* Perform minimal Titan GPIO configuration */
+static void titan_gpio_init(void)
+{
+        unsigned i;
+
+        for (i = 44; i < 48; i++) {
+                titan_gpio_pinsel(i);
+                ar7_gpio_enable_titan(i);
+                titan_gpio_direction_input(&titan_gpio_chip.chip, i);
+        }
+}
+
+int __init ar7_gpio_init(void)
 {
         int ret;
+        struct ar7_gpio_chip *gpch;
+        unsigned size;
+
+        if (!ar7_is_titan()) {
+                gpch = &ar7_gpio_chip;
+                size = 0x10;
+        } else {
+                gpch = &titan_gpio_chip;
+                size = 0x1f;
+        }
 
-        ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
+        gpch->regs = ioremap_nocache(AR7_REGS_GPIO,
                                         AR7_REGS_GPIO + 0x10);
 
-        if (!ar7_gpio_chip.regs) {
-                printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
+        if (!gpch->regs) {
+                printk(KERN_ERR "%s: failed to ioremap regs\n",
+                                        gpch->chip.label);
                 return -ENOMEM;
         }
 
-        ret = gpiochip_add(&ar7_gpio_chip.chip);
+        ret = gpiochip_add(&gpch->chip);
         if (ret) {
-                printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
+                printk(KERN_ERR "%s: failed to add gpiochip\n",
+                                        gpch->chip.label);
                 return ret;
         }
-        printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
-                                ar7_gpio_chip.chip.ngpio);
+        printk(KERN_INFO "%s: registered %d GPIOs\n",
+                                gpch->chip.label, gpch->chip.ngpio);
+
+        if (ar7_is_titan())
+                titan_gpio_init();
+
         return ret;
 }
-arch_initcall(ar7_gpio_init);
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 0da5b2b8dd88..7d2fab392327 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -357,6 +357,11 @@ static struct gpio_led default_leds[] = {
         },
 };
 
+static struct gpio_led titan_leds[] = {
+        { .name = "status", .gpio = 8, .active_low = 1, },
+        { .name = "wifi", .gpio = 13, .active_low = 1, },
+};
+
 static struct gpio_led dsl502t_leds[] = {
         {
                 .name                   = "status",
@@ -495,6 +500,9 @@ static void __init detect_leds(void)
         } else if (strstr(prid, "DG834")) {
                 ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
                 ar7_led_data.leds = dg834g_leds;
+        } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
+                ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
+                ar7_led_data.leds = titan_leds;
         }
 }
 
@@ -560,6 +568,51 @@ static int __init ar7_register_uarts(void)
         return 0;
 }
 
+static void __init titan_fixup_devices(void)
+{
+        /* Set vlynq0 data */
+        vlynq_low_data.reset_bit = 15;
+        vlynq_low_data.gpio_bit = 14;
+
+        /* Set vlynq1 data */
+        vlynq_high_data.reset_bit = 16;
+        vlynq_high_data.gpio_bit = 7;
+
+        /* Set vlynq0 resources */
+        vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;
+        vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;
+        vlynq_low_res[1].start = 33;
+        vlynq_low_res[1].end = 33;
+        vlynq_low_res[2].start = 0x0c000000;
+        vlynq_low_res[2].end = 0x0fffffff;
+        vlynq_low_res[3].start = 80;
+        vlynq_low_res[3].end = 111;
+
+        /* Set vlynq1 resources */
+        vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;
+        vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;
+        vlynq_high_res[1].start = 34;
+        vlynq_high_res[1].end = 34;
+        vlynq_high_res[2].start = 0x40000000;
+        vlynq_high_res[2].end = 0x43ffffff;
+        vlynq_high_res[3].start = 112;
+        vlynq_high_res[3].end = 143;
+
+        /* Set cpmac0 data */
+        cpmac_low_data.phy_mask = 0x40000000;
+
+        /* Set cpmac1 data */
+        cpmac_high_data.phy_mask = 0x80000000;
+
+        /* Set cpmac0 resources */
+        cpmac_low_res[0].start = TITAN_REGS_MAC0;
+        cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;
+
+        /* Set cpmac1 resources */
+        cpmac_high_res[0].start = TITAN_REGS_MAC1;
+        cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;
+}
+
 static int __init ar7_register_devices(void)
 {
         void __iomem *bootcr;
@@ -574,6 +627,9 @@ static int __init ar7_register_devices(void)
         if (res)
                 pr_warning("unable to register physmap-flash: %d\n", res);
 
+        if (ar7_is_titan())
+                titan_fixup_devices();
+
         ar7_device_disable(vlynq_low_data.reset_bit);
         res = platform_device_register(&vlynq_low);
         if (res)
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index 52385790e5c1..23818d299127 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -246,6 +246,8 @@ void __init prom_init(void)
         ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
         ar7_init_env((struct env_var *)fw_arg2);
         console_config();
+
+        ar7_gpio_init();
 }
 
 #define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c
index 3a801d2cb6e5..f20b53e597c4 100644
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -23,6 +23,7 @@
 #include <asm/reboot.h>
 #include <asm/mach-ar7/ar7.h>
 #include <asm/mach-ar7/prom.h>
+#include <asm/mach-ar7/gpio.h>
 
 static void ar7_machine_restart(char *command)
 {
@@ -49,6 +50,8 @@ static void ar7_machine_power_off(void)
 const char *get_system_type(void)
 {
         u16 chip_id = ar7_chip_id();
+        u16 titan_variant_id = titan_chip_id();
+
         switch (chip_id) {
         case AR7_CHIP_7100:
                 return "TI AR7 (TNETD7100)";
@@ -56,6 +59,17 @@ const char *get_system_type(void)
                 return "TI AR7 (TNETD7200)";
         case AR7_CHIP_7300:
                 return "TI AR7 (TNETD7300)";
+        case AR7_CHIP_TITAN:
+                switch (titan_variant_id) {
+                case TITAN_CHIP_1050:
+                        return "TI AR7 (TNETV1050)";
+                case TITAN_CHIP_1055:
+                        return "TI AR7 (TNETV1055)";
+                case TITAN_CHIP_1056:
+                        return "TI AR7 (TNETV1056)";
+                case TITAN_CHIP_1060:
+                        return "TI AR7 (TNETV1060)";
+                }
         default:
                 return "TI AR7 (unknown)";
         }
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index cbb7caf86d77..7c7e4d4486ce 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -10,7 +10,9 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/cpu.h>
+#include <asm/cpu.h>
 #include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_regs.h>
 #include <bcm63xx_io.h>
@@ -296,26 +298,24 @@ void __init bcm63xx_cpu_init(void)
         expected_cpu_id = 0;
 
         switch (c->cputype) {
-        /*
-         * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
-         */
-        case CPU_BCM3302:
-                __cpu_name[cpu] = "Broadcom BCM6338";
-                expected_cpu_id = BCM6338_CPU_ID;
-                bcm63xx_regs_base = bcm96338_regs_base;
-                bcm63xx_irqs = bcm96338_irqs;
+        case CPU_BMIPS3300:
+                if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
+                        expected_cpu_id = BCM6348_CPU_ID;
+                        bcm63xx_regs_base = bcm96348_regs_base;
+                        bcm63xx_irqs = bcm96348_irqs;
+                } else {
+                        __cpu_name[cpu] = "Broadcom BCM6338";
+                        expected_cpu_id = BCM6338_CPU_ID;
+                        bcm63xx_regs_base = bcm96338_regs_base;
+                        bcm63xx_irqs = bcm96338_irqs;
+                }
                 break;
-        case CPU_BCM6345:
+        case CPU_BMIPS32:
                 expected_cpu_id = BCM6345_CPU_ID;
                 bcm63xx_regs_base = bcm96345_regs_base;
                 bcm63xx_irqs = bcm96345_irqs;
                 break;
-        case CPU_BCM6348:
-                expected_cpu_id = BCM6348_CPU_ID;
-                bcm63xx_regs_base = bcm96348_regs_base;
-                bcm63xx_irqs = bcm96348_irqs;
-                break;
-        case CPU_BCM6358:
+        case CPU_BMIPS4350:
                 expected_cpu_id = BCM6358_CPU_ID;
                 bcm63xx_regs_base = bcm96358_regs_base;
                 bcm63xx_irqs = bcm96358_irqs;
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 47323ca452dc..caae22858163 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -3,6 +3,17 @@ config CAVIUM_OCTEON_SPECIFIC_OPTIONS
         depends on CPU_CAVIUM_OCTEON
         default "y"
 
+config CAVIUM_CN63XXP1
+        bool "Enable CN63XXP1 errata worarounds"
+        depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
+        default "n"
+        help
+          The CN63XXP1 chip requires build time workarounds to
+          function reliably, select this option to enable them.  These
+          workarounds will cause a slight decrease in performance on
+          non-CN63XXP1 hardware, so it is recommended to select "n"
+          unless it is known the workarounds are needed.
+
 config CAVIUM_OCTEON_2ND_KERNEL
         bool "Build the kernel to be used as a 2nd kernel on the same chip"
         depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
@@ -87,3 +98,15 @@ config ARCH_SPARSEMEM_ENABLE
 config CAVIUM_OCTEON_HELPER
         def_bool y
         depends on OCTEON_ETHERNET || PCI
+
+config IOMMU_HELPER
+        bool
+
+config NEED_SG_DMA_LENGTH
+        bool
+
+config SWIOTLB
+        def_bool y
+        depends on CPU_CAVIUM_OCTEON
+        select IOMMU_HELPER
+        select NEED_SG_DMA_LENGTH
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index b6847c8e0ddd..26bf71130bf8 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -4,14 +4,18 @@
  * for more details.
  *
  * Copyright (C) 2007 by Ralf Baechle
+ * Copyright (C) 2009, 2010 Cavium Networks, Inc.
  */
 #include <linux/clocksource.h>
 #include <linux/init.h>
+#include <linux/smp.h>
 
+#include <asm/cpu-info.h>
 #include <asm/time.h>
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-ipd-defs.h>
+#include <asm/octeon/cvmx-mio-defs.h>
 
 /*
  * Set the current core's cvmcount counter to the value of the
@@ -19,11 +23,23 @@
  * on-line.  This allows for a read from a local cpu register to
  * access a synchronized counter.
  *
+ * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
  */
 void octeon_init_cvmcount(void)
 {
         unsigned long flags;
         unsigned loops = 2;
+        u64 f = 0;
+        u64 rdiv = 0;
+        u64 sdiv = 0;
+        if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
+                union cvmx_mio_rst_boot rst_boot;
+                rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+                rdiv = rst_boot.s.c_mul;        /* CPU clock */
+                sdiv = rst_boot.s.pnr_mul;      /* I/O clock */
+                f = (0x8000000000000000ull / sdiv) * 2;
+        }
+
 
         /* Clobber loops so GCC will not unroll the following while loop. */
         asm("" : "+r" (loops));
@@ -33,8 +49,20 @@ void octeon_init_cvmcount(void)
          * Loop several times so we are executing from the cache,
          * which should give more deterministic timing.
          */
-        while (loops--)
-                write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
+        while (loops--) {
+                u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
+                if (rdiv != 0) {
+                        ipd_clk_count *= rdiv;
+                        if (f != 0) {
+                                asm("dmultu\t%[cnt],%[f]\n\t"
+                                    "mfhi\t%[cnt]"
+                                    : [cnt] "+r" (ipd_clk_count),
+                                      [f] "=r" (f)
+                                    : : "hi", "lo");
+                        }
+                }
+                write_c0_cvmcount(ipd_clk_count);
+        }
         local_irq_restore(flags);
 }
 
@@ -77,7 +105,7 @@ unsigned long long notrace sched_clock(void)
 void __init plat_time_init(void)
 {
         clocksource_mips.rating = 300;
-        clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
+        clocksource_set_clock(&clocksource_mips, octeon_get_clock_rate());
         clocksource_register(&clocksource_mips);
 }
 
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index d22b5a2d64f4..1abb66caaa1d 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -8,335 +8,342 @@
  * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
  * IP32 changes by Ilya.
- * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
- * the kernels original.
+ * Copyright (C) 2010 Cavium Networks, Inc.
  */
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/string.h>
 #include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
 #include <linux/scatterlist.h>
+#include <linux/bootmem.h>
+#include <linux/swiotlb.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
 
-#include <linux/cache.h>
-#include <linux/io.h>
+#include <asm/bootinfo.h>
 
 #include <asm/octeon/octeon.h>
+
+#ifdef CONFIG_PCI
+#include <asm/octeon/pci-octeon.h>
 #include <asm/octeon/cvmx-npi-defs.h>
 #include <asm/octeon/cvmx-pci-defs.h>
 
-#include <dma-coherence.h>
+static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
+{
+        if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
+                return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
+        else
+                return paddr;
+}
 
-#ifdef CONFIG_PCI
-#include <asm/octeon/pci-octeon.h>
-#endif
+static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
+{
+        if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
+                return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
+        else
+                return daddr;
+}
+
+static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+                paddr -= 0x400000000ull;
+        return octeon_hole_phys_to_dma(paddr);
+}
 
-#define BAR2_PCI_ADDRESS 0x8000000000ul
+static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        daddr = octeon_hole_dma_to_phys(daddr);
 
-struct bar1_index_state {
-        int16_t ref_count;      /* Number of PCI mappings using this index */
-        uint16_t address_bits;  /* Upper bits of physical address. This is
-                                   shifted 22 bits */
-};
+        if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+                daddr += 0x400000000ull;
 
-#ifdef CONFIG_PCI
-static DEFINE_RAW_SPINLOCK(bar1_lock);
-static struct bar1_index_state bar1_state[32];
-#endif
+        return daddr;
+}
 
-dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
+static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
-#ifndef CONFIG_PCI
-        /* Without PCI/PCIe this function can be called for Octeon internal
-           devices such as USB. These devices all support 64bit addressing */
+        if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+                paddr -= 0x400000000ull;
+
+        /* Anything in the BAR1 hole or above goes via BAR2 */
+        if (paddr >= 0xf0000000ull)
+                paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+        return paddr;
+}
+
+static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+                daddr -= OCTEON_BAR2_PCI_ADDRESS;
+
+        if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+                daddr += 0x400000000ull;
+        return daddr;
+}
+
+static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
+                                           phys_addr_t paddr)
+{
+        if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
+                paddr -= 0x400000000ull;
+
+        /* Anything not in the BAR1 range goes via BAR2 */
+        if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
+                paddr = paddr - octeon_bar1_pci_phys;
+        else
+                paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
+
+        return paddr;
+}
+
+static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
+                                            dma_addr_t daddr)
+{
+        if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
+                daddr -= OCTEON_BAR2_PCI_ADDRESS;
+        else
+                daddr += octeon_bar1_pci_phys;
+
+        if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
+                daddr += 0x400000000ull;
+        return daddr;
+}
+
+#endif /* CONFIG_PCI */
+
+static dma_addr_t octeon_dma_map_page(struct device *dev, struct page *page,
+        unsigned long offset, size_t size, enum dma_data_direction direction,
+        struct dma_attrs *attrs)
+{
+        dma_addr_t daddr = swiotlb_map_page(dev, page, offset, size,
+                                            direction, attrs);
         mb();
-        return virt_to_phys(ptr);
-#else
-        unsigned long flags;
-        uint64_t dma_mask;
-        int64_t start_index;
-        dma_addr_t result = -1;
-        uint64_t physical = virt_to_phys(ptr);
-        int64_t index;
 
+        return daddr;
+}
+
+static int octeon_dma_map_sg(struct device *dev, struct scatterlist *sg,
+        int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
+{
+        int r = swiotlb_map_sg_attrs(dev, sg, nents, direction, attrs);
         mb();
-        /*
-         * Use the DMA masks to determine the allowed memory
-         * region. For us it doesn't limit the actual memory, just the
-         * address visible over PCI.  Devices with limits need to use
-         * lower indexed Bar1 entries.
-         */
-        if (dev) {
-                dma_mask = dev->coherent_dma_mask;
-                if (dev->dma_mask)
-                        dma_mask = *dev->dma_mask;
-        } else {
-                dma_mask = 0xfffffffful;
-        }
+        return r;
+}
 
-        /*
-         * Platform devices, such as the internal USB, skip all
-         * translation and use Octeon physical addresses directly.
-         */
-        if (!dev || dev->bus == &platform_bus_type)
-                return physical;
+static void octeon_dma_sync_single_for_device(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
+{
+        swiotlb_sync_single_for_device(dev, dma_handle, size, direction);
+        mb();
+}
 
-        switch (octeon_dma_bar_type) {
-        case OCTEON_DMA_BAR_TYPE_PCIE:
-                if (unlikely(physical < (16ul << 10)))
-                        panic("dma_map_single: Not allowed to map first 16KB."
-                              " It interferes with BAR0 special area\n");
-                else if ((physical + size >= (256ul << 20)) &&
-                         (physical < (512ul << 20)))
-                        panic("dma_map_single: Not allowed to map bootbus\n");
-                else if ((physical + size >= 0x400000000ull) &&
-                         physical < 0x410000000ull)
-                        panic("dma_map_single: "
-                              "Attempt to map illegal memory address 0x%llx\n",
-                              physical);
-                else if (physical >= 0x420000000ull)
-                        panic("dma_map_single: "
-                              "Attempt to map illegal memory address 0x%llx\n",
-                              physical);
-                else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
-                         physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
-                        result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
-
-                        if (((result+size-1) & dma_mask) != result+size-1)
-                                panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
-                                      physical, physical+size-1, dma_mask);
-                        goto done;
-                }
-
-                /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
-                if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
-                        result = physical - 0x400000000ull;
-                else
-                        result = physical;
-                if (((result+size-1) & dma_mask) != result+size-1)
-                        panic("dma_map_single: Attempt to map address "
-                              "0x%llx-0x%llx, which can't be accessed "
-                              "according to the dma mask 0x%llx\n",
-                              physical, physical+size-1, dma_mask);
-                goto done;
+static void octeon_dma_sync_sg_for_device(struct device *dev,
+        struct scatterlist *sg, int nelems, enum dma_data_direction direction)
+{
+        swiotlb_sync_sg_for_device(dev, sg, nelems, direction);
+        mb();
+}
 
-        case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
-                /* If the device supports 64bit addressing, then use BAR2 */
-                if (dma_mask > BAR2_PCI_ADDRESS) {
-                        result = physical + BAR2_PCI_ADDRESS;
-                        goto done;
-                }
-#endif
-                if (unlikely(physical < (4ul << 10))) {
-                        panic("dma_map_single: Not allowed to map first 4KB. "
-                              "It interferes with BAR0 special area\n");
-                } else if (physical < (256ul << 20)) {
-                        if (unlikely(physical + size > (256ul << 20)))
-                                panic("dma_map_single: Requested memory spans "
-                                      "Bar0 0:256MB and bootbus\n");
-                        result = physical;
-                        goto done;
-                } else if (unlikely(physical < (512ul << 20))) {
-                        panic("dma_map_single: Not allowed to map bootbus\n");
-                } else if (physical < (2ul << 30)) {
-                        if (unlikely(physical + size > (2ul << 30)))
-                                panic("dma_map_single: Requested memory spans "
-                                      "Bar0 512MB:2GB and BAR1\n");
-                        result = physical;
-                        goto done;
-                } else if (physical < (2ul << 30) + (128 << 20)) {
-                        /* Fall through */
-                } else if (physical <
-                           (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
-                        if (unlikely
-                            (physical + size >
-                             (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
-                                panic("dma_map_single: Requested memory "
-                                      "extends past Bar1 (4GB-%luMB)\n",
-                                      OCTEON_PCI_BAR1_HOLE_SIZE);
-                        result = physical;
-                        goto done;
-                } else if ((physical >= 0x410000000ull) &&
-                           (physical < 0x420000000ull)) {
-                        if (unlikely(physical + size > 0x420000000ull))
-                                panic("dma_map_single: Requested memory spans "
-                                      "non existant memory\n");
-                        /* BAR0 fixed mapping 256MB:512MB ->
-                         * 16GB+256MB:16GB+512MB */
-                        result = physical - 0x400000000ull;
-                        goto done;
-                } else {
-                        /* Continued below switch statement */
-                }
-                break;
+static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
+        dma_addr_t *dma_handle, gfp_t gfp)
+{
+        void *ret;
 
-        case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
-                /* If the device supports 64bit addressing, then use BAR2 */
-                if (dma_mask > BAR2_PCI_ADDRESS) {
-                        result = physical + BAR2_PCI_ADDRESS;
-                        goto done;
-                }
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
+                return ret;
+
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
+
+#ifdef CONFIG_ZONE_DMA
+        if (dev == NULL)
+                gfp |= __GFP_DMA;
+        else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
+                gfp |= __GFP_DMA;
+        else
 #endif
-                /* Continued below switch statement */
-                break;
+#ifdef CONFIG_ZONE_DMA32
+             if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
+                gfp |= __GFP_DMA32;
+        else
+#endif
+                ;
 
-        default:
-                panic("dma_map_single: Invalid octeon_dma_bar_type\n");
-        }
+        /* Don't invoke OOM killer */
+        gfp |= __GFP_NORETRY;
 
-        /* Don't allow mapping to span multiple Bar entries. The hardware guys
-           won't guarantee that DMA across boards work */
-        if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
-                panic("dma_map_single: "
-                      "Requested memory spans more than one Bar1 entry\n");
+        ret = swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
 
-        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
-                start_index = 31;
-        else if (unlikely(dma_mask < (1ul << 27)))
-                start_index = (dma_mask >> 22);
-        else
-                start_index = 31;
-
-        /* Only one processor can access the Bar register at once */
-        raw_spin_lock_irqsave(&bar1_lock, flags);
-
-        /* Look through Bar1 for existing mapping that will work */
-        for (index = start_index; index >= 0; index--) {
-                if ((bar1_state[index].address_bits == physical >> 22) &&
-                    (bar1_state[index].ref_count)) {
-                        /* An existing mapping will work, use it */
-                        bar1_state[index].ref_count++;
-                        if (unlikely(bar1_state[index].ref_count < 0))
-                                panic("dma_map_single: "
-                                      "Bar1[%d] reference count overflowed\n",
-                                      (int) index);
-                        result = (index << 22) | (physical & ((1 << 22) - 1));
-                        /* Large BAR1 is offset at 2GB */
-                        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
-                                result += 2ul << 30;
-                        goto done_unlock;
-                }
-        }
+        mb();
 
-        /* No existing mappings, look for a free entry */
-        for (index = start_index; index >= 0; index--) {
-                if (unlikely(bar1_state[index].ref_count == 0)) {
-                        union cvmx_pci_bar1_indexx bar1_index;
-                        /* We have a free entry, use it */
-                        bar1_state[index].ref_count = 1;
-                        bar1_state[index].address_bits = physical >> 22;
-                        bar1_index.u32 = 0;
-                        /* Address bits[35:22] sent to L2C */
-                        bar1_index.s.addr_idx = physical >> 22;
-                        /* Don't put PCI accesses in L2. */
-                        bar1_index.s.ca = 1;
-                        /* Endian Swap Mode */
-                        bar1_index.s.end_swp = 1;
-                        /* Set '1' when the selected address range is valid. */
-                        bar1_index.s.addr_v = 1;
-                        octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
-                                           bar1_index.u32);
-                        /* An existing mapping will work, use it */
-                        result = (index << 22) | (physical & ((1 << 22) - 1));
-                        /* Large BAR1 is offset at 2GB */
-                        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
-                                result += 2ul << 30;
-                        goto done_unlock;
-                }
-        }
+        return ret;
+}
 
-        pr_err("dma_map_single: "
-               "Can't find empty BAR1 index for physical mapping 0x%llx\n",
-               (unsigned long long) physical);
+static void octeon_dma_free_coherent(struct device *dev, size_t size,
+        void *vaddr, dma_addr_t dma_handle)
+{
+        int order = get_order(size);
 
-done_unlock:
-        raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
-        pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
-        return result;
-#endif
+        if (dma_release_from_coherent(dev, order, vaddr))
+                return;
+
+        swiotlb_free_coherent(dev, size, vaddr, dma_handle);
 }
 
-void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static dma_addr_t octeon_unity_phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
-#ifndef CONFIG_PCI
-        /*
-         * Without PCI/PCIe this function can be called for Octeon internal
-         * devices such as USB. These devices all support 64bit addressing.
-         */
-        return;
-#else
-        unsigned long flags;
-        uint64_t index;
+        return paddr;
+}
 
+static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr;
+}
+
+struct octeon_dma_map_ops {
+        struct dma_map_ops dma_map_ops;
+        dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
+        phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
+};
+
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+                                                      struct octeon_dma_map_ops,
+                                                      dma_map_ops);
+
+        return ops->phys_to_dma(dev, paddr);
+}
+EXPORT_SYMBOL(phys_to_dma);
+
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        struct octeon_dma_map_ops *ops = container_of(get_dma_ops(dev),
+                                                      struct octeon_dma_map_ops,
+                                                      dma_map_ops);
+
+        return ops->dma_to_phys(dev, daddr);
+}
+EXPORT_SYMBOL(dma_to_phys);
+
+static struct octeon_dma_map_ops octeon_linear_dma_map_ops = {
+        .dma_map_ops = {
+                .alloc_coherent = octeon_dma_alloc_coherent,
+                .free_coherent = octeon_dma_free_coherent,
+                .map_page = octeon_dma_map_page,
+                .unmap_page = swiotlb_unmap_page,
+                .map_sg = octeon_dma_map_sg,
+                .unmap_sg = swiotlb_unmap_sg_attrs,
+                .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+                .sync_single_for_device = octeon_dma_sync_single_for_device,
+                .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+                .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+                .mapping_error = swiotlb_dma_mapping_error,
+                .dma_supported = swiotlb_dma_supported
+        },
+        .phys_to_dma = octeon_unity_phys_to_dma,
+        .dma_to_phys = octeon_unity_dma_to_phys
+};
+
+char *octeon_swiotlb;
+
+void __init plat_swiotlb_setup(void)
+{
+        int i;
+        phys_t max_addr;
+        phys_t addr_size;
+        size_t swiotlbsize;
+        unsigned long swiotlb_nslabs;
+
+        max_addr = 0;
+        addr_size = 0;
+
+        for (i = 0 ; i < boot_mem_map.nr_map; i++) {
+                struct boot_mem_map_entry *e = &boot_mem_map.map[i];
+                if (e->type != BOOT_MEM_RAM)
+                        continue;
+
+                /* These addresses map low for PCI. */
+                if (e->addr > 0x410000000ull)
+                        continue;
+
+                addr_size += e->size;
+
+                if (max_addr < e->addr + e->size)
+                        max_addr = e->addr + e->size;
+
+        }
+
+        swiotlbsize = PAGE_SIZE;
+
+#ifdef CONFIG_PCI
         /*
-         * Platform devices, such as the internal USB, skip all
-         * translation and use Octeon physical addresses directly.
+         * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
+         * size to a maximum of 64MB
          */
-        if (dev->bus == &platform_bus_type)
-                return;
+        if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+            || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+                swiotlbsize = addr_size / 4;
+                if (swiotlbsize > 64 * (1<<20))
+                        swiotlbsize = 64 * (1<<20);
+        } else if (max_addr > 0xf0000000ul) {
+                /*
+                 * Otherwise only allocate a big iotlb if there is
+                 * memory past the BAR1 hole.
+                 */
+                swiotlbsize = 64 * (1<<20);
+        }
+#endif
+        swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
+        swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
+        swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
+
+        octeon_swiotlb = alloc_bootmem_low_pages(swiotlbsize);
 
+        swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1);
+
+        mips_dma_map_ops = &octeon_linear_dma_map_ops.dma_map_ops;
+}
+
+#ifdef CONFIG_PCI
+static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = {
+        .dma_map_ops = {
+                .alloc_coherent = octeon_dma_alloc_coherent,
+                .free_coherent = octeon_dma_free_coherent,
+                .map_page = octeon_dma_map_page,
+                .unmap_page = swiotlb_unmap_page,
+                .map_sg = octeon_dma_map_sg,
+                .unmap_sg = swiotlb_unmap_sg_attrs,
+                .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+                .sync_single_for_device = octeon_dma_sync_single_for_device,
+                .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+                .sync_sg_for_device = octeon_dma_sync_sg_for_device,
+                .mapping_error = swiotlb_dma_mapping_error,
+                .dma_supported = swiotlb_dma_supported
+        },
+};
+
+struct dma_map_ops *octeon_pci_dma_map_ops;
+
+void __init octeon_pci_dma_init(void)
+{
         switch (octeon_dma_bar_type) {
         case OCTEON_DMA_BAR_TYPE_PCIE:
-                /* Nothing to do, all mappings are static */
-                goto done;
-
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
+                break;
         case OCTEON_DMA_BAR_TYPE_BIG:
-#ifdef CONFIG_64BIT
-                /* Nothing to do for addresses using BAR2 */
-                if (dma_addr >= BAR2_PCI_ADDRESS)
-                        goto done;
-#endif
-                if (unlikely(dma_addr < (4ul << 10)))
-                        panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
-                              dma_addr);
-                else if (dma_addr < (2ul << 30))
-                        /* Nothing to do for addresses using BAR0 */
-                        goto done;
-                else if (dma_addr < (2ul << 30) + (128ul << 20))
-                        /* Need to unmap, fall through */
-                        index = (dma_addr - (2ul << 30)) >> 22;
-                else if (dma_addr <
-                         (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
-                        goto done;      /* Nothing to do for the rest of BAR1 */
-                else
-                        panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
-                              dma_addr);
-                /* Continued below switch statement */
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_big_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_big_dma_to_phys;
                 break;
-
         case OCTEON_DMA_BAR_TYPE_SMALL:
-#ifdef CONFIG_64BIT
-                /* Nothing to do for addresses using BAR2 */
-                if (dma_addr >= BAR2_PCI_ADDRESS)
-                        goto done;
-#endif
-                index = dma_addr >> 22;
-                /* Continued below switch statement */
+                _octeon_pci_dma_map_ops.phys_to_dma = octeon_small_phys_to_dma;
+                _octeon_pci_dma_map_ops.dma_to_phys = octeon_small_dma_to_phys;
                 break;
-
         default:
-                panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
+                BUG();
         }
-
-        if (unlikely(index > 31))
-                panic("dma_unmap_single: "
-                      "Attempt to unmap an invalid address (0x%llx)\n",
-                      dma_addr);
-
-        raw_spin_lock_irqsave(&bar1_lock, flags);
-        bar1_state[index].ref_count--;
-        if (bar1_state[index].ref_count == 0)
-                octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
-        else if (unlikely(bar1_state[index].ref_count < 0))
-                panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
-                      (int) index);
-        raw_spin_unlock_irqrestore(&bar1_lock, flags);
-done:
-        pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
-        return;
-#endif
+        octeon_pci_dma_map_ops = &_octeon_pci_dma_map_ops.dma_map_ops;
 }
+#endif /* CONFIG_PCI */
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 6abe56f1e097..d38246e33ddb 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -26,8 +26,8 @@
  ***********************license end**************************************/
 
 /*
- * Implementation of the Level 2 Cache (L2C) control, measurement, and
- * debugging facilities.
+ * Implementation of the Level 2 Cache (L2C) control,
+ * measurement, and debugging facilities.
  */
 
 #include <asm/octeon/cvmx.h>
@@ -42,13 +42,7 @@
  * if multiple applications or operating systems are running, then it
  * is up to the user program to coordinate between them.
  */
-static cvmx_spinlock_t cvmx_l2c_spinlock;
-
-static inline int l2_size_half(void)
-{
-        uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
-        return !!(val & (1ull << 34));
-}
+cvmx_spinlock_t cvmx_l2c_spinlock;
 
 int cvmx_l2c_get_core_way_partition(uint32_t core)
 {
@@ -58,6 +52,9 @@ int cvmx_l2c_get_core_way_partition(uint32_t core)
         if (core >= cvmx_octeon_num_cores())
                 return -1;
 
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return cvmx_read_csr(CVMX_L2C_WPAR_PPX(core)) & 0xffff;
+
         /*
          * Use the lower two bits of the coreNumber to determine the
          * bit offset of the UMSK[] field in the L2C_SPAR register.
@@ -71,17 +68,13 @@ int cvmx_l2c_get_core_way_partition(uint32_t core)
 
         switch (core & 0xC) {
         case 0x0:
-                return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >> field;
         case 0x4:
-                return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >> field;
         case 0x8:
-                return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >> field;
         case 0xC:
-                return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >>
-                        field;
+                return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >> field;
         }
         return 0;
 }
@@ -95,48 +88,50 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
 
         mask &= valid_mask;
 
-        /* A UMSK setting which blocks all L2C Ways is an error. */
-        if (mask == valid_mask)
+        /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+        if (mask == valid_mask && !OCTEON_IS_MODEL(OCTEON_CN63XX))
                 return -1;
 
         /* Validate the core number */
         if (core >= cvmx_octeon_num_cores())
                 return -1;
 
-        /* Check to make sure current mask & new mask don't block all ways */
-        if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) ==
-            valid_mask)
-                return -1;
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                cvmx_write_csr(CVMX_L2C_WPAR_PPX(core), mask);
+                return 0;
+        }
 
-        /* Use the lower two bits of core to determine the bit offset of the
+        /*
+         * Use the lower two bits of core to determine the bit offset of the
          * UMSK[] field in the L2C_SPAR register.
          */
         field = (core & 0x3) * 8;
 
-        /* Assign the new mask setting to the UMSK[] field in the appropriate
+        /*
+         * Assign the new mask setting to the UMSK[] field in the appropriate
          * L2C_SPAR register based on the core_num.
          *
          */
         switch (core & 0xC) {
         case 0x0:
                 cvmx_write_csr(CVMX_L2C_SPAR0,
-                               (cvmx_read_csr(CVMX_L2C_SPAR0) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR0) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         case 0x4:
                 cvmx_write_csr(CVMX_L2C_SPAR1,
-                               (cvmx_read_csr(CVMX_L2C_SPAR1) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR1) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         case 0x8:
                 cvmx_write_csr(CVMX_L2C_SPAR2,
-                               (cvmx_read_csr(CVMX_L2C_SPAR2) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR2) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         case 0xC:
                 cvmx_write_csr(CVMX_L2C_SPAR3,
-                               (cvmx_read_csr(CVMX_L2C_SPAR3) &
-                                ~(0xFF << field)) | mask << field);
+                               (cvmx_read_csr(CVMX_L2C_SPAR3) & ~(0xFF << field)) |
+                               mask << field);
                 break;
         }
         return 0;
@@ -146,84 +141,137 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
 {
         uint32_t valid_mask;
 
-        valid_mask = 0xff;
-
-        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) {
-                if (l2_size_half())
-                        valid_mask = 0xf;
-        } else if (l2_size_half())
-                valid_mask = 0x3;
-
+        valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
         mask &= valid_mask;
 
-        /* A UMSK setting which blocks all L2C Ways is an error. */
-        if (mask == valid_mask)
-                return -1;
-        /* Check to make sure current mask & new mask don't block all ways */
-        if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) ==
-            valid_mask)
+        /* A UMSK setting which blocks all L2C Ways is an error on some chips */
+        if (mask == valid_mask  && !OCTEON_IS_MODEL(OCTEON_CN63XX))
                 return -1;
 
-        cvmx_write_csr(CVMX_L2C_SPAR4,
-                       (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                cvmx_write_csr(CVMX_L2C_WPAR_IOBX(0), mask);
+        else
+                cvmx_write_csr(CVMX_L2C_SPAR4,
+                               (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
         return 0;
 }
 
 int cvmx_l2c_get_hw_way_partition(void)
 {
-        return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return cvmx_read_csr(CVMX_L2C_WPAR_IOBX(0)) & 0xffff;
+        else
+                return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
 }
 
 void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
                           uint32_t clear_on_read)
 {
-        union cvmx_l2c_pfctl pfctl;
+        if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                union cvmx_l2c_pfctl pfctl;
 
-        pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
+                pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
 
-        switch (counter) {
-        case 0:
-                pfctl.s.cnt0sel = event;
-                pfctl.s.cnt0ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                switch (counter) {
+                case 0:
+                        pfctl.s.cnt0sel = event;
+                        pfctl.s.cnt0ena = 1;
                         pfctl.s.cnt0rdclr = clear_on_read;
-                break;
-        case 1:
-                pfctl.s.cnt1sel = event;
-                pfctl.s.cnt1ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                        break;
+                case 1:
+                        pfctl.s.cnt1sel = event;
+                        pfctl.s.cnt1ena = 1;
                         pfctl.s.cnt1rdclr = clear_on_read;
-                break;
-        case 2:
-                pfctl.s.cnt2sel = event;
-                pfctl.s.cnt2ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                        break;
+                case 2:
+                        pfctl.s.cnt2sel = event;
+                        pfctl.s.cnt2ena = 1;
                         pfctl.s.cnt2rdclr = clear_on_read;
-                break;
-        case 3:
-        default:
-                pfctl.s.cnt3sel = event;
-                pfctl.s.cnt3ena = 1;
-                if (!cvmx_octeon_is_pass1())
+                        break;
+                case 3:
+                default:
+                        pfctl.s.cnt3sel = event;
+                        pfctl.s.cnt3ena = 1;
                         pfctl.s.cnt3rdclr = clear_on_read;
-                break;
-        }
+                        break;
+                }
 
-        cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+                cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
+        } else {
+                union cvmx_l2c_tadx_prf l2c_tadx_prf;
+                int tad;
+
+                cvmx_dprintf("L2C performance counter events are different for this chip, mapping 'event' to cvmx_l2c_tad_event_t\n");
+                if (clear_on_read)
+                        cvmx_dprintf("L2C counters don't support clear on read for this chip\n");
+
+                l2c_tadx_prf.u64 = cvmx_read_csr(CVMX_L2C_TADX_PRF(0));
+
+                switch (counter) {
+                case 0:
+                        l2c_tadx_prf.s.cnt0sel = event;
+                        break;
+                case 1:
+                        l2c_tadx_prf.s.cnt1sel = event;
+                        break;
+                case 2:
+                        l2c_tadx_prf.s.cnt2sel = event;
+                        break;
+                default:
+                case 3:
+                        l2c_tadx_prf.s.cnt3sel = event;
+                        break;
+                }
+                for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                        cvmx_write_csr(CVMX_L2C_TADX_PRF(tad),
+                                       l2c_tadx_prf.u64);
+        }
 }
 
 uint64_t cvmx_l2c_read_perf(uint32_t counter)
 {
         switch (counter) {
         case 0:
-                return cvmx_read_csr(CVMX_L2C_PFC0);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC0);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC0(tad));
+                        return counter;
+                }
         case 1:
-                return cvmx_read_csr(CVMX_L2C_PFC1);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC1);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC1(tad));
+                        return counter;
+                }
         case 2:
-                return cvmx_read_csr(CVMX_L2C_PFC2);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC2);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC2(tad));
+                        return counter;
+                }
         case 3:
         default:
-                return cvmx_read_csr(CVMX_L2C_PFC3);
+                if (OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        return cvmx_read_csr(CVMX_L2C_PFC3);
+                else {
+                        uint64_t counter = 0;
+                        int tad;
+                        for (tad = 0; tad < CVMX_L2C_TADS; tad++)
+                                counter += cvmx_read_csr(CVMX_L2C_TADX_PFC3(tad));
+                        return counter;
+                }
         }
 }
 
@@ -240,7 +288,7 @@ static void fault_in(uint64_t addr, int len)
         volatile char dummy;
         /*
          * Adjust addr and length so we get all cache lines even for
-         * small ranges spanning two cache lines
+         * small ranges spanning two cache lines.
          */
         len += addr & CVMX_CACHE_LINE_MASK;
         addr &= ~CVMX_CACHE_LINE_MASK;
@@ -259,67 +307,100 @@ static void fault_in(uint64_t addr, int len)
 
 int cvmx_l2c_lock_line(uint64_t addr)
 {
-        int retval = 0;
-        union cvmx_l2c_dbg l2cdbg;
-        union cvmx_l2c_lckbase lckbase;
-        union cvmx_l2c_lckoff lckoff;
-        union cvmx_l2t_err l2t_err;
-        l2cdbg.u64 = 0;
-        lckbase.u64 = 0;
-        lckoff.u64 = 0;
-
-        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-
-        /* Clear l2t error bits if set */
-        l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-        l2t_err.s.lckerr = 1;
-        l2t_err.s.lckerr2 = 1;
-        cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                int shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+                uint64_t assoc = cvmx_l2c_get_num_assoc();
+                uint64_t tag = addr >> shift;
+                uint64_t index = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, cvmx_l2c_address_to_index(addr) << CVMX_L2C_IDX_ADDR_SHIFT);
+                uint64_t way;
+                union cvmx_l2c_tadx_tag l2c_tadx_tag;
+
+                CVMX_CACHE_LCKL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, addr), 0);
+
+                /* Make sure we were able to lock the line */
+                for (way = 0; way < assoc; way++) {
+                        CVMX_CACHE_LTGL2I(index | (way << shift), 0);
+                        /* make sure CVMX_L2C_TADX_TAG is updated */
+                        CVMX_SYNC;
+                        l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+                        if (l2c_tadx_tag.s.valid && l2c_tadx_tag.s.tag == tag)
+                                break;
+                }
 
-        addr &= ~CVMX_CACHE_LINE_MASK;
+                /* Check if a valid line is found */
+                if (way >= assoc) {
+                        /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: line not found for locking at 0x%llx address\n", (unsigned long long)addr); */
+                        return -1;
+                }
 
-        /* Set this core as debug core */
-        l2cdbg.s.ppnum = cvmx_get_core_num();
-        CVMX_SYNC;
-        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-        cvmx_read_csr(CVMX_L2C_DBG);
-
-        lckoff.s.lck_offset = 0;        /* Only lock 1 line at a time */
-        cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
-        cvmx_read_csr(CVMX_L2C_LCKOFF);
-
-        if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
-                int alias_shift =
-                    CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
-                uint64_t addr_tmp =
-                    addr ^ (addr & ((1 << alias_shift) - 1)) >>
-                    CVMX_L2_SET_BITS;
-                lckbase.s.lck_base = addr_tmp >> 7;
+                /* Check if lock bit is not set */
+                if (!l2c_tadx_tag.s.lock) {
+                        /* cvmx_dprintf("ERROR: cvmx_l2c_lock_line: Not able to lock at 0x%llx address\n", (unsigned long long)addr); */
+                        return -1;
+                }
+                return way;
         } else {
-                lckbase.s.lck_base = addr >> 7;
-        }
+                int retval = 0;
+                union cvmx_l2c_dbg l2cdbg;
+                union cvmx_l2c_lckbase lckbase;
+                union cvmx_l2c_lckoff lckoff;
+                union cvmx_l2t_err l2t_err;
 
-        lckbase.s.lck_ena = 1;
-        cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-        cvmx_read_csr(CVMX_L2C_LCKBASE);        /* Make sure it gets there */
+                cvmx_spinlock_lock(&cvmx_l2c_spinlock);
 
-        fault_in(addr, CVMX_CACHE_LINE_SIZE);
+                l2cdbg.u64 = 0;
+                lckbase.u64 = 0;
+                lckoff.u64 = 0;
 
-        lckbase.s.lck_ena = 0;
-        cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
-        cvmx_read_csr(CVMX_L2C_LCKBASE);        /* Make sure it gets there */
+                /* Clear l2t error bits if set */
+                l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+                l2t_err.s.lckerr = 1;
+                l2t_err.s.lckerr2 = 1;
+                cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
 
-        /* Stop being debug core */
-        cvmx_write_csr(CVMX_L2C_DBG, 0);
-        cvmx_read_csr(CVMX_L2C_DBG);
+                addr &= ~CVMX_CACHE_LINE_MASK;
 
-        l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
-        if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
-                retval = 1;     /* We were unable to lock the line */
+                /* Set this core as debug core */
+                l2cdbg.s.ppnum = cvmx_get_core_num();
+                CVMX_SYNC;
+                cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+                cvmx_read_csr(CVMX_L2C_DBG);
+
+                lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
+                cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
+                cvmx_read_csr(CVMX_L2C_LCKOFF);
+
+                if (((union cvmx_l2c_cfg)(cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
+                        int alias_shift = CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
+                        uint64_t addr_tmp = addr ^ (addr & ((1 << alias_shift) - 1)) >> CVMX_L2_SET_BITS;
+                        lckbase.s.lck_base = addr_tmp >> 7;
+                } else {
+                        lckbase.s.lck_base = addr >> 7;
+                }
 
-        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+                lckbase.s.lck_ena = 1;
+                cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+                /* Make sure it gets there */
+                cvmx_read_csr(CVMX_L2C_LCKBASE);
 
-        return retval;
+                fault_in(addr, CVMX_CACHE_LINE_SIZE);
+
+                lckbase.s.lck_ena = 0;
+                cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
+                /* Make sure it gets there */
+                cvmx_read_csr(CVMX_L2C_LCKBASE);
+
+                /* Stop being debug core */
+                cvmx_write_csr(CVMX_L2C_DBG, 0);
+                cvmx_read_csr(CVMX_L2C_DBG);
+
+                l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
+                if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
+                        retval = 1;  /* We were unable to lock the line */
+
+                cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+                return retval;
+        }
 }
 
 int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
@@ -336,7 +417,6 @@ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
                 start += CVMX_CACHE_LINE_SIZE;
                 len -= CVMX_CACHE_LINE_SIZE;
         }
-
         return retval;
 }
 
@@ -344,80 +424,73 @@ void cvmx_l2c_flush(void)
 {
         uint64_t assoc, set;
         uint64_t n_assoc, n_set;
-        union cvmx_l2c_dbg l2cdbg;
-
-        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
 
-        l2cdbg.u64 = 0;
-        if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
-                l2cdbg.s.ppnum = cvmx_get_core_num();
-        l2cdbg.s.finv = 1;
-        n_set = CVMX_L2_SETS;
-        n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC;
-        for (set = 0; set < n_set; set++) {
-                for (assoc = 0; assoc < n_assoc; assoc++) {
-                        l2cdbg.s.set = assoc;
-                        /* Enter debug mode, and make sure all other
-                         ** writes complete before we enter debug
-                         ** mode */
-                        CVMX_SYNCW;
-                        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-                        cvmx_read_csr(CVMX_L2C_DBG);
-
-                        CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
-                                               (CVMX_MIPS_SPACE_XKPHYS,
-                                                set * CVMX_CACHE_LINE_SIZE), 0);
-                        CVMX_SYNCW;     /* Push STF out to L2 */
-                        /* Exit debug mode */
-                        CVMX_SYNC;
-                        cvmx_write_csr(CVMX_L2C_DBG, 0);
-                        cvmx_read_csr(CVMX_L2C_DBG);
+        n_set = cvmx_l2c_get_num_sets();
+        n_assoc = cvmx_l2c_get_num_assoc();
+
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                uint64_t address;
+                /* These may look like constants, but they aren't... */
+                int assoc_shift = CVMX_L2C_TAG_ADDR_ALIAS_SHIFT;
+                int set_shift = CVMX_L2C_IDX_ADDR_SHIFT;
+                for (set = 0; set < n_set; set++) {
+                        for (assoc = 0; assoc < n_assoc; assoc++) {
+                                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                       (assoc << assoc_shift) | (set << set_shift));
+                                CVMX_CACHE_WBIL2I(address, 0);
+                        }
                 }
+        } else {
+                for (set = 0; set < n_set; set++)
+                        for (assoc = 0; assoc < n_assoc; assoc++)
+                                cvmx_l2c_flush_line(assoc, set);
         }
-
-        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
 }
 
+
 int cvmx_l2c_unlock_line(uint64_t address)
 {
-        int assoc;
-        union cvmx_l2c_tag tag;
-        union cvmx_l2c_dbg l2cdbg;
-        uint32_t tag_addr;
 
-        uint32_t index = cvmx_l2c_address_to_index(address);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                int assoc;
+                union cvmx_l2c_tag tag;
+                uint32_t tag_addr;
+                uint32_t index = cvmx_l2c_address_to_index(address);
+
+                tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+
+                /*
+                 * For 63XX, we can flush a line by using the physical
+                 * address directly, so finding the cache line used by
+                 * the address is only required to provide the proper
+                 * return value for the function.
+                 */
+                for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+                        tag = cvmx_l2c_get_tag(assoc, index);
+
+                        if (tag.s.V && (tag.s.addr == tag_addr)) {
+                                CVMX_CACHE_WBIL2(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, address), 0);
+                                return tag.s.L;
+                        }
+                }
+        } else {
+                int assoc;
+                union cvmx_l2c_tag tag;
+                uint32_t tag_addr;
 
-        cvmx_spinlock_lock(&cvmx_l2c_spinlock);
-        /* Compute portion of address that is stored in tag */
-        tag_addr =
-            ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) &
-             ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
-        for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
-                tag = cvmx_get_l2c_tag(assoc, index);
+                uint32_t index = cvmx_l2c_address_to_index(address);
 
-                if (tag.s.V && (tag.s.addr == tag_addr)) {
-                        l2cdbg.u64 = 0;
-                        l2cdbg.s.ppnum = cvmx_get_core_num();
-                        l2cdbg.s.set = assoc;
-                        l2cdbg.s.finv = 1;
+                /* Compute portion of address that is stored in tag */
+                tag_addr = ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) & ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
+                for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
+                        tag = cvmx_l2c_get_tag(assoc, index);
 
-                        CVMX_SYNC;
-                        /* Enter debug mode */
-                        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-                        cvmx_read_csr(CVMX_L2C_DBG);
-
-                        CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
-                                               (CVMX_MIPS_SPACE_XKPHYS,
-                                                address), 0);
-                        CVMX_SYNC;
-                        /* Exit debug mode */
-                        cvmx_write_csr(CVMX_L2C_DBG, 0);
-                        cvmx_read_csr(CVMX_L2C_DBG);
-                        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
-                        return tag.s.L;
+                        if (tag.s.V && (tag.s.addr == tag_addr)) {
+                                cvmx_l2c_flush_line(assoc, index);
+                                return tag.s.L;
+                        }
                 }
         }
-        cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
         return 0;
 }
 
@@ -445,48 +518,49 @@ union __cvmx_l2c_tag {
         uint64_t u64;
         struct cvmx_l2c_tag_cn50xx {
                 uint64_t reserved:40;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:20;       /* Phys mem addr (33..14) */
         } cn50xx;
         struct cvmx_l2c_tag_cn30xx {
                 uint64_t reserved:41;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:19;       /* Phys mem addr (33..15) */
         } cn30xx;
         struct cvmx_l2c_tag_cn31xx {
                 uint64_t reserved:42;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:18;       /* Phys mem addr (33..16) */
         } cn31xx;
         struct cvmx_l2c_tag_cn38xx {
                 uint64_t reserved:43;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:17;       /* Phys mem addr (33..17) */
         } cn38xx;
         struct cvmx_l2c_tag_cn58xx {
                 uint64_t reserved:44;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:16;       /* Phys mem addr (33..18) */
         } cn58xx;
         struct cvmx_l2c_tag_cn58xx cn56xx;      /* 2048 sets */
         struct cvmx_l2c_tag_cn31xx cn52xx;      /* 512 sets */
 };
 
+
 /**
  * @INTERNAL
  * Function to read a L2C tag.  This code make the current core
@@ -503,7 +577,7 @@ union __cvmx_l2c_tag {
 static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
 {
 
-        uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
+        uint64_t debug_tag_addr = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, (index << 7) + 96);
         uint64_t core = cvmx_get_core_num();
         union __cvmx_l2c_tag tag_val;
         uint64_t dbg_addr = CVMX_L2C_DBG;
@@ -512,12 +586,15 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
         union cvmx_l2c_dbg debug_val;
         debug_val.u64 = 0;
         /*
-         * For low core count parts, the core number is always small enough
-         * to stay in the correct field and not set any reserved bits.
+         * For low core count parts, the core number is always small
+         * enough to stay in the correct field and not set any
+         * reserved bits.
          */
         debug_val.s.ppnum = core;
         debug_val.s.l2t = 1;
         debug_val.s.set = assoc;
+
+        local_irq_save(flags);
         /*
          * Make sure core is quiet (no prefetches, etc.) before
          * entering debug mode.
@@ -526,112 +603,139 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
         /* Flush L1 to make sure debug load misses L1 */
         CVMX_DCACHE_INVALIDATE;
 
-        local_irq_save(flags);
-
         /*
          * The following must be done in assembly as when in debug
          * mode all data loads from L2 return special debug data, not
-         * normal memory contents.  Also, interrupts must be
-         * disabled, since if an interrupt occurs while in debug mode
-         * the ISR will get debug data from all its memory reads
-         * instead of the contents of memory
+         * normal memory contents.  Also, interrupts must be disabled,
+         * since if an interrupt occurs while in debug mode the ISR
+         * will get debug data from all its memory * reads instead of
+         * the contents of memory.
          */
 
-        asm volatile (".set push              \n"
-                "        .set mips64              \n"
-                "        .set noreorder           \n"
-                /* Enter debug mode, wait for store */
-                "        sd    %[dbg_val], 0(%[dbg_addr])  \n"
-                "        ld    $0, 0(%[dbg_addr]) \n"
-                /* Read L2C tag data */
-                "        ld    %[tag_val], 0(%[tag_addr]) \n"
-                /* Exit debug mode, wait for store */
-                "        sd    $0, 0(%[dbg_addr])  \n"
-                "        ld    $0, 0(%[dbg_addr]) \n"
-                /* Invalidate dcache to discard debug data */
-                "        cache 9, 0($0) \n"
-                "        .set pop" :
-                [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr),
-                [dbg_val] "r"(debug_val.u64),
-                [tag_addr] "r"(debug_tag_addr) : "memory");
+        asm volatile (
+                ".set push\n\t"
+                ".set mips64\n\t"
+                ".set noreorder\n\t"
+                "sd    %[dbg_val], 0(%[dbg_addr])\n\t"   /* Enter debug mode, wait for store */
+                "ld    $0, 0(%[dbg_addr])\n\t"
+                "ld    %[tag_val], 0(%[tag_addr])\n\t"   /* Read L2C tag data */
+                "sd    $0, 0(%[dbg_addr])\n\t"          /* Exit debug mode, wait for store */
+                "ld    $0, 0(%[dbg_addr])\n\t"
+                "cache 9, 0($0)\n\t"             /* Invalidate dcache to discard debug data */
+                ".set pop"
+                : [tag_val] "=r" (tag_val)
+                : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
+                : "memory");
 
         local_irq_restore(flags);
-        return tag_val;
 
+        return tag_val;
 }
 
+
 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
 {
-        union __cvmx_l2c_tag tmp_tag;
         union cvmx_l2c_tag tag;
         tag.u64 = 0;
 
         if ((int)association >= cvmx_l2c_get_num_assoc()) {
-                cvmx_dprintf
-                    ("ERROR: cvmx_get_l2c_tag association out of range\n");
+                cvmx_dprintf("ERROR: cvmx_l2c_get_tag association out of range\n");
                 return tag;
         }
         if ((int)index >= cvmx_l2c_get_num_sets()) {
-                cvmx_dprintf("ERROR: cvmx_get_l2c_tag "
-                             "index out of range (arg: %d, max: %d\n",
-                     index, cvmx_l2c_get_num_sets());
+                cvmx_dprintf("ERROR: cvmx_l2c_get_tag index out of range (arg: %d, max: %d)\n",
+                             (int)index, cvmx_l2c_get_num_sets());
                 return tag;
         }
-        /* __read_l2_tag is intended for internal use only */
-        tmp_tag = __read_l2_tag(association, index);
-
-        /*
-         * Convert all tag structure types to generic version, as it
-         * can represent all models.
-         */
-        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
-                tag.s.V = tmp_tag.cn58xx.V;
-                tag.s.D = tmp_tag.cn58xx.D;
-                tag.s.L = tmp_tag.cn58xx.L;
-                tag.s.U = tmp_tag.cn58xx.U;
-                tag.s.addr = tmp_tag.cn58xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
-                tag.s.V = tmp_tag.cn38xx.V;
-                tag.s.D = tmp_tag.cn38xx.D;
-                tag.s.L = tmp_tag.cn38xx.L;
-                tag.s.U = tmp_tag.cn38xx.U;
-                tag.s.addr = tmp_tag.cn38xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
-                   || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
-                tag.s.V = tmp_tag.cn31xx.V;
-                tag.s.D = tmp_tag.cn31xx.D;
-                tag.s.L = tmp_tag.cn31xx.L;
-                tag.s.U = tmp_tag.cn31xx.U;
-                tag.s.addr = tmp_tag.cn31xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
-                tag.s.V = tmp_tag.cn30xx.V;
-                tag.s.D = tmp_tag.cn30xx.D;
-                tag.s.L = tmp_tag.cn30xx.L;
-                tag.s.U = tmp_tag.cn30xx.U;
-                tag.s.addr = tmp_tag.cn30xx.addr;
-        } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
-                tag.s.V = tmp_tag.cn50xx.V;
-                tag.s.D = tmp_tag.cn50xx.D;
-                tag.s.L = tmp_tag.cn50xx.L;
-                tag.s.U = tmp_tag.cn50xx.U;
-                tag.s.addr = tmp_tag.cn50xx.addr;
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                union cvmx_l2c_tadx_tag l2c_tadx_tag;
+                uint64_t address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                (association << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                                                (index << CVMX_L2C_IDX_ADDR_SHIFT));
+                /*
+                 * Use L2 cache Index load tag cache instruction, as
+                 * hardware loads the virtual tag for the L2 cache
+                 * block with the contents of L2C_TAD0_TAG
+                 * register.
+                 */
+                CVMX_CACHE_LTGL2I(address, 0);
+                CVMX_SYNC;   /* make sure CVMX_L2C_TADX_TAG is updated */
+                l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
+
+                tag.s.V     = l2c_tadx_tag.s.valid;
+                tag.s.D     = l2c_tadx_tag.s.dirty;
+                tag.s.L     = l2c_tadx_tag.s.lock;
+                tag.s.U     = l2c_tadx_tag.s.use;
+                tag.s.addr  = l2c_tadx_tag.s.tag;
         } else {
-                cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+                union __cvmx_l2c_tag tmp_tag;
+                /* __read_l2_tag is intended for internal use only */
+                tmp_tag = __read_l2_tag(association, index);
+
+                /*
+                 * Convert all tag structure types to generic version,
+                 * as it can represent all models.
+                 */
+                if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+                        tag.s.V    = tmp_tag.cn58xx.V;
+                        tag.s.D    = tmp_tag.cn58xx.D;
+                        tag.s.L    = tmp_tag.cn58xx.L;
+                        tag.s.U    = tmp_tag.cn58xx.U;
+                        tag.s.addr = tmp_tag.cn58xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+                        tag.s.V    = tmp_tag.cn38xx.V;
+                        tag.s.D    = tmp_tag.cn38xx.D;
+                        tag.s.L    = tmp_tag.cn38xx.L;
+                        tag.s.U    = tmp_tag.cn38xx.U;
+                        tag.s.addr = tmp_tag.cn38xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                        tag.s.V    = tmp_tag.cn31xx.V;
+                        tag.s.D    = tmp_tag.cn31xx.D;
+                        tag.s.L    = tmp_tag.cn31xx.L;
+                        tag.s.U    = tmp_tag.cn31xx.U;
+                        tag.s.addr = tmp_tag.cn31xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+                        tag.s.V    = tmp_tag.cn30xx.V;
+                        tag.s.D    = tmp_tag.cn30xx.D;
+                        tag.s.L    = tmp_tag.cn30xx.L;
+                        tag.s.U    = tmp_tag.cn30xx.U;
+                        tag.s.addr = tmp_tag.cn30xx.addr;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                        tag.s.V    = tmp_tag.cn50xx.V;
+                        tag.s.D    = tmp_tag.cn50xx.D;
+                        tag.s.L    = tmp_tag.cn50xx.L;
+                        tag.s.U    = tmp_tag.cn50xx.U;
+                        tag.s.addr = tmp_tag.cn50xx.addr;
+                } else {
+                        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
+                }
         }
-
         return tag;
 }
 
 uint32_t cvmx_l2c_address_to_index(uint64_t addr)
 {
         uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
-        union cvmx_l2c_cfg l2c_cfg;
-        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+        int indxalias = 0;
 
-        if (l2c_cfg.s.idxalias) {
-                idx ^=
-                    ((addr & CVMX_L2C_ALIAS_MASK) >>
-                     CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                union cvmx_l2c_ctl l2c_ctl;
+                l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);
+                indxalias = !l2c_ctl.s.disidxalias;
+        } else {
+                union cvmx_l2c_cfg l2c_cfg;
+                l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+                indxalias = l2c_cfg.s.idxalias;
+        }
+
+        if (indxalias) {
+                if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                        uint32_t a_14_12 = (idx / (CVMX_L2C_MEMBANK_SELECT_SIZE/(1<<CVMX_L2C_IDX_ADDR_SHIFT))) & 0x7;
+                        idx ^= idx / cvmx_l2c_get_num_sets();
+                        idx ^= a_14_12;
+                } else {
+                        idx ^= ((addr & CVMX_L2C_ALIAS_MASK) >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
+                }
         }
         idx &= CVMX_L2C_IDX_MASK;
         return idx;
@@ -652,10 +756,9 @@ int cvmx_l2c_get_set_bits(void)
         int l2_set_bits;
         if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
                 l2_set_bits = 11;       /* 2048 sets */
-        else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+        else if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
                 l2_set_bits = 10;       /* 1024 sets */
-        else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
-                 || OCTEON_IS_MODEL(OCTEON_CN52XX))
+        else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
                 l2_set_bits = 9;        /* 512 sets */
         else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
                 l2_set_bits = 8;        /* 256 sets */
@@ -666,7 +769,6 @@ int cvmx_l2c_get_set_bits(void)
                 l2_set_bits = 11;       /* 2048 sets */
         }
         return l2_set_bits;
-
 }
 
 /* Return the number of sets in the L2 Cache */
@@ -682,8 +784,11 @@ int cvmx_l2c_get_num_assoc(void)
         if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
             OCTEON_IS_MODEL(OCTEON_CN52XX) ||
             OCTEON_IS_MODEL(OCTEON_CN58XX) ||
-            OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX))
+            OCTEON_IS_MODEL(OCTEON_CN50XX) ||
+            OCTEON_IS_MODEL(OCTEON_CN38XX))
                 l2_assoc = 8;
+        else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+                l2_assoc = 16;
         else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
                  OCTEON_IS_MODEL(OCTEON_CN30XX))
                 l2_assoc = 4;
@@ -693,11 +798,42 @@ int cvmx_l2c_get_num_assoc(void)
         }
 
         /* Check to see if part of the cache is disabled */
-        if (cvmx_fuse_read(265))
-                l2_assoc = l2_assoc >> 2;
-        else if (cvmx_fuse_read(264))
-                l2_assoc = l2_assoc >> 1;
-
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                union cvmx_mio_fus_dat3 mio_fus_dat3;
+
+                mio_fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
+                /*
+                 * cvmx_mio_fus_dat3.s.l2c_crip fuses map as follows
+                 * <2> will be not used for 63xx
+                 * <1> disables 1/2 ways
+                 * <0> disables 1/4 ways
+                 * They are cumulative, so for 63xx:
+                 * <1> <0>
+                 * 0 0 16-way 2MB cache
+                 * 0 1 12-way 1.5MB cache
+                 * 1 0 8-way 1MB cache
+                 * 1 1 4-way 512KB cache
+                 */
+
+                if (mio_fus_dat3.s.l2c_crip == 3)
+                        l2_assoc = 4;
+                else if (mio_fus_dat3.s.l2c_crip == 2)
+                        l2_assoc = 8;
+                else if (mio_fus_dat3.s.l2c_crip == 1)
+                        l2_assoc = 12;
+        } else {
+                union cvmx_l2d_fus3 val;
+                val.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
+                /*
+                 * Using shifts here, as bit position names are
+                 * different for each model but they all mean the
+                 * same.
+                 */
+                if ((val.u64 >> 35) & 0x1)
+                        l2_assoc = l2_assoc >> 2;
+                else if ((val.u64 >> 34) & 0x1)
+                        l2_assoc = l2_assoc >> 1;
+        }
         return l2_assoc;
 }
 
@@ -711,24 +847,54 @@ int cvmx_l2c_get_num_assoc(void)
  */
 void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
 {
-        union cvmx_l2c_dbg l2cdbg;
+        /* Check the range of the index. */
+        if (index > (uint32_t)cvmx_l2c_get_num_sets()) {
+                cvmx_dprintf("ERROR: cvmx_l2c_flush_line index out of range.\n");
+                return;
+        }
 
-        l2cdbg.u64 = 0;
-        l2cdbg.s.ppnum = cvmx_get_core_num();
-        l2cdbg.s.finv = 1;
+        /* Check the range of association. */
+        if (assoc > (uint32_t)cvmx_l2c_get_num_assoc()) {
+                cvmx_dprintf("ERROR: cvmx_l2c_flush_line association out of range.\n");
+                return;
+        }
 
-        l2cdbg.s.set = assoc;
-        /*
-         * Enter debug mode, and make sure all other writes complete
-         * before we enter debug mode.
-         */
-        asm volatile ("sync" : : : "memory");
-        cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
-        cvmx_read_csr(CVMX_L2C_DBG);
-
-        CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0);
-        /* Exit debug mode */
-        asm volatile ("sync" : : : "memory");
-        cvmx_write_csr(CVMX_L2C_DBG, 0);
-        cvmx_read_csr(CVMX_L2C_DBG);
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
+                uint64_t address;
+                /* Create the address based on index and association.
+                 * Bits<20:17> select the way of the cache block involved in
+                 *             the operation
+                 * Bits<16:7> of the effect address select the index
+                 */
+                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                (assoc << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) |
+                                (index << CVMX_L2C_IDX_ADDR_SHIFT));
+                CVMX_CACHE_WBIL2I(address, 0);
+        } else {
+                union cvmx_l2c_dbg l2cdbg;
+
+                l2cdbg.u64 = 0;
+                if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
+                        l2cdbg.s.ppnum = cvmx_get_core_num();
+                l2cdbg.s.finv = 1;
+
+                l2cdbg.s.set = assoc;
+                cvmx_spinlock_lock(&cvmx_l2c_spinlock);
+                /*
+                 * Enter debug mode, and make sure all other writes
+                 * complete before we enter debug mode
+                 */
+                CVMX_SYNC;
+                cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
+                cvmx_read_csr(CVMX_L2C_DBG);
+
+                CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                    index * CVMX_CACHE_LINE_SIZE),
+                                       0);
+                /* Exit debug mode */
+                CVMX_SYNC;
+                cvmx_write_csr(CVMX_L2C_DBG, 0);
+                cvmx_read_csr(CVMX_L2C_DBG);
+                cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
+        }
 }
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 62ac30eef5e8..cecaf62aef32 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -3,13 +3,15 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2009 Cavium Networks
+ * Copyright (C) 2004-2010 Cavium Networks
  * Copyright (C) 2008 Wind River Systems
  */
 
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/i2c.h>
+#include <linux/usb.h>
+#include <linux/dma-mapping.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
@@ -198,7 +200,7 @@ static int __init octeon_i2c_device_init(void)
                 num_ports = 1;
 
         for (port = 0; port < num_ports; port++) {
-                octeon_i2c_data[port].sys_freq = octeon_get_clock_rate();
+                octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate();
                 /*FIXME: should be examined. At the moment is set for 100Khz */
                 octeon_i2c_data[port].i2c_freq = 100000;
 
@@ -301,6 +303,10 @@ static int __init octeon_mgmt_device_init(void)
                         ret = -ENOMEM;
                         goto out;
                 }
+                /* No DMA restrictions */
+                pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
+                pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
+
                 switch (port) {
                 case 0:
                         mgmt_port_resource.start = OCTEON_IRQ_MII0;
@@ -332,6 +338,108 @@ out:
 }
 device_initcall(octeon_mgmt_device_init);
 
+#ifdef CONFIG_USB
+
+static int __init octeon_ehci_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+
+        struct resource usb_resources[] = {
+                {
+                        .flags  = IORESOURCE_MEM,
+                }, {
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        /* Only Octeon2 has ehci/ohci */
+        if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return 0;
+
+        if (octeon_is_simulation() || usb_disabled())
+                return 0; /* No USB in the simulator. */
+
+        pd = platform_device_alloc("octeon-ehci", 0);
+        if (!pd) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        usb_resources[0].start = 0x00016F0000000000ULL;
+        usb_resources[0].end = usb_resources[0].start + 0x100;
+
+        usb_resources[1].start = OCTEON_IRQ_USB0;
+        usb_resources[1].end = OCTEON_IRQ_USB0;
+
+        ret = platform_device_add_resources(pd, usb_resources,
+                                            ARRAY_SIZE(usb_resources));
+        if (ret)
+                goto fail;
+
+        ret = platform_device_add(pd);
+        if (ret)
+                goto fail;
+
+        return ret;
+fail:
+        platform_device_put(pd);
+out:
+        return ret;
+}
+device_initcall(octeon_ehci_device_init);
+
+static int __init octeon_ohci_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+
+        struct resource usb_resources[] = {
+                {
+                        .flags  = IORESOURCE_MEM,
+                }, {
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        /* Only Octeon2 has ehci/ohci */
+        if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
+                return 0;
+
+        if (octeon_is_simulation() || usb_disabled())
+                return 0; /* No USB in the simulator. */
+
+        pd = platform_device_alloc("octeon-ohci", 0);
+        if (!pd) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        usb_resources[0].start = 0x00016F0000000400ULL;
+        usb_resources[0].end = usb_resources[0].start + 0x100;
+
+        usb_resources[1].start = OCTEON_IRQ_USB0;
+        usb_resources[1].end = OCTEON_IRQ_USB0;
+
+        ret = platform_device_add_resources(pd, usb_resources,
+                                            ARRAY_SIZE(usb_resources));
+        if (ret)
+                goto fail;
+
+        ret = platform_device_add(pd);
+        if (ret)
+                goto fail;
+
+        return ret;
+fail:
+        platform_device_put(pd);
+out:
+        return ret;
+}
+device_initcall(octeon_ohci_device_init);
+
+#endif /* CONFIG_USB */
+
 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 12dbf533b77d..057f0ae88c99 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -66,7 +66,7 @@ static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
                 /* Make simulator output fast*/
                 p->uartclk = 115200 * 16;
         else
-                p->uartclk = mips_hpt_frequency;
+                p->uartclk = octeon_get_io_clock_rate();
         p->serial_in = octeon_serial_in;
         p->serial_out = octeon_serial_out;
 }
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 69197cb6c7ea..b0c3686c96dd 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -33,6 +33,7 @@
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/pci-octeon.h>
+#include <asm/octeon/cvmx-mio-defs.h>
 
 #ifdef CONFIG_CAVIUM_DECODE_RSL
 extern void cvmx_interrupt_rsl_decode(void);
@@ -96,12 +97,21 @@ int octeon_is_pci_host(void)
  */
 uint64_t octeon_get_clock_rate(void)
 {
-        if (octeon_is_simulation())
-                octeon_bootinfo->eclock_hz = 6000000;
-        return octeon_bootinfo->eclock_hz;
+        struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
+
+        return sysinfo->cpu_clock_hz;
 }
 EXPORT_SYMBOL(octeon_get_clock_rate);
 
+static u64 octeon_io_clock_rate;
+
+u64 octeon_get_io_clock_rate(void)
+{
+        return octeon_io_clock_rate;
+}
+EXPORT_SYMBOL(octeon_get_io_clock_rate);
+
+
 /**
  * Write to the LCD display connected to the bootbus. This display
  * exists on most Cavium evaluation boards. If it doesn't exist, then
@@ -346,8 +356,18 @@ void octeon_user_io_init(void)
         cvmmemctl.s.wbfltime = 0;
         /* R/W If set, do not put Istream in the L2 cache. */
         cvmmemctl.s.istrnol2 = 0;
-        /* R/W The write buffer threshold. */
-        cvmmemctl.s.wbthresh = 10;
+
+        /*
+         * R/W The write buffer threshold. As per erratum Core-14752
+         * for CN63XX, a sc/scd might fail if the write buffer is
+         * full.  Lowering WBTHRESH greatly lowers the chances of the
+         * write buffer ever being full and triggering the erratum.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+                cvmmemctl.s.wbthresh = 4;
+        else
+                cvmmemctl.s.wbthresh = 10;
+
         /* R/W If set, CVMSEG is available for loads/stores in
          * kernel/debug mode. */
 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
@@ -365,14 +385,13 @@ void octeon_user_io_init(void)
          * is max legal value. */
         cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
 
+        write_c0_cvmmemctl(cvmmemctl.u64);
 
         if (smp_processor_id() == 0)
                 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
 
-        write_c0_cvmmemctl(cvmmemctl.u64);
-
         /* Move the performance counter interrupts to IRQ 6 */
         cvmctl = read_c0_cvmctl();
         cvmctl &= ~(7 << 7);
@@ -416,6 +435,41 @@ void __init prom_init(void)
                 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
         cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
 
+        sysinfo = cvmx_sysinfo_get();
+        memset(sysinfo, 0, sizeof(*sysinfo));
+        sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
+        sysinfo->phy_mem_desc_ptr =
+                cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
+        sysinfo->core_mask = octeon_bootinfo->core_mask;
+        sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
+        sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
+        sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
+        sysinfo->board_type = octeon_bootinfo->board_type;
+        sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
+        sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
+        memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
+               sizeof(sysinfo->mac_addr_base));
+        sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
+        memcpy(sysinfo->board_serial_number,
+               octeon_bootinfo->board_serial_number,
+               sizeof(sysinfo->board_serial_number));
+        sysinfo->compact_flash_common_base_addr =
+                octeon_bootinfo->compact_flash_common_base_addr;
+        sysinfo->compact_flash_attribute_base_addr =
+                octeon_bootinfo->compact_flash_attribute_base_addr;
+        sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
+        sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
+        sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
+
+        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                /* I/O clock runs at a different rate than the CPU. */
+                union cvmx_mio_rst_boot rst_boot;
+                rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
+                octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
+        } else {
+                octeon_io_clock_rate = sysinfo->cpu_clock_hz;
+        }
+
         /*
          * Only enable the LED controller if we're running on a CN38XX, CN58XX,
          * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
@@ -479,33 +533,6 @@ void __init prom_init(void)
         }
 #endif
 
-        sysinfo = cvmx_sysinfo_get();
-        memset(sysinfo, 0, sizeof(*sysinfo));
-        sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
-        sysinfo->phy_mem_desc_ptr =
-                cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
-        sysinfo->core_mask = octeon_bootinfo->core_mask;
-        sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
-        sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
-        sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
-        sysinfo->board_type = octeon_bootinfo->board_type;
-        sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
-        sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
-        memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
-               sizeof(sysinfo->mac_addr_base));
-        sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
-        memcpy(sysinfo->board_serial_number,
-               octeon_bootinfo->board_serial_number,
-               sizeof(sysinfo->board_serial_number));
-        sysinfo->compact_flash_common_base_addr =
-                octeon_bootinfo->compact_flash_common_base_addr;
-        sysinfo->compact_flash_attribute_base_addr =
-                octeon_bootinfo->compact_flash_attribute_base_addr;
-        sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
-        sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
-        sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
-
-
         octeon_check_cpu_bist();
 
         octeon_uart = octeon_get_boot_uart();
@@ -740,6 +767,31 @@ EXPORT_SYMBOL(prom_putchar);
 
 void prom_free_prom_memory(void)
 {
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
+                /* Check for presence of Core-14449 fix.  */
+                u32 insn;
+                u32 *foo;
+
+                foo = &insn;
+
+                asm volatile("# before" : : : "memory");
+                prefetch(foo);
+                asm volatile(
+                        ".set push\n\t"
+                        ".set noreorder\n\t"
+                        "bal 1f\n\t"
+                        "nop\n"
+                        "1:\tlw %0,-12($31)\n\t"
+                        ".set pop\n\t"
+                        : "=r" (insn) : : "$31", "memory");
+
+                if ((insn >> 26) != 0x33)
+                        panic("No PREF instruction at Core-14449 probe point.\n");
+
+                if (((insn >> 16) & 0x1f) != 28)
+                        panic("Core-14449 WAR not in place (%04x).\n"
+                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
+        }
 #ifdef CONFIG_CAVIUM_DECODE_RSL
         cvmx_interrupt_rsl_enable();
 
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 47d87da379f9..4a02fe891ab6 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -64,18 +64,16 @@ static __inline__ void atomic_add(int i, atomic_t * v)
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_add            \n"
-                "       addu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %0, %1          # atomic_add    \n"
+                        "       addu    %0, %2                          \n"
+                        "       sc      %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -109,18 +107,16 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_sub            \n"
-                "       subu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %0, %1          # atomic_sub    \n"
+                        "       subu    %0, %2                          \n"
+                        "       sc      %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -156,20 +152,19 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_add_return     \n"
-                "       addu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %1, %2  # atomic_add_return     \n"
+                        "       addu    %0, %1, %3                      \n"
+                        "       sc      %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp + i;
         } else {
                 unsigned long flags;
 
@@ -205,23 +200,24 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
                 : "Ir" (i), "m" (v->counter)
                 : "memory");
+
+                result = temp - i;
         } else if (kernel_uses_llsc) {
                 int temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_sub_return     \n"
-                "       subu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %1, %2  # atomic_sub_return     \n"
+                        "       subu    %0, %1, %3                      \n"
+                        "       sc      %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp - i;
         } else {
                 unsigned long flags;
 
@@ -279,12 +275,9 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
                 "       bltz    %0, 1f                                  \n"
                 "       sc      %0, %2                                  \n"
                 "       .set    noreorder                               \n"
-                "       beqz    %0, 2f                                  \n"
+                "       beqz    %0, 1b                                  \n"
                 "        subu   %0, %1, %3                              \n"
                 "       .set    reorder                                 \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
                 "1:                                                     \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
@@ -443,18 +436,16 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_add          \n"
-                "       daddu   %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %0, %1          # atomic64_add  \n"
+                        "       daddu   %0, %2                          \n"
+                        "       scd     %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -488,18 +479,16 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_sub          \n"
-                "       dsubu   %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %0, %1          # atomic64_sub  \n"
+                        "       dsubu   %0, %2                          \n"
+                        "       scd     %0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter));
+                } while (unlikely(!temp));
         } else {
                 unsigned long flags;
 
@@ -535,20 +524,19 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_add_return   \n"
-                "       daddu   %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       daddu   %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %1, %2  # atomic64_add_return   \n"
+                        "       daddu   %0, %1, %3                      \n"
+                        "       scd     %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp + i;
         } else {
                 unsigned long flags;
 
@@ -587,20 +575,19 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
         } else if (kernel_uses_llsc) {
                 long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_sub_return   \n"
-                "       dsubu   %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       dsubu   %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %1, %2  # atomic64_sub_return   \n"
+                        "       dsubu   %0, %1, %3                      \n"
+                        "       scd     %0, %2                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (result), "=&r" (temp), "=m" (v->counter)
+                        : "Ir" (i), "m" (v->counter)
+                        : "memory");
+                } while (unlikely(!result));
+
+                result = temp - i;
         } else {
                 unsigned long flags;
 
@@ -658,12 +645,9 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
                 "       bltz    %0, 1f                                  \n"
                 "       scd     %0, %2                                  \n"
                 "       .set    noreorder                               \n"
-                "       beqz    %0, 2f                                  \n"
+                "       beqz    %0, 1b                                  \n"
                 "        dsubu  %0, %1, %3                              \n"
                 "       .set    reorder                                 \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
                 "1:                                                     \n"
                 "       .set    mips0                                   \n"
                 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index b0ce7ca2851f..50b4ef288c53 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -73,30 +73,26 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
                 : "ir" (1UL << bit), "m" (*m));
 #ifdef CONFIG_CPU_MIPSR2
         } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
-                __asm__ __volatile__(
-                "1:     " __LL "%0, %1                  # set_bit       \n"
-                "       " __INS "%0, %4, %2, 1                          \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m), "r" (~0));
+                do {
+                        __asm__ __volatile__(
+                        "       " __LL "%0, %1          # set_bit       \n"
+                        "       " __INS "%0, %3, %2, 1                  \n"
+                        "       " __SC "%0, %1                          \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (bit), "r" (~0));
+                } while (unlikely(!temp));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (kernel_uses_llsc) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # set_bit       \n"
-                "       or      %0, %2                                  \n"
-                "       " __SC  "%0, %1                                 \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1          # set_bit       \n"
+                        "       or      %0, %2                          \n"
+                        "       " __SC  "%0, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (1UL << bit));
+                } while (unlikely(!temp));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -134,34 +130,30 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
                 "       " __SC "%0, %1                                  \n"
                 "       beqzl   %0, 1b                                  \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << bit)), "m" (*m));
+                : "=&r" (temp), "+m" (*m)
+                : "ir" (~(1UL << bit)));
 #ifdef CONFIG_CPU_MIPSR2
         } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
-                __asm__ __volatile__(
-                "1:     " __LL "%0, %1                  # clear_bit     \n"
-                "       " __INS "%0, $0, %2, 1                          \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       " __LL "%0, %1          # clear_bit     \n"
+                        "       " __INS "%0, $0, %2, 1                  \n"
+                        "       " __SC "%0, %1                          \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (bit));
+                } while (unlikely(!temp));
 #endif /* CONFIG_CPU_MIPSR2 */
         } else if (kernel_uses_llsc) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # clear_bit     \n"
-                "       and     %0, %2                                  \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << bit)), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1          # clear_bit     \n"
+                        "       and     %0, %2                          \n"
+                        "       " __SC "%0, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (~(1UL << bit)));
+                } while (unlikely(!temp));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -213,24 +205,22 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
                 "       " __SC  "%0, %1                         \n"
                 "       beqzl   %0, 1b                          \n"
                 "       .set    mips0                           \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
+                : "=&r" (temp), "+m" (*m)
+                : "ir" (1UL << bit));
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    mips3                           \n"
-                "1:     " __LL "%0, %1          # change_bit    \n"
-                "       xor     %0, %2                          \n"
-                "       " __SC  "%0, %1                         \n"
-                "       beqz    %0, 2f                          \n"
-                "       .subsection 2                           \n"
-                "2:     b       1b                              \n"
-                "       .previous                               \n"
-                "       .set    mips0                           \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1          # change_bit    \n"
+                        "       xor     %0, %2                          \n"
+                        "       " __SC  "%0, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m)
+                        : "ir" (1UL << bit));
+                } while (unlikely(!temp));
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -272,30 +262,26 @@ static inline int test_and_set_bit(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1  # test_and_set_bit      \n"
+                        "       or      %2, %0, %3                      \n"
+                        "       " __SC  "%2, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -340,30 +326,26 @@ static inline int test_and_set_bit_lock(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL "%0, %1  # test_and_set_bit      \n"
+                        "       or      %2, %0, %3                      \n"
+                        "       " __SC  "%2, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -410,49 +392,43 @@ static inline int test_and_clear_bit(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
 #ifdef CONFIG_CPU_MIPSR2
         } else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
-                "       " __EXT "%2, %0, %3, 1                          \n"
-                "       " __INS "%0, $0, %3, 1                          \n"
-                "       " __SC  "%0, %1                                 \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "ir" (bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       " __LL  "%0, %1 # test_and_clear_bit    \n"
+                        "       " __EXT "%2, %0, %3, 1                  \n"
+                        "       " __INS "%0, $0, %3, 1                  \n"
+                        "       " __SC  "%0, %1                         \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "ir" (bit)
+                        : "memory");
+                } while (unlikely(!temp));
 #endif
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
-                "       or      %2, %0, %3                              \n"
-                "       xor     %2, %3                                  \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL  "%0, %1 # test_and_clear_bit    \n"
+                        "       or      %2, %0, %3                      \n"
+                        "       xor     %2, %3                          \n"
+                        "       " __SC  "%2, %1                         \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
@@ -499,30 +475,26 @@ static inline int test_and_change_bit(unsigned long nr,
                 "       beqzl   %2, 1b                                  \n"
                 "       and     %2, %0, %3                              \n"
                 "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
+                : "=&r" (temp), "+m" (*m), "=&r" (res)
+                : "r" (1UL << bit)
                 : "memory");
         } else if (kernel_uses_llsc) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
                 unsigned long temp;
 
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
-                "       xor     %2, %0, %3                              \n"
-                "       " __SC  "\t%2, %1                               \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       " __LL  "%0, %1 # test_and_change_bit   \n"
+                        "       xor     %2, %0, %3                      \n"
+                        "       " __SC  "\t%2, %1                       \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (temp), "+m" (*m), "=&r" (res)
+                        : "r" (1UL << bit)
+                        : "memory");
+                } while (unlikely(!res));
+
+                res = temp & (1UL << bit);
         } else {
                 volatile unsigned long *a = addr;
                 unsigned long mask;
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 15a8ef0707c6..35cd1bab69c3 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -125,4 +125,16 @@ extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
  */
 extern void plat_mem_setup(void);
 
+#ifdef CONFIG_SWIOTLB
+/*
+ * Optional platform hook to call swiotlb_setup().
+ */
+extern void plat_swiotlb_setup(void);
+
+#else
+
+static inline void plat_swiotlb_setup(void) {}
+
+#endif /* CONFIG_SWIOTLB */
+
 #endif /* _ASM_BOOTINFO_H */
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 2d28017e95d0..d8d1c2805ac7 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -44,12 +44,9 @@
                 "       move    $1, %z4                         \n"     \
                 "       .set    mips3                           \n"     \
                 "       " st "  $1, %1                          \n"     \
-                "       beqz    $1, 3f                          \n"     \
-                "2:                                             \n"     \
-                "       .subsection 2                           \n"     \
-                "3:     b       1b                              \n"     \
-                "       .previous                               \n"     \
+                "       beqz    $1, 1b                          \n"     \
                 "       .set    pop                             \n"     \
+                "2:                                             \n"     \
                 : "=&r" (__ret), "=R" (*m)                              \
                 : "R" (*m), "Jr" (old), "Jr" (new)                      \
                 : "memory");                                            \
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index b201a8f5b127..06d59dcbe243 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -111,14 +111,16 @@
  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
  */
 
-#define PRID_IMP_BCM4710        0x4000
-#define PRID_IMP_BCM3302        0x9000
-#define PRID_IMP_BCM6338        0x9000
-#define PRID_IMP_BCM6345        0x8000
-#define PRID_IMP_BCM6348        0x9100
-#define PRID_IMP_BCM4350        0xA000
-#define PRID_REV_BCM6358        0x0010
-#define PRID_REV_BCM6368        0x0030
+#define PRID_IMP_BMIPS4KC       0x4000
+#define PRID_IMP_BMIPS32        0x8000
+#define PRID_IMP_BMIPS3300      0x9000
+#define PRID_IMP_BMIPS3300_ALT  0x9100
+#define PRID_IMP_BMIPS3300_BUG  0x0000
+#define PRID_IMP_BMIPS43XX      0xa000
+#define PRID_IMP_BMIPS5000      0x5a00
+
+#define PRID_REV_BMIPS4380_LO   0x0040
+#define PRID_REV_BMIPS4380_HI   0x006f
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
@@ -131,6 +133,7 @@
 #define PRID_IMP_CAVIUM_CN56XX 0x0400
 #define PRID_IMP_CAVIUM_CN50XX 0x0600
 #define PRID_IMP_CAVIUM_CN52XX 0x0700
+#define PRID_IMP_CAVIUM_CN63XX 0x9000
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
@@ -223,15 +226,14 @@ enum cpu_type_enum {
          * MIPS32 class processors
          */
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
-        CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
-        CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
-        CPU_JZRISC,
+        CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
+        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
 
         /*
          * MIPS64 class processors
          */
         CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
 
         CPU_LAST
 };
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
index 06746c5e8099..c94fafba9e62 100644
--- a/arch/mips/include/asm/device.h
+++ b/arch/mips/include/asm/device.h
@@ -3,4 +3,17 @@
  *
  * This file is released under the GPLv2
  */
-#include <asm-generic/device.h>
+#ifndef _ASM_MIPS_DEVICE_H
+#define _ASM_MIPS_DEVICE_H
+
+struct dma_map_ops;
+
+struct dev_archdata {
+        /* DMA operations on that device */
+        struct dma_map_ops *dma_ops;
+};
+
+struct pdev_archdata {
+};
+
+#endif /* _ASM_MIPS_DEVICE_H*/
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 18fbf7af8e93..655f849bd08d 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -5,51 +5,41 @@
 #include <asm/cache.h>
 #include <asm-generic/dma-coherent.h>
 
-void *dma_alloc_noncoherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
+#include <dma-coherence.h>
 
-void dma_free_noncoherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
+extern struct dma_map_ops *mips_dma_map_ops;
 
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
+{
+        if (dev && dev->archdata.dma_ops)
+                return dev->archdata.dma_ops;
+        else
+                return mips_dma_map_ops;
+}
 
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+        if (!dev->dma_mask)
+                return 0;
 
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-        enum dma_data_direction direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-        size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-        enum dma_data_direction direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
-        unsigned long offset, size_t size, enum dma_data_direction direction);
-
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-        size_t size, enum dma_data_direction direction)
+        return addr + size <= *dev->dma_mask;
+}
+
+static inline void dma_mark_clean(void *addr, size_t size) {}
+
+#include <asm-generic/dma-mapping-common.h>
+
+static inline int dma_supported(struct device *dev, u64 mask)
 {
-        dma_unmap_single(dev, dma_address, size, direction);
+        struct dma_map_ops *ops = get_dma_ops(dev);
+        return ops->dma_supported(dev, mask);
 }
 
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-        int nhwentries, enum dma_data_direction direction);
-extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-        size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_for_device(struct device *dev,
-        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_range_for_cpu(struct device *dev,
-        dma_addr_t dma_handle, unsigned long offset, size_t size,
-        enum dma_data_direction direction);
-extern void dma_sync_single_range_for_device(struct device *dev,
-        dma_addr_t dma_handle, unsigned long offset, size_t size,
-        enum dma_data_direction direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
-        int nelems, enum dma_data_direction direction);
-extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
-        int nelems, enum dma_data_direction direction);
-extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
-extern int dma_supported(struct device *dev, u64 mask);
+static inline int dma_mapping_error(struct device *dev, u64 mask)
+{
+        struct dma_map_ops *ops = get_dma_ops(dev);
+        return ops->mapping_error(dev, mask);
+}
 
 static inline int
 dma_set_mask(struct device *dev, u64 mask)
@@ -65,4 +55,34 @@ dma_set_mask(struct device *dev, u64 mask)
 extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                enum dma_data_direction direction);
 
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+                                       dma_addr_t *dma_handle, gfp_t gfp)
+{
+        void *ret;
+        struct dma_map_ops *ops = get_dma_ops(dev);
+
+        ret = ops->alloc_coherent(dev, size, dma_handle, gfp);
+
+        debug_dma_alloc_coherent(dev, size, *dma_handle, ret);
+
+        return ret;
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *vaddr, dma_addr_t dma_handle)
+{
+        struct dma_map_ops *ops = get_dma_ops(dev);
+
+        ops->free_coherent(dev, size, vaddr, dma_handle);
+
+        debug_dma_free_coherent(dev, size, vaddr, dma_handle);
+}
+
+
+void *dma_alloc_noncoherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t flag);
+
+void dma_free_noncoherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle);
+
 #endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index 1353c81065d1..2d47da62d5a7 100644
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -91,7 +91,10 @@
 #define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
 #endif
 #define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
+
+#ifndef MAX_DMA32_PFN
 #define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
+#endif
 
 /* 8237 DMA controllers */
 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index bdcdef02d147..fffc8307a80a 100644
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -117,7 +117,7 @@ static __inline__ long local_sub_return(long i, local_t * l)
 
 #define local_cmpxchg(l, o, n) \
         ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
-#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+#define local_xchg(l, n) (atomic_long_xchg((&(l)->a), (n)))
 
 /**
  * local_add_unless - add unless the number is a given value
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 483ffea9ecb1..7919d76186bf 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -39,6 +39,7 @@
 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
 #define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
+#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
@@ -50,6 +51,14 @@
 #define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
 #define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
 
+/* Titan registers */
+#define TITAN_REGS_ESWITCH_BASE (0x08640000)
+#define TITAN_REGS_MAC0         (TITAN_REGS_ESWITCH_BASE)
+#define TITAN_REGS_MAC1         (TITAN_REGS_ESWITCH_BASE + 0x0800)
+#define TITAN_REGS_MDIO         (TITAN_REGS_ESWITCH_BASE + 0x02000)
+#define TITAN_REGS_VLYNQ0       (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1       (AR7_REGS_BASE + 0x1300)
+
 #define AR7_RESET_PERIPHERAL    0x0
 #define AR7_RESET_SOFTWARE      0x4
 #define AR7_RESET_STATUS        0x8
@@ -59,15 +68,30 @@
 #define AR7_RESET_BIT_MDIO      22
 #define AR7_RESET_BIT_EPHY      26
 
+#define TITAN_RESET_BIT_EPHY1   28
+
 /* GPIO control registers */
 #define AR7_GPIO_INPUT  0x0
 #define AR7_GPIO_OUTPUT 0x4
 #define AR7_GPIO_DIR    0x8
 #define AR7_GPIO_ENABLE 0xc
+#define TITAN_GPIO_INPUT_0      0x0
+#define TITAN_GPIO_INPUT_1      0x4
+#define TITAN_GPIO_OUTPUT_0     0x8
+#define TITAN_GPIO_OUTPUT_1     0xc
+#define TITAN_GPIO_DIR_0        0x10
+#define TITAN_GPIO_DIR_1        0x14
+#define TITAN_GPIO_ENBL_0       0x18
+#define TITAN_GPIO_ENBL_1       0x1c
 
 #define AR7_CHIP_7100   0x18
 #define AR7_CHIP_7200   0x2b
 #define AR7_CHIP_7300   0x05
+#define AR7_CHIP_TITAN  0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07
 
 /* Interrupts */
 #define AR7_IRQ_UART0   15
@@ -95,14 +119,29 @@ struct plat_dsl_data {
 
 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 
+static inline int ar7_is_titan(void)
+{
+        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+                AR7_CHIP_TITAN;
+}
+
 static inline u16 ar7_chip_id(void)
 {
-        return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+        return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+                KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
+}
+
+static inline u16 titan_chip_id(void)
+{
+        unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO +
+                                                TITAN_GPIO_INPUT_1));
+        return ((val >> 12) & 0x0f);
 }
 
 static inline u8 ar7_chip_rev(void)
 {
-        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
+        return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+                0x14))) >> 16) & 0xff;
 }
 
 struct clk {
@@ -161,4 +200,8 @@ static inline void ar7_device_off(u32 bit)
         msleep(20);
 }
 
+int __init ar7_gpio_init(void);
+
+int __init ar7_gpio_init(void);
+
 #endif /* __AR7_H__ */
diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h
index abc317c0372e..c177cd1eed25 100644
--- a/arch/mips/include/asm/mach-ar7/gpio.h
+++ b/arch/mips/include/asm/mach-ar7/gpio.h
@@ -22,7 +22,8 @@
 #include <asm/mach-ar7/ar7.h>
 
 #define AR7_GPIO_MAX 32
-#define NR_BUILTIN_GPIO AR7_GPIO_MAX
+#define TITAN_GPIO_MAX  51
+#define NR_BUILTIN_GPIO TITAN_GPIO_MAX
 
 #define gpio_to_irq(gpio)       -1
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
new file mode 100644
index 000000000000..5325084d5c48
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -0,0 +1,97 @@
+#ifndef __BCM963XX_TAG_H
+#define __BCM963XX_TAG_H
+
+#define TAGVER_LEN              4       /* Length of Tag Version */
+#define TAGLAYOUT_LEN           4       /* Length of FlashLayoutVer */
+#define SIG1_LEN                20      /* Company Signature 1 Length */
+#define SIG2_LEN                14      /* Company Signature 2 Lenght */
+#define BOARDID_LEN             16      /* Length of BoardId */
+#define ENDIANFLAG_LEN          2       /* Endian Flag Length */
+#define CHIPID_LEN              6       /* Chip Id Length */
+#define IMAGE_LEN               10      /* Length of Length Field */
+#define ADDRESS_LEN             12      /* Length of Address field */
+#define DUALFLAG_LEN            2       /* Dual Image flag Length */
+#define INACTIVEFLAG_LEN        2       /* Inactie Flag Length */
+#define RSASIG_LEN              20      /* Length of RSA Signature in tag */
+#define TAGINFO1_LEN            30      /* Length of vendor information field1 in tag */
+#define FLASHLAYOUTVER_LEN      4       /* Length of Flash Layout Version String tag */
+#define TAGINFO2_LEN            16      /* Length of vendor information field2 in tag */
+#define CRC_LEN                 4       /* Length of CRC in bytes */
+#define ALTTAGINFO_LEN          54      /* Alternate length for vendor information; Pirelli */
+
+#define NUM_PIRELLI             2
+#define IMAGETAG_CRC_START      0xFFFFFFFF
+
+#define PIRELLI_BOARDS { \
+        "AGPF-S0", \
+        "DWV-S0", \
+}
+
+/*
+ * The broadcom firmware assumes the rootfs starts the image,
+ * therefore uses the rootfs start (flash_image_address)
+ * to determine where to flash the image.  Since we have the kernel first
+ * we have to give it the kernel address, but the crc uses the length
+ * associated with this address (root_length), which is added to the kernel
+ * length (kernel_length) to determine the length of image to flash and thus
+ * needs to be rootfs + deadcode (jffs2 EOF marker)
+*/
+
+struct bcm_tag {
+        /* 0-3: Version of the image tag */
+        char tag_version[TAGVER_LEN];
+        /* 4-23: Company Line 1 */
+        char sig_1[SIG1_LEN];
+        /*  24-37: Company Line 2 */
+        char sig_2[SIG2_LEN];
+        /* 38-43: Chip this image is for */
+        char chip_id[CHIPID_LEN];
+        /* 44-59: Board name */
+        char board_id[BOARDID_LEN];
+        /* 60-61: Map endianness -- 1 BE 0 LE */
+        char big_endian[ENDIANFLAG_LEN];
+        /* 62-71: Total length of image */
+        char total_length[IMAGE_LEN];
+        /* 72-83: Address in memory of CFE */
+        char cfe__address[ADDRESS_LEN];
+        /* 84-93: Size of CFE */
+        char cfe_length[IMAGE_LEN];
+        /* 94-105: Address in memory of image start
+         * (kernel for OpenWRT, rootfs for stock firmware)
+         */
+        char flash_image_start[ADDRESS_LEN];
+        /* 106-115: Size of rootfs */
+        char root_length[IMAGE_LEN];
+        /* 116-127: Address in memory of kernel */
+        char kernel_address[ADDRESS_LEN];
+        /* 128-137: Size of kernel */
+        char kernel_length[IMAGE_LEN];
+        /* 138-139: Unused at the moment */
+        char dual_image[DUALFLAG_LEN];
+        /* 140-141: Unused at the moment */
+        char inactive_flag[INACTIVEFLAG_LEN];
+        /* 142-161: RSA Signature (not used; some vendors may use this) */
+        char rsa_signature[RSASIG_LEN];
+        /* 162-191: Compilation and related information (not used in OpenWrt) */
+        char information1[TAGINFO1_LEN];
+        /* 192-195: Version flash layout */
+        char flash_layout_ver[FLASHLAYOUTVER_LEN];
+        /* 196-199: kernel+rootfs CRC32 */
+        char fskernel_crc[CRC_LEN];
+        /* 200-215: Unused except on Alice Gate where is is information */
+        char information2[TAGINFO2_LEN];
+        /* 216-219: CRC32 of image less imagetag (kernel for Alice Gate) */
+        char image_crc[CRC_LEN];
+        /* 220-223: CRC32 of rootfs partition */
+        char rootfs_crc[CRC_LEN];
+        /* 224-227: CRC32 of kernel partition */
+        char kernel_crc[CRC_LEN];
+        /* 228-235: Unused at present */
+        char reserved1[8];
+        /* 236-239: CRC32 of header excluding tagVersion */
+        char header_crc[CRC_LEN];
+        /* 240-255: Unused at present */
+        char reserved2[16];
+};
+
+#endif /* __BCM63XX_TAG_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index b952fc7215e2..0d5a42b5f47a 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -59,7 +59,7 @@
 #define cpu_has_veic            0
 #define cpu_hwrena_impl_bits    0xc0000000
 
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
 
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
@@ -81,4 +81,10 @@ static inline int octeon_has_saa(void)
         return id >= 0x000d0300;
 }
 
+/*
+ * The last 256MB are reserved for device to device mappings and the
+ * BAR1 hole.
+ */
+#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT)
+
 #endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index 17d579471ec4..be8fb4240cec 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -15,41 +15,40 @@
 
 struct device;
 
-dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
-void octeon_unmap_dma_mem(struct device *, dma_addr_t);
+extern void octeon_pci_dma_init(void);
 
 static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         size_t size)
 {
-        return octeon_map_dma_mem(dev, addr, size);
+        BUG();
 }
 
 static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         struct page *page)
 {
-        return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
+        BUG();
 }
 
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
-        return dma_addr;
+        BUG();
 }
 
 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
         size_t size, enum dma_data_direction direction)
 {
-        octeon_unmap_dma_mem(dev, dma_addr);
+        BUG();
 }
 
 static inline int plat_dma_supported(struct device *dev, u64 mask)
 {
-        return 1;
+        BUG();
 }
 
 static inline void plat_extra_sync_for_device(struct device *dev)
 {
-        mb();
+        BUG();
 }
 
 static inline int plat_device_is_coherent(struct device *dev)
@@ -60,7 +59,14 @@ static inline int plat_device_is_coherent(struct device *dev)
 static inline int plat_dma_mapping_error(struct device *dev,
                                          dma_addr_t dma_addr)
 {
-        return dma_addr == -1;
+        BUG();
 }
 
+dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
+phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
+
+struct dma_map_ops;
+extern struct dma_map_ops *octeon_pci_dma_map_ops;
+extern char *octeon_swiotlb;
+
 #endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index d3d04018a858..016d0989b141 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -26,14 +26,15 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         return pa;
 }
 
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
 {
         dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
 
         return pa;
 }
 
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
         return dma_addr & ~(0xffUL << 56);
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 37855955b313..c8fb5aacf50a 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -37,7 +37,8 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
         return pa;
 }
 
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
 {
         dma_addr_t pa;
 
@@ -50,7 +51,7 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
 }
 
 /* This is almost certainly wrong but it's what dma-ip32.c used to use  */
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
         unsigned long addr = dma_addr & RAM_OFFSET_MASK;
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index f93aee59454a..302101b54acb 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -12,23 +12,24 @@
 
 struct device;
 
-static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
 {
         return vdma_alloc(virt_to_phys(addr), size);
 }
 
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+        struct page *page)
 {
         return vdma_alloc(page_to_phys(page), PAGE_SIZE);
 }
 
-static unsigned long plat_dma_addr_to_phys(struct device *dev,
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
         dma_addr_t dma_addr)
 {
         return vdma_log2phys(dma_addr);
 }
 
-static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
         size_t size, enum dma_data_direction direction)
 {
         vdma_free(dma_addr);
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 335474c155f6..4d9870975382 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1040,6 +1040,12 @@ do {									\
 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
 
+#define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
+#define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
+
+#define read_c0_staglo()        __read_32bit_c0_register($28, 4)
+#define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
+
 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
 
@@ -1082,6 +1088,51 @@ do {									\
 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
 
+/* BMIPS3300 */
+#define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
+
+/* BMIPS4380 */
+#define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
+#define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
+
+#define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
+#define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
+
+/* BMIPS5000 */
+#define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
+#define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
+
+#define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
+#define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
+
+#define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
+#define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
+
+#define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
+#define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
+
+#define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
+#define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
+
+#define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
+#define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
+
 /*
  * Macros to access the floating point coprocessor control registers
  */
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
index ec94b9ab7be1..30d68f2365e0 100644
--- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,148 +28,80 @@
 #ifndef __CVMX_AGL_DEFS_H__
 #define __CVMX_AGL_DEFS_H__
 
-#define CVMX_AGL_GMX_BAD_REG \
-         CVMX_ADD_IO_SEG(0x00011800E0000518ull)
-#define CVMX_AGL_GMX_BIST \
-         CVMX_ADD_IO_SEG(0x00011800E0000400ull)
-#define CVMX_AGL_GMX_DRV_CTL \
-         CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
-#define CVMX_AGL_GMX_INF_MODE \
-         CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
-#define CVMX_AGL_GMX_PRTX_CFG(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_DECISION(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_IFG(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_JABBER(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
-#define CVMX_AGL_GMX_RX_PRT_INFO \
-         CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
-#define CVMX_AGL_GMX_RX_TX_STATUS \
-         CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
-#define CVMX_AGL_GMX_SMACX(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_STAT_BP \
-         CVMX_ADD_IO_SEG(0x00011800E0000520ull)
-#define CVMX_AGL_GMX_TXX_APPEND(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT0(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT1(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT2(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT3(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT4(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT5(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT6(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT7(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT8(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STAT9(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TXX_THRESH(offset) \
-         CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
-#define CVMX_AGL_GMX_TX_BP \
-         CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
-#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
-         CVMX_ADD_IO_SEG(0x00011800E0000498ull)
-#define CVMX_AGL_GMX_TX_IFG \
-         CVMX_ADD_IO_SEG(0x00011800E0000488ull)
-#define CVMX_AGL_GMX_TX_INT_EN \
-         CVMX_ADD_IO_SEG(0x00011800E0000508ull)
-#define CVMX_AGL_GMX_TX_INT_REG \
-         CVMX_ADD_IO_SEG(0x00011800E0000500ull)
-#define CVMX_AGL_GMX_TX_JAM \
-         CVMX_ADD_IO_SEG(0x00011800E0000490ull)
-#define CVMX_AGL_GMX_TX_LFSR \
-         CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
-#define CVMX_AGL_GMX_TX_OVR_BP \
-         CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
-         CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
-#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
-         CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
+#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
+#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
+#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
+#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
+#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
+#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
+#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
+#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
+#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
+#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
+#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
+#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
+#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
+#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
+#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
+#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
+#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
+#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
 
 union cvmx_agl_gmx_bad_reg {
         uint64_t u64;
@@ -183,14 +115,29 @@ union cvmx_agl_gmx_bad_reg {
                 uint64_t ovrflw:1;
                 uint64_t reserved_27_31:5;
                 uint64_t statovr:1;
+                uint64_t reserved_24_25:2;
+                uint64_t loststat:2;
+                uint64_t reserved_4_21:18;
+                uint64_t out_ovr:2;
+                uint64_t reserved_0_1:2;
+        } s;
+        struct cvmx_agl_gmx_bad_reg_cn52xx {
+                uint64_t reserved_38_63:26;
+                uint64_t txpsh1:1;
+                uint64_t txpop1:1;
+                uint64_t ovrflw1:1;
+                uint64_t txpsh:1;
+                uint64_t txpop:1;
+                uint64_t ovrflw:1;
+                uint64_t reserved_27_31:5;
+                uint64_t statovr:1;
                 uint64_t reserved_23_25:3;
                 uint64_t loststat:1;
                 uint64_t reserved_4_21:18;
                 uint64_t out_ovr:2;
                 uint64_t reserved_0_1:2;
-        } s;
-        struct cvmx_agl_gmx_bad_reg_s cn52xx;
-        struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_bad_reg_cn56xx {
                 uint64_t reserved_35_63:29;
                 uint64_t txpsh:1;
@@ -205,18 +152,25 @@ union cvmx_agl_gmx_bad_reg {
                 uint64_t reserved_0_1:2;
         } cn56xx;
         struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_bad_reg_s cn63xx;
+        struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_bist {
         uint64_t u64;
         struct cvmx_agl_gmx_bist_s {
+                uint64_t reserved_25_63:39;
+                uint64_t status:25;
+        } s;
+        struct cvmx_agl_gmx_bist_cn52xx {
                 uint64_t reserved_10_63:54;
                 uint64_t status:10;
-        } s;
-        struct cvmx_agl_gmx_bist_s cn52xx;
-        struct cvmx_agl_gmx_bist_s cn52xxp1;
-        struct cvmx_agl_gmx_bist_s cn56xx;
-        struct cvmx_agl_gmx_bist_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_bist_cn52xx cn56xx;
+        struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_bist_s cn63xx;
+        struct cvmx_agl_gmx_bist_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_drv_ctl {
@@ -264,7 +218,13 @@ union cvmx_agl_gmx_inf_mode {
 union cvmx_agl_gmx_prtx_cfg {
         uint64_t u64;
         struct cvmx_agl_gmx_prtx_cfg_s {
-                uint64_t reserved_6_63:58;
+                uint64_t reserved_14_63:50;
+                uint64_t tx_idle:1;
+                uint64_t rx_idle:1;
+                uint64_t reserved_9_11:3;
+                uint64_t speed_msb:1;
+                uint64_t reserved_7_7:1;
+                uint64_t burst:1;
                 uint64_t tx_en:1;
                 uint64_t rx_en:1;
                 uint64_t slottime:1;
@@ -272,10 +232,20 @@ union cvmx_agl_gmx_prtx_cfg {
                 uint64_t speed:1;
                 uint64_t en:1;
         } s;
-        struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
-        struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
-        struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
-        struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx {
+                uint64_t reserved_6_63:58;
+                uint64_t tx_en:1;
+                uint64_t rx_en:1;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
+        struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
+        struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam0 {
@@ -287,6 +257,8 @@ union cvmx_agl_gmx_rxx_adr_cam0 {
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam1 {
@@ -298,6 +270,8 @@ union cvmx_agl_gmx_rxx_adr_cam1 {
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam2 {
@@ -309,6 +283,8 @@ union cvmx_agl_gmx_rxx_adr_cam2 {
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam3 {
@@ -320,6 +296,8 @@ union cvmx_agl_gmx_rxx_adr_cam3 {
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam4 {
@@ -331,6 +309,8 @@ union cvmx_agl_gmx_rxx_adr_cam4 {
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam5 {
@@ -342,6 +322,8 @@ union cvmx_agl_gmx_rxx_adr_cam5 {
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_cam_en {
@@ -354,6 +336,8 @@ union cvmx_agl_gmx_rxx_adr_cam_en {
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_adr_ctl {
@@ -368,6 +352,8 @@ union cvmx_agl_gmx_rxx_adr_ctl {
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_decision {
@@ -380,11 +366,26 @@ union cvmx_agl_gmx_rxx_decision {
         struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_decision_s cn56xx;
         struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_decision_s cn63xx;
+        struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_chk {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_chk_s {
+                uint64_t reserved_10_63:54;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
                 uint64_t reserved_9_63:55;
                 uint64_t skperr:1;
                 uint64_t rcverr:1;
@@ -395,17 +396,21 @@ union cvmx_agl_gmx_rxx_frm_chk {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-        } s;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
-        struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_ctl {
         uint64_t u64;
         struct cvmx_agl_gmx_rxx_frm_ctl_s {
-                uint64_t reserved_10_63:54;
+                uint64_t reserved_13_63:51;
+                uint64_t ptp_mode:1;
+                uint64_t reserved_11_11:1;
+                uint64_t null_dis:1;
                 uint64_t pre_align:1;
                 uint64_t pad_len:1;
                 uint64_t vlan_len:1;
@@ -417,10 +422,24 @@ union cvmx_agl_gmx_rxx_frm_ctl {
                 uint64_t pre_strp:1;
                 uint64_t pre_chk:1;
         } s;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
-        struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
+                uint64_t reserved_10_63:54;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_max {
@@ -433,6 +452,8 @@ union cvmx_agl_gmx_rxx_frm_max {
         struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
         struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_frm_min {
@@ -445,6 +466,8 @@ union cvmx_agl_gmx_rxx_frm_min {
         struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
         struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
+        struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_ifg {
@@ -457,6 +480,8 @@ union cvmx_agl_gmx_rxx_ifg {
         struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
         struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
+        struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_en {
@@ -464,6 +489,29 @@ union cvmx_agl_gmx_rxx_int_en {
         struct cvmx_agl_gmx_rxx_int_en_s {
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
                 uint64_t reserved_16_18:3;
                 uint64_t ifgerr:1;
                 uint64_t coldet:1;
@@ -481,11 +529,12 @@ union cvmx_agl_gmx_rxx_int_en {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-        } s;
-        struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
-        struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
-        struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
+        struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_int_reg {
@@ -493,6 +542,29 @@ union cvmx_agl_gmx_rxx_int_reg {
         struct cvmx_agl_gmx_rxx_int_reg_s {
                 uint64_t reserved_20_63:44;
                 uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
                 uint64_t reserved_16_18:3;
                 uint64_t ifgerr:1;
                 uint64_t coldet:1;
@@ -510,11 +582,12 @@ union cvmx_agl_gmx_rxx_int_reg {
                 uint64_t maxerr:1;
                 uint64_t reserved_1_1:1;
                 uint64_t minerr:1;
-        } s;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
-        struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
+        struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
+        struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_jabber {
@@ -527,6 +600,8 @@ union cvmx_agl_gmx_rxx_jabber {
         struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
         struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
+        struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_pause_drop_time {
@@ -539,6 +614,20 @@ union cvmx_agl_gmx_rxx_pause_drop_time {
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
         struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
+        struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_rxx_rx_inbnd {
+        uint64_t u64;
+        struct cvmx_agl_gmx_rxx_rx_inbnd_s {
+                uint64_t reserved_4_63:60;
+                uint64_t duplex:1;
+                uint64_t speed:2;
+                uint64_t status:1;
+        } s;
+        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
+        struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_ctl {
@@ -551,6 +640,8 @@ union cvmx_agl_gmx_rxx_stats_ctl {
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs {
@@ -563,6 +654,8 @@ union cvmx_agl_gmx_rxx_stats_octs {
         struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_ctl {
@@ -575,6 +668,8 @@ union cvmx_agl_gmx_rxx_stats_octs_ctl {
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_dmac {
@@ -587,6 +682,8 @@ union cvmx_agl_gmx_rxx_stats_octs_dmac {
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_octs_drp {
@@ -599,6 +696,8 @@ union cvmx_agl_gmx_rxx_stats_octs_drp {
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts {
@@ -611,6 +710,8 @@ union cvmx_agl_gmx_rxx_stats_pkts {
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_bad {
@@ -623,6 +724,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_bad {
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_ctl {
@@ -635,6 +738,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_ctl {
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_dmac {
@@ -647,6 +752,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_dmac {
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_stats_pkts_drp {
@@ -659,6 +766,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_drp {
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
         struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
+        struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rxx_udd_skp {
@@ -673,6 +782,8 @@ union cvmx_agl_gmx_rxx_udd_skp {
         struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
         struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
+        struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_dropx {
@@ -685,6 +796,8 @@ union cvmx_agl_gmx_rx_bp_dropx {
         struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
+        struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_offx {
@@ -697,6 +810,8 @@ union cvmx_agl_gmx_rx_bp_offx {
         struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
+        struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_bp_onx {
@@ -709,6 +824,8 @@ union cvmx_agl_gmx_rx_bp_onx {
         struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
         struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
         struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
+        struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_prt_info {
@@ -728,6 +845,8 @@ union cvmx_agl_gmx_rx_prt_info {
                 uint64_t commit:1;
         } cn56xx;
         struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
+        struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_rx_tx_status {
@@ -747,6 +866,8 @@ union cvmx_agl_gmx_rx_tx_status {
                 uint64_t rx:1;
         } cn56xx;
         struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
+        struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_smacx {
@@ -759,6 +880,8 @@ union cvmx_agl_gmx_smacx {
         struct cvmx_agl_gmx_smacx_s cn52xxp1;
         struct cvmx_agl_gmx_smacx_s cn56xx;
         struct cvmx_agl_gmx_smacx_s cn56xxp1;
+        struct cvmx_agl_gmx_smacx_s cn63xx;
+        struct cvmx_agl_gmx_smacx_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_stat_bp {
@@ -772,6 +895,8 @@ union cvmx_agl_gmx_stat_bp {
         struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
         struct cvmx_agl_gmx_stat_bp_s cn56xx;
         struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
+        struct cvmx_agl_gmx_stat_bp_s cn63xx;
+        struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_append {
@@ -787,6 +912,18 @@ union cvmx_agl_gmx_txx_append {
         struct cvmx_agl_gmx_txx_append_s cn52xxp1;
         struct cvmx_agl_gmx_txx_append_s cn56xx;
         struct cvmx_agl_gmx_txx_append_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_append_s cn63xx;
+        struct cvmx_agl_gmx_txx_append_s cn63xxp1;
+};
+
+union cvmx_agl_gmx_txx_clk {
+        uint64_t u64;
+        struct cvmx_agl_gmx_txx_clk_s {
+                uint64_t reserved_6_63:58;
+                uint64_t clk_cnt:6;
+        } s;
+        struct cvmx_agl_gmx_txx_clk_s cn63xx;
+        struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_ctl {
@@ -800,6 +937,8 @@ union cvmx_agl_gmx_txx_ctl {
         struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_txx_ctl_s cn56xx;
         struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_ctl_s cn63xx;
+        struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_min_pkt {
@@ -812,6 +951,8 @@ union cvmx_agl_gmx_txx_min_pkt {
         struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
         struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
         struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
+        struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_interval {
@@ -824,6 +965,8 @@ union cvmx_agl_gmx_txx_pause_pkt_interval {
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_pkt_time {
@@ -836,6 +979,8 @@ union cvmx_agl_gmx_txx_pause_pkt_time {
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_togo {
@@ -848,6 +993,8 @@ union cvmx_agl_gmx_txx_pause_togo {
         struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_pause_zero {
@@ -860,6 +1007,8 @@ union cvmx_agl_gmx_txx_pause_zero {
         struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
         struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
         struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
+        struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_soft_pause {
@@ -872,6 +1021,8 @@ union cvmx_agl_gmx_txx_soft_pause {
         struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
         struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
         struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
+        struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat0 {
@@ -884,6 +1035,8 @@ union cvmx_agl_gmx_txx_stat0 {
         struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat0_s cn56xx;
         struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat0_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat1 {
@@ -896,6 +1049,8 @@ union cvmx_agl_gmx_txx_stat1 {
         struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat1_s cn56xx;
         struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat1_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat2 {
@@ -908,6 +1063,8 @@ union cvmx_agl_gmx_txx_stat2 {
         struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat2_s cn56xx;
         struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat2_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat3 {
@@ -920,6 +1077,8 @@ union cvmx_agl_gmx_txx_stat3 {
         struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat3_s cn56xx;
         struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat3_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat4 {
@@ -932,6 +1091,8 @@ union cvmx_agl_gmx_txx_stat4 {
         struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat4_s cn56xx;
         struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat4_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat5 {
@@ -944,6 +1105,8 @@ union cvmx_agl_gmx_txx_stat5 {
         struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat5_s cn56xx;
         struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat5_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat6 {
@@ -956,6 +1119,8 @@ union cvmx_agl_gmx_txx_stat6 {
         struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat6_s cn56xx;
         struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat6_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat7 {
@@ -968,6 +1133,8 @@ union cvmx_agl_gmx_txx_stat7 {
         struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat7_s cn56xx;
         struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat7_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat8 {
@@ -980,6 +1147,8 @@ union cvmx_agl_gmx_txx_stat8 {
         struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat8_s cn56xx;
         struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat8_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stat9 {
@@ -992,6 +1161,8 @@ union cvmx_agl_gmx_txx_stat9 {
         struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stat9_s cn56xx;
         struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stat9_s cn63xx;
+        struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_stats_ctl {
@@ -1004,6 +1175,8 @@ union cvmx_agl_gmx_txx_stats_ctl {
         struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
         struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
+        struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_txx_thresh {
@@ -1016,6 +1189,8 @@ union cvmx_agl_gmx_txx_thresh {
         struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
         struct cvmx_agl_gmx_txx_thresh_s cn56xx;
         struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
+        struct cvmx_agl_gmx_txx_thresh_s cn63xx;
+        struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_bp {
@@ -1031,6 +1206,8 @@ union cvmx_agl_gmx_tx_bp {
                 uint64_t bp:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_bp_s cn63xx;
+        struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_col_attempt {
@@ -1043,6 +1220,8 @@ union cvmx_agl_gmx_tx_col_attempt {
         struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
         struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
         struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
+        struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_ifg {
@@ -1056,12 +1235,16 @@ union cvmx_agl_gmx_tx_ifg {
         struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
         struct cvmx_agl_gmx_tx_ifg_s cn56xx;
         struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_ifg_s cn63xx;
+        struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_en {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_int_en_s {
-                uint64_t reserved_18_63:46;
+                uint64_t reserved_22_63:42;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
                 uint64_t late_col:2;
                 uint64_t reserved_14_15:2;
                 uint64_t xsdef:2;
@@ -1072,8 +1255,19 @@ union cvmx_agl_gmx_tx_int_en {
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
         } s;
-        struct cvmx_agl_gmx_tx_int_en_s cn52xx;
-        struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_en_cn52xx {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_tx_int_en_cn56xx {
                 uint64_t reserved_17_63:47;
                 uint64_t late_col:1;
@@ -1087,12 +1281,16 @@ union cvmx_agl_gmx_tx_int_en {
                 uint64_t pko_nxa:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_int_en_s cn63xx;
+        struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_int_reg {
         uint64_t u64;
         struct cvmx_agl_gmx_tx_int_reg_s {
-                uint64_t reserved_18_63:46;
+                uint64_t reserved_22_63:42;
+                uint64_t ptp_lost:2;
+                uint64_t reserved_18_19:2;
                 uint64_t late_col:2;
                 uint64_t reserved_14_15:2;
                 uint64_t xsdef:2;
@@ -1103,8 +1301,19 @@ union cvmx_agl_gmx_tx_int_reg {
                 uint64_t reserved_1_1:1;
                 uint64_t pko_nxa:1;
         } s;
-        struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
-        struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
+        struct cvmx_agl_gmx_tx_int_reg_cn52xx {
+                uint64_t reserved_18_63:46;
+                uint64_t late_col:2;
+                uint64_t reserved_14_15:2;
+                uint64_t xsdef:2;
+                uint64_t reserved_10_11:2;
+                uint64_t xscol:2;
+                uint64_t reserved_4_7:4;
+                uint64_t undflw:2;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn52xx;
+        struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
         struct cvmx_agl_gmx_tx_int_reg_cn56xx {
                 uint64_t reserved_17_63:47;
                 uint64_t late_col:1;
@@ -1118,6 +1327,8 @@ union cvmx_agl_gmx_tx_int_reg {
                 uint64_t pko_nxa:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
+        struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_jam {
@@ -1130,6 +1341,8 @@ union cvmx_agl_gmx_tx_jam {
         struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
         struct cvmx_agl_gmx_tx_jam_s cn56xx;
         struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_jam_s cn63xx;
+        struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_lfsr {
@@ -1142,6 +1355,8 @@ union cvmx_agl_gmx_tx_lfsr {
         struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
         struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
         struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
+        struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_ovr_bp {
@@ -1165,6 +1380,8 @@ union cvmx_agl_gmx_tx_ovr_bp {
                 uint64_t ign_full:1;
         } cn56xx;
         struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
+        struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_dmac {
@@ -1177,6 +1394,8 @@ union cvmx_agl_gmx_tx_pause_pkt_dmac {
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
         struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
 };
 
 union cvmx_agl_gmx_tx_pause_pkt_type {
@@ -1189,6 +1408,39 @@ union cvmx_agl_gmx_tx_pause_pkt_type {
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
         struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
+        struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
+};
+
+union cvmx_agl_prtx_ctl {
+        uint64_t u64;
+        struct cvmx_agl_prtx_ctl_s {
+                uint64_t drv_byp:1;
+                uint64_t reserved_62_62:1;
+                uint64_t cmp_pctl:6;
+                uint64_t reserved_54_55:2;
+                uint64_t cmp_nctl:6;
+                uint64_t reserved_46_47:2;
+                uint64_t drv_pctl:6;
+                uint64_t reserved_38_39:2;
+                uint64_t drv_nctl:6;
+                uint64_t reserved_29_31:3;
+                uint64_t clk_set:5;
+                uint64_t clkrx_byp:1;
+                uint64_t reserved_21_22:2;
+                uint64_t clkrx_set:5;
+                uint64_t clktx_byp:1;
+                uint64_t reserved_13_14:2;
+                uint64_t clktx_set:5;
+                uint64_t reserved_5_7:3;
+                uint64_t dllrst:1;
+                uint64_t comp:1;
+                uint64_t enable:1;
+                uint64_t clkrst:1;
+                uint64_t mode:1;
+        } s;
+        struct cvmx_agl_prtx_ctl_s cn63xx;
+        struct cvmx_agl_prtx_ctl_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
index b21d3fc1ef91..5de5de95311b 100644
--- a/arch/mips/include/asm/octeon/cvmx-asm.h
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -114,6 +114,17 @@
 #define CVMX_DCACHE_INVALIDATE \
         { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
 
+#define CVMX_CACHE(op, address, offset)                                 \
+        asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \
+                : : [rbase] "d" (address) )
+/* fetch and lock the state. */
+#define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset)
+/* unlock the state. */
+#define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset)
+/* invalidate the cache block and clear the USED bits for the block */
+#define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset)
+/* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */
+#define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset)
 
 #define CVMX_POP(result, input) \
         asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index f8f05b7764b7..27cead370411 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,87 +28,61 @@
 #ifndef __CVMX_CIU_DEFS_H__
 #define __CVMX_CIU_DEFS_H__
 
-#define CVMX_CIU_BIST \
-         CVMX_ADD_IO_SEG(0x0001070000000730ull)
-#define CVMX_CIU_DINT \
-         CVMX_ADD_IO_SEG(0x0001070000000720ull)
-#define CVMX_CIU_FUSE \
-         CVMX_ADD_IO_SEG(0x0001070000000728ull)
-#define CVMX_CIU_GSTOP \
-         CVMX_ADD_IO_SEG(0x0001070000000710ull)
-#define CVMX_CIU_INTX_EN0(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN0_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN1_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
-#define CVMX_CIU_INTX_EN4_0(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
-#define CVMX_CIU_INTX_SUM0(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
-#define CVMX_CIU_INTX_SUM4(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
-#define CVMX_CIU_INT_SUM1 \
-         CVMX_ADD_IO_SEG(0x0001070000000108ull)
-#define CVMX_CIU_MBOX_CLRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
-#define CVMX_CIU_MBOX_SETX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
-#define CVMX_CIU_NMI \
-         CVMX_ADD_IO_SEG(0x0001070000000718ull)
-#define CVMX_CIU_PCI_INTA \
-         CVMX_ADD_IO_SEG(0x0001070000000750ull)
-#define CVMX_CIU_PP_DBG \
-         CVMX_ADD_IO_SEG(0x0001070000000708ull)
-#define CVMX_CIU_PP_POKEX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
-#define CVMX_CIU_PP_RST \
-         CVMX_ADD_IO_SEG(0x0001070000000700ull)
-#define CVMX_CIU_QLM_DCOK \
-         CVMX_ADD_IO_SEG(0x0001070000000760ull)
-#define CVMX_CIU_QLM_JTGC \
-         CVMX_ADD_IO_SEG(0x0001070000000768ull)
-#define CVMX_CIU_QLM_JTGD \
-         CVMX_ADD_IO_SEG(0x0001070000000770ull)
-#define CVMX_CIU_SOFT_BIST \
-         CVMX_ADD_IO_SEG(0x0001070000000738ull)
-#define CVMX_CIU_SOFT_PRST \
-         CVMX_ADD_IO_SEG(0x0001070000000748ull)
-#define CVMX_CIU_SOFT_PRST1 \
-         CVMX_ADD_IO_SEG(0x0001070000000758ull)
-#define CVMX_CIU_SOFT_RST \
-         CVMX_ADD_IO_SEG(0x0001070000000740ull)
-#define CVMX_CIU_TIMX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
-#define CVMX_CIU_WDOGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
+#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
+#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
+#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
+#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
+#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
+#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
+#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
+#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
+#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
+#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
+#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
+#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
+#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
+#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
+#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
+#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
+#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
+#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
+#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
+#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
+#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
+#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
+#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
+#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
+#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
+#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
+#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
+#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
 
 union cvmx_ciu_bist {
         uint64_t u64;
         struct cvmx_ciu_bist_s {
+                uint64_t reserved_5_63:59;
+                uint64_t bist:5;
+        } s;
+        struct cvmx_ciu_bist_cn30xx {
                 uint64_t reserved_4_63:60;
                 uint64_t bist:4;
-        } s;
-        struct cvmx_ciu_bist_s cn30xx;
-        struct cvmx_ciu_bist_s cn31xx;
-        struct cvmx_ciu_bist_s cn38xx;
-        struct cvmx_ciu_bist_s cn38xxp2;
+        } cn30xx;
+        struct cvmx_ciu_bist_cn30xx cn31xx;
+        struct cvmx_ciu_bist_cn30xx cn38xx;
+        struct cvmx_ciu_bist_cn30xx cn38xxp2;
         struct cvmx_ciu_bist_cn50xx {
                 uint64_t reserved_2_63:62;
                 uint64_t bist:2;
@@ -118,10 +92,57 @@ union cvmx_ciu_bist {
                 uint64_t bist:3;
         } cn52xx;
         struct cvmx_ciu_bist_cn52xx cn52xxp1;
-        struct cvmx_ciu_bist_s cn56xx;
-        struct cvmx_ciu_bist_s cn56xxp1;
-        struct cvmx_ciu_bist_s cn58xx;
-        struct cvmx_ciu_bist_s cn58xxp1;
+        struct cvmx_ciu_bist_cn30xx cn56xx;
+        struct cvmx_ciu_bist_cn30xx cn56xxp1;
+        struct cvmx_ciu_bist_cn30xx cn58xx;
+        struct cvmx_ciu_bist_cn30xx cn58xxp1;
+        struct cvmx_ciu_bist_s cn63xx;
+        struct cvmx_ciu_bist_s cn63xxp1;
+};
+
+union cvmx_ciu_block_int {
+        uint64_t u64;
+        struct cvmx_ciu_block_int_s {
+                uint64_t reserved_43_63:21;
+                uint64_t ptp:1;
+                uint64_t dpi:1;
+                uint64_t dfm:1;
+                uint64_t reserved_34_39:6;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t reserved_31_31:1;
+                uint64_t iob:1;
+                uint64_t reserved_29_29:1;
+                uint64_t agl:1;
+                uint64_t reserved_27_27:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t asxpcs0:1;
+                uint64_t reserved_21_21:1;
+                uint64_t pip:1;
+                uint64_t reserved_18_19:2;
+                uint64_t lmc0:1;
+                uint64_t l2c:1;
+                uint64_t reserved_15_15:1;
+                uint64_t rad:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t reserved_8_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t sli:1;
+                uint64_t reserved_2_2:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } s;
+        struct cvmx_ciu_block_int_s cn63xx;
+        struct cvmx_ciu_block_int_s cn63xxp1;
 };
 
 union cvmx_ciu_dint {
@@ -153,6 +174,11 @@ union cvmx_ciu_dint {
         struct cvmx_ciu_dint_cn56xx cn56xxp1;
         struct cvmx_ciu_dint_s cn58xx;
         struct cvmx_ciu_dint_s cn58xxp1;
+        struct cvmx_ciu_dint_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t dint:6;
+        } cn63xx;
+        struct cvmx_ciu_dint_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_fuse {
@@ -184,6 +210,11 @@ union cvmx_ciu_fuse {
         struct cvmx_ciu_fuse_cn56xx cn56xxp1;
         struct cvmx_ciu_fuse_s cn58xx;
         struct cvmx_ciu_fuse_s cn58xxp1;
+        struct cvmx_ciu_fuse_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t fuse:6;
+        } cn63xx;
+        struct cvmx_ciu_fuse_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_gstop {
@@ -203,6 +234,8 @@ union cvmx_ciu_gstop {
         struct cvmx_ciu_gstop_s cn56xxp1;
         struct cvmx_ciu_gstop_s cn58xx;
         struct cvmx_ciu_gstop_s cn58xxp1;
+        struct cvmx_ciu_gstop_s cn63xx;
+        struct cvmx_ciu_gstop_s cn63xxp1;
 };
 
 union cvmx_ciu_intx_en0 {
@@ -343,6 +376,8 @@ union cvmx_ciu_intx_en0 {
         struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en0_cn38xx cn58xx;
         struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
+        struct cvmx_ciu_intx_en0_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en0_w1c {
@@ -412,6 +447,8 @@ union cvmx_ciu_intx_en0_w1c {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en0_w1s {
@@ -481,12 +518,42 @@ union cvmx_ciu_intx_en0_w1s {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en1 {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -531,12 +598,76 @@ union cvmx_ciu_intx_en1 {
         struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_en1_cn38xx cn58xx;
         struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
+        struct cvmx_ciu_intx_en1_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en1_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_w1c_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -560,12 +691,76 @@ union cvmx_ciu_intx_en1_w1c {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en1_w1c_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en1_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en1_w1s_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -589,6 +784,42 @@ union cvmx_ciu_intx_en1_w1s {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en1_w1s_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_0 {
@@ -705,6 +936,8 @@ union cvmx_ciu_intx_en4_0 {
                 uint64_t workq:16;
         } cn58xx;
         struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
+        struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_0_w1c {
@@ -774,6 +1007,8 @@ union cvmx_ciu_intx_en4_0_w1c {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_0_w1s {
@@ -843,12 +1078,42 @@ union cvmx_ciu_intx_en4_0_w1s {
                 uint64_t gpio:16;
                 uint64_t workq:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
+        struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_1 {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -886,12 +1151,76 @@ union cvmx_ciu_intx_en4_1 {
                 uint64_t wdog:16;
         } cn58xx;
         struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
+        struct cvmx_ciu_intx_en4_1_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_1_w1c {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_w1c_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -915,12 +1244,76 @@ union cvmx_ciu_intx_en4_1_w1c {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_en4_1_w1s {
         uint64_t u64;
         struct cvmx_ciu_intx_en4_1_w1s_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -944,6 +1337,42 @@ union cvmx_ciu_intx_en4_1_w1s {
                 uint64_t reserved_16_63:48;
                 uint64_t wdog:16;
         } cn58xx;
+        struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_sum0 {
@@ -1084,6 +1513,8 @@ union cvmx_ciu_intx_sum0 {
         struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
         struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
         struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
+        struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
+        struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_intx_sum4 {
@@ -1200,12 +1631,85 @@ union cvmx_ciu_intx_sum4 {
                 uint64_t workq:16;
         } cn58xx;
         struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
+        struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
+        struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
+};
+
+union cvmx_ciu_int33_sum0 {
+        uint64_t u64;
+        struct cvmx_ciu_int33_sum0_s {
+                uint64_t bootdma:1;
+                uint64_t mii:1;
+                uint64_t ipdppthr:1;
+                uint64_t powiq:1;
+                uint64_t twsi2:1;
+                uint64_t reserved_57_58:2;
+                uint64_t usb:1;
+                uint64_t timer:4;
+                uint64_t reserved_51_51:1;
+                uint64_t ipd_drp:1;
+                uint64_t reserved_49_49:1;
+                uint64_t gmx_drp:1;
+                uint64_t trace:1;
+                uint64_t rml:1;
+                uint64_t twsi:1;
+                uint64_t wdog_sum:1;
+                uint64_t pci_msi:4;
+                uint64_t pci_int:4;
+                uint64_t uart:2;
+                uint64_t mbox:2;
+                uint64_t gpio:16;
+                uint64_t workq:16;
+        } s;
+        struct cvmx_ciu_int33_sum0_s cn63xx;
+        struct cvmx_ciu_int33_sum0_s cn63xxp1;
+};
+
+union cvmx_ciu_int_dbg_sel {
+        uint64_t u64;
+        struct cvmx_ciu_int_dbg_sel_s {
+                uint64_t reserved_19_63:45;
+                uint64_t sel:3;
+                uint64_t reserved_10_15:6;
+                uint64_t irq:2;
+                uint64_t reserved_3_7:5;
+                uint64_t pp:3;
+        } s;
+        struct cvmx_ciu_int_dbg_sel_s cn63xx;
 };
 
 union cvmx_ciu_int_sum1 {
         uint64_t u64;
         struct cvmx_ciu_int_sum1_s {
-                uint64_t reserved_20_63:44;
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
                 uint64_t nand:1;
                 uint64_t mii1:1;
                 uint64_t usb1:1;
@@ -1250,6 +1754,42 @@ union cvmx_ciu_int_sum1 {
         struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
         struct cvmx_ciu_int_sum1_cn38xx cn58xx;
         struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
+        struct cvmx_ciu_int_sum1_cn63xx {
+                uint64_t rst:1;
+                uint64_t reserved_57_62:6;
+                uint64_t dfm:1;
+                uint64_t reserved_53_55:3;
+                uint64_t lmc0:1;
+                uint64_t srio1:1;
+                uint64_t srio0:1;
+                uint64_t pem1:1;
+                uint64_t pem0:1;
+                uint64_t ptp:1;
+                uint64_t agl:1;
+                uint64_t reserved_37_45:9;
+                uint64_t agx0:1;
+                uint64_t dpi:1;
+                uint64_t sli:1;
+                uint64_t usb:1;
+                uint64_t dfa:1;
+                uint64_t key:1;
+                uint64_t rad:1;
+                uint64_t tim:1;
+                uint64_t zip:1;
+                uint64_t pko:1;
+                uint64_t pip:1;
+                uint64_t ipd:1;
+                uint64_t l2c:1;
+                uint64_t pow:1;
+                uint64_t fpa:1;
+                uint64_t iob:1;
+                uint64_t mio:1;
+                uint64_t nand:1;
+                uint64_t mii1:1;
+                uint64_t reserved_6_17:12;
+                uint64_t wdog:6;
+        } cn63xx;
+        struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_mbox_clrx {
@@ -1269,6 +1809,8 @@ union cvmx_ciu_mbox_clrx {
         struct cvmx_ciu_mbox_clrx_s cn56xxp1;
         struct cvmx_ciu_mbox_clrx_s cn58xx;
         struct cvmx_ciu_mbox_clrx_s cn58xxp1;
+        struct cvmx_ciu_mbox_clrx_s cn63xx;
+        struct cvmx_ciu_mbox_clrx_s cn63xxp1;
 };
 
 union cvmx_ciu_mbox_setx {
@@ -1288,6 +1830,8 @@ union cvmx_ciu_mbox_setx {
         struct cvmx_ciu_mbox_setx_s cn56xxp1;
         struct cvmx_ciu_mbox_setx_s cn58xx;
         struct cvmx_ciu_mbox_setx_s cn58xxp1;
+        struct cvmx_ciu_mbox_setx_s cn63xx;
+        struct cvmx_ciu_mbox_setx_s cn63xxp1;
 };
 
 union cvmx_ciu_nmi {
@@ -1319,6 +1863,11 @@ union cvmx_ciu_nmi {
         struct cvmx_ciu_nmi_cn56xx cn56xxp1;
         struct cvmx_ciu_nmi_s cn58xx;
         struct cvmx_ciu_nmi_s cn58xxp1;
+        struct cvmx_ciu_nmi_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t nmi:6;
+        } cn63xx;
+        struct cvmx_ciu_nmi_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_pci_inta {
@@ -1338,6 +1887,8 @@ union cvmx_ciu_pci_inta {
         struct cvmx_ciu_pci_inta_s cn56xxp1;
         struct cvmx_ciu_pci_inta_s cn58xx;
         struct cvmx_ciu_pci_inta_s cn58xxp1;
+        struct cvmx_ciu_pci_inta_s cn63xx;
+        struct cvmx_ciu_pci_inta_s cn63xxp1;
 };
 
 union cvmx_ciu_pp_dbg {
@@ -1369,12 +1920,17 @@ union cvmx_ciu_pp_dbg {
         struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
         struct cvmx_ciu_pp_dbg_s cn58xx;
         struct cvmx_ciu_pp_dbg_s cn58xxp1;
+        struct cvmx_ciu_pp_dbg_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t ppdbg:6;
+        } cn63xx;
+        struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_pp_pokex {
         uint64_t u64;
         struct cvmx_ciu_pp_pokex_s {
-                uint64_t reserved_0_63:64;
+                uint64_t poke:64;
         } s;
         struct cvmx_ciu_pp_pokex_s cn30xx;
         struct cvmx_ciu_pp_pokex_s cn31xx;
@@ -1387,6 +1943,8 @@ union cvmx_ciu_pp_pokex {
         struct cvmx_ciu_pp_pokex_s cn56xxp1;
         struct cvmx_ciu_pp_pokex_s cn58xx;
         struct cvmx_ciu_pp_pokex_s cn58xxp1;
+        struct cvmx_ciu_pp_pokex_s cn63xx;
+        struct cvmx_ciu_pp_pokex_s cn63xxp1;
 };
 
 union cvmx_ciu_pp_rst {
@@ -1422,6 +1980,97 @@ union cvmx_ciu_pp_rst {
         struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
         struct cvmx_ciu_pp_rst_s cn58xx;
         struct cvmx_ciu_pp_rst_s cn58xxp1;
+        struct cvmx_ciu_pp_rst_cn63xx {
+                uint64_t reserved_6_63:58;
+                uint64_t rst:5;
+                uint64_t rst0:1;
+        } cn63xx;
+        struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
+};
+
+union cvmx_ciu_qlm0 {
+        uint64_t u64;
+        struct cvmx_ciu_qlm0_s {
+                uint64_t g2bypass:1;
+                uint64_t reserved_53_62:10;
+                uint64_t g2deemph:5;
+                uint64_t reserved_45_47:3;
+                uint64_t g2margin:5;
+                uint64_t reserved_32_39:8;
+                uint64_t txbypass:1;
+                uint64_t reserved_21_30:10;
+                uint64_t txdeemph:5;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } s;
+        struct cvmx_ciu_qlm0_s cn63xx;
+        struct cvmx_ciu_qlm0_cn63xxp1 {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_20_30:11;
+                uint64_t txdeemph:4;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } cn63xxp1;
+};
+
+union cvmx_ciu_qlm1 {
+        uint64_t u64;
+        struct cvmx_ciu_qlm1_s {
+                uint64_t g2bypass:1;
+                uint64_t reserved_53_62:10;
+                uint64_t g2deemph:5;
+                uint64_t reserved_45_47:3;
+                uint64_t g2margin:5;
+                uint64_t reserved_32_39:8;
+                uint64_t txbypass:1;
+                uint64_t reserved_21_30:10;
+                uint64_t txdeemph:5;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } s;
+        struct cvmx_ciu_qlm1_s cn63xx;
+        struct cvmx_ciu_qlm1_cn63xxp1 {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_20_30:11;
+                uint64_t txdeemph:4;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } cn63xxp1;
+};
+
+union cvmx_ciu_qlm2 {
+        uint64_t u64;
+        struct cvmx_ciu_qlm2_s {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_21_30:10;
+                uint64_t txdeemph:5;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } s;
+        struct cvmx_ciu_qlm2_s cn63xx;
+        struct cvmx_ciu_qlm2_cn63xxp1 {
+                uint64_t reserved_32_63:32;
+                uint64_t txbypass:1;
+                uint64_t reserved_20_30:11;
+                uint64_t txdeemph:4;
+                uint64_t reserved_13_15:3;
+                uint64_t txmargin:5;
+                uint64_t reserved_4_7:4;
+                uint64_t lane_en:4;
+        } cn63xxp1;
 };
 
 union cvmx_ciu_qlm_dcok {
@@ -1459,6 +2108,15 @@ union cvmx_ciu_qlm_jtgc {
         struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
         struct cvmx_ciu_qlm_jtgc_s cn56xx;
         struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
+        struct cvmx_ciu_qlm_jtgc_cn63xx {
+                uint64_t reserved_11_63:53;
+                uint64_t clk_div:3;
+                uint64_t reserved_6_7:2;
+                uint64_t mux_sel:2;
+                uint64_t reserved_3_3:1;
+                uint64_t bypass:3;
+        } cn63xx;
+        struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_qlm_jtgd {
@@ -1493,6 +2151,17 @@ union cvmx_ciu_qlm_jtgd {
                 uint64_t shft_cnt:5;
                 uint64_t shft_reg:32;
         } cn56xxp1;
+        struct cvmx_ciu_qlm_jtgd_cn63xx {
+                uint64_t capture:1;
+                uint64_t shift:1;
+                uint64_t update:1;
+                uint64_t reserved_43_60:18;
+                uint64_t select:3;
+                uint64_t reserved_37_39:3;
+                uint64_t shft_cnt:5;
+                uint64_t shft_reg:32;
+        } cn63xx;
+        struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1;
 };
 
 union cvmx_ciu_soft_bist {
@@ -1512,6 +2181,8 @@ union cvmx_ciu_soft_bist {
         struct cvmx_ciu_soft_bist_s cn56xxp1;
         struct cvmx_ciu_soft_bist_s cn58xx;
         struct cvmx_ciu_soft_bist_s cn58xxp1;
+        struct cvmx_ciu_soft_bist_s cn63xx;
+        struct cvmx_ciu_soft_bist_s cn63xxp1;
 };
 
 union cvmx_ciu_soft_prst {
@@ -1536,6 +2207,8 @@ union cvmx_ciu_soft_prst {
         struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
         struct cvmx_ciu_soft_prst_s cn58xx;
         struct cvmx_ciu_soft_prst_s cn58xxp1;
+        struct cvmx_ciu_soft_prst_cn52xx cn63xx;
+        struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
 };
 
 union cvmx_ciu_soft_prst1 {
@@ -1548,6 +2221,8 @@ union cvmx_ciu_soft_prst1 {
         struct cvmx_ciu_soft_prst1_s cn52xxp1;
         struct cvmx_ciu_soft_prst1_s cn56xx;
         struct cvmx_ciu_soft_prst1_s cn56xxp1;
+        struct cvmx_ciu_soft_prst1_s cn63xx;
+        struct cvmx_ciu_soft_prst1_s cn63xxp1;
 };
 
 union cvmx_ciu_soft_rst {
@@ -1567,6 +2242,8 @@ union cvmx_ciu_soft_rst {
         struct cvmx_ciu_soft_rst_s cn56xxp1;
         struct cvmx_ciu_soft_rst_s cn58xx;
         struct cvmx_ciu_soft_rst_s cn58xxp1;
+        struct cvmx_ciu_soft_rst_s cn63xx;
+        struct cvmx_ciu_soft_rst_s cn63xxp1;
 };
 
 union cvmx_ciu_timx {
@@ -1587,6 +2264,8 @@ union cvmx_ciu_timx {
         struct cvmx_ciu_timx_s cn56xxp1;
         struct cvmx_ciu_timx_s cn58xx;
         struct cvmx_ciu_timx_s cn58xxp1;
+        struct cvmx_ciu_timx_s cn63xx;
+        struct cvmx_ciu_timx_s cn63xxp1;
 };
 
 union cvmx_ciu_wdogx {
@@ -1611,6 +2290,8 @@ union cvmx_ciu_wdogx {
         struct cvmx_ciu_wdogx_s cn56xxp1;
         struct cvmx_ciu_wdogx_s cn58xx;
         struct cvmx_ciu_wdogx_s cn58xxp1;
+        struct cvmx_ciu_wdogx_s cn63xx;
+        struct cvmx_ciu_wdogx_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
index 5fdd6ba48a05..395564e8d1f0 100644
--- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,29 +28,22 @@
 #ifndef __CVMX_GPIO_DEFS_H__
 #define __CVMX_GPIO_DEFS_H__
 
-#define CVMX_GPIO_BIT_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
-#define CVMX_GPIO_BOOT_ENA \
-         CVMX_ADD_IO_SEG(0x00010700000008A8ull)
-#define CVMX_GPIO_CLK_GENX(offset) \
-         CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
-#define CVMX_GPIO_DBG_ENA \
-         CVMX_ADD_IO_SEG(0x00010700000008A0ull)
-#define CVMX_GPIO_INT_CLR \
-         CVMX_ADD_IO_SEG(0x0001070000000898ull)
-#define CVMX_GPIO_RX_DAT \
-         CVMX_ADD_IO_SEG(0x0001070000000880ull)
-#define CVMX_GPIO_TX_CLR \
-         CVMX_ADD_IO_SEG(0x0001070000000890ull)
-#define CVMX_GPIO_TX_SET \
-         CVMX_ADD_IO_SEG(0x0001070000000888ull)
-#define CVMX_GPIO_XBIT_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
+#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
+#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
+#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
+#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
+#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
+#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
+#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
+#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
+#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
+#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
 
 union cvmx_gpio_bit_cfgx {
         uint64_t u64;
         struct cvmx_gpio_bit_cfgx_s {
-                uint64_t reserved_15_63:49;
+                uint64_t reserved_17_63:47;
+                uint64_t synce_sel:2;
                 uint64_t clk_gen:1;
                 uint64_t clk_sel:2;
                 uint64_t fil_sel:4;
@@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx {
         struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
         struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
-        struct cvmx_gpio_bit_cfgx_s cn52xx;
-        struct cvmx_gpio_bit_cfgx_s cn52xxp1;
-        struct cvmx_gpio_bit_cfgx_s cn56xx;
-        struct cvmx_gpio_bit_cfgx_s cn56xxp1;
+        struct cvmx_gpio_bit_cfgx_cn52xx {
+                uint64_t reserved_15_63:49;
+                uint64_t clk_gen:1;
+                uint64_t clk_sel:2;
+                uint64_t fil_sel:4;
+                uint64_t fil_cnt:4;
+                uint64_t int_type:1;
+                uint64_t int_en:1;
+                uint64_t rx_xor:1;
+                uint64_t tx_oe:1;
+        } cn52xx;
+        struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
+        struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
+        struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
         struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
         struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
+        struct cvmx_gpio_bit_cfgx_s cn63xx;
+        struct cvmx_gpio_bit_cfgx_s cn63xxp1;
 };
 
 union cvmx_gpio_boot_ena {
@@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx {
         struct cvmx_gpio_clk_genx_s cn52xxp1;
         struct cvmx_gpio_clk_genx_s cn56xx;
         struct cvmx_gpio_clk_genx_s cn56xxp1;
+        struct cvmx_gpio_clk_genx_s cn63xx;
+        struct cvmx_gpio_clk_genx_s cn63xxp1;
+};
+
+union cvmx_gpio_clk_qlmx {
+        uint64_t u64;
+        struct cvmx_gpio_clk_qlmx_s {
+                uint64_t reserved_3_63:61;
+                uint64_t div:1;
+                uint64_t lane_sel:2;
+        } s;
+        struct cvmx_gpio_clk_qlmx_s cn63xx;
+        struct cvmx_gpio_clk_qlmx_s cn63xxp1;
 };
 
 union cvmx_gpio_dbg_ena {
@@ -133,6 +151,8 @@ union cvmx_gpio_int_clr {
         struct cvmx_gpio_int_clr_s cn56xxp1;
         struct cvmx_gpio_int_clr_s cn58xx;
         struct cvmx_gpio_int_clr_s cn58xxp1;
+        struct cvmx_gpio_int_clr_s cn63xx;
+        struct cvmx_gpio_int_clr_s cn63xxp1;
 };
 
 union cvmx_gpio_rx_dat {
@@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat {
         struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
         struct cvmx_gpio_rx_dat_cn38xx cn58xx;
         struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
+        struct cvmx_gpio_rx_dat_cn38xx cn63xx;
+        struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
 };
 
 union cvmx_gpio_tx_clr {
@@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr {
         struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
         struct cvmx_gpio_tx_clr_cn38xx cn58xx;
         struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
+        struct cvmx_gpio_tx_clr_cn38xx cn63xx;
+        struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
 };
 
 union cvmx_gpio_tx_set {
@@ -199,6 +223,8 @@ union cvmx_gpio_tx_set {
         struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
         struct cvmx_gpio_tx_set_cn38xx cn58xx;
         struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
+        struct cvmx_gpio_tx_set_cn38xx cn63xx;
+        struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
 };
 
 union cvmx_gpio_xbit_cfgx {
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
index 0ee36baec500..d7d856c2483d 100644
--- a/arch/mips/include/asm/octeon/cvmx-iob-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,55 +28,39 @@
 #ifndef __CVMX_IOB_DEFS_H__
 #define __CVMX_IOB_DEFS_H__
 
-#define CVMX_IOB_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00011800F00007F8ull)
-#define CVMX_IOB_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00011800F0000050ull)
-#define CVMX_IOB_DWB_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000028ull)
-#define CVMX_IOB_FAU_TIMEOUT \
-         CVMX_ADD_IO_SEG(0x00011800F0000000ull)
-#define CVMX_IOB_I2C_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000010ull)
-#define CVMX_IOB_INB_CONTROL_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000078ull)
-#define CVMX_IOB_INB_CONTROL_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F0000088ull)
-#define CVMX_IOB_INB_DATA_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000070ull)
-#define CVMX_IOB_INB_DATA_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F0000080ull)
-#define CVMX_IOB_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F0000060ull)
-#define CVMX_IOB_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00011800F0000058ull)
-#define CVMX_IOB_N2C_L2C_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000020ull)
-#define CVMX_IOB_N2C_RSP_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000008ull)
-#define CVMX_IOB_OUTB_COM_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000040ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000098ull)
-#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
-#define CVMX_IOB_OUTB_DATA_MATCH \
-         CVMX_ADD_IO_SEG(0x00011800F0000090ull)
-#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
-         CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
-#define CVMX_IOB_OUTB_FPA_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000048ull)
-#define CVMX_IOB_OUTB_REQ_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000038ull)
-#define CVMX_IOB_P2C_REQ_PRI_CNT \
-         CVMX_ADD_IO_SEG(0x00011800F0000018ull)
-#define CVMX_IOB_PKT_ERR \
-         CVMX_ADD_IO_SEG(0x00011800F0000068ull)
+#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
+#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
+#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
+#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
+#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
+#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
+#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
+#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
+#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
+#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
+#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
+#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
+#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
+#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
+#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
+#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
+#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
+#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
+#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
 
 union cvmx_iob_bist_status {
         uint64_t u64;
         struct cvmx_iob_bist_status_s {
-                uint64_t reserved_18_63:46;
+                uint64_t reserved_23_63:41;
+                uint64_t xmdfif:1;
+                uint64_t xmcfif:1;
+                uint64_t iorfif:1;
+                uint64_t rsdfif:1;
+                uint64_t iocfif:1;
                 uint64_t icnrcb:1;
                 uint64_t icr0:1;
                 uint64_t icr1:1;
@@ -96,40 +80,81 @@ union cvmx_iob_bist_status {
                 uint64_t ibd:1;
                 uint64_t icd:1;
         } s;
-        struct cvmx_iob_bist_status_s cn30xx;
-        struct cvmx_iob_bist_status_s cn31xx;
-        struct cvmx_iob_bist_status_s cn38xx;
-        struct cvmx_iob_bist_status_s cn38xxp2;
-        struct cvmx_iob_bist_status_s cn50xx;
-        struct cvmx_iob_bist_status_s cn52xx;
-        struct cvmx_iob_bist_status_s cn52xxp1;
-        struct cvmx_iob_bist_status_s cn56xx;
-        struct cvmx_iob_bist_status_s cn56xxp1;
-        struct cvmx_iob_bist_status_s cn58xx;
-        struct cvmx_iob_bist_status_s cn58xxp1;
+        struct cvmx_iob_bist_status_cn30xx {
+                uint64_t reserved_18_63:46;
+                uint64_t icnrcb:1;
+                uint64_t icr0:1;
+                uint64_t icr1:1;
+                uint64_t icnr1:1;
+                uint64_t icnr0:1;
+                uint64_t ibdr0:1;
+                uint64_t ibdr1:1;
+                uint64_t ibr0:1;
+                uint64_t ibr1:1;
+                uint64_t icnrt:1;
+                uint64_t ibrq0:1;
+                uint64_t ibrq1:1;
+                uint64_t icrn0:1;
+                uint64_t icrn1:1;
+                uint64_t icrp0:1;
+                uint64_t icrp1:1;
+                uint64_t ibd:1;
+                uint64_t icd:1;
+        } cn30xx;
+        struct cvmx_iob_bist_status_cn30xx cn31xx;
+        struct cvmx_iob_bist_status_cn30xx cn38xx;
+        struct cvmx_iob_bist_status_cn30xx cn38xxp2;
+        struct cvmx_iob_bist_status_cn30xx cn50xx;
+        struct cvmx_iob_bist_status_cn30xx cn52xx;
+        struct cvmx_iob_bist_status_cn30xx cn52xxp1;
+        struct cvmx_iob_bist_status_cn30xx cn56xx;
+        struct cvmx_iob_bist_status_cn30xx cn56xxp1;
+        struct cvmx_iob_bist_status_cn30xx cn58xx;
+        struct cvmx_iob_bist_status_cn30xx cn58xxp1;
+        struct cvmx_iob_bist_status_s cn63xx;
+        struct cvmx_iob_bist_status_s cn63xxp1;
 };
 
 union cvmx_iob_ctl_status {
         uint64_t u64;
         struct cvmx_iob_ctl_status_s {
-                uint64_t reserved_5_63:59;
+                uint64_t reserved_10_63:54;
+                uint64_t xmc_per:4;
+                uint64_t rr_mode:1;
                 uint64_t outb_mat:1;
                 uint64_t inb_mat:1;
                 uint64_t pko_enb:1;
                 uint64_t dwb_enb:1;
                 uint64_t fau_end:1;
         } s;
-        struct cvmx_iob_ctl_status_s cn30xx;
-        struct cvmx_iob_ctl_status_s cn31xx;
-        struct cvmx_iob_ctl_status_s cn38xx;
-        struct cvmx_iob_ctl_status_s cn38xxp2;
-        struct cvmx_iob_ctl_status_s cn50xx;
-        struct cvmx_iob_ctl_status_s cn52xx;
-        struct cvmx_iob_ctl_status_s cn52xxp1;
-        struct cvmx_iob_ctl_status_s cn56xx;
-        struct cvmx_iob_ctl_status_s cn56xxp1;
-        struct cvmx_iob_ctl_status_s cn58xx;
-        struct cvmx_iob_ctl_status_s cn58xxp1;
+        struct cvmx_iob_ctl_status_cn30xx {
+                uint64_t reserved_5_63:59;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+        } cn30xx;
+        struct cvmx_iob_ctl_status_cn30xx cn31xx;
+        struct cvmx_iob_ctl_status_cn30xx cn38xx;
+        struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
+        struct cvmx_iob_ctl_status_cn30xx cn50xx;
+        struct cvmx_iob_ctl_status_cn52xx {
+                uint64_t reserved_6_63:58;
+                uint64_t rr_mode:1;
+                uint64_t outb_mat:1;
+                uint64_t inb_mat:1;
+                uint64_t pko_enb:1;
+                uint64_t dwb_enb:1;
+                uint64_t fau_end:1;
+        } cn52xx;
+        struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
+        struct cvmx_iob_ctl_status_cn30xx cn56xx;
+        struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
+        struct cvmx_iob_ctl_status_cn30xx cn58xx;
+        struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
+        struct cvmx_iob_ctl_status_s cn63xx;
+        struct cvmx_iob_ctl_status_s cn63xxp1;
 };
 
 union cvmx_iob_dwb_pri_cnt {
@@ -147,6 +172,8 @@ union cvmx_iob_dwb_pri_cnt {
         struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
         struct cvmx_iob_dwb_pri_cnt_s cn58xx;
         struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_dwb_pri_cnt_s cn63xx;
+        struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_fau_timeout {
@@ -167,6 +194,8 @@ union cvmx_iob_fau_timeout {
         struct cvmx_iob_fau_timeout_s cn56xxp1;
         struct cvmx_iob_fau_timeout_s cn58xx;
         struct cvmx_iob_fau_timeout_s cn58xxp1;
+        struct cvmx_iob_fau_timeout_s cn63xx;
+        struct cvmx_iob_fau_timeout_s cn63xxp1;
 };
 
 union cvmx_iob_i2c_pri_cnt {
@@ -184,6 +213,8 @@ union cvmx_iob_i2c_pri_cnt {
         struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
         struct cvmx_iob_i2c_pri_cnt_s cn58xx;
         struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_i2c_pri_cnt_s cn63xx;
+        struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_inb_control_match {
@@ -206,6 +237,8 @@ union cvmx_iob_inb_control_match {
         struct cvmx_iob_inb_control_match_s cn56xxp1;
         struct cvmx_iob_inb_control_match_s cn58xx;
         struct cvmx_iob_inb_control_match_s cn58xxp1;
+        struct cvmx_iob_inb_control_match_s cn63xx;
+        struct cvmx_iob_inb_control_match_s cn63xxp1;
 };
 
 union cvmx_iob_inb_control_match_enb {
@@ -228,6 +261,8 @@ union cvmx_iob_inb_control_match_enb {
         struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
         struct cvmx_iob_inb_control_match_enb_s cn58xx;
         struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
+        struct cvmx_iob_inb_control_match_enb_s cn63xx;
+        struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_inb_data_match {
@@ -246,6 +281,8 @@ union cvmx_iob_inb_data_match {
         struct cvmx_iob_inb_data_match_s cn56xxp1;
         struct cvmx_iob_inb_data_match_s cn58xx;
         struct cvmx_iob_inb_data_match_s cn58xxp1;
+        struct cvmx_iob_inb_data_match_s cn63xx;
+        struct cvmx_iob_inb_data_match_s cn63xxp1;
 };
 
 union cvmx_iob_inb_data_match_enb {
@@ -264,6 +301,8 @@ union cvmx_iob_inb_data_match_enb {
         struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
         struct cvmx_iob_inb_data_match_enb_s cn58xx;
         struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
+        struct cvmx_iob_inb_data_match_enb_s cn63xx;
+        struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_int_enb {
@@ -294,6 +333,8 @@ union cvmx_iob_int_enb {
         struct cvmx_iob_int_enb_s cn56xxp1;
         struct cvmx_iob_int_enb_s cn58xx;
         struct cvmx_iob_int_enb_s cn58xxp1;
+        struct cvmx_iob_int_enb_s cn63xx;
+        struct cvmx_iob_int_enb_s cn63xxp1;
 };
 
 union cvmx_iob_int_sum {
@@ -324,6 +365,8 @@ union cvmx_iob_int_sum {
         struct cvmx_iob_int_sum_s cn56xxp1;
         struct cvmx_iob_int_sum_s cn58xx;
         struct cvmx_iob_int_sum_s cn58xxp1;
+        struct cvmx_iob_int_sum_s cn63xx;
+        struct cvmx_iob_int_sum_s cn63xxp1;
 };
 
 union cvmx_iob_n2c_l2c_pri_cnt {
@@ -341,6 +384,8 @@ union cvmx_iob_n2c_l2c_pri_cnt {
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
         struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
+        struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_n2c_rsp_pri_cnt {
@@ -358,6 +403,8 @@ union cvmx_iob_n2c_rsp_pri_cnt {
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
         struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
+        struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_outb_com_pri_cnt {
@@ -375,6 +422,8 @@ union cvmx_iob_outb_com_pri_cnt {
         struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
+        struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_outb_control_match {
@@ -397,6 +446,8 @@ union cvmx_iob_outb_control_match {
         struct cvmx_iob_outb_control_match_s cn56xxp1;
         struct cvmx_iob_outb_control_match_s cn58xx;
         struct cvmx_iob_outb_control_match_s cn58xxp1;
+        struct cvmx_iob_outb_control_match_s cn63xx;
+        struct cvmx_iob_outb_control_match_s cn63xxp1;
 };
 
 union cvmx_iob_outb_control_match_enb {
@@ -419,6 +470,8 @@ union cvmx_iob_outb_control_match_enb {
         struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
         struct cvmx_iob_outb_control_match_enb_s cn58xx;
         struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
+        struct cvmx_iob_outb_control_match_enb_s cn63xx;
+        struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_outb_data_match {
@@ -437,6 +490,8 @@ union cvmx_iob_outb_data_match {
         struct cvmx_iob_outb_data_match_s cn56xxp1;
         struct cvmx_iob_outb_data_match_s cn58xx;
         struct cvmx_iob_outb_data_match_s cn58xxp1;
+        struct cvmx_iob_outb_data_match_s cn63xx;
+        struct cvmx_iob_outb_data_match_s cn63xxp1;
 };
 
 union cvmx_iob_outb_data_match_enb {
@@ -455,6 +510,8 @@ union cvmx_iob_outb_data_match_enb {
         struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
         struct cvmx_iob_outb_data_match_enb_s cn58xx;
         struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
+        struct cvmx_iob_outb_data_match_enb_s cn63xx;
+        struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
 };
 
 union cvmx_iob_outb_fpa_pri_cnt {
@@ -472,6 +529,8 @@ union cvmx_iob_outb_fpa_pri_cnt {
         struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
+        struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_outb_req_pri_cnt {
@@ -489,6 +548,8 @@ union cvmx_iob_outb_req_pri_cnt {
         struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
         struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
         struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
+        struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_p2c_req_pri_cnt {
@@ -506,25 +567,46 @@ union cvmx_iob_p2c_req_pri_cnt {
         struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
         struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
         struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
+        struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
+        struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
 };
 
 union cvmx_iob_pkt_err {
         uint64_t u64;
         struct cvmx_iob_pkt_err_s {
+                uint64_t reserved_12_63:52;
+                uint64_t vport:6;
+                uint64_t port:6;
+        } s;
+        struct cvmx_iob_pkt_err_cn30xx {
                 uint64_t reserved_6_63:58;
                 uint64_t port:6;
+        } cn30xx;
+        struct cvmx_iob_pkt_err_cn30xx cn31xx;
+        struct cvmx_iob_pkt_err_cn30xx cn38xx;
+        struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
+        struct cvmx_iob_pkt_err_cn30xx cn50xx;
+        struct cvmx_iob_pkt_err_cn30xx cn52xx;
+        struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
+        struct cvmx_iob_pkt_err_cn30xx cn56xx;
+        struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
+        struct cvmx_iob_pkt_err_cn30xx cn58xx;
+        struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
+        struct cvmx_iob_pkt_err_s cn63xx;
+        struct cvmx_iob_pkt_err_s cn63xxp1;
+};
+
+union cvmx_iob_to_cmb_credits {
+        uint64_t u64;
+        struct cvmx_iob_to_cmb_credits_s {
+                uint64_t reserved_9_63:55;
+                uint64_t pko_rd:3;
+                uint64_t ncb_rd:3;
+                uint64_t ncb_wr:3;
         } s;
-        struct cvmx_iob_pkt_err_s cn30xx;
-        struct cvmx_iob_pkt_err_s cn31xx;
-        struct cvmx_iob_pkt_err_s cn38xx;
-        struct cvmx_iob_pkt_err_s cn38xxp2;
-        struct cvmx_iob_pkt_err_s cn50xx;
-        struct cvmx_iob_pkt_err_s cn52xx;
-        struct cvmx_iob_pkt_err_s cn52xxp1;
-        struct cvmx_iob_pkt_err_s cn56xx;
-        struct cvmx_iob_pkt_err_s cn56xxp1;
-        struct cvmx_iob_pkt_err_s cn58xx;
-        struct cvmx_iob_pkt_err_s cn58xxp1;
+        struct cvmx_iob_to_cmb_credits_s cn52xx;
+        struct cvmx_iob_to_cmb_credits_s cn63xx;
+        struct cvmx_iob_to_cmb_credits_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
index f8b8fc657d2c..e0a5bfe88d04 100644
--- a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,104 +28,57 @@
 #ifndef __CVMX_IPD_DEFS_H__
 #define __CVMX_IPD_DEFS_H__
 
-#define CVMX_IPD_1ST_MBUFF_SKIP \
-         CVMX_ADD_IO_SEG(0x00014F0000000000ull)
-#define CVMX_IPD_1st_NEXT_PTR_BACK \
-         CVMX_ADD_IO_SEG(0x00014F0000000150ull)
-#define CVMX_IPD_2nd_NEXT_PTR_BACK \
-         CVMX_ADD_IO_SEG(0x00014F0000000158ull)
-#define CVMX_IPD_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00014F00000007F8ull)
-#define CVMX_IPD_BP_PRT_RED_END \
-         CVMX_ADD_IO_SEG(0x00014F0000000328ull)
-#define CVMX_IPD_CLK_COUNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000338ull)
-#define CVMX_IPD_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00014F0000000018ull)
-#define CVMX_IPD_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00014F0000000160ull)
-#define CVMX_IPD_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00014F0000000168ull)
-#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \
-         CVMX_ADD_IO_SEG(0x00014F0000000008ull)
-#define CVMX_IPD_PACKET_MBUFF_SIZE \
-         CVMX_ADD_IO_SEG(0x00014F0000000010ull)
-#define CVMX_IPD_PKT_PTR_VALID \
-         CVMX_ADD_IO_SEG(0x00014F0000000358ull)
-#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36)
-#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8))
-#define CVMX_IPD_PORT_QOS_INTX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8))
-#define CVMX_IPD_PORT_QOS_X_CNT(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8))
-#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \
-         CVMX_ADD_IO_SEG(0x00014F0000000348ull)
-#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \
-         CVMX_ADD_IO_SEG(0x00014F0000000350ull)
-#define CVMX_IPD_PTR_COUNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000320ull)
-#define CVMX_IPD_PWP_PTR_FIFO_CTL \
-         CVMX_ADD_IO_SEG(0x00014F0000000340ull)
-#define CVMX_IPD_QOS0_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000178ull)
-#define CVMX_IPD_QOS1_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000180ull)
-#define CVMX_IPD_QOS2_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000188ull)
-#define CVMX_IPD_QOS3_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000190ull)
-#define CVMX_IPD_QOS4_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F0000000198ull)
-#define CVMX_IPD_QOS5_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
-#define CVMX_IPD_QOS6_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
-#define CVMX_IPD_QOS7_RED_MARKS \
-         CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
-#define CVMX_IPD_QOSX_RED_MARKS(offset) \
-         CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
-#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000330ull)
-#define CVMX_IPD_RED_PORT_ENABLE \
-         CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
-#define CVMX_IPD_RED_PORT_ENABLE2 \
-         CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
-#define CVMX_IPD_RED_QUE0_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
-#define CVMX_IPD_RED_QUE1_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
-#define CVMX_IPD_RED_QUE2_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
-#define CVMX_IPD_RED_QUE3_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
-#define CVMX_IPD_RED_QUE4_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000300ull)
-#define CVMX_IPD_RED_QUE5_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000308ull)
-#define CVMX_IPD_RED_QUE6_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000310ull)
-#define CVMX_IPD_RED_QUE7_PARAM \
-         CVMX_ADD_IO_SEG(0x00014F0000000318ull)
-#define CVMX_IPD_RED_QUEX_PARAM(offset) \
-         CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
-#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000148ull)
-#define CVMX_IPD_SUB_PORT_FCS \
-         CVMX_ADD_IO_SEG(0x00014F0000000170ull)
-#define CVMX_IPD_SUB_PORT_QOS_CNT \
-         CVMX_ADD_IO_SEG(0x00014F0000000800ull)
-#define CVMX_IPD_WQE_FPA_QUEUE \
-         CVMX_ADD_IO_SEG(0x00014F0000000020ull)
-#define CVMX_IPD_WQE_PTR_VALID \
-         CVMX_ADD_IO_SEG(0x00014F0000000360ull)
+#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
+#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
+#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
+#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
+#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
+#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
+#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
+#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
+#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
+#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
+#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
+#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
+#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
+#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
+#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
+#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
+#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
+#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
+#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
+#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
+#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
+#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
+#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
+#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
+#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
+#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
+#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
+#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
+#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
+#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
+#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
+#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
+#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
+#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
+#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
+#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
+#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
+#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
+#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
+#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
+#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
+#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
+#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
+#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
+#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
 
 union cvmx_ipd_1st_mbuff_skip {
         uint64_t u64;
@@ -144,6 +97,8 @@ union cvmx_ipd_1st_mbuff_skip {
         struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
         struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
         struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
+        struct cvmx_ipd_1st_mbuff_skip_s cn63xx;
+        struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;
 };
 
 union cvmx_ipd_1st_next_ptr_back {
@@ -163,6 +118,8 @@ union cvmx_ipd_1st_next_ptr_back {
         struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
         struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
         struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
+        struct cvmx_ipd_1st_next_ptr_back_s cn63xx;
+        struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;
 };
 
 union cvmx_ipd_2nd_next_ptr_back {
@@ -182,6 +139,8 @@ union cvmx_ipd_2nd_next_ptr_back {
         struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
         struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
         struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
+        struct cvmx_ipd_2nd_next_ptr_back_s cn63xx;
+        struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;
 };
 
 union cvmx_ipd_bist_status {
@@ -236,13 +195,15 @@ union cvmx_ipd_bist_status {
         struct cvmx_ipd_bist_status_s cn56xxp1;
         struct cvmx_ipd_bist_status_cn30xx cn58xx;
         struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
+        struct cvmx_ipd_bist_status_s cn63xx;
+        struct cvmx_ipd_bist_status_s cn63xxp1;
 };
 
 union cvmx_ipd_bp_prt_red_end {
         uint64_t u64;
         struct cvmx_ipd_bp_prt_red_end_s {
-                uint64_t reserved_40_63:24;
-                uint64_t prt_enb:40;
+                uint64_t reserved_44_63:20;
+                uint64_t prt_enb:44;
         } s;
         struct cvmx_ipd_bp_prt_red_end_cn30xx {
                 uint64_t reserved_36_63:28;
@@ -252,12 +213,17 @@ union cvmx_ipd_bp_prt_red_end {
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
-        struct cvmx_ipd_bp_prt_red_end_s cn52xx;
-        struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
-        struct cvmx_ipd_bp_prt_red_end_s cn56xx;
-        struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx {
+                uint64_t reserved_40_63:24;
+                uint64_t prt_enb:40;
+        } cn52xx;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
+        struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
         struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
+        struct cvmx_ipd_bp_prt_red_end_s cn63xx;
+        struct cvmx_ipd_bp_prt_red_end_s cn63xxp1;
 };
 
 union cvmx_ipd_clk_count {
@@ -276,12 +242,17 @@ union cvmx_ipd_clk_count {
         struct cvmx_ipd_clk_count_s cn56xxp1;
         struct cvmx_ipd_clk_count_s cn58xx;
         struct cvmx_ipd_clk_count_s cn58xxp1;
+        struct cvmx_ipd_clk_count_s cn63xx;
+        struct cvmx_ipd_clk_count_s cn63xxp1;
 };
 
 union cvmx_ipd_ctl_status {
         uint64_t u64;
         struct cvmx_ipd_ctl_status_s {
-                uint64_t reserved_15_63:49;
+                uint64_t reserved_18_63:46;
+                uint64_t use_sop:1;
+                uint64_t rst_done:1;
+                uint64_t clken:1;
                 uint64_t no_wptr:1;
                 uint64_t pq_apkt:1;
                 uint64_t pq_nabuf:1;
@@ -322,11 +293,27 @@ union cvmx_ipd_ctl_status {
                 uint64_t opc_mode:2;
                 uint64_t ipd_en:1;
         } cn38xxp2;
-        struct cvmx_ipd_ctl_status_s cn50xx;
-        struct cvmx_ipd_ctl_status_s cn52xx;
-        struct cvmx_ipd_ctl_status_s cn52xxp1;
-        struct cvmx_ipd_ctl_status_s cn56xx;
-        struct cvmx_ipd_ctl_status_s cn56xxp1;
+        struct cvmx_ipd_ctl_status_cn50xx {
+                uint64_t reserved_15_63:49;
+                uint64_t no_wptr:1;
+                uint64_t pq_apkt:1;
+                uint64_t pq_nabuf:1;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+        } cn50xx;
+        struct cvmx_ipd_ctl_status_cn50xx cn52xx;
+        struct cvmx_ipd_ctl_status_cn50xx cn52xxp1;
+        struct cvmx_ipd_ctl_status_cn50xx cn56xx;
+        struct cvmx_ipd_ctl_status_cn50xx cn56xxp1;
         struct cvmx_ipd_ctl_status_cn58xx {
                 uint64_t reserved_12_63:52;
                 uint64_t ipd_full:1;
@@ -342,6 +329,25 @@ union cvmx_ipd_ctl_status {
                 uint64_t ipd_en:1;
         } cn58xx;
         struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
+        struct cvmx_ipd_ctl_status_s cn63xx;
+        struct cvmx_ipd_ctl_status_cn63xxp1 {
+                uint64_t reserved_16_63:48;
+                uint64_t clken:1;
+                uint64_t no_wptr:1;
+                uint64_t pq_apkt:1;
+                uint64_t pq_nabuf:1;
+                uint64_t ipd_full:1;
+                uint64_t pkt_off:1;
+                uint64_t len_m8:1;
+                uint64_t reset:1;
+                uint64_t addpkt:1;
+                uint64_t naddbuf:1;
+                uint64_t pkt_lend:1;
+                uint64_t wqe_lend:1;
+                uint64_t pbp_en:1;
+                uint64_t opc_mode:2;
+                uint64_t ipd_en:1;
+        } cn63xxp1;
 };
 
 union cvmx_ipd_int_enb {
@@ -391,6 +397,8 @@ union cvmx_ipd_int_enb {
         struct cvmx_ipd_int_enb_s cn56xxp1;
         struct cvmx_ipd_int_enb_cn38xx cn58xx;
         struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
+        struct cvmx_ipd_int_enb_s cn63xx;
+        struct cvmx_ipd_int_enb_s cn63xxp1;
 };
 
 union cvmx_ipd_int_sum {
@@ -440,6 +448,8 @@ union cvmx_ipd_int_sum {
         struct cvmx_ipd_int_sum_s cn56xxp1;
         struct cvmx_ipd_int_sum_cn38xx cn58xx;
         struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
+        struct cvmx_ipd_int_sum_s cn63xx;
+        struct cvmx_ipd_int_sum_s cn63xxp1;
 };
 
 union cvmx_ipd_not_1st_mbuff_skip {
@@ -459,6 +469,8 @@ union cvmx_ipd_not_1st_mbuff_skip {
         struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
         struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
+        struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;
+        struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;
 };
 
 union cvmx_ipd_packet_mbuff_size {
@@ -478,6 +490,8 @@ union cvmx_ipd_packet_mbuff_size {
         struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
         struct cvmx_ipd_packet_mbuff_size_s cn58xx;
         struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
+        struct cvmx_ipd_packet_mbuff_size_s cn63xx;
+        struct cvmx_ipd_packet_mbuff_size_s cn63xxp1;
 };
 
 union cvmx_ipd_pkt_ptr_valid {
@@ -496,6 +510,8 @@ union cvmx_ipd_pkt_ptr_valid {
         struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
         struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
         struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
+        struct cvmx_ipd_pkt_ptr_valid_s cn63xx;
+        struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;
 };
 
 union cvmx_ipd_portx_bp_page_cnt {
@@ -516,6 +532,8 @@ union cvmx_ipd_portx_bp_page_cnt {
         struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
         struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
         struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
+        struct cvmx_ipd_portx_bp_page_cnt_s cn63xx;
+        struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_portx_bp_page_cnt2 {
@@ -529,6 +547,19 @@ union cvmx_ipd_portx_bp_page_cnt2 {
         struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
         struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
+        struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;
+        struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;
+};
+
+union cvmx_ipd_portx_bp_page_cnt3 {
+        uint64_t u64;
+        struct cvmx_ipd_portx_bp_page_cnt3_s {
+                uint64_t reserved_18_63:46;
+                uint64_t bp_enb:1;
+                uint64_t page_cnt:17;
+        } s;
+        struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;
+        struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;
 };
 
 union cvmx_ipd_port_bp_counters2_pairx {
@@ -541,6 +572,18 @@ union cvmx_ipd_port_bp_counters2_pairx {
         struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
         struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
+        struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
+        struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
+};
+
+union cvmx_ipd_port_bp_counters3_pairx {
+        uint64_t u64;
+        struct cvmx_ipd_port_bp_counters3_pairx_s {
+                uint64_t reserved_25_63:39;
+                uint64_t cnt_val:25;
+        } s;
+        struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
+        struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
 };
 
 union cvmx_ipd_port_bp_counters_pairx {
@@ -560,6 +603,8 @@ union cvmx_ipd_port_bp_counters_pairx {
         struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
         struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
         struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
+        struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
+        struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
 };
 
 union cvmx_ipd_port_qos_x_cnt {
@@ -572,6 +617,8 @@ union cvmx_ipd_port_qos_x_cnt {
         struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
         struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
         struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
+        struct cvmx_ipd_port_qos_x_cnt_s cn63xx;
+        struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_port_qos_intx {
@@ -583,6 +630,8 @@ union cvmx_ipd_port_qos_intx {
         struct cvmx_ipd_port_qos_intx_s cn52xxp1;
         struct cvmx_ipd_port_qos_intx_s cn56xx;
         struct cvmx_ipd_port_qos_intx_s cn56xxp1;
+        struct cvmx_ipd_port_qos_intx_s cn63xx;
+        struct cvmx_ipd_port_qos_intx_s cn63xxp1;
 };
 
 union cvmx_ipd_port_qos_int_enbx {
@@ -594,6 +643,8 @@ union cvmx_ipd_port_qos_int_enbx {
         struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
         struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
         struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
+        struct cvmx_ipd_port_qos_int_enbx_s cn63xx;
+        struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;
 };
 
 union cvmx_ipd_prc_hold_ptr_fifo_ctl {
@@ -616,6 +667,8 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl {
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
+        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
+        struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
 };
 
 union cvmx_ipd_prc_port_ptr_fifo_ctl {
@@ -637,6 +690,8 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl {
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
+        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
+        struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
 };
 
 union cvmx_ipd_ptr_count {
@@ -660,6 +715,8 @@ union cvmx_ipd_ptr_count {
         struct cvmx_ipd_ptr_count_s cn56xxp1;
         struct cvmx_ipd_ptr_count_s cn58xx;
         struct cvmx_ipd_ptr_count_s cn58xxp1;
+        struct cvmx_ipd_ptr_count_s cn63xx;
+        struct cvmx_ipd_ptr_count_s cn63xxp1;
 };
 
 union cvmx_ipd_pwp_ptr_fifo_ctl {
@@ -683,6 +740,8 @@ union cvmx_ipd_pwp_ptr_fifo_ctl {
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
         struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
+        struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;
+        struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;
 };
 
 union cvmx_ipd_qosx_red_marks {
@@ -702,6 +761,8 @@ union cvmx_ipd_qosx_red_marks {
         struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
         struct cvmx_ipd_qosx_red_marks_s cn58xx;
         struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
+        struct cvmx_ipd_qosx_red_marks_s cn63xx;
+        struct cvmx_ipd_qosx_red_marks_s cn63xxp1;
 };
 
 union cvmx_ipd_que0_free_page_cnt {
@@ -721,6 +782,8 @@ union cvmx_ipd_que0_free_page_cnt {
         struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
         struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
         struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
+        struct cvmx_ipd_que0_free_page_cnt_s cn63xx;
+        struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_red_port_enable {
@@ -741,18 +804,25 @@ union cvmx_ipd_red_port_enable {
         struct cvmx_ipd_red_port_enable_s cn56xxp1;
         struct cvmx_ipd_red_port_enable_s cn58xx;
         struct cvmx_ipd_red_port_enable_s cn58xxp1;
+        struct cvmx_ipd_red_port_enable_s cn63xx;
+        struct cvmx_ipd_red_port_enable_s cn63xxp1;
 };
 
 union cvmx_ipd_red_port_enable2 {
         uint64_t u64;
         struct cvmx_ipd_red_port_enable2_s {
+                uint64_t reserved_8_63:56;
+                uint64_t prt_enb:8;
+        } s;
+        struct cvmx_ipd_red_port_enable2_cn52xx {
                 uint64_t reserved_4_63:60;
                 uint64_t prt_enb:4;
-        } s;
-        struct cvmx_ipd_red_port_enable2_s cn52xx;
-        struct cvmx_ipd_red_port_enable2_s cn52xxp1;
-        struct cvmx_ipd_red_port_enable2_s cn56xx;
-        struct cvmx_ipd_red_port_enable2_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
+        struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
+        struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
+        struct cvmx_ipd_red_port_enable2_s cn63xx;
+        struct cvmx_ipd_red_port_enable2_s cn63xxp1;
 };
 
 union cvmx_ipd_red_quex_param {
@@ -775,6 +845,8 @@ union cvmx_ipd_red_quex_param {
         struct cvmx_ipd_red_quex_param_s cn56xxp1;
         struct cvmx_ipd_red_quex_param_s cn58xx;
         struct cvmx_ipd_red_quex_param_s cn58xxp1;
+        struct cvmx_ipd_red_quex_param_s cn63xx;
+        struct cvmx_ipd_red_quex_param_s cn63xxp1;
 };
 
 union cvmx_ipd_sub_port_bp_page_cnt {
@@ -795,6 +867,8 @@ union cvmx_ipd_sub_port_bp_page_cnt {
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
         struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
+        struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
+        struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_sub_port_fcs {
@@ -822,6 +896,8 @@ union cvmx_ipd_sub_port_fcs {
         struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
         struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
         struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
+        struct cvmx_ipd_sub_port_fcs_s cn63xx;
+        struct cvmx_ipd_sub_port_fcs_s cn63xxp1;
 };
 
 union cvmx_ipd_sub_port_qos_cnt {
@@ -835,6 +911,8 @@ union cvmx_ipd_sub_port_qos_cnt {
         struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
         struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
         struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
+        struct cvmx_ipd_sub_port_qos_cnt_s cn63xx;
+        struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;
 };
 
 union cvmx_ipd_wqe_fpa_queue {
@@ -854,6 +932,8 @@ union cvmx_ipd_wqe_fpa_queue {
         struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
         struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
         struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
+        struct cvmx_ipd_wqe_fpa_queue_s cn63xx;
+        struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;
 };
 
 union cvmx_ipd_wqe_ptr_valid {
@@ -872,6 +952,8 @@ union cvmx_ipd_wqe_ptr_valid {
         struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
         struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
         struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
+        struct cvmx_ipd_wqe_ptr_valid_s cn63xx;
+        struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
index 337583842b51..7a50a0beb472 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,70 +28,113 @@
 #ifndef __CVMX_L2C_DEFS_H__
 #define __CVMX_L2C_DEFS_H__
 
-#define CVMX_L2C_BST0 \
-         CVMX_ADD_IO_SEG(0x00011800800007F8ull)
-#define CVMX_L2C_BST1 \
-         CVMX_ADD_IO_SEG(0x00011800800007F0ull)
-#define CVMX_L2C_BST2 \
-         CVMX_ADD_IO_SEG(0x00011800800007E8ull)
-#define CVMX_L2C_CFG \
-         CVMX_ADD_IO_SEG(0x0001180080000000ull)
-#define CVMX_L2C_DBG \
-         CVMX_ADD_IO_SEG(0x0001180080000030ull)
-#define CVMX_L2C_DUT \
-         CVMX_ADD_IO_SEG(0x0001180080000050ull)
-#define CVMX_L2C_GRPWRR0 \
-         CVMX_ADD_IO_SEG(0x00011800800000C8ull)
-#define CVMX_L2C_GRPWRR1 \
-         CVMX_ADD_IO_SEG(0x00011800800000D0ull)
-#define CVMX_L2C_INT_EN \
-         CVMX_ADD_IO_SEG(0x0001180080000100ull)
-#define CVMX_L2C_INT_STAT \
-         CVMX_ADD_IO_SEG(0x00011800800000F8ull)
-#define CVMX_L2C_LCKBASE \
-         CVMX_ADD_IO_SEG(0x0001180080000058ull)
-#define CVMX_L2C_LCKOFF \
-         CVMX_ADD_IO_SEG(0x0001180080000060ull)
-#define CVMX_L2C_LFB0 \
-         CVMX_ADD_IO_SEG(0x0001180080000038ull)
-#define CVMX_L2C_LFB1 \
-         CVMX_ADD_IO_SEG(0x0001180080000040ull)
-#define CVMX_L2C_LFB2 \
-         CVMX_ADD_IO_SEG(0x0001180080000048ull)
-#define CVMX_L2C_LFB3 \
-         CVMX_ADD_IO_SEG(0x00011800800000B8ull)
-#define CVMX_L2C_OOB \
-         CVMX_ADD_IO_SEG(0x00011800800000D8ull)
-#define CVMX_L2C_OOB1 \
-         CVMX_ADD_IO_SEG(0x00011800800000E0ull)
-#define CVMX_L2C_OOB2 \
-         CVMX_ADD_IO_SEG(0x00011800800000E8ull)
-#define CVMX_L2C_OOB3 \
-         CVMX_ADD_IO_SEG(0x00011800800000F0ull)
-#define CVMX_L2C_PFC0 \
-         CVMX_ADD_IO_SEG(0x0001180080000098ull)
-#define CVMX_L2C_PFC1 \
-         CVMX_ADD_IO_SEG(0x00011800800000A0ull)
-#define CVMX_L2C_PFC2 \
-         CVMX_ADD_IO_SEG(0x00011800800000A8ull)
-#define CVMX_L2C_PFC3 \
-         CVMX_ADD_IO_SEG(0x00011800800000B0ull)
-#define CVMX_L2C_PFCTL \
-         CVMX_ADD_IO_SEG(0x0001180080000090ull)
-#define CVMX_L2C_PFCX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8))
-#define CVMX_L2C_PPGRP \
-         CVMX_ADD_IO_SEG(0x00011800800000C0ull)
-#define CVMX_L2C_SPAR0 \
-         CVMX_ADD_IO_SEG(0x0001180080000068ull)
-#define CVMX_L2C_SPAR1 \
-         CVMX_ADD_IO_SEG(0x0001180080000070ull)
-#define CVMX_L2C_SPAR2 \
-         CVMX_ADD_IO_SEG(0x0001180080000078ull)
-#define CVMX_L2C_SPAR3 \
-         CVMX_ADD_IO_SEG(0x0001180080000080ull)
-#define CVMX_L2C_SPAR4 \
-         CVMX_ADD_IO_SEG(0x0001180080000088ull)
+#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
+#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
+#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
+#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
+#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
+#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
+#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
+#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
+#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
+#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
+#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
+#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
+#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
+#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
+#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
+#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
+#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
+#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
+#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
+#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
+#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
+#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
+#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
+#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
+#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
+#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
+#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
+#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
+#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull))
+#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull))
+#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull))
+#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
+#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
+#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
+#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
+#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
+#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
+#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
+#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
+#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
+#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
+#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
+#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
+#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
+#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
+#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
+#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
+#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
+#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
+#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
+#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
+#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
+#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
+#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
+#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
+#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
+#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
+#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
+#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
+#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
+#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
+#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
+#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
+#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
+#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
+#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
+#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
+#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
+#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
+#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
+#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
+#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
+#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
+#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
+
+union cvmx_l2c_big_ctl {
+        uint64_t u64;
+        struct cvmx_l2c_big_ctl_s {
+                uint64_t reserved_8_63:56;
+                uint64_t maxdram:4;
+                uint64_t reserved_1_3:3;
+                uint64_t disable:1;
+        } s;
+        struct cvmx_l2c_big_ctl_s cn63xx;
+};
+
+union cvmx_l2c_bst {
+        uint64_t u64;
+        struct cvmx_l2c_bst_s {
+                uint64_t reserved_38_63:26;
+                uint64_t dutfl:6;
+                uint64_t reserved_17_31:15;
+                uint64_t ioccmdfl:1;
+                uint64_t reserved_13_15:3;
+                uint64_t iocdatfl:1;
+                uint64_t reserved_9_11:3;
+                uint64_t dutresfl:1;
+                uint64_t reserved_5_7:3;
+                uint64_t vrtfl:1;
+                uint64_t reserved_1_3:3;
+                uint64_t tdffl:1;
+        } s;
+        struct cvmx_l2c_bst_s cn63xx;
+        struct cvmx_l2c_bst_s cn63xxp1;
+};
 
 union cvmx_l2c_bst0 {
         uint64_t u64;
@@ -253,6 +296,48 @@ union cvmx_l2c_bst2 {
         struct cvmx_l2c_bst2_cn56xx cn58xxp1;
 };
 
+union cvmx_l2c_bst_memx {
+        uint64_t u64;
+        struct cvmx_l2c_bst_memx_s {
+                uint64_t start_bist:1;
+                uint64_t clear_bist:1;
+                uint64_t reserved_5_61:57;
+                uint64_t rdffl:1;
+                uint64_t vbffl:4;
+        } s;
+        struct cvmx_l2c_bst_memx_s cn63xx;
+        struct cvmx_l2c_bst_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_bst_tdtx {
+        uint64_t u64;
+        struct cvmx_l2c_bst_tdtx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t fbfrspfl:8;
+                uint64_t sbffl:8;
+                uint64_t fbffl:8;
+                uint64_t l2dfl:8;
+        } s;
+        struct cvmx_l2c_bst_tdtx_s cn63xx;
+        struct cvmx_l2c_bst_tdtx_cn63xxp1 {
+                uint64_t reserved_24_63:40;
+                uint64_t sbffl:8;
+                uint64_t fbffl:8;
+                uint64_t l2dfl:8;
+        } cn63xxp1;
+};
+
+union cvmx_l2c_bst_ttgx {
+        uint64_t u64;
+        struct cvmx_l2c_bst_ttgx_s {
+                uint64_t reserved_17_63:47;
+                uint64_t lrufl:1;
+                uint64_t tagfl:16;
+        } s;
+        struct cvmx_l2c_bst_ttgx_s cn63xx;
+        struct cvmx_l2c_bst_ttgx_s cn63xxp1;
+};
+
 union cvmx_l2c_cfg {
         uint64_t u64;
         struct cvmx_l2c_cfg_s {
@@ -333,6 +418,49 @@ union cvmx_l2c_cfg {
         } cn58xxp1;
 };
 
+union cvmx_l2c_cop0_mapx {
+        uint64_t u64;
+        struct cvmx_l2c_cop0_mapx_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_l2c_cop0_mapx_s cn63xx;
+        struct cvmx_l2c_cop0_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_ctl {
+        uint64_t u64;
+        struct cvmx_l2c_ctl_s {
+                uint64_t reserved_28_63:36;
+                uint64_t disstgl2i:1;
+                uint64_t l2dfsbe:1;
+                uint64_t l2dfdbe:1;
+                uint64_t discclk:1;
+                uint64_t maxvab:4;
+                uint64_t maxlfb:4;
+                uint64_t rsp_arb_mode:1;
+                uint64_t xmc_arb_mode:1;
+                uint64_t ef_ena:1;
+                uint64_t ef_cnt:7;
+                uint64_t vab_thresh:4;
+                uint64_t disecc:1;
+                uint64_t disidxalias:1;
+        } s;
+        struct cvmx_l2c_ctl_s cn63xx;
+        struct cvmx_l2c_ctl_cn63xxp1 {
+                uint64_t reserved_25_63:39;
+                uint64_t discclk:1;
+                uint64_t maxvab:4;
+                uint64_t maxlfb:4;
+                uint64_t rsp_arb_mode:1;
+                uint64_t xmc_arb_mode:1;
+                uint64_t ef_ena:1;
+                uint64_t ef_cnt:7;
+                uint64_t vab_thresh:4;
+                uint64_t disecc:1;
+                uint64_t disidxalias:1;
+        } cn63xxp1;
+};
+
 union cvmx_l2c_dbg {
         uint64_t u64;
         struct cvmx_l2c_dbg_s {
@@ -349,7 +477,9 @@ union cvmx_l2c_dbg {
                 uint64_t reserved_13_63:51;
                 uint64_t lfb_enum:2;
                 uint64_t lfb_dmp:1;
-                uint64_t reserved_5_9:5;
+                uint64_t reserved_7_9:3;
+                uint64_t ppnum:1;
+                uint64_t reserved_5_5:1;
                 uint64_t set:2;
                 uint64_t finv:1;
                 uint64_t l2d:1;
@@ -420,6 +550,79 @@ union cvmx_l2c_dut {
         struct cvmx_l2c_dut_s cn58xxp1;
 };
 
+union cvmx_l2c_dut_mapx {
+        uint64_t u64;
+        struct cvmx_l2c_dut_mapx_s {
+                uint64_t reserved_38_63:26;
+                uint64_t tag:28;
+                uint64_t reserved_1_9:9;
+                uint64_t valid:1;
+        } s;
+        struct cvmx_l2c_dut_mapx_s cn63xx;
+        struct cvmx_l2c_dut_mapx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_tdtx {
+        uint64_t u64;
+        struct cvmx_l2c_err_tdtx_s {
+                uint64_t dbe:1;
+                uint64_t sbe:1;
+                uint64_t vdbe:1;
+                uint64_t vsbe:1;
+                uint64_t syn:10;
+                uint64_t reserved_21_49:29;
+                uint64_t wayidx:17;
+                uint64_t reserved_2_3:2;
+                uint64_t type:2;
+        } s;
+        struct cvmx_l2c_err_tdtx_s cn63xx;
+        struct cvmx_l2c_err_tdtx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_ttgx {
+        uint64_t u64;
+        struct cvmx_l2c_err_ttgx_s {
+                uint64_t dbe:1;
+                uint64_t sbe:1;
+                uint64_t noway:1;
+                uint64_t reserved_56_60:5;
+                uint64_t syn:6;
+                uint64_t reserved_21_49:29;
+                uint64_t wayidx:14;
+                uint64_t reserved_2_6:5;
+                uint64_t type:2;
+        } s;
+        struct cvmx_l2c_err_ttgx_s cn63xx;
+        struct cvmx_l2c_err_ttgx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_vbfx {
+        uint64_t u64;
+        struct cvmx_l2c_err_vbfx_s {
+                uint64_t reserved_62_63:2;
+                uint64_t vdbe:1;
+                uint64_t vsbe:1;
+                uint64_t vsyn:10;
+                uint64_t reserved_2_49:48;
+                uint64_t type:2;
+        } s;
+        struct cvmx_l2c_err_vbfx_s cn63xx;
+        struct cvmx_l2c_err_vbfx_s cn63xxp1;
+};
+
+union cvmx_l2c_err_xmc {
+        uint64_t u64;
+        struct cvmx_l2c_err_xmc_s {
+                uint64_t cmd:6;
+                uint64_t reserved_52_57:6;
+                uint64_t sid:4;
+                uint64_t reserved_38_47:10;
+                uint64_t addr:38;
+        } s;
+        struct cvmx_l2c_err_xmc_s cn63xx;
+        struct cvmx_l2c_err_xmc_s cn63xxp1;
+};
+
 union cvmx_l2c_grpwrr0 {
         uint64_t u64;
         struct cvmx_l2c_grpwrr0_s {
@@ -464,6 +667,60 @@ union cvmx_l2c_int_en {
         struct cvmx_l2c_int_en_s cn56xxp1;
 };
 
+union cvmx_l2c_int_ena {
+        uint64_t u64;
+        struct cvmx_l2c_int_ena_s {
+                uint64_t reserved_8_63:56;
+                uint64_t bigrd:1;
+                uint64_t bigwr:1;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } s;
+        struct cvmx_l2c_int_ena_s cn63xx;
+        struct cvmx_l2c_int_ena_cn63xxp1 {
+                uint64_t reserved_6_63:58;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } cn63xxp1;
+};
+
+union cvmx_l2c_int_reg {
+        uint64_t u64;
+        struct cvmx_l2c_int_reg_s {
+                uint64_t reserved_17_63:47;
+                uint64_t tad0:1;
+                uint64_t reserved_8_15:8;
+                uint64_t bigrd:1;
+                uint64_t bigwr:1;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } s;
+        struct cvmx_l2c_int_reg_s cn63xx;
+        struct cvmx_l2c_int_reg_cn63xxp1 {
+                uint64_t reserved_17_63:47;
+                uint64_t tad0:1;
+                uint64_t reserved_6_15:10;
+                uint64_t vrtpe:1;
+                uint64_t vrtadrng:1;
+                uint64_t vrtidrng:1;
+                uint64_t vrtwr:1;
+                uint64_t holewr:1;
+                uint64_t holerd:1;
+        } cn63xxp1;
+};
+
 union cvmx_l2c_int_stat {
         uint64_t u64;
         struct cvmx_l2c_int_stat_s {
@@ -484,6 +741,24 @@ union cvmx_l2c_int_stat {
         struct cvmx_l2c_int_stat_s cn56xxp1;
 };
 
+union cvmx_l2c_iocx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_iocx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_iocx_pfc_s cn63xx;
+        struct cvmx_l2c_iocx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_iorx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_iorx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_iorx_pfc_s cn63xx;
+        struct cvmx_l2c_iorx_pfc_s cn63xxp1;
+};
+
 union cvmx_l2c_lckbase {
         uint64_t u64;
         struct cvmx_l2c_lckbase_s {
@@ -855,6 +1130,59 @@ union cvmx_l2c_ppgrp {
         struct cvmx_l2c_ppgrp_s cn56xxp1;
 };
 
+union cvmx_l2c_qos_iobx {
+        uint64_t u64;
+        struct cvmx_l2c_qos_iobx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t dwblvl:2;
+                uint64_t reserved_2_3:2;
+                uint64_t lvl:2;
+        } s;
+        struct cvmx_l2c_qos_iobx_s cn63xx;
+        struct cvmx_l2c_qos_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_ppx {
+        uint64_t u64;
+        struct cvmx_l2c_qos_ppx_s {
+                uint64_t reserved_2_63:62;
+                uint64_t lvl:2;
+        } s;
+        struct cvmx_l2c_qos_ppx_s cn63xx;
+        struct cvmx_l2c_qos_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_qos_wgt {
+        uint64_t u64;
+        struct cvmx_l2c_qos_wgt_s {
+                uint64_t reserved_32_63:32;
+                uint64_t wgt3:8;
+                uint64_t wgt2:8;
+                uint64_t wgt1:8;
+                uint64_t wgt0:8;
+        } s;
+        struct cvmx_l2c_qos_wgt_s cn63xx;
+        struct cvmx_l2c_qos_wgt_s cn63xxp1;
+};
+
+union cvmx_l2c_rscx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_rscx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_rscx_pfc_s cn63xx;
+        struct cvmx_l2c_rscx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_rsdx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_rsdx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_rsdx_pfc_s cn63xx;
+        struct cvmx_l2c_rsdx_pfc_s cn63xxp1;
+};
+
 union cvmx_l2c_spar0 {
         uint64_t u64;
         struct cvmx_l2c_spar0_s {
@@ -960,4 +1288,282 @@ union cvmx_l2c_spar4 {
         struct cvmx_l2c_spar4_s cn58xxp1;
 };
 
+union cvmx_l2c_tadx_ecc0 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_ecc0_s {
+                uint64_t reserved_58_63:6;
+                uint64_t ow3ecc:10;
+                uint64_t reserved_42_47:6;
+                uint64_t ow2ecc:10;
+                uint64_t reserved_26_31:6;
+                uint64_t ow1ecc:10;
+                uint64_t reserved_10_15:6;
+                uint64_t ow0ecc:10;
+        } s;
+        struct cvmx_l2c_tadx_ecc0_s cn63xx;
+        struct cvmx_l2c_tadx_ecc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ecc1 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_ecc1_s {
+                uint64_t reserved_58_63:6;
+                uint64_t ow7ecc:10;
+                uint64_t reserved_42_47:6;
+                uint64_t ow6ecc:10;
+                uint64_t reserved_26_31:6;
+                uint64_t ow5ecc:10;
+                uint64_t reserved_10_15:6;
+                uint64_t ow4ecc:10;
+        } s;
+        struct cvmx_l2c_tadx_ecc1_s cn63xx;
+        struct cvmx_l2c_tadx_ecc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_ien {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_ien_s {
+                uint64_t reserved_9_63:55;
+                uint64_t wrdislmc:1;
+                uint64_t rddislmc:1;
+                uint64_t noway:1;
+                uint64_t vbfdbe:1;
+                uint64_t vbfsbe:1;
+                uint64_t tagdbe:1;
+                uint64_t tagsbe:1;
+                uint64_t l2ddbe:1;
+                uint64_t l2dsbe:1;
+        } s;
+        struct cvmx_l2c_tadx_ien_s cn63xx;
+        struct cvmx_l2c_tadx_ien_cn63xxp1 {
+                uint64_t reserved_7_63:57;
+                uint64_t noway:1;
+                uint64_t vbfdbe:1;
+                uint64_t vbfsbe:1;
+                uint64_t tagdbe:1;
+                uint64_t tagsbe:1;
+                uint64_t l2ddbe:1;
+                uint64_t l2dsbe:1;
+        } cn63xxp1;
+};
+
+union cvmx_l2c_tadx_int {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_int_s {
+                uint64_t reserved_9_63:55;
+                uint64_t wrdislmc:1;
+                uint64_t rddislmc:1;
+                uint64_t noway:1;
+                uint64_t vbfdbe:1;
+                uint64_t vbfsbe:1;
+                uint64_t tagdbe:1;
+                uint64_t tagsbe:1;
+                uint64_t l2ddbe:1;
+                uint64_t l2dsbe:1;
+        } s;
+        struct cvmx_l2c_tadx_int_s cn63xx;
+};
+
+union cvmx_l2c_tadx_pfc0 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc0_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc0_s cn63xx;
+        struct cvmx_l2c_tadx_pfc0_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc1 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc1_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc1_s cn63xx;
+        struct cvmx_l2c_tadx_pfc1_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc2 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc2_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc2_s cn63xx;
+        struct cvmx_l2c_tadx_pfc2_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_pfc3 {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_pfc3_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_tadx_pfc3_s cn63xx;
+        struct cvmx_l2c_tadx_pfc3_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_prf {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_prf_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt3sel:8;
+                uint64_t cnt2sel:8;
+                uint64_t cnt1sel:8;
+                uint64_t cnt0sel:8;
+        } s;
+        struct cvmx_l2c_tadx_prf_s cn63xx;
+        struct cvmx_l2c_tadx_prf_s cn63xxp1;
+};
+
+union cvmx_l2c_tadx_tag {
+        uint64_t u64;
+        struct cvmx_l2c_tadx_tag_s {
+                uint64_t reserved_46_63:18;
+                uint64_t ecc:6;
+                uint64_t reserved_36_39:4;
+                uint64_t tag:19;
+                uint64_t reserved_4_16:13;
+                uint64_t use:1;
+                uint64_t valid:1;
+                uint64_t dirty:1;
+                uint64_t lock:1;
+        } s;
+        struct cvmx_l2c_tadx_tag_s cn63xx;
+        struct cvmx_l2c_tadx_tag_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_id {
+        uint64_t u64;
+        struct cvmx_l2c_ver_id_s {
+                uint64_t mask:64;
+        } s;
+        struct cvmx_l2c_ver_id_s cn63xx;
+        struct cvmx_l2c_ver_id_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_iob {
+        uint64_t u64;
+        struct cvmx_l2c_ver_iob_s {
+                uint64_t reserved_1_63:63;
+                uint64_t mask:1;
+        } s;
+        struct cvmx_l2c_ver_iob_s cn63xx;
+        struct cvmx_l2c_ver_iob_s cn63xxp1;
+};
+
+union cvmx_l2c_ver_msc {
+        uint64_t u64;
+        struct cvmx_l2c_ver_msc_s {
+                uint64_t reserved_2_63:62;
+                uint64_t invl2:1;
+                uint64_t dwb:1;
+        } s;
+        struct cvmx_l2c_ver_msc_s cn63xx;
+};
+
+union cvmx_l2c_ver_pp {
+        uint64_t u64;
+        struct cvmx_l2c_ver_pp_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mask:6;
+        } s;
+        struct cvmx_l2c_ver_pp_s cn63xx;
+        struct cvmx_l2c_ver_pp_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_iobx {
+        uint64_t u64;
+        struct cvmx_l2c_virtid_iobx_s {
+                uint64_t reserved_14_63:50;
+                uint64_t dwbid:6;
+                uint64_t reserved_6_7:2;
+                uint64_t id:6;
+        } s;
+        struct cvmx_l2c_virtid_iobx_s cn63xx;
+        struct cvmx_l2c_virtid_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_virtid_ppx {
+        uint64_t u64;
+        struct cvmx_l2c_virtid_ppx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t id:6;
+        } s;
+        struct cvmx_l2c_virtid_ppx_s cn63xx;
+        struct cvmx_l2c_virtid_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_ctl {
+        uint64_t u64;
+        struct cvmx_l2c_vrt_ctl_s {
+                uint64_t reserved_9_63:55;
+                uint64_t ooberr:1;
+                uint64_t reserved_7_7:1;
+                uint64_t memsz:3;
+                uint64_t numid:3;
+                uint64_t enable:1;
+        } s;
+        struct cvmx_l2c_vrt_ctl_s cn63xx;
+        struct cvmx_l2c_vrt_ctl_s cn63xxp1;
+};
+
+union cvmx_l2c_vrt_memx {
+        uint64_t u64;
+        struct cvmx_l2c_vrt_memx_s {
+                uint64_t reserved_36_63:28;
+                uint64_t parity:4;
+                uint64_t data:32;
+        } s;
+        struct cvmx_l2c_vrt_memx_s cn63xx;
+        struct cvmx_l2c_vrt_memx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_iobx {
+        uint64_t u64;
+        struct cvmx_l2c_wpar_iobx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t mask:16;
+        } s;
+        struct cvmx_l2c_wpar_iobx_s cn63xx;
+        struct cvmx_l2c_wpar_iobx_s cn63xxp1;
+};
+
+union cvmx_l2c_wpar_ppx {
+        uint64_t u64;
+        struct cvmx_l2c_wpar_ppx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t mask:16;
+        } s;
+        struct cvmx_l2c_wpar_ppx_s cn63xx;
+        struct cvmx_l2c_wpar_ppx_s cn63xxp1;
+};
+
+union cvmx_l2c_xmcx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_xmcx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_xmcx_pfc_s cn63xx;
+        struct cvmx_l2c_xmcx_pfc_s cn63xxp1;
+};
+
+union cvmx_l2c_xmc_cmd {
+        uint64_t u64;
+        struct cvmx_l2c_xmc_cmd_s {
+                uint64_t inuse:1;
+                uint64_t cmd:6;
+                uint64_t reserved_38_56:19;
+                uint64_t addr:38;
+        } s;
+        struct cvmx_l2c_xmc_cmd_s cn63xx;
+        struct cvmx_l2c_xmc_cmd_s cn63xxp1;
+};
+
+union cvmx_l2c_xmdx_pfc {
+        uint64_t u64;
+        struct cvmx_l2c_xmdx_pfc_s {
+                uint64_t count:64;
+        } s;
+        struct cvmx_l2c_xmdx_pfc_s cn63xx;
+        struct cvmx_l2c_xmdx_pfc_s cn63xxp1;
+};
+
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 2a8c0902ea50..0b32c5b118e2 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -26,7 +26,6 @@
  ***********************license end**************************************/
 
 /*
- *
  * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
  * facilities.
  */
@@ -34,93 +33,126 @@
 #ifndef __CVMX_L2C_H__
 #define __CVMX_L2C_H__
 
-/* Deprecated macro, use function */
-#define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()
-
-/* Deprecated macro, use function */
-#define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()
+#define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()   /* Deprecated macro, use function */
+#define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()    /* Deprecated macro, use function */
+#define CVMX_L2_SETS      cvmx_l2c_get_num_sets()    /* Deprecated macro, use function */
 
-/* Deprecated macro, use function */
-#define CVMX_L2_SETS      cvmx_l2c_get_num_sets()
 
 #define CVMX_L2C_IDX_ADDR_SHIFT 7  /* based on 128 byte cache line size */
 #define CVMX_L2C_IDX_MASK       (cvmx_l2c_get_num_sets() - 1)
 
 /* Defines for index aliasing computations */
-#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
-        (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
+#define CVMX_L2C_ALIAS_MASK (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+#define CVMX_L2C_MEMBANK_SELECT_SIZE  4096
 
-#define CVMX_L2C_ALIAS_MASK \
-        (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
+/* Defines for Virtualizations, valid only from Octeon II onwards. */
+#define CVMX_L2C_VRT_MAX_VIRTID_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 64 : 0)
+#define CVMX_L2C_VRT_MAX_MEMSZ_ALLOWED ((OCTEON_IS_MODEL(OCTEON_CN63XX)) ? 32 : 0)
 
 union cvmx_l2c_tag {
         uint64_t u64;
         struct {
                 uint64_t reserved:28;
-                uint64_t V:1;   /* Line valid */
-                uint64_t D:1;   /* Line dirty */
-                uint64_t L:1;   /* Line locked */
-                uint64_t U:1;   /* Use, LRU eviction */
+                uint64_t V:1;           /* Line valid */
+                uint64_t D:1;           /* Line dirty */
+                uint64_t L:1;           /* Line locked */
+                uint64_t U:1;           /* Use, LRU eviction */
                 uint64_t addr:32;       /* Phys mem (not all bits valid) */
         } s;
 };
 
+/* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
+#define CVMX_L2C_TADS  1
+
   /* L2C Performance Counter events. */
 enum cvmx_l2c_event {
-        CVMX_L2C_EVENT_CYCLES = 0,
-        CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
-        CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
-        CVMX_L2C_EVENT_DATA_MISS = 3,
-        CVMX_L2C_EVENT_DATA_HIT = 4,
-        CVMX_L2C_EVENT_MISS = 5,
-        CVMX_L2C_EVENT_HIT = 6,
-        CVMX_L2C_EVENT_VICTIM_HIT = 7,
-        CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
-        CVMX_L2C_EVENT_TAG_PROBE = 9,
-        CVMX_L2C_EVENT_TAG_UPDATE = 10,
-        CVMX_L2C_EVENT_TAG_COMPLETE = 11,
-        CVMX_L2C_EVENT_TAG_DIRTY = 12,
-        CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
-        CVMX_L2C_EVENT_DATA_STORE_READ = 14,
+        CVMX_L2C_EVENT_CYCLES           =  0,
+        CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,
+        CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
+        CVMX_L2C_EVENT_DATA_MISS        =  3,
+        CVMX_L2C_EVENT_DATA_HIT         =  4,
+        CVMX_L2C_EVENT_MISS             =  5,
+        CVMX_L2C_EVENT_HIT              =  6,
+        CVMX_L2C_EVENT_VICTIM_HIT       =  7,
+        CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
+        CVMX_L2C_EVENT_TAG_PROBE        =  9,
+        CVMX_L2C_EVENT_TAG_UPDATE       = 10,
+        CVMX_L2C_EVENT_TAG_COMPLETE     = 11,
+        CVMX_L2C_EVENT_TAG_DIRTY        = 12,
+        CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
+        CVMX_L2C_EVENT_DATA_STORE_READ  = 14,
         CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
-        CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
-        CVMX_L2C_EVENT_WRITE_REQUEST = 17,
-        CVMX_L2C_EVENT_READ_REQUEST = 18,
+        CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
+        CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
+        CVMX_L2C_EVENT_READ_REQUEST     = 18,
         CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
-        CVMX_L2C_EVENT_XMC_NOP = 20,
-        CVMX_L2C_EVENT_XMC_LDT = 21,
-        CVMX_L2C_EVENT_XMC_LDI = 22,
-        CVMX_L2C_EVENT_XMC_LDD = 23,
-        CVMX_L2C_EVENT_XMC_STF = 24,
-        CVMX_L2C_EVENT_XMC_STT = 25,
-        CVMX_L2C_EVENT_XMC_STP = 26,
-        CVMX_L2C_EVENT_XMC_STC = 27,
-        CVMX_L2C_EVENT_XMC_DWB = 28,
-        CVMX_L2C_EVENT_XMC_PL2 = 29,
-        CVMX_L2C_EVENT_XMC_PSL1 = 30,
-        CVMX_L2C_EVENT_XMC_IOBLD = 31,
-        CVMX_L2C_EVENT_XMC_IOBST = 32,
-        CVMX_L2C_EVENT_XMC_IOBDMA = 33,
-        CVMX_L2C_EVENT_XMC_IOBRSP = 34,
-        CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
-        CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
-        CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
-        CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
-        CVMX_L2C_EVENT_RSC_NOP = 39,
-        CVMX_L2C_EVENT_RSC_STDN = 40,
-        CVMX_L2C_EVENT_RSC_FILL = 41,
-        CVMX_L2C_EVENT_RSC_REFL = 42,
-        CVMX_L2C_EVENT_RSC_STIN = 43,
-        CVMX_L2C_EVENT_RSC_SCIN = 44,
-        CVMX_L2C_EVENT_RSC_SCFL = 45,
-        CVMX_L2C_EVENT_RSC_SCDN = 46,
-        CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
-        CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
-        CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
-        CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
-        CVMX_L2C_EVENT_LRF_REQ = 51,
-        CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
-        CVMX_L2C_EVENT_DT_WR_INVAL = 53
+        CVMX_L2C_EVENT_XMC_NOP          = 20,
+        CVMX_L2C_EVENT_XMC_LDT          = 21,
+        CVMX_L2C_EVENT_XMC_LDI          = 22,
+        CVMX_L2C_EVENT_XMC_LDD          = 23,
+        CVMX_L2C_EVENT_XMC_STF          = 24,
+        CVMX_L2C_EVENT_XMC_STT          = 25,
+        CVMX_L2C_EVENT_XMC_STP          = 26,
+        CVMX_L2C_EVENT_XMC_STC          = 27,
+        CVMX_L2C_EVENT_XMC_DWB          = 28,
+        CVMX_L2C_EVENT_XMC_PL2          = 29,
+        CVMX_L2C_EVENT_XMC_PSL1         = 30,
+        CVMX_L2C_EVENT_XMC_IOBLD        = 31,
+        CVMX_L2C_EVENT_XMC_IOBST        = 32,
+        CVMX_L2C_EVENT_XMC_IOBDMA       = 33,
+        CVMX_L2C_EVENT_XMC_IOBRSP       = 34,
+        CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
+        CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,
+        CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
+        CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
+        CVMX_L2C_EVENT_RSC_NOP          = 39,
+        CVMX_L2C_EVENT_RSC_STDN         = 40,
+        CVMX_L2C_EVENT_RSC_FILL         = 41,
+        CVMX_L2C_EVENT_RSC_REFL         = 42,
+        CVMX_L2C_EVENT_RSC_STIN         = 43,
+        CVMX_L2C_EVENT_RSC_SCIN         = 44,
+        CVMX_L2C_EVENT_RSC_SCFL         = 45,
+        CVMX_L2C_EVENT_RSC_SCDN         = 46,
+        CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
+        CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
+        CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
+        CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
+        CVMX_L2C_EVENT_LRF_REQ          = 51,
+        CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,
+        CVMX_L2C_EVENT_DT_WR_INVAL      = 53,
+        CVMX_L2C_EVENT_MAX
+};
+
+/* L2C Performance Counter events for Octeon2. */
+enum cvmx_l2c_tad_event {
+        CVMX_L2C_TAD_EVENT_NONE          = 0,
+        CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,
+        CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,
+        CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,
+        CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,
+        CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,
+        CVMX_L2C_TAD_EVENT_SC_PASS       = 6,
+        CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,
+        CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,
+        CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,
+        CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,
+        CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,
+        CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,
+        CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,
+        CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,
+        CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,
+        CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,
+        CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,
+        CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,
+        CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,
+        CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,
+        CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,
+        CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,
+        CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,
+        CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,
+        CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,
+        CVMX_L2C_TAD_EVENT_MAX
 };
 
 /**
@@ -132,10 +164,10 @@ enum cvmx_l2c_event {
  * @clear_on_read:  When asserted, any read of the performance counter
  *                       clears the counter.
  *
- * The routine does not clear the counter.
+ * @note The routine does not clear the counter.
  */
-void cvmx_l2c_config_perf(uint32_t counter,
-                          enum cvmx_l2c_event event, uint32_t clear_on_read);
+void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event, uint32_t clear_on_read);
+
 /**
  * Read the given L2 Cache performance counter. The counter must be configured
  * before reading, but this routine does not enforce this requirement.
@@ -160,18 +192,18 @@ int cvmx_l2c_get_core_way_partition(uint32_t core);
 /**
  * Partitions the L2 cache for a core
  *
- * @core:  The core that the partitioning applies to.
+ * @core: The core that the partitioning applies to.
+ * @mask: The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
  *
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- *        bit allows the core to evict cache lines from a way, while a
- *        1 bit blocks the core from evicting any lines from that
- *        way. There must be at least one allowed way (0 bit) in the
- *        mask.
- *
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them.  All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
  */
 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
 
@@ -187,19 +219,21 @@ int cvmx_l2c_get_hw_way_partition(void);
 /**
  * Partitions the L2 cache for the hardware blocks.
  *
- * @mask: The partitioning of the ways expressed as a binary mask. A 0
- *        bit allows the core to evict cache lines from a way, while a
- *        1 bit blocks the core from evicting any lines from that
- *        way. There must be at least one allowed way (0 bit) in the
- *        mask.
+ * @mask: The partitioning of the ways expressed as a binary
+ *             mask. A 0 bit allows the core to evict cache lines from
+ *             a way, while a 1 bit blocks the core from evicting any
+ *             lines from that way. There must be at least one allowed
+ *             way (0 bit) in the mask.
  *
- * If any ways are blocked for all cores and the HW blocks, then those
- * ways will never have any cache lines evicted from them.  All cores
- * and the hardware blocks are free to read from all ways regardless
- * of the partitioning.
+
+ * @note If any ways are blocked for all cores and the HW blocks, then
+ *       those ways will never have any cache lines evicted from them.
+ *       All cores and the hardware blocks are free to read from all
+ *       ways regardless of the partitioning.
  */
 int cvmx_l2c_set_hw_way_partition(uint32_t mask);
 
+
 /**
  * Locks a line in the L2 cache at the specified physical address
  *
@@ -263,13 +297,14 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
  */
 union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
 
-/* Wrapper around deprecated old function name */
-static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
-                                              uint32_t index)
+/* Wrapper providing a deprecated old function name */
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index) __attribute__((deprecated));
+static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association, uint32_t index)
 {
         return cvmx_l2c_get_tag(association, index);
 }
 
+
 /**
  * Returns the cache index for a given physical address
  *
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
index d7102d455e1b..60543e0e77fc 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,30 +28,18 @@
 #ifndef __CVMX_L2D_DEFS_H__
 #define __CVMX_L2D_DEFS_H__
 
-#define CVMX_L2D_BST0 \
-         CVMX_ADD_IO_SEG(0x0001180080000780ull)
-#define CVMX_L2D_BST1 \
-         CVMX_ADD_IO_SEG(0x0001180080000788ull)
-#define CVMX_L2D_BST2 \
-         CVMX_ADD_IO_SEG(0x0001180080000790ull)
-#define CVMX_L2D_BST3 \
-         CVMX_ADD_IO_SEG(0x0001180080000798ull)
-#define CVMX_L2D_ERR \
-         CVMX_ADD_IO_SEG(0x0001180080000010ull)
-#define CVMX_L2D_FADR \
-         CVMX_ADD_IO_SEG(0x0001180080000018ull)
-#define CVMX_L2D_FSYN0 \
-         CVMX_ADD_IO_SEG(0x0001180080000020ull)
-#define CVMX_L2D_FSYN1 \
-         CVMX_ADD_IO_SEG(0x0001180080000028ull)
-#define CVMX_L2D_FUS0 \
-         CVMX_ADD_IO_SEG(0x00011800800007A0ull)
-#define CVMX_L2D_FUS1 \
-         CVMX_ADD_IO_SEG(0x00011800800007A8ull)
-#define CVMX_L2D_FUS2 \
-         CVMX_ADD_IO_SEG(0x00011800800007B0ull)
-#define CVMX_L2D_FUS3 \
-         CVMX_ADD_IO_SEG(0x00011800800007B8ull)
+#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
+#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
+#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
+#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
+#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
+#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
+#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
+#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
+#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
+#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
+#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
+#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
 
 union cvmx_l2d_bst0 {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
index 2639a3f5ffc2..873968f55eeb 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,8 +28,7 @@
 #ifndef __CVMX_L2T_DEFS_H__
 #define __CVMX_L2T_DEFS_H__
 
-#define CVMX_L2T_ERR \
-         CVMX_ADD_IO_SEG(0x0001180080000008ull)
+#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
 
 union cvmx_l2t_err {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
index 16f174a4dadf..e25173bb8bb7 100644
--- a/arch/mips/include/asm/octeon/cvmx-led-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,32 +28,19 @@
 #ifndef __CVMX_LED_DEFS_H__
 #define __CVMX_LED_DEFS_H__
 
-#define CVMX_LED_BLINK \
-         CVMX_ADD_IO_SEG(0x0001180000001A48ull)
-#define CVMX_LED_CLK_PHASE \
-         CVMX_ADD_IO_SEG(0x0001180000001A08ull)
-#define CVMX_LED_CYLON \
-         CVMX_ADD_IO_SEG(0x0001180000001AF8ull)
-#define CVMX_LED_DBG \
-         CVMX_ADD_IO_SEG(0x0001180000001A18ull)
-#define CVMX_LED_EN \
-         CVMX_ADD_IO_SEG(0x0001180000001A00ull)
-#define CVMX_LED_POLARITY \
-         CVMX_ADD_IO_SEG(0x0001180000001A50ull)
-#define CVMX_LED_PRT \
-         CVMX_ADD_IO_SEG(0x0001180000001A10ull)
-#define CVMX_LED_PRT_FMT \
-         CVMX_ADD_IO_SEG(0x0001180000001A30ull)
-#define CVMX_LED_PRT_STATUSX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
-#define CVMX_LED_UDD_CNTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DATX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
-#define CVMX_LED_UDD_DAT_CLRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
-#define CVMX_LED_UDD_DAT_SETX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
+#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
+#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
+#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
+#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
+#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
+#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
+#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
+#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
+#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
+#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
+#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
+#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
 
 union cvmx_led_blink {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 6555f0530988..52b14a333ad4 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,191 +28,117 @@
 #ifndef __CVMX_MIO_DEFS_H__
 #define __CVMX_MIO_DEFS_H__
 
-#define CVMX_MIO_BOOT_BIST_STAT \
-         CVMX_ADD_IO_SEG(0x00011800000000F8ull)
-#define CVMX_MIO_BOOT_COMP \
-         CVMX_ADD_IO_SEG(0x00011800000000B8ull)
-#define CVMX_MIO_BOOT_DMA_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_DMA_TIMX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8))
-#define CVMX_MIO_BOOT_ERR \
-         CVMX_ADD_IO_SEG(0x00011800000000A0ull)
-#define CVMX_MIO_BOOT_INT \
-         CVMX_ADD_IO_SEG(0x00011800000000A8ull)
-#define CVMX_MIO_BOOT_LOC_ADR \
-         CVMX_ADD_IO_SEG(0x0001180000000090ull)
-#define CVMX_MIO_BOOT_LOC_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8))
-#define CVMX_MIO_BOOT_LOC_DAT \
-         CVMX_ADD_IO_SEG(0x0001180000000098ull)
-#define CVMX_MIO_BOOT_PIN_DEFS \
-         CVMX_ADD_IO_SEG(0x00011800000000C0ull)
-#define CVMX_MIO_BOOT_REG_CFGX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_REG_TIMX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8))
-#define CVMX_MIO_BOOT_THR \
-         CVMX_ADD_IO_SEG(0x00011800000000B0ull)
-#define CVMX_MIO_FUS_BNK_DATX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8))
-#define CVMX_MIO_FUS_DAT0 \
-         CVMX_ADD_IO_SEG(0x0001180000001400ull)
-#define CVMX_MIO_FUS_DAT1 \
-         CVMX_ADD_IO_SEG(0x0001180000001408ull)
-#define CVMX_MIO_FUS_DAT2 \
-         CVMX_ADD_IO_SEG(0x0001180000001410ull)
-#define CVMX_MIO_FUS_DAT3 \
-         CVMX_ADD_IO_SEG(0x0001180000001418ull)
-#define CVMX_MIO_FUS_EMA \
-         CVMX_ADD_IO_SEG(0x0001180000001550ull)
-#define CVMX_MIO_FUS_PDF \
-         CVMX_ADD_IO_SEG(0x0001180000001420ull)
-#define CVMX_MIO_FUS_PLL \
-         CVMX_ADD_IO_SEG(0x0001180000001580ull)
-#define CVMX_MIO_FUS_PROG \
-         CVMX_ADD_IO_SEG(0x0001180000001510ull)
-#define CVMX_MIO_FUS_PROG_TIMES \
-         CVMX_ADD_IO_SEG(0x0001180000001518ull)
-#define CVMX_MIO_FUS_RCMD \
-         CVMX_ADD_IO_SEG(0x0001180000001500ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_RES \
-         CVMX_ADD_IO_SEG(0x0001180000001548ull)
-#define CVMX_MIO_FUS_SPR_REPAIR_SUM \
-         CVMX_ADD_IO_SEG(0x0001180000001540ull)
-#define CVMX_MIO_FUS_UNLOCK \
-         CVMX_ADD_IO_SEG(0x0001180000001578ull)
-#define CVMX_MIO_FUS_WADR \
-         CVMX_ADD_IO_SEG(0x0001180000001508ull)
-#define CVMX_MIO_NDF_DMA_CFG \
-         CVMX_ADD_IO_SEG(0x0001180000000168ull)
-#define CVMX_MIO_NDF_DMA_INT \
-         CVMX_ADD_IO_SEG(0x0001180000000170ull)
-#define CVMX_MIO_NDF_DMA_INT_EN \
-         CVMX_ADD_IO_SEG(0x0001180000000178ull)
-#define CVMX_MIO_PLL_CTL \
-         CVMX_ADD_IO_SEG(0x0001180000001448ull)
-#define CVMX_MIO_PLL_SETTING \
-         CVMX_ADD_IO_SEG(0x0001180000001440ull)
-#define CVMX_MIO_TWSX_INT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512))
-#define CVMX_MIO_TWSX_TWSI_SW(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512))
-#define CVMX_MIO_UART2_DLH \
-         CVMX_ADD_IO_SEG(0x0001180000000488ull)
-#define CVMX_MIO_UART2_DLL \
-         CVMX_ADD_IO_SEG(0x0001180000000480ull)
-#define CVMX_MIO_UART2_FAR \
-         CVMX_ADD_IO_SEG(0x0001180000000520ull)
-#define CVMX_MIO_UART2_FCR \
-         CVMX_ADD_IO_SEG(0x0001180000000450ull)
-#define CVMX_MIO_UART2_HTX \
-         CVMX_ADD_IO_SEG(0x0001180000000708ull)
-#define CVMX_MIO_UART2_IER \
-         CVMX_ADD_IO_SEG(0x0001180000000408ull)
-#define CVMX_MIO_UART2_IIR \
-         CVMX_ADD_IO_SEG(0x0001180000000410ull)
-#define CVMX_MIO_UART2_LCR \
-         CVMX_ADD_IO_SEG(0x0001180000000418ull)
-#define CVMX_MIO_UART2_LSR \
-         CVMX_ADD_IO_SEG(0x0001180000000428ull)
-#define CVMX_MIO_UART2_MCR \
-         CVMX_ADD_IO_SEG(0x0001180000000420ull)
-#define CVMX_MIO_UART2_MSR \
-         CVMX_ADD_IO_SEG(0x0001180000000430ull)
-#define CVMX_MIO_UART2_RBR \
-         CVMX_ADD_IO_SEG(0x0001180000000400ull)
-#define CVMX_MIO_UART2_RFL \
-         CVMX_ADD_IO_SEG(0x0001180000000608ull)
-#define CVMX_MIO_UART2_RFW \
-         CVMX_ADD_IO_SEG(0x0001180000000530ull)
-#define CVMX_MIO_UART2_SBCR \
-         CVMX_ADD_IO_SEG(0x0001180000000620ull)
-#define CVMX_MIO_UART2_SCR \
-         CVMX_ADD_IO_SEG(0x0001180000000438ull)
-#define CVMX_MIO_UART2_SFE \
-         CVMX_ADD_IO_SEG(0x0001180000000630ull)
-#define CVMX_MIO_UART2_SRR \
-         CVMX_ADD_IO_SEG(0x0001180000000610ull)
-#define CVMX_MIO_UART2_SRT \
-         CVMX_ADD_IO_SEG(0x0001180000000638ull)
-#define CVMX_MIO_UART2_SRTS \
-         CVMX_ADD_IO_SEG(0x0001180000000618ull)
-#define CVMX_MIO_UART2_STT \
-         CVMX_ADD_IO_SEG(0x0001180000000700ull)
-#define CVMX_MIO_UART2_TFL \
-         CVMX_ADD_IO_SEG(0x0001180000000600ull)
-#define CVMX_MIO_UART2_TFR \
-         CVMX_ADD_IO_SEG(0x0001180000000528ull)
-#define CVMX_MIO_UART2_THR \
-         CVMX_ADD_IO_SEG(0x0001180000000440ull)
-#define CVMX_MIO_UART2_USR \
-         CVMX_ADD_IO_SEG(0x0001180000000538ull)
-#define CVMX_MIO_UARTX_DLH(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_DLL(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FAR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_FCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_HTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IER(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_IIR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_LSR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_MSR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RBR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFL(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_RFW(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SBCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SCR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SFE(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_SRTS(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_STT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFL(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_TFR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_THR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
-#define CVMX_MIO_UARTX_USR(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
+#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
+#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
+#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
+#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
+#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
+#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
+#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
+#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
+#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
+#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
+#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
+#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
+#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
+#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
+#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
+#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
+#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
+#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
+#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
+#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
+#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
+#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
+#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
+#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
+#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
+#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
+#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
+#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
+#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
+#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
+#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
+#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
+#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
+#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
+#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
+#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
+#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
+#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
+#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
+#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
+#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
+#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
+#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
+#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
+#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
+#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
+#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
+#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
+#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
+#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
+#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
+#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
+#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
+#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
+#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
+#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
+#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
+#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
+#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
+#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
+#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
+#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
+#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
+#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
+#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
+#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
+#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
+#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
+#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
+#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
+#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
+#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
+#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
 
 union cvmx_mio_boot_bist_stat {
         uint64_t u64;
         struct cvmx_mio_boot_bist_stat_s {
-                uint64_t reserved_2_63:62;
-                uint64_t loc:1;
-                uint64_t ncbi:1;
+                uint64_t reserved_0_63:64;
         } s;
         struct cvmx_mio_boot_bist_stat_cn30xx {
                 uint64_t reserved_4_63:60;
@@ -257,20 +183,33 @@ union cvmx_mio_boot_bist_stat {
         struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
         struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
+        struct cvmx_mio_boot_bist_stat_cn63xx {
+                uint64_t reserved_9_63:55;
+                uint64_t stat:9;
+        } cn63xx;
+        struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_boot_comp {
         uint64_t u64;
         struct cvmx_mio_boot_comp_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_mio_boot_comp_cn50xx {
                 uint64_t reserved_10_63:54;
                 uint64_t pctl:5;
                 uint64_t nctl:5;
-        } s;
-        struct cvmx_mio_boot_comp_s cn50xx;
-        struct cvmx_mio_boot_comp_s cn52xx;
-        struct cvmx_mio_boot_comp_s cn52xxp1;
-        struct cvmx_mio_boot_comp_s cn56xx;
-        struct cvmx_mio_boot_comp_s cn56xxp1;
+        } cn50xx;
+        struct cvmx_mio_boot_comp_cn50xx cn52xx;
+        struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
+        struct cvmx_mio_boot_comp_cn50xx cn56xx;
+        struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
+        struct cvmx_mio_boot_comp_cn63xx {
+                uint64_t reserved_12_63:52;
+                uint64_t pctl:6;
+                uint64_t nctl:6;
+        } cn63xx;
+        struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_cfgx {
@@ -291,6 +230,8 @@ union cvmx_mio_boot_dma_cfgx {
         struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
         struct cvmx_mio_boot_dma_cfgx_s cn56xx;
         struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_cfgx_s cn63xx;
+        struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_intx {
@@ -304,6 +245,8 @@ union cvmx_mio_boot_dma_intx {
         struct cvmx_mio_boot_dma_intx_s cn52xxp1;
         struct cvmx_mio_boot_dma_intx_s cn56xx;
         struct cvmx_mio_boot_dma_intx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_intx_s cn63xx;
+        struct cvmx_mio_boot_dma_intx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_int_enx {
@@ -317,6 +260,8 @@ union cvmx_mio_boot_dma_int_enx {
         struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
         struct cvmx_mio_boot_dma_int_enx_s cn56xx;
         struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_int_enx_s cn63xx;
+        struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_dma_timx {
@@ -342,6 +287,8 @@ union cvmx_mio_boot_dma_timx {
         struct cvmx_mio_boot_dma_timx_s cn52xxp1;
         struct cvmx_mio_boot_dma_timx_s cn56xx;
         struct cvmx_mio_boot_dma_timx_s cn56xxp1;
+        struct cvmx_mio_boot_dma_timx_s cn63xx;
+        struct cvmx_mio_boot_dma_timx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_err {
@@ -362,6 +309,8 @@ union cvmx_mio_boot_err {
         struct cvmx_mio_boot_err_s cn56xxp1;
         struct cvmx_mio_boot_err_s cn58xx;
         struct cvmx_mio_boot_err_s cn58xxp1;
+        struct cvmx_mio_boot_err_s cn63xx;
+        struct cvmx_mio_boot_err_s cn63xxp1;
 };
 
 union cvmx_mio_boot_int {
@@ -382,6 +331,8 @@ union cvmx_mio_boot_int {
         struct cvmx_mio_boot_int_s cn56xxp1;
         struct cvmx_mio_boot_int_s cn58xx;
         struct cvmx_mio_boot_int_s cn58xxp1;
+        struct cvmx_mio_boot_int_s cn63xx;
+        struct cvmx_mio_boot_int_s cn63xxp1;
 };
 
 union cvmx_mio_boot_loc_adr {
@@ -402,6 +353,8 @@ union cvmx_mio_boot_loc_adr {
         struct cvmx_mio_boot_loc_adr_s cn56xxp1;
         struct cvmx_mio_boot_loc_adr_s cn58xx;
         struct cvmx_mio_boot_loc_adr_s cn58xxp1;
+        struct cvmx_mio_boot_loc_adr_s cn63xx;
+        struct cvmx_mio_boot_loc_adr_s cn63xxp1;
 };
 
 union cvmx_mio_boot_loc_cfgx {
@@ -424,6 +377,8 @@ union cvmx_mio_boot_loc_cfgx {
         struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_loc_cfgx_s cn58xx;
         struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
+        struct cvmx_mio_boot_loc_cfgx_s cn63xx;
+        struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_loc_dat {
@@ -442,6 +397,8 @@ union cvmx_mio_boot_loc_dat {
         struct cvmx_mio_boot_loc_dat_s cn56xxp1;
         struct cvmx_mio_boot_loc_dat_s cn58xx;
         struct cvmx_mio_boot_loc_dat_s cn58xxp1;
+        struct cvmx_mio_boot_loc_dat_s cn63xx;
+        struct cvmx_mio_boot_loc_dat_s cn63xxp1;
 };
 
 union cvmx_mio_boot_pin_defs {
@@ -478,6 +435,8 @@ union cvmx_mio_boot_pin_defs {
                 uint64_t term:2;
                 uint64_t reserved_0_8:9;
         } cn56xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
+        struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
 };
 
 union cvmx_mio_boot_reg_cfgx {
@@ -539,6 +498,8 @@ union cvmx_mio_boot_reg_cfgx {
         struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
         struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_reg_cfgx_s cn63xx;
+        struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_reg_timx {
@@ -583,6 +544,8 @@ union cvmx_mio_boot_reg_timx {
         struct cvmx_mio_boot_reg_timx_s cn56xxp1;
         struct cvmx_mio_boot_reg_timx_s cn58xx;
         struct cvmx_mio_boot_reg_timx_s cn58xxp1;
+        struct cvmx_mio_boot_reg_timx_s cn63xx;
+        struct cvmx_mio_boot_reg_timx_s cn63xxp1;
 };
 
 union cvmx_mio_boot_thr {
@@ -611,6 +574,8 @@ union cvmx_mio_boot_thr {
         struct cvmx_mio_boot_thr_s cn56xxp1;
         struct cvmx_mio_boot_thr_cn30xx cn58xx;
         struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
+        struct cvmx_mio_boot_thr_s cn63xx;
+        struct cvmx_mio_boot_thr_s cn63xxp1;
 };
 
 union cvmx_mio_fus_bnk_datx {
@@ -625,6 +590,8 @@ union cvmx_mio_fus_bnk_datx {
         struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
         struct cvmx_mio_fus_bnk_datx_s cn58xx;
         struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
+        struct cvmx_mio_fus_bnk_datx_s cn63xx;
+        struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
 };
 
 union cvmx_mio_fus_dat0 {
@@ -644,6 +611,8 @@ union cvmx_mio_fus_dat0 {
         struct cvmx_mio_fus_dat0_s cn56xxp1;
         struct cvmx_mio_fus_dat0_s cn58xx;
         struct cvmx_mio_fus_dat0_s cn58xxp1;
+        struct cvmx_mio_fus_dat0_s cn63xx;
+        struct cvmx_mio_fus_dat0_s cn63xxp1;
 };
 
 union cvmx_mio_fus_dat1 {
@@ -663,12 +632,15 @@ union cvmx_mio_fus_dat1 {
         struct cvmx_mio_fus_dat1_s cn56xxp1;
         struct cvmx_mio_fus_dat1_s cn58xx;
         struct cvmx_mio_fus_dat1_s cn58xxp1;
+        struct cvmx_mio_fus_dat1_s cn63xx;
+        struct cvmx_mio_fus_dat1_s cn63xxp1;
 };
 
 union cvmx_mio_fus_dat2 {
         uint64_t u64;
         struct cvmx_mio_fus_dat2_s {
-                uint64_t reserved_34_63:30;
+                uint64_t reserved_35_63:29;
+                uint64_t dorm_crypto:1;
                 uint64_t fus318:1;
                 uint64_t raid_en:1;
                 uint64_t reserved_30_31:2;
@@ -775,14 +747,38 @@ union cvmx_mio_fus_dat2 {
                 uint64_t pp_dis:16;
         } cn58xx;
         struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_dat2_cn63xx {
+                uint64_t reserved_35_63:29;
+                uint64_t dorm_crypto:1;
+                uint64_t fus318:1;
+                uint64_t raid_en:1;
+                uint64_t reserved_29_31:3;
+                uint64_t nodfa_cp2:1;
+                uint64_t nomul:1;
+                uint64_t nocrypto:1;
+                uint64_t reserved_24_25:2;
+                uint64_t chip_id:8;
+                uint64_t reserved_6_15:10;
+                uint64_t pp_dis:6;
+        } cn63xx;
+        struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_dat3 {
         uint64_t u64;
         struct cvmx_mio_fus_dat3_s {
-                uint64_t reserved_32_63:32;
+                uint64_t reserved_58_63:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t reserved_40_40:1;
+                uint64_t ema:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
                 uint64_t pll_div4:1;
-                uint64_t zip_crip:2;
+                uint64_t reserved_29_30:2;
                 uint64_t bar2_en:1;
                 uint64_t efus_lck:1;
                 uint64_t efus_ign:1;
@@ -801,7 +797,17 @@ union cvmx_mio_fus_dat3 {
                 uint64_t nodfa_dte:1;
                 uint64_t icache:24;
         } cn30xx;
-        struct cvmx_mio_fus_dat3_s cn31xx;
+        struct cvmx_mio_fus_dat3_cn31xx {
+                uint64_t reserved_32_63:32;
+                uint64_t pll_div4:1;
+                uint64_t zip_crip:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t icache:24;
+        } cn31xx;
         struct cvmx_mio_fus_dat3_cn38xx {
                 uint64_t reserved_31_63:33;
                 uint64_t zip_crip:2;
@@ -828,6 +834,27 @@ union cvmx_mio_fus_dat3 {
         struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
         struct cvmx_mio_fus_dat3_cn38xx cn58xx;
         struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
+        struct cvmx_mio_fus_dat3_cn63xx {
+                uint64_t reserved_58_63:6;
+                uint64_t pll_ctl:10;
+                uint64_t dfa_info_dte:3;
+                uint64_t dfa_info_clm:4;
+                uint64_t reserved_40_40:1;
+                uint64_t ema:2;
+                uint64_t efus_lck_rsv:1;
+                uint64_t efus_lck_man:1;
+                uint64_t pll_half_dis:1;
+                uint64_t l2c_crip:3;
+                uint64_t reserved_31_31:1;
+                uint64_t zip_info:2;
+                uint64_t bar2_en:1;
+                uint64_t efus_lck:1;
+                uint64_t efus_ign:1;
+                uint64_t nozip:1;
+                uint64_t nodfa_dte:1;
+                uint64_t reserved_0_23:24;
+        } cn63xx;
+        struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_ema {
@@ -848,6 +875,8 @@ union cvmx_mio_fus_ema {
                 uint64_t ema:2;
         } cn58xx;
         struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
+        struct cvmx_mio_fus_ema_s cn63xx;
+        struct cvmx_mio_fus_ema_s cn63xxp1;
 };
 
 union cvmx_mio_fus_pdf {
@@ -861,60 +890,96 @@ union cvmx_mio_fus_pdf {
         struct cvmx_mio_fus_pdf_s cn56xx;
         struct cvmx_mio_fus_pdf_s cn56xxp1;
         struct cvmx_mio_fus_pdf_s cn58xx;
+        struct cvmx_mio_fus_pdf_s cn63xx;
+        struct cvmx_mio_fus_pdf_s cn63xxp1;
 };
 
 union cvmx_mio_fus_pll {
         uint64_t u64;
         struct cvmx_mio_fus_pll_s {
-                uint64_t reserved_2_63:62;
+                uint64_t reserved_8_63:56;
+                uint64_t c_cout_rst:1;
+                uint64_t c_cout_sel:2;
+                uint64_t pnr_cout_rst:1;
+                uint64_t pnr_cout_sel:2;
                 uint64_t rfslip:1;
                 uint64_t fbslip:1;
         } s;
-        struct cvmx_mio_fus_pll_s cn50xx;
-        struct cvmx_mio_fus_pll_s cn52xx;
-        struct cvmx_mio_fus_pll_s cn52xxp1;
-        struct cvmx_mio_fus_pll_s cn56xx;
-        struct cvmx_mio_fus_pll_s cn56xxp1;
-        struct cvmx_mio_fus_pll_s cn58xx;
-        struct cvmx_mio_fus_pll_s cn58xxp1;
+        struct cvmx_mio_fus_pll_cn50xx {
+                uint64_t reserved_2_63:62;
+                uint64_t rfslip:1;
+                uint64_t fbslip:1;
+        } cn50xx;
+        struct cvmx_mio_fus_pll_cn50xx cn52xx;
+        struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
+        struct cvmx_mio_fus_pll_cn50xx cn56xx;
+        struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
+        struct cvmx_mio_fus_pll_cn50xx cn58xx;
+        struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
+        struct cvmx_mio_fus_pll_s cn63xx;
+        struct cvmx_mio_fus_pll_s cn63xxp1;
 };
 
 union cvmx_mio_fus_prog {
         uint64_t u64;
         struct cvmx_mio_fus_prog_s {
-                uint64_t reserved_1_63:63;
+                uint64_t reserved_2_63:62;
+                uint64_t soft:1;
                 uint64_t prog:1;
         } s;
-        struct cvmx_mio_fus_prog_s cn30xx;
-        struct cvmx_mio_fus_prog_s cn31xx;
-        struct cvmx_mio_fus_prog_s cn38xx;
-        struct cvmx_mio_fus_prog_s cn38xxp2;
-        struct cvmx_mio_fus_prog_s cn50xx;
-        struct cvmx_mio_fus_prog_s cn52xx;
-        struct cvmx_mio_fus_prog_s cn52xxp1;
-        struct cvmx_mio_fus_prog_s cn56xx;
-        struct cvmx_mio_fus_prog_s cn56xxp1;
-        struct cvmx_mio_fus_prog_s cn58xx;
-        struct cvmx_mio_fus_prog_s cn58xxp1;
+        struct cvmx_mio_fus_prog_cn30xx {
+                uint64_t reserved_1_63:63;
+                uint64_t prog:1;
+        } cn30xx;
+        struct cvmx_mio_fus_prog_cn30xx cn31xx;
+        struct cvmx_mio_fus_prog_cn30xx cn38xx;
+        struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
+        struct cvmx_mio_fus_prog_cn30xx cn50xx;
+        struct cvmx_mio_fus_prog_cn30xx cn52xx;
+        struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
+        struct cvmx_mio_fus_prog_cn30xx cn56xx;
+        struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
+        struct cvmx_mio_fus_prog_cn30xx cn58xx;
+        struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_prog_s cn63xx;
+        struct cvmx_mio_fus_prog_s cn63xxp1;
 };
 
 union cvmx_mio_fus_prog_times {
         uint64_t u64;
         struct cvmx_mio_fus_prog_times_s {
+                uint64_t reserved_35_63:29;
+                uint64_t vgate_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t prog_pin:1;
+                uint64_t reserved_6_31:26;
+                uint64_t setup:6;
+        } s;
+        struct cvmx_mio_fus_prog_times_cn50xx {
                 uint64_t reserved_33_63:31;
                 uint64_t prog_pin:1;
                 uint64_t out:8;
                 uint64_t sclk_lo:4;
                 uint64_t sclk_hi:12;
                 uint64_t setup:8;
-        } s;
-        struct cvmx_mio_fus_prog_times_s cn50xx;
-        struct cvmx_mio_fus_prog_times_s cn52xx;
-        struct cvmx_mio_fus_prog_times_s cn52xxp1;
-        struct cvmx_mio_fus_prog_times_s cn56xx;
-        struct cvmx_mio_fus_prog_times_s cn56xxp1;
-        struct cvmx_mio_fus_prog_times_s cn58xx;
-        struct cvmx_mio_fus_prog_times_s cn58xxp1;
+        } cn50xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
+        struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
+        struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
+        struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
+        struct cvmx_mio_fus_prog_times_cn63xx {
+                uint64_t reserved_35_63:29;
+                uint64_t vgate_pin:1;
+                uint64_t fsrc_pin:1;
+                uint64_t prog_pin:1;
+                uint64_t out:7;
+                uint64_t sclk_lo:4;
+                uint64_t sclk_hi:15;
+                uint64_t setup:6;
+        } cn63xx;
+        struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
 };
 
 union cvmx_mio_fus_rcmd {
@@ -948,6 +1013,57 @@ union cvmx_mio_fus_rcmd {
         struct cvmx_mio_fus_rcmd_s cn56xxp1;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
         struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
+        struct cvmx_mio_fus_rcmd_s cn63xx;
+        struct cvmx_mio_fus_rcmd_s cn63xxp1;
+};
+
+union cvmx_mio_fus_read_times {
+        uint64_t u64;
+        struct cvmx_mio_fus_read_times_s {
+                uint64_t reserved_26_63:38;
+                uint64_t sch:4;
+                uint64_t fsh:4;
+                uint64_t prh:4;
+                uint64_t sdh:4;
+                uint64_t setup:10;
+        } s;
+        struct cvmx_mio_fus_read_times_s cn63xx;
+        struct cvmx_mio_fus_read_times_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res0 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res0_s {
+                uint64_t reserved_55_63:9;
+                uint64_t too_many:1;
+                uint64_t repair2:18;
+                uint64_t repair1:18;
+                uint64_t repair0:18;
+        } s;
+        struct cvmx_mio_fus_repair_res0_s cn63xx;
+        struct cvmx_mio_fus_repair_res0_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res1 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res1_s {
+                uint64_t reserved_54_63:10;
+                uint64_t repair5:18;
+                uint64_t repair4:18;
+                uint64_t repair3:18;
+        } s;
+        struct cvmx_mio_fus_repair_res1_s cn63xx;
+        struct cvmx_mio_fus_repair_res1_s cn63xxp1;
+};
+
+union cvmx_mio_fus_repair_res2 {
+        uint64_t u64;
+        struct cvmx_mio_fus_repair_res2_s {
+                uint64_t reserved_18_63:46;
+                uint64_t repair6:18;
+        } s;
+        struct cvmx_mio_fus_repair_res2_s cn63xx;
+        struct cvmx_mio_fus_repair_res2_s cn63xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_res {
@@ -968,6 +1084,8 @@ union cvmx_mio_fus_spr_repair_res {
         struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_res_s cn58xx;
         struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_res_s cn63xx;
+        struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
 };
 
 union cvmx_mio_fus_spr_repair_sum {
@@ -986,6 +1104,8 @@ union cvmx_mio_fus_spr_repair_sum {
         struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
         struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
+        struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
+        struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
 };
 
 union cvmx_mio_fus_unlock {
@@ -1021,6 +1141,22 @@ union cvmx_mio_fus_wadr {
         struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
         struct cvmx_mio_fus_wadr_cn50xx cn58xx;
         struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
+        struct cvmx_mio_fus_wadr_cn63xx {
+                uint64_t reserved_4_63:60;
+                uint64_t addr:4;
+        } cn63xx;
+        struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
+};
+
+union cvmx_mio_gpio_comp {
+        uint64_t u64;
+        struct cvmx_mio_gpio_comp_s {
+                uint64_t reserved_12_63:52;
+                uint64_t pctl:6;
+                uint64_t nctl:6;
+        } s;
+        struct cvmx_mio_gpio_comp_s cn63xx;
+        struct cvmx_mio_gpio_comp_s cn63xxp1;
 };
 
 union cvmx_mio_ndf_dma_cfg {
@@ -1038,6 +1174,8 @@ union cvmx_mio_ndf_dma_cfg {
                 uint64_t adr:36;
         } s;
         struct cvmx_mio_ndf_dma_cfg_s cn52xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn63xx;
+        struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
 };
 
 union cvmx_mio_ndf_dma_int {
@@ -1047,6 +1185,8 @@ union cvmx_mio_ndf_dma_int {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_s cn63xx;
+        struct cvmx_mio_ndf_dma_int_s cn63xxp1;
 };
 
 union cvmx_mio_ndf_dma_int_en {
@@ -1056,6 +1196,8 @@ union cvmx_mio_ndf_dma_int_en {
                 uint64_t done:1;
         } s;
         struct cvmx_mio_ndf_dma_int_en_s cn52xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn63xx;
+        struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
 };
 
 union cvmx_mio_pll_ctl {
@@ -1078,6 +1220,173 @@ union cvmx_mio_pll_setting {
         struct cvmx_mio_pll_setting_s cn31xx;
 };
 
+union cvmx_mio_ptp_clock_cfg {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_cfg_s {
+                uint64_t reserved_24_63:40;
+                uint64_t evcnt_in:6;
+                uint64_t evcnt_edge:1;
+                uint64_t evcnt_en:1;
+                uint64_t tstmp_in:6;
+                uint64_t tstmp_edge:1;
+                uint64_t tstmp_en:1;
+                uint64_t ext_clk_in:6;
+                uint64_t ext_clk_en:1;
+                uint64_t ptp_en:1;
+        } s;
+        struct cvmx_mio_ptp_clock_cfg_s cn63xx;
+        struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_comp {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_comp_s {
+                uint64_t nanosec:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_clock_comp_s cn63xx;
+        struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_hi {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_hi_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_clock_hi_s cn63xx;
+        struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_clock_lo {
+        uint64_t u64;
+        struct cvmx_mio_ptp_clock_lo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t frnanosec:32;
+        } s;
+        struct cvmx_mio_ptp_clock_lo_s cn63xx;
+        struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_evt_cnt {
+        uint64_t u64;
+        struct cvmx_mio_ptp_evt_cnt_s {
+                uint64_t cntr:64;
+        } s;
+        struct cvmx_mio_ptp_evt_cnt_s cn63xx;
+        struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
+};
+
+union cvmx_mio_ptp_timestamp {
+        uint64_t u64;
+        struct cvmx_mio_ptp_timestamp_s {
+                uint64_t nanosec:64;
+        } s;
+        struct cvmx_mio_ptp_timestamp_s cn63xx;
+        struct cvmx_mio_ptp_timestamp_s cn63xxp1;
+};
+
+union cvmx_mio_rst_boot {
+        uint64_t u64;
+        struct cvmx_mio_rst_boot_s {
+                uint64_t reserved_36_63:28;
+                uint64_t c_mul:6;
+                uint64_t pnr_mul:6;
+                uint64_t qlm2_spd:4;
+                uint64_t qlm1_spd:4;
+                uint64_t qlm0_spd:4;
+                uint64_t lboot:10;
+                uint64_t rboot:1;
+                uint64_t rboot_pin:1;
+        } s;
+        struct cvmx_mio_rst_boot_s cn63xx;
+        struct cvmx_mio_rst_boot_s cn63xxp1;
+};
+
+union cvmx_mio_rst_cfg {
+        uint64_t u64;
+        struct cvmx_mio_rst_cfg_s {
+                uint64_t bist_delay:58;
+                uint64_t reserved_3_5:3;
+                uint64_t cntl_clr_bist:1;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } s;
+        struct cvmx_mio_rst_cfg_s cn63xx;
+        struct cvmx_mio_rst_cfg_cn63xxp1 {
+                uint64_t bist_delay:58;
+                uint64_t reserved_2_5:4;
+                uint64_t warm_clr_bist:1;
+                uint64_t soft_clr_bist:1;
+        } cn63xxp1;
+};
+
+union cvmx_mio_rst_ctlx {
+        uint64_t u64;
+        struct cvmx_mio_rst_ctlx_s {
+                uint64_t reserved_10_63:54;
+                uint64_t prst_link:1;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } s;
+        struct cvmx_mio_rst_ctlx_s cn63xx;
+        struct cvmx_mio_rst_ctlx_cn63xxp1 {
+                uint64_t reserved_9_63:55;
+                uint64_t rst_done:1;
+                uint64_t rst_link:1;
+                uint64_t host_mode:1;
+                uint64_t prtmode:2;
+                uint64_t rst_drv:1;
+                uint64_t rst_rcv:1;
+                uint64_t rst_chip:1;
+                uint64_t rst_val:1;
+        } cn63xxp1;
+};
+
+union cvmx_mio_rst_delay {
+        uint64_t u64;
+        struct cvmx_mio_rst_delay_s {
+                uint64_t reserved_32_63:32;
+                uint64_t soft_rst_dly:16;
+                uint64_t warm_rst_dly:16;
+        } s;
+        struct cvmx_mio_rst_delay_s cn63xx;
+        struct cvmx_mio_rst_delay_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int {
+        uint64_t u64;
+        struct cvmx_mio_rst_int_s {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } s;
+        struct cvmx_mio_rst_int_s cn63xx;
+        struct cvmx_mio_rst_int_s cn63xxp1;
+};
+
+union cvmx_mio_rst_int_en {
+        uint64_t u64;
+        struct cvmx_mio_rst_int_en_s {
+                uint64_t reserved_10_63:54;
+                uint64_t perst1:1;
+                uint64_t perst0:1;
+                uint64_t reserved_2_7:6;
+                uint64_t rst_link1:1;
+                uint64_t rst_link0:1;
+        } s;
+        struct cvmx_mio_rst_int_en_s cn63xx;
+        struct cvmx_mio_rst_int_en_s cn63xxp1;
+};
+
 union cvmx_mio_twsx_int {
         uint64_t u64;
         struct cvmx_mio_twsx_int_s {
@@ -1115,6 +1424,8 @@ union cvmx_mio_twsx_int {
         struct cvmx_mio_twsx_int_s cn56xxp1;
         struct cvmx_mio_twsx_int_s cn58xx;
         struct cvmx_mio_twsx_int_s cn58xxp1;
+        struct cvmx_mio_twsx_int_s cn63xx;
+        struct cvmx_mio_twsx_int_s cn63xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi {
@@ -1144,6 +1455,8 @@ union cvmx_mio_twsx_sw_twsi {
         struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_s cn63xx;
+        struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
 };
 
 union cvmx_mio_twsx_sw_twsi_ext {
@@ -1164,6 +1477,8 @@ union cvmx_mio_twsx_sw_twsi_ext {
         struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
         struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
+        struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
 };
 
 union cvmx_mio_twsx_twsi_sw {
@@ -1184,6 +1499,8 @@ union cvmx_mio_twsx_twsi_sw {
         struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
         struct cvmx_mio_twsx_twsi_sw_s cn58xx;
         struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
+        struct cvmx_mio_twsx_twsi_sw_s cn63xx;
+        struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_dlh {
@@ -1203,6 +1520,8 @@ union cvmx_mio_uartx_dlh {
         struct cvmx_mio_uartx_dlh_s cn56xxp1;
         struct cvmx_mio_uartx_dlh_s cn58xx;
         struct cvmx_mio_uartx_dlh_s cn58xxp1;
+        struct cvmx_mio_uartx_dlh_s cn63xx;
+        struct cvmx_mio_uartx_dlh_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_dll {
@@ -1222,6 +1541,8 @@ union cvmx_mio_uartx_dll {
         struct cvmx_mio_uartx_dll_s cn56xxp1;
         struct cvmx_mio_uartx_dll_s cn58xx;
         struct cvmx_mio_uartx_dll_s cn58xxp1;
+        struct cvmx_mio_uartx_dll_s cn63xx;
+        struct cvmx_mio_uartx_dll_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_far {
@@ -1241,6 +1562,8 @@ union cvmx_mio_uartx_far {
         struct cvmx_mio_uartx_far_s cn56xxp1;
         struct cvmx_mio_uartx_far_s cn58xx;
         struct cvmx_mio_uartx_far_s cn58xxp1;
+        struct cvmx_mio_uartx_far_s cn63xx;
+        struct cvmx_mio_uartx_far_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_fcr {
@@ -1265,6 +1588,8 @@ union cvmx_mio_uartx_fcr {
         struct cvmx_mio_uartx_fcr_s cn56xxp1;
         struct cvmx_mio_uartx_fcr_s cn58xx;
         struct cvmx_mio_uartx_fcr_s cn58xxp1;
+        struct cvmx_mio_uartx_fcr_s cn63xx;
+        struct cvmx_mio_uartx_fcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_htx {
@@ -1284,6 +1609,8 @@ union cvmx_mio_uartx_htx {
         struct cvmx_mio_uartx_htx_s cn56xxp1;
         struct cvmx_mio_uartx_htx_s cn58xx;
         struct cvmx_mio_uartx_htx_s cn58xxp1;
+        struct cvmx_mio_uartx_htx_s cn63xx;
+        struct cvmx_mio_uartx_htx_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_ier {
@@ -1308,6 +1635,8 @@ union cvmx_mio_uartx_ier {
         struct cvmx_mio_uartx_ier_s cn56xxp1;
         struct cvmx_mio_uartx_ier_s cn58xx;
         struct cvmx_mio_uartx_ier_s cn58xxp1;
+        struct cvmx_mio_uartx_ier_s cn63xx;
+        struct cvmx_mio_uartx_ier_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_iir {
@@ -1329,6 +1658,8 @@ union cvmx_mio_uartx_iir {
         struct cvmx_mio_uartx_iir_s cn56xxp1;
         struct cvmx_mio_uartx_iir_s cn58xx;
         struct cvmx_mio_uartx_iir_s cn58xxp1;
+        struct cvmx_mio_uartx_iir_s cn63xx;
+        struct cvmx_mio_uartx_iir_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_lcr {
@@ -1354,6 +1685,8 @@ union cvmx_mio_uartx_lcr {
         struct cvmx_mio_uartx_lcr_s cn56xxp1;
         struct cvmx_mio_uartx_lcr_s cn58xx;
         struct cvmx_mio_uartx_lcr_s cn58xxp1;
+        struct cvmx_mio_uartx_lcr_s cn63xx;
+        struct cvmx_mio_uartx_lcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_lsr {
@@ -1380,6 +1713,8 @@ union cvmx_mio_uartx_lsr {
         struct cvmx_mio_uartx_lsr_s cn56xxp1;
         struct cvmx_mio_uartx_lsr_s cn58xx;
         struct cvmx_mio_uartx_lsr_s cn58xxp1;
+        struct cvmx_mio_uartx_lsr_s cn63xx;
+        struct cvmx_mio_uartx_lsr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_mcr {
@@ -1404,6 +1739,8 @@ union cvmx_mio_uartx_mcr {
         struct cvmx_mio_uartx_mcr_s cn56xxp1;
         struct cvmx_mio_uartx_mcr_s cn58xx;
         struct cvmx_mio_uartx_mcr_s cn58xxp1;
+        struct cvmx_mio_uartx_mcr_s cn63xx;
+        struct cvmx_mio_uartx_mcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_msr {
@@ -1430,6 +1767,8 @@ union cvmx_mio_uartx_msr {
         struct cvmx_mio_uartx_msr_s cn56xxp1;
         struct cvmx_mio_uartx_msr_s cn58xx;
         struct cvmx_mio_uartx_msr_s cn58xxp1;
+        struct cvmx_mio_uartx_msr_s cn63xx;
+        struct cvmx_mio_uartx_msr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_rbr {
@@ -1449,6 +1788,8 @@ union cvmx_mio_uartx_rbr {
         struct cvmx_mio_uartx_rbr_s cn56xxp1;
         struct cvmx_mio_uartx_rbr_s cn58xx;
         struct cvmx_mio_uartx_rbr_s cn58xxp1;
+        struct cvmx_mio_uartx_rbr_s cn63xx;
+        struct cvmx_mio_uartx_rbr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_rfl {
@@ -1468,6 +1809,8 @@ union cvmx_mio_uartx_rfl {
         struct cvmx_mio_uartx_rfl_s cn56xxp1;
         struct cvmx_mio_uartx_rfl_s cn58xx;
         struct cvmx_mio_uartx_rfl_s cn58xxp1;
+        struct cvmx_mio_uartx_rfl_s cn63xx;
+        struct cvmx_mio_uartx_rfl_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_rfw {
@@ -1489,6 +1832,8 @@ union cvmx_mio_uartx_rfw {
         struct cvmx_mio_uartx_rfw_s cn56xxp1;
         struct cvmx_mio_uartx_rfw_s cn58xx;
         struct cvmx_mio_uartx_rfw_s cn58xxp1;
+        struct cvmx_mio_uartx_rfw_s cn63xx;
+        struct cvmx_mio_uartx_rfw_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_sbcr {
@@ -1508,6 +1853,8 @@ union cvmx_mio_uartx_sbcr {
         struct cvmx_mio_uartx_sbcr_s cn56xxp1;
         struct cvmx_mio_uartx_sbcr_s cn58xx;
         struct cvmx_mio_uartx_sbcr_s cn58xxp1;
+        struct cvmx_mio_uartx_sbcr_s cn63xx;
+        struct cvmx_mio_uartx_sbcr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_scr {
@@ -1527,6 +1874,8 @@ union cvmx_mio_uartx_scr {
         struct cvmx_mio_uartx_scr_s cn56xxp1;
         struct cvmx_mio_uartx_scr_s cn58xx;
         struct cvmx_mio_uartx_scr_s cn58xxp1;
+        struct cvmx_mio_uartx_scr_s cn63xx;
+        struct cvmx_mio_uartx_scr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_sfe {
@@ -1546,6 +1895,8 @@ union cvmx_mio_uartx_sfe {
         struct cvmx_mio_uartx_sfe_s cn56xxp1;
         struct cvmx_mio_uartx_sfe_s cn58xx;
         struct cvmx_mio_uartx_sfe_s cn58xxp1;
+        struct cvmx_mio_uartx_sfe_s cn63xx;
+        struct cvmx_mio_uartx_sfe_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_srr {
@@ -1567,6 +1918,8 @@ union cvmx_mio_uartx_srr {
         struct cvmx_mio_uartx_srr_s cn56xxp1;
         struct cvmx_mio_uartx_srr_s cn58xx;
         struct cvmx_mio_uartx_srr_s cn58xxp1;
+        struct cvmx_mio_uartx_srr_s cn63xx;
+        struct cvmx_mio_uartx_srr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_srt {
@@ -1586,6 +1939,8 @@ union cvmx_mio_uartx_srt {
         struct cvmx_mio_uartx_srt_s cn56xxp1;
         struct cvmx_mio_uartx_srt_s cn58xx;
         struct cvmx_mio_uartx_srt_s cn58xxp1;
+        struct cvmx_mio_uartx_srt_s cn63xx;
+        struct cvmx_mio_uartx_srt_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_srts {
@@ -1605,6 +1960,8 @@ union cvmx_mio_uartx_srts {
         struct cvmx_mio_uartx_srts_s cn56xxp1;
         struct cvmx_mio_uartx_srts_s cn58xx;
         struct cvmx_mio_uartx_srts_s cn58xxp1;
+        struct cvmx_mio_uartx_srts_s cn63xx;
+        struct cvmx_mio_uartx_srts_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_stt {
@@ -1624,6 +1981,8 @@ union cvmx_mio_uartx_stt {
         struct cvmx_mio_uartx_stt_s cn56xxp1;
         struct cvmx_mio_uartx_stt_s cn58xx;
         struct cvmx_mio_uartx_stt_s cn58xxp1;
+        struct cvmx_mio_uartx_stt_s cn63xx;
+        struct cvmx_mio_uartx_stt_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_tfl {
@@ -1643,6 +2002,8 @@ union cvmx_mio_uartx_tfl {
         struct cvmx_mio_uartx_tfl_s cn56xxp1;
         struct cvmx_mio_uartx_tfl_s cn58xx;
         struct cvmx_mio_uartx_tfl_s cn58xxp1;
+        struct cvmx_mio_uartx_tfl_s cn63xx;
+        struct cvmx_mio_uartx_tfl_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_tfr {
@@ -1662,6 +2023,8 @@ union cvmx_mio_uartx_tfr {
         struct cvmx_mio_uartx_tfr_s cn56xxp1;
         struct cvmx_mio_uartx_tfr_s cn58xx;
         struct cvmx_mio_uartx_tfr_s cn58xxp1;
+        struct cvmx_mio_uartx_tfr_s cn63xx;
+        struct cvmx_mio_uartx_tfr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_thr {
@@ -1681,6 +2044,8 @@ union cvmx_mio_uartx_thr {
         struct cvmx_mio_uartx_thr_s cn56xxp1;
         struct cvmx_mio_uartx_thr_s cn58xx;
         struct cvmx_mio_uartx_thr_s cn58xxp1;
+        struct cvmx_mio_uartx_thr_s cn63xx;
+        struct cvmx_mio_uartx_thr_s cn63xxp1;
 };
 
 union cvmx_mio_uartx_usr {
@@ -1704,6 +2069,8 @@ union cvmx_mio_uartx_usr {
         struct cvmx_mio_uartx_usr_s cn56xxp1;
         struct cvmx_mio_uartx_usr_s cn58xx;
         struct cvmx_mio_uartx_usr_s cn58xxp1;
+        struct cvmx_mio_uartx_usr_s cn63xx;
+        struct cvmx_mio_uartx_usr_s cn63xxp1;
 };
 
 union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
index dab6dca492f9..7057c447e69e 100644
--- a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,52 @@
 #ifndef __CVMX_MIXX_DEFS_H__
 #define __CVMX_MIXX_DEFS_H__
 
-#define CVMX_MIXX_BIST(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_CTL(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_INTENA(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRCNT(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRHWM(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_IRING2(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ISR(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORCNT(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORHWM(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING1(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_ORING2(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
-#define CVMX_MIXX_REMCNT(offset) \
-         CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
+#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
+#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
 
 union cvmx_mixx_bist {
         uint64_t u64;
         struct cvmx_mixx_bist_s {
-                uint64_t reserved_4_63:60;
+                uint64_t reserved_6_63:58;
+                uint64_t opfdat:1;
+                uint64_t mrgdat:1;
                 uint64_t mrqdat:1;
                 uint64_t ipfdat:1;
                 uint64_t irfdat:1;
                 uint64_t orfdat:1;
         } s;
-        struct cvmx_mixx_bist_s cn52xx;
-        struct cvmx_mixx_bist_s cn52xxp1;
-        struct cvmx_mixx_bist_s cn56xx;
-        struct cvmx_mixx_bist_s cn56xxp1;
+        struct cvmx_mixx_bist_cn52xx {
+                uint64_t reserved_4_63:60;
+                uint64_t mrqdat:1;
+                uint64_t ipfdat:1;
+                uint64_t irfdat:1;
+                uint64_t orfdat:1;
+        } cn52xx;
+        struct cvmx_mixx_bist_cn52xx cn52xxp1;
+        struct cvmx_mixx_bist_cn52xx cn56xx;
+        struct cvmx_mixx_bist_cn52xx cn56xxp1;
+        struct cvmx_mixx_bist_s cn63xx;
+        struct cvmx_mixx_bist_s cn63xxp1;
 };
 
 union cvmx_mixx_ctl {
         uint64_t u64;
         struct cvmx_mixx_ctl_s {
-                uint64_t reserved_8_63:56;
+                uint64_t reserved_12_63:52;
+                uint64_t ts_thresh:4;
                 uint64_t crc_strip:1;
                 uint64_t busy:1;
                 uint64_t en:1;
@@ -82,16 +82,28 @@ union cvmx_mixx_ctl {
                 uint64_t nbtarb:1;
                 uint64_t mrq_hwm:2;
         } s;
-        struct cvmx_mixx_ctl_s cn52xx;
-        struct cvmx_mixx_ctl_s cn52xxp1;
-        struct cvmx_mixx_ctl_s cn56xx;
-        struct cvmx_mixx_ctl_s cn56xxp1;
+        struct cvmx_mixx_ctl_cn52xx {
+                uint64_t reserved_8_63:56;
+                uint64_t crc_strip:1;
+                uint64_t busy:1;
+                uint64_t en:1;
+                uint64_t reset:1;
+                uint64_t lendian:1;
+                uint64_t nbtarb:1;
+                uint64_t mrq_hwm:2;
+        } cn52xx;
+        struct cvmx_mixx_ctl_cn52xx cn52xxp1;
+        struct cvmx_mixx_ctl_cn52xx cn56xx;
+        struct cvmx_mixx_ctl_cn52xx cn56xxp1;
+        struct cvmx_mixx_ctl_s cn63xx;
+        struct cvmx_mixx_ctl_s cn63xxp1;
 };
 
 union cvmx_mixx_intena {
         uint64_t u64;
         struct cvmx_mixx_intena_s {
-                uint64_t reserved_7_63:57;
+                uint64_t reserved_8_63:56;
+                uint64_t tsena:1;
                 uint64_t orunena:1;
                 uint64_t irunena:1;
                 uint64_t data_drpena:1;
@@ -100,10 +112,21 @@ union cvmx_mixx_intena {
                 uint64_t ivfena:1;
                 uint64_t ovfena:1;
         } s;
-        struct cvmx_mixx_intena_s cn52xx;
-        struct cvmx_mixx_intena_s cn52xxp1;
-        struct cvmx_mixx_intena_s cn56xx;
-        struct cvmx_mixx_intena_s cn56xxp1;
+        struct cvmx_mixx_intena_cn52xx {
+                uint64_t reserved_7_63:57;
+                uint64_t orunena:1;
+                uint64_t irunena:1;
+                uint64_t data_drpena:1;
+                uint64_t ithena:1;
+                uint64_t othena:1;
+                uint64_t ivfena:1;
+                uint64_t ovfena:1;
+        } cn52xx;
+        struct cvmx_mixx_intena_cn52xx cn52xxp1;
+        struct cvmx_mixx_intena_cn52xx cn56xx;
+        struct cvmx_mixx_intena_cn52xx cn56xxp1;
+        struct cvmx_mixx_intena_s cn63xx;
+        struct cvmx_mixx_intena_s cn63xxp1;
 };
 
 union cvmx_mixx_ircnt {
@@ -116,6 +139,8 @@ union cvmx_mixx_ircnt {
         struct cvmx_mixx_ircnt_s cn52xxp1;
         struct cvmx_mixx_ircnt_s cn56xx;
         struct cvmx_mixx_ircnt_s cn56xxp1;
+        struct cvmx_mixx_ircnt_s cn63xx;
+        struct cvmx_mixx_ircnt_s cn63xxp1;
 };
 
 union cvmx_mixx_irhwm {
@@ -129,6 +154,8 @@ union cvmx_mixx_irhwm {
         struct cvmx_mixx_irhwm_s cn52xxp1;
         struct cvmx_mixx_irhwm_s cn56xx;
         struct cvmx_mixx_irhwm_s cn56xxp1;
+        struct cvmx_mixx_irhwm_s cn63xx;
+        struct cvmx_mixx_irhwm_s cn63xxp1;
 };
 
 union cvmx_mixx_iring1 {
@@ -136,14 +163,21 @@ union cvmx_mixx_iring1 {
         struct cvmx_mixx_iring1_s {
                 uint64_t reserved_60_63:4;
                 uint64_t isize:20;
+                uint64_t ibase:37;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_iring1_cn52xx {
+                uint64_t reserved_60_63:4;
+                uint64_t isize:20;
                 uint64_t reserved_36_39:4;
                 uint64_t ibase:33;
                 uint64_t reserved_0_2:3;
-        } s;
-        struct cvmx_mixx_iring1_s cn52xx;
-        struct cvmx_mixx_iring1_s cn52xxp1;
-        struct cvmx_mixx_iring1_s cn56xx;
-        struct cvmx_mixx_iring1_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_mixx_iring1_cn52xx cn52xxp1;
+        struct cvmx_mixx_iring1_cn52xx cn56xx;
+        struct cvmx_mixx_iring1_cn52xx cn56xxp1;
+        struct cvmx_mixx_iring1_s cn63xx;
+        struct cvmx_mixx_iring1_s cn63xxp1;
 };
 
 union cvmx_mixx_iring2 {
@@ -158,12 +192,15 @@ union cvmx_mixx_iring2 {
         struct cvmx_mixx_iring2_s cn52xxp1;
         struct cvmx_mixx_iring2_s cn56xx;
         struct cvmx_mixx_iring2_s cn56xxp1;
+        struct cvmx_mixx_iring2_s cn63xx;
+        struct cvmx_mixx_iring2_s cn63xxp1;
 };
 
 union cvmx_mixx_isr {
         uint64_t u64;
         struct cvmx_mixx_isr_s {
-                uint64_t reserved_7_63:57;
+                uint64_t reserved_8_63:56;
+                uint64_t ts:1;
                 uint64_t orun:1;
                 uint64_t irun:1;
                 uint64_t data_drp:1;
@@ -172,10 +209,21 @@ union cvmx_mixx_isr {
                 uint64_t idblovf:1;
                 uint64_t odblovf:1;
         } s;
-        struct cvmx_mixx_isr_s cn52xx;
-        struct cvmx_mixx_isr_s cn52xxp1;
-        struct cvmx_mixx_isr_s cn56xx;
-        struct cvmx_mixx_isr_s cn56xxp1;
+        struct cvmx_mixx_isr_cn52xx {
+                uint64_t reserved_7_63:57;
+                uint64_t orun:1;
+                uint64_t irun:1;
+                uint64_t data_drp:1;
+                uint64_t irthresh:1;
+                uint64_t orthresh:1;
+                uint64_t idblovf:1;
+                uint64_t odblovf:1;
+        } cn52xx;
+        struct cvmx_mixx_isr_cn52xx cn52xxp1;
+        struct cvmx_mixx_isr_cn52xx cn56xx;
+        struct cvmx_mixx_isr_cn52xx cn56xxp1;
+        struct cvmx_mixx_isr_s cn63xx;
+        struct cvmx_mixx_isr_s cn63xxp1;
 };
 
 union cvmx_mixx_orcnt {
@@ -188,6 +236,8 @@ union cvmx_mixx_orcnt {
         struct cvmx_mixx_orcnt_s cn52xxp1;
         struct cvmx_mixx_orcnt_s cn56xx;
         struct cvmx_mixx_orcnt_s cn56xxp1;
+        struct cvmx_mixx_orcnt_s cn63xx;
+        struct cvmx_mixx_orcnt_s cn63xxp1;
 };
 
 union cvmx_mixx_orhwm {
@@ -200,6 +250,8 @@ union cvmx_mixx_orhwm {
         struct cvmx_mixx_orhwm_s cn52xxp1;
         struct cvmx_mixx_orhwm_s cn56xx;
         struct cvmx_mixx_orhwm_s cn56xxp1;
+        struct cvmx_mixx_orhwm_s cn63xx;
+        struct cvmx_mixx_orhwm_s cn63xxp1;
 };
 
 union cvmx_mixx_oring1 {
@@ -207,14 +259,21 @@ union cvmx_mixx_oring1 {
         struct cvmx_mixx_oring1_s {
                 uint64_t reserved_60_63:4;
                 uint64_t osize:20;
+                uint64_t obase:37;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_mixx_oring1_cn52xx {
+                uint64_t reserved_60_63:4;
+                uint64_t osize:20;
                 uint64_t reserved_36_39:4;
                 uint64_t obase:33;
                 uint64_t reserved_0_2:3;
-        } s;
-        struct cvmx_mixx_oring1_s cn52xx;
-        struct cvmx_mixx_oring1_s cn52xxp1;
-        struct cvmx_mixx_oring1_s cn56xx;
-        struct cvmx_mixx_oring1_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_mixx_oring1_cn52xx cn52xxp1;
+        struct cvmx_mixx_oring1_cn52xx cn56xx;
+        struct cvmx_mixx_oring1_cn52xx cn56xxp1;
+        struct cvmx_mixx_oring1_s cn63xx;
+        struct cvmx_mixx_oring1_s cn63xxp1;
 };
 
 union cvmx_mixx_oring2 {
@@ -229,6 +288,8 @@ union cvmx_mixx_oring2 {
         struct cvmx_mixx_oring2_s cn52xxp1;
         struct cvmx_mixx_oring2_s cn56xx;
         struct cvmx_mixx_oring2_s cn56xxp1;
+        struct cvmx_mixx_oring2_s cn63xx;
+        struct cvmx_mixx_oring2_s cn63xxp1;
 };
 
 union cvmx_mixx_remcnt {
@@ -243,6 +304,31 @@ union cvmx_mixx_remcnt {
         struct cvmx_mixx_remcnt_s cn52xxp1;
         struct cvmx_mixx_remcnt_s cn56xx;
         struct cvmx_mixx_remcnt_s cn56xxp1;
+        struct cvmx_mixx_remcnt_s cn63xx;
+        struct cvmx_mixx_remcnt_s cn63xxp1;
+};
+
+union cvmx_mixx_tsctl {
+        uint64_t u64;
+        struct cvmx_mixx_tsctl_s {
+                uint64_t reserved_21_63:43;
+                uint64_t tsavl:5;
+                uint64_t reserved_13_15:3;
+                uint64_t tstot:5;
+                uint64_t reserved_5_7:3;
+                uint64_t tscnt:5;
+        } s;
+        struct cvmx_mixx_tsctl_s cn63xx;
+        struct cvmx_mixx_tsctl_s cn63xxp1;
+};
+
+union cvmx_mixx_tstamp {
+        uint64_t u64;
+        struct cvmx_mixx_tstamp_s {
+                uint64_t tstamp:64;
+        } s;
+        struct cvmx_mixx_tstamp_s cn63xx;
+        struct cvmx_mixx_tstamp_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 4b347bb8ce80..9899a9d2ba72 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,206 +28,114 @@
 #ifndef __CVMX_NPEI_DEFS_H__
 #define __CVMX_NPEI_DEFS_H__
 
-#define CVMX_NPEI_BAR1_INDEXX(offset) \
-         (0x0000000000000000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_BIST_STATUS \
-         (0x0000000000000580ull)
-#define CVMX_NPEI_BIST_STATUS2 \
-         (0x0000000000000680ull)
-#define CVMX_NPEI_CTL_PORT0 \
-         (0x0000000000000250ull)
-#define CVMX_NPEI_CTL_PORT1 \
-         (0x0000000000000260ull)
-#define CVMX_NPEI_CTL_STATUS \
-         (0x0000000000000570ull)
-#define CVMX_NPEI_CTL_STATUS2 \
-         (0x0000000000003C00ull)
-#define CVMX_NPEI_DATA_OUT_CNT \
-         (0x00000000000005F0ull)
-#define CVMX_NPEI_DBG_DATA \
-         (0x0000000000000510ull)
-#define CVMX_NPEI_DBG_SELECT \
-         (0x0000000000000500ull)
-#define CVMX_NPEI_DMA0_INT_LEVEL \
-         (0x00000000000005C0ull)
-#define CVMX_NPEI_DMA1_INT_LEVEL \
-         (0x00000000000005D0ull)
-#define CVMX_NPEI_DMAX_COUNTS(offset) \
-         (0x0000000000000450ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_DBELL(offset) \
-         (0x00000000000003B0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
-         (0x0000000000000400ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMAX_NADDR(offset) \
-         (0x00000000000004A0ull + (((offset) & 7) * 16))
-#define CVMX_NPEI_DMA_CNTS \
-         (0x00000000000005E0ull)
-#define CVMX_NPEI_DMA_CONTROL \
-         (0x00000000000003A0ull)
-#define CVMX_NPEI_INT_A_ENB \
-         (0x0000000000000560ull)
-#define CVMX_NPEI_INT_A_ENB2 \
-         (0x0000000000003CE0ull)
-#define CVMX_NPEI_INT_A_SUM \
-         (0x0000000000000550ull)
-#define CVMX_NPEI_INT_ENB \
-         (0x0000000000000540ull)
-#define CVMX_NPEI_INT_ENB2 \
-         (0x0000000000003CD0ull)
-#define CVMX_NPEI_INT_INFO \
-         (0x0000000000000590ull)
-#define CVMX_NPEI_INT_SUM \
-         (0x0000000000000530ull)
-#define CVMX_NPEI_INT_SUM2 \
-         (0x0000000000003CC0ull)
-#define CVMX_NPEI_LAST_WIN_RDATA0 \
-         (0x0000000000000600ull)
-#define CVMX_NPEI_LAST_WIN_RDATA1 \
-         (0x0000000000000610ull)
-#define CVMX_NPEI_MEM_ACCESS_CTL \
-         (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
-         (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_NPEI_MSI_ENB0 \
-         (0x0000000000003C50ull)
-#define CVMX_NPEI_MSI_ENB1 \
-         (0x0000000000003C60ull)
-#define CVMX_NPEI_MSI_ENB2 \
-         (0x0000000000003C70ull)
-#define CVMX_NPEI_MSI_ENB3 \
-         (0x0000000000003C80ull)
-#define CVMX_NPEI_MSI_RCV0 \
-         (0x0000000000003C10ull)
-#define CVMX_NPEI_MSI_RCV1 \
-         (0x0000000000003C20ull)
-#define CVMX_NPEI_MSI_RCV2 \
-         (0x0000000000003C30ull)
-#define CVMX_NPEI_MSI_RCV3 \
-         (0x0000000000003C40ull)
-#define CVMX_NPEI_MSI_RD_MAP \
-         (0x0000000000003CA0ull)
-#define CVMX_NPEI_MSI_W1C_ENB0 \
-         (0x0000000000003CF0ull)
-#define CVMX_NPEI_MSI_W1C_ENB1 \
-         (0x0000000000003D00ull)
-#define CVMX_NPEI_MSI_W1C_ENB2 \
-         (0x0000000000003D10ull)
-#define CVMX_NPEI_MSI_W1C_ENB3 \
-         (0x0000000000003D20ull)
-#define CVMX_NPEI_MSI_W1S_ENB0 \
-         (0x0000000000003D30ull)
-#define CVMX_NPEI_MSI_W1S_ENB1 \
-         (0x0000000000003D40ull)
-#define CVMX_NPEI_MSI_W1S_ENB2 \
-         (0x0000000000003D50ull)
-#define CVMX_NPEI_MSI_W1S_ENB3 \
-         (0x0000000000003D60ull)
-#define CVMX_NPEI_MSI_WR_MAP \
-         (0x0000000000003C90ull)
-#define CVMX_NPEI_PCIE_CREDIT_CNT \
-         (0x0000000000003D70ull)
-#define CVMX_NPEI_PCIE_MSI_RCV \
-         (0x0000000000003CB0ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
-         (0x0000000000000650ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
-         (0x0000000000000660ull)
-#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
-         (0x0000000000000670ull)
-#define CVMX_NPEI_PKTX_CNTS(offset) \
-         (0x0000000000002400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
-         (0x0000000000002800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
-         (0x0000000000002C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
-         (0x0000000000003000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
-         (0x0000000000003400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_IN_BP(offset) \
-         (0x0000000000003800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
-         (0x0000000000001400ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
-         (0x0000000000001800ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
-         (0x0000000000001C00ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_CNT_INT \
-         (0x0000000000001110ull)
-#define CVMX_NPEI_PKT_CNT_INT_ENB \
-         (0x0000000000001130ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ES \
-         (0x00000000000010B0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_NS \
-         (0x00000000000010A0ull)
-#define CVMX_NPEI_PKT_DATA_OUT_ROR \
-         (0x0000000000001090ull)
-#define CVMX_NPEI_PKT_DPADDR \
-         (0x0000000000001080ull)
-#define CVMX_NPEI_PKT_INPUT_CONTROL \
-         (0x0000000000001150ull)
-#define CVMX_NPEI_PKT_INSTR_ENB \
-         (0x0000000000001000ull)
-#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
-         (0x0000000000001190ull)
-#define CVMX_NPEI_PKT_INSTR_SIZE \
-         (0x0000000000001020ull)
-#define CVMX_NPEI_PKT_INT_LEVELS \
-         (0x0000000000001100ull)
-#define CVMX_NPEI_PKT_IN_BP \
-         (0x00000000000006B0ull)
-#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
-         (0x0000000000002000ull + (((offset) & 31) * 16))
-#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
-         (0x00000000000006A0ull)
-#define CVMX_NPEI_PKT_IN_PCIE_PORT \
-         (0x00000000000011A0ull)
-#define CVMX_NPEI_PKT_IPTR \
-         (0x0000000000001070ull)
-#define CVMX_NPEI_PKT_OUTPUT_WMARK \
-         (0x0000000000001160ull)
-#define CVMX_NPEI_PKT_OUT_BMODE \
-         (0x00000000000010D0ull)
-#define CVMX_NPEI_PKT_OUT_ENB \
-         (0x0000000000001010ull)
-#define CVMX_NPEI_PKT_PCIE_PORT \
-         (0x00000000000010E0ull)
-#define CVMX_NPEI_PKT_PORT_IN_RST \
-         (0x0000000000000690ull)
-#define CVMX_NPEI_PKT_SLIST_ES \
-         (0x0000000000001050ull)
-#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
-         (0x0000000000001180ull)
-#define CVMX_NPEI_PKT_SLIST_NS \
-         (0x0000000000001040ull)
-#define CVMX_NPEI_PKT_SLIST_ROR \
-         (0x0000000000001030ull)
-#define CVMX_NPEI_PKT_TIME_INT \
-         (0x0000000000001120ull)
-#define CVMX_NPEI_PKT_TIME_INT_ENB \
-         (0x0000000000001140ull)
-#define CVMX_NPEI_RSL_INT_BLOCKS \
-         (0x0000000000000520ull)
-#define CVMX_NPEI_SCRATCH_1 \
-         (0x0000000000000270ull)
-#define CVMX_NPEI_STATE1 \
-         (0x0000000000000620ull)
-#define CVMX_NPEI_STATE2 \
-         (0x0000000000000630ull)
-#define CVMX_NPEI_STATE3 \
-         (0x0000000000000640ull)
-#define CVMX_NPEI_WINDOW_CTL \
-         (0x0000000000000380ull)
-#define CVMX_NPEI_WIN_RD_ADDR \
-         (0x0000000000000210ull)
-#define CVMX_NPEI_WIN_RD_DATA \
-         (0x0000000000000240ull)
-#define CVMX_NPEI_WIN_WR_ADDR \
-         (0x0000000000000200ull)
-#define CVMX_NPEI_WIN_WR_DATA \
-         (0x0000000000000220ull)
-#define CVMX_NPEI_WIN_WR_MASK \
-         (0x0000000000000230ull)
+#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
+#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
+#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
+#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
+#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
+#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
+#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
+#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
+#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
+#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
+#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
+#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
+#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
+#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
+#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
+#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
+#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
+#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
+#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
+#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
+#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
+#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
+#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
+#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
+#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
+#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
+#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
+#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
+#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
+#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
+#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
+#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
+#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
+#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
+#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
+#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
+#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
+#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
+#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
+#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
+#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
+#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
+#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
+#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
+#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
+#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
+#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
+#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
+#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
 
 union cvmx_npei_bar1_indexx {
         uint32_t u32;
@@ -248,9 +156,7 @@ union cvmx_npei_bist_status {
         uint64_t u64;
         struct cvmx_npei_bist_status_s {
                 uint64_t pkt_rdf:1;
-                uint64_t pkt_pmem:1;
-                uint64_t pkt_p1:1;
-                uint64_t reserved_60_60:1;
+                uint64_t reserved_60_62:3;
                 uint64_t pcr_gim:1;
                 uint64_t pkt_pif:1;
                 uint64_t pcsr_int:1;
@@ -301,9 +207,7 @@ union cvmx_npei_bist_status {
         } s;
         struct cvmx_npei_bist_status_cn52xx {
                 uint64_t pkt_rdf:1;
-                uint64_t pkt_pmem:1;
-                uint64_t pkt_p1:1;
-                uint64_t reserved_60_60:1;
+                uint64_t reserved_60_62:3;
                 uint64_t pcr_gim:1;
                 uint64_t pkt_pif:1;
                 uint64_t pcsr_int:1;
@@ -410,66 +314,7 @@ union cvmx_npei_bist_status {
                 uint64_t msi:1;
                 uint64_t ncb_cmd:1;
         } cn52xxp1;
-        struct cvmx_npei_bist_status_cn56xx {
-                uint64_t pkt_rdf:1;
-                uint64_t reserved_60_62:3;
-                uint64_t pcr_gim:1;
-                uint64_t pkt_pif:1;
-                uint64_t pcsr_int:1;
-                uint64_t pcsr_im:1;
-                uint64_t pcsr_cnt:1;
-                uint64_t pcsr_id:1;
-                uint64_t pcsr_sl:1;
-                uint64_t pkt_imem:1;
-                uint64_t pkt_pfm:1;
-                uint64_t pkt_pof:1;
-                uint64_t reserved_48_49:2;
-                uint64_t pkt_pop0:1;
-                uint64_t pkt_pop1:1;
-                uint64_t d0_mem:1;
-                uint64_t d1_mem:1;
-                uint64_t d2_mem:1;
-                uint64_t d3_mem:1;
-                uint64_t d4_mem:1;
-                uint64_t ds_mem:1;
-                uint64_t reserved_36_39:4;
-                uint64_t d0_pst:1;
-                uint64_t d1_pst:1;
-                uint64_t d2_pst:1;
-                uint64_t d3_pst:1;
-                uint64_t d4_pst:1;
-                uint64_t n2p0_c:1;
-                uint64_t n2p0_o:1;
-                uint64_t n2p1_c:1;
-                uint64_t n2p1_o:1;
-                uint64_t cpl_p0:1;
-                uint64_t cpl_p1:1;
-                uint64_t p2n1_po:1;
-                uint64_t p2n1_no:1;
-                uint64_t p2n1_co:1;
-                uint64_t p2n0_po:1;
-                uint64_t p2n0_no:1;
-                uint64_t p2n0_co:1;
-                uint64_t p2n0_c0:1;
-                uint64_t p2n0_c1:1;
-                uint64_t p2n0_n:1;
-                uint64_t p2n0_p0:1;
-                uint64_t p2n0_p1:1;
-                uint64_t p2n1_c0:1;
-                uint64_t p2n1_c1:1;
-                uint64_t p2n1_n:1;
-                uint64_t p2n1_p0:1;
-                uint64_t p2n1_p1:1;
-                uint64_t csm0:1;
-                uint64_t csm1:1;
-                uint64_t dif0:1;
-                uint64_t dif1:1;
-                uint64_t dif2:1;
-                uint64_t dif3:1;
-                uint64_t dif4:1;
-                uint64_t msi:1;
-                uint64_t ncb_cmd:1;
-        } cn56xx;
+        struct cvmx_npei_bist_status_cn52xx cn56xx;
         struct cvmx_npei_bist_status_cn56xxp1 {
                 uint64_t reserved_58_63:6;
                 uint64_t pcsr_int:1;
@@ -536,7 +381,16 @@ union cvmx_npei_bist_status {
 union cvmx_npei_bist_status2 {
         uint64_t u64;
         struct cvmx_npei_bist_status2_s {
-                uint64_t reserved_5_63:59;
+                uint64_t reserved_14_63:50;
+                uint64_t prd_tag:1;
+                uint64_t prd_st0:1;
+                uint64_t prd_st1:1;
+                uint64_t prd_err:1;
+                uint64_t nrd_st:1;
+                uint64_t nwe_st:1;
+                uint64_t nwe_wr0:1;
+                uint64_t nwe_wr1:1;
+                uint64_t pkt_rd:1;
                 uint64_t psc_p0:1;
                 uint64_t psc_p1:1;
                 uint64_t pkt_gd:1;
@@ -630,8 +484,7 @@ union cvmx_npei_ctl_status {
         } cn52xxp1;
         struct cvmx_npei_ctl_status_s cn56xx;
         struct cvmx_npei_ctl_status_cn56xxp1 {
-                uint64_t reserved_16_63:48;
-                uint64_t ring_en:1;
+                uint64_t reserved_15_63:49;
                 uint64_t lnk_rst:1;
                 uint64_t arb:1;
                 uint64_t pkt_bp:4;
@@ -756,14 +609,14 @@ union cvmx_npei_dmax_ibuff_saddr {
                 uint64_t saddr:29;
                 uint64_t reserved_0_6:7;
         } s;
-        struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
+        struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
                 uint64_t reserved_36_63:28;
                 uint64_t saddr:29;
                 uint64_t reserved_0_6:7;
-        } cn52xx;
-        struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
+        } cn52xxp1;
         struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
-        struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
 };
 
 union cvmx_npei_dmax_naddr {
@@ -817,7 +670,8 @@ union cvmx_npei_dma_cnts {
 union cvmx_npei_dma_control {
         uint64_t u64;
         struct cvmx_npei_dma_control_s {
-                uint64_t reserved_39_63:25;
+                uint64_t reserved_40_63:24;
+                uint64_t p_32b_m:1;
                 uint64_t dma4_enb:1;
                 uint64_t dma3_enb:1;
                 uint64_t dma2_enb:1;
@@ -853,7 +707,161 @@ union cvmx_npei_dma_control {
                 uint64_t csize:14;
         } cn52xxp1;
         struct cvmx_npei_dma_control_s cn56xx;
-        struct cvmx_npei_dma_control_s cn56xxp1;
+        struct cvmx_npei_dma_control_cn56xxp1 {
+                uint64_t reserved_39_63:25;
+                uint64_t dma4_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma0_enb:1;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t csize:14;
+        } cn56xxp1;
+};
+
+union cvmx_npei_dma_pcie_req_num {
+        uint64_t u64;
+        struct cvmx_npei_dma_pcie_req_num_s {
+                uint64_t dma_arb:1;
+                uint64_t reserved_53_62:10;
+                uint64_t pkt_cnt:5;
+                uint64_t reserved_45_47:3;
+                uint64_t dma4_cnt:5;
+                uint64_t reserved_37_39:3;
+                uint64_t dma3_cnt:5;
+                uint64_t reserved_29_31:3;
+                uint64_t dma2_cnt:5;
+                uint64_t reserved_21_23:3;
+                uint64_t dma1_cnt:5;
+                uint64_t reserved_13_15:3;
+                uint64_t dma0_cnt:5;
+                uint64_t reserved_5_7:3;
+                uint64_t dma_cnt:5;
+        } s;
+        struct cvmx_npei_dma_pcie_req_num_s cn52xx;
+        struct cvmx_npei_dma_pcie_req_num_s cn56xx;
+};
+
+union cvmx_npei_dma_state1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state1_s {
+                uint64_t reserved_40_63:24;
+                uint64_t d4_dwe:8;
+                uint64_t d3_dwe:8;
+                uint64_t d2_dwe:8;
+                uint64_t d1_dwe:8;
+                uint64_t d0_dwe:8;
+        } s;
+        struct cvmx_npei_dma_state1_s cn52xx;
+};
+
+union cvmx_npei_dma_state1_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state1_p1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t d0_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d3_difst:7;
+                uint64_t d4_difst:7;
+                uint64_t d0_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d3_reqst:5;
+                uint64_t d4_reqst:5;
+        } s;
+        struct cvmx_npei_dma_state1_p1_cn52xxp1 {
+                uint64_t reserved_60_63:4;
+                uint64_t d0_difst:7;
+                uint64_t d1_difst:7;
+                uint64_t d2_difst:7;
+                uint64_t d3_difst:7;
+                uint64_t reserved_25_31:7;
+                uint64_t d0_reqst:5;
+                uint64_t d1_reqst:5;
+                uint64_t d2_reqst:5;
+                uint64_t d3_reqst:5;
+                uint64_t reserved_0_4:5;
+        } cn52xxp1;
+        struct cvmx_npei_dma_state1_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state2 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state2_s {
+                uint64_t reserved_28_63:36;
+                uint64_t ndwe:4;
+                uint64_t reserved_21_23:3;
+                uint64_t ndre:5;
+                uint64_t reserved_10_15:6;
+                uint64_t prd:10;
+        } s;
+        struct cvmx_npei_dma_state2_s cn52xx;
+};
+
+union cvmx_npei_dma_state2_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state2_p1_s {
+                uint64_t reserved_45_63:19;
+                uint64_t d0_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d3_dffst:9;
+                uint64_t d4_dffst:9;
+        } s;
+        struct cvmx_npei_dma_state2_p1_cn52xxp1 {
+                uint64_t reserved_45_63:19;
+                uint64_t d0_dffst:9;
+                uint64_t d1_dffst:9;
+                uint64_t d2_dffst:9;
+                uint64_t d3_dffst:9;
+                uint64_t reserved_0_8:9;
+        } cn52xxp1;
+        struct cvmx_npei_dma_state2_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state3_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state3_p1_s {
+                uint64_t reserved_60_63:4;
+                uint64_t d0_drest:15;
+                uint64_t d1_drest:15;
+                uint64_t d2_drest:15;
+                uint64_t d3_drest:15;
+        } s;
+        struct cvmx_npei_dma_state3_p1_s cn52xxp1;
+        struct cvmx_npei_dma_state3_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state4_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state4_p1_s {
+                uint64_t reserved_52_63:12;
+                uint64_t d0_dwest:13;
+                uint64_t d1_dwest:13;
+                uint64_t d2_dwest:13;
+                uint64_t d3_dwest:13;
+        } s;
+        struct cvmx_npei_dma_state4_p1_s cn52xxp1;
+        struct cvmx_npei_dma_state4_p1_s cn56xxp1;
+};
+
+union cvmx_npei_dma_state5_p1 {
+        uint64_t u64;
+        struct cvmx_npei_dma_state5_p1_s {
+                uint64_t reserved_28_63:36;
+                uint64_t d4_drest:15;
+                uint64_t d4_dwest:13;
+        } s;
+        struct cvmx_npei_dma_state5_p1_s cn56xxp1;
 };
 
 union cvmx_npei_int_a_enb {
@@ -871,17 +879,7 @@ union cvmx_npei_int_a_enb {
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
         } s;
-        struct cvmx_npei_int_a_enb_cn52xx {
-                uint64_t reserved_8_63:56;
-                uint64_t p1_rdlk:1;
-                uint64_t p0_rdlk:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t dma1_cpl:1;
-                uint64_t dma0_cpl:1;
-        } cn52xx;
+        struct cvmx_npei_int_a_enb_s cn52xx;
         struct cvmx_npei_int_a_enb_cn52xxp1 {
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
@@ -905,16 +903,7 @@ union cvmx_npei_int_a_enb2 {
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
         } s;
-        struct cvmx_npei_int_a_enb2_cn52xx {
-                uint64_t reserved_8_63:56;
-                uint64_t p1_rdlk:1;
-                uint64_t p0_rdlk:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t reserved_0_1:2;
-        } cn52xx;
+        struct cvmx_npei_int_a_enb2_s cn52xx;
         struct cvmx_npei_int_a_enb2_cn52xxp1 {
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
@@ -938,17 +927,7 @@ union cvmx_npei_int_a_sum {
                 uint64_t dma1_cpl:1;
                 uint64_t dma0_cpl:1;
         } s;
-        struct cvmx_npei_int_a_sum_cn52xx {
-                uint64_t reserved_8_63:56;
-                uint64_t p1_rdlk:1;
-                uint64_t p0_rdlk:1;
-                uint64_t pgl_err:1;
-                uint64_t pdi_err:1;
-                uint64_t pop_err:1;
-                uint64_t pins_err:1;
-                uint64_t dma1_cpl:1;
-                uint64_t dma0_cpl:1;
-        } cn52xx;
+        struct cvmx_npei_int_a_sum_s cn52xx;
         struct cvmx_npei_int_a_sum_cn52xxp1 {
                 uint64_t reserved_2_63:62;
                 uint64_t dma1_cpl:1;
@@ -1550,10 +1529,7 @@ union cvmx_npei_int_sum {
                 uint64_t c0_se:1;
                 uint64_t reserved_20_20:1;
                 uint64_t c0_aeri:1;
-                uint64_t ptime:1;
-                uint64_t pcnt:1;
-                uint64_t pidbof:1;
-                uint64_t psldbof:1;
+                uint64_t reserved_15_18:4;
                 uint64_t dtime1:1;
                 uint64_t dtime0:1;
                 uint64_t dcnt1:1;
@@ -1959,7 +1935,6 @@ union cvmx_npei_pktx_cnts {
         } s;
         struct cvmx_npei_pktx_cnts_s cn52xx;
         struct cvmx_npei_pktx_cnts_s cn56xx;
-        struct cvmx_npei_pktx_cnts_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_in_bp {
@@ -1970,7 +1945,6 @@ union cvmx_npei_pktx_in_bp {
         } s;
         struct cvmx_npei_pktx_in_bp_s cn52xx;
         struct cvmx_npei_pktx_in_bp_s cn56xx;
-        struct cvmx_npei_pktx_in_bp_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_baddr {
@@ -1981,7 +1955,6 @@ union cvmx_npei_pktx_instr_baddr {
         } s;
         struct cvmx_npei_pktx_instr_baddr_s cn52xx;
         struct cvmx_npei_pktx_instr_baddr_s cn56xx;
-        struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_baoff_dbell {
@@ -1992,7 +1965,6 @@ union cvmx_npei_pktx_instr_baoff_dbell {
         } s;
         struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
         struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
-        struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_fifo_rsize {
@@ -2006,7 +1978,6 @@ union cvmx_npei_pktx_instr_fifo_rsize {
         } s;
         struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
         struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
-        struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_instr_header {
@@ -2014,21 +1985,20 @@ union cvmx_npei_pktx_instr_header {
         struct cvmx_npei_pktx_instr_header_s {
                 uint64_t reserved_44_63:20;
                 uint64_t pbp:1;
-                uint64_t rsv_f:5;
+                uint64_t reserved_38_42:5;
                 uint64_t rparmode:2;
-                uint64_t rsv_e:1;
+                uint64_t reserved_35_35:1;
                 uint64_t rskp_len:7;
-                uint64_t rsv_d:6;
+                uint64_t reserved_22_27:6;
                 uint64_t use_ihdr:1;
-                uint64_t rsv_c:5;
+                uint64_t reserved_16_20:5;
                 uint64_t par_mode:2;
-                uint64_t rsv_b:1;
+                uint64_t reserved_13_13:1;
                 uint64_t skp_len:7;
-                uint64_t rsv_a:6;
+                uint64_t reserved_0_5:6;
         } s;
         struct cvmx_npei_pktx_instr_header_s cn52xx;
         struct cvmx_npei_pktx_instr_header_s cn56xx;
-        struct cvmx_npei_pktx_instr_header_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_slist_baddr {
@@ -2039,7 +2009,6 @@ union cvmx_npei_pktx_slist_baddr {
         } s;
         struct cvmx_npei_pktx_slist_baddr_s cn52xx;
         struct cvmx_npei_pktx_slist_baddr_s cn56xx;
-        struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_slist_baoff_dbell {
@@ -2050,7 +2019,6 @@ union cvmx_npei_pktx_slist_baoff_dbell {
         } s;
         struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
         struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
-        struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
 };
 
 union cvmx_npei_pktx_slist_fifo_rsize {
@@ -2061,7 +2029,6 @@ union cvmx_npei_pktx_slist_fifo_rsize {
         } s;
         struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
         struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
-        struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_cnt_int {
@@ -2072,7 +2039,6 @@ union cvmx_npei_pkt_cnt_int {
         } s;
         struct cvmx_npei_pkt_cnt_int_s cn52xx;
         struct cvmx_npei_pkt_cnt_int_s cn56xx;
-        struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_cnt_int_enb {
@@ -2083,7 +2049,6 @@ union cvmx_npei_pkt_cnt_int_enb {
         } s;
         struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
         struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
-        struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_data_out_es {
@@ -2093,7 +2058,6 @@ union cvmx_npei_pkt_data_out_es {
         } s;
         struct cvmx_npei_pkt_data_out_es_s cn52xx;
         struct cvmx_npei_pkt_data_out_es_s cn56xx;
-        struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_data_out_ns {
@@ -2104,7 +2068,6 @@ union cvmx_npei_pkt_data_out_ns {
         } s;
         struct cvmx_npei_pkt_data_out_ns_s cn52xx;
         struct cvmx_npei_pkt_data_out_ns_s cn56xx;
-        struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_data_out_ror {
@@ -2115,7 +2078,6 @@ union cvmx_npei_pkt_data_out_ror {
         } s;
         struct cvmx_npei_pkt_data_out_ror_s cn52xx;
         struct cvmx_npei_pkt_data_out_ror_s cn56xx;
-        struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_dpaddr {
@@ -2126,7 +2088,6 @@ union cvmx_npei_pkt_dpaddr {
         } s;
         struct cvmx_npei_pkt_dpaddr_s cn52xx;
         struct cvmx_npei_pkt_dpaddr_s cn56xx;
-        struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_in_bp {
@@ -2135,6 +2096,7 @@ union cvmx_npei_pkt_in_bp {
                 uint64_t reserved_32_63:32;
                 uint64_t bp:32;
         } s;
+        struct cvmx_npei_pkt_in_bp_s cn52xx;
         struct cvmx_npei_pkt_in_bp_s cn56xx;
 };
 
@@ -2146,7 +2108,6 @@ union cvmx_npei_pkt_in_donex_cnts {
         } s;
         struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
         struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
-        struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_in_instr_counts {
@@ -2184,7 +2145,6 @@ union cvmx_npei_pkt_input_control {
         } s;
         struct cvmx_npei_pkt_input_control_s cn52xx;
         struct cvmx_npei_pkt_input_control_s cn56xx;
-        struct cvmx_npei_pkt_input_control_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_instr_enb {
@@ -2195,7 +2155,6 @@ union cvmx_npei_pkt_instr_enb {
         } s;
         struct cvmx_npei_pkt_instr_enb_s cn52xx;
         struct cvmx_npei_pkt_instr_enb_s cn56xx;
-        struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_instr_rd_size {
@@ -2215,7 +2174,6 @@ union cvmx_npei_pkt_instr_size {
         } s;
         struct cvmx_npei_pkt_instr_size_s cn52xx;
         struct cvmx_npei_pkt_instr_size_s cn56xx;
-        struct cvmx_npei_pkt_instr_size_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_int_levels {
@@ -2227,7 +2185,6 @@ union cvmx_npei_pkt_int_levels {
         } s;
         struct cvmx_npei_pkt_int_levels_s cn52xx;
         struct cvmx_npei_pkt_int_levels_s cn56xx;
-        struct cvmx_npei_pkt_int_levels_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_iptr {
@@ -2238,7 +2195,6 @@ union cvmx_npei_pkt_iptr {
         } s;
         struct cvmx_npei_pkt_iptr_s cn52xx;
         struct cvmx_npei_pkt_iptr_s cn56xx;
-        struct cvmx_npei_pkt_iptr_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_out_bmode {
@@ -2249,7 +2205,6 @@ union cvmx_npei_pkt_out_bmode {
         } s;
         struct cvmx_npei_pkt_out_bmode_s cn52xx;
         struct cvmx_npei_pkt_out_bmode_s cn56xx;
-        struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_out_enb {
@@ -2260,7 +2215,6 @@ union cvmx_npei_pkt_out_enb {
         } s;
         struct cvmx_npei_pkt_out_enb_s cn52xx;
         struct cvmx_npei_pkt_out_enb_s cn56xx;
-        struct cvmx_npei_pkt_out_enb_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_output_wmark {
@@ -2280,7 +2234,6 @@ union cvmx_npei_pkt_pcie_port {
         } s;
         struct cvmx_npei_pkt_pcie_port_s cn52xx;
         struct cvmx_npei_pkt_pcie_port_s cn56xx;
-        struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_port_in_rst {
@@ -2300,7 +2253,6 @@ union cvmx_npei_pkt_slist_es {
         } s;
         struct cvmx_npei_pkt_slist_es_s cn52xx;
         struct cvmx_npei_pkt_slist_es_s cn56xx;
-        struct cvmx_npei_pkt_slist_es_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_slist_id_size {
@@ -2312,7 +2264,6 @@ union cvmx_npei_pkt_slist_id_size {
         } s;
         struct cvmx_npei_pkt_slist_id_size_s cn52xx;
         struct cvmx_npei_pkt_slist_id_size_s cn56xx;
-        struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_slist_ns {
@@ -2323,7 +2274,6 @@ union cvmx_npei_pkt_slist_ns {
         } s;
         struct cvmx_npei_pkt_slist_ns_s cn52xx;
         struct cvmx_npei_pkt_slist_ns_s cn56xx;
-        struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_slist_ror {
@@ -2334,7 +2284,6 @@ union cvmx_npei_pkt_slist_ror {
         } s;
         struct cvmx_npei_pkt_slist_ror_s cn52xx;
         struct cvmx_npei_pkt_slist_ror_s cn56xx;
-        struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_time_int {
@@ -2345,7 +2294,6 @@ union cvmx_npei_pkt_time_int {
         } s;
         struct cvmx_npei_pkt_time_int_s cn52xx;
         struct cvmx_npei_pkt_time_int_s cn56xx;
-        struct cvmx_npei_pkt_time_int_s cn56xxp1;
 };
 
 union cvmx_npei_pkt_time_int_enb {
@@ -2356,7 +2304,6 @@ union cvmx_npei_pkt_time_int_enb {
         } s;
         struct cvmx_npei_pkt_time_int_enb_s cn52xx;
         struct cvmx_npei_pkt_time_int_enb_s cn56xx;
-        struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
 };
 
 union cvmx_npei_rsl_int_blocks {
@@ -2371,7 +2318,8 @@ union cvmx_npei_rsl_int_blocks {
                 uint64_t asxpcs0:1;
                 uint64_t reserved_21_21:1;
                 uint64_t pip:1;
-                uint64_t reserved_18_19:2;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
                 uint64_t lmc0:1;
                 uint64_t l2c:1;
                 uint64_t usb1:1;
@@ -2383,7 +2331,7 @@ union cvmx_npei_rsl_int_blocks {
                 uint64_t ipd:1;
                 uint64_t reserved_8_8:1;
                 uint64_t zip:1;
-                uint64_t reserved_6_6:1;
+                uint64_t dfa:1;
                 uint64_t fpa:1;
                 uint64_t key:1;
                 uint64_t npei:1;
@@ -2393,37 +2341,8 @@ union cvmx_npei_rsl_int_blocks {
         } s;
         struct cvmx_npei_rsl_int_blocks_s cn52xx;
         struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
-        struct cvmx_npei_rsl_int_blocks_cn56xx {
-                uint64_t reserved_31_63:33;
-                uint64_t iob:1;
-                uint64_t lmc1:1;
-                uint64_t agl:1;
-                uint64_t reserved_24_27:4;
-                uint64_t asxpcs1:1;
-                uint64_t asxpcs0:1;
-                uint64_t reserved_21_21:1;
-                uint64_t pip:1;
-                uint64_t reserved_18_19:2;
-                uint64_t lmc0:1;
-                uint64_t l2c:1;
-                uint64_t reserved_15_15:1;
-                uint64_t rad:1;
-                uint64_t usb:1;
-                uint64_t pow:1;
-                uint64_t tim:1;
-                uint64_t pko:1;
-                uint64_t ipd:1;
-                uint64_t reserved_8_8:1;
-                uint64_t zip:1;
-                uint64_t reserved_6_6:1;
-                uint64_t fpa:1;
-                uint64_t key:1;
-                uint64_t npei:1;
-                uint64_t gmx1:1;
-                uint64_t gmx0:1;
-                uint64_t mio:1;
-        } cn56xx;
-        struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
+        struct cvmx_npei_rsl_int_blocks_s cn56xx;
+        struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
 };
 
 union cvmx_npei_scratch_1 {
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index 4e03cd8561e3..f089c780060f 100644
--- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,246 +28,126 @@
 #ifndef __CVMX_NPI_DEFS_H__
 #define __CVMX_NPI_DEFS_H__
 
-#define CVMX_NPI_BASE_ADDR_INPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000000070ull)
-#define CVMX_NPI_BASE_ADDR_INPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000000080ull)
-#define CVMX_NPI_BASE_ADDR_INPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F0000000090ull)
-#define CVMX_NPI_BASE_ADDR_INPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
-#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
-#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
-#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
-#define CVMX_NPI_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
-#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_COMP_CTL \
-         CVMX_ADD_IO_SEG(0x00011F0000000218ull)
-#define CVMX_NPI_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F0000000010ull)
-#define CVMX_NPI_DBG_SELECT \
-         CVMX_ADD_IO_SEG(0x00011F0000000008ull)
-#define CVMX_NPI_DMA_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000000128ull)
-#define CVMX_NPI_DMA_HIGHP_COUNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000148ull)
-#define CVMX_NPI_DMA_HIGHP_NADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000158ull)
-#define CVMX_NPI_DMA_LOWP_COUNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000140ull)
-#define CVMX_NPI_DMA_LOWP_NADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000150ull)
-#define CVMX_NPI_HIGHP_DBELL \
-         CVMX_ADD_IO_SEG(0x00011F0000000120ull)
-#define CVMX_NPI_HIGHP_IBUFF_SADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000110ull)
-#define CVMX_NPI_INPUT_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000000138ull)
-#define CVMX_NPI_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000000020ull)
-#define CVMX_NPI_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00011F0000000018ull)
-#define CVMX_NPI_LOWP_DBELL \
-         CVMX_ADD_IO_SEG(0x00011F0000000118ull)
-#define CVMX_NPI_LOWP_IBUFF_SADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000108ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID3 \
-         CVMX_ADD_IO_SEG(0x00011F0000000028ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID4 \
-         CVMX_ADD_IO_SEG(0x00011F0000000030ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID5 \
-         CVMX_ADD_IO_SEG(0x00011F0000000038ull)
-#define CVMX_NPI_MEM_ACCESS_SUBID6 \
-         CVMX_ADD_IO_SEG(0x00011F0000000040ull)
-#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
-#define CVMX_NPI_MSI_RCV \
-         (0x0000000000000190ull)
-#define CVMX_NPI_NPI_MSI_RCV \
-         CVMX_ADD_IO_SEG(0x00011F0000001190ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000000050ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000000058ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F0000000060ull)
-#define CVMX_NPI_NUM_DESC_OUTPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F0000000068ull)
-#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
-#define CVMX_NPI_OUTPUT_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000000100ull)
-#define CVMX_NPI_P0_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000180ull)
-#define CVMX_NPI_P0_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
-#define CVMX_NPI_P0_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
-#define CVMX_NPI_P0_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000160ull)
-#define CVMX_NPI_P1_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000188ull)
-#define CVMX_NPI_P1_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
-#define CVMX_NPI_P1_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
-#define CVMX_NPI_P1_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000168ull)
-#define CVMX_NPI_P2_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000190ull)
-#define CVMX_NPI_P2_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
-#define CVMX_NPI_P2_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
-#define CVMX_NPI_P2_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000170ull)
-#define CVMX_NPI_P3_DBPAIR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000198ull)
-#define CVMX_NPI_P3_INSTR_ADDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
-#define CVMX_NPI_P3_INSTR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
-#define CVMX_NPI_P3_PAIR_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F0000000178ull)
-#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
-#define CVMX_NPI_PCI_BIST_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
-#define CVMX_NPI_PCI_BURST_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
-#define CVMX_NPI_PCI_CFG00 \
-         CVMX_ADD_IO_SEG(0x00011F0000001800ull)
-#define CVMX_NPI_PCI_CFG01 \
-         CVMX_ADD_IO_SEG(0x00011F0000001804ull)
-#define CVMX_NPI_PCI_CFG02 \
-         CVMX_ADD_IO_SEG(0x00011F0000001808ull)
-#define CVMX_NPI_PCI_CFG03 \
-         CVMX_ADD_IO_SEG(0x00011F000000180Cull)
-#define CVMX_NPI_PCI_CFG04 \
-         CVMX_ADD_IO_SEG(0x00011F0000001810ull)
-#define CVMX_NPI_PCI_CFG05 \
-         CVMX_ADD_IO_SEG(0x00011F0000001814ull)
-#define CVMX_NPI_PCI_CFG06 \
-         CVMX_ADD_IO_SEG(0x00011F0000001818ull)
-#define CVMX_NPI_PCI_CFG07 \
-         CVMX_ADD_IO_SEG(0x00011F000000181Cull)
-#define CVMX_NPI_PCI_CFG08 \
-         CVMX_ADD_IO_SEG(0x00011F0000001820ull)
-#define CVMX_NPI_PCI_CFG09 \
-         CVMX_ADD_IO_SEG(0x00011F0000001824ull)
-#define CVMX_NPI_PCI_CFG10 \
-         CVMX_ADD_IO_SEG(0x00011F0000001828ull)
-#define CVMX_NPI_PCI_CFG11 \
-         CVMX_ADD_IO_SEG(0x00011F000000182Cull)
-#define CVMX_NPI_PCI_CFG12 \
-         CVMX_ADD_IO_SEG(0x00011F0000001830ull)
-#define CVMX_NPI_PCI_CFG13 \
-         CVMX_ADD_IO_SEG(0x00011F0000001834ull)
-#define CVMX_NPI_PCI_CFG15 \
-         CVMX_ADD_IO_SEG(0x00011F000000183Cull)
-#define CVMX_NPI_PCI_CFG16 \
-         CVMX_ADD_IO_SEG(0x00011F0000001840ull)
-#define CVMX_NPI_PCI_CFG17 \
-         CVMX_ADD_IO_SEG(0x00011F0000001844ull)
-#define CVMX_NPI_PCI_CFG18 \
-         CVMX_ADD_IO_SEG(0x00011F0000001848ull)
-#define CVMX_NPI_PCI_CFG19 \
-         CVMX_ADD_IO_SEG(0x00011F000000184Cull)
-#define CVMX_NPI_PCI_CFG20 \
-         CVMX_ADD_IO_SEG(0x00011F0000001850ull)
-#define CVMX_NPI_PCI_CFG21 \
-         CVMX_ADD_IO_SEG(0x00011F0000001854ull)
-#define CVMX_NPI_PCI_CFG22 \
-         CVMX_ADD_IO_SEG(0x00011F0000001858ull)
-#define CVMX_NPI_PCI_CFG56 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
-#define CVMX_NPI_PCI_CFG57 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
-#define CVMX_NPI_PCI_CFG58 \
-         CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
-#define CVMX_NPI_PCI_CFG59 \
-         CVMX_ADD_IO_SEG(0x00011F00000018ECull)
-#define CVMX_NPI_PCI_CFG60 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
-#define CVMX_NPI_PCI_CFG61 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
-#define CVMX_NPI_PCI_CFG62 \
-         CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
-#define CVMX_NPI_PCI_CFG63 \
-         CVMX_ADD_IO_SEG(0x00011F00000018FCull)
-#define CVMX_NPI_PCI_CNT_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
-#define CVMX_NPI_PCI_CTL_STATUS_2 \
-         CVMX_ADD_IO_SEG(0x00011F000000118Cull)
-#define CVMX_NPI_PCI_INT_ARB_CFG \
-         CVMX_ADD_IO_SEG(0x00011F0000000130ull)
-#define CVMX_NPI_PCI_INT_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
-#define CVMX_NPI_PCI_INT_SUM2 \
-         CVMX_ADD_IO_SEG(0x00011F0000001198ull)
-#define CVMX_NPI_PCI_READ_CMD \
-         CVMX_ADD_IO_SEG(0x00011F0000000048ull)
-#define CVMX_NPI_PCI_READ_CMD_6 \
-         CVMX_ADD_IO_SEG(0x00011F0000001180ull)
-#define CVMX_NPI_PCI_READ_CMD_C \
-         CVMX_ADD_IO_SEG(0x00011F0000001184ull)
-#define CVMX_NPI_PCI_READ_CMD_E \
-         CVMX_ADD_IO_SEG(0x00011F0000001188ull)
-#define CVMX_NPI_PCI_SCM_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
-#define CVMX_NPI_PCI_TSR_REG \
-         CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
-#define CVMX_NPI_PORT32_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
-#define CVMX_NPI_PORT33_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000200ull)
-#define CVMX_NPI_PORT34_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000208ull)
-#define CVMX_NPI_PORT35_INSTR_HDR \
-         CVMX_ADD_IO_SEG(0x00011F0000000210ull)
-#define CVMX_NPI_PORT_BP_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
-#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_ADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_INSTR_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
-#define CVMX_NPI_PX_PAIR_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
-#define CVMX_NPI_RSL_INT_BLOCKS \
-         CVMX_ADD_IO_SEG(0x00011F0000000000ull)
-#define CVMX_NPI_SIZE_INPUT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000000078ull)
-#define CVMX_NPI_SIZE_INPUT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000000088ull)
-#define CVMX_NPI_SIZE_INPUT2 \
-         CVMX_ADD_IO_SEG(0x00011F0000000098ull)
-#define CVMX_NPI_SIZE_INPUT3 \
-         CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
-#define CVMX_NPI_SIZE_INPUTX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
-#define CVMX_NPI_WIN_READ_TO \
-         CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
+#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
+#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
+#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
+#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
+#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
+#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
+#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
+#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
+#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
+#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
+#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
+#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
+#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
+#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
+#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
+#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
+#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
+#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
+#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
+#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
+#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
+#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
+#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
+#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
+#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
+#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
+#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
+#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
+#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
+#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
+#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
+#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
+#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
+#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
+#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
+#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
+#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
+#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
+#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
+#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
+#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
+#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
+#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
+#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
+#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
+#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
+#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
+#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
+#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
+#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
+#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
+#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
+#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
+#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
+#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
+#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
+#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
+#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
+#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
+#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
+#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
+#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
+#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
+#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
+#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
+#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
+#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
+#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
+#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
+#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
+#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
+#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
+#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
+#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
+#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
+#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
+#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
+#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
+#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
+#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
+#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
+#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
+#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
+#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
+#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
+#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
+#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
+#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
+#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
 
 union cvmx_npi_base_addr_inputx {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
index 90f8d6535753..6ff6d9d357ba 100644
--- a/arch/mips/include/asm/octeon/cvmx-pci-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,184 +28,91 @@
 #ifndef __CVMX_PCI_DEFS_H__
 #define __CVMX_PCI_DEFS_H__
 
-#define CVMX_PCI_BAR1_INDEXX(offset) \
-         (0x0000000000000100ull + (((offset) & 31) * 4))
-#define CVMX_PCI_BIST_REG \
-         (0x00000000000001C0ull)
-#define CVMX_PCI_CFG00 \
-         (0x0000000000000000ull)
-#define CVMX_PCI_CFG01 \
-         (0x0000000000000004ull)
-#define CVMX_PCI_CFG02 \
-         (0x0000000000000008ull)
-#define CVMX_PCI_CFG03 \
-         (0x000000000000000Cull)
-#define CVMX_PCI_CFG04 \
-         (0x0000000000000010ull)
-#define CVMX_PCI_CFG05 \
-         (0x0000000000000014ull)
-#define CVMX_PCI_CFG06 \
-         (0x0000000000000018ull)
-#define CVMX_PCI_CFG07 \
-         (0x000000000000001Cull)
-#define CVMX_PCI_CFG08 \
-         (0x0000000000000020ull)
-#define CVMX_PCI_CFG09 \
-         (0x0000000000000024ull)
-#define CVMX_PCI_CFG10 \
-         (0x0000000000000028ull)
-#define CVMX_PCI_CFG11 \
-         (0x000000000000002Cull)
-#define CVMX_PCI_CFG12 \
-         (0x0000000000000030ull)
-#define CVMX_PCI_CFG13 \
-         (0x0000000000000034ull)
-#define CVMX_PCI_CFG15 \
-         (0x000000000000003Cull)
-#define CVMX_PCI_CFG16 \
-         (0x0000000000000040ull)
-#define CVMX_PCI_CFG17 \
-         (0x0000000000000044ull)
-#define CVMX_PCI_CFG18 \
-         (0x0000000000000048ull)
-#define CVMX_PCI_CFG19 \
-         (0x000000000000004Cull)
-#define CVMX_PCI_CFG20 \
-         (0x0000000000000050ull)
-#define CVMX_PCI_CFG21 \
-         (0x0000000000000054ull)
-#define CVMX_PCI_CFG22 \
-         (0x0000000000000058ull)
-#define CVMX_PCI_CFG56 \
-         (0x00000000000000E0ull)
-#define CVMX_PCI_CFG57 \
-         (0x00000000000000E4ull)
-#define CVMX_PCI_CFG58 \
-         (0x00000000000000E8ull)
-#define CVMX_PCI_CFG59 \
-         (0x00000000000000ECull)
-#define CVMX_PCI_CFG60 \
-         (0x00000000000000F0ull)
-#define CVMX_PCI_CFG61 \
-         (0x00000000000000F4ull)
-#define CVMX_PCI_CFG62 \
-         (0x00000000000000F8ull)
-#define CVMX_PCI_CFG63 \
-         (0x00000000000000FCull)
-#define CVMX_PCI_CNT_REG \
-         (0x00000000000001B8ull)
-#define CVMX_PCI_CTL_STATUS_2 \
-         (0x000000000000018Cull)
-#define CVMX_PCI_DBELL_0 \
-         (0x0000000000000080ull)
-#define CVMX_PCI_DBELL_1 \
-         (0x0000000000000088ull)
-#define CVMX_PCI_DBELL_2 \
-         (0x0000000000000090ull)
-#define CVMX_PCI_DBELL_3 \
-         (0x0000000000000098ull)
-#define CVMX_PCI_DBELL_X(offset) \
-         (0x0000000000000080ull + (((offset) & 3) * 8))
-#define CVMX_PCI_DMA_CNT0 \
-         (0x00000000000000A0ull)
-#define CVMX_PCI_DMA_CNT1 \
-         (0x00000000000000A8ull)
-#define CVMX_PCI_DMA_CNTX(offset) \
-         (0x00000000000000A0ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_INT_LEV0 \
-         (0x00000000000000A4ull)
-#define CVMX_PCI_DMA_INT_LEV1 \
-         (0x00000000000000ACull)
-#define CVMX_PCI_DMA_INT_LEVX(offset) \
-         (0x00000000000000A4ull + (((offset) & 1) * 8))
-#define CVMX_PCI_DMA_TIME0 \
-         (0x00000000000000B0ull)
-#define CVMX_PCI_DMA_TIME1 \
-         (0x00000000000000B4ull)
-#define CVMX_PCI_DMA_TIMEX(offset) \
-         (0x00000000000000B0ull + (((offset) & 1) * 4))
-#define CVMX_PCI_INSTR_COUNT0 \
-         (0x0000000000000084ull)
-#define CVMX_PCI_INSTR_COUNT1 \
-         (0x000000000000008Cull)
-#define CVMX_PCI_INSTR_COUNT2 \
-         (0x0000000000000094ull)
-#define CVMX_PCI_INSTR_COUNT3 \
-         (0x000000000000009Cull)
-#define CVMX_PCI_INSTR_COUNTX(offset) \
-         (0x0000000000000084ull + (((offset) & 3) * 8))
-#define CVMX_PCI_INT_ENB \
-         (0x0000000000000038ull)
-#define CVMX_PCI_INT_ENB2 \
-         (0x00000000000001A0ull)
-#define CVMX_PCI_INT_SUM \
-         (0x0000000000000030ull)
-#define CVMX_PCI_INT_SUM2 \
-         (0x0000000000000198ull)
-#define CVMX_PCI_MSI_RCV \
-         (0x00000000000000F0ull)
-#define CVMX_PCI_PKTS_SENT0 \
-         (0x0000000000000040ull)
-#define CVMX_PCI_PKTS_SENT1 \
-         (0x0000000000000050ull)
-#define CVMX_PCI_PKTS_SENT2 \
-         (0x0000000000000060ull)
-#define CVMX_PCI_PKTS_SENT3 \
-         (0x0000000000000070ull)
-#define CVMX_PCI_PKTS_SENTX(offset) \
-         (0x0000000000000040ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
-         (0x0000000000000048ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
-         (0x0000000000000058ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
-         (0x0000000000000068ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
-         (0x0000000000000078ull)
-#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
-         (0x0000000000000048ull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKTS_SENT_TIME0 \
-         (0x000000000000004Cull)
-#define CVMX_PCI_PKTS_SENT_TIME1 \
-         (0x000000000000005Cull)
-#define CVMX_PCI_PKTS_SENT_TIME2 \
-         (0x000000000000006Cull)
-#define CVMX_PCI_PKTS_SENT_TIME3 \
-         (0x000000000000007Cull)
-#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
-         (0x000000000000004Cull + (((offset) & 3) * 16))
-#define CVMX_PCI_PKT_CREDITS0 \
-         (0x0000000000000044ull)
-#define CVMX_PCI_PKT_CREDITS1 \
-         (0x0000000000000054ull)
-#define CVMX_PCI_PKT_CREDITS2 \
-         (0x0000000000000064ull)
-#define CVMX_PCI_PKT_CREDITS3 \
-         (0x0000000000000074ull)
-#define CVMX_PCI_PKT_CREDITSX(offset) \
-         (0x0000000000000044ull + (((offset) & 3) * 16))
-#define CVMX_PCI_READ_CMD_6 \
-         (0x0000000000000180ull)
-#define CVMX_PCI_READ_CMD_C \
-         (0x0000000000000184ull)
-#define CVMX_PCI_READ_CMD_E \
-         (0x0000000000000188ull)
-#define CVMX_PCI_READ_TIMEOUT \
-         CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
-#define CVMX_PCI_SCM_REG \
-         (0x00000000000001A8ull)
-#define CVMX_PCI_TSR_REG \
-         (0x00000000000001B0ull)
-#define CVMX_PCI_WIN_RD_ADDR \
-         (0x0000000000000008ull)
-#define CVMX_PCI_WIN_RD_DATA \
-         (0x0000000000000020ull)
-#define CVMX_PCI_WIN_WR_ADDR \
-         (0x0000000000000000ull)
-#define CVMX_PCI_WIN_WR_DATA \
-         (0x0000000000000010ull)
-#define CVMX_PCI_WIN_WR_MASK \
-         (0x0000000000000018ull)
+#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
+#define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
+#define CVMX_PCI_CFG00 (0x0000000000000000ull)
+#define CVMX_PCI_CFG01 (0x0000000000000004ull)
+#define CVMX_PCI_CFG02 (0x0000000000000008ull)
+#define CVMX_PCI_CFG03 (0x000000000000000Cull)
+#define CVMX_PCI_CFG04 (0x0000000000000010ull)
+#define CVMX_PCI_CFG05 (0x0000000000000014ull)
+#define CVMX_PCI_CFG06 (0x0000000000000018ull)
+#define CVMX_PCI_CFG07 (0x000000000000001Cull)
+#define CVMX_PCI_CFG08 (0x0000000000000020ull)
+#define CVMX_PCI_CFG09 (0x0000000000000024ull)
+#define CVMX_PCI_CFG10 (0x0000000000000028ull)
+#define CVMX_PCI_CFG11 (0x000000000000002Cull)
+#define CVMX_PCI_CFG12 (0x0000000000000030ull)
+#define CVMX_PCI_CFG13 (0x0000000000000034ull)
+#define CVMX_PCI_CFG15 (0x000000000000003Cull)
+#define CVMX_PCI_CFG16 (0x0000000000000040ull)
+#define CVMX_PCI_CFG17 (0x0000000000000044ull)
+#define CVMX_PCI_CFG18 (0x0000000000000048ull)
+#define CVMX_PCI_CFG19 (0x000000000000004Cull)
+#define CVMX_PCI_CFG20 (0x0000000000000050ull)
+#define CVMX_PCI_CFG21 (0x0000000000000054ull)
+#define CVMX_PCI_CFG22 (0x0000000000000058ull)
+#define CVMX_PCI_CFG56 (0x00000000000000E0ull)
+#define CVMX_PCI_CFG57 (0x00000000000000E4ull)
+#define CVMX_PCI_CFG58 (0x00000000000000E8ull)
+#define CVMX_PCI_CFG59 (0x00000000000000ECull)
+#define CVMX_PCI_CFG60 (0x00000000000000F0ull)
+#define CVMX_PCI_CFG61 (0x00000000000000F4ull)
+#define CVMX_PCI_CFG62 (0x00000000000000F8ull)
+#define CVMX_PCI_CFG63 (0x00000000000000FCull)
+#define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
+#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
+#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
+#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
+#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
+#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
+#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
+#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
+#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
+#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
+#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
+#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
+#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
+#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
+#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
+#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
+#define CVMX_PCI_INT_ENB (0x0000000000000038ull)
+#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
+#define CVMX_PCI_INT_SUM (0x0000000000000030ull)
+#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
+#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
+#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
+#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
+#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
+#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
+#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
+#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
+#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
+#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
+#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
+#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
+#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
+#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
+#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
+#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
+#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
+#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
+#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
+#define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
+#define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
+#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
+#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
+#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
+#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
 
 union cvmx_pci_bar1_indexx {
         uint32_t u32;
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index 75574c918942..f8cb88902efb 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,158 +28,83 @@
 #ifndef __CVMX_PCIERCX_DEFS_H__
 #define __CVMX_PCIERCX_DEFS_H__
 
-#define CVMX_PCIERCX_CFG000(offset) \
-         (0x0000000000000000ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG001(offset) \
-         (0x0000000000000004ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG002(offset) \
-         (0x0000000000000008ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG003(offset) \
-         (0x000000000000000Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG004(offset) \
-         (0x0000000000000010ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG005(offset) \
-         (0x0000000000000014ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG006(offset) \
-         (0x0000000000000018ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG007(offset) \
-         (0x000000000000001Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG008(offset) \
-         (0x0000000000000020ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG009(offset) \
-         (0x0000000000000024ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG010(offset) \
-         (0x0000000000000028ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG011(offset) \
-         (0x000000000000002Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG012(offset) \
-         (0x0000000000000030ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG013(offset) \
-         (0x0000000000000034ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG014(offset) \
-         (0x0000000000000038ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG015(offset) \
-         (0x000000000000003Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG016(offset) \
-         (0x0000000000000040ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG017(offset) \
-         (0x0000000000000044ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG020(offset) \
-         (0x0000000000000050ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG021(offset) \
-         (0x0000000000000054ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG022(offset) \
-         (0x0000000000000058ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG023(offset) \
-         (0x000000000000005Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG028(offset) \
-         (0x0000000000000070ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG029(offset) \
-         (0x0000000000000074ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG030(offset) \
-         (0x0000000000000078ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG031(offset) \
-         (0x000000000000007Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG032(offset) \
-         (0x0000000000000080ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG033(offset) \
-         (0x0000000000000084ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG034(offset) \
-         (0x0000000000000088ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG035(offset) \
-         (0x000000000000008Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG036(offset) \
-         (0x0000000000000090ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG037(offset) \
-         (0x0000000000000094ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG038(offset) \
-         (0x0000000000000098ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG039(offset) \
-         (0x000000000000009Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG040(offset) \
-         (0x00000000000000A0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG041(offset) \
-         (0x00000000000000A4ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG042(offset) \
-         (0x00000000000000A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG064(offset) \
-         (0x0000000000000100ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG065(offset) \
-         (0x0000000000000104ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG066(offset) \
-         (0x0000000000000108ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG067(offset) \
-         (0x000000000000010Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG068(offset) \
-         (0x0000000000000110ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG069(offset) \
-         (0x0000000000000114ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG070(offset) \
-         (0x0000000000000118ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG071(offset) \
-         (0x000000000000011Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG072(offset) \
-         (0x0000000000000120ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG073(offset) \
-         (0x0000000000000124ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG074(offset) \
-         (0x0000000000000128ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG075(offset) \
-         (0x000000000000012Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG076(offset) \
-         (0x0000000000000130ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG077(offset) \
-         (0x0000000000000134ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG448(offset) \
-         (0x0000000000000700ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG449(offset) \
-         (0x0000000000000704ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG450(offset) \
-         (0x0000000000000708ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG451(offset) \
-         (0x000000000000070Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG452(offset) \
-         (0x0000000000000710ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG453(offset) \
-         (0x0000000000000714ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG454(offset) \
-         (0x0000000000000718ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG455(offset) \
-         (0x000000000000071Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG456(offset) \
-         (0x0000000000000720ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG458(offset) \
-         (0x0000000000000728ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG459(offset) \
-         (0x000000000000072Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG460(offset) \
-         (0x0000000000000730ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG461(offset) \
-         (0x0000000000000734ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG462(offset) \
-         (0x0000000000000738ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG463(offset) \
-         (0x000000000000073Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG464(offset) \
-         (0x0000000000000740ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG465(offset) \
-         (0x0000000000000744ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG466(offset) \
-         (0x0000000000000748ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG467(offset) \
-         (0x000000000000074Cull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG468(offset) \
-         (0x0000000000000750ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG490(offset) \
-         (0x00000000000007A8ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG491(offset) \
-         (0x00000000000007ACull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG492(offset) \
-         (0x00000000000007B0ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG516(offset) \
-         (0x0000000000000810ull + (((offset) & 1) * 0))
-#define CVMX_PCIERCX_CFG517(offset) \
-         (0x0000000000000814ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull)
+#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
+#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull)
+#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull)
+#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull)
+#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull)
+#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
+#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull)
+#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
+#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
+#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
+#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
+#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull)
+#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull)
+#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull)
+#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull)
+#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull)
+#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull)
+#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull)
+#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull)
+#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull)
+#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull)
+#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull)
+#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull)
+#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
+#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
+#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
+#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull)
+#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
+#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
+#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull)
+#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull)
+#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull)
+#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull)
+#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
+#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull)
+#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull)
+#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull)
+#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull)
+#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
+#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull)
+#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull)
+#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
+#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
+#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull)
+#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull)
+#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull)
+#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull)
+#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
+#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull)
+#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull)
+#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
+#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull)
+#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull)
+#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull)
+#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
+#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull)
+#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull)
+#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
+#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull)
+#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull)
+#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull)
+#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull)
+#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull)
+#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull)
+#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull)
+#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull)
+#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull)
+#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull)
+#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull)
+#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull)
+#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull)
+#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull)
+#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull)
+#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
+#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull)
+#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull)
 
 union cvmx_pciercx_cfg000 {
         uint32_t u32;
@@ -191,6 +116,8 @@ union cvmx_pciercx_cfg000 {
         struct cvmx_pciercx_cfg000_s cn52xxp1;
         struct cvmx_pciercx_cfg000_s cn56xx;
         struct cvmx_pciercx_cfg000_s cn56xxp1;
+        struct cvmx_pciercx_cfg000_s cn63xx;
+        struct cvmx_pciercx_cfg000_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg001 {
@@ -225,6 +152,8 @@ union cvmx_pciercx_cfg001 {
         struct cvmx_pciercx_cfg001_s cn52xxp1;
         struct cvmx_pciercx_cfg001_s cn56xx;
         struct cvmx_pciercx_cfg001_s cn56xxp1;
+        struct cvmx_pciercx_cfg001_s cn63xx;
+        struct cvmx_pciercx_cfg001_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg002 {
@@ -239,6 +168,8 @@ union cvmx_pciercx_cfg002 {
         struct cvmx_pciercx_cfg002_s cn52xxp1;
         struct cvmx_pciercx_cfg002_s cn56xx;
         struct cvmx_pciercx_cfg002_s cn56xxp1;
+        struct cvmx_pciercx_cfg002_s cn63xx;
+        struct cvmx_pciercx_cfg002_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg003 {
@@ -254,6 +185,8 @@ union cvmx_pciercx_cfg003 {
         struct cvmx_pciercx_cfg003_s cn52xxp1;
         struct cvmx_pciercx_cfg003_s cn56xx;
         struct cvmx_pciercx_cfg003_s cn56xxp1;
+        struct cvmx_pciercx_cfg003_s cn63xx;
+        struct cvmx_pciercx_cfg003_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg004 {
@@ -265,6 +198,8 @@ union cvmx_pciercx_cfg004 {
         struct cvmx_pciercx_cfg004_s cn52xxp1;
         struct cvmx_pciercx_cfg004_s cn56xx;
         struct cvmx_pciercx_cfg004_s cn56xxp1;
+        struct cvmx_pciercx_cfg004_s cn63xx;
+        struct cvmx_pciercx_cfg004_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg005 {
@@ -276,6 +211,8 @@ union cvmx_pciercx_cfg005 {
         struct cvmx_pciercx_cfg005_s cn52xxp1;
         struct cvmx_pciercx_cfg005_s cn56xx;
         struct cvmx_pciercx_cfg005_s cn56xxp1;
+        struct cvmx_pciercx_cfg005_s cn63xx;
+        struct cvmx_pciercx_cfg005_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg006 {
@@ -290,6 +227,8 @@ union cvmx_pciercx_cfg006 {
         struct cvmx_pciercx_cfg006_s cn52xxp1;
         struct cvmx_pciercx_cfg006_s cn56xx;
         struct cvmx_pciercx_cfg006_s cn56xxp1;
+        struct cvmx_pciercx_cfg006_s cn63xx;
+        struct cvmx_pciercx_cfg006_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg007 {
@@ -317,6 +256,8 @@ union cvmx_pciercx_cfg007 {
         struct cvmx_pciercx_cfg007_s cn52xxp1;
         struct cvmx_pciercx_cfg007_s cn56xx;
         struct cvmx_pciercx_cfg007_s cn56xxp1;
+        struct cvmx_pciercx_cfg007_s cn63xx;
+        struct cvmx_pciercx_cfg007_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg008 {
@@ -331,6 +272,8 @@ union cvmx_pciercx_cfg008 {
         struct cvmx_pciercx_cfg008_s cn52xxp1;
         struct cvmx_pciercx_cfg008_s cn56xx;
         struct cvmx_pciercx_cfg008_s cn56xxp1;
+        struct cvmx_pciercx_cfg008_s cn63xx;
+        struct cvmx_pciercx_cfg008_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg009 {
@@ -347,6 +290,8 @@ union cvmx_pciercx_cfg009 {
         struct cvmx_pciercx_cfg009_s cn52xxp1;
         struct cvmx_pciercx_cfg009_s cn56xx;
         struct cvmx_pciercx_cfg009_s cn56xxp1;
+        struct cvmx_pciercx_cfg009_s cn63xx;
+        struct cvmx_pciercx_cfg009_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg010 {
@@ -358,6 +303,8 @@ union cvmx_pciercx_cfg010 {
         struct cvmx_pciercx_cfg010_s cn52xxp1;
         struct cvmx_pciercx_cfg010_s cn56xx;
         struct cvmx_pciercx_cfg010_s cn56xxp1;
+        struct cvmx_pciercx_cfg010_s cn63xx;
+        struct cvmx_pciercx_cfg010_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg011 {
@@ -369,6 +316,8 @@ union cvmx_pciercx_cfg011 {
         struct cvmx_pciercx_cfg011_s cn52xxp1;
         struct cvmx_pciercx_cfg011_s cn56xx;
         struct cvmx_pciercx_cfg011_s cn56xxp1;
+        struct cvmx_pciercx_cfg011_s cn63xx;
+        struct cvmx_pciercx_cfg011_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg012 {
@@ -381,6 +330,8 @@ union cvmx_pciercx_cfg012 {
         struct cvmx_pciercx_cfg012_s cn52xxp1;
         struct cvmx_pciercx_cfg012_s cn56xx;
         struct cvmx_pciercx_cfg012_s cn56xxp1;
+        struct cvmx_pciercx_cfg012_s cn63xx;
+        struct cvmx_pciercx_cfg012_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg013 {
@@ -393,6 +344,8 @@ union cvmx_pciercx_cfg013 {
         struct cvmx_pciercx_cfg013_s cn52xxp1;
         struct cvmx_pciercx_cfg013_s cn56xx;
         struct cvmx_pciercx_cfg013_s cn56xxp1;
+        struct cvmx_pciercx_cfg013_s cn63xx;
+        struct cvmx_pciercx_cfg013_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg014 {
@@ -404,6 +357,8 @@ union cvmx_pciercx_cfg014 {
         struct cvmx_pciercx_cfg014_s cn52xxp1;
         struct cvmx_pciercx_cfg014_s cn56xx;
         struct cvmx_pciercx_cfg014_s cn56xxp1;
+        struct cvmx_pciercx_cfg014_s cn63xx;
+        struct cvmx_pciercx_cfg014_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg015 {
@@ -429,6 +384,8 @@ union cvmx_pciercx_cfg015 {
         struct cvmx_pciercx_cfg015_s cn52xxp1;
         struct cvmx_pciercx_cfg015_s cn56xx;
         struct cvmx_pciercx_cfg015_s cn56xxp1;
+        struct cvmx_pciercx_cfg015_s cn63xx;
+        struct cvmx_pciercx_cfg015_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg016 {
@@ -449,6 +406,8 @@ union cvmx_pciercx_cfg016 {
         struct cvmx_pciercx_cfg016_s cn52xxp1;
         struct cvmx_pciercx_cfg016_s cn56xx;
         struct cvmx_pciercx_cfg016_s cn56xxp1;
+        struct cvmx_pciercx_cfg016_s cn63xx;
+        struct cvmx_pciercx_cfg016_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg017 {
@@ -471,6 +430,8 @@ union cvmx_pciercx_cfg017 {
         struct cvmx_pciercx_cfg017_s cn52xxp1;
         struct cvmx_pciercx_cfg017_s cn56xx;
         struct cvmx_pciercx_cfg017_s cn56xxp1;
+        struct cvmx_pciercx_cfg017_s cn63xx;
+        struct cvmx_pciercx_cfg017_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg020 {
@@ -488,6 +449,8 @@ union cvmx_pciercx_cfg020 {
         struct cvmx_pciercx_cfg020_s cn52xxp1;
         struct cvmx_pciercx_cfg020_s cn56xx;
         struct cvmx_pciercx_cfg020_s cn56xxp1;
+        struct cvmx_pciercx_cfg020_s cn63xx;
+        struct cvmx_pciercx_cfg020_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg021 {
@@ -500,6 +463,8 @@ union cvmx_pciercx_cfg021 {
         struct cvmx_pciercx_cfg021_s cn52xxp1;
         struct cvmx_pciercx_cfg021_s cn56xx;
         struct cvmx_pciercx_cfg021_s cn56xxp1;
+        struct cvmx_pciercx_cfg021_s cn63xx;
+        struct cvmx_pciercx_cfg021_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg022 {
@@ -511,6 +476,8 @@ union cvmx_pciercx_cfg022 {
         struct cvmx_pciercx_cfg022_s cn52xxp1;
         struct cvmx_pciercx_cfg022_s cn56xx;
         struct cvmx_pciercx_cfg022_s cn56xxp1;
+        struct cvmx_pciercx_cfg022_s cn63xx;
+        struct cvmx_pciercx_cfg022_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg023 {
@@ -523,6 +490,8 @@ union cvmx_pciercx_cfg023 {
         struct cvmx_pciercx_cfg023_s cn52xxp1;
         struct cvmx_pciercx_cfg023_s cn56xx;
         struct cvmx_pciercx_cfg023_s cn56xxp1;
+        struct cvmx_pciercx_cfg023_s cn63xx;
+        struct cvmx_pciercx_cfg023_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg028 {
@@ -540,6 +509,8 @@ union cvmx_pciercx_cfg028 {
         struct cvmx_pciercx_cfg028_s cn52xxp1;
         struct cvmx_pciercx_cfg028_s cn56xx;
         struct cvmx_pciercx_cfg028_s cn56xxp1;
+        struct cvmx_pciercx_cfg028_s cn63xx;
+        struct cvmx_pciercx_cfg028_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg029 {
@@ -561,6 +532,8 @@ union cvmx_pciercx_cfg029 {
         struct cvmx_pciercx_cfg029_s cn52xxp1;
         struct cvmx_pciercx_cfg029_s cn56xx;
         struct cvmx_pciercx_cfg029_s cn56xxp1;
+        struct cvmx_pciercx_cfg029_s cn63xx;
+        struct cvmx_pciercx_cfg029_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg030 {
@@ -590,6 +563,8 @@ union cvmx_pciercx_cfg030 {
         struct cvmx_pciercx_cfg030_s cn52xxp1;
         struct cvmx_pciercx_cfg030_s cn56xx;
         struct cvmx_pciercx_cfg030_s cn56xxp1;
+        struct cvmx_pciercx_cfg030_s cn63xx;
+        struct cvmx_pciercx_cfg030_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg031 {
@@ -611,6 +586,8 @@ union cvmx_pciercx_cfg031 {
         struct cvmx_pciercx_cfg031_s cn52xxp1;
         struct cvmx_pciercx_cfg031_s cn56xx;
         struct cvmx_pciercx_cfg031_s cn56xxp1;
+        struct cvmx_pciercx_cfg031_s cn63xx;
+        struct cvmx_pciercx_cfg031_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg032 {
@@ -641,6 +618,8 @@ union cvmx_pciercx_cfg032 {
         struct cvmx_pciercx_cfg032_s cn52xxp1;
         struct cvmx_pciercx_cfg032_s cn56xx;
         struct cvmx_pciercx_cfg032_s cn56xxp1;
+        struct cvmx_pciercx_cfg032_s cn63xx;
+        struct cvmx_pciercx_cfg032_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg033 {
@@ -663,6 +642,8 @@ union cvmx_pciercx_cfg033 {
         struct cvmx_pciercx_cfg033_s cn52xxp1;
         struct cvmx_pciercx_cfg033_s cn56xx;
         struct cvmx_pciercx_cfg033_s cn56xxp1;
+        struct cvmx_pciercx_cfg033_s cn63xx;
+        struct cvmx_pciercx_cfg033_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg034 {
@@ -695,6 +676,8 @@ union cvmx_pciercx_cfg034 {
         struct cvmx_pciercx_cfg034_s cn52xxp1;
         struct cvmx_pciercx_cfg034_s cn56xx;
         struct cvmx_pciercx_cfg034_s cn56xxp1;
+        struct cvmx_pciercx_cfg034_s cn63xx;
+        struct cvmx_pciercx_cfg034_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg035 {
@@ -713,6 +696,8 @@ union cvmx_pciercx_cfg035 {
         struct cvmx_pciercx_cfg035_s cn52xxp1;
         struct cvmx_pciercx_cfg035_s cn56xx;
         struct cvmx_pciercx_cfg035_s cn56xxp1;
+        struct cvmx_pciercx_cfg035_s cn63xx;
+        struct cvmx_pciercx_cfg035_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg036 {
@@ -727,6 +712,8 @@ union cvmx_pciercx_cfg036 {
         struct cvmx_pciercx_cfg036_s cn52xxp1;
         struct cvmx_pciercx_cfg036_s cn56xx;
         struct cvmx_pciercx_cfg036_s cn56xxp1;
+        struct cvmx_pciercx_cfg036_s cn63xx;
+        struct cvmx_pciercx_cfg036_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg037 {
@@ -740,6 +727,8 @@ union cvmx_pciercx_cfg037 {
         struct cvmx_pciercx_cfg037_s cn52xxp1;
         struct cvmx_pciercx_cfg037_s cn56xx;
         struct cvmx_pciercx_cfg037_s cn56xxp1;
+        struct cvmx_pciercx_cfg037_s cn63xx;
+        struct cvmx_pciercx_cfg037_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg038 {
@@ -753,28 +742,51 @@ union cvmx_pciercx_cfg038 {
         struct cvmx_pciercx_cfg038_s cn52xxp1;
         struct cvmx_pciercx_cfg038_s cn56xx;
         struct cvmx_pciercx_cfg038_s cn56xxp1;
+        struct cvmx_pciercx_cfg038_s cn63xx;
+        struct cvmx_pciercx_cfg038_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg039 {
         uint32_t u32;
         struct cvmx_pciercx_cfg039_s {
-                uint32_t reserved_0_31:32;
+                uint32_t reserved_9_31:23;
+                uint32_t cls:1;
+                uint32_t slsv:7;
+                uint32_t reserved_0_0:1;
         } s;
-        struct cvmx_pciercx_cfg039_s cn52xx;
-        struct cvmx_pciercx_cfg039_s cn52xxp1;
-        struct cvmx_pciercx_cfg039_s cn56xx;
-        struct cvmx_pciercx_cfg039_s cn56xxp1;
+        struct cvmx_pciercx_cfg039_cn52xx {
+                uint32_t reserved_0_31:32;
+        } cn52xx;
+        struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg039_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg039_s cn63xx;
+        struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
 };
 
 union cvmx_pciercx_cfg040 {
         uint32_t u32;
         struct cvmx_pciercx_cfg040_s {
+                uint32_t reserved_17_31:15;
+                uint32_t cdl:1;
+                uint32_t reserved_13_15:3;
+                uint32_t cde:1;
+                uint32_t csos:1;
+                uint32_t emc:1;
+                uint32_t tm:3;
+                uint32_t sde:1;
+                uint32_t hasd:1;
+                uint32_t ec:1;
+                uint32_t tls:4;
+        } s;
+        struct cvmx_pciercx_cfg040_cn52xx {
                 uint32_t reserved_0_31:32;
-        } s;
-        struct cvmx_pciercx_cfg040_s cn52xx;
-        struct cvmx_pciercx_cfg040_s cn52xxp1;
-        struct cvmx_pciercx_cfg040_s cn56xx;
-        struct cvmx_pciercx_cfg040_s cn56xxp1;
+        } cn52xx;
+        struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
+        struct cvmx_pciercx_cfg040_cn52xx cn56xx;
+        struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
+        struct cvmx_pciercx_cfg040_s cn63xx;
+        struct cvmx_pciercx_cfg040_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg041 {
@@ -786,6 +798,8 @@ union cvmx_pciercx_cfg041 {
         struct cvmx_pciercx_cfg041_s cn52xxp1;
         struct cvmx_pciercx_cfg041_s cn56xx;
         struct cvmx_pciercx_cfg041_s cn56xxp1;
+        struct cvmx_pciercx_cfg041_s cn63xx;
+        struct cvmx_pciercx_cfg041_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg042 {
@@ -797,6 +811,8 @@ union cvmx_pciercx_cfg042 {
         struct cvmx_pciercx_cfg042_s cn52xxp1;
         struct cvmx_pciercx_cfg042_s cn56xx;
         struct cvmx_pciercx_cfg042_s cn56xxp1;
+        struct cvmx_pciercx_cfg042_s cn63xx;
+        struct cvmx_pciercx_cfg042_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg064 {
@@ -810,6 +826,8 @@ union cvmx_pciercx_cfg064 {
         struct cvmx_pciercx_cfg064_s cn52xxp1;
         struct cvmx_pciercx_cfg064_s cn56xx;
         struct cvmx_pciercx_cfg064_s cn56xxp1;
+        struct cvmx_pciercx_cfg064_s cn63xx;
+        struct cvmx_pciercx_cfg064_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg065 {
@@ -834,6 +852,8 @@ union cvmx_pciercx_cfg065 {
         struct cvmx_pciercx_cfg065_s cn52xxp1;
         struct cvmx_pciercx_cfg065_s cn56xx;
         struct cvmx_pciercx_cfg065_s cn56xxp1;
+        struct cvmx_pciercx_cfg065_s cn63xx;
+        struct cvmx_pciercx_cfg065_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg066 {
@@ -858,6 +878,8 @@ union cvmx_pciercx_cfg066 {
         struct cvmx_pciercx_cfg066_s cn52xxp1;
         struct cvmx_pciercx_cfg066_s cn56xx;
         struct cvmx_pciercx_cfg066_s cn56xxp1;
+        struct cvmx_pciercx_cfg066_s cn63xx;
+        struct cvmx_pciercx_cfg066_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg067 {
@@ -882,6 +904,8 @@ union cvmx_pciercx_cfg067 {
         struct cvmx_pciercx_cfg067_s cn52xxp1;
         struct cvmx_pciercx_cfg067_s cn56xx;
         struct cvmx_pciercx_cfg067_s cn56xxp1;
+        struct cvmx_pciercx_cfg067_s cn63xx;
+        struct cvmx_pciercx_cfg067_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg068 {
@@ -901,6 +925,8 @@ union cvmx_pciercx_cfg068 {
         struct cvmx_pciercx_cfg068_s cn52xxp1;
         struct cvmx_pciercx_cfg068_s cn56xx;
         struct cvmx_pciercx_cfg068_s cn56xxp1;
+        struct cvmx_pciercx_cfg068_s cn63xx;
+        struct cvmx_pciercx_cfg068_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg069 {
@@ -920,6 +946,8 @@ union cvmx_pciercx_cfg069 {
         struct cvmx_pciercx_cfg069_s cn52xxp1;
         struct cvmx_pciercx_cfg069_s cn56xx;
         struct cvmx_pciercx_cfg069_s cn56xxp1;
+        struct cvmx_pciercx_cfg069_s cn63xx;
+        struct cvmx_pciercx_cfg069_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg070 {
@@ -936,6 +964,8 @@ union cvmx_pciercx_cfg070 {
         struct cvmx_pciercx_cfg070_s cn52xxp1;
         struct cvmx_pciercx_cfg070_s cn56xx;
         struct cvmx_pciercx_cfg070_s cn56xxp1;
+        struct cvmx_pciercx_cfg070_s cn63xx;
+        struct cvmx_pciercx_cfg070_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg071 {
@@ -947,6 +977,8 @@ union cvmx_pciercx_cfg071 {
         struct cvmx_pciercx_cfg071_s cn52xxp1;
         struct cvmx_pciercx_cfg071_s cn56xx;
         struct cvmx_pciercx_cfg071_s cn56xxp1;
+        struct cvmx_pciercx_cfg071_s cn63xx;
+        struct cvmx_pciercx_cfg071_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg072 {
@@ -958,6 +990,8 @@ union cvmx_pciercx_cfg072 {
         struct cvmx_pciercx_cfg072_s cn52xxp1;
         struct cvmx_pciercx_cfg072_s cn56xx;
         struct cvmx_pciercx_cfg072_s cn56xxp1;
+        struct cvmx_pciercx_cfg072_s cn63xx;
+        struct cvmx_pciercx_cfg072_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg073 {
@@ -969,6 +1003,8 @@ union cvmx_pciercx_cfg073 {
         struct cvmx_pciercx_cfg073_s cn52xxp1;
         struct cvmx_pciercx_cfg073_s cn56xx;
         struct cvmx_pciercx_cfg073_s cn56xxp1;
+        struct cvmx_pciercx_cfg073_s cn63xx;
+        struct cvmx_pciercx_cfg073_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg074 {
@@ -980,6 +1016,8 @@ union cvmx_pciercx_cfg074 {
         struct cvmx_pciercx_cfg074_s cn52xxp1;
         struct cvmx_pciercx_cfg074_s cn56xx;
         struct cvmx_pciercx_cfg074_s cn56xxp1;
+        struct cvmx_pciercx_cfg074_s cn63xx;
+        struct cvmx_pciercx_cfg074_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg075 {
@@ -994,6 +1032,8 @@ union cvmx_pciercx_cfg075 {
         struct cvmx_pciercx_cfg075_s cn52xxp1;
         struct cvmx_pciercx_cfg075_s cn56xx;
         struct cvmx_pciercx_cfg075_s cn56xxp1;
+        struct cvmx_pciercx_cfg075_s cn63xx;
+        struct cvmx_pciercx_cfg075_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg076 {
@@ -1013,6 +1053,8 @@ union cvmx_pciercx_cfg076 {
         struct cvmx_pciercx_cfg076_s cn52xxp1;
         struct cvmx_pciercx_cfg076_s cn56xx;
         struct cvmx_pciercx_cfg076_s cn56xxp1;
+        struct cvmx_pciercx_cfg076_s cn63xx;
+        struct cvmx_pciercx_cfg076_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg077 {
@@ -1025,6 +1067,8 @@ union cvmx_pciercx_cfg077 {
         struct cvmx_pciercx_cfg077_s cn52xxp1;
         struct cvmx_pciercx_cfg077_s cn56xx;
         struct cvmx_pciercx_cfg077_s cn56xxp1;
+        struct cvmx_pciercx_cfg077_s cn63xx;
+        struct cvmx_pciercx_cfg077_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg448 {
@@ -1037,6 +1081,8 @@ union cvmx_pciercx_cfg448 {
         struct cvmx_pciercx_cfg448_s cn52xxp1;
         struct cvmx_pciercx_cfg448_s cn56xx;
         struct cvmx_pciercx_cfg448_s cn56xxp1;
+        struct cvmx_pciercx_cfg448_s cn63xx;
+        struct cvmx_pciercx_cfg448_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg449 {
@@ -1048,6 +1094,8 @@ union cvmx_pciercx_cfg449 {
         struct cvmx_pciercx_cfg449_s cn52xxp1;
         struct cvmx_pciercx_cfg449_s cn56xx;
         struct cvmx_pciercx_cfg449_s cn56xxp1;
+        struct cvmx_pciercx_cfg449_s cn63xx;
+        struct cvmx_pciercx_cfg449_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg450 {
@@ -1064,6 +1112,8 @@ union cvmx_pciercx_cfg450 {
         struct cvmx_pciercx_cfg450_s cn52xxp1;
         struct cvmx_pciercx_cfg450_s cn56xx;
         struct cvmx_pciercx_cfg450_s cn56xxp1;
+        struct cvmx_pciercx_cfg450_s cn63xx;
+        struct cvmx_pciercx_cfg450_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg451 {
@@ -1080,6 +1130,8 @@ union cvmx_pciercx_cfg451 {
         struct cvmx_pciercx_cfg451_s cn52xxp1;
         struct cvmx_pciercx_cfg451_s cn56xx;
         struct cvmx_pciercx_cfg451_s cn56xxp1;
+        struct cvmx_pciercx_cfg451_s cn63xx;
+        struct cvmx_pciercx_cfg451_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg452 {
@@ -1103,6 +1155,8 @@ union cvmx_pciercx_cfg452 {
         struct cvmx_pciercx_cfg452_s cn52xxp1;
         struct cvmx_pciercx_cfg452_s cn56xx;
         struct cvmx_pciercx_cfg452_s cn56xxp1;
+        struct cvmx_pciercx_cfg452_s cn63xx;
+        struct cvmx_pciercx_cfg452_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg453 {
@@ -1118,6 +1172,8 @@ union cvmx_pciercx_cfg453 {
         struct cvmx_pciercx_cfg453_s cn52xxp1;
         struct cvmx_pciercx_cfg453_s cn56xx;
         struct cvmx_pciercx_cfg453_s cn56xxp1;
+        struct cvmx_pciercx_cfg453_s cn63xx;
+        struct cvmx_pciercx_cfg453_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg454 {
@@ -1136,6 +1192,8 @@ union cvmx_pciercx_cfg454 {
         struct cvmx_pciercx_cfg454_s cn52xxp1;
         struct cvmx_pciercx_cfg454_s cn56xx;
         struct cvmx_pciercx_cfg454_s cn56xxp1;
+        struct cvmx_pciercx_cfg454_s cn63xx;
+        struct cvmx_pciercx_cfg454_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg455 {
@@ -1165,6 +1223,8 @@ union cvmx_pciercx_cfg455 {
         struct cvmx_pciercx_cfg455_s cn52xxp1;
         struct cvmx_pciercx_cfg455_s cn56xx;
         struct cvmx_pciercx_cfg455_s cn56xxp1;
+        struct cvmx_pciercx_cfg455_s cn63xx;
+        struct cvmx_pciercx_cfg455_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg456 {
@@ -1178,6 +1238,8 @@ union cvmx_pciercx_cfg456 {
         struct cvmx_pciercx_cfg456_s cn52xxp1;
         struct cvmx_pciercx_cfg456_s cn56xx;
         struct cvmx_pciercx_cfg456_s cn56xxp1;
+        struct cvmx_pciercx_cfg456_s cn63xx;
+        struct cvmx_pciercx_cfg456_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg458 {
@@ -1189,6 +1251,8 @@ union cvmx_pciercx_cfg458 {
         struct cvmx_pciercx_cfg458_s cn52xxp1;
         struct cvmx_pciercx_cfg458_s cn56xx;
         struct cvmx_pciercx_cfg458_s cn56xxp1;
+        struct cvmx_pciercx_cfg458_s cn63xx;
+        struct cvmx_pciercx_cfg458_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg459 {
@@ -1200,6 +1264,8 @@ union cvmx_pciercx_cfg459 {
         struct cvmx_pciercx_cfg459_s cn52xxp1;
         struct cvmx_pciercx_cfg459_s cn56xx;
         struct cvmx_pciercx_cfg459_s cn56xxp1;
+        struct cvmx_pciercx_cfg459_s cn63xx;
+        struct cvmx_pciercx_cfg459_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg460 {
@@ -1213,6 +1279,8 @@ union cvmx_pciercx_cfg460 {
         struct cvmx_pciercx_cfg460_s cn52xxp1;
         struct cvmx_pciercx_cfg460_s cn56xx;
         struct cvmx_pciercx_cfg460_s cn56xxp1;
+        struct cvmx_pciercx_cfg460_s cn63xx;
+        struct cvmx_pciercx_cfg460_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg461 {
@@ -1226,6 +1294,8 @@ union cvmx_pciercx_cfg461 {
         struct cvmx_pciercx_cfg461_s cn52xxp1;
         struct cvmx_pciercx_cfg461_s cn56xx;
         struct cvmx_pciercx_cfg461_s cn56xxp1;
+        struct cvmx_pciercx_cfg461_s cn63xx;
+        struct cvmx_pciercx_cfg461_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg462 {
@@ -1239,6 +1309,8 @@ union cvmx_pciercx_cfg462 {
         struct cvmx_pciercx_cfg462_s cn52xxp1;
         struct cvmx_pciercx_cfg462_s cn56xx;
         struct cvmx_pciercx_cfg462_s cn56xxp1;
+        struct cvmx_pciercx_cfg462_s cn63xx;
+        struct cvmx_pciercx_cfg462_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg463 {
@@ -1253,6 +1325,8 @@ union cvmx_pciercx_cfg463 {
         struct cvmx_pciercx_cfg463_s cn52xxp1;
         struct cvmx_pciercx_cfg463_s cn56xx;
         struct cvmx_pciercx_cfg463_s cn56xxp1;
+        struct cvmx_pciercx_cfg463_s cn63xx;
+        struct cvmx_pciercx_cfg463_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg464 {
@@ -1267,6 +1341,8 @@ union cvmx_pciercx_cfg464 {
         struct cvmx_pciercx_cfg464_s cn52xxp1;
         struct cvmx_pciercx_cfg464_s cn56xx;
         struct cvmx_pciercx_cfg464_s cn56xxp1;
+        struct cvmx_pciercx_cfg464_s cn63xx;
+        struct cvmx_pciercx_cfg464_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg465 {
@@ -1281,6 +1357,8 @@ union cvmx_pciercx_cfg465 {
         struct cvmx_pciercx_cfg465_s cn52xxp1;
         struct cvmx_pciercx_cfg465_s cn56xx;
         struct cvmx_pciercx_cfg465_s cn56xxp1;
+        struct cvmx_pciercx_cfg465_s cn63xx;
+        struct cvmx_pciercx_cfg465_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg466 {
@@ -1298,6 +1376,8 @@ union cvmx_pciercx_cfg466 {
         struct cvmx_pciercx_cfg466_s cn52xxp1;
         struct cvmx_pciercx_cfg466_s cn56xx;
         struct cvmx_pciercx_cfg466_s cn56xxp1;
+        struct cvmx_pciercx_cfg466_s cn63xx;
+        struct cvmx_pciercx_cfg466_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg467 {
@@ -1313,6 +1393,8 @@ union cvmx_pciercx_cfg467 {
         struct cvmx_pciercx_cfg467_s cn52xxp1;
         struct cvmx_pciercx_cfg467_s cn56xx;
         struct cvmx_pciercx_cfg467_s cn56xxp1;
+        struct cvmx_pciercx_cfg467_s cn63xx;
+        struct cvmx_pciercx_cfg467_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg468 {
@@ -1328,6 +1410,8 @@ union cvmx_pciercx_cfg468 {
         struct cvmx_pciercx_cfg468_s cn52xxp1;
         struct cvmx_pciercx_cfg468_s cn56xx;
         struct cvmx_pciercx_cfg468_s cn56xxp1;
+        struct cvmx_pciercx_cfg468_s cn63xx;
+        struct cvmx_pciercx_cfg468_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg490 {
@@ -1342,6 +1426,8 @@ union cvmx_pciercx_cfg490 {
         struct cvmx_pciercx_cfg490_s cn52xxp1;
         struct cvmx_pciercx_cfg490_s cn56xx;
         struct cvmx_pciercx_cfg490_s cn56xxp1;
+        struct cvmx_pciercx_cfg490_s cn63xx;
+        struct cvmx_pciercx_cfg490_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg491 {
@@ -1356,6 +1442,8 @@ union cvmx_pciercx_cfg491 {
         struct cvmx_pciercx_cfg491_s cn52xxp1;
         struct cvmx_pciercx_cfg491_s cn56xx;
         struct cvmx_pciercx_cfg491_s cn56xxp1;
+        struct cvmx_pciercx_cfg491_s cn63xx;
+        struct cvmx_pciercx_cfg491_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg492 {
@@ -1370,6 +1458,23 @@ union cvmx_pciercx_cfg492 {
         struct cvmx_pciercx_cfg492_s cn52xxp1;
         struct cvmx_pciercx_cfg492_s cn56xx;
         struct cvmx_pciercx_cfg492_s cn56xxp1;
+        struct cvmx_pciercx_cfg492_s cn63xx;
+        struct cvmx_pciercx_cfg492_s cn63xxp1;
+};
+
+union cvmx_pciercx_cfg515 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg515_s {
+                uint32_t reserved_21_31:11;
+                uint32_t s_d_e:1;
+                uint32_t ctcrb:1;
+                uint32_t cpyts:1;
+                uint32_t dsc:1;
+                uint32_t le:9;
+                uint32_t n_fts:8;
+        } s;
+        struct cvmx_pciercx_cfg515_s cn63xx;
+        struct cvmx_pciercx_cfg515_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg516 {
@@ -1381,6 +1486,8 @@ union cvmx_pciercx_cfg516 {
         struct cvmx_pciercx_cfg516_s cn52xxp1;
         struct cvmx_pciercx_cfg516_s cn56xx;
         struct cvmx_pciercx_cfg516_s cn56xxp1;
+        struct cvmx_pciercx_cfg516_s cn63xx;
+        struct cvmx_pciercx_cfg516_s cn63xxp1;
 };
 
 union cvmx_pciercx_cfg517 {
@@ -1392,6 +1499,8 @@ union cvmx_pciercx_cfg517 {
         struct cvmx_pciercx_cfg517_s cn52xxp1;
         struct cvmx_pciercx_cfg517_s cn56xx;
         struct cvmx_pciercx_cfg517_s cn56xxp1;
+        struct cvmx_pciercx_cfg517_s cn63xx;
+        struct cvmx_pciercx_cfg517_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
index f40cfaf84454..aef84851a94c 100644
--- a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,38 +28,22 @@
 #ifndef __CVMX_PESCX_DEFS_H__
 #define __CVMX_PESCX_DEFS_H__
 
-#define CVMX_PESCX_BIST_STATUS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_BIST_STATUS2(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_RD(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CFG_WR(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_CTL_STATUS2(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DBG_INFO_EN(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_DIAG_STATUS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR0_START(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR1_START(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2N_BAR2_START(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
-#define CVMX_PESCX_TLP_CREDITS(block_id) \
-         CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
+#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
+#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
 
 union cvmx_pescx_bist_status {
         uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ea5dc571b54..5ab8679d89af 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -35,195 +35,191 @@
 #ifndef __CVMX_PEXP_DEFS_H__
 #define __CVMX_PEXP_DEFS_H__
 
-#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F0000008580ull)
-#define CVMX_PEXP_NPEI_BIST_STATUS2 \
-         CVMX_ADD_IO_SEG(0x00011F0000008680ull)
-#define CVMX_PEXP_NPEI_CTL_PORT0 \
-         CVMX_ADD_IO_SEG(0x00011F0000008250ull)
-#define CVMX_PEXP_NPEI_CTL_PORT1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008260ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x00011F0000008570ull)
-#define CVMX_PEXP_NPEI_CTL_STATUS2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
-#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
-         CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
-#define CVMX_PEXP_NPEI_DBG_DATA \
-         CVMX_ADD_IO_SEG(0x00011F0000008510ull)
-#define CVMX_PEXP_NPEI_DBG_SELECT \
-         CVMX_ADD_IO_SEG(0x00011F0000008500ull)
-#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
-         CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
-#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
-         CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
-#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
-#define CVMX_PEXP_NPEI_DMA_CNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
-#define CVMX_PEXP_NPEI_DMA_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000008560ull)
-#define CVMX_PEXP_NPEI_INT_A_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
-#define CVMX_PEXP_NPEI_INT_A_SUM \
-         CVMX_ADD_IO_SEG(0x00011F0000008550ull)
-#define CVMX_PEXP_NPEI_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000008540ull)
-#define CVMX_PEXP_NPEI_INT_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
-#define CVMX_PEXP_NPEI_INT_INFO \
-         CVMX_ADD_IO_SEG(0x00011F0000008590ull)
-#define CVMX_PEXP_NPEI_INT_SUM \
-         CVMX_ADD_IO_SEG(0x00011F0000008530ull)
-#define CVMX_PEXP_NPEI_INT_SUM2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
-         CVMX_ADD_IO_SEG(0x00011F0000008600ull)
-#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008610ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
-         CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
-#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
-#define CVMX_PEXP_NPEI_MSI_ENB0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
-#define CVMX_PEXP_NPEI_MSI_ENB1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
-#define CVMX_PEXP_NPEI_MSI_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
-#define CVMX_PEXP_NPEI_MSI_ENB3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
-#define CVMX_PEXP_NPEI_MSI_RCV0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
-#define CVMX_PEXP_NPEI_MSI_RCV1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
-#define CVMX_PEXP_NPEI_MSI_RCV2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
-#define CVMX_PEXP_NPEI_MSI_RCV3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
-#define CVMX_PEXP_NPEI_MSI_RD_MAP \
-         CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
-#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
-#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
-         CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
-#define CVMX_PEXP_NPEI_MSI_WR_MAP \
-         CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
-#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
-         CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
-         CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008650ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
-         CVMX_ADD_IO_SEG(0x00011F0000008660ull)
-#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
-         CVMX_ADD_IO_SEG(0x00011F0000008670ull)
-#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
-         CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_CNT_INT \
-         CVMX_ADD_IO_SEG(0x00011F0000009110ull)
-#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009130ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
-         CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
-         CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
-#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
-         CVMX_ADD_IO_SEG(0x00011F0000009090ull)
-#define CVMX_PEXP_NPEI_PKT_DPADDR \
-         CVMX_ADD_IO_SEG(0x00011F0000009080ull)
-#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
-         CVMX_ADD_IO_SEG(0x00011F0000009150ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009000ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F0000009190ull)
-#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F0000009020ull)
-#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
-         CVMX_ADD_IO_SEG(0x00011F0000009100ull)
-#define CVMX_PEXP_NPEI_PKT_IN_BP \
-         CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
-         CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
-#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
-         CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
-#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
-         CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
-#define CVMX_PEXP_NPEI_PKT_IPTR \
-         CVMX_ADD_IO_SEG(0x00011F0000009070ull)
-#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
-         CVMX_ADD_IO_SEG(0x00011F0000009160ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
-         CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
-#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009010ull)
-#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
-         CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
-#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
-         CVMX_ADD_IO_SEG(0x00011F0000008690ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
-         CVMX_ADD_IO_SEG(0x00011F0000009050ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
-         CVMX_ADD_IO_SEG(0x00011F0000009180ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
-         CVMX_ADD_IO_SEG(0x00011F0000009040ull)
-#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
-         CVMX_ADD_IO_SEG(0x00011F0000009030ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT \
-         CVMX_ADD_IO_SEG(0x00011F0000009120ull)
-#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
-         CVMX_ADD_IO_SEG(0x00011F0000009140ull)
-#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
-         CVMX_ADD_IO_SEG(0x00011F0000008520ull)
-#define CVMX_PEXP_NPEI_SCRATCH_1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008270ull)
-#define CVMX_PEXP_NPEI_STATE1 \
-         CVMX_ADD_IO_SEG(0x00011F0000008620ull)
-#define CVMX_PEXP_NPEI_STATE2 \
-         CVMX_ADD_IO_SEG(0x00011F0000008630ull)
-#define CVMX_PEXP_NPEI_STATE3 \
-         CVMX_ADD_IO_SEG(0x00011F0000008640ull)
-#define CVMX_PEXP_NPEI_WINDOW_CTL \
-         CVMX_ADD_IO_SEG(0x00011F0000008380ull)
+#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
+#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
+#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
+#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
+#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
+#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
+#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
+#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
+#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
+#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
+#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
+#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
+#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
+#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
+#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
+#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
+#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
+#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
+#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
+#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
+#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
+#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
+#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
+#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
+#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
+#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
+#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
+#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
+#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
+#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
+#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
+#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
+#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
+#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
+#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
+#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
+#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
+#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
+#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
+#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
+#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
+#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
+#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
+#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
+#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
+#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
+#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
+#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
+#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
+#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
+#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
+#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
+#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
+#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
+#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
+#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
+#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
+#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
+#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
+#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
+#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
+#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
+#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
+#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
+#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
+#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
+#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
+#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
+#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
+#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
+#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
+#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
+#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
+#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
+#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
+#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
+#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
index 2d82e24be51c..39fd75b03f77 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,29 @@
 #ifndef __CVMX_POW_DEFS_H__
 #define __CVMX_POW_DEFS_H__
 
-#define CVMX_POW_BIST_STAT \
-         CVMX_ADD_IO_SEG(0x00016700000003F8ull)
-#define CVMX_POW_DS_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000398ull)
-#define CVMX_POW_ECC_ERR \
-         CVMX_ADD_IO_SEG(0x0001670000000218ull)
-#define CVMX_POW_INT_CTL \
-         CVMX_ADD_IO_SEG(0x0001670000000220ull)
-#define CVMX_POW_IQ_CNTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8))
-#define CVMX_POW_IQ_COM_CNT \
-         CVMX_ADD_IO_SEG(0x0001670000000388ull)
-#define CVMX_POW_IQ_INT \
-         CVMX_ADD_IO_SEG(0x0001670000000238ull)
-#define CVMX_POW_IQ_INT_EN \
-         CVMX_ADD_IO_SEG(0x0001670000000240ull)
-#define CVMX_POW_IQ_THRX(offset) \
-         CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8))
-#define CVMX_POW_NOS_CNT \
-         CVMX_ADD_IO_SEG(0x0001670000000228ull)
-#define CVMX_POW_NW_TIM \
-         CVMX_ADD_IO_SEG(0x0001670000000210ull)
-#define CVMX_POW_PF_RST_MSK \
-         CVMX_ADD_IO_SEG(0x0001670000000230ull)
-#define CVMX_POW_PP_GRP_MSKX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
-#define CVMX_POW_QOS_RNDX(offset) \
-         CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
-#define CVMX_POW_QOS_THRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
-#define CVMX_POW_TS_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000390ull)
-#define CVMX_POW_WA_COM_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000380ull)
-#define CVMX_POW_WA_PCX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
-#define CVMX_POW_WQ_INT \
-         CVMX_ADD_IO_SEG(0x0001670000000200ull)
-#define CVMX_POW_WQ_INT_CNTX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
-#define CVMX_POW_WQ_INT_PC \
-         CVMX_ADD_IO_SEG(0x0001670000000208ull)
-#define CVMX_POW_WQ_INT_THRX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
-#define CVMX_POW_WS_PCX(offset) \
-         CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
+#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
+#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
+#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
+#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
+#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
+#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
+#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
+#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
+#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
+#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
+#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
+#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
+#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
+#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
+#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
+#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
+#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
+#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
+#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
+#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
+#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
 
 union cvmx_pow_bist_stat {
         uint64_t u64;
@@ -160,6 +137,19 @@ union cvmx_pow_bist_stat {
         struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
         struct cvmx_pow_bist_stat_cn38xx cn58xx;
         struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
+        struct cvmx_pow_bist_stat_cn63xx {
+                uint64_t reserved_22_63:42;
+                uint64_t pp:6;
+                uint64_t reserved_12_15:4;
+                uint64_t cam:1;
+                uint64_t nbr:3;
+                uint64_t nbt:4;
+                uint64_t index:1;
+                uint64_t fidx:1;
+                uint64_t pend:1;
+                uint64_t adr:1;
+        } cn63xx;
+        struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_ds_pc {
@@ -179,6 +169,8 @@ union cvmx_pow_ds_pc {
         struct cvmx_pow_ds_pc_s cn56xxp1;
         struct cvmx_pow_ds_pc_s cn58xx;
         struct cvmx_pow_ds_pc_s cn58xxp1;
+        struct cvmx_pow_ds_pc_s cn63xx;
+        struct cvmx_pow_ds_pc_s cn63xxp1;
 };
 
 union cvmx_pow_ecc_err {
@@ -219,6 +211,8 @@ union cvmx_pow_ecc_err {
         struct cvmx_pow_ecc_err_s cn56xxp1;
         struct cvmx_pow_ecc_err_s cn58xx;
         struct cvmx_pow_ecc_err_s cn58xxp1;
+        struct cvmx_pow_ecc_err_s cn63xx;
+        struct cvmx_pow_ecc_err_s cn63xxp1;
 };
 
 union cvmx_pow_int_ctl {
@@ -239,6 +233,8 @@ union cvmx_pow_int_ctl {
         struct cvmx_pow_int_ctl_s cn56xxp1;
         struct cvmx_pow_int_ctl_s cn58xx;
         struct cvmx_pow_int_ctl_s cn58xxp1;
+        struct cvmx_pow_int_ctl_s cn63xx;
+        struct cvmx_pow_int_ctl_s cn63xxp1;
 };
 
 union cvmx_pow_iq_cntx {
@@ -258,6 +254,8 @@ union cvmx_pow_iq_cntx {
         struct cvmx_pow_iq_cntx_s cn56xxp1;
         struct cvmx_pow_iq_cntx_s cn58xx;
         struct cvmx_pow_iq_cntx_s cn58xxp1;
+        struct cvmx_pow_iq_cntx_s cn63xx;
+        struct cvmx_pow_iq_cntx_s cn63xxp1;
 };
 
 union cvmx_pow_iq_com_cnt {
@@ -277,6 +275,8 @@ union cvmx_pow_iq_com_cnt {
         struct cvmx_pow_iq_com_cnt_s cn56xxp1;
         struct cvmx_pow_iq_com_cnt_s cn58xx;
         struct cvmx_pow_iq_com_cnt_s cn58xxp1;
+        struct cvmx_pow_iq_com_cnt_s cn63xx;
+        struct cvmx_pow_iq_com_cnt_s cn63xxp1;
 };
 
 union cvmx_pow_iq_int {
@@ -289,6 +289,8 @@ union cvmx_pow_iq_int {
         struct cvmx_pow_iq_int_s cn52xxp1;
         struct cvmx_pow_iq_int_s cn56xx;
         struct cvmx_pow_iq_int_s cn56xxp1;
+        struct cvmx_pow_iq_int_s cn63xx;
+        struct cvmx_pow_iq_int_s cn63xxp1;
 };
 
 union cvmx_pow_iq_int_en {
@@ -301,6 +303,8 @@ union cvmx_pow_iq_int_en {
         struct cvmx_pow_iq_int_en_s cn52xxp1;
         struct cvmx_pow_iq_int_en_s cn56xx;
         struct cvmx_pow_iq_int_en_s cn56xxp1;
+        struct cvmx_pow_iq_int_en_s cn63xx;
+        struct cvmx_pow_iq_int_en_s cn63xxp1;
 };
 
 union cvmx_pow_iq_thrx {
@@ -313,6 +317,8 @@ union cvmx_pow_iq_thrx {
         struct cvmx_pow_iq_thrx_s cn52xxp1;
         struct cvmx_pow_iq_thrx_s cn56xx;
         struct cvmx_pow_iq_thrx_s cn56xxp1;
+        struct cvmx_pow_iq_thrx_s cn63xx;
+        struct cvmx_pow_iq_thrx_s cn63xxp1;
 };
 
 union cvmx_pow_nos_cnt {
@@ -341,6 +347,11 @@ union cvmx_pow_nos_cnt {
         struct cvmx_pow_nos_cnt_s cn56xxp1;
         struct cvmx_pow_nos_cnt_s cn58xx;
         struct cvmx_pow_nos_cnt_s cn58xxp1;
+        struct cvmx_pow_nos_cnt_cn63xx {
+                uint64_t reserved_11_63:53;
+                uint64_t nos_cnt:11;
+        } cn63xx;
+        struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_nw_tim {
@@ -360,6 +371,8 @@ union cvmx_pow_nw_tim {
         struct cvmx_pow_nw_tim_s cn56xxp1;
         struct cvmx_pow_nw_tim_s cn58xx;
         struct cvmx_pow_nw_tim_s cn58xxp1;
+        struct cvmx_pow_nw_tim_s cn63xx;
+        struct cvmx_pow_nw_tim_s cn63xxp1;
 };
 
 union cvmx_pow_pf_rst_msk {
@@ -375,6 +388,8 @@ union cvmx_pow_pf_rst_msk {
         struct cvmx_pow_pf_rst_msk_s cn56xxp1;
         struct cvmx_pow_pf_rst_msk_s cn58xx;
         struct cvmx_pow_pf_rst_msk_s cn58xxp1;
+        struct cvmx_pow_pf_rst_msk_s cn63xx;
+        struct cvmx_pow_pf_rst_msk_s cn63xxp1;
 };
 
 union cvmx_pow_pp_grp_mskx {
@@ -405,6 +420,8 @@ union cvmx_pow_pp_grp_mskx {
         struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
         struct cvmx_pow_pp_grp_mskx_s cn58xx;
         struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
+        struct cvmx_pow_pp_grp_mskx_s cn63xx;
+        struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
 };
 
 union cvmx_pow_qos_rndx {
@@ -427,6 +444,8 @@ union cvmx_pow_qos_rndx {
         struct cvmx_pow_qos_rndx_s cn56xxp1;
         struct cvmx_pow_qos_rndx_s cn58xx;
         struct cvmx_pow_qos_rndx_s cn58xxp1;
+        struct cvmx_pow_qos_rndx_s cn63xx;
+        struct cvmx_pow_qos_rndx_s cn63xxp1;
 };
 
 union cvmx_pow_qos_thrx {
@@ -485,6 +504,19 @@ union cvmx_pow_qos_thrx {
         struct cvmx_pow_qos_thrx_s cn56xxp1;
         struct cvmx_pow_qos_thrx_s cn58xx;
         struct cvmx_pow_qos_thrx_s cn58xxp1;
+        struct cvmx_pow_qos_thrx_cn63xx {
+                uint64_t reserved_59_63:5;
+                uint64_t des_cnt:11;
+                uint64_t reserved_47_47:1;
+                uint64_t buf_cnt:11;
+                uint64_t reserved_35_35:1;
+                uint64_t free_cnt:11;
+                uint64_t reserved_22_23:2;
+                uint64_t max_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t min_thr:10;
+        } cn63xx;
+        struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_ts_pc {
@@ -504,6 +536,8 @@ union cvmx_pow_ts_pc {
         struct cvmx_pow_ts_pc_s cn56xxp1;
         struct cvmx_pow_ts_pc_s cn58xx;
         struct cvmx_pow_ts_pc_s cn58xxp1;
+        struct cvmx_pow_ts_pc_s cn63xx;
+        struct cvmx_pow_ts_pc_s cn63xxp1;
 };
 
 union cvmx_pow_wa_com_pc {
@@ -523,6 +557,8 @@ union cvmx_pow_wa_com_pc {
         struct cvmx_pow_wa_com_pc_s cn56xxp1;
         struct cvmx_pow_wa_com_pc_s cn58xx;
         struct cvmx_pow_wa_com_pc_s cn58xxp1;
+        struct cvmx_pow_wa_com_pc_s cn63xx;
+        struct cvmx_pow_wa_com_pc_s cn63xxp1;
 };
 
 union cvmx_pow_wa_pcx {
@@ -542,6 +578,8 @@ union cvmx_pow_wa_pcx {
         struct cvmx_pow_wa_pcx_s cn56xxp1;
         struct cvmx_pow_wa_pcx_s cn58xx;
         struct cvmx_pow_wa_pcx_s cn58xxp1;
+        struct cvmx_pow_wa_pcx_s cn63xx;
+        struct cvmx_pow_wa_pcx_s cn63xxp1;
 };
 
 union cvmx_pow_wq_int {
@@ -562,6 +600,8 @@ union cvmx_pow_wq_int {
         struct cvmx_pow_wq_int_s cn56xxp1;
         struct cvmx_pow_wq_int_s cn58xx;
         struct cvmx_pow_wq_int_s cn58xxp1;
+        struct cvmx_pow_wq_int_s cn63xx;
+        struct cvmx_pow_wq_int_s cn63xxp1;
 };
 
 union cvmx_pow_wq_int_cntx {
@@ -604,6 +644,15 @@ union cvmx_pow_wq_int_cntx {
         struct cvmx_pow_wq_int_cntx_s cn56xxp1;
         struct cvmx_pow_wq_int_cntx_s cn58xx;
         struct cvmx_pow_wq_int_cntx_s cn58xxp1;
+        struct cvmx_pow_wq_int_cntx_cn63xx {
+                uint64_t reserved_28_63:36;
+                uint64_t tc_cnt:4;
+                uint64_t reserved_23_23:1;
+                uint64_t ds_cnt:11;
+                uint64_t reserved_11_11:1;
+                uint64_t iq_cnt:11;
+        } cn63xx;
+        struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_wq_int_pc {
@@ -626,6 +675,8 @@ union cvmx_pow_wq_int_pc {
         struct cvmx_pow_wq_int_pc_s cn56xxp1;
         struct cvmx_pow_wq_int_pc_s cn58xx;
         struct cvmx_pow_wq_int_pc_s cn58xxp1;
+        struct cvmx_pow_wq_int_pc_s cn63xx;
+        struct cvmx_pow_wq_int_pc_s cn63xxp1;
 };
 
 union cvmx_pow_wq_int_thrx {
@@ -674,6 +725,16 @@ union cvmx_pow_wq_int_thrx {
         struct cvmx_pow_wq_int_thrx_s cn56xxp1;
         struct cvmx_pow_wq_int_thrx_s cn58xx;
         struct cvmx_pow_wq_int_thrx_s cn58xxp1;
+        struct cvmx_pow_wq_int_thrx_cn63xx {
+                uint64_t reserved_29_63:35;
+                uint64_t tc_en:1;
+                uint64_t tc_thr:4;
+                uint64_t reserved_22_23:2;
+                uint64_t ds_thr:10;
+                uint64_t reserved_10_11:2;
+                uint64_t iq_thr:10;
+        } cn63xx;
+        struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
 };
 
 union cvmx_pow_ws_pcx {
@@ -693,6 +754,8 @@ union cvmx_pow_ws_pcx {
         struct cvmx_pow_ws_pcx_s cn56xxp1;
         struct cvmx_pow_ws_pcx_s cn58xx;
         struct cvmx_pow_ws_pcx_s cn58xxp1;
+        struct cvmx_pow_ws_pcx_s cn63xx;
+        struct cvmx_pow_ws_pcx_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
index 4586958c97be..c45da1f35ea7 100644
--- a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -30,10 +30,11 @@
 
 #include <linux/types.h>
 
-#define CVMX_RNM_BIST_STATUS \
-         CVMX_ADD_IO_SEG(0x0001180040000008ull)
-#define CVMX_RNM_CTL_STATUS \
-         CVMX_ADD_IO_SEG(0x0001180040000000ull)
+#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
+#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
+#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
+#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
+#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
 
 union cvmx_rnm_bist_status {
         uint64_t u64;
@@ -53,12 +54,16 @@ union cvmx_rnm_bist_status {
         struct cvmx_rnm_bist_status_s cn56xxp1;
         struct cvmx_rnm_bist_status_s cn58xx;
         struct cvmx_rnm_bist_status_s cn58xxp1;
+        struct cvmx_rnm_bist_status_s cn63xx;
+        struct cvmx_rnm_bist_status_s cn63xxp1;
 };
 
 union cvmx_rnm_ctl_status {
         uint64_t u64;
         struct cvmx_rnm_ctl_status_s {
-                uint64_t reserved_9_63:55;
+                uint64_t reserved_11_63:53;
+                uint64_t eer_lck:1;
+                uint64_t eer_val:1;
                 uint64_t ent_sel:4;
                 uint64_t exp_ent:1;
                 uint64_t rng_rst:1;
@@ -76,13 +81,49 @@ union cvmx_rnm_ctl_status {
         struct cvmx_rnm_ctl_status_cn30xx cn31xx;
         struct cvmx_rnm_ctl_status_cn30xx cn38xx;
         struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
-        struct cvmx_rnm_ctl_status_s cn50xx;
-        struct cvmx_rnm_ctl_status_s cn52xx;
-        struct cvmx_rnm_ctl_status_s cn52xxp1;
-        struct cvmx_rnm_ctl_status_s cn56xx;
-        struct cvmx_rnm_ctl_status_s cn56xxp1;
-        struct cvmx_rnm_ctl_status_s cn58xx;
-        struct cvmx_rnm_ctl_status_s cn58xxp1;
+        struct cvmx_rnm_ctl_status_cn50xx {
+                uint64_t reserved_9_63:55;
+                uint64_t ent_sel:4;
+                uint64_t exp_ent:1;
+                uint64_t rng_rst:1;
+                uint64_t rnm_rst:1;
+                uint64_t rng_en:1;
+                uint64_t ent_en:1;
+        } cn50xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn52xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
+        struct cvmx_rnm_ctl_status_cn50xx cn56xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
+        struct cvmx_rnm_ctl_status_cn50xx cn58xx;
+        struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
+        struct cvmx_rnm_ctl_status_s cn63xx;
+        struct cvmx_rnm_ctl_status_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_dbg {
+        uint64_t u64;
+        struct cvmx_rnm_eer_dbg_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_rnm_eer_dbg_s cn63xx;
+        struct cvmx_rnm_eer_dbg_s cn63xxp1;
+};
+
+union cvmx_rnm_eer_key {
+        uint64_t u64;
+        struct cvmx_rnm_eer_key_s {
+                uint64_t key:64;
+        } s;
+        struct cvmx_rnm_eer_key_s cn63xx;
+        struct cvmx_rnm_eer_key_s cn63xxp1;
+};
+
+union cvmx_rnm_serial_num {
+        uint64_t u64;
+        struct cvmx_rnm_serial_num_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_rnm_serial_num_s cn63xx;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
index 9ae45fcbe3e3..4f3c0666e94a 100644
--- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2008 Cavium Networks
+ * Copyright (c) 2003-2010 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,16 +28,11 @@
 #ifndef __CVMX_SMIX_DEFS_H__
 #define __CVMX_SMIX_DEFS_H__
 
-#define CVMX_SMIX_CLK(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_CMD(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_EN(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_RD_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
-#define CVMX_SMIX_WR_DAT(offset) \
-         CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
+#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
 
 union cvmx_smix_clk {
         uint64_t u64;
@@ -56,7 +51,8 @@ union cvmx_smix_clk {
         struct cvmx_smix_clk_cn30xx {
                 uint64_t reserved_21_63:43;
                 uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
+                uint64_t sample_mode:1;
+                uint64_t reserved_14_14:1;
                 uint64_t clk_idle:1;
                 uint64_t preamble:1;
                 uint64_t sample:4;
@@ -65,23 +61,15 @@ union cvmx_smix_clk {
         struct cvmx_smix_clk_cn30xx cn31xx;
         struct cvmx_smix_clk_cn30xx cn38xx;
         struct cvmx_smix_clk_cn30xx cn38xxp2;
-        struct cvmx_smix_clk_cn50xx {
-                uint64_t reserved_25_63:39;
-                uint64_t mode:1;
-                uint64_t reserved_21_23:3;
-                uint64_t sample_hi:5;
-                uint64_t reserved_14_15:2;
-                uint64_t clk_idle:1;
-                uint64_t preamble:1;
-                uint64_t sample:4;
-                uint64_t phase:8;
-        } cn50xx;
+        struct cvmx_smix_clk_s cn50xx;
         struct cvmx_smix_clk_s cn52xx;
-        struct cvmx_smix_clk_cn50xx cn52xxp1;
+        struct cvmx_smix_clk_s cn52xxp1;
         struct cvmx_smix_clk_s cn56xx;
-        struct cvmx_smix_clk_cn50xx cn56xxp1;
+        struct cvmx_smix_clk_s cn56xxp1;
         struct cvmx_smix_clk_cn30xx cn58xx;
         struct cvmx_smix_clk_cn30xx cn58xxp1;
+        struct cvmx_smix_clk_s cn63xx;
+        struct cvmx_smix_clk_s cn63xxp1;
 };
 
 union cvmx_smix_cmd {
@@ -112,6 +100,8 @@ union cvmx_smix_cmd {
         struct cvmx_smix_cmd_s cn56xxp1;
         struct cvmx_smix_cmd_cn30xx cn58xx;
         struct cvmx_smix_cmd_cn30xx cn58xxp1;
+        struct cvmx_smix_cmd_s cn63xx;
+        struct cvmx_smix_cmd_s cn63xxp1;
 };
 
 union cvmx_smix_en {
@@ -131,6 +121,8 @@ union cvmx_smix_en {
         struct cvmx_smix_en_s cn56xxp1;
         struct cvmx_smix_en_s cn58xx;
         struct cvmx_smix_en_s cn58xxp1;
+        struct cvmx_smix_en_s cn63xx;
+        struct cvmx_smix_en_s cn63xxp1;
 };
 
 union cvmx_smix_rd_dat {
@@ -152,6 +144,8 @@ union cvmx_smix_rd_dat {
         struct cvmx_smix_rd_dat_s cn56xxp1;
         struct cvmx_smix_rd_dat_s cn58xx;
         struct cvmx_smix_rd_dat_s cn58xxp1;
+        struct cvmx_smix_rd_dat_s cn63xx;
+        struct cvmx_smix_rd_dat_s cn63xxp1;
 };
 
 union cvmx_smix_wr_dat {
@@ -173,6 +167,8 @@ union cvmx_smix_wr_dat {
         struct cvmx_smix_wr_dat_s cn56xxp1;
         struct cvmx_smix_wr_dat_s cn58xx;
         struct cvmx_smix_wr_dat_s cn58xxp1;
+        struct cvmx_smix_wr_dat_s cn63xx;
+        struct cvmx_smix_wr_dat_s cn63xxp1;
 };
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
new file mode 100644
index 000000000000..594f1b68cd62
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-uctlx-defs.h
@@ -0,0 +1,261 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2010 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_UCTLX_TYPEDEFS_H__
+#define __CVMX_UCTLX_TYPEDEFS_H__
+
+#define CVMX_UCTLX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A0ull))
+#define CVMX_UCTLX_CLK_RST_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000000ull))
+#define CVMX_UCTLX_EHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000080ull))
+#define CVMX_UCTLX_EHCI_FLA(block_id) (CVMX_ADD_IO_SEG(0x000118006F0000A8ull))
+#define CVMX_UCTLX_ERTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000090ull))
+#define CVMX_UCTLX_IF_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000030ull))
+#define CVMX_UCTLX_INT_ENA(block_id) (CVMX_ADD_IO_SEG(0x000118006F000028ull))
+#define CVMX_UCTLX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x000118006F000020ull))
+#define CVMX_UCTLX_OHCI_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000088ull))
+#define CVMX_UCTLX_ORTO_CTL(block_id) (CVMX_ADD_IO_SEG(0x000118006F000098ull))
+#define CVMX_UCTLX_PPAF_WM(block_id) (CVMX_ADD_IO_SEG(0x000118006F000038ull))
+#define CVMX_UCTLX_UPHY_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x000118006F000008ull))
+#define CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(offset, block_id) (CVMX_ADD_IO_SEG(0x000118006F000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
+
+union cvmx_uctlx_bist_status {
+        uint64_t u64;
+        struct cvmx_uctlx_bist_status_s {
+                uint64_t reserved_6_63:58;
+                uint64_t data_bis:1;
+                uint64_t desc_bis:1;
+                uint64_t erbm_bis:1;
+                uint64_t orbm_bis:1;
+                uint64_t wrbm_bis:1;
+                uint64_t ppaf_bis:1;
+        } s;
+        struct cvmx_uctlx_bist_status_s       cn63xx;
+        struct cvmx_uctlx_bist_status_s       cn63xxp1;
+};
+
+union cvmx_uctlx_clk_rst_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_clk_rst_ctl_s {
+                uint64_t reserved_25_63:39;
+                uint64_t clear_bist:1;
+                uint64_t start_bist:1;
+                uint64_t ehci_sm:1;
+                uint64_t ohci_clkcktrst:1;
+                uint64_t ohci_sm:1;
+                uint64_t ohci_susp_lgcy:1;
+                uint64_t app_start_clk:1;
+                uint64_t o_clkdiv_rst:1;
+                uint64_t h_clkdiv_byp:1;
+                uint64_t h_clkdiv_rst:1;
+                uint64_t h_clkdiv_en:1;
+                uint64_t o_clkdiv_en:1;
+                uint64_t h_div:4;
+                uint64_t p_refclk_sel:2;
+                uint64_t p_refclk_div:2;
+                uint64_t reserved_4_4:1;
+                uint64_t p_com_on:1;
+                uint64_t p_por:1;
+                uint64_t p_prst:1;
+                uint64_t hrst:1;
+        } s;
+        struct cvmx_uctlx_clk_rst_ctl_s       cn63xx;
+        struct cvmx_uctlx_clk_rst_ctl_s       cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_ehci_ctl_s {
+                uint64_t reserved_20_63:44;
+                uint64_t desc_rbm:1;
+                uint64_t reg_nb:1;
+                uint64_t l2c_dc:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_desc_emod:2;
+                uint64_t inv_reg_a2:1;
+                uint64_t ehci_64b_addr_en:1;
+                uint64_t l2c_addr_msb:8;
+        } s;
+        struct cvmx_uctlx_ehci_ctl_s          cn63xx;
+        struct cvmx_uctlx_ehci_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_ehci_fla {
+        uint64_t u64;
+        struct cvmx_uctlx_ehci_fla_s {
+                uint64_t reserved_6_63:58;
+                uint64_t fla:6;
+        } s;
+        struct cvmx_uctlx_ehci_fla_s          cn63xx;
+        struct cvmx_uctlx_ehci_fla_s          cn63xxp1;
+};
+
+union cvmx_uctlx_erto_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_erto_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t to_val:27;
+                uint64_t reserved_0_4:5;
+        } s;
+        struct cvmx_uctlx_erto_ctl_s          cn63xx;
+        struct cvmx_uctlx_erto_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_if_ena {
+        uint64_t u64;
+        struct cvmx_uctlx_if_ena_s {
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+        } s;
+        struct cvmx_uctlx_if_ena_s            cn63xx;
+        struct cvmx_uctlx_if_ena_s            cn63xxp1;
+};
+
+union cvmx_uctlx_int_ena {
+        uint64_t u64;
+        struct cvmx_uctlx_int_ena_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ec_ovf_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t wb_pop_e:1;
+                uint64_t wb_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t pp_psh_f:1;
+        } s;
+        struct cvmx_uctlx_int_ena_s           cn63xx;
+        struct cvmx_uctlx_int_ena_s           cn63xxp1;
+};
+
+union cvmx_uctlx_int_reg {
+        uint64_t u64;
+        struct cvmx_uctlx_int_reg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ec_ovf_e:1;
+                uint64_t oc_ovf_e:1;
+                uint64_t wb_pop_e:1;
+                uint64_t wb_psh_f:1;
+                uint64_t cf_psh_f:1;
+                uint64_t or_psh_f:1;
+                uint64_t er_psh_f:1;
+                uint64_t pp_psh_f:1;
+        } s;
+        struct cvmx_uctlx_int_reg_s           cn63xx;
+        struct cvmx_uctlx_int_reg_s           cn63xxp1;
+};
+
+union cvmx_uctlx_ohci_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_ohci_ctl_s {
+                uint64_t reserved_19_63:45;
+                uint64_t reg_nb:1;
+                uint64_t l2c_dc:1;
+                uint64_t l2c_bc:1;
+                uint64_t l2c_0pag:1;
+                uint64_t l2c_stt:1;
+                uint64_t l2c_buff_emod:2;
+                uint64_t l2c_desc_emod:2;
+                uint64_t inv_reg_a2:1;
+                uint64_t reserved_8_8:1;
+                uint64_t l2c_addr_msb:8;
+        } s;
+        struct cvmx_uctlx_ohci_ctl_s          cn63xx;
+        struct cvmx_uctlx_ohci_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_orto_ctl {
+        uint64_t u64;
+        struct cvmx_uctlx_orto_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t to_val:24;
+                uint64_t reserved_0_7:8;
+        } s;
+        struct cvmx_uctlx_orto_ctl_s          cn63xx;
+        struct cvmx_uctlx_orto_ctl_s          cn63xxp1;
+};
+
+union cvmx_uctlx_ppaf_wm {
+        uint64_t u64;
+        struct cvmx_uctlx_ppaf_wm_s {
+                uint64_t reserved_5_63:59;
+                uint64_t wm:5;
+        } s;
+        struct cvmx_uctlx_ppaf_wm_s           cn63xx;
+        struct cvmx_uctlx_ppaf_wm_s           cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_ctl_status {
+        uint64_t u64;
+        struct cvmx_uctlx_uphy_ctl_status_s {
+                uint64_t reserved_10_63:54;
+                uint64_t bist_done:1;
+                uint64_t bist_err:1;
+                uint64_t hsbist:1;
+                uint64_t fsbist:1;
+                uint64_t lsbist:1;
+                uint64_t siddq:1;
+                uint64_t vtest_en:1;
+                uint64_t uphy_bist:1;
+                uint64_t bist_en:1;
+                uint64_t ate_reset:1;
+        } s;
+        struct cvmx_uctlx_uphy_ctl_status_s   cn63xx;
+        struct cvmx_uctlx_uphy_ctl_status_s   cn63xxp1;
+};
+
+union cvmx_uctlx_uphy_portx_ctl_status {
+        uint64_t u64;
+        struct cvmx_uctlx_uphy_portx_ctl_status_s {
+                uint64_t reserved_43_63:21;
+                uint64_t tdata_out:4;
+                uint64_t txbiststuffenh:1;
+                uint64_t txbiststuffen:1;
+                uint64_t dmpulldown:1;
+                uint64_t dppulldown:1;
+                uint64_t vbusvldext:1;
+                uint64_t portreset:1;
+                uint64_t txhsvxtune:2;
+                uint64_t txvreftune:4;
+                uint64_t txrisetune:1;
+                uint64_t txpreemphasistune:1;
+                uint64_t txfslstune:4;
+                uint64_t sqrxtune:3;
+                uint64_t compdistune:3;
+                uint64_t loop_en:1;
+                uint64_t tclk:1;
+                uint64_t tdata_sel:1;
+                uint64_t taddr_in:4;
+                uint64_t tdata_in:8;
+        } s;
+        struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xx;
+        struct cvmx_uctlx_uphy_portx_ctl_status_s cn63xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index cf50336eca2e..700f88e31cad 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -35,14 +35,6 @@
 #ifndef __OCTEON_MODEL_H__
 #define __OCTEON_MODEL_H__
 
-/* NOTE: These must match what is checked in common-config.mk */
-/* Defines to represent the different versions of Octeon.  */
-
-/*
- * IMPORTANT: When the default pass is updated for an Octeon Model,
- * the corresponding change must also be made in the oct-sim script.
- */
-
 /*
  * The defines below should be used with the OCTEON_IS_MODEL() macro
  * to determine what model of chip the software is running on.  Models
@@ -71,6 +63,21 @@
 #define OM_IGNORE_MINOR_REVISION  0x08000000
 #define OM_FLAG_MASK              0xff000000
 
+#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000 /* Match all cn5XXX Octeon models. */
+#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000 /* Match all cn6XXX Octeon models. */
+
+/*
+ * CN6XXX models with new revision encoding
+ */
+#define OCTEON_CN63XX_PASS1_0   0x000d9000
+#define OCTEON_CN63XX_PASS1_1   0x000d9001
+#define OCTEON_CN63XX_PASS1_2   0x000d9002
+#define OCTEON_CN63XX_PASS2_0   0x000d9008
+
+#define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+
 /*
  * CN5XXX models with new revision encoding
  */
@@ -189,6 +196,9 @@
                                  | OM_MATCH_PREVIOUS_MODELS \
                                  | OM_IGNORE_REVISION)
 
+#define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
+#define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
+
 /* The revision byte (low byte) has two different encodings.
  * CN3XXX:
  *
@@ -222,6 +232,7 @@
                                       | OCTEON_58XX_MODEL_MASK)
 #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
                                           & 0x00fffff8)
+#define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
 
 #define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
 
@@ -273,6 +284,15 @@ static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
                     __OCTEON_MATCH_MASK__((chip_model), (arg_model),
                                           OCTEON_58XX_MODEL_REV_MASK))
                         return 1;
+
+                if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
+                    ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
+                        return 1;
+
+                if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
+                    ((chip_model) >= OCTEON_CN63XX_PASS1_0))
+                        return 1;
+
                 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
                     ((chip_model & OCTEON_58XX_MODEL_MASK) <
                             (arg_model & OCTEON_58XX_MODEL_MASK)))
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 917a6c413b1a..6b34afd0d4e7 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -35,6 +35,7 @@ extern int octeon_is_simulation(void);
 extern int octeon_is_pci_host(void);
 extern int octeon_usb_is_ref_clk(void);
 extern uint64_t octeon_get_clock_rate(void);
+extern u64 octeon_get_io_clock_rate(void);
 extern const char *octeon_board_type_string(void);
 extern const char *octeon_get_pci_interrupts(void);
 extern int octeon_get_southbridge_interrupt(void);
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index ece78043acf6..fba2ba200f58 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -36,6 +36,16 @@ extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
                                      u8 slot, u8 pin);
 
 /*
+ * For PCI (not PCIe) the BAR2 base address.
+ */
+#define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull
+
+/*
+ * For PCI (not PCIe) the base of the memory mapped by BAR1
+ */
+extern u64 octeon_bar1_pci_phys;
+
+/*
  * The following defines are used when octeon_dma_bar_type =
  * OCTEON_DMA_BAR_TYPE_BIG
  */
diff --git a/arch/mips/include/asm/perf_event.h b/arch/mips/include/asm/perf_event.h
new file mode 100644
index 000000000000..e00007cf8162
--- /dev/null
+++ b/arch/mips/include/asm/perf_event.h
@@ -0,0 +1,25 @@
+/*
+ * linux/arch/mips/include/asm/perf_event.h
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MIPS_PERF_EVENT_H__
+#define __MIPS_PERF_EVENT_H__
+
+/*
+ * MIPS performance counters do not raise NMI upon overflow, a regular
+ * interrupt will be signaled. Hence we can do the pending perf event
+ * work at the tail of the irq handler.
+ */
+static inline void
+set_perf_event_pending(void)
+{
+}
+
+#endif /* __MIPS_PERF_EVENT_H__ */
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index f00896087dda..55908fd56b1f 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -113,10 +113,10 @@
 #endif
 #define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
-#if PGDIR_SIZE >= TASK_SIZE
+#if PGDIR_SIZE >= TASK_SIZE64
 #define USER_PTRS_PER_PGD       (1)
 #else
-#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
+#define USER_PTRS_PER_PGD       (TASK_SIZE64 / PGDIR_SIZE)
 #endif
 #define FIRST_USER_ADDRESS      0UL
 
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 0d629bb93cbe..ead6928fa6b8 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -50,13 +50,10 @@ extern unsigned int vced_count, vcei_count;
  * so don't change it unless you know what you are doing.
  */
 #define TASK_SIZE       0x7fff8000UL
-#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
 
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
+#ifdef __KERNEL__
+#define STACK_TOP_MAX   TASK_SIZE
+#endif
 
 #define TASK_IS_32BIT_ADDR 1
 
@@ -71,28 +68,29 @@ extern unsigned int vced_count, vcei_count;
  * 8192EB ...
  */
 #define TASK_SIZE32     0x7fff8000UL
-#define TASK_SIZE       0x10000000000UL
-#define STACK_TOP       \
-        (((test_thread_flag(TIF_32BIT_ADDR) ?                           \
-           TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+#define TASK_SIZE64     0x10000000000UL
+#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
+
+#ifdef __KERNEL__
+#define STACK_TOP_MAX   TASK_SIZE64
+#endif
+
 
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE                                              \
-        (test_thread_flag(TIF_32BIT_ADDR) ?                             \
-                PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
 #define TASK_SIZE_OF(tsk)                                               \
-        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
+        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
 
 #define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
 
 #endif
 
-#ifdef __KERNEL__
-#define STACK_TOP_MAX   TASK_SIZE
-#endif
+#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
+
 
 #define NUM_FPU_REGS    32
 
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index bb937ccfba1e..6018c80ce37a 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -115,21 +115,19 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
         } else if (kernel_uses_llsc) {
                 unsigned long dummy;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %3                  # xchg_u32      \n"
-                "       .set    mips0                                   \n"
-                "       move    %2, %z4                                 \n"
-                "       .set    mips3                                   \n"
-                "       sc      %2, %1                                  \n"
-                "       beqz    %2, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %0, %3          # xchg_u32      \n"
+                        "       .set    mips0                           \n"
+                        "       move    %2, %z4                         \n"
+                        "       .set    mips3                           \n"
+                        "       sc      %2, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                        : "R" (*m), "Jr" (val)
+                        : "memory");
+                } while (unlikely(!dummy));
         } else {
                 unsigned long flags;
 
@@ -167,19 +165,17 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
         } else if (kernel_uses_llsc) {
                 unsigned long dummy;
 
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %3                  # xchg_u64      \n"
-                "       move    %2, %z4                                 \n"
-                "       scd     %2, %1                                  \n"
-                "       beqz    %2, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %0, %3          # xchg_u64      \n"
+                        "       move    %2, %z4                         \n"
+                        "       scd     %2, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                        : "R" (*m), "Jr" (val)
+                        : "memory");
+                } while (unlikely(!dummy));
         } else {
                 unsigned long flags;
 
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 70df9c0d3c5b..d309556cacf8 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -83,6 +83,8 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
 #define THREAD_MASK (THREAD_SIZE - 1UL)
 
+#define STACK_WARN      (THREAD_SIZE / 8)
+
 #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 
 #ifdef CONFIG_DEBUG_STACK_USAGE
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index c2d53c18fd36..653a412c036c 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -35,7 +35,9 @@
 
 #ifdef CONFIG_64BIT
 
-#define __UA_LIMIT      (- TASK_SIZE)
+extern u64 __ua_limit;
+
+#define __UA_LIMIT      __ua_limit
 
 #define __UA_ADDR       ".dword"
 #define __UA_LA         "dla"
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 80884983270d..22b2e0e38617 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -104,4 +104,6 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
 
 obj-$(CONFIG_MIPS_CPUFREQ)      += cpufreq/
 
+obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
+
 CPPFLAGS_vmlinux.lds            := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b1b304ea2128..71620e19827a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -25,6 +25,8 @@
 #include <asm/system.h>
 #include <asm/watch.h>
 #include <asm/spram.h>
+#include <asm/uaccess.h>
+
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  * the implementation of the "wait" feature differs between CPU families. This
@@ -181,12 +183,13 @@ void __init check_wait(void)
         case CPU_5KC:
         case CPU_25KF:
         case CPU_PR4450:
-        case CPU_BCM3302:
-        case CPU_BCM6338:
-        case CPU_BCM6348:
-        case CPU_BCM6358:
+        case CPU_BMIPS3300:
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+        case CPU_BMIPS5000:
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
+        case CPU_CAVIUM_OCTEON2:
         case CPU_JZRISC:
                 cpu_wait = r4k_wait;
                 break;
@@ -902,33 +905,37 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 {
         decode_configs(c);
         switch (c->processor_id & 0xff00) {
-        case PRID_IMP_BCM3302:
-         /* same as PRID_IMP_BCM6338 */
-                c->cputype = CPU_BCM3302;
-                __cpu_name[cpu] = "Broadcom BCM3302";
-                break;
-        case PRID_IMP_BCM4710:
-                c->cputype = CPU_BCM4710;
-                __cpu_name[cpu] = "Broadcom BCM4710";
-                break;
-        case PRID_IMP_BCM6345:
-                c->cputype = CPU_BCM6345;
-                __cpu_name[cpu] = "Broadcom BCM6345";
+        case PRID_IMP_BMIPS32:
+                c->cputype = CPU_BMIPS32;
+                __cpu_name[cpu] = "Broadcom BMIPS32";
+                break;
+        case PRID_IMP_BMIPS3300:
+        case PRID_IMP_BMIPS3300_ALT:
+        case PRID_IMP_BMIPS3300_BUG:
+                c->cputype = CPU_BMIPS3300;
+                __cpu_name[cpu] = "Broadcom BMIPS3300";
+                break;
+        case PRID_IMP_BMIPS43XX: {
+                int rev = c->processor_id & 0xff;
+
+                if (rev >= PRID_REV_BMIPS4380_LO &&
+                                rev <= PRID_REV_BMIPS4380_HI) {
+                        c->cputype = CPU_BMIPS4380;
+                        __cpu_name[cpu] = "Broadcom BMIPS4380";
+                } else {
+                        c->cputype = CPU_BMIPS4350;
+                        __cpu_name[cpu] = "Broadcom BMIPS4350";
+                }
                 break;
-        case PRID_IMP_BCM6348:
-                c->cputype = CPU_BCM6348;
-                __cpu_name[cpu] = "Broadcom BCM6348";
+        }
+        case PRID_IMP_BMIPS5000:
+                c->cputype = CPU_BMIPS5000;
+                __cpu_name[cpu] = "Broadcom BMIPS5000";
+                c->options |= MIPS_CPU_ULRI;
                 break;
-        case PRID_IMP_BCM4350:
-                switch (c->processor_id & 0xf0) {
-                case PRID_REV_BCM6358:
-                        c->cputype = CPU_BCM6358;
-                        __cpu_name[cpu] = "Broadcom BCM6358";
-                        break;
-                default:
-                        c->cputype = CPU_UNKNOWN;
-                        break;
-                }
+        case PRID_IMP_BMIPS4KC:
+                c->cputype = CPU_4KC;
+                __cpu_name[cpu] = "MIPS 4Kc";
                 break;
         }
 }
@@ -953,6 +960,12 @@ platform:
                 if (cpu == 0)
                         __elf_platform = "octeon";
                 break;
+        case PRID_IMP_CAVIUM_CN63XX:
+                c->cputype = CPU_CAVIUM_OCTEON2;
+                __cpu_name[cpu] = "Cavium Octeon II";
+                if (cpu == 0)
+                        __elf_platform = "octeon2";
+                break;
         default:
                 printk(KERN_INFO "Unknown Octeon chip!\n");
                 c->cputype = CPU_UNKNOWN;
@@ -976,6 +989,12 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
         }
 }
 
+#ifdef CONFIG_64BIT
+/* For use by uaccess.h */
+u64 __ua_limit;
+EXPORT_SYMBOL(__ua_limit);
+#endif
+
 const char *__cpu_name[NR_CPUS];
 const char *__elf_platform;
 
@@ -1053,6 +1072,11 @@ __cpuinit void cpu_probe(void)
                 c->srsets = 1;
 
         cpu_probe_vmbits(c);
+
+#ifdef CONFIG_64BIT
+        if (cpu == 0)
+                __ua_limit = ~((1ull << cpu_vmbits) - 1);
+#endif
 }
 
 __cpuinit void cpu_report(void)
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index c6345f579a8a..4f93db58a79e 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -151,6 +151,29 @@ void __init init_IRQ(void)
 #endif
 }
 
+#ifdef DEBUG_STACKOVERFLOW
+static inline void check_stack_overflow(void)
+{
+        unsigned long sp;
+
+        __asm__ __volatile__("move %0, $sp" : "=r" (sp));
+        sp &= THREAD_MASK;
+
+        /*
+         * Check for stack overflow: is there less than STACK_WARN free?
+         * STACK_WARN is defined as 1/8 of THREAD_SIZE by default.
+         */
+        if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
+                printk("do_IRQ: stack overflow: %ld\n",
+                       sp - sizeof(struct thread_info));
+                dump_stack();
+        }
+}
+#else
+static inline void check_stack_overflow(void) {}
+#endif
+
+
 /*
  * do_IRQ handles all normal device IRQ's (the special
  * SMP cross-CPU interrupts have their own specific
@@ -159,6 +182,7 @@ void __init init_IRQ(void)
 void __irq_entry do_IRQ(unsigned int irq)
 {
         irq_enter();
+        check_stack_overflow();
         __DO_IRQ_SMTC_HOOK(irq);
         generic_handle_irq(irq);
         irq_exit();
diff --git a/arch/mips/kernel/perf_event.c b/arch/mips/kernel/perf_event.c
new file mode 100644
index 000000000000..2b7f3f703b83
--- /dev/null
+++ b/arch/mips/kernel/perf_event.c
@@ -0,0 +1,601 @@
+/*
+ * Linux performance counter support for MIPS.
+ *
+ * Copyright (C) 2010 MIPS Technologies, Inc.
+ * Author: Deng-Cheng Zhu
+ *
+ * This code is based on the implementation for ARM, which is in turn
+ * based on the sparc64 perf event code and the x86 code. Performance
+ * counter access is based on the MIPS Oprofile code. And the callchain
+ * support references the code of MIPS stacktrace.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/uaccess.h>
+
+#include <asm/irq.h>
+#include <asm/irq_regs.h>
+#include <asm/stacktrace.h>
+#include <asm/time.h> /* For perf_irq */
+
+/* These are for 32bit counters. For 64bit ones, define them accordingly. */
+#define MAX_PERIOD      ((1ULL << 32) - 1)
+#define VALID_COUNT     0x7fffffff
+#define TOTAL_BITS      32
+#define HIGHEST_BIT     31
+
+#define MIPS_MAX_HWEVENTS 4
+
+struct cpu_hw_events {
+        /* Array of events on this cpu. */
+        struct perf_event       *events[MIPS_MAX_HWEVENTS];
+
+        /*
+         * Set the bit (indexed by the counter number) when the counter
+         * is used for an event.
+         */
+        unsigned long           used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+        /*
+         * The borrowed MSB for the performance counter. A MIPS performance
+         * counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit
+         * counters) as a factor of determining whether a counter overflow
+         * should be signaled. So here we use a separate MSB for each
+         * counter to make things easy.
+         */
+        unsigned long           msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
+
+        /*
+         * Software copy of the control register for each performance counter.
+         * MIPS CPUs vary in performance counters. They use this differently,
+         * and even may not use it.
+         */
+        unsigned int            saved_ctrl[MIPS_MAX_HWEVENTS];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
+        .saved_ctrl = {0},
+};
+
+/* The description of MIPS performance events. */
+struct mips_perf_event {
+        unsigned int event_id;
+        /*
+         * MIPS performance counters are indexed starting from 0.
+         * CNTR_EVEN indicates the indexes of the counters to be used are
+         * even numbers.
+         */
+        unsigned int cntr_mask;
+        #define CNTR_EVEN       0x55555555
+        #define CNTR_ODD        0xaaaaaaaa
+#ifdef CONFIG_MIPS_MT_SMP
+        enum {
+                T  = 0,
+                V  = 1,
+                P  = 2,
+        } range;
+#else
+        #define T
+        #define V
+        #define P
+#endif
+};
+
+static struct mips_perf_event raw_event;
+static DEFINE_MUTEX(raw_event_mutex);
+
+#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+struct mips_pmu {
+        const char      *name;
+        int             irq;
+        irqreturn_t     (*handle_irq)(int irq, void *dev);
+        int             (*handle_shared_irq)(void);
+        void            (*start)(void);
+        void            (*stop)(void);
+        int             (*alloc_counter)(struct cpu_hw_events *cpuc,
+                                        struct hw_perf_event *hwc);
+        u64             (*read_counter)(unsigned int idx);
+        void            (*write_counter)(unsigned int idx, u64 val);
+        void            (*enable_event)(struct hw_perf_event *evt, int idx);
+        void            (*disable_event)(int idx);
+        const struct mips_perf_event *(*map_raw_event)(u64 config);
+        const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
+        const struct mips_perf_event (*cache_event_map)
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX];
+        unsigned int    num_counters;
+};
+
+static const struct mips_pmu *mipspmu;
+
+static int
+mipspmu_event_set_period(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        s64 left = local64_read(&hwc->period_left);
+        s64 period = hwc->sample_period;
+        int ret = 0;
+        u64 uleft;
+        unsigned long flags;
+
+        if (unlikely(left <= -period)) {
+                left = period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (unlikely(left <= 0)) {
+                left += period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (left > (s64)MAX_PERIOD)
+                left = MAX_PERIOD;
+
+        local64_set(&hwc->prev_count, (u64)-left);
+
+        local_irq_save(flags);
+        uleft = (u64)(-left) & MAX_PERIOD;
+        uleft > VALID_COUNT ?
+                set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs);
+        mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT);
+        local_irq_restore(flags);
+
+        perf_event_update_userpage(event);
+
+        return ret;
+}
+
+static int mipspmu_enable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx;
+        int err = 0;
+
+        /* To look for a free counter for this event. */
+        idx = mipspmu->alloc_counter(cpuc, hwc);
+        if (idx < 0) {
+                err = idx;
+                goto out;
+        }
+
+        /*
+         * If there is an event in the counter we are going to use then
+         * make sure it is disabled.
+         */
+        event->hw.idx = idx;
+        mipspmu->disable_event(idx);
+        cpuc->events[idx] = event;
+
+        /* Set the period for the event. */
+        mipspmu_event_set_period(event, hwc, idx);
+
+        /* Enable the event. */
+        mipspmu->enable_event(hwc, idx);
+
+        /* Propagate our changes to the userspace mapping. */
+        perf_event_update_userpage(event);
+
+out:
+        return err;
+}
+
+static void mipspmu_event_update(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        unsigned long flags;
+        int shift = 64 - TOTAL_BITS;
+        s64 prev_raw_count, new_raw_count;
+        s64 delta;
+
+again:
+        prev_raw_count = local64_read(&hwc->prev_count);
+        local_irq_save(flags);
+        /* Make the counter value be a "real" one. */
+        new_raw_count = mipspmu->read_counter(idx);
+        if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) {
+                new_raw_count &= VALID_COUNT;
+                clear_bit(idx, cpuc->msbs);
+        } else
+                new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT);
+        local_irq_restore(flags);
+
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                                new_raw_count) != prev_raw_count)
+                goto again;
+
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
+
+        return;
+}
+
+static void mipspmu_disable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+
+        WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+        /* We are working on a local event. */
+        mipspmu->disable_event(idx);
+
+        barrier();
+
+        mipspmu_event_update(event, hwc, idx);
+        cpuc->events[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
+static void mipspmu_unthrottle(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        mipspmu->enable_event(hwc, hwc->idx);
+}
+
+static void mipspmu_read(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        /* Don't read disabled counters! */
+        if (hwc->idx < 0)
+                return;
+
+        mipspmu_event_update(event, hwc, hwc->idx);
+}
+
+static struct pmu pmu = {
+        .enable         = mipspmu_enable,
+        .disable        = mipspmu_disable,
+        .unthrottle     = mipspmu_unthrottle,
+        .read           = mipspmu_read,
+};
+
+static atomic_t active_events = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmu_reserve_mutex);
+static int (*save_perf_irq)(void);
+
+static int mipspmu_get_irq(void)
+{
+        int err;
+
+        if (mipspmu->irq >= 0) {
+                /* Request my own irq handler. */
+                err = request_irq(mipspmu->irq, mipspmu->handle_irq,
+                        IRQF_DISABLED | IRQF_NOBALANCING,
+                        "mips_perf_pmu", NULL);
+                if (err) {
+                        pr_warning("Unable to request IRQ%d for MIPS "
+                           "performance counters!\n", mipspmu->irq);
+                }
+        } else if (cp0_perfcount_irq < 0) {
+                /*
+                 * We are sharing the irq number with the timer interrupt.
+                 */
+                save_perf_irq = perf_irq;
+                perf_irq = mipspmu->handle_shared_irq;
+                err = 0;
+        } else {
+                pr_warning("The platform hasn't properly defined its "
+                        "interrupt controller.\n");
+                err = -ENOENT;
+        }
+
+        return err;
+}
+
+static void mipspmu_free_irq(void)
+{
+        if (mipspmu->irq >= 0)
+                free_irq(mipspmu->irq, NULL);
+        else if (cp0_perfcount_irq < 0)
+                perf_irq = save_perf_irq;
+}
+
+static inline unsigned int
+mipspmu_perf_event_encode(const struct mips_perf_event *pev)
+{
+/*
+ * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
+ * event_id.
+ */
+#ifdef CONFIG_MIPS_MT_SMP
+        return ((unsigned int)pev->range << 24) |
+                (pev->cntr_mask & 0xffff00) |
+                (pev->event_id & 0xff);
+#else
+        return (pev->cntr_mask & 0xffff00) |
+                (pev->event_id & 0xff);
+#endif
+}
+
+static const struct mips_perf_event *
+mipspmu_map_general_event(int idx)
+{
+        const struct mips_perf_event *pev;
+
+        pev = ((*mipspmu->general_event_map)[idx].event_id ==
+                UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
+                &(*mipspmu->general_event_map)[idx]);
+
+        return pev;
+}
+
+static const struct mips_perf_event *
+mipspmu_map_cache_event(u64 config)
+{
+        unsigned int cache_type, cache_op, cache_result;
+        const struct mips_perf_event *pev;
+
+        cache_type = (config >> 0) & 0xff;
+        if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+                return ERR_PTR(-EINVAL);
+
+        cache_op = (config >> 8) & 0xff;
+        if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+                return ERR_PTR(-EINVAL);
+
+        cache_result = (config >> 16) & 0xff;
+        if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return ERR_PTR(-EINVAL);
+
+        pev = &((*mipspmu->cache_event_map)
+                                        [cache_type]
+                                        [cache_op]
+                                        [cache_result]);
+
+        if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
+                return ERR_PTR(-EOPNOTSUPP);
+
+        return pev;
+
+}
+
+static int validate_event(struct cpu_hw_events *cpuc,
+               struct perf_event *event)
+{
+        struct hw_perf_event fake_hwc = event->hw;
+
+        if (event->pmu && event->pmu != &pmu)
+                return 0;
+
+        return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
+}
+
+static int validate_group(struct perf_event *event)
+{
+        struct perf_event *sibling, *leader = event->group_leader;
+        struct cpu_hw_events fake_cpuc;
+
+        memset(&fake_cpuc, 0, sizeof(fake_cpuc));
+
+        if (!validate_event(&fake_cpuc, leader))
+                return -ENOSPC;
+
+        list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+                if (!validate_event(&fake_cpuc, sibling))
+                        return -ENOSPC;
+        }
+
+        if (!validate_event(&fake_cpuc, event))
+                return -ENOSPC;
+
+        return 0;
+}
+
+/*
+ * mipsxx/rm9000/loongson2 have different performance counters, they have
+ * specific low-level init routines.
+ */
+static void reset_counters(void *arg);
+static int __hw_perf_event_init(struct perf_event *event);
+
+static void hw_perf_event_destroy(struct perf_event *event)
+{
+        if (atomic_dec_and_mutex_lock(&active_events,
+                                &pmu_reserve_mutex)) {
+                /*
+                 * We must not call the destroy function with interrupts
+                 * disabled.
+                 */
+                on_each_cpu(reset_counters,
+                        (void *)(long)mipspmu->num_counters, 1);
+                mipspmu_free_irq();
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+}
+
+const struct pmu *hw_perf_event_init(struct perf_event *event)
+{
+        int err = 0;
+
+        if (!mipspmu || event->cpu >= nr_cpumask_bits ||
+                (event->cpu >= 0 && !cpu_online(event->cpu)))
+                return ERR_PTR(-ENODEV);
+
+        if (!atomic_inc_not_zero(&active_events)) {
+                if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
+                        atomic_dec(&active_events);
+                        return ERR_PTR(-ENOSPC);
+                }
+
+                mutex_lock(&pmu_reserve_mutex);
+                if (atomic_read(&active_events) == 0)
+                        err = mipspmu_get_irq();
+
+                if (!err)
+                        atomic_inc(&active_events);
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+
+        if (err)
+                return ERR_PTR(err);
+
+        err = __hw_perf_event_init(event);
+        if (err)
+                hw_perf_event_destroy(event);
+
+        return err ? ERR_PTR(err) : &pmu;
+}
+
+void hw_perf_enable(void)
+{
+        if (mipspmu)
+                mipspmu->start();
+}
+
+void hw_perf_disable(void)
+{
+        if (mipspmu)
+                mipspmu->stop();
+}
+
+/* This is needed by specific irq handlers in perf_event_*.c */
+static void
+handle_associated_event(struct cpu_hw_events *cpuc,
+        int idx, struct perf_sample_data *data, struct pt_regs *regs)
+{
+        struct perf_event *event = cpuc->events[idx];
+        struct hw_perf_event *hwc = &event->hw;
+
+        mipspmu_event_update(event, hwc, idx);
+        data->period = event->hw.last_period;
+        if (!mipspmu_event_set_period(event, hwc, idx))
+                return;
+
+        if (perf_event_overflow(event, 0, data, regs))
+                mipspmu->disable_event(idx);
+}
+
+#include "perf_event_mipsxx.c"
+
+/* Callchain handling code. */
+static inline void
+callchain_store(struct perf_callchain_entry *entry,
+                u64 ip)
+{
+        if (entry->nr < PERF_MAX_STACK_DEPTH)
+                entry->ip[entry->nr++] = ip;
+}
+
+/*
+ * Leave userspace callchain empty for now. When we find a way to trace
+ * the user stack callchains, we add here.
+ */
+static void
+perf_callchain_user(struct pt_regs *regs,
+                    struct perf_callchain_entry *entry)
+{
+}
+
+static void save_raw_perf_callchain(struct perf_callchain_entry *entry,
+        unsigned long reg29)
+{
+        unsigned long *sp = (unsigned long *)reg29;
+        unsigned long addr;
+
+        while (!kstack_end(sp)) {
+                addr = *sp++;
+                if (__kernel_text_address(addr)) {
+                        callchain_store(entry, addr);
+                        if (entry->nr >= PERF_MAX_STACK_DEPTH)
+                                break;
+                }
+        }
+}
+
+static void
+perf_callchain_kernel(struct pt_regs *regs,
+                      struct perf_callchain_entry *entry)
+{
+        unsigned long sp = regs->regs[29];
+#ifdef CONFIG_KALLSYMS
+        unsigned long ra = regs->regs[31];
+        unsigned long pc = regs->cp0_epc;
+
+        callchain_store(entry, PERF_CONTEXT_KERNEL);
+        if (raw_show_trace || !__kernel_text_address(pc)) {
+                unsigned long stack_page =
+                        (unsigned long)task_stack_page(current);
+                if (stack_page && sp >= stack_page &&
+                    sp <= stack_page + THREAD_SIZE - 32)
+                        save_raw_perf_callchain(entry, sp);
+                return;
+        }
+        do {
+                callchain_store(entry, pc);
+                if (entry->nr >= PERF_MAX_STACK_DEPTH)
+                        break;
+                pc = unwind_stack(current, &sp, pc, &ra);
+        } while (pc);
+#else
+        callchain_store(entry, PERF_CONTEXT_KERNEL);
+        save_raw_perf_callchain(entry, sp);
+#endif
+}
+
+static void
+perf_do_callchain(struct pt_regs *regs,
+                  struct perf_callchain_entry *entry)
+{
+        int is_user;
+
+        if (!regs)
+                return;
+
+        is_user = user_mode(regs);
+
+        if (!current || !current->pid)
+                return;
+
+        if (is_user && current->state != TASK_RUNNING)
+                return;
+
+        if (!is_user) {
+                perf_callchain_kernel(regs, entry);
+                if (current->mm)
+                        regs = task_pt_regs(current);
+                else
+                        regs = NULL;
+        }
+        if (regs)
+                perf_callchain_user(regs, entry);
+}
+
+static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
+
+struct perf_callchain_entry *
+perf_callchain(struct pt_regs *regs)
+{
+        struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
+
+        entry->nr = 0;
+        perf_do_callchain(regs, entry);
+        return entry;
+}
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
new file mode 100644
index 000000000000..5c7c6fc07565
--- /dev/null
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -0,0 +1,1052 @@
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
+    defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
+
+#define M_CONFIG1_PC    (1 << 4)
+
+#define M_PERFCTL_EXL                   (1UL      <<  0)
+#define M_PERFCTL_KERNEL                (1UL      <<  1)
+#define M_PERFCTL_SUPERVISOR            (1UL      <<  2)
+#define M_PERFCTL_USER                  (1UL      <<  3)
+#define M_PERFCTL_INTERRUPT_ENABLE      (1UL      <<  4)
+#define M_PERFCTL_EVENT(event)          (((event) & 0x3ff)  << 5)
+#define M_PERFCTL_VPEID(vpe)            ((vpe)    << 16)
+#define M_PERFCTL_MT_EN(filter)         ((filter) << 20)
+#define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
+#define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
+#define    M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
+#define M_PERFCTL_TCID(tcid)            ((tcid)   << 22)
+#define M_PERFCTL_WIDE                  (1UL      << 30)
+#define M_PERFCTL_MORE                  (1UL      << 31)
+
+#define M_PERFCTL_COUNT_EVENT_WHENEVER  (M_PERFCTL_EXL |                \
+                                        M_PERFCTL_KERNEL |              \
+                                        M_PERFCTL_USER |                \
+                                        M_PERFCTL_SUPERVISOR |          \
+                                        M_PERFCTL_INTERRUPT_ENABLE)
+
+#ifdef CONFIG_MIPS_MT_SMP
+#define M_PERFCTL_CONFIG_MASK           0x3fff801f
+#else
+#define M_PERFCTL_CONFIG_MASK           0x1f
+#endif
+#define M_PERFCTL_EVENT_MASK            0xfe0
+
+#define M_COUNTER_OVERFLOW              (1UL      << 31)
+
+#ifdef CONFIG_MIPS_MT_SMP
+static int cpu_has_mipsmt_pertccounters;
+
+/*
+ * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
+ * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
+ */
+#if defined(CONFIG_HW_PERF_EVENTS)
+#define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
+                        0 : smp_processor_id())
+#else
+#define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
+                        0 : cpu_data[smp_processor_id()].vpe_id)
+#endif
+
+/* Copied from op_model_mipsxx.c */
+static inline unsigned int vpe_shift(void)
+{
+        if (num_possible_cpus() > 1)
+                return 1;
+
+        return 0;
+}
+#else /* !CONFIG_MIPS_MT_SMP */
+#define vpe_id()        0
+
+static inline unsigned int vpe_shift(void)
+{
+        return 0;
+}
+#endif /* CONFIG_MIPS_MT_SMP */
+
+static inline unsigned int
+counters_total_to_per_cpu(unsigned int counters)
+{
+        return counters >> vpe_shift();
+}
+
+static inline unsigned int
+counters_per_cpu_to_total(unsigned int counters)
+{
+        return counters << vpe_shift();
+}
+
+#define __define_perf_accessors(r, n, np)                               \
+                                                                        \
+static inline unsigned int r_c0_ ## r ## n(void)                        \
+{                                                                       \
+        unsigned int cpu = vpe_id();                                    \
+                                                                        \
+        switch (cpu) {                                                  \
+        case 0:                                                         \
+                return read_c0_ ## r ## n();                            \
+        case 1:                                                         \
+                return read_c0_ ## r ## np();                           \
+        default:                                                        \
+                BUG();                                                  \
+        }                                                               \
+        return 0;                                                       \
+}                                                                       \
+                                                                        \
+static inline void w_c0_ ## r ## n(unsigned int value)                  \
+{                                                                       \
+        unsigned int cpu = vpe_id();                                    \
+                                                                        \
+        switch (cpu) {                                                  \
+        case 0:                                                         \
+                write_c0_ ## r ## n(value);                             \
+                return;                                                 \
+        case 1:                                                         \
+                write_c0_ ## r ## np(value);                            \
+                return;                                                 \
+        default:                                                        \
+                BUG();                                                  \
+        }                                                               \
+        return;                                                         \
+}                                                                       \
+
+__define_perf_accessors(perfcntr, 0, 2)
+__define_perf_accessors(perfcntr, 1, 3)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
+
+__define_perf_accessors(perfctrl, 0, 2)
+__define_perf_accessors(perfctrl, 1, 3)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
+
+static inline int __n_counters(void)
+{
+        if (!(read_c0_config1() & M_CONFIG1_PC))
+                return 0;
+        if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
+                return 1;
+        if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
+                return 2;
+        if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
+                return 3;
+
+        return 4;
+}
+
+static inline int n_counters(void)
+{
+        int counters;
+
+        switch (current_cpu_type()) {
+        case CPU_R10000:
+                counters = 2;
+                break;
+
+        case CPU_R12000:
+        case CPU_R14000:
+                counters = 4;
+                break;
+
+        default:
+                counters = __n_counters();
+        }
+
+        return counters;
+}
+
+static void reset_counters(void *arg)
+{
+        int counters = (int)(long)arg;
+        switch (counters) {
+        case 4:
+                w_c0_perfctrl3(0);
+                w_c0_perfcntr3(0);
+        case 3:
+                w_c0_perfctrl2(0);
+                w_c0_perfcntr2(0);
+        case 2:
+                w_c0_perfctrl1(0);
+                w_c0_perfcntr1(0);
+        case 1:
+                w_c0_perfctrl0(0);
+                w_c0_perfcntr0(0);
+        }
+}
+
+static inline u64
+mipsxx_pmu_read_counter(unsigned int idx)
+{
+        switch (idx) {
+        case 0:
+                return r_c0_perfcntr0();
+        case 1:
+                return r_c0_perfcntr1();
+        case 2:
+                return r_c0_perfcntr2();
+        case 3:
+                return r_c0_perfcntr3();
+        default:
+                WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+                return 0;
+        }
+}
+
+static inline void
+mipsxx_pmu_write_counter(unsigned int idx, u64 val)
+{
+        switch (idx) {
+        case 0:
+                w_c0_perfcntr0(val);
+                return;
+        case 1:
+                w_c0_perfcntr1(val);
+                return;
+        case 2:
+                w_c0_perfcntr2(val);
+                return;
+        case 3:
+                w_c0_perfcntr3(val);
+                return;
+        }
+}
+
+static inline unsigned int
+mipsxx_pmu_read_control(unsigned int idx)
+{
+        switch (idx) {
+        case 0:
+                return r_c0_perfctrl0();
+        case 1:
+                return r_c0_perfctrl1();
+        case 2:
+                return r_c0_perfctrl2();
+        case 3:
+                return r_c0_perfctrl3();
+        default:
+                WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
+                return 0;
+        }
+}
+
+static inline void
+mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
+{
+        switch (idx) {
+        case 0:
+                w_c0_perfctrl0(val);
+                return;
+        case 1:
+                w_c0_perfctrl1(val);
+                return;
+        case 2:
+                w_c0_perfctrl2(val);
+                return;
+        case 3:
+                w_c0_perfctrl3(val);
+                return;
+        }
+}
+
+#ifdef CONFIG_MIPS_MT_SMP
+static DEFINE_RWLOCK(pmuint_rwlock);
+#endif
+
+/* 24K/34K/1004K cores can share the same event map. */
+static const struct mips_perf_event mipsxxcore_event_map
+                                [PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+        [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
+        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
+        [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 74K core has different branch event code. */
+static const struct mips_perf_event mipsxx74Kcore_event_map
+                                [PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
+        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
+        [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
+        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
+        [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
+};
+
+/* 24K/34K/1004K cores can share the same cache event map. */
+static const struct mips_perf_event mipsxxcore_cache_map
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+        /*
+         * Like some other architectures (e.g. ARM), the performance
+         * counters don't differentiate between read and write
+         * accesses/misses, so this isn't strictly correct, but it's the
+         * best we can do. Writes and reads get combined.
+         */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x0a, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x09, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x09, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { 0x14, CNTR_EVEN, T },
+                /*
+                 * Note that MIPS has only "hit" events countable for
+                 * the prefetch operation.
+                 */
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x15, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x16, CNTR_EVEN, P },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(DTLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x05, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x05, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(BPU)] = {
+        /* Using the same code for *HW_BRANCH* */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x02, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x02, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+};
+
+/* 74K core has completely different cache event map. */
+static const struct mips_perf_event mipsxx74Kcore_cache_map
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+[C(L1D)] = {
+        /*
+         * Like some other architectures (e.g. ARM), the performance
+         * counters don't differentiate between read and write
+         * accesses/misses, so this isn't strictly correct, but it's the
+         * best we can do. Writes and reads get combined.
+         */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
+                [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x17, CNTR_ODD, T },
+                [C(RESULT_MISS)]        = { 0x18, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(L1I)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x06, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x06, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { 0x34, CNTR_EVEN, T },
+                /*
+                 * Note that MIPS has only "hit" events countable for
+                 * the prefetch operation.
+                 */
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(LL)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x1c, CNTR_ODD, P },
+                [C(RESULT_MISS)]        = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(DTLB)] = {
+        /* 74K core does not have specific DTLB events. */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(ITLB)] = {
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x04, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x04, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+[C(BPU)] = {
+        /* Using the same code for *HW_BRANCH* */
+        [C(OP_READ)] = {
+                [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
+        },
+        [C(OP_WRITE)] = {
+                [C(RESULT_ACCESS)]      = { 0x27, CNTR_EVEN, T },
+                [C(RESULT_MISS)]        = { 0x27, CNTR_ODD, T },
+        },
+        [C(OP_PREFETCH)] = {
+                [C(RESULT_ACCESS)]      = { UNSUPPORTED_PERF_EVENT_ID },
+                [C(RESULT_MISS)]        = { UNSUPPORTED_PERF_EVENT_ID },
+        },
+},
+};
+
+#ifdef CONFIG_MIPS_MT_SMP
+static void
+check_and_calc_range(struct perf_event *event,
+                        const struct mips_perf_event *pev)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (event->cpu >= 0) {
+                if (pev->range > V) {
+                        /*
+                         * The user selected an event that is processor
+                         * wide, while expecting it to be VPE wide.
+                         */
+                        hwc->config_base |= M_TC_EN_ALL;
+                } else {
+                        /*
+                         * FIXME: cpu_data[event->cpu].vpe_id reports 0
+                         * for both CPUs.
+                         */
+                        hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
+                        hwc->config_base |= M_TC_EN_VPE;
+                }
+        } else
+                hwc->config_base |= M_TC_EN_ALL;
+}
+#else
+static void
+check_and_calc_range(struct perf_event *event,
+                        const struct mips_perf_event *pev)
+{
+}
+#endif
+
+static int __hw_perf_event_init(struct perf_event *event)
+{
+        struct perf_event_attr *attr = &event->attr;
+        struct hw_perf_event *hwc = &event->hw;
+        const struct mips_perf_event *pev;
+        int err;
+
+        /* Returning MIPS event descriptor for generic perf event. */
+        if (PERF_TYPE_HARDWARE == event->attr.type) {
+                if (event->attr.config >= PERF_COUNT_HW_MAX)
+                        return -EINVAL;
+                pev = mipspmu_map_general_event(event->attr.config);
+        } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
+                pev = mipspmu_map_cache_event(event->attr.config);
+        } else if (PERF_TYPE_RAW == event->attr.type) {
+                /* We are working on the global raw event. */
+                mutex_lock(&raw_event_mutex);
+                pev = mipspmu->map_raw_event(event->attr.config);
+        } else {
+                /* The event type is not (yet) supported. */
+                return -EOPNOTSUPP;
+        }
+
+        if (IS_ERR(pev)) {
+                if (PERF_TYPE_RAW == event->attr.type)
+                        mutex_unlock(&raw_event_mutex);
+                return PTR_ERR(pev);
+        }
+
+        /*
+         * We allow max flexibility on how each individual counter shared
+         * by the single CPU operates (the mode exclusion and the range).
+         */
+        hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
+
+        /* Calculate range bits and validate it. */
+        if (num_possible_cpus() > 1)
+                check_and_calc_range(event, pev);
+
+        hwc->event_base = mipspmu_perf_event_encode(pev);
+        if (PERF_TYPE_RAW == event->attr.type)
+                mutex_unlock(&raw_event_mutex);
+
+        if (!attr->exclude_user)
+                hwc->config_base |= M_PERFCTL_USER;
+        if (!attr->exclude_kernel) {
+                hwc->config_base |= M_PERFCTL_KERNEL;
+                /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
+                hwc->config_base |= M_PERFCTL_EXL;
+        }
+        if (!attr->exclude_hv)
+                hwc->config_base |= M_PERFCTL_SUPERVISOR;
+
+        hwc->config_base &= M_PERFCTL_CONFIG_MASK;
+        /*
+         * The event can belong to another cpu. We do not assign a local
+         * counter for it for now.
+         */
+        hwc->idx = -1;
+        hwc->config = 0;
+
+        if (!hwc->sample_period) {
+                hwc->sample_period  = MAX_PERIOD;
+                hwc->last_period    = hwc->sample_period;
+                local64_set(&hwc->period_left, hwc->sample_period);
+        }
+
+        err = 0;
+        if (event->group_leader != event) {
+                err = validate_group(event);
+                if (err)
+                        return -EINVAL;
+        }
+
+        event->destroy = hw_perf_event_destroy;
+
+        return err;
+}
+
+static void pause_local_counters(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        int counters = mipspmu->num_counters;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        switch (counters) {
+        case 4:
+                cpuc->saved_ctrl[3] = r_c0_perfctrl3();
+                w_c0_perfctrl3(cpuc->saved_ctrl[3] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        case 3:
+                cpuc->saved_ctrl[2] = r_c0_perfctrl2();
+                w_c0_perfctrl2(cpuc->saved_ctrl[2] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        case 2:
+                cpuc->saved_ctrl[1] = r_c0_perfctrl1();
+                w_c0_perfctrl1(cpuc->saved_ctrl[1] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        case 1:
+                cpuc->saved_ctrl[0] = r_c0_perfctrl0();
+                w_c0_perfctrl0(cpuc->saved_ctrl[0] &
+                        ~M_PERFCTL_COUNT_EVENT_WHENEVER);
+        }
+        local_irq_restore(flags);
+}
+
+static void resume_local_counters(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        int counters = mipspmu->num_counters;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        switch (counters) {
+        case 4:
+                w_c0_perfctrl3(cpuc->saved_ctrl[3]);
+        case 3:
+                w_c0_perfctrl2(cpuc->saved_ctrl[2]);
+        case 2:
+                w_c0_perfctrl1(cpuc->saved_ctrl[1]);
+        case 1:
+                w_c0_perfctrl0(cpuc->saved_ctrl[0]);
+        }
+        local_irq_restore(flags);
+}
+
+static int mipsxx_pmu_handle_shared_irq(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct perf_sample_data data;
+        unsigned int counters = mipspmu->num_counters;
+        unsigned int counter;
+        int handled = IRQ_NONE;
+        struct pt_regs *regs;
+
+        if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+                return handled;
+
+        /*
+         * First we pause the local counters, so that when we are locked
+         * here, the counters are all paused. When it gets locked due to
+         * perf_disable(), the timer interrupt handler will be delayed.
+         *
+         * See also mipsxx_pmu_start().
+         */
+        pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+        read_lock(&pmuint_rwlock);
+#endif
+
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        switch (counters) {
+#define HANDLE_COUNTER(n)                                               \
+        case n + 1:                                                     \
+                if (test_bit(n, cpuc->used_mask)) {                     \
+                        counter = r_c0_perfcntr ## n();                 \
+                        if (counter & M_COUNTER_OVERFLOW) {             \
+                                w_c0_perfcntr ## n(counter &            \
+                                                VALID_COUNT);           \
+                                if (test_and_change_bit(n, cpuc->msbs)) \
+                                        handle_associated_event(cpuc,   \
+                                                n, &data, regs);        \
+                                handled = IRQ_HANDLED;                  \
+                        }                                               \
+                }
+        HANDLE_COUNTER(3)
+        HANDLE_COUNTER(2)
+        HANDLE_COUNTER(1)
+        HANDLE_COUNTER(0)
+        }
+
+        /*
+         * Do all the work for the pending perf events. We can do this
+         * in here because the performance counter interrupt is a regular
+         * interrupt, not NMI.
+         */
+        if (handled == IRQ_HANDLED)
+                perf_event_do_pending();
+
+#ifdef CONFIG_MIPS_MT_SMP
+        read_unlock(&pmuint_rwlock);
+#endif
+        resume_local_counters();
+        return handled;
+}
+
+static irqreturn_t
+mipsxx_pmu_handle_irq(int irq, void *dev)
+{
+        return mipsxx_pmu_handle_shared_irq();
+}
+
+static void mipsxx_pmu_start(void)
+{
+#ifdef CONFIG_MIPS_MT_SMP
+        write_unlock(&pmuint_rwlock);
+#endif
+        resume_local_counters();
+}
+
+/*
+ * MIPS performance counters can be per-TC. The control registers can
+ * not be directly accessed accross CPUs. Hence if we want to do global
+ * control, we need cross CPU calls. on_each_cpu() can help us, but we
+ * can not make sure this function is called with interrupts enabled. So
+ * here we pause local counters and then grab a rwlock and leave the
+ * counters on other CPUs alone. If any counter interrupt raises while
+ * we own the write lock, simply pause local counters on that CPU and
+ * spin in the handler. Also we know we won't be switched to another
+ * CPU after pausing local counters and before grabbing the lock.
+ */
+static void mipsxx_pmu_stop(void)
+{
+        pause_local_counters();
+#ifdef CONFIG_MIPS_MT_SMP
+        write_lock(&pmuint_rwlock);
+#endif
+}
+
+static int
+mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
+                        struct hw_perf_event *hwc)
+{
+        int i;
+
+        /*
+         * We only need to care the counter mask. The range has been
+         * checked definitely.
+         */
+        unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
+
+        for (i = mipspmu->num_counters - 1; i >= 0; i--) {
+                /*
+                 * Note that some MIPS perf events can be counted by both
+                 * even and odd counters, wheresas many other are only by
+                 * even _or_ odd counters. This introduces an issue that
+                 * when the former kind of event takes the counter the
+                 * latter kind of event wants to use, then the "counter
+                 * allocation" for the latter event will fail. In fact if
+                 * they can be dynamically swapped, they both feel happy.
+                 * But here we leave this issue alone for now.
+                 */
+                if (test_bit(i, &cntr_mask) &&
+                        !test_and_set_bit(i, cpuc->used_mask))
+                        return i;
+        }
+
+        return -EAGAIN;
+}
+
+static void
+mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        unsigned long flags;
+
+        WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+        local_irq_save(flags);
+        cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
+                (evt->config_base & M_PERFCTL_CONFIG_MASK) |
+                /* Make sure interrupt enabled. */
+                M_PERFCTL_INTERRUPT_ENABLE;
+        /*
+         * We do not actually let the counter run. Leave it until start().
+         */
+        local_irq_restore(flags);
+}
+
+static void
+mipsxx_pmu_disable_event(int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        unsigned long flags;
+
+        WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
+
+        local_irq_save(flags);
+        cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
+                ~M_PERFCTL_COUNT_EVENT_WHENEVER;
+        mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
+        local_irq_restore(flags);
+}
+
+/* 24K */
+#define IS_UNSUPPORTED_24K_EVENT(r, b)                                  \
+        ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 ||          \
+         (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 ||           \
+         (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 ||           \
+         (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) ||         \
+         ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_24K_EVENT(b)                                   \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+
+/* 34K */
+#define IS_UNSUPPORTED_34K_EVENT(r, b)                                  \
+        ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 ||           \
+         (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) ||         \
+         ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_34K_EVENT(b)                                   \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_34K_EVENT(r, b)                                      \
+        ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
+         (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||           \
+         (r) == 176 || ((b) >= 50 && (b) <= 55) ||                      \
+         ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
+#endif
+
+/* 74K */
+#define IS_UNSUPPORTED_74K_EVENT(r, b)                                  \
+        ((r) == 5 || ((r) >= 135 && (r) <= 137) ||                      \
+         ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 ||          \
+         (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) ||          \
+         (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 ||           \
+         (b) == 61 || (r) == 62 || (r) == 191 ||                        \
+         ((b) >= 64 && (b) <= 127))
+#define IS_BOTH_COUNTERS_74K_EVENT(b)                                   \
+        ((b) == 0 || (b) == 1)
+
+/* 1004K */
+#define IS_UNSUPPORTED_1004K_EVENT(r, b)                                \
+        ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 ||           \
+         (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
+#define IS_BOTH_COUNTERS_1004K_EVENT(b)                                 \
+        ((b) == 0 || (b) == 1 || (b) == 11)
+#ifdef CONFIG_MIPS_MT_SMP
+#define IS_RANGE_P_1004K_EVENT(r, b)                                    \
+        ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 ||             \
+         (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 ||            \
+         (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) ||        \
+         (r) == 188 || (b) == 61 || (b) == 62 ||                        \
+         ((b) >= 64 && (b) <= 67))
+#define IS_RANGE_V_1004K_EVENT(r)       ((r) == 47)
+#endif
+
+/*
+ * User can use 0-255 raw events, where 0-127 for the events of even
+ * counters, and 128-255 for odd counters. Note that bit 7 is used to
+ * indicate the parity. So, for example, when user wants to take the
+ * Event Num of 15 for odd counters (by referring to the user manual),
+ * then 128 needs to be added to 15 as the input for the event config,
+ * i.e., 143 (0x8F) to be used.
+ */
+static const struct mips_perf_event *
+mipsxx_pmu_map_raw_event(u64 config)
+{
+        unsigned int raw_id = config & 0xff;
+        unsigned int base_id = raw_id & 0x7f;
+
+        switch (current_cpu_type()) {
+        case CPU_24K:
+                if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                /*
+                 * This is actually doing nothing. Non-multithreading
+                 * CPUs will not check and calculate the range.
+                 */
+                raw_event.range = P;
+#endif
+                break;
+        case CPU_34K:
+                if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
+                        raw_event.range = P;
+                else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
+                        raw_event.range = V;
+                else
+                        raw_event.range = T;
+#endif
+                break;
+        case CPU_74K:
+                if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                raw_event.range = P;
+#endif
+                break;
+        case CPU_1004K:
+                if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
+                        return ERR_PTR(-EOPNOTSUPP);
+                raw_event.event_id = base_id;
+                if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
+                        raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
+                else
+                        raw_event.cntr_mask =
+                                raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
+#ifdef CONFIG_MIPS_MT_SMP
+                if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
+                        raw_event.range = P;
+                else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
+                        raw_event.range = V;
+                else
+                        raw_event.range = T;
+#endif
+                break;
+        }
+
+        return &raw_event;
+}
+
+static struct mips_pmu mipsxxcore_pmu = {
+        .handle_irq = mipsxx_pmu_handle_irq,
+        .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+        .start = mipsxx_pmu_start,
+        .stop = mipsxx_pmu_stop,
+        .alloc_counter = mipsxx_pmu_alloc_counter,
+        .read_counter = mipsxx_pmu_read_counter,
+        .write_counter = mipsxx_pmu_write_counter,
+        .enable_event = mipsxx_pmu_enable_event,
+        .disable_event = mipsxx_pmu_disable_event,
+        .map_raw_event = mipsxx_pmu_map_raw_event,
+        .general_event_map = &mipsxxcore_event_map,
+        .cache_event_map = &mipsxxcore_cache_map,
+};
+
+static struct mips_pmu mipsxx74Kcore_pmu = {
+        .handle_irq = mipsxx_pmu_handle_irq,
+        .handle_shared_irq = mipsxx_pmu_handle_shared_irq,
+        .start = mipsxx_pmu_start,
+        .stop = mipsxx_pmu_stop,
+        .alloc_counter = mipsxx_pmu_alloc_counter,
+        .read_counter = mipsxx_pmu_read_counter,
+        .write_counter = mipsxx_pmu_write_counter,
+        .enable_event = mipsxx_pmu_enable_event,
+        .disable_event = mipsxx_pmu_disable_event,
+        .map_raw_event = mipsxx_pmu_map_raw_event,
+        .general_event_map = &mipsxx74Kcore_event_map,
+        .cache_event_map = &mipsxx74Kcore_cache_map,
+};
+
+static int __init
+init_hw_perf_events(void)
+{
+        int counters, irq;
+
+        pr_info("Performance counters: ");
+
+        counters = n_counters();
+        if (counters == 0) {
+                pr_cont("No available PMU.\n");
+                return -ENODEV;
+        }
+
+#ifdef CONFIG_MIPS_MT_SMP
+        cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
+        if (!cpu_has_mipsmt_pertccounters)
+                counters = counters_total_to_per_cpu(counters);
+#endif
+
+#ifdef MSC01E_INT_BASE
+        if (cpu_has_veic) {
+                /*
+                 * Using platform specific interrupt controller defines.
+                 */
+                irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+        } else {
+#endif
+                if (cp0_perfcount_irq >= 0)
+                        irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
+                else
+                        irq = -1;
+#ifdef MSC01E_INT_BASE
+        }
+#endif
+
+        on_each_cpu(reset_counters, (void *)(long)counters, 1);
+
+        switch (current_cpu_type()) {
+        case CPU_24K:
+                mipsxxcore_pmu.name = "mips/24K";
+                mipsxxcore_pmu.num_counters = counters;
+                mipsxxcore_pmu.irq = irq;
+                mipspmu = &mipsxxcore_pmu;
+                break;
+        case CPU_34K:
+                mipsxxcore_pmu.name = "mips/34K";
+                mipsxxcore_pmu.num_counters = counters;
+                mipsxxcore_pmu.irq = irq;
+                mipspmu = &mipsxxcore_pmu;
+                break;
+        case CPU_74K:
+                mipsxx74Kcore_pmu.name = "mips/74K";
+                mipsxx74Kcore_pmu.num_counters = counters;
+                mipsxx74Kcore_pmu.irq = irq;
+                mipspmu = &mipsxx74Kcore_pmu;
+                break;
+        case CPU_1004K:
+                mipsxxcore_pmu.name = "mips/1004K";
+                mipsxxcore_pmu.num_counters = counters;
+                mipsxxcore_pmu.irq = irq;
+                mipspmu = &mipsxxcore_pmu;
+                break;
+        default:
+                pr_cont("Either hardware does not support performance "
+                        "counters, or not yet implemented.\n");
+                return -ENODEV;
+        }
+
+        if (mipspmu)
+                pr_cont("%s PMU enabled, %d counters available to each "
+                        "CPU, irq %d%s\n", mipspmu->name, counters, irq,
+                        irq < 0 ? " (share with timer interrupt)" : "");
+
+        return 0;
+}
+arch_initcall(init_hw_perf_events);
+
+#endif /* defined(CONFIG_CPU_MIPS32)... */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index a6b900f2962b..acd3f2c49c06 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -490,6 +490,7 @@ static void __init arch_mem_init(char **cmdline_p)
         bootmem_init();
         device_tree_init();
         sparse_init();
+        plat_swiotlb_setup();
         paging_init();
 }
 
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index d053bf4759e4..8e9fbe75894e 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -29,6 +29,7 @@
 #include <linux/notifier.h>
 #include <linux/kdb.h>
 #include <linux/irq.h>
+#include <linux/perf_event.h>
 
 #include <asm/bootinfo.h>
 #include <asm/branch.h>
@@ -576,10 +577,16 @@ static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
  */
 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
 {
-        if ((opcode & OPCODE) == LL)
+        if ((opcode & OPCODE) == LL) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return simulate_ll(regs, opcode);
-        if ((opcode & OPCODE) == SC)
+        }
+        if ((opcode & OPCODE) == SC) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return simulate_sc(regs, opcode);
+        }
 
         return -1;                      /* Must be something else ... */
 }
@@ -595,6 +602,8 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
                 int rd = (opcode & RD) >> 11;
                 int rt = (opcode & RT) >> 16;
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 switch (rd) {
                 case 0:         /* CPU number */
                         regs->regs[rt] = smp_processor_id();
@@ -630,8 +639,11 @@ static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
 
 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
 {
-        if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC)
+        if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
+                perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                                1, 0, regs, 0);
                 return 0;
+        }
 
         return -1;                      /* Must be something else ... */
 }
@@ -1469,6 +1481,7 @@ void __cpuinit per_cpu_trap_init(void)
 {
         unsigned int cpu = smp_processor_id();
         unsigned int status_set = ST0_CU0;
+        unsigned int hwrena = cpu_hwrena_impl_bits;
 #ifdef CONFIG_MIPS_MT_SMTC
         int secondaryTC = 0;
         int bootTC = (cpu == 0);
@@ -1501,14 +1514,14 @@ void __cpuinit per_cpu_trap_init(void)
         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
                          status_set);
 
-        if (cpu_has_mips_r2) {
-                unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
+        if (cpu_has_mips_r2)
+                hwrena |= 0x0000000f;
 
-                if (!noulri && cpu_has_userlocal)
-                        enable |= (1 << 29);
+        if (!noulri && cpu_has_userlocal)
+                hwrena |= (1 << 29);
 
-                write_c0_hwrena(enable);
-        }
+        if (hwrena)
+                write_c0_hwrena(hwrena);
 
 #ifdef CONFIG_MIPS_MT_SMTC
         if (!secondaryTC) {
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 33d5a5ce4a29..cfea1adfa153 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -78,6 +78,8 @@
 #include <linux/smp.h>
 #include <linux/sched.h>
 #include <linux/debugfs.h>
+#include <linux/perf_event.h>
+
 #include <asm/asm.h>
 #include <asm/branch.h>
 #include <asm/byteorder.h>
@@ -109,6 +111,9 @@ static void emulate_load_store_insn(struct pt_regs *regs,
         unsigned long value;
         unsigned int res;
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                      1, 0, regs, 0);
+
         /*
          * This load never faults.
          */
@@ -511,6 +516,8 @@ asmlinkage void do_ade(struct pt_regs *regs)
         unsigned int __user *pc;
         mm_segment_t seg;
 
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
+                        1, 0, regs, regs->cp0_badvaddr);
         /*
          * Did we catch a fault trying to load an instruction?
          * Or are we running in MIPS16 mode?
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index c97ca69b94e0..6e1b77fec7ea 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -20,7 +20,6 @@ config LEMOTE_FULOONG2E
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
         select SYS_HAS_EARLY_PRINTK
-        select GENERIC_HARDIRQS_NO__DO_IRQ
         select GENERIC_ISA_DMA_SUPPORT_BROKEN
         select CPU_HAS_WB
         select LOONGSON_MC146818
@@ -40,7 +39,6 @@ config LEMOTE_MACH2F
         select CS5536
         select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
         select DMA_NONCOHERENT
-        select GENERIC_HARDIRQS_NO__DO_IRQ
         select GENERIC_ISA_DMA_SUPPORT_BROKEN
         select HW_HAS_PCI
         select I8259
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index ec3faa413f3b..b2ad1b0910ff 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -36,6 +36,7 @@
 #include <linux/sched.h>
 #include <linux/module.h>
 #include <linux/debugfs.h>
+#include <linux/perf_event.h>
 
 #include <asm/inst.h>
 #include <asm/bootinfo.h>
@@ -258,6 +259,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
         }
 
       emul:
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
+                        1, 0, xcp, 0);
         MIPS_FPU_EMU_INC_STATS(emulated);
         switch (MIPSInst_OPCODE(ir)) {
         case ldc1_op:{
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 0f9c488044d1..16c4d256b76f 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -181,10 +181,10 @@ static void __cpuinit probe_octeon(void)
         unsigned int config1;
         struct cpuinfo_mips *c = &current_cpu_data;
 
+        config1 = read_c0_config1();
         switch (c->cputype) {
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
-                config1 = read_c0_config1();
                 c->icache.linesz = 2 << ((config1 >> 19) & 7);
                 c->icache.sets = 64 << ((config1 >> 22) & 7);
                 c->icache.ways = 1 + ((config1 >> 16) & 7);
@@ -204,6 +204,20 @@ static void __cpuinit probe_octeon(void)
                 c->options |= MIPS_CPU_PREFETCH;
                 break;
 
+        case CPU_CAVIUM_OCTEON2:
+                c->icache.linesz = 2 << ((config1 >> 19) & 7);
+                c->icache.sets = 8;
+                c->icache.ways = 37;
+                c->icache.flags |= MIPS_CACHE_VTAG;
+                icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+                c->dcache.linesz = 128;
+                c->dcache.ways = 32;
+                c->dcache.sets = 8;
+                dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+                c->options |= MIPS_CPU_PREFETCH;
+                break;
+
         default:
                 panic("Unsupported Cavium Networks CPU type\n");
                 break;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6721ee2b1e8b..b4923a75cb4b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -42,14 +42,14 @@
  *  o collapses to normal function call on UP kernels
  *  o collapses to normal function call on systems with a single shared
  *    primary cache.
+ *  o doesn't disable interrupts on the local CPU
  */
-static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
-                                   int wait)
+static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
 {
         preempt_disable();
 
 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
-        smp_call_function(func, info, wait);
+        smp_call_function(func, info, 1);
 #endif
         func(info);
         preempt_enable();
@@ -363,7 +363,7 @@ static inline void local_r4k___flush_cache_all(void * args)
 
 static void r4k___flush_cache_all(void)
 {
-        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
+        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
 }
 
 static inline int has_valid_asid(const struct mm_struct *mm)
@@ -410,7 +410,7 @@ static void r4k_flush_cache_range(struct vm_area_struct *vma,
         int exec = vma->vm_flags & VM_EXEC;
 
         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
-                r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1);
+                r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
 }
 
 static inline void local_r4k_flush_cache_mm(void * args)
@@ -442,7 +442,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
         if (!cpu_has_dc_aliases)
                 return;
 
-        r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
 }
 
 struct flush_cache_page_args {
@@ -534,7 +534,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
         args.addr = addr;
         args.pfn = pfn;
 
-        r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
 }
 
 static inline void local_r4k_flush_data_cache_page(void * addr)
@@ -547,8 +547,7 @@ static void r4k_flush_data_cache_page(unsigned long addr)
         if (in_atomic())
                 local_r4k_flush_data_cache_page((void *)addr);
         else
-                r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
-                                1);
+                r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
 }
 
 struct flush_icache_range_args {
@@ -589,7 +588,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
         args.start = start;
         args.end = end;
 
-        r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1);
+        r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
         instruction_hazard();
 }
 
@@ -710,7 +709,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
 
 static void r4k_flush_cache_sigtramp(unsigned long addr)
 {
-        r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 }
 
 static void r4k_flush_icache_all(void)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 469d4019f795..4fc1a0fbe007 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -95,10 +95,9 @@ void *dma_alloc_noncoherent(struct device *dev, size_t size,
 
         return ret;
 }
-
 EXPORT_SYMBOL(dma_alloc_noncoherent);
 
-void *dma_alloc_coherent(struct device *dev, size_t size,
+static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
         dma_addr_t * dma_handle, gfp_t gfp)
 {
         void *ret;
@@ -123,7 +122,6 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
         return ret;
 }
 
-EXPORT_SYMBOL(dma_alloc_coherent);
 
 void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
         dma_addr_t dma_handle)
@@ -131,10 +129,9 @@ void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
         plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
         free_pages((unsigned long) vaddr, get_order(size));
 }
-
 EXPORT_SYMBOL(dma_free_noncoherent);
 
-void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
         dma_addr_t dma_handle)
 {
         unsigned long addr = (unsigned long) vaddr;
@@ -151,8 +148,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
         free_pages(addr, get_order(size));
 }
 
-EXPORT_SYMBOL(dma_free_coherent);
-
 static inline void __dma_sync(unsigned long addr, size_t size,
         enum dma_data_direction direction)
 {
@@ -174,21 +169,8 @@ static inline void __dma_sync(unsigned long addr, size_t size,
         }
 }
 
-dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-        enum dma_data_direction direction)
-{
-        unsigned long addr = (unsigned long) ptr;
-
-        if (!plat_device_is_coherent(dev))
-                __dma_sync(addr, size, direction);
-
-        return plat_map_dma_mem(dev, ptr, size);
-}
-
-EXPORT_SYMBOL(dma_map_single);
-
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-        enum dma_data_direction direction)
+static void mips_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction, struct dma_attrs *attrs)
 {
         if (cpu_is_noncoherent_r10000(dev))
                 __dma_sync(dma_addr_to_virt(dev, dma_addr), size,
@@ -197,15 +179,11 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
         plat_unmap_dma_mem(dev, dma_addr, size, direction);
 }
 
-EXPORT_SYMBOL(dma_unmap_single);
-
-int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-        enum dma_data_direction direction)
+static int mips_dma_map_sg(struct device *dev, struct scatterlist *sg,
+        int nents, enum dma_data_direction direction, struct dma_attrs *attrs)
 {
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         for (i = 0; i < nents; i++, sg++) {
                 unsigned long addr;
 
@@ -219,33 +197,27 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
         return nents;
 }
 
-EXPORT_SYMBOL(dma_map_sg);
-
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
-        unsigned long offset, size_t size, enum dma_data_direction direction)
+static dma_addr_t mips_dma_map_page(struct device *dev, struct page *page,
+        unsigned long offset, size_t size, enum dma_data_direction direction,
+        struct dma_attrs *attrs)
 {
-        BUG_ON(direction == DMA_NONE);
+        unsigned long addr;
 
-        if (!plat_device_is_coherent(dev)) {
-                unsigned long addr;
+        addr = (unsigned long) page_address(page) + offset;
 
-                addr = (unsigned long) page_address(page) + offset;
+        if (!plat_device_is_coherent(dev))
                 __dma_sync(addr, size, direction);
-        }
 
-        return plat_map_dma_mem_page(dev, page) + offset;
+        return plat_map_dma_mem(dev, (void *)addr, size);
 }
 
-EXPORT_SYMBOL(dma_map_page);
-
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
-        enum dma_data_direction direction)
+static void mips_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+        int nhwentries, enum dma_data_direction direction,
+        struct dma_attrs *attrs)
 {
         unsigned long addr;
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         for (i = 0; i < nhwentries; i++, sg++) {
                 if (!plat_device_is_coherent(dev) &&
                     direction != DMA_TO_DEVICE) {
@@ -257,13 +229,9 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
         }
 }
 
-EXPORT_SYMBOL(dma_unmap_sg);
-
-void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-        size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_cpu(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
 {
-        BUG_ON(direction == DMA_NONE);
-
         if (cpu_is_noncoherent_r10000(dev)) {
                 unsigned long addr;
 
@@ -272,13 +240,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
         }
 }
 
-EXPORT_SYMBOL(dma_sync_single_for_cpu);
-
-void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
-        size_t size, enum dma_data_direction direction)
+static void mips_dma_sync_single_for_device(struct device *dev,
+        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction)
 {
-        BUG_ON(direction == DMA_NONE);
-
         plat_extra_sync_for_device(dev);
         if (!plat_device_is_coherent(dev)) {
                 unsigned long addr;
@@ -288,46 +252,11 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
         }
 }
 
-EXPORT_SYMBOL(dma_sync_single_for_device);
-
-void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
-        unsigned long offset, size_t size, enum dma_data_direction direction)
-{
-        BUG_ON(direction == DMA_NONE);
-
-        if (cpu_is_noncoherent_r10000(dev)) {
-                unsigned long addr;
-
-                addr = dma_addr_to_virt(dev, dma_handle);
-                __dma_sync(addr + offset, size, direction);
-        }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
-
-void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
-        unsigned long offset, size_t size, enum dma_data_direction direction)
-{
-        BUG_ON(direction == DMA_NONE);
-
-        plat_extra_sync_for_device(dev);
-        if (!plat_device_is_coherent(dev)) {
-                unsigned long addr;
-
-                addr = dma_addr_to_virt(dev, dma_handle);
-                __dma_sync(addr + offset, size, direction);
-        }
-}
-
-EXPORT_SYMBOL(dma_sync_single_range_for_device);
-
-void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
-        enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_cpu(struct device *dev,
+        struct scatterlist *sg, int nelems, enum dma_data_direction direction)
 {
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         /* Make sure that gcc doesn't leave the empty loop body.  */
         for (i = 0; i < nelems; i++, sg++) {
                 if (cpu_is_noncoherent_r10000(dev))
@@ -336,15 +265,11 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
         }
 }
 
-EXPORT_SYMBOL(dma_sync_sg_for_cpu);
-
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
-        enum dma_data_direction direction)
+static void mips_dma_sync_sg_for_device(struct device *dev,
+        struct scatterlist *sg, int nelems, enum dma_data_direction direction)
 {
         int i;
 
-        BUG_ON(direction == DMA_NONE);
-
         /* Make sure that gcc doesn't leave the empty loop body.  */
         for (i = 0; i < nelems; i++, sg++) {
                 if (!plat_device_is_coherent(dev))
@@ -353,24 +278,18 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nele
         }
 }
 
-EXPORT_SYMBOL(dma_sync_sg_for_device);
-
-int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
         return plat_dma_mapping_error(dev, dma_addr);
 }
 
-EXPORT_SYMBOL(dma_mapping_error);
-
-int dma_supported(struct device *dev, u64 mask)
+int mips_dma_supported(struct device *dev, u64 mask)
 {
         return plat_dma_supported(dev, mask);
 }
 
-EXPORT_SYMBOL(dma_supported);
-
-void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-               enum dma_data_direction direction)
+void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+                         enum dma_data_direction direction)
 {
         BUG_ON(direction == DMA_NONE);
 
@@ -379,4 +298,30 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                 __dma_sync((unsigned long)vaddr, size, direction);
 }
 
-EXPORT_SYMBOL(dma_cache_sync);
+static struct dma_map_ops mips_default_dma_map_ops = {
+        .alloc_coherent = mips_dma_alloc_coherent,
+        .free_coherent = mips_dma_free_coherent,
+        .map_page = mips_dma_map_page,
+        .unmap_page = mips_dma_unmap_page,
+        .map_sg = mips_dma_map_sg,
+        .unmap_sg = mips_dma_unmap_sg,
+        .sync_single_for_cpu = mips_dma_sync_single_for_cpu,
+        .sync_single_for_device = mips_dma_sync_single_for_device,
+        .sync_sg_for_cpu = mips_dma_sync_sg_for_cpu,
+        .sync_sg_for_device = mips_dma_sync_sg_for_device,
+        .mapping_error = mips_dma_mapping_error,
+        .dma_supported = mips_dma_supported
+};
+
+struct dma_map_ops *mips_dma_map_ops = &mips_default_dma_map_ops;
+EXPORT_SYMBOL(mips_dma_map_ops);
+
+#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
+
+static int __init mips_dma_init(void)
+{
+        dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+
+        return 0;
+}
+fs_initcall(mips_dma_init);
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 783ad0065fdf..137ee76a0045 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -18,6 +18,7 @@
 #include <linux/smp.h>
 #include <linux/module.h>
 #include <linux/kprobes.h>
+#include <linux/perf_event.h>
 
 #include <asm/branch.h>
 #include <asm/mmu_context.h>
@@ -144,6 +145,7 @@ good_area:
          * the fault.
          */
         fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
                         goto out_of_memory;
@@ -151,10 +153,15 @@ good_area:
                         goto do_sigbus;
                 BUG();
         }
-        if (fault & VM_FAULT_MAJOR)
+        if (fault & VM_FAULT_MAJOR) {
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
+                                1, 0, regs, address);
                 tsk->maj_flt++;
-        else
+        } else {
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
+                                1, 0, regs, address);
                 tsk->min_flt++;
+        }
 
         up_read(&mm->mmap_sem);
         return;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5ab5fa8c1d82..505fecad4684 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -57,6 +57,34 @@ static struct bcache_ops mips_sc_ops = {
         .bc_inv = mips_sc_inv
 };
 
+/*
+ * Check if the L2 cache controller is activated on a particular platform.
+ * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
+ * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
+ * cache being disabled.  However there is no guarantee for this to be
+ * true on all platforms.  In an act of stupidity the spec defined bits
+ * 12..15 as implementation defined so below function will eventually have
+ * to be replaced by a platform specific probe.
+ */
+static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
+{
+        /* Check the bypass bit (L2B) */
+        switch (c->cputype) {
+        case CPU_34K:
+        case CPU_74K:
+        case CPU_1004K:
+        case CPU_BMIPS5000:
+                if (config2 & (1 << 12))
+                        return 0;
+        }
+
+        tmp = (config2 >> 4) & 0x0f;
+        if (0 < tmp && tmp <= 7)
+                c->scache.linesz = 2 << tmp;
+        else
+                return 0;
+}
+
 static inline int __init mips_sc_probe(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
@@ -79,10 +107,8 @@ static inline int __init mips_sc_probe(void)
                 return 0;
 
         config2 = read_c0_config2();
-        tmp = (config2 >> 4) & 0x0f;
-        if (0 < tmp && tmp <= 7)
-                c->scache.linesz = 2 << tmp;
-        else
+
+        if (!mips_sc_is_activated(c))
                 return 0;
 
         tmp = (config2 >> 8) & 0x0f;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 4510e61883eb..93816f3bca67 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -338,13 +338,12 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_4KSC:
         case CPU_20KC:
         case CPU_25KF:
-        case CPU_BCM3302:
-        case CPU_BCM4710:
+        case CPU_BMIPS32:
+        case CPU_BMIPS3300:
+        case CPU_BMIPS4350:
+        case CPU_BMIPS4380:
+        case CPU_BMIPS5000:
         case CPU_LOONGSON2:
-        case CPU_BCM6338:
-        case CPU_BCM6345:
-        case CPU_BCM6348:
-        case CPU_BCM6358:
         case CPU_R5500:
                 if (m4kc_tlbp_war())
                         uasm_i_nop(p);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index d2647a4e012b..23afdebc8e5c 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -405,7 +405,6 @@ I_u1u2u3(_mfc0)
 I_u1u2u3(_mtc0)
 I_u2u1u3(_ori)
 I_u3u1u2(_or)
-I_u2s3u1(_pref)
 I_0(_rfe)
 I_u2s3u1(_sc)
 I_u2s3u1(_scd)
@@ -427,6 +426,25 @@ I_u1(_syscall);
 I_u1u2s3(_bbit0);
 I_u1u2s3(_bbit1);
 
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#include <asm/octeon/octeon.h>
+void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
+                            unsigned int c)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
+                /*
+                 * As per erratum Core-14449, replace prefetches 0-4,
+                 * 6-24 with 'pref 28'.
+                 */
+                build_insn(buf, insn_pref, c, 28, b);
+        else
+                build_insn(buf, insn_pref, c, a, b);
+}
+UASM_EXPORT_SYMBOL(uasm_i_pref);
+#else
+I_u2s3u1(_pref)
+#endif
+
 /* Handle labels. */
 void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
 {
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index d248b707eff3..2d74fc9ae3ba 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -11,6 +11,7 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/delay.h>
+#include <linux/swiotlb.h>
 
 #include <asm/time.h>
 
@@ -19,6 +20,8 @@
 #include <asm/octeon/cvmx-pci-defs.h>
 #include <asm/octeon/pci-octeon.h>
 
+#include <dma-coherence.h>
+
 #define USE_OCTEON_INTERNAL_ARBITER
 
 /*
@@ -32,6 +35,8 @@
 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
 
+u64 octeon_bar1_pci_phys;
+
 /**
  * This is the bit decoding used for the Octeon PCI controller addresses
  */
@@ -170,6 +175,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
                 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
         }
 
+        dev->dev.archdata.dma_ops = octeon_pci_dma_map_ops;
+
         return 0;
 }
 
@@ -618,12 +625,10 @@ static int __init octeon_pci_setup(void)
          * before the readl()'s below. We don't want BAR2 overlapping
          * with BAR0/BAR1 during these reads.
          */
-        octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
-        octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
-
-        /* Disable the BAR1 movable mappings */
-        for (index = 0; index < 32; index++)
-                octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
+        octeon_npi_write32(CVMX_NPI_PCI_CFG08,
+                           (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull));
+        octeon_npi_write32(CVMX_NPI_PCI_CFG09,
+                           (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32));
 
         if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
                 /* Remap the Octeon BAR 0 to 0-2GB */
@@ -637,6 +642,25 @@ static int __init octeon_pci_setup(void)
                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
 
+                /* BAR1 movable mappings set for identity mapping */
+                octeon_bar1_pci_phys = 0x80000000ull;
+                for (index = 0; index < 32; index++) {
+                        union cvmx_pci_bar1_indexx bar1_index;
+
+                        bar1_index.u32 = 0;
+                        /* Address bits[35:22] sent to L2C */
+                        bar1_index.s.addr_idx =
+                                (octeon_bar1_pci_phys >> 22) + index;
+                        /* Don't put PCI accesses in L2. */
+                        bar1_index.s.ca = 1;
+                        /* Endian Swap Mode */
+                        bar1_index.s.end_swp = 1;
+                        /* Set '1' when the selected address range is valid. */
+                        bar1_index.s.addr_v = 1;
+                        octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+                                           bar1_index.u32);
+                }
+
                 /* Devices go after BAR1 */
                 octeon_pci_mem_resource.start =
                         OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
@@ -652,6 +676,27 @@ static int __init octeon_pci_setup(void)
                 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
                 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
 
+                /* BAR1 movable regions contiguous to cover the swiotlb */
+                octeon_bar1_pci_phys =
+                        virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1);
+
+                for (index = 0; index < 32; index++) {
+                        union cvmx_pci_bar1_indexx bar1_index;
+
+                        bar1_index.u32 = 0;
+                        /* Address bits[35:22] sent to L2C */
+                        bar1_index.s.addr_idx =
+                                (octeon_bar1_pci_phys >> 22) + index;
+                        /* Don't put PCI accesses in L2. */
+                        bar1_index.s.ca = 1;
+                        /* Endian Swap Mode */
+                        bar1_index.s.end_swp = 1;
+                        /* Set '1' when the selected address range is valid. */
+                        bar1_index.s.addr_v = 1;
+                        octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+                                           bar1_index.u32);
+                }
+
                 /* Devices go after BAR0 */
                 octeon_pci_mem_resource.start =
                         OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
@@ -667,6 +712,9 @@ static int __init octeon_pci_setup(void)
          * was setup properly.
          */
         cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
+
+        octeon_pci_dma_init();
+
         return 0;
 }
 
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 861361e0c9af..385f035b24e4 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -75,6 +75,8 @@ union cvmx_pcie_address {
         } mem;
 };
 
+#include <dma-coherence.h>
+
 /**
  * Return the Core virtual base address for PCIe IO access. IOs are
  * read/written as an offset from this address.
@@ -1391,6 +1393,9 @@ static int __init octeon_pcie_setup(void)
                         cvmx_pcie_get_io_size(1) - 1;
                 register_pci_controller(&octeon_pcie1_controller);
         }
+
+        octeon_pci_dma_init();
+
         return 0;
 }
 
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 365766a3d536..41ba38513c89 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux Kernel Configuration"
-
 config MN10300
         def_bool y
         select HAVE_OPROFILE
@@ -93,8 +86,6 @@ config GENERIC_HARDIRQS
 config HOTPLUG_CPU
         def_bool n
 
-mainmenu "Panasonic MN10300/AM33 Kernel Configuration"
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 79a04a9394d5..0888675c98dd 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux/PA-RISC Kernel Configuration"
-
 config PARISC
         def_bool y
         select HAVE_IDE
@@ -19,6 +12,7 @@ config PARISC
         select HAVE_IRQ_WORK
         select HAVE_PERF_EVENTS
         select GENERIC_ATOMIC64 if !64BIT
+        select GENERIC_HARDIRQS_NO__DO_IRQ
         help
           The PA-RISC microprocessor is designed by Hewlett-Packard and used
           in many of their workstations & servers (HP9000 700 and 800 series,
@@ -85,6 +79,9 @@ config IRQ_PER_CPU
         bool
         default y
 
+config GENERIC_HARDIRQS_NO__DO_IRQ
+        def_bool y
+
 # unless you want to implement ACPI on PA-RISC ... ;-)
 config PM
         bool
diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 039880e7d2c9..47f11c707b65 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -24,8 +24,6 @@
 
 #ifndef __ASSEMBLY__
 
-#define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
-
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
 
 #define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index dba11aedce1b..f388a85bba11 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -126,20 +126,20 @@ static inline void *kmap(struct page *page)
 
 #define kunmap(page)                    kunmap_parisc(page_address(page))
 
-static inline void *kmap_atomic(struct page *page, enum km_type idx)
+static inline void *__kmap_atomic(struct page *page)
 {
         pagefault_disable();
         return page_address(page);
 }
 
-static inline void kunmap_atomic_notypecheck(void *addr, enum km_type idx)
+static inline void __kunmap_atomic(void *addr)
 {
         kunmap_parisc(addr);
         pagefault_enable();
 }
 
-#define kmap_atomic_prot(page, idx, prot)       kmap_atomic(page, idx)
-#define kmap_atomic_pfn(pfn, idx)       kmap_atomic(pfn_to_page(pfn), (idx))
+#define kmap_atomic_prot(page, prot)    kmap_atomic(page)
+#define kmap_atomic_pfn(pfn)    kmap_atomic(pfn_to_page(pfn))
 #define kmap_atomic_to_page(ptr)        virt_to_page(ptr)
 #endif
 
diff --git a/arch/parisc/include/asm/irq.h b/arch/parisc/include/asm/irq.h
index dfa26b67f919..c67dccf2e31f 100644
--- a/arch/parisc/include/asm/irq.h
+++ b/arch/parisc/include/asm/irq.h
@@ -40,7 +40,7 @@ struct irq_chip;
 void no_ack_irq(unsigned int irq);
 void no_end_irq(unsigned int irq);
 void cpu_ack_irq(unsigned int irq);
-void cpu_end_irq(unsigned int irq);
+void cpu_eoi_irq(unsigned int irq);
 
 extern int txn_alloc_irq(unsigned int nbits);
 extern int txn_claim_irq(int);
diff --git a/arch/parisc/include/asm/unistd.h b/arch/parisc/include/asm/unistd.h
index 1ce7d2851d90..3eb82c2a5ec3 100644
--- a/arch/parisc/include/asm/unistd.h
+++ b/arch/parisc/include/asm/unistd.h
@@ -813,8 +813,9 @@
 #define __NR_perf_event_open    (__NR_Linux + 318)
 #define __NR_recvmmsg           (__NR_Linux + 319)
 #define __NR_accept4            (__NR_Linux + 320)
+#define __NR_prlimit64          (__NR_Linux + 321)
 
-#define __NR_Linux_syscalls     (__NR_accept4 + 1)
+#define __NR_Linux_syscalls     (__NR_prlimit64 + 1)
 
 
 #define __IGNORE_select         /* newselect */
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index efbcee5d2220..5024f643b3b1 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -52,7 +52,7 @@ static volatile unsigned long cpu_eiem = 0;
 */
 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
 
-static void cpu_disable_irq(unsigned int irq)
+static void cpu_mask_irq(unsigned int irq)
 {
         unsigned long eirr_bit = EIEM_MASK(irq);
 
@@ -63,7 +63,7 @@ static void cpu_disable_irq(unsigned int irq)
          * then gets disabled */
 }
 
-static void cpu_enable_irq(unsigned int irq)
+static void cpu_unmask_irq(unsigned int irq)
 {
         unsigned long eirr_bit = EIEM_MASK(irq);
 
@@ -75,12 +75,6 @@ static void cpu_enable_irq(unsigned int irq)
         smp_send_all_nop();
 }
 
-static unsigned int cpu_startup_irq(unsigned int irq)
-{
-        cpu_enable_irq(irq);
-        return 0;
-}
-
 void no_ack_irq(unsigned int irq) { }
 void no_end_irq(unsigned int irq) { }
 
@@ -99,7 +93,7 @@ void cpu_ack_irq(unsigned int irq)
         mtctl(mask, 23);
 }
 
-void cpu_end_irq(unsigned int irq)
+void cpu_eoi_irq(unsigned int irq)
 {
         unsigned long mask = EIEM_MASK(irq);
         int cpu = smp_processor_id();
@@ -146,12 +140,10 @@ static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest)
 
 static struct irq_chip cpu_interrupt_type = {
         .name           = "CPU",
-        .startup        = cpu_startup_irq,
-        .shutdown       = cpu_disable_irq,
-        .enable         = cpu_enable_irq,
-        .disable        = cpu_disable_irq,
+        .mask           = cpu_mask_irq,
+        .unmask         = cpu_unmask_irq,
         .ack            = cpu_ack_irq,
-        .end            = cpu_end_irq,
+        .eoi            = cpu_eoi_irq,
 #ifdef CONFIG_SMP
         .set_affinity   = cpu_set_affinity_irq,
 #endif
@@ -247,10 +239,11 @@ int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
         if (irq_desc[irq].chip != &cpu_interrupt_type)
                 return -EBUSY;
 
+        /* for iosapic interrupts */
         if (type) {
-                irq_desc[irq].chip = type;
-                irq_desc[irq].chip_data = data;
-                cpu_interrupt_type.enable(irq);
+                set_irq_chip_and_handler(irq, type, handle_level_irq);
+                set_irq_chip_data(irq, data);
+                cpu_unmask_irq(irq);
         }
         return 0;
 }
@@ -368,7 +361,7 @@ void do_cpu_irq_mask(struct pt_regs *regs)
                 goto set_out;
         }
 #endif
-        __do_IRQ(irq);
+        generic_handle_irq(irq);
 
  out:
         irq_exit();
@@ -398,14 +391,15 @@ static void claim_cpu_irqs(void)
 {
         int i;
         for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
-                irq_desc[i].chip = &cpu_interrupt_type;
+                set_irq_chip_and_handler(i, &cpu_interrupt_type,
+                        handle_level_irq);
         }
 
-        irq_desc[TIMER_IRQ].action = &timer_action;
-        irq_desc[TIMER_IRQ].status = IRQ_PER_CPU;
+        set_irq_handler(TIMER_IRQ, handle_percpu_irq);
+        setup_irq(TIMER_IRQ, &timer_action);
 #ifdef CONFIG_SMP
-        irq_desc[IPI_IRQ].action = &ipi_action;
-        irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
+        set_irq_handler(IPI_IRQ, handle_percpu_irq);
+        setup_irq(IPI_IRQ, &ipi_action);
 #endif
 }
 
@@ -423,3 +417,4 @@ void __init init_IRQ(void)
         set_eiem(cpu_eiem);     /* EIEM : enable all external intr */
 
 }
+
diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c
index 1ff366cb9685..66d1f17fdb94 100644
--- a/arch/parisc/kernel/pdc_cons.c
+++ b/arch/parisc/kernel/pdc_cons.c
@@ -12,6 +12,7 @@
  *    Copyright (C) 2001 Helge Deller <deller at parisc-linux.org>
  *    Copyright (C) 2001 Thomas Bogendoerfer <tsbogend at parisc-linux.org>
  *    Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
+ *    Copyright (C) 2010 Guy Martin <gmsoft at tuxicoman.be>
  *
  *
  *    This program is free software; you can redistribute it and/or modify
@@ -31,12 +32,11 @@
 
 /*
  *  The PDC console is a simple console, which can be used for debugging 
- *  boot related problems on HP PA-RISC machines.
+ *  boot related problems on HP PA-RISC machines. It is also useful when no
+ *  other console works.
  *
  *  This code uses the ROM (=PDC) based functions to read and write characters
  *  from and to PDC's boot path.
- *  Since all character read from that path must be polled, this code never
- *  can or will be a fully functional linux console.
  */
 
 /* Define EARLY_BOOTUP_DEBUG to debug kernel related boot problems. 
@@ -53,6 +53,7 @@
 #include <asm/pdc.h>            /* for iodc_call() proto and friends */
 
 static DEFINE_SPINLOCK(pdc_console_lock);
+static struct console pdc_cons;
 
 static void pdc_console_write(struct console *co, const char *s, unsigned count)
 {
@@ -85,12 +86,138 @@ static int pdc_console_setup(struct console *co, char *options)
 
 #if defined(CONFIG_PDC_CONSOLE)
 #include <linux/vt_kern.h>
+#include <linux/tty_flip.h>
+
+#define PDC_CONS_POLL_DELAY (30 * HZ / 1000)
+
+static struct timer_list pdc_console_timer;
+
+extern struct console * console_drivers;
+
+static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
+{
+
+        mod_timer(&pdc_console_timer, jiffies + PDC_CONS_POLL_DELAY);
+
+        return 0;
+}
+
+static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp)
+{
+        if (!tty->count)
+                del_timer(&pdc_console_timer);
+}
+
+static int pdc_console_tty_write(struct tty_struct *tty, const unsigned char *buf, int count)
+{
+        pdc_console_write(NULL, buf, count);
+        return count;
+}
+
+static int pdc_console_tty_write_room(struct tty_struct *tty)
+{
+        return 32768; /* no limit, no buffer used */
+}
+
+static int pdc_console_tty_chars_in_buffer(struct tty_struct *tty)
+{
+        return 0; /* no buffer */
+}
+
+static struct tty_driver *pdc_console_tty_driver;
+
+static const struct tty_operations pdc_console_tty_ops = {
+        .open = pdc_console_tty_open,
+        .close = pdc_console_tty_close,
+        .write = pdc_console_tty_write,
+        .write_room = pdc_console_tty_write_room,
+        .chars_in_buffer = pdc_console_tty_chars_in_buffer,
+};
+
+static void pdc_console_poll(unsigned long unused)
+{
+
+        int data, count = 0;
+
+        struct tty_struct *tty = pdc_console_tty_driver->ttys[0];
+
+        if (!tty)
+                return;
+
+        while (1) {
+                data = pdc_console_poll_key(NULL);
+                if (data == -1)
+                        break;
+                tty_insert_flip_char(tty, data & 0xFF, TTY_NORMAL);
+                count ++;
+        }
+
+        if (count)
+                tty_flip_buffer_push(tty);
+
+        if (tty->count && (pdc_cons.flags & CON_ENABLED))
+                mod_timer(&pdc_console_timer, jiffies + PDC_CONS_POLL_DELAY);
+}
+
+static int __init pdc_console_tty_driver_init(void)
+{
+
+        int err;
+        struct tty_driver *drv;
+
+        /* Check if the console driver is still registered.
+         * It is unregistered if the pdc console was not selected as the
+         * primary console. */
+
+        struct console *tmp = console_drivers;
+
+        for (tmp = console_drivers; tmp; tmp = tmp->next)
+                if (tmp == &pdc_cons)
+                        break;
+
+        if (!tmp) {
+                printk(KERN_INFO "PDC console driver not registered anymore, not creating %s\n", pdc_cons.name);
+                return -ENODEV;
+        }
+
+        printk(KERN_INFO "The PDC console driver is still registered, removing CON_BOOT flag\n");
+        pdc_cons.flags &= ~CON_BOOT;
+
+        drv = alloc_tty_driver(1);
+
+        if (!drv)
+                return -ENOMEM;
+
+        drv->driver_name = "pdc_cons";
+        drv->name = "ttyB";
+        drv->major = MUX_MAJOR;
+        drv->minor_start = 0;
+        drv->type = TTY_DRIVER_TYPE_SYSTEM;
+        drv->init_termios = tty_std_termios;
+        drv->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_RESET_TERMIOS;
+        tty_set_operations(drv, &pdc_console_tty_ops);
+
+        err = tty_register_driver(drv);
+        if (err) {
+                printk(KERN_ERR "Unable to register the PDC console TTY driver\n");
+                return err;
+        }
+
+        pdc_console_tty_driver = drv;
+
+        /* No need to initialize the pdc_console_timer if tty isn't allocated */
+        init_timer(&pdc_console_timer);
+        pdc_console_timer.function = pdc_console_poll;
+
+        return 0;
+}
+
+module_init(pdc_console_tty_driver_init);
 
 static struct tty_driver * pdc_console_device (struct console *c, int *index)
 {
-        extern struct tty_driver console_driver;
-        *index = c->index ? c->index-1 : fg_console;
-        return &console_driver;
+        *index = c->index;
+        return pdc_console_tty_driver;
 }
 #else
 #define pdc_console_device NULL
@@ -101,7 +228,7 @@ static struct console pdc_cons = {
         .write =        pdc_console_write,
         .device =       pdc_console_device,
         .setup =        pdc_console_setup,
-        .flags =        CON_BOOT | CON_PRINTBUFFER | CON_ENABLED,
+        .flags =        CON_BOOT | CON_PRINTBUFFER,
         .index =        -1,
 };
 
diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S
index 3d52c978738f..74867dfdabe5 100644
--- a/arch/parisc/kernel/syscall_table.S
+++ b/arch/parisc/kernel/syscall_table.S
@@ -419,6 +419,7 @@
         ENTRY_SAME(perf_event_open)
         ENTRY_COMP(recvmmsg)
         ENTRY_SAME(accept4)             /* 320 */
+        ENTRY_SAME(prlimit64)
 
         /* Nothing yet */
 
diff --git a/arch/parisc/kernel/unaligned.c b/arch/parisc/kernel/unaligned.c
index 92d977bb5ea8..234e3682cf09 100644
--- a/arch/parisc/kernel/unaligned.c
+++ b/arch/parisc/kernel/unaligned.c
@@ -619,15 +619,12 @@ void handle_unaligned(struct pt_regs *regs)
                 flop=1;
                 ret = emulate_std(regs, R2(regs->iir),1);
                 break;
-
-#ifdef CONFIG_PA20
         case OPCODE_LDD_L:
                 ret = emulate_ldd(regs, R2(regs->iir),0);
                 break;
         case OPCODE_STD_L:
                 ret = emulate_std(regs, R2(regs->iir),0);
                 break;
-#endif
         }
 #endif
         switch (regs->iir & OPCODE3_MASK)
diff --git a/arch/parisc/kernel/unwind.c b/arch/parisc/kernel/unwind.c
index d58eac1a8288..76ed62ed785b 100644
--- a/arch/parisc/kernel/unwind.c
+++ b/arch/parisc/kernel/unwind.c
@@ -80,8 +80,11 @@ find_unwind_entry(unsigned long addr)
                         if (addr >= table->start && 
                             addr <= table->end)
                                 e = find_unwind_entry_in_table(table, addr);
-                        if (e)
+                        if (e) {
+                                /* Move-to-front to exploit common traces */
+                                list_move(&table->list, &unwind_tables);
                                 break;
+                        }
                 }
 
         return e;
diff --git a/arch/parisc/math-emu/Makefile b/arch/parisc/math-emu/Makefile
index 1f3f225897f5..0bd63b08a79a 100644
--- a/arch/parisc/math-emu/Makefile
+++ b/arch/parisc/math-emu/Makefile
@@ -3,7 +3,7 @@
 #
 
 # See arch/parisc/math-emu/README
-EXTRA_CFLAGS += -Wno-parentheses -Wno-implicit-function-declaration \
+ccflags-y := -Wno-parentheses -Wno-implicit-function-declaration \
         -Wno-uninitialized -Wno-strict-prototypes -Wno-return-type \
         -Wno-implicit-int
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 4b1e521d966f..b6447190e1a2 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -1,9 +1,3 @@
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux/PowerPC Kernel Configuration"
-
 source "arch/powerpc/platforms/Kconfig.cputype"
 
 config PPC32
@@ -688,9 +682,12 @@ config 4xx_SOC
         bool
 
 config FSL_LBC
-        bool
+        bool "Freescale Local Bus support"
+        depends on FSL_SOC
         help
-          Freescale Localbus support
+          Enables reporting of errors from the Freescale local bus
+          controller.  Also contains some common code used by
+          drivers for specific local bus peripherals.
 
 config FSL_GTM
         bool
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 1b5a21041f9b..5c1bf3466749 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -1,9 +1,10 @@
 /* Freescale Local Bus Controller
  *
- * Copyright (c) 2006-2007 Freescale Semiconductor
+ * Copyright © 2006-2007, 2010 Freescale Semiconductor
  *
  * Authors: Nick Spence <nick.spence@freescale.com>,
  *          Scott Wood <scottwood@freescale.com>
+ *          Jack Lan <jack.lan@freescale.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,6 +27,8 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <linux/io.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
 
 struct fsl_lbc_bank {
         __be32 br;             /**< Base Register  */
@@ -125,13 +128,23 @@ struct fsl_lbc_regs {
 #define LTESR_ATMW 0x00800000
 #define LTESR_ATMR 0x00400000
 #define LTESR_CS   0x00080000
+#define LTESR_UPM  0x00000002
 #define LTESR_CC   0x00000001
 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
+#define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
+                         | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
+                         | LTESR_CC)
+#define LTESR_CLEAR     0xFFFFFFFF
+#define LTECCR_CLEAR    0xFFFFFFFF
+#define LTESR_STATUS    LTESR_MASK
+#define LTEIR_ENABLE    LTESR_MASK
+#define LTEDR_ENABLE    0x00000000
         __be32 ltedr;           /**< Transfer Error Disable Register */
         __be32 lteir;           /**< Transfer Error Interrupt Register */
         __be32 lteatr;          /**< Transfer Error Attributes Register */
         __be32 ltear;           /**< Transfer Error Address Register */
-        u8 res6[0xC];
+        __be32 lteccr;          /**< Transfer Error ECC Register */
+        u8 res6[0x8];
         __be32 lbcr;            /**< Configuration Register */
 #define LBCR_LDIS  0x80000000
 #define LBCR_LDIS_SHIFT    31
@@ -235,6 +248,7 @@ struct fsl_upm {
         int width;
 };
 
+extern u32 fsl_lbc_addr(phys_addr_t addr_base);
 extern int fsl_lbc_find(phys_addr_t addr_base);
 extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
 
@@ -265,7 +279,23 @@ static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
                 cpu_relax();
 }
 
+/* overview of the fsl lbc controller */
+
+struct fsl_lbc_ctrl {
+        /* device info */
+        struct device                   *dev;
+        struct fsl_lbc_regs __iomem     *regs;
+        int                             irq;
+        wait_queue_head_t               irq_wait;
+        spinlock_t                      lock;
+        void                            *nand;
+
+        /* status read from LTESR by irq handler */
+        unsigned int                    irq_status;
+};
+
 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
                                u32 mar);
+extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
 
 #endif /* __ASM_FSL_LBC_H */
diff --git a/arch/powerpc/include/asm/kgdb.h b/arch/powerpc/include/asm/kgdb.h
index edd217006d27..9db24e77b9f4 100644
--- a/arch/powerpc/include/asm/kgdb.h
+++ b/arch/powerpc/include/asm/kgdb.h
@@ -31,6 +31,7 @@ static inline void arch_kgdb_breakpoint(void)
         asm(".long 0x7d821008"); /* twge r2, r2 */
 }
 #define CACHE_FLUSH_IS_SAFE     1
+#define DBG_MAX_REG_NUM     70
 
 /* The number bytes of registers we have to save depends on a few
  * things.  For 64bit we default to not including vector registers and
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index 7f61a3ac787c..7a9db64f3f04 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -194,40 +194,6 @@ static int kgdb_dabr_match(struct pt_regs *regs)
         ptr = (unsigned long *)ptr32; \
         } while (0)
 
-
-void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
-{
-        unsigned long *ptr = gdb_regs;
-        int reg;
-
-        memset(gdb_regs, 0, NUMREGBYTES);
-
-        for (reg = 0; reg < 32; reg++)
-                PACK64(ptr, regs->gpr[reg]);
-
-#ifdef CONFIG_FSL_BOOKE
-#ifdef CONFIG_SPE
-        for (reg = 0; reg < 32; reg++)
-                PACK64(ptr, current->thread.evr[reg]);
-#else
-        ptr += 32;
-#endif
-#else
-        /* fp registers not used by kernel, leave zero */
-        ptr += 32 * 8 / sizeof(long);
-#endif
-
-        PACK64(ptr, regs->nip);
-        PACK64(ptr, regs->msr);
-        PACK32(ptr, regs->ccr);
-        PACK64(ptr, regs->link);
-        PACK64(ptr, regs->ctr);
-        PACK32(ptr, regs->xer);
-
-        BUG_ON((unsigned long)ptr >
-               (unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
-}
-
 void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
 {
         struct pt_regs *regs = (struct pt_regs *)(p->thread.ksp +
@@ -271,44 +237,140 @@ void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
                (unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
 }
 
-#define UNPACK64(dest, ptr) do { dest = *(ptr++); } while (0)
+#define GDB_SIZEOF_REG sizeof(unsigned long)
+#define GDB_SIZEOF_REG_U32 sizeof(u32)
 
-#define UNPACK32(dest, ptr) do {       \
-        u32 *ptr32;                   \
-        ptr32 = (u32 *)ptr;           \
-        dest = *(ptr32++);            \
-        ptr = (unsigned long *)ptr32; \
-        } while (0)
+#ifdef CONFIG_FSL_BOOKE
+#define GDB_SIZEOF_FLOAT_REG sizeof(unsigned long)
+#else
+#define GDB_SIZEOF_FLOAT_REG sizeof(u64)
+#endif
 
-void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
+struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
 {
-        unsigned long *ptr = gdb_regs;
-        int reg;
-
-        for (reg = 0; reg < 32; reg++)
-                UNPACK64(regs->gpr[reg], ptr);
+        { "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[0]) },
+        { "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[1]) },
+        { "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[2]) },
+        { "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[3]) },
+        { "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[4]) },
+        { "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[5]) },
+        { "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[6]) },
+        { "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[7]) },
+        { "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[8]) },
+        { "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[9]) },
+        { "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[10]) },
+        { "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[11]) },
+        { "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[12]) },
+        { "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[13]) },
+        { "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[14]) },
+        { "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[15]) },
+        { "r16", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[16]) },
+        { "r17", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[17]) },
+        { "r18", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[18]) },
+        { "r19", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[19]) },
+        { "r20", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[20]) },
+        { "r21", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[21]) },
+        { "r22", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[22]) },
+        { "r23", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[23]) },
+        { "r24", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[24]) },
+        { "r25", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[25]) },
+        { "r26", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[26]) },
+        { "r27", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[27]) },
+        { "r28", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[28]) },
+        { "r29", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[29]) },
+        { "r30", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[30]) },
+        { "r31", GDB_SIZEOF_REG, offsetof(struct pt_regs, gpr[31]) },
+
+        { "f0", GDB_SIZEOF_FLOAT_REG, 0 },
+        { "f1", GDB_SIZEOF_FLOAT_REG, 1 },
+        { "f2", GDB_SIZEOF_FLOAT_REG, 2 },
+        { "f3", GDB_SIZEOF_FLOAT_REG, 3 },
+        { "f4", GDB_SIZEOF_FLOAT_REG, 4 },
+        { "f5", GDB_SIZEOF_FLOAT_REG, 5 },
+        { "f6", GDB_SIZEOF_FLOAT_REG, 6 },
+        { "f7", GDB_SIZEOF_FLOAT_REG, 7 },
+        { "f8", GDB_SIZEOF_FLOAT_REG, 8 },
+        { "f9", GDB_SIZEOF_FLOAT_REG, 9 },
+        { "f10", GDB_SIZEOF_FLOAT_REG, 10 },
+        { "f11", GDB_SIZEOF_FLOAT_REG, 11 },
+        { "f12", GDB_SIZEOF_FLOAT_REG, 12 },
+        { "f13", GDB_SIZEOF_FLOAT_REG, 13 },
+        { "f14", GDB_SIZEOF_FLOAT_REG, 14 },
+        { "f15", GDB_SIZEOF_FLOAT_REG, 15 },
+        { "f16", GDB_SIZEOF_FLOAT_REG, 16 },
+        { "f17", GDB_SIZEOF_FLOAT_REG, 17 },
+        { "f18", GDB_SIZEOF_FLOAT_REG, 18 },
+        { "f19", GDB_SIZEOF_FLOAT_REG, 19 },
+        { "f20", GDB_SIZEOF_FLOAT_REG, 20 },
+        { "f21", GDB_SIZEOF_FLOAT_REG, 21 },
+        { "f22", GDB_SIZEOF_FLOAT_REG, 22 },
+        { "f23", GDB_SIZEOF_FLOAT_REG, 23 },
+        { "f24", GDB_SIZEOF_FLOAT_REG, 24 },
+        { "f25", GDB_SIZEOF_FLOAT_REG, 25 },
+        { "f26", GDB_SIZEOF_FLOAT_REG, 26 },
+        { "f27", GDB_SIZEOF_FLOAT_REG, 27 },
+        { "f28", GDB_SIZEOF_FLOAT_REG, 28 },
+        { "f29", GDB_SIZEOF_FLOAT_REG, 29 },
+        { "f30", GDB_SIZEOF_FLOAT_REG, 30 },
+        { "f31", GDB_SIZEOF_FLOAT_REG, 31 },
+
+        { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, nip) },
+        { "msr", GDB_SIZEOF_REG, offsetof(struct pt_regs, msr) },
+        { "cr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ccr) },
+        { "lr", GDB_SIZEOF_REG, offsetof(struct pt_regs, link) },
+        { "ctr", GDB_SIZEOF_REG_U32, offsetof(struct pt_regs, ctr) },
+        { "xer", GDB_SIZEOF_REG, offsetof(struct pt_regs, xer) },
+};
 
-#ifdef CONFIG_FSL_BOOKE
-#ifdef CONFIG_SPE
-        for (reg = 0; reg < 32; reg++)
-                UNPACK64(current->thread.evr[reg], ptr);
+char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
+{
+        if (regno >= DBG_MAX_REG_NUM || regno < 0)
+                return NULL;
+
+        if (regno < 32 || regno >= 64)
+                /* First 0 -> 31 gpr registers*/
+                /* pc, msr, ls... registers 64 -> 69 */
+                memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
+                                dbg_reg_def[regno].size);
+
+        if (regno >= 32 && regno < 64) {
+                /* FP registers 32 -> 63 */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE)
+                if (current)
+                        memcpy(mem, current->thread.evr[regno-32],
+                                        dbg_reg_def[regno].size);
 #else
-        ptr += 32;
+                /* fp registers not used by kernel, leave zero */
+                memset(mem, 0, dbg_reg_def[regno].size);
 #endif
+        }
+
+        return dbg_reg_def[regno].name;
+}
+
+int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
+{
+        if (regno >= DBG_MAX_REG_NUM || regno < 0)
+                return -EINVAL;
+
+        if (regno < 32 || regno >= 64)
+                /* First 0 -> 31 gpr registers*/
+                /* pc, msr, ls... registers 64 -> 69 */
+                memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
+                                dbg_reg_def[regno].size);
+
+        if (regno >= 32 && regno < 64) {
+                /* FP registers 32 -> 63 */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_SPE)
+                memcpy(current->thread.evr[regno-32], mem,
+                                dbg_reg_def[regno].size);
 #else
-        /* fp registers not used by kernel, leave zero */
-        ptr += 32 * 8 / sizeof(int);
+                /* fp registers not used by kernel, leave zero */
+                return 0;
 #endif
+        }
 
-        UNPACK64(regs->nip, ptr);
-        UNPACK64(regs->msr, ptr);
-        UNPACK32(regs->ccr, ptr);
-        UNPACK64(regs->link, ptr);
-        UNPACK64(regs->ctr, ptr);
-        UNPACK32(regs->xer, ptr);
-
-        BUG_ON((unsigned long)ptr >
-               (unsigned long)(((void *)gdb_regs) + NUMREGBYTES));
+        return 0;
 }
 
 void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long pc)
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 428d0e538aec..b06bdae04064 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -127,7 +127,7 @@ static void kvm_patch_ins_nop(u32 *inst)
 
 static void kvm_patch_ins_b(u32 *inst, int addr)
 {
-#ifdef CONFIG_RELOCATABLE
+#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_PPC_BOOK3S)
         /* On relocatable kernels interrupts handlers and our code
            can be in different regions, so we don't patch them */
 
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S
index 049846911ce4..1cc471faac2d 100644
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@ -416,7 +416,7 @@ lightweight_exit:
         lwz     r3, VCPU_PC(r4)
         mtsrr0  r3
         lwz     r3, VCPU_SHARED(r4)
-        lwz     r3, VCPU_SHARED_MSR(r3)
+        lwz     r3, (VCPU_SHARED_MSR + 4)(r3)
         oris    r3, r3, KVMPPC_MSR_MASK@h
         ori     r3, r3, KVMPPC_MSR_MASK@l
         mtsrr1  r3
diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index 71750f2dd5d3..e3768ee9b595 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -138,8 +138,8 @@ void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
         struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
 
         free_page((unsigned long)vcpu->arch.shared);
-        kvmppc_e500_tlb_uninit(vcpu_e500);
         kvm_vcpu_uninit(vcpu);
+        kvmppc_e500_tlb_uninit(vcpu_e500);
         kmem_cache_free(kvm_vcpu_cache, vcpu_e500);
 }
 
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 2f87a1627f6c..38f756f25053 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -617,6 +617,7 @@ long kvm_arch_vm_ioctl(struct file *filp,
         switch (ioctl) {
         case KVM_PPC_GET_PVINFO: {
                 struct kvm_ppc_pvinfo pvinfo;
+                memset(&pvinfo, 0, sizeof(pvinfo));
                 r = kvm_vm_ioctl_get_pvinfo(&pvinfo);
                 if (copy_to_user(argp, &pvinfo, sizeof(pvinfo))) {
                         r = -EFAULT;
diff --git a/arch/powerpc/kvm/timing.c b/arch/powerpc/kvm/timing.c
index 46fa04f12a9b..a021f5827a33 100644
--- a/arch/powerpc/kvm/timing.c
+++ b/arch/powerpc/kvm/timing.c
@@ -35,7 +35,6 @@ void kvmppc_init_timing_stats(struct kvm_vcpu *vcpu)
         int i;
 
         /* pause guest execution to avoid concurrent updates */
-        local_irq_disable();
         mutex_lock(&vcpu->mutex);
 
         vcpu->arch.last_exit_type = 0xDEAD;
@@ -51,7 +50,6 @@ void kvmppc_init_timing_stats(struct kvm_vcpu *vcpu)
         vcpu->arch.timing_last_enter.tv64 = 0;
 
         mutex_unlock(&vcpu->mutex);
-        local_irq_enable();
 }
 
 static void add_exit_timing(struct kvm_vcpu *vcpu, u64 duration, int type)
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 5dec408d6703..3532b92de983 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -798,17 +798,17 @@ spufs_fill_super(struct super_block *sb, void *data, int silent)
         return spufs_create_root(sb, data);
 }
 
-static int
-spufs_get_sb(struct file_system_type *fstype, int flags,
-                const char *name, void *data, struct vfsmount *mnt)
+static struct dentry *
+spufs_mount(struct file_system_type *fstype, int flags,
+                const char *name, void *data)
 {
-        return get_sb_single(fstype, flags, data, spufs_fill_super, mnt);
+        return mount_single(fstype, flags, data, spufs_fill_super);
 }
 
 static struct file_system_type spufs_type = {
         .owner = THIS_MODULE,
         .name = "spufs",
-        .get_sb = spufs_get_sb,
+        .mount = spufs_mount,
         .kill_sb = kill_litter_super,
 };
 
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index dceb8d1a843d..4fcb5a4e60dd 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -1,9 +1,12 @@
 /*
  * Freescale LBC and UPM routines.
  *
- * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ * Copyright © 2007-2008  MontaVista Software, Inc.
+ * Copyright © 2010 Freescale Semiconductor
  *
  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ * Author: Jack Lan <Jack.Lan@freescale.com>
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,39 +22,37 @@
 #include <linux/types.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mod_devicetable.h>
 #include <asm/prom.h>
 #include <asm/fsl_lbc.h>
 
 static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
-static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
+struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
+EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
 
-static char __initdata *compat_lbc[] = {
-        "fsl,pq2-localbus",
-        "fsl,pq2pro-localbus",
-        "fsl,pq3-localbus",
-        "fsl,elbc",
-};
-
-static int __init fsl_lbc_init(void)
+/**
+ * fsl_lbc_addr - convert the base address
+ * @addr_base:  base address of the memory bank
+ *
+ * This function converts a base address of lbc into the right format for the
+ * BR register. If the SOC has eLBC then it returns 32bit physical address
+ * else it convers a 34bit local bus physical address to correct format of
+ * 32bit address for BR register (Example: MPC8641).
+ */
+u32 fsl_lbc_addr(phys_addr_t addr_base)
 {
-        struct device_node *lbus;
-        int i;
+        struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
+        u32 addr = addr_base & 0xffff8000;
 
-        for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
-                lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
-                if (lbus)
-                        goto found;
-        }
-        return -ENODEV;
+        if (of_device_is_compatible(np, "fsl,elbc"))
+                return addr;
 
-found:
-        fsl_lbc_regs = of_iomap(lbus, 0);
-        of_node_put(lbus);
-        if (!fsl_lbc_regs)
-                return -ENOMEM;
-        return 0;
+        return addr | ((addr_base & 0x300000000ull) >> 19);
 }
-arch_initcall(fsl_lbc_init);
+EXPORT_SYMBOL(fsl_lbc_addr);
 
 /**
  * fsl_lbc_find - find Localbus bank
@@ -65,15 +66,17 @@ arch_initcall(fsl_lbc_init);
 int fsl_lbc_find(phys_addr_t addr_base)
 {
         int i;
+        struct fsl_lbc_regs __iomem *lbc;
 
-        if (!fsl_lbc_regs)
+        if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
                 return -ENODEV;
 
-        for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
-                __be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
-                __be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
+        lbc = fsl_lbc_ctrl_dev->regs;
+        for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
+                __be32 br = in_be32(&lbc->bank[i].br);
+                __be32 or = in_be32(&lbc->bank[i].or);
 
-                if (br & BR_V && (br & or & BR_BA) == addr_base)
+                if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
                         return i;
         }
 
@@ -94,22 +97,27 @@ int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
 {
         int bank;
         __be32 br;
+        struct fsl_lbc_regs __iomem *lbc;
 
         bank = fsl_lbc_find(addr_base);
         if (bank < 0)
                 return bank;
 
-        br = in_be32(&fsl_lbc_regs->bank[bank].br);
+        if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
+                return -ENODEV;
+
+        lbc = fsl_lbc_ctrl_dev->regs;
+        br = in_be32(&lbc->bank[bank].br);
 
         switch (br & BR_MSEL) {
         case BR_MS_UPMA:
-                upm->mxmr = &fsl_lbc_regs->mamr;
+                upm->mxmr = &lbc->mamr;
                 break;
         case BR_MS_UPMB:
-                upm->mxmr = &fsl_lbc_regs->mbmr;
+                upm->mxmr = &lbc->mbmr;
                 break;
         case BR_MS_UPMC:
-                upm->mxmr = &fsl_lbc_regs->mcmr;
+                upm->mxmr = &lbc->mcmr;
                 break;
         default:
                 return -EINVAL;
@@ -148,9 +156,12 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
         int ret = 0;
         unsigned long flags;
 
+        if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
+                return -ENODEV;
+
         spin_lock_irqsave(&fsl_lbc_lock, flags);
 
-        out_be32(&fsl_lbc_regs->mar, mar);
+        out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
 
         switch (upm->width) {
         case 8:
@@ -172,3 +183,166 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
         return ret;
 }
 EXPORT_SYMBOL(fsl_upm_run_pattern);
+
+static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
+{
+        struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+
+        /* clear event registers */
+        setbits32(&lbc->ltesr, LTESR_CLEAR);
+        out_be32(&lbc->lteatr, 0);
+        out_be32(&lbc->ltear, 0);
+        out_be32(&lbc->lteccr, LTECCR_CLEAR);
+        out_be32(&lbc->ltedr, LTEDR_ENABLE);
+
+        /* Enable interrupts for any detected events */
+        out_be32(&lbc->lteir, LTEIR_ENABLE);
+
+        return 0;
+}
+
+/*
+ * NOTE: This interrupt is used to report localbus events of various kinds,
+ * such as transaction errors on the chipselects.
+ */
+
+static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
+{
+        struct fsl_lbc_ctrl *ctrl = data;
+        struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
+        u32 status;
+
+        status = in_be32(&lbc->ltesr);
+        if (!status)
+                return IRQ_NONE;
+
+        out_be32(&lbc->ltesr, LTESR_CLEAR);
+        out_be32(&lbc->lteatr, 0);
+        out_be32(&lbc->ltear, 0);
+        ctrl->irq_status = status;
+
+        if (status & LTESR_BM)
+                dev_err(ctrl->dev, "Local bus monitor time-out: "
+                        "LTESR 0x%08X\n", status);
+        if (status & LTESR_WP)
+                dev_err(ctrl->dev, "Write protect error: "
+                        "LTESR 0x%08X\n", status);
+        if (status & LTESR_ATMW)
+                dev_err(ctrl->dev, "Atomic write error: "
+                        "LTESR 0x%08X\n", status);
+        if (status & LTESR_ATMR)
+                dev_err(ctrl->dev, "Atomic read error: "
+                        "LTESR 0x%08X\n", status);
+        if (status & LTESR_CS)
+                dev_err(ctrl->dev, "Chip select error: "
+                        "LTESR 0x%08X\n", status);
+        if (status & LTESR_UPM)
+                ;
+        if (status & LTESR_FCT) {
+                dev_err(ctrl->dev, "FCM command time-out: "
+                        "LTESR 0x%08X\n", status);
+                smp_wmb();
+                wake_up(&ctrl->irq_wait);
+        }
+        if (status & LTESR_PAR) {
+                dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
+                        "LTESR 0x%08X\n", status);
+                smp_wmb();
+                wake_up(&ctrl->irq_wait);
+        }
+        if (status & LTESR_CC) {
+                smp_wmb();
+                wake_up(&ctrl->irq_wait);
+        }
+        if (status & ~LTESR_MASK)
+                dev_err(ctrl->dev, "Unknown error: "
+                        "LTESR 0x%08X\n", status);
+        return IRQ_HANDLED;
+}
+
+/*
+ * fsl_lbc_ctrl_probe
+ *
+ * called by device layer when it finds a device matching
+ * one our driver can handled. This code allocates all of
+ * the resources needed for the controller only.  The
+ * resources for the NAND banks themselves are allocated
+ * in the chip probe function.
+*/
+
+static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
+{
+        int ret;
+
+        if (!dev->dev.of_node) {
+                dev_err(&dev->dev, "Device OF-Node is NULL");
+                return -EFAULT;
+        }
+
+        fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
+        if (!fsl_lbc_ctrl_dev)
+                return -ENOMEM;
+
+        dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
+
+        spin_lock_init(&fsl_lbc_ctrl_dev->lock);
+        init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
+
+        fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
+        if (!fsl_lbc_ctrl_dev->regs) {
+                dev_err(&dev->dev, "failed to get memory region\n");
+                ret = -ENODEV;
+                goto err;
+        }
+
+        fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
+        if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
+                dev_err(&dev->dev, "failed to get irq resource\n");
+                ret = -ENODEV;
+                goto err;
+        }
+
+        fsl_lbc_ctrl_dev->dev = &dev->dev;
+
+        ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
+        if (ret < 0)
+                goto err;
+
+        ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
+                                "fsl-lbc", fsl_lbc_ctrl_dev);
+        if (ret != 0) {
+                dev_err(&dev->dev, "failed to install irq (%d)\n",
+                        fsl_lbc_ctrl_dev->irq);
+                ret = fsl_lbc_ctrl_dev->irq;
+                goto err;
+        }
+
+        return 0;
+
+err:
+        iounmap(fsl_lbc_ctrl_dev->regs);
+        kfree(fsl_lbc_ctrl_dev);
+        return ret;
+}
+
+static const struct of_device_id fsl_lbc_match[] = {
+        { .compatible = "fsl,elbc", },
+        { .compatible = "fsl,pq3-localbus", },
+        { .compatible = "fsl,pq2-localbus", },
+        { .compatible = "fsl,pq2pro-localbus", },
+        {},
+};
+
+static struct platform_driver fsl_lbc_ctrl_driver = {
+        .driver = {
+                .name = "fsl-lbc",
+                .of_match_table = fsl_lbc_match,
+        },
+        .probe = fsl_lbc_ctrl_probe,
+};
+
+static int __init fsl_lbc_init(void)
+{
+        return platform_driver_register(&fsl_lbc_ctrl_driver);
+}
+module_init(fsl_lbc_init);
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 068e55d1bba8..e0b98e71ff47 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -1,8 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
 config SCHED_MC
         def_bool y
         depends on SMP
@@ -78,8 +73,6 @@ config VIRT_CPU_ACCOUNTING
 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
         def_bool y
 
-mainmenu "Linux Kernel Configuration"
-
 config S390
         def_bool y
         select USE_GENERIC_SMP_HELPERS if SMP
@@ -87,6 +80,7 @@ config S390
         select HAVE_FUNCTION_TRACER
         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
         select HAVE_FTRACE_MCOUNT_RECORD
+        select HAVE_C_RECORDMCOUNT
         select HAVE_SYSCALL_TRACEPOINTS
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FUNCTION_GRAPH_TRACER
@@ -151,7 +145,7 @@ source "kernel/time/Kconfig"
 config 64BIT
         bool "64 bit kernel"
         help
-          Select this option if you have a 64 bit IBM zSeries machine
+          Select this option if you have an IBM z/Architecture machine
           and want to use the 64 bit addressing mode.
 
 config 32BIT
@@ -203,9 +197,18 @@ config HOTPLUG_CPU
           can be controlled through /sys/devices/system/cpu/cpu#.
           Say N if you want to disable CPU hotplug.
 
+config SCHED_MC
+        def_bool y
+        prompt "Multi-core scheduler support"
+        depends on SMP
+        help
+          Multi-core scheduler support improves the CPU scheduler's decision
+          making when dealing with multi-core CPU chips at a cost of slightly
+          increased overhead in some places.
+
 config SCHED_BOOK
         bool "Book scheduler support"
-        depends on SMP
+        depends on SMP && SCHED_MC
         help
           Book scheduler support improves the CPU scheduler's decision making
           when dealing with machines that have several books.
@@ -215,7 +218,7 @@ config MATHEMU
         depends on MARCH_G5
         help
           This option is required for IEEE compliant floating point arithmetic
-          on older S/390 machines. Say Y unless you know your machine doesn't
+          on older ESA/390 machines. Say Y unless you know your machine doesn't
           need this.
 
 config COMPAT
@@ -244,8 +247,8 @@ config S390_EXEC_PROTECT
           space programs and it also selects the addressing mode option above.
           The kernel parameter noexec=on will enable this feature and also
           switch the addressing modes, default is disabled. Enabling this (via
-          kernel parameter) on machines earlier than IBM System z9-109 EC/BC
-          will reduce system performance.
+          kernel parameter) on machines earlier than IBM System z9 this will
+          reduce system performance.
 
 comment "Code generation options"
 
@@ -254,49 +257,46 @@ choice
         default MARCH_G5
 
 config MARCH_G5
-        bool "S/390 model G5 and G6"
+        bool "System/390 model G5 and G6"
         depends on !64BIT
         help
           Select this to build a 31 bit kernel that works
-          on all S/390 and zSeries machines.
+          on all ESA/390 and z/Architecture machines.
 
 config MARCH_Z900
-        bool "IBM eServer zSeries model z800 and z900"
+        bool "IBM zSeries model z800 and z900"
         help
-          Select this to optimize for zSeries machines. This
-          will enable some optimizations that are not available
-          on older 31 bit only CPUs.
+          Select this to enable optimizations for model z800/z900 (2064 and
+          2066 series). This will enable some optimizations that are not
+          available on older ESA/390 (31 Bit) only CPUs.
 
 config MARCH_Z990
-        bool "IBM eServer zSeries model z890 and z990"
+        bool "IBM zSeries model z890 and z990"
         help
-          Select this enable optimizations for model z890/z990.
-          This will be slightly faster but does not work on
-          older machines such as the z900.
+          Select this to enable optimizations for model z890/z990 (2084 and
+          2086 series). The kernel will be slightly faster but will not work
+          on older machines.
 
 config MARCH_Z9_109
         bool "IBM System z9"
         help
-          Select this to enable optimizations for IBM System z9-109, IBM
-          System z9 Enterprise Class (z9 EC), and IBM System z9 Business
-          Class (z9 BC). The kernel will be slightly faster but will not
-          work on older machines such as the z990, z890, z900, and z800.
+          Select this to enable optimizations for IBM System z9 (2094 and
+          2096 series). The kernel will be slightly faster but will not work
+          on older machines.
 
 config MARCH_Z10
         bool "IBM System z10"
         help
-          Select this to enable optimizations for IBM System z10. The
-          kernel will be slightly faster but will not work on older
-          machines such as the z990, z890, z900, z800, z9-109, z9-ec
-          and z9-bc.
+          Select this to enable optimizations for IBM System z10 (2097 and
+          2098 series). The kernel will be slightly faster but will not work
+          on older machines.
 
 config MARCH_Z196
         bool "IBM zEnterprise 196"
         help
-          Select this to enable optimizations for IBM zEnterprise 196.
-          The kernel will be slightly faster but will not work on older
-          machines such as the z990, z890, z900, z800, z9-109, z9-ec,
-          z9-bc, z10-ec and z10-bc.
+          Select this to enable optimizations for IBM zEnterprise 196
+          (2817 series). The kernel will be slightly faster but will not work
+          on older machines.
 
 endchoice
 
diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c
index 020e51c063d2..cd4a81be9cf8 100644
--- a/arch/s390/hypfs/hypfs_diag.c
+++ b/arch/s390/hypfs/hypfs_diag.c
@@ -638,18 +638,21 @@ __init int hypfs_diag_init(void)
                 pr_err("The hardware system does not support hypfs\n");
                 return -ENODATA;
         }
-        rc = diag224_get_name_table();
-        if (rc) {
-                diag204_free_buffer();
-                pr_err("The hardware system does not provide all "
-                       "functions required by hypfs\n");
-        }
         if (diag204_info_type == INFO_EXT) {
                 rc = hypfs_dbfs_init();
                 if (rc)
-                        diag204_free_buffer();
+                        return rc;
         }
-        return rc;
+        if (MACHINE_IS_LPAR) {
+                rc = diag224_get_name_table();
+                if (rc) {
+                        pr_err("The hardware system does not provide all "
+                               "functions required by hypfs\n");
+                        debugfs_remove(dbfs_d204_file);
+                        return rc;
+                }
+        }
+        return 0;
 }
 
 void hypfs_diag_exit(void)
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index 74d98670be27..47cc446dab8f 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -316,10 +316,10 @@ static int hypfs_fill_super(struct super_block *sb, void *data, int silent)
         return 0;
 }
 
-static int hypfs_get_super(struct file_system_type *fst, int flags,
-                        const char *devname, void *data, struct vfsmount *mnt)
+static struct dentry *hypfs_mount(struct file_system_type *fst, int flags,
+                        const char *devname, void *data)
 {
-        return get_sb_single(fst, flags, data, hypfs_fill_super, mnt);
+        return mount_single(fst, flags, data, hypfs_fill_super);
 }
 
 static void hypfs_kill_super(struct super_block *sb)
@@ -455,7 +455,7 @@ static const struct file_operations hypfs_file_ops = {
 static struct file_system_type hypfs_type = {
         .owner          = THIS_MODULE,
         .name           = "s390_hypfs",
-        .get_sb         = hypfs_get_super,
+        .mount          = hypfs_mount,
         .kill_sb        = hypfs_kill_super
 };
 
diff --git a/arch/s390/include/asm/dasd.h b/arch/s390/include/asm/dasd.h
index 218bce81ec70..b604a9186f8e 100644
--- a/arch/s390/include/asm/dasd.h
+++ b/arch/s390/include/asm/dasd.h
@@ -217,6 +217,25 @@ typedef struct dasd_symmio_parms {
         int rssd_result_len;
 } __attribute__ ((packed)) dasd_symmio_parms_t;
 
+/*
+ * Data returned by Sense Path Group ID (SNID)
+ */
+struct dasd_snid_data {
+        struct {
+                __u8 group:2;
+                __u8 reserve:2;
+                __u8 mode:1;
+                __u8 res:3;
+        } __attribute__ ((packed)) path_state;
+        __u8 pgid[11];
+} __attribute__ ((packed));
+
+struct dasd_snid_ioctl_data {
+        struct dasd_snid_data data;
+        __u8 path_mask;
+} __attribute__ ((packed));
+
+
 /********************************************************************************
  * SECTION: Definition of IOCTLs
  *
@@ -261,25 +280,10 @@ typedef struct dasd_symmio_parms {
 /* Set Attributes (cache operations) */
 #define BIODASDSATTR   _IOW(DASD_IOCTL_LETTER,2,attrib_data_t) 
 
+/* Get Sense Path Group ID (SNID) data */
+#define BIODASDSNID    _IOWR(DASD_IOCTL_LETTER, 1, struct dasd_snid_ioctl_data)
+
 #define BIODASDSYMMIO  _IOWR(DASD_IOCTL_LETTER, 240, dasd_symmio_parms_t)
 
 #endif                          /* DASD_H */
 
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-indent-level: 4 
- * c-brace-imaginary-offset: 0
- * c-brace-offset: -4
- * c-argdecl-indent: 4
- * c-label-offset: -4
- * c-continued-statement-offset: 4
- * c-continued-brace-offset: 0
- * indent-tabs-mode: nil
- * tab-width: 8
- * End:
- */
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index f3c1b823c9a8..33982e7ce04d 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -66,9 +66,9 @@ int main(void)
         DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base));
         DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time));
         /* constants used by the vdso */
-        DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
-        DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
-        DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
+        DEFINE(__CLOCK_REALTIME, CLOCK_REALTIME);
+        DEFINE(__CLOCK_MONOTONIC, CLOCK_MONOTONIC);
+        DEFINE(__CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
         BLANK();
         /* constants for SIGP */
         DEFINE(__SIGP_STOP, sigp_stop);
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index d149609e46e6..3b7e7dddc324 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -282,8 +282,6 @@ static noinline __init void setup_facility_list(void)
 static noinline __init void setup_hpage(void)
 {
 #ifndef CONFIG_DEBUG_PAGEALLOC
-        unsigned int facilities;
-
         if (!test_facility(2) || !test_facility(8))
                 return;
         S390_lowcore.machine_flags |= MACHINE_FLAG_HPAGE;
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 5efce7202984..1ecc337fb679 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -557,6 +557,7 @@ pgm_svcper:
 # per was called from kernel, must be kprobes
 #
 kernel_per:
+        REENABLE_IRQS
         mvi     SP_SVCNR(%r15),0xff     # set trap indication to pgm check
         mvi     SP_SVCNR+1(%r15),0xff
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index a2be23922f43..8f3e802174db 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -568,6 +568,7 @@ pgm_svcper:
 # per was called from kernel, must be kprobes
 #
 kernel_per:
+        REENABLE_IRQS
         xc      SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
         brasl   %r14,do_single_step
diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c
index 2a3d2bf6f083..d60fc4398516 100644
--- a/arch/s390/kernel/kprobes.c
+++ b/arch/s390/kernel/kprobes.c
@@ -316,6 +316,8 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
                 return 1;
 
 ss_probe:
+        if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+                local_irq_disable();
         prepare_singlestep(p, regs);
         kcb->kprobe_status = KPROBE_HIT_SS;
         return 1;
@@ -463,6 +465,8 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs)
                 goto out;
         }
         reset_current_kprobe();
+        if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+                local_irq_enable();
 out:
         preempt_enable_no_resched();
 
@@ -502,8 +506,11 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
                 regs->psw.mask |= kcb->kprobe_saved_imask;
                 if (kcb->kprobe_status == KPROBE_REENTER)
                         restore_previous_kprobe(kcb);
-                else
+                else {
                         reset_current_kprobe();
+                        if (regs->psw.mask & (PSW_MASK_PER | PSW_MASK_IO))
+                                local_irq_enable();
+                }
                 preempt_enable_no_resched();
                 break;
         case KPROBE_HIT_ACTIVE:
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index e3ceb911dc75..6f6350826c81 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -761,6 +761,9 @@ static void __init setup_hwcaps(void)
         case 0x2098:
                 strcpy(elf_platform, "z10");
                 break;
+        case 0x2817:
+                strcpy(elf_platform, "z196");
+                break;
         }
 }
 
diff --git a/arch/s390/kernel/sysinfo.c b/arch/s390/kernel/sysinfo.c
index f04d93aa48ec..5c9e439bf3f6 100644
--- a/arch/s390/kernel/sysinfo.c
+++ b/arch/s390/kernel/sysinfo.c
@@ -106,11 +106,13 @@ static int stsi_15_1_x(struct sysinfo_15_1_x *info, char *page, int len)
         for (i = 0; i < TOPOLOGY_NR_MAG; i++)
                 len += sprintf(page + len, " %d", info->mag[i]);
         len += sprintf(page + len, "\n");
+#ifdef CONFIG_SCHED_MC
         store_topology(info);
         len += sprintf(page + len, "CPU Topology SW:     ");
         for (i = 0; i < TOPOLOGY_NR_MAG; i++)
                 len += sprintf(page + len, " %d", info->mag[i]);
         len += sprintf(page + len, "\n");
+#endif
         return len;
 }
 
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index a9dee9048ee5..94b06c31fc8a 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -53,8 +53,10 @@ static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu)
         cpumask_t mask;
 
         cpus_clear(mask);
-        if (!topology_enabled || !MACHINE_HAS_TOPOLOGY)
-                return cpu_possible_map;
+        if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) {
+                cpumask_copy(&mask, cpumask_of(cpu));
+                return mask;
+        }
         while (info) {
                 if (cpu_isset(cpu, info->mask)) {
                         mask = info->mask;
diff --git a/arch/s390/kernel/vdso32/clock_getres.S b/arch/s390/kernel/vdso32/clock_getres.S
index 9532c4e6a9d2..36aaa25d05da 100644
--- a/arch/s390/kernel/vdso32/clock_getres.S
+++ b/arch/s390/kernel/vdso32/clock_getres.S
@@ -19,9 +19,9 @@
         .type  __kernel_clock_getres,@function
 __kernel_clock_getres:
         .cfi_startproc
-        chi     %r2,CLOCK_REALTIME
+        chi     %r2,__CLOCK_REALTIME
         je      0f
-        chi     %r2,CLOCK_MONOTONIC
+        chi     %r2,__CLOCK_MONOTONIC
         jne     3f
 0:      ltr     %r3,%r3
         jz      2f                              /* res == NULL */
@@ -34,6 +34,6 @@ __kernel_clock_getres:
 3:      lhi     %r1,__NR_clock_getres           /* fallback to svc */
         svc     0
         br      %r14
-4:      .long   CLOCK_REALTIME_RES
+4:      .long   __CLOCK_REALTIME_RES
         .cfi_endproc
         .size   __kernel_clock_getres,.-__kernel_clock_getres
diff --git a/arch/s390/kernel/vdso32/clock_gettime.S b/arch/s390/kernel/vdso32/clock_gettime.S
index 969643954273..b2224e0b974c 100644
--- a/arch/s390/kernel/vdso32/clock_gettime.S
+++ b/arch/s390/kernel/vdso32/clock_gettime.S
@@ -21,9 +21,9 @@ __kernel_clock_gettime:
         .cfi_startproc
         basr    %r5,0
 0:      al      %r5,21f-0b(%r5)                 /* get &_vdso_data */
-        chi     %r2,CLOCK_REALTIME
+        chi     %r2,__CLOCK_REALTIME
         je      10f
-        chi     %r2,CLOCK_MONOTONIC
+        chi     %r2,__CLOCK_MONOTONIC
         jne     19f
 
         /* CLOCK_MONOTONIC */
diff --git a/arch/s390/kernel/vdso64/clock_getres.S b/arch/s390/kernel/vdso64/clock_getres.S
index 9ce8caafdb4e..176e1f75f9aa 100644
--- a/arch/s390/kernel/vdso64/clock_getres.S
+++ b/arch/s390/kernel/vdso64/clock_getres.S
@@ -19,9 +19,9 @@
         .type  __kernel_clock_getres,@function
 __kernel_clock_getres:
         .cfi_startproc
-        cghi    %r2,CLOCK_REALTIME
+        cghi    %r2,__CLOCK_REALTIME
         je      0f
-        cghi    %r2,CLOCK_MONOTONIC
+        cghi    %r2,__CLOCK_MONOTONIC
         je      0f
         cghi    %r2,-2          /* CLOCK_THREAD_CPUTIME_ID for this thread */
         jne     2f
@@ -39,6 +39,6 @@ __kernel_clock_getres:
 2:      lghi    %r1,__NR_clock_getres           /* fallback to svc */
         svc     0
         br      %r14
-3:      .quad   CLOCK_REALTIME_RES
+3:      .quad   __CLOCK_REALTIME_RES
         .cfi_endproc
         .size   __kernel_clock_getres,.-__kernel_clock_getres
diff --git a/arch/s390/kernel/vdso64/clock_gettime.S b/arch/s390/kernel/vdso64/clock_gettime.S
index f40467884a03..d46c95ed5f19 100644
--- a/arch/s390/kernel/vdso64/clock_gettime.S
+++ b/arch/s390/kernel/vdso64/clock_gettime.S
@@ -20,11 +20,11 @@
 __kernel_clock_gettime:
         .cfi_startproc
         larl    %r5,_vdso_data
-        cghi    %r2,CLOCK_REALTIME
+        cghi    %r2,__CLOCK_REALTIME
         je      4f
         cghi    %r2,-2          /* CLOCK_THREAD_CPUTIME_ID for this thread */
         je      9f
-        cghi    %r2,CLOCK_MONOTONIC
+        cghi    %r2,__CLOCK_MONOTONIC
         jne     12f
 
         /* CLOCK_MONOTONIC */
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index be4a15584751..4293fdcb5398 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -1,8 +1,3 @@
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-
-mainmenu "Linux/SCORE Kernel Configuration"
-
 menu "Machine selection"
 
 choice
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 0f40fc35d0a2..7f217b3a50a8 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -1,10 +1,3 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux/SuperH Kernel Configuration"
-
 config SUPERH
         def_bool y
         select EMBEDDED
@@ -25,8 +18,11 @@ config SUPERH
         select HAVE_KERNEL_LZO
         select HAVE_SYSCALL_TRACEPOINTS
         select HAVE_REGS_AND_STACK_ACCESS_API
+        select HAVE_GENERIC_HARDIRQS
+        select HAVE_SPARSE_IRQ
         select RTC_LIB
         select GENERIC_ATOMIC64
+        select GENERIC_HARDIRQS_NO_DEPRECATED
         help
           The SuperH is a RISC processor targeted for use in embedded systems
           and consumer electronics; it was also used in the Sega Dreamcast
@@ -49,6 +45,7 @@ config SUPERH32
         select HAVE_MIXED_BREAKPOINTS_REGS
         select PERF_EVENTS
         select ARCH_HIBERNATION_POSSIBLE if MMU
+        select SPARSE_IRQ
 
 config SUPERH64
         def_bool ARCH = "sh64"
@@ -78,19 +75,9 @@ config GENERIC_FIND_NEXT_BIT
 config GENERIC_HWEIGHT
         def_bool y
 
-config GENERIC_HARDIRQS
-        def_bool y
-
-config GENERIC_HARDIRQS_NO__DO_IRQ
-        def_bool y
-
 config IRQ_PER_CPU
         def_bool y
 
-config SPARSE_IRQ
-        def_bool y
-        depends on SUPERH32
-
 config GENERIC_GPIO
         def_bool n
 
@@ -206,6 +193,7 @@ config CPU_SH2
 config CPU_SH2A
         bool
         select CPU_SH2
+        select UNCACHED_MAPPING
 
 config CPU_SH3
         bool
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 307b3a4a790b..9c8c6e1a2a15 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -133,10 +133,7 @@ machdir-$(CONFIG_SOLUTION_ENGINE)		+= mach-se
 machdir-$(CONFIG_SH_HP6XX)                      += mach-hp6xx
 machdir-$(CONFIG_SH_DREAMCAST)                  += mach-dreamcast
 machdir-$(CONFIG_SH_SH03)                       += mach-sh03
-machdir-$(CONFIG_SH_SECUREEDGE5410)             += mach-snapgear
 machdir-$(CONFIG_SH_RTS7751R2D)                 += mach-r2d
-machdir-$(CONFIG_SH_7751_SYSTEMH)               += mach-systemh
-machdir-$(CONFIG_SH_EDOSK7705)                  += mach-edosk7705
 machdir-$(CONFIG_SH_HIGHLANDER)                 += mach-highlander
 machdir-$(CONFIG_SH_MIGOR)                      += mach-migor
 machdir-$(CONFIG_SH_AP325RXA)                   += mach-ap325rxa
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 9c94711aa6ca..2018c7ea4c93 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -81,13 +81,6 @@ config SH_7343_SOLUTION_ENGINE
           Select 7343 SolutionEngine if configuring for a Hitachi
           SH7343 (SH-Mobile 3AS) evaluation board.
 
-config SH_7751_SYSTEMH
-        bool "SystemH7751R"
-        depends on CPU_SUBTYPE_SH7751R
-        help
-          Select SystemH if you are configuring for a Renesas SystemH
-          7751R evaluation board.
-
 config SH_HP6XX
         bool "HP6XX"
         select SYS_SUPPORTS_APM_EMULATION
diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile
index 38ef655cc0f0..be7d11d04b26 100644
--- a/arch/sh/boards/Makefile
+++ b/arch/sh/boards/Makefile
@@ -2,10 +2,12 @@
 # Specific board support, not covered by a mach group.
 #
 obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
+obj-$(CONFIG_SH_SECUREEDGE5410) += board-secureedge5410.o
 obj-$(CONFIG_SH_SH2007)         += board-sh2007.o
 obj-$(CONFIG_SH_SH7785LCR)      += board-sh7785lcr.o
 obj-$(CONFIG_SH_URQUELL)        += board-urquell.o
 obj-$(CONFIG_SH_SHMIN)          += board-shmin.o
+obj-$(CONFIG_SH_EDOSK7705)      += board-edosk7705.o
 obj-$(CONFIG_SH_EDOSK7760)      += board-edosk7760.o
 obj-$(CONFIG_SH_ESPT)           += board-espt.o
 obj-$(CONFIG_SH_POLARIS)        += board-polaris.o
diff --git a/arch/sh/boards/board-edosk7705.c b/arch/sh/boards/board-edosk7705.c
new file mode 100644
index 000000000000..4cb3bb74c36f
--- /dev/null
+++ b/arch/sh/boards/board-edosk7705.c
@@ -0,0 +1,78 @@
+/*
+ * arch/sh/boards/renesas/edosk7705/setup.c
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine Support.
+ *
+ * Modified for edosk7705 development
+ * board by S. Dunn, 2003.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/smc91x.h>
+#include <asm/machvec.h>
+#include <asm/sizes.h>
+
+#define SMC_IOBASE      0xA2000000
+#define SMC_IO_OFFSET   0x300
+#define SMC_IOADDR      (SMC_IOBASE + SMC_IO_OFFSET)
+
+#define ETHERNET_IRQ    0x09
+
+static void __init sh_edosk7705_init_irq(void)
+{
+        make_imask_irq(ETHERNET_IRQ);
+}
+
+/* eth initialization functions */
+static struct smc91x_platdata smc91x_info = {
+        .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL,
+};
+
+static struct resource smc91x_res[] = {
+        [0] = {
+                .start  = SMC_IOADDR,
+                .end    = SMC_IOADDR + SZ_32 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ETHERNET_IRQ,
+                .end    = ETHERNET_IRQ,
+                .flags  = IORESOURCE_IRQ ,
+        }
+};
+
+static struct platform_device smc91x_dev = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc91x_res),
+        .resource       = smc91x_res,
+
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
+};
+
+/* platform init code */
+static struct platform_device *edosk7705_devices[] __initdata = {
+        &smc91x_dev,
+};
+
+static int __init init_edosk7705_devices(void)
+{
+        return platform_add_devices(edosk7705_devices,
+                                    ARRAY_SIZE(edosk7705_devices));
+}
+__initcall(init_edosk7705_devices);
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_edosk7705 __initmv = {
+        .mv_name                = "EDOSK7705",
+        .mv_nr_irqs             = 80,
+        .mv_init_irq            = sh_edosk7705_init_irq,
+};
diff --git a/arch/sh/boards/mach-snapgear/setup.c b/arch/sh/boards/board-secureedge5410.c
index 331745dee379..32f875e8493d 100644
--- a/arch/sh/boards/mach-snapgear/setup.c
+++ b/arch/sh/boards/board-secureedge5410.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/sh/boards/snapgear/setup.c
- *
  * Copyright (C) 2002  David McCullough <davidm@snapgear.com>
  * Copyright (C) 2003  Paul Mundt <lethal@linux-sh.org>
  *
@@ -19,18 +17,19 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <asm/machvec.h>
-#include <mach/snapgear.h>
+#include <mach/secureedge5410.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <cpu/timer.h>
 
+unsigned short secureedge5410_ioport;
+
 /*
  * EraseConfig handling functions
  */
-
 static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
 {
-        (void)__raw_readb(0xb8000000);  /* dummy read */
+        ctrl_delay();   /* dummy read */
 
         printk("SnapGear: erase switch interrupt!\n");
 
@@ -39,21 +38,22 @@ static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
 
 static int __init eraseconfig_init(void)
 {
+        unsigned int irq = evt2irq(0x240);
+
         printk("SnapGear: EraseConfig init\n");
+
         /* Setup "EraseConfig" switch on external IRQ 0 */
-        if (request_irq(IRL0_IRQ, eraseconfig_interrupt, IRQF_DISABLED,
+        if (request_irq(irq, eraseconfig_interrupt, IRQF_DISABLED,
                                 "Erase Config", NULL))
                 printk("SnapGear: failed to register IRQ%d for Reset witch\n",
-                                IRL0_IRQ);
+                                irq);
         else
                 printk("SnapGear: registered EraseConfig switch on IRQ%d\n",
-                                IRL0_IRQ);
-        return(0);
+                                irq);
+        return 0;
 }
-
 module_init(eraseconfig_init);
 
-/****************************************************************************/
 /*
  * Initialize IRQ setting
  *
@@ -62,7 +62,6 @@ module_init(eraseconfig_init);
  * IRL2 = eth1
  * IRL3 = crypto
  */
-
 static void __init init_snapgear_IRQ(void)
 {
         printk("Setup SnapGear IRQ/IPR ...\n");
@@ -76,20 +75,5 @@ static void __init init_snapgear_IRQ(void)
 static struct sh_machine_vector mv_snapgear __initmv = {
         .mv_name                = "SnapGear SecureEdge5410",
         .mv_nr_irqs             = 72,
-
-        .mv_inb                 = snapgear_inb,
-        .mv_inw                 = snapgear_inw,
-        .mv_inl                 = snapgear_inl,
-        .mv_outb                = snapgear_outb,
-        .mv_outw                = snapgear_outw,
-        .mv_outl                = snapgear_outl,
-
-        .mv_inb_p               = snapgear_inb_p,
-        .mv_inw_p               = snapgear_inw,
-        .mv_inl_p               = snapgear_inl,
-        .mv_outb_p              = snapgear_outb_p,
-        .mv_outw_p              = snapgear_outw,
-        .mv_outl_p              = snapgear_outl,
-
         .mv_init_irq            = init_snapgear_IRQ,
 };
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 3da116f47f01..07ea908c510d 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -176,6 +176,21 @@ static void ap320_wvga_power_off(void *board_data)
         __raw_writew(0, FPGA_LCDREG);
 }
 
+const static struct fb_videomode ap325rxa_lcdc_modes[] = {
+        {
+                .name = "LB070WV1",
+                .xres = 800,
+                .yres = 480,
+                .left_margin = 32,
+                .right_margin = 160,
+                .hsync_len = 8,
+                .upper_margin = 63,
+                .lower_margin = 80,
+                .vsync_len = 1,
+                .sync = 0, /* hsync and vsync are active low */
+        },
+};
+
 static struct sh_mobile_lcdc_info lcdc_info = {
         .clock_source = LCDC_CLK_EXTERNAL,
         .ch[0] = {
@@ -183,18 +198,8 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                 .bpp = 16,
                 .interface_type = RGB18,
                 .clock_divider = 1,
-                .lcd_cfg = {
-                        .name = "LB070WV1",
-                        .xres = 800,
-                        .yres = 480,
-                        .left_margin = 32,
-                        .right_margin = 160,
-                        .hsync_len = 8,
-                        .upper_margin = 63,
-                        .lower_margin = 80,
-                        .vsync_len = 1,
-                        .sync = 0, /* hsync and vsync are active low */
-                },
+                .lcd_cfg = ap325rxa_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
@@ -481,7 +486,6 @@ static struct soc_camera_link ov7725_link = {
         .power          = ov7725_power,
         .board_info     = &ap325rxa_i2c_camera[0],
         .i2c_adapter_id = 0,
-        .module_name    = "ov772x",
         .priv           = &ov7725_info,
 };
 
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index 1394b078db36..d7ac5af9d102 100644
--- a/arch/sh/boards/mach-cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -55,8 +55,9 @@ static struct irqaction cayman_action_pci2 = {
         .flags          = IRQF_DISABLED,
 };
 
-static void enable_cayman_irq(unsigned int irq)
+static void enable_cayman_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long flags;
         unsigned long mask;
         unsigned int reg;
@@ -72,8 +73,9 @@ static void enable_cayman_irq(unsigned int irq)
         local_irq_restore(flags);
 }
 
-void disable_cayman_irq(unsigned int irq)
+static void disable_cayman_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long flags;
         unsigned long mask;
         unsigned int reg;
@@ -89,16 +91,10 @@ void disable_cayman_irq(unsigned int irq)
         local_irq_restore(flags);
 }
 
-static void ack_cayman_irq(unsigned int irq)
-{
-        disable_cayman_irq(irq);
-}
-
 struct irq_chip cayman_irq_type = {
         .name           = "Cayman-IRQ",
-        .unmask         = enable_cayman_irq,
-        .mask           = disable_cayman_irq,
-        .mask_ack       = ack_cayman_irq,
+        .irq_unmask     = enable_cayman_irq,
+        .irq_mask       = disable_cayman_irq,
 };
 
 int cayman_irq_demux(int evt)
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index d932667410ab..72e7ac9549da 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -60,8 +60,9 @@
  */
 
 /* Disable the hardware event by masking its bit in its EMR */
-static inline void disable_systemasic_irq(unsigned int irq)
+static inline void disable_systemasic_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
         __u32 mask;
 
@@ -71,8 +72,9 @@ static inline void disable_systemasic_irq(unsigned int irq)
 }
 
 /* Enable the hardware event by setting its bit in its EMR */
-static inline void enable_systemasic_irq(unsigned int irq)
+static inline void enable_systemasic_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
         __u32 mask;
 
@@ -82,18 +84,19 @@ static inline void enable_systemasic_irq(unsigned int irq)
 }
 
 /* Acknowledge a hardware event by writing its bit back to its ESR */
-static void mask_ack_systemasic_irq(unsigned int irq)
+static void mask_ack_systemasic_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
-        disable_systemasic_irq(irq);
+        disable_systemasic_irq(data);
         outl((1 << EVENT_BIT(irq)), esr);
 }
 
 struct irq_chip systemasic_int = {
         .name           = "System ASIC",
-        .mask           = disable_systemasic_irq,
-        .mask_ack       = mask_ack_systemasic_irq,
-        .unmask         = enable_systemasic_irq,
+        .irq_mask       = disable_systemasic_irq,
+        .irq_mask_ack   = mask_ack_systemasic_irq,
+        .irq_unmask     = enable_systemasic_irq,
 };
 
 /*
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 71a3368ab1fc..2eaeb9e59585 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -231,14 +231,41 @@ static struct platform_device usb1_common_device = {
 };
 
 /* LCDC */
+const static struct fb_videomode ecovec_lcd_modes[] = {
+        {
+                .name           = "Panel",
+                .xres           = 800,
+                .yres           = 480,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 70,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync           = 0, /* hsync and vsync are active low */
+        },
+};
+
+const static struct fb_videomode ecovec_dvi_modes[] = {
+        {
+                .name           = "DVI",
+                .xres           = 1280,
+                .yres           = 720,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 40,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync = 0, /* hsync and vsync are active low */
+        },
+};
+
 static struct sh_mobile_lcdc_info lcdc_info = {
         .ch[0] = {
                 .interface_type = RGB18,
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
-                .lcd_cfg = {
-                        .sync = 0, /* hsync and vsync are active low */
-                },
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
@@ -620,7 +647,6 @@ static struct soc_camera_link tw9910_link = {
         .bus_id         = 1,
         .power          = tw9910_power,
         .board_info     = &i2c_camera[0],
-        .module_name    = "tw9910",
         .priv           = &tw9910_info,
 };
 
@@ -644,7 +670,6 @@ static struct soc_camera_link mt9t112_link1 = {
         .power          = mt9t112_power1,
         .bus_id         = 0,
         .board_info     = &i2c_camera[1],
-        .module_name    = "mt9t112",
         .priv           = &mt9t112_info1,
 };
 
@@ -667,7 +692,6 @@ static struct soc_camera_link mt9t112_link2 = {
         .power          = mt9t112_power2,
         .bus_id         = 1,
         .board_info     = &i2c_camera[2],
-        .module_name    = "mt9t112",
         .priv           = &mt9t112_info2,
 };
 
@@ -793,7 +817,6 @@ static struct sh_vou_pdata sh_vou_pdata = {
         .flags          = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
         .board_info     = &ak8813,
         .i2c_adap       = 0,
-        .module_name    = "ak881x",
 };
 
 static struct resource sh_vou_resources[] = {
@@ -1079,33 +1102,18 @@ static int __init arch_setup(void)
         if (gpio_get_value(GPIO_PTE6)) {
                 /* DVI */
                 lcdc_info.clock_source                  = LCDC_CLK_EXTERNAL;
-                lcdc_info.ch[0].clock_divider           = 1,
-                lcdc_info.ch[0].lcd_cfg.name            = "DVI";
-                lcdc_info.ch[0].lcd_cfg.xres            = 1280;
-                lcdc_info.ch[0].lcd_cfg.yres            = 720;
-                lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
-                lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
-                lcdc_info.ch[0].lcd_cfg.hsync_len       = 40;
-                lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
-                lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
-                lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
+                lcdc_info.ch[0].clock_divider           = 1;
+                lcdc_info.ch[0].lcd_cfg                 = ecovec_dvi_modes;
+                lcdc_info.ch[0].num_cfg                 = ARRAY_SIZE(ecovec_dvi_modes);
 
                 gpio_set_value(GPIO_PTA2, 1);
                 gpio_set_value(GPIO_PTU1, 1);
         } else {
                 /* Panel */
-
                 lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
-                lcdc_info.ch[0].clock_divider           = 2,
-                lcdc_info.ch[0].lcd_cfg.name            = "Panel";
-                lcdc_info.ch[0].lcd_cfg.xres            = 800;
-                lcdc_info.ch[0].lcd_cfg.yres            = 480;
-                lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
-                lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
-                lcdc_info.ch[0].lcd_cfg.hsync_len       = 70;
-                lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
-                lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
-                lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
+                lcdc_info.ch[0].clock_divider           = 2;
+                lcdc_info.ch[0].lcd_cfg                 = ecovec_lcd_modes;
+                lcdc_info.ch[0].num_cfg                 = ARRAY_SIZE(ecovec_lcd_modes);
 
                 gpio_set_value(GPIO_PTR1, 1);
 
diff --git a/arch/sh/boards/mach-edosk7705/Makefile b/arch/sh/boards/mach-edosk7705/Makefile
deleted file mode 100644
index cd54acb51499..000000000000
--- a/arch/sh/boards/mach-edosk7705/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the EDOSK7705 specific parts of the kernel
-#
-
-obj-y    := setup.o io.o
diff --git a/arch/sh/boards/mach-edosk7705/io.c b/arch/sh/boards/mach-edosk7705/io.c
deleted file mode 100644
index 5b9c57c43241..000000000000
--- a/arch/sh/boards/mach-edosk7705/io.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * arch/sh/boards/renesas/edosk7705/io.c
- *
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routines for Hitachi EDOSK7705 board.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/edosk7705.h>
-#include <asm/addrspace.h>
-
-#define SMC_IOADDR      0xA2000000
-
-/* Map the Ethernet addresses as if it is at 0x300 - 0x320 */
-static unsigned long sh_edosk7705_isa_port2addr(unsigned long port)
-{
-        /*
-         * SMC91C96 registers are 4 byte aligned rather than the
-         * usual 2 byte!
-         */
-        if (port >= 0x300 && port < 0x320)
-                return SMC_IOADDR + ((port - 0x300) * 2);
-
-        maybebadio(port);
-        return port;
-}
-
-/* Trying to read / write bytes on odd-byte boundaries to the Ethernet
- * registers causes problems. So we bit-shift the value and read / write
- * in 2 byte chunks. Setting the low byte to 0 does not cause problems
- * now as odd byte writes are only made on the bit mask / interrupt
- * register. This may not be the case in future Mar-2003 SJD
- */
-unsigned char sh_edosk7705_inb(unsigned long port)
-{
-        if (port >= 0x300 && port < 0x320 && port & 0x01)
-                return __raw_readw(port - 1) >> 8;
-
-        return __raw_readb(sh_edosk7705_isa_port2addr(port));
-}
-
-void sh_edosk7705_outb(unsigned char value, unsigned long port)
-{
-        if (port >= 0x300 && port < 0x320 && port & 0x01) {
-                __raw_writew(((unsigned short)value << 8), port - 1);
-                return;
-        }
-
-        __raw_writeb(value, sh_edosk7705_isa_port2addr(port));
-}
-
-void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count)
-{
-        unsigned char *p = addr;
-
-        while (count--)
-                *p++ = sh_edosk7705_inb(port);
-}
-
-void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        unsigned char *p = (unsigned char *)addr;
-
-        while (count--)
-                sh_edosk7705_outb(*p++, port);
-}
diff --git a/arch/sh/boards/mach-edosk7705/setup.c b/arch/sh/boards/mach-edosk7705/setup.c
deleted file mode 100644
index d59225e26fb9..000000000000
--- a/arch/sh/boards/mach-edosk7705/setup.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/sh/boards/renesas/edosk7705/setup.c
- *
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * Hitachi SolutionEngine Support.
- *
- * Modified for edosk7705 development
- * board by S. Dunn, 2003.
- */
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <asm/machvec.h>
-#include <mach/edosk7705.h>
-
-static void __init sh_edosk7705_init_irq(void)
-{
-        /* This is the Ethernet interrupt */
-        make_imask_irq(0x09);
-}
-
-/*
- * The Machine Vector
- */
-static struct sh_machine_vector mv_edosk7705 __initmv = {
-        .mv_name                = "EDOSK7705",
-        .mv_nr_irqs             = 80,
-
-        .mv_inb                 = sh_edosk7705_inb,
-        .mv_outb                = sh_edosk7705_outb,
-
-        .mv_insb                = sh_edosk7705_insb,
-        .mv_outsb               = sh_edosk7705_outsb,
-
-        .mv_init_irq            = sh_edosk7705_init_irq,
-};
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 68994a163f6c..9b60eaabf8f3 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -126,6 +126,21 @@ static struct platform_device kfr2r09_sh_keysc_device = {
         },
 };
 
+const static struct fb_videomode kfr2r09_lcdc_modes[] = {
+        {
+                .name = "TX07D34VM0AAA",
+                .xres = 240,
+                .yres = 400,
+                .left_margin = 0,
+                .right_margin = 16,
+                .hsync_len = 8,
+                .upper_margin = 0,
+                .lower_margin = 1,
+                .vsync_len = 1,
+                .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+        },
+};
+
 static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
         .clock_source = LCDC_CLK_BUS,
         .ch[0] = {
@@ -134,18 +149,8 @@ static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
                 .interface_type = SYS18,
                 .clock_divider = 6,
                 .flags = LCDC_FLAGS_DWPOL,
-                .lcd_cfg = {
-                        .name = "TX07D34VM0AAA",
-                        .xres = 240,
-                        .yres = 400,
-                        .left_margin = 0,
-                        .right_margin = 16,
-                        .hsync_len = 8,
-                        .upper_margin = 0,
-                        .lower_margin = 1,
-                        .vsync_len = 1,
-                        .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                },
+                .lcd_cfg = kfr2r09_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
                 .lcd_size_cfg = {
                         .width = 35,
                         .height = 58,
@@ -333,7 +338,6 @@ static struct soc_camera_link rj54n1_link = {
         .power          = camera_power,
         .board_info     = &kfr2r09_i2c_camera,
         .i2c_adapter_id = 1,
-        .module_name    = "rj54n1cb0c",
         .priv           = &rj54n1_priv,
 };
 
diff --git a/arch/sh/boards/mach-landisk/irq.c b/arch/sh/boards/mach-landisk/irq.c
index 96f38a4187d0..e79412a40490 100644
--- a/arch/sh/boards/mach-landisk/irq.c
+++ b/arch/sh/boards/mach-landisk/irq.c
@@ -18,25 +18,24 @@
 #include <linux/io.h>
 #include <mach-landisk/mach/iodata_landisk.h>
 
-static void disable_landisk_irq(unsigned int irq)
+static void disable_landisk_irq(struct irq_data *data)
 {
-        unsigned char mask = 0xff ^ (0x01 << (irq - 5));
+        unsigned char mask = 0xff ^ (0x01 << (data->irq - 5));
 
         __raw_writeb(__raw_readb(PA_IMASK) & mask, PA_IMASK);
 }
 
-static void enable_landisk_irq(unsigned int irq)
+static void enable_landisk_irq(struct irq_data *data)
 {
-        unsigned char value = (0x01 << (irq - 5));
+        unsigned char value = (0x01 << (data->irq - 5));
 
         __raw_writeb(__raw_readb(PA_IMASK) | value, PA_IMASK);
 }
 
 static struct irq_chip landisk_irq_chip __read_mostly = {
         .name           = "LANDISK",
-        .mask           = disable_landisk_irq,
-        .unmask         = enable_landisk_irq,
-        .mask_ack       = disable_landisk_irq,
+        .irq_mask       = disable_landisk_irq,
+        .irq_unmask     = enable_landisk_irq,
 };
 
 /*
@@ -50,7 +49,7 @@ void __init init_landisk_IRQ(void)
                 disable_irq_nosync(i);
                 set_irq_chip_and_handler_name(i, &landisk_irq_chip,
                                               handle_level_irq, "level");
-                enable_landisk_irq(i);
+                enable_landisk_irq(irq_get_irq_data(i));
         }
         __raw_writeb(0x00, PA_PWRINT_CLR);
 }
diff --git a/arch/sh/boards/mach-microdev/io.c b/arch/sh/boards/mach-microdev/io.c
index 2960c659020e..acdafb0c6404 100644
--- a/arch/sh/boards/mach-microdev/io.c
+++ b/arch/sh/boards/mach-microdev/io.c
@@ -54,7 +54,7 @@
 /*
  * map I/O ports to memory-mapped addresses
  */
-static unsigned long microdev_isa_port2addr(unsigned long offset)
+void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len)
 {
         unsigned long result;
 
@@ -72,16 +72,6 @@ static unsigned long microdev_isa_port2addr(unsigned long offset)
                          *      Configuration Registers
                          */
                 result = IO_SUPERIO_PHYS + (offset << 1);
-#if 0
-        } else if (offset == KBD_DATA_REG || offset == KBD_CNTL_REG ||
-                   offset == KBD_STATUS_REG) {
-                        /*
-                         *      SMSC FDC37C93xAPM SuperIO chip
-                         *
-                         *      PS/2 Keyboard + Mouse (ports 0x60 and 0x64).
-                         */
-                result = IO_SUPERIO_PHYS + (offset << 1);
-#endif
         } else if (((offset >= IO_IDE1_BASE) &&
                     (offset <  IO_IDE1_BASE + IO_IDE_EXTENT)) ||
                     (offset == IO_IDE1_MISC)) {
@@ -131,237 +121,5 @@ static unsigned long microdev_isa_port2addr(unsigned long offset)
                 result = PVR;
         }
 
-        return result;
-}
-
-#define PORT2ADDR(x) (microdev_isa_port2addr(x))
-
-static inline void delay(void)
-{
-#if defined(CONFIG_PCI)
-        /* System board present, just make a dummy SRAM access.  (CS0 will be
-           mapped to PCI memory, probably good to avoid it.) */
-        __raw_readw(0xa6800000);
-#else
-        /* CS0 will be mapped to flash, ROM etc so safe to access it. */
-        __raw_readw(0xa0000000);
-#endif
-}
-
-unsigned char microdev_inb(unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO)
-                return microdev_pci_inb(port);
-#endif
-        return *(volatile unsigned char*)PORT2ADDR(port);
-}
-
-unsigned short microdev_inw(unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO)
-                return microdev_pci_inw(port);
-#endif
-        return *(volatile unsigned short*)PORT2ADDR(port);
-}
-
-unsigned int microdev_inl(unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO)
-                return microdev_pci_inl(port);
-#endif
-        return *(volatile unsigned int*)PORT2ADDR(port);
-}
-
-void microdev_outw(unsigned short b, unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO) {
-                microdev_pci_outw(b, port);
-                return;
-        }
-#endif
-        *(volatile unsigned short*)PORT2ADDR(port) = b;
-}
-
-void microdev_outb(unsigned char b, unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO) {
-                microdev_pci_outb(b, port);
-                return;
-        }
-#endif
-
-        /*
-         *      There is a board feature with the current SH4-202 MicroDev in
-         *      that the 2 byte enables (nBE0 and nBE1) are tied together (and
-         *      to the Chip Select Line (Ethernet_CS)). Due to this connectivity,
-         *      it is not possible to safely perform 8-bit writes to the
-         *      Ethernet registers, as 16-bits will be consumed from the Data
-         *      lines (corrupting the other byte).  Hence, this function is
-         *      written to implement 16-bit read/modify/write for all byte-wide
-         *      accesses.
-         *
-         *      Note: there is no problem with byte READS (even or odd).
-         *
-         *                      Sean McGoogan - 16th June 2003.
-         */
-        if ((port >= IO_LAN91C111_BASE) &&
-            (port <  IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
-                        /*
-                         * Then are trying to perform a byte-write to the
-                         * LAN91C111.  This needs special care.
-                         */
-                if (port % 2 == 1) {    /* is the port odd ? */
-                        /* unset bit-0, i.e. make even */
-                        const unsigned long evenPort = port-1;
-                        unsigned short word;
-
-                        /*
-                         * do a 16-bit read/write to write to 'port',
-                         * preserving even byte.
-                         *
-                         *      Even addresses are bits 0-7
-                         *      Odd  addresses are bits 8-15
-                         */
-                        word = microdev_inw(evenPort);
-                        word = (word & 0xffu) | (b << 8);
-                        microdev_outw(word, evenPort);
-                } else {
-                        /* else, we are trying to do an even byte write */
-                        unsigned short word;
-
-                        /*
-                         * do a 16-bit read/write to write to 'port',
-                         * preserving odd byte.
-                         *
-                         *      Even addresses are bits 0-7
-                         *      Odd  addresses are bits 8-15
-                         */
-                        word = microdev_inw(port);
-                        word = (word & 0xff00u) | (b);
-                        microdev_outw(word, port);
-                }
-        } else {
-                *(volatile unsigned char*)PORT2ADDR(port) = b;
-        }
-}
-
-void microdev_outl(unsigned int b, unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO) {
-                microdev_pci_outl(b, port);
-                return;
-        }
-#endif
-        *(volatile unsigned int*)PORT2ADDR(port) = b;
-}
-
-unsigned char microdev_inb_p(unsigned long port)
-{
-        unsigned char v = microdev_inb(port);
-        delay();
-        return v;
-}
-
-unsigned short microdev_inw_p(unsigned long port)
-{
-        unsigned short v = microdev_inw(port);
-        delay();
-        return v;
-}
-
-unsigned int microdev_inl_p(unsigned long port)
-{
-        unsigned int v = microdev_inl(port);
-        delay();
-        return v;
-}
-
-void microdev_outb_p(unsigned char b, unsigned long port)
-{
-        microdev_outb(b, port);
-        delay();
-}
-
-void microdev_outw_p(unsigned short b, unsigned long port)
-{
-        microdev_outw(b, port);
-        delay();
-}
-
-void microdev_outl_p(unsigned int b, unsigned long port)
-{
-        microdev_outl(b, port);
-        delay();
-}
-
-void microdev_insb(unsigned long port, void *buffer, unsigned long count)
-{
-        volatile unsigned char *port_addr;
-        unsigned char *buf = buffer;
-
-        port_addr = (volatile unsigned char *)PORT2ADDR(port);
-
-        while (count--)
-                *buf++ = *port_addr;
-}
-
-void microdev_insw(unsigned long port, void *buffer, unsigned long count)
-{
-        volatile unsigned short *port_addr;
-        unsigned short *buf = buffer;
-
-        port_addr = (volatile unsigned short *)PORT2ADDR(port);
-
-        while (count--)
-                *buf++ = *port_addr;
-}
-
-void microdev_insl(unsigned long port, void *buffer, unsigned long count)
-{
-        volatile unsigned long *port_addr;
-        unsigned int *buf = buffer;
-
-        port_addr = (volatile unsigned long *)PORT2ADDR(port);
-
-        while (count--)
-                *buf++ = *port_addr;
-}
-
-void microdev_outsb(unsigned long port, const void *buffer, unsigned long count)
-{
-        volatile unsigned char *port_addr;
-        const unsigned char *buf = buffer;
-
-        port_addr = (volatile unsigned char *)PORT2ADDR(port);
-
-        while (count--)
-                *port_addr = *buf++;
-}
-
-void microdev_outsw(unsigned long port, const void *buffer, unsigned long count)
-{
-        volatile unsigned short *port_addr;
-        const unsigned short *buf = buffer;
-
-        port_addr = (volatile unsigned short *)PORT2ADDR(port);
-
-        while (count--)
-                *port_addr = *buf++;
-}
-
-void microdev_outsl(unsigned long port, const void *buffer, unsigned long count)
-{
-        volatile unsigned long *port_addr;
-        const unsigned int *buf = buffer;
-
-        port_addr = (volatile unsigned long *)PORT2ADDR(port);
-
-        while (count--)
-                *port_addr = *buf++;
+        return (void __iomem *)result;
 }
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index a26d16669aa2..c35001fd9032 100644
--- a/arch/sh/boards/mach-microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
@@ -65,19 +65,9 @@ static const struct {
 #  error Inconsistancy in defining the IRQ# for primary IDE!
 #endif
 
-static void enable_microdev_irq(unsigned int irq);
-static void disable_microdev_irq(unsigned int irq);
-static void mask_and_ack_microdev(unsigned int);
-
-static struct irq_chip microdev_irq_type = {
-        .name = "MicroDev-IRQ",
-        .unmask = enable_microdev_irq,
-        .mask = disable_microdev_irq,
-        .ack = mask_and_ack_microdev,
-};
-
-static void disable_microdev_irq(unsigned int irq)
+static void disable_microdev_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned int fpgaIrq;
 
         if (irq >= NUM_EXTERNAL_IRQS)
@@ -91,8 +81,9 @@ static void disable_microdev_irq(unsigned int irq)
         __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
 }
 
-static void enable_microdev_irq(unsigned int irq)
+static void enable_microdev_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long priorityReg, priorities, pri;
         unsigned int fpgaIrq;
 
@@ -116,17 +107,18 @@ static void enable_microdev_irq(unsigned int irq)
         __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
 }
 
+static struct irq_chip microdev_irq_type = {
+        .name = "MicroDev-IRQ",
+        .irq_unmask = enable_microdev_irq,
+        .irq_mask = disable_microdev_irq,
+};
+
 /* This function sets the desired irq handler to be a MicroDev type */
 static void __init make_microdev_irq(unsigned int irq)
 {
         disable_irq_nosync(irq);
         set_irq_chip_and_handler(irq, &microdev_irq_type, handle_level_irq);
-        disable_microdev_irq(irq);
-}
-
-static void mask_and_ack_microdev(unsigned int irq)
-{
-        disable_microdev_irq(irq);
+        disable_microdev_irq(irq_get_irq_data(irq));
 }
 
 extern void __init init_microdev_irq(void)
diff --git a/arch/sh/boards/mach-microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c
index d1df2a4fb9b8..d8a747291e03 100644
--- a/arch/sh/boards/mach-microdev/setup.c
+++ b/arch/sh/boards/mach-microdev/setup.c
@@ -195,27 +195,6 @@ device_initcall(microdev_devices_setup);
 static struct sh_machine_vector mv_sh4202_microdev __initmv = {
         .mv_name                = "SH4-202 MicroDev",
         .mv_nr_irqs             = 72,
-
-        .mv_inb                 = microdev_inb,
-        .mv_inw                 = microdev_inw,
-        .mv_inl                 = microdev_inl,
-        .mv_outb                = microdev_outb,
-        .mv_outw                = microdev_outw,
-        .mv_outl                = microdev_outl,
-
-        .mv_inb_p               = microdev_inb_p,
-        .mv_inw_p               = microdev_inw_p,
-        .mv_inl_p               = microdev_inl_p,
-        .mv_outb_p              = microdev_outb_p,
-        .mv_outw_p              = microdev_outw_p,
-        .mv_outl_p              = microdev_outl_p,
-
-        .mv_insb                = microdev_insb,
-        .mv_insw                = microdev_insw,
-        .mv_insl                = microdev_insl,
-        .mv_outsb               = microdev_outsb,
-        .mv_outsw               = microdev_outsw,
-        .mv_outsl               = microdev_outsl,
-
+        .mv_ioport_map          = microdev_ioport_map,
         .mv_init_irq            = init_microdev_irq,
 };
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 662debe4ead2..c8acfec98695 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -213,51 +213,55 @@ static struct platform_device migor_nand_flash_device = {
         }
 };
 
+const static struct fb_videomode migor_lcd_modes[] = {
+        {
+#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
+                .name = "LB070WV1",
+                .xres = 800,
+                .yres = 480,
+                .left_margin = 64,
+                .right_margin = 16,
+                .hsync_len = 120,
+                .sync = 0,
+#elif defined(CONFIG_SH_MIGOR_QVGA)
+                .name = "PH240320T",
+                .xres = 320,
+                .yres = 240,
+                .left_margin = 0,
+                .right_margin = 16,
+                .hsync_len = 8,
+                .sync = FB_SYNC_HOR_HIGH_ACT,
+#endif
+                .upper_margin = 1,
+                .lower_margin = 17,
+                .vsync_len = 2,
+        },
+};
+
 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
-#ifdef CONFIG_SH_MIGOR_RTA_WVGA
+#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
         .clock_source = LCDC_CLK_BUS,
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
                 .interface_type = RGB16,
                 .clock_divider = 2,
-                .lcd_cfg = {
-                        .name = "LB070WV1",
-                        .xres = 800,
-                        .yres = 480,
-                        .left_margin = 64,
-                        .right_margin = 16,
-                        .hsync_len = 120,
-                        .upper_margin = 1,
-                        .lower_margin = 17,
-                        .vsync_len = 2,
-                        .sync = 0,
-                },
+                .lcd_cfg = migor_lcd_modes,
+                .num_cfg = ARRAY_SIZE(migor_lcd_modes),
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
                 },
         }
-#endif
-#ifdef CONFIG_SH_MIGOR_QVGA
+#elif defined(CONFIG_SH_MIGOR_QVGA)
         .clock_source = LCDC_CLK_PERIPHERAL,
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
                 .interface_type = SYS16A,
                 .clock_divider = 10,
-                .lcd_cfg = {
-                        .name = "PH240320T",
-                        .xres = 320,
-                        .yres = 240,
-                        .left_margin = 0,
-                        .right_margin = 16,
-                        .hsync_len = 8,
-                        .upper_margin = 1,
-                        .lower_margin = 17,
-                        .vsync_len = 2,
-                        .sync = FB_SYNC_HOR_HIGH_ACT,
-                },
+                .lcd_cfg = migor_lcd_modes,
+                .num_cfg = ARRAY_SIZE(migor_lcd_modes),
                 .lcd_size_cfg = { /* 2.4 inch */
                         .width = 49,
                         .height = 37,
@@ -450,7 +454,6 @@ static struct soc_camera_link ov7725_link = {
         .power          = ov7725_power,
         .board_info     = &migor_i2c_camera[0],
         .i2c_adapter_id = 0,
-        .module_name    = "ov772x",
         .priv           = &ov7725_info,
 };
 
@@ -463,7 +466,6 @@ static struct soc_camera_link tw9910_link = {
         .power          = tw9910_power,
         .board_info     = &migor_i2c_camera[1],
         .i2c_adapter_id = 0,
-        .module_name    = "tw9910",
         .priv           = &tw9910_info,
 };
 
diff --git a/arch/sh/boards/mach-se/7206/Makefile b/arch/sh/boards/mach-se/7206/Makefile
index 63e7ed699f39..5c9eaa0535b9 100644
--- a/arch/sh/boards/mach-se/7206/Makefile
+++ b/arch/sh/boards/mach-se/7206/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the 7206 SolutionEngine specific parts of the kernel
 #
 
-obj-y    := setup.o io.o irq.o
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/mach-se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c
deleted file mode 100644
index adadc77532ee..000000000000
--- a/arch/sh/boards/mach-se/7206/io.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* $Id: io.c,v 1.5 2004/02/22 23:08:43 kkojima Exp $
- *
- * linux/arch/sh/boards/se/7206/io.c
- *
- * Copyright (C) 2006 Yoshinori Sato
- *
- * I/O routine for Hitachi 7206 SolutionEngine.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <mach-se/mach/se7206.h>
-
-
-static inline void delay(void)
-{
-        __raw_readw(0x20000000);  /* P2 ROM Area */
-}
-
-/* MS7750 requires special versions of in*, out* routines, since
-   PC-like io ports are located at upper half byte of 16-bit word which
-   can be accessed only with 16-bit wide.  */
-
-static inline volatile __u16 *
-port2adr(unsigned int port)
-{
-        if (port >= 0x2000 && port < 0x2020)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        else if (port >= 0x300 && port < 0x310)
-                return (volatile __u16 *) (PA_SMSC + (port - 0x300));
-
-        return (volatile __u16 *)port;
-}
-
-unsigned char se7206_inb(unsigned long port)
-{
-        return (*port2adr(port)) & 0xff;
-}
-
-unsigned char se7206_inb_p(unsigned long port)
-{
-        unsigned long v;
-
-        v = (*port2adr(port)) & 0xff;
-        delay();
-        return v;
-}
-
-unsigned short se7206_inw(unsigned long port)
-{
-        return *port2adr(port);
-}
-
-void se7206_outb(unsigned char value, unsigned long port)
-{
-        *(port2adr(port)) = value;
-}
-
-void se7206_outb_p(unsigned char value, unsigned long port)
-{
-        *(port2adr(port)) = value;
-        delay();
-}
-
-void se7206_outw(unsigned short value, unsigned long port)
-{
-        *port2adr(port) = value;
-}
-
-void se7206_insb(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u8 *ap = addr;
-
-        while (count--)
-                *ap++ = *p;
-}
-
-void se7206_insw(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u16 *ap = addr;
-        while (count--)
-                *ap++ = *p;
-}
-
-void se7206_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u8 *ap = addr;
-
-        while (count--)
-                *p = *ap++;
-}
-
-void se7206_outsw(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u16 *ap = addr;
-        while (count--)
-                *p = *ap++;
-}
diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c
index 8d82175d83ab..d961949600fd 100644
--- a/arch/sh/boards/mach-se/7206/irq.c
+++ b/arch/sh/boards/mach-se/7206/irq.c
@@ -25,8 +25,9 @@
 #define INTC_IPR01 0xfffe0818
 #define INTC_ICR1  0xfffe0802
 
-static void disable_se7206_irq(unsigned int irq)
+static void disable_se7206_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short val;
         unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
         unsigned short msk0,msk1;
@@ -55,8 +56,9 @@ static void disable_se7206_irq(unsigned int irq)
         __raw_writew(msk1, INTMSK1);
 }
 
-static void enable_se7206_irq(unsigned int irq)
+static void enable_se7206_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short val;
         unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
         unsigned short msk0,msk1;
@@ -86,13 +88,14 @@ static void enable_se7206_irq(unsigned int irq)
         __raw_writew(msk1, INTMSK1);
 }
 
-static void eoi_se7206_irq(unsigned int irq)
+static void eoi_se7206_irq(struct irq_data *data)
 {
         unsigned short sts0,sts1;
+        unsigned int irq = data->irq;
         struct irq_desc *desc = irq_to_desc(irq);
 
         if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-                enable_se7206_irq(irq);
+                enable_se7206_irq(data);
         /* FPGA isr clear */
         sts0 = __raw_readw(INTSTS0);
         sts1 = __raw_readw(INTSTS1);
@@ -115,10 +118,9 @@ static void eoi_se7206_irq(unsigned int irq)
 
 static struct irq_chip se7206_irq_chip __read_mostly = {
         .name           = "SE7206-FPGA",
-        .mask           = disable_se7206_irq,
-        .unmask         = enable_se7206_irq,
-        .mask_ack       = disable_se7206_irq,
-        .eoi            = eoi_se7206_irq,
+        .irq_mask       = disable_se7206_irq,
+        .irq_unmask     = enable_se7206_irq,
+        .irq_eoi        = eoi_se7206_irq,
 };
 
 static void make_se7206_irq(unsigned int irq)
@@ -126,7 +128,7 @@ static void make_se7206_irq(unsigned int irq)
         disable_irq_nosync(irq);
         set_irq_chip_and_handler_name(irq, &se7206_irq_chip,
                                       handle_level_irq, "level");
-        disable_se7206_irq(irq);
+        disable_se7206_irq(irq_get_irq_data(irq));
 }
 
 /*
@@ -137,11 +139,13 @@ void __init init_se7206_IRQ(void)
         make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
         make_se7206_irq(IRQ1_IRQ); /* ATA */
         make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
-        __raw_writew(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
+
+        __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR); /* ICR1 */
 
         /* FPGA System register setup*/
         __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
         __raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
+
         /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
         __raw_writew(0x0001,INTSEL);
 }
diff --git a/arch/sh/boards/mach-se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c
index 8f5c65d43d1d..7f4871c71a01 100644
--- a/arch/sh/boards/mach-se/7206/setup.c
+++ b/arch/sh/boards/mach-se/7206/setup.c
@@ -86,20 +86,5 @@ __initcall(se7206_devices_setup);
 static struct sh_machine_vector mv_se __initmv = {
         .mv_name                = "SolutionEngine",
         .mv_nr_irqs             = 256,
-        .mv_inb                 = se7206_inb,
-        .mv_inw                 = se7206_inw,
-        .mv_outb                = se7206_outb,
-        .mv_outw                = se7206_outw,
-
-        .mv_inb_p               = se7206_inb_p,
-        .mv_inw_p               = se7206_inw,
-        .mv_outb_p              = se7206_outb_p,
-        .mv_outw_p              = se7206_outw,
-
-        .mv_insb                = se7206_insb,
-        .mv_insw                = se7206_insw,
-        .mv_outsb               = se7206_outsb,
-        .mv_outsw               = se7206_outsw,
-
         .mv_init_irq            = init_se7206_IRQ,
 };
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
index d4305c26e9f7..76255a19417f 100644
--- a/arch/sh/boards/mach-se/7343/irq.c
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -18,23 +18,22 @@
 
 unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
 
-static void disable_se7343_irq(unsigned int irq)
+static void disable_se7343_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
 }
 
-static void enable_se7343_irq(unsigned int irq)
+static void enable_se7343_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
 }
 
 static struct irq_chip se7343_irq_chip __read_mostly = {
-        .name           = "SE7343-FPGA",
-        .mask           = disable_se7343_irq,
-        .unmask         = enable_se7343_irq,
-        .mask_ack       = disable_se7343_irq,
+        .name           = "SE7343-FPGA",
+        .irq_mask       = disable_se7343_irq,
+        .irq_unmask     = enable_se7343_irq,
 };
 
 static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/sh/boards/mach-se/770x/Makefile b/arch/sh/boards/mach-se/770x/Makefile
index 8e624b06d5ea..43ea14feef51 100644
--- a/arch/sh/boards/mach-se/770x/Makefile
+++ b/arch/sh/boards/mach-se/770x/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the 770x SolutionEngine specific parts of the kernel
 #
 
-obj-y    := setup.o io.o irq.o
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/mach-se/770x/io.c b/arch/sh/boards/mach-se/770x/io.c
deleted file mode 100644
index 28833c8786ea..000000000000
--- a/arch/sh/boards/mach-se/770x/io.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * I/O routine for Hitachi SolutionEngine.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <mach-se/mach/se.h>
-
-/* MS7750 requires special versions of in*, out* routines, since
-   PC-like io ports are located at upper half byte of 16-bit word which
-   can be accessed only with 16-bit wide.  */
-
-static inline volatile __u16 *
-port2adr(unsigned int port)
-{
-        if (port & 0xff000000)
-                return ( volatile __u16 *) port;
-        if (port >= 0x2000)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        else if (port >= 0x1000)
-                return (volatile __u16 *) (PA_83902 + (port << 1));
-        else
-                return (volatile __u16 *) (PA_SUPERIO + (port << 1));
-}
-
-static inline int
-shifted_port(unsigned long port)
-{
-        /* For IDE registers, value is not shifted */
-        if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
-                return 0;
-        else
-                return 1;
-}
-
-unsigned char se_inb(unsigned long port)
-{
-        if (shifted_port(port))
-                return (*port2adr(port) >> 8);
-        else
-                return (*port2adr(port))&0xff;
-}
-
-unsigned char se_inb_p(unsigned long port)
-{
-        unsigned long v;
-
-        if (shifted_port(port))
-                v = (*port2adr(port) >> 8);
-        else
-                v = (*port2adr(port))&0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short se_inw(unsigned long port)
-{
-        if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int se_inl(unsigned long port)
-{
-        maybebadio(port);
-        return 0;
-}
-
-void se_outb(unsigned char value, unsigned long port)
-{
-        if (shifted_port(port))
-                *(port2adr(port)) = value << 8;
-        else
-                *(port2adr(port)) = value;
-}
-
-void se_outb_p(unsigned char value, unsigned long port)
-{
-        if (shifted_port(port))
-                *(port2adr(port)) = value << 8;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void se_outw(unsigned short value, unsigned long port)
-{
-        if (port >= 0x2000)
-                *port2adr(port) = value;
-        else
-                maybebadio(port);
-}
-
-void se_outl(unsigned int value, unsigned long port)
-{
-        maybebadio(port);
-}
-
-void se_insb(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u8 *ap = addr;
-
-        if (shifted_port(port)) {
-                while (count--)
-                        *ap++ = *p >> 8;
-        } else {
-                while (count--)
-                        *ap++ = *p;
-        }
-}
-
-void se_insw(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u16 *ap = addr;
-        while (count--)
-                *ap++ = *p;
-}
-
-void se_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void se_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u8 *ap = addr;
-
-        if (shifted_port(port)) {
-                while (count--)
-                        *p = *ap++ << 8;
-        } else {
-                while (count--)
-                        *p = *ap++;
-        }
-}
-
-void se_outsw(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u16 *ap = addr;
-
-        while (count--)
-                *p = *ap++;
-}
-
-void se_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c
index 66d39d1b0901..31330c65c0ce 100644
--- a/arch/sh/boards/mach-se/770x/setup.c
+++ b/arch/sh/boards/mach-se/770x/setup.c
@@ -195,27 +195,5 @@ static struct sh_machine_vector mv_se __initmv = {
 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
         .mv_nr_irqs             = 104,
 #endif
-
-        .mv_inb                 = se_inb,
-        .mv_inw                 = se_inw,
-        .mv_inl                 = se_inl,
-        .mv_outb                = se_outb,
-        .mv_outw                = se_outw,
-        .mv_outl                = se_outl,
-
-        .mv_inb_p               = se_inb_p,
-        .mv_inw_p               = se_inw,
-        .mv_inl_p               = se_inl,
-        .mv_outb_p              = se_outb_p,
-        .mv_outw_p              = se_outw,
-        .mv_outl_p              = se_outl,
-
-        .mv_insb                = se_insb,
-        .mv_insw                = se_insw,
-        .mv_insl                = se_insl,
-        .mv_outsb               = se_outsb,
-        .mv_outsw               = se_outsw,
-        .mv_outsl               = se_outsl,
-
         .mv_init_irq            = init_se_IRQ,
 };
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index 61605db04ee6..c013f95628ed 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -18,23 +18,22 @@
 
 unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };
 
-static void disable_se7722_irq(unsigned int irq)
+static void disable_se7722_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
 }
 
-static void enable_se7722_irq(unsigned int irq)
+static void enable_se7722_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
 }
 
 static struct irq_chip se7722_irq_chip __read_mostly = {
-        .name           = "SE7722-FPGA",
-        .mask           = disable_se7722_irq,
-        .unmask         = enable_se7722_irq,
-        .mask_ack       = disable_se7722_irq,
+        .name           = "SE7722-FPGA",
+        .irq_mask       = disable_se7722_irq,
+        .irq_unmask     = enable_se7722_irq,
 };
 
 static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
index 0942be2daef6..5bd87c22b65b 100644
--- a/arch/sh/boards/mach-se/7724/irq.c
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -68,25 +68,26 @@ static struct fpga_irq get_fpga_irq(unsigned int irq)
         return set;
 }
 
-static void disable_se7724_irq(unsigned int irq)
+static void disable_se7724_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
         unsigned int bit = irq - set.base;
         __raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
 }
 
-static void enable_se7724_irq(unsigned int irq)
+static void enable_se7724_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
         unsigned int bit = irq - set.base;
         __raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
 }
 
 static struct irq_chip se7724_irq_chip __read_mostly = {
-        .name           = "SE7724-FPGA",
-        .mask           = disable_se7724_irq,
-        .unmask         = enable_se7724_irq,
-        .mask_ack       = disable_se7724_irq,
+        .name           = "SE7724-FPGA",
+        .irq_mask       = disable_se7724_irq,
+        .irq_unmask     = enable_se7724_irq,
 };
 
 static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 552ebd9ba82b..c31d228fdfc6 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -144,16 +144,42 @@ static struct platform_device nor_flash_device = {
 };
 
 /* LCDC */
+const static struct fb_videomode lcdc_720p_modes[] = {
+        {
+                .name           = "LB070WV1",
+                .sync           = 0, /* hsync and vsync are active low */
+                .xres           = 1280,
+                .yres           = 720,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 40,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+        },
+};
+
+const static struct fb_videomode lcdc_vga_modes[] = {
+        {
+                .name           = "LB070WV1",
+                .sync           = 0, /* hsync and vsync are active low */
+                .xres           = 640,
+                .yres           = 480,
+                .left_margin    = 105,
+                .right_margin   = 50,
+                .hsync_len      = 96,
+                .upper_margin   = 33,
+                .lower_margin   = 10,
+                .vsync_len      = 2,
+        },
+};
+
 static struct sh_mobile_lcdc_info lcdc_info = {
         .clock_source = LCDC_CLK_EXTERNAL,
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
                 .clock_divider = 1,
-                .lcd_cfg = {
-                        .name = "LB070WV1",
-                        .sync = 0, /* hsync and vsync are active low */
-                },
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
@@ -550,7 +576,6 @@ static struct sh_vou_pdata sh_vou_pdata = {
         .flags          = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
         .board_info     = &ak8813,
         .i2c_adap       = 0,
-        .module_name    = "ak881x",
 };
 
 static struct resource sh_vou_resources[] = {
@@ -909,24 +934,12 @@ static int __init devices_setup(void)
 
         if (sw & SW41_B) {
                 /* 720p */
-                lcdc_info.ch[0].lcd_cfg.xres         = 1280;
-                lcdc_info.ch[0].lcd_cfg.yres         = 720;
-                lcdc_info.ch[0].lcd_cfg.left_margin  = 220;
-                lcdc_info.ch[0].lcd_cfg.right_margin = 110;
-                lcdc_info.ch[0].lcd_cfg.hsync_len    = 40;
-                lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
-                lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
-                lcdc_info.ch[0].lcd_cfg.vsync_len    = 5;
+                lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
+                lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
         } else {
                 /* VGA */
-                lcdc_info.ch[0].lcd_cfg.xres         = 640;
-                lcdc_info.ch[0].lcd_cfg.yres         = 480;
-                lcdc_info.ch[0].lcd_cfg.left_margin  = 105;
-                lcdc_info.ch[0].lcd_cfg.right_margin = 50;
-                lcdc_info.ch[0].lcd_cfg.hsync_len    = 96;
-                lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
-                lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
-                lcdc_info.ch[0].lcd_cfg.vsync_len    = 2;
+                lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
+                lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
         }
 
         if (sw & SW41_A) {
diff --git a/arch/sh/boards/mach-se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile
index e6f4341bfe6e..a338fd9d5039 100644
--- a/arch/sh/boards/mach-se/7751/Makefile
+++ b/arch/sh/boards/mach-se/7751/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the 7751 SolutionEngine specific parts of the kernel
 #
 
-obj-y    := setup.o io.o irq.o
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/mach-se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c
deleted file mode 100644
index 6e75bd4459e5..000000000000
--- a/arch/sh/boards/mach-se/7751/io.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routine for Hitachi 7751 SolutionEngine.
- *
- * Initial version only to support LAN access; some
- * placeholder code from io_se.c left in with the
- * expectation of later SuperIO and PCMCIA access.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-#include <mach-se/mach/se7751.h>
-#include <asm/addrspace.h>
-
-static inline volatile u16 *port2adr(unsigned int port)
-{
-        if (port >= 0x2000)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        maybebadio((unsigned long)port);
-        return (volatile __u16*)port;
-}
-
-/*
- * General outline: remap really low stuff [eventually] to SuperIO,
- * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
- * is mapped through the PCI IO window.  Stuff with high bits (PXSEG)
- * should be way beyond the window, and is used  w/o translation for
- * compatibility.
- */
-unsigned char sh7751se_inb(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned char *)port;
-        else
-                return (*port2adr(port)) & 0xff;
-}
-
-unsigned char sh7751se_inb_p(unsigned long port)
-{
-        unsigned char v;
-
-        if (PXSEG(port))
-                v = *(volatile unsigned char *)port;
-        else
-                v = (*port2adr(port)) & 0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short sh7751se_inw(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned short *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int sh7751se_inl(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned long *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-void sh7751se_outb(unsigned char value, unsigned long port)
-{
-
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-}
-
-void sh7751se_outb_p(unsigned char value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void sh7751se_outw(unsigned short value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned short *)port = value;
-        else if (port >= 0x2000)
-                *port2adr(port) = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751se_outl(unsigned int value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned long *)port = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751se_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-se/7751/setup.c b/arch/sh/boards/mach-se/7751/setup.c
index 50572512e3e8..9fbc51beb181 100644
--- a/arch/sh/boards/mach-se/7751/setup.c
+++ b/arch/sh/boards/mach-se/7751/setup.c
@@ -56,23 +56,5 @@ __initcall(se7751_devices_setup);
 static struct sh_machine_vector mv_7751se __initmv = {
         .mv_name                = "7751 SolutionEngine",
         .mv_nr_irqs             = 72,
-
-        .mv_inb                 = sh7751se_inb,
-        .mv_inw                 = sh7751se_inw,
-        .mv_inl                 = sh7751se_inl,
-        .mv_outb                = sh7751se_outb,
-        .mv_outw                = sh7751se_outw,
-        .mv_outl                = sh7751se_outl,
-
-        .mv_inb_p               = sh7751se_inb_p,
-        .mv_inw_p               = sh7751se_inw,
-        .mv_inl_p               = sh7751se_inl,
-        .mv_outb_p              = sh7751se_outb_p,
-        .mv_outw_p              = sh7751se_outw,
-        .mv_outl_p              = sh7751se_outl,
-
-        .mv_insl                = sh7751se_insl,
-        .mv_outsl               = sh7751se_outsl,
-
         .mv_init_irq            = init_7751se_IRQ,
 };
diff --git a/arch/sh/boards/mach-snapgear/Makefile b/arch/sh/boards/mach-snapgear/Makefile
deleted file mode 100644
index d2d2f4b6a502..000000000000
--- a/arch/sh/boards/mach-snapgear/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the SnapGear specific parts of the kernel
-#
-
-obj-y    := setup.o io.o
diff --git a/arch/sh/boards/mach-snapgear/io.c b/arch/sh/boards/mach-snapgear/io.c
deleted file mode 100644
index 476650e42dbc..000000000000
--- a/arch/sh/boards/mach-snapgear/io.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (C) 2002  David McCullough <davidm@snapgear.com>
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routine for Hitachi 7751 SolutionEngine.
- *
- * Initial version only to support LAN access; some
- * placeholder code from io_se.c left in with the
- * expectation of later SuperIO and PCMCIA access.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-#include <asm/addrspace.h>
-
-#ifdef CONFIG_SH_SECUREEDGE5410
-unsigned short secureedge5410_ioport;
-#endif
-
-static inline volatile __u16 *port2adr(unsigned int port)
-{
-        maybebadio((unsigned long)port);
-        return (volatile __u16*)port;
-}
-
-/*
- * General outline: remap really low stuff [eventually] to SuperIO,
- * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
- * is mapped through the PCI IO window.  Stuff with high bits (PXSEG)
- * should be way beyond the window, and is used  w/o translation for
- * compatibility.
- */
-unsigned char snapgear_inb(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned char *)port;
-        else
-                return (*port2adr(port)) & 0xff;
-}
-
-unsigned char snapgear_inb_p(unsigned long port)
-{
-        unsigned char v;
-
-        if (PXSEG(port))
-                v = *(volatile unsigned char *)port;
-        else
-                v = (*port2adr(port))&0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short snapgear_inw(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned short *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int snapgear_inl(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned long *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-void snapgear_outb(unsigned char value, unsigned long port)
-{
-
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-}
-
-void snapgear_outb_p(unsigned char value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void snapgear_outw(unsigned short value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned short *)port = value;
-        else if (port >= 0x2000)
-                *port2adr(port) = value;
-        else
-                maybebadio(port);
-}
-
-void snapgear_outl(unsigned int value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned long *)port = value;
-        else
-                maybebadio(port);
-}
-
-void snapgear_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void snapgear_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-systemh/Makefile b/arch/sh/boards/mach-systemh/Makefile
deleted file mode 100644
index 2cc6a23d9d39..000000000000
--- a/arch/sh/boards/mach-systemh/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile for the SystemH specific parts of the kernel
-#
-
-obj-y    := setup.o irq.o io.o
-
-# XXX: This wants to be consolidated in arch/sh/drivers/pci, and more
-# importantly, with the generic sh7751_pcic_init() code. For now, we'll
-# just abuse the hell out of kbuild, because we can..
-
-obj-$(CONFIG_PCI) += pci.o
-pci-y := ../../se/7751/pci.o
-
diff --git a/arch/sh/boards/mach-systemh/io.c b/arch/sh/boards/mach-systemh/io.c
deleted file mode 100644
index 15577ff1f715..000000000000
--- a/arch/sh/boards/mach-systemh/io.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * linux/arch/sh/boards/renesas/systemh/io.c
- *
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routine for Hitachi 7751 Systemh.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <mach/systemh7751.h>
-#include <asm/addrspace.h>
-#include <asm/io.h>
-
-#define ETHER_IOMAP(adr) (0xB3000000 + (adr)) /*map to 16bits access area
-                                                of smc lan chip*/
-static inline volatile __u16 *
-port2adr(unsigned int port)
-{
-        if (port >= 0x2000)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        maybebadio((unsigned long)port);
-        return (volatile __u16*)port;
-}
-
-/*
- * General outline: remap really low stuff [eventually] to SuperIO,
- * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
- * is mapped through the PCI IO window.  Stuff with high bits (PXSEG)
- * should be way beyond the window, and is used  w/o translation for
- * compatibility.
- */
-unsigned char sh7751systemh_inb(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned char *)port;
-        else if (port <= 0x3F1)
-                return *(volatile unsigned char *)ETHER_IOMAP(port);
-        else
-                return (*port2adr(port))&0xff;
-}
-
-unsigned char sh7751systemh_inb_p(unsigned long port)
-{
-        unsigned char v;
-
-        if (PXSEG(port))
-                v = *(volatile unsigned char *)port;
-        else if (port <= 0x3F1)
-                v = *(volatile unsigned char *)ETHER_IOMAP(port);
-        else
-                v = (*port2adr(port))&0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short sh7751systemh_inw(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned short *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else if (port <= 0x3F1)
-                return *(volatile unsigned int *)ETHER_IOMAP(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int sh7751systemh_inl(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned long *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else if (port <= 0x3F1)
-                return *(volatile unsigned int *)ETHER_IOMAP(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-void sh7751systemh_outb(unsigned char value, unsigned long port)
-{
-
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else if (port <= 0x3F1)
-                *(volatile unsigned char *)ETHER_IOMAP(port) = value;
-        else
-                *(port2adr(port)) = value;
-}
-
-void sh7751systemh_outb_p(unsigned char value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else if (port <= 0x3F1)
-                *(volatile unsigned char *)ETHER_IOMAP(port) = value;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void sh7751systemh_outw(unsigned short value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned short *)port = value;
-        else if (port >= 0x2000)
-                *port2adr(port) = value;
-        else if (port <= 0x3F1)
-                *(volatile unsigned short *)ETHER_IOMAP(port) = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751systemh_outl(unsigned int value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned long *)port = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count)
-{
-        unsigned char *p = addr;
-        while (count--) *p++ = sh7751systemh_inb(port);
-}
-
-void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count)
-{
-        unsigned short *p = addr;
-        while (count--) *p++ = sh7751systemh_inw(port);
-}
-
-void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        unsigned char *p = (unsigned char*)addr;
-        while (count--) sh7751systemh_outb(*p++, port);
-}
-
-void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count)
-{
-        unsigned short *p = (unsigned short*)addr;
-        while (count--) sh7751systemh_outw(*p++, port);
-}
-
-void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-systemh/irq.c b/arch/sh/boards/mach-systemh/irq.c
deleted file mode 100644
index 523aea5dc94e..000000000000
--- a/arch/sh/boards/mach-systemh/irq.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * linux/arch/sh/boards/renesas/systemh/irq.c
- *
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * Hitachi SystemH Support.
- *
- * Modified for 7751 SystemH by
- * Jonathan Short.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-
-#include <mach/systemh7751.h>
-#include <asm/smc37c93x.h>
-
-/* address of external interrupt mask register
- * address must be set prior to use these (maybe in init_XXX_irq())
- * XXX : is it better to use .config than specifying it in code? */
-static unsigned long *systemh_irq_mask_register = (unsigned long *)0xB3F10004;
-static unsigned long *systemh_irq_request_register = (unsigned long *)0xB3F10000;
-
-/* forward declaration */
-static void enable_systemh_irq(unsigned int irq);
-static void disable_systemh_irq(unsigned int irq);
-static void mask_and_ack_systemh(unsigned int);
-
-static struct irq_chip systemh_irq_type = {
-        .name = " SystemH Register",
-        .unmask = enable_systemh_irq,
-        .mask = disable_systemh_irq,
-        .ack = mask_and_ack_systemh,
-};
-
-static void disable_systemh_irq(unsigned int irq)
-{
-        if (systemh_irq_mask_register) {
-                unsigned long val, mask = 0x01 << 1;
-
-                /* Clear the "irq"th bit in the mask and set it in the request */
-                val = __raw_readl((unsigned long)systemh_irq_mask_register);
-                val &= ~mask;
-                __raw_writel(val, (unsigned long)systemh_irq_mask_register);
-
-                val = __raw_readl((unsigned long)systemh_irq_request_register);
-                val |= mask;
-                __raw_writel(val, (unsigned long)systemh_irq_request_register);
-        }
-}
-
-static void enable_systemh_irq(unsigned int irq)
-{
-        if (systemh_irq_mask_register) {
-                unsigned long val, mask = 0x01 << 1;
-
-                /* Set "irq"th bit in the mask register */
-                val = __raw_readl((unsigned long)systemh_irq_mask_register);
-                val |= mask;
-                __raw_writel(val, (unsigned long)systemh_irq_mask_register);
-        }
-}
-
-static void mask_and_ack_systemh(unsigned int irq)
-{
-        disable_systemh_irq(irq);
-}
-
-void make_systemh_irq(unsigned int irq)
-{
-        disable_irq_nosync(irq);
-        set_irq_chip_and_handler(irq, &systemh_irq_type, handle_level_irq);
-        disable_systemh_irq(irq);
-}
diff --git a/arch/sh/boards/mach-systemh/setup.c b/arch/sh/boards/mach-systemh/setup.c
deleted file mode 100644
index 219fd800a43f..000000000000
--- a/arch/sh/boards/mach-systemh/setup.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/arch/sh/boards/renesas/systemh/setup.c
- *
- * Copyright (C) 2000  Kazumoto Kojima
- * Copyright (C) 2003  Paul Mundt
- *
- * Hitachi SystemH Support.
- *
- * Modified for 7751 SystemH by Jonathan Short.
- *
- * Rewritten for 2.6 by Paul Mundt.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <asm/machvec.h>
-#include <mach/systemh7751.h>
-
-extern void make_systemh_irq(unsigned int irq);
-
-/*
- * Initialize IRQ setting
- */
-static void __init sh7751systemh_init_irq(void)
-{
-        make_systemh_irq(0xb);  /* Ethernet interrupt */
-}
-
-static struct sh_machine_vector mv_7751systemh __initmv = {
-        .mv_name                = "7751 SystemH",
-        .mv_nr_irqs             = 72,
-
-        .mv_inb                 = sh7751systemh_inb,
-        .mv_inw                 = sh7751systemh_inw,
-        .mv_inl                 = sh7751systemh_inl,
-        .mv_outb                = sh7751systemh_outb,
-        .mv_outw                = sh7751systemh_outw,
-        .mv_outl                = sh7751systemh_outl,
-
-        .mv_inb_p               = sh7751systemh_inb_p,
-        .mv_inw_p               = sh7751systemh_inw,
-        .mv_inl_p               = sh7751systemh_inl,
-        .mv_outb_p              = sh7751systemh_outb_p,
-        .mv_outw_p              = sh7751systemh_outw,
-        .mv_outl_p              = sh7751systemh_outl,
-
-        .mv_insb                = sh7751systemh_insb,
-        .mv_insw                = sh7751systemh_insw,
-        .mv_insl                = sh7751systemh_insl,
-        .mv_outsb               = sh7751systemh_outsb,
-        .mv_outsw               = sh7751systemh_outsw,
-        .mv_outsl               = sh7751systemh_outsl,
-
-        .mv_init_irq            = sh7751systemh_init_irq,
-};
diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c
index 594adf76e46a..239e74066253 100644
--- a/arch/sh/boards/mach-x3proto/gpio.c
+++ b/arch/sh/boards/mach-x3proto/gpio.c
@@ -54,18 +54,19 @@ static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
 
 static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_data *data = irq_get_irq_data(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
         unsigned long mask;
         int pin;
 
-        chip->mask_ack(irq);
+        chip->irq_mask_ack(data);
 
         mask = __raw_readw(KEYDETR);
 
         for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
                 generic_handle_irq(x3proto_gpio_to_irq(NULL, pin));
 
-        chip->unmask(irq);
+        chip->irq_unmask(data);
 }
 
 struct gpio_chip x3proto_gpio_chip = {
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index bcb31ae84a51..177a10b25cad 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -17,8 +17,9 @@
 /* This belongs in cpu specific */
 #define INTC_ICR1 0xA4140010UL
 
-static void hd64461_mask_irq(unsigned int irq)
+static void hd64461_mask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short nimr;
         unsigned short mask = 1 << (irq - HD64461_IRQBASE);
 
@@ -27,8 +28,9 @@ static void hd64461_mask_irq(unsigned int irq)
         __raw_writew(nimr, HD64461_NIMR);
 }
 
-static void hd64461_unmask_irq(unsigned int irq)
+static void hd64461_unmask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short nimr;
         unsigned short mask = 1 << (irq - HD64461_IRQBASE);
 
@@ -37,20 +39,21 @@ static void hd64461_unmask_irq(unsigned int irq)
         __raw_writew(nimr, HD64461_NIMR);
 }
 
-static void hd64461_mask_and_ack_irq(unsigned int irq)
+static void hd64461_mask_and_ack_irq(struct irq_data *data)
 {
-        hd64461_mask_irq(irq);
+        hd64461_mask_irq(data);
+
 #ifdef CONFIG_HD64461_ENABLER
-        if (irq == HD64461_IRQBASE + 13)
+        if (data->irq == HD64461_IRQBASE + 13)
                 __raw_writeb(0x00, HD64461_PCC1CSCR);
 #endif
 }
 
 static struct irq_chip hd64461_irq_chip = {
         .name           = "HD64461-IRQ",
-        .mask           = hd64461_mask_irq,
-        .mask_ack       = hd64461_mask_and_ack_irq,
-        .unmask         = hd64461_unmask_irq,
+        .irq_mask       = hd64461_mask_irq,
+        .irq_mask_ack   = hd64461_mask_and_ack_irq,
+        .irq_unmask     = hd64461_unmask_irq,
 };
 
 static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/sh/configs/snapgear_defconfig b/arch/sh/configs/secureedge5410_defconfig
index 7eae4e59d7f0..7eae4e59d7f0 100644
--- a/arch/sh/configs/snapgear_defconfig
+++ b/arch/sh/configs/secureedge5410_defconfig
diff --git a/arch/sh/configs/systemh_defconfig b/arch/sh/configs/systemh_defconfig
deleted file mode 100644
index b58dfc505efe..000000000000
--- a/arch/sh/configs/systemh_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_CPU_SUBTYPE_SH7751R=y
-CONFIG_MEMORY_START=0x0c000000
-CONFIG_MEMORY_SIZE=0x00400000
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_SH_7751_SYSTEMH=y
-CONFIG_PREEMPT=y
-# CONFIG_STANDALONE is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=1024
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_HW_RANDOM=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
index 446b3831c214..3d1ae2bfaa6f 100644
--- a/arch/sh/include/asm/addrspace.h
+++ b/arch/sh/include/asm/addrspace.h
@@ -44,10 +44,10 @@
 /*
  * These will never work in 32-bit, don't even bother.
  */
-#define P1SEGADDR(a)    __futile_remapping_attempt
-#define P2SEGADDR(a)    __futile_remapping_attempt
-#define P3SEGADDR(a)    __futile_remapping_attempt
-#define P4SEGADDR(a)    __futile_remapping_attempt
+#define P1SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
+#define P2SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
+#define P3SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
+#define P4SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
 #endif
 #endif /* P1SEG */
 
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 02f77450cd8f..083ea068e819 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -66,7 +66,6 @@ static inline unsigned long long neff_sign_extend(unsigned long val)
 #define PHYS_ADDR_MASK29                0x1fffffff
 #define PHYS_ADDR_MASK32                0xffffffff
 
-#ifdef CONFIG_PMB
 static inline unsigned long phys_addr_mask(void)
 {
         /* Is the MMU in 29bit mode? */
@@ -75,17 +74,6 @@ static inline unsigned long phys_addr_mask(void)
 
         return PHYS_ADDR_MASK32;
 }
-#elif defined(CONFIG_32BIT)
-static inline unsigned long phys_addr_mask(void)
-{
-        return PHYS_ADDR_MASK32;
-}
-#else
-static inline unsigned long phys_addr_mask(void)
-{
-        return PHYS_ADDR_MASK29;
-}
-#endif
 
 #define PTE_PHYS_MASK           (phys_addr_mask() & PAGE_MASK)
 #define PTE_FLAGS_MASK          (~(PTE_PHYS_MASK) << PAGE_SHIFT)
@@ -169,6 +157,8 @@ extern void page_table_range_init(unsigned long start, unsigned long end,
 #define HAVE_ARCH_UNMAPPED_AREA
 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 
+#define __HAVE_ARCH_PTE_SPECIAL
+
 #include <asm-generic/pgtable.h>
 
 #endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
index 69fdfbf14ea5..43528ec656ba 100644
--- a/arch/sh/include/asm/pgtable_32.h
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -378,8 +378,6 @@ PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
 PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
 PTE_BIT_FUNC(low, mkspecial, |= _PAGE_SPECIAL);
 
-#define __HAVE_ARCH_PTE_SPECIAL
-
 /*
  * Macro and implementation to make a page protection as uncachable.
  */
diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h
index 10a48111226d..42cb9dd52161 100644
--- a/arch/sh/include/asm/pgtable_64.h
+++ b/arch/sh/include/asm/pgtable_64.h
@@ -130,6 +130,7 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
  * anything above the PPN field.
  */
 #define _PAGE_WIRED     _PAGE_EXT(0x001) /* software: wire the tlb entry */
+#define _PAGE_SPECIAL   _PAGE_EXT(0x002)
 
 #define _PAGE_CLEAR_FLAGS       (_PAGE_PRESENT | _PAGE_FILE | _PAGE_SHARED | \
                                  _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_WIRED)
@@ -173,7 +174,8 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
 /* Default flags for a User page */
 #define _PAGE_TABLE     (_KERNPG_TABLE | _PAGE_USER)
 
-#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
+                         _PAGE_SPECIAL)
 
 /*
  * We have full permissions (Read/Write/Execute/Shared).
@@ -263,7 +265,7 @@ static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_DIRTY; }
 static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
 static inline int pte_file(pte_t pte)   { return pte_val(pte) & _PAGE_FILE; }
 static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_special(pte_t pte){ return 0; }
+static inline int pte_special(pte_t pte){ return pte_val(pte) & _PAGE_SPECIAL; }
 
 static inline pte_t pte_wrprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
 static inline pte_t pte_mkclean(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
@@ -272,8 +274,7 @@ static inline pte_t pte_mkwrite(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) |
 static inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
 static inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
 static inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
-static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
-
+static inline pte_t pte_mkspecial(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SPECIAL)); return pte; }
 
 /*
  * Conversion functions: convert a page and protection to a page entry.
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 0a58cb25a658..c9e7cbc4768a 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -89,6 +89,7 @@ struct sh_cpuinfo {
         struct task_struct *idle;
 #endif
 
+        unsigned int phys_bits;
         unsigned long flags;
 } __attribute__ ((aligned(L1_CACHE_BYTES)));
 
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index 1f1af5afff03..10c8b1823a18 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -10,6 +10,7 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <asm/types.h>
+#include <asm/uncached.h>
 
 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
 
@@ -137,9 +138,6 @@ extern unsigned int instruction_size(unsigned int insn);
 #define instruction_size(insn)  (4)
 #endif
 
-extern unsigned long cached_to_uncached;
-extern unsigned long uncached_size;
-
 void per_cpu_trap_init(void);
 void default_idle(void);
 void cpu_idle_wait(void);
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index c941b2739405..a4ad1cd9bc4d 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -145,42 +145,6 @@ do {								\
                 __restore_dsp(prev);                            \
 } while (0)
 
-/*
- * Jump to uncached area.
- * When handling TLB or caches, we need to do it from an uncached area.
- */
-#define jump_to_uncached()                      \
-do {                                            \
-        unsigned long __dummy;                  \
-                                                \
-        __asm__ __volatile__(                   \
-                "mova   1f, %0\n\t"             \
-                "add    %1, %0\n\t"             \
-                "jmp    @%0\n\t"                \
-                " nop\n\t"                      \
-                ".balign 4\n"                   \
-                "1:"                            \
-                : "=&z" (__dummy)               \
-                : "r" (cached_to_uncached));    \
-} while (0)
-
-/*
- * Back to cached area.
- */
-#define back_to_cached()                                \
-do {                                                    \
-        unsigned long __dummy;                          \
-        ctrl_barrier();                                 \
-        __asm__ __volatile__(                           \
-                "mov.l  1f, %0\n\t"                     \
-                "jmp    @%0\n\t"                        \
-                " nop\n\t"                              \
-                ".balign 4\n"                           \
-                "1:     .long 2f\n"                     \
-                "2:"                                    \
-                : "=&r" (__dummy));                     \
-} while (0)
-
 #ifdef CONFIG_CPU_HAS_SR_RB
 #define lookup_exception_vector()       \
 ({                                      \
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
index 36338646dfc8..8593bc8d1a4e 100644
--- a/arch/sh/include/asm/system_64.h
+++ b/arch/sh/include/asm/system_64.h
@@ -34,9 +34,6 @@ do {								\
                               &next->thread);                   \
 } while (0)
 
-#define jump_to_uncached()      do { } while (0)
-#define back_to_cached()        do { } while (0)
-
 #define __icbi(addr)    __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
 #define __ocbp(addr)    __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
 #define __ocbi(addr)    __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
diff --git a/arch/sh/include/asm/uncached.h b/arch/sh/include/asm/uncached.h
index e3419f96626a..6f8816b79cf1 100644
--- a/arch/sh/include/asm/uncached.h
+++ b/arch/sh/include/asm/uncached.h
@@ -4,15 +4,55 @@
 #include <linux/bug.h>
 
 #ifdef CONFIG_UNCACHED_MAPPING
+extern unsigned long cached_to_uncached;
+extern unsigned long uncached_size;
 extern unsigned long uncached_start, uncached_end;
 
 extern int virt_addr_uncached(unsigned long kaddr);
 extern void uncached_init(void);
 extern void uncached_resize(unsigned long size);
+
+/*
+ * Jump to uncached area.
+ * When handling TLB or caches, we need to do it from an uncached area.
+ */
+#define jump_to_uncached()                      \
+do {                                            \
+        unsigned long __dummy;                  \
+                                                \
+        __asm__ __volatile__(                   \
+                "mova   1f, %0\n\t"             \
+                "add    %1, %0\n\t"             \
+                "jmp    @%0\n\t"                \
+                " nop\n\t"                      \
+                ".balign 4\n"                   \
+                "1:"                            \
+                : "=&z" (__dummy)               \
+                : "r" (cached_to_uncached));    \
+} while (0)
+
+/*
+ * Back to cached area.
+ */
+#define back_to_cached()                                \
+do {                                                    \
+        unsigned long __dummy;                          \
+        ctrl_barrier();                                 \
+        __asm__ __volatile__(                           \
+                "mov.l  1f, %0\n\t"                     \
+                "jmp    @%0\n\t"                        \
+                " nop\n\t"                              \
+                ".balign 4\n"                           \
+                "1:     .long 2f\n"                     \
+                "2:"                                    \
+                : "=&r" (__dummy));                     \
+} while (0)
 #else
 #define virt_addr_uncached(kaddr)       (0)
 #define uncached_init()                 do { } while (0)
 #define uncached_resize(size)           BUG()
+#define jump_to_uncached()              do { } while (0)
+#define back_to_cached()                do { } while (0)
 #endif
 
 #endif /* __ASM_SH_UNCACHED_H */
diff --git a/arch/sh/include/mach-common/mach/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h
deleted file mode 100644
index efc43b323466..000000000000
--- a/arch/sh/include/mach-common/mach/edosk7705.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_SH_EDOSK7705_H
-#define __ASM_SH_EDOSK7705_H
-
-#define __IO_PREFIX sh_edosk7705
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_EDOSK7705_H */
diff --git a/arch/sh/include/mach-common/mach/microdev.h b/arch/sh/include/mach-common/mach/microdev.h
index 1aed15856e11..dcb05fa8c164 100644
--- a/arch/sh/include/mach-common/mach/microdev.h
+++ b/arch/sh/include/mach-common/mach/microdev.h
@@ -68,13 +68,4 @@ extern void microdev_print_fpga_intc_status(void);
 #define __IO_PREFIX microdev
 #include <asm/io_generic.h>
 
-#if defined(CONFIG_PCI)
-unsigned char  microdev_pci_inb(unsigned long port);
-unsigned short microdev_pci_inw(unsigned long port);
-unsigned long  microdev_pci_inl(unsigned long port);
-void           microdev_pci_outb(unsigned char  data, unsigned long port);
-void           microdev_pci_outw(unsigned short data, unsigned long port);
-void           microdev_pci_outl(unsigned long  data, unsigned long port);
-#endif
-
 #endif /* __ASM_SH_MICRODEV_H */
diff --git a/arch/sh/include/mach-common/mach/snapgear.h b/arch/sh/include/mach-common/mach/secureedge5410.h
index 042d95f51c4d..3653b9a4bacc 100644
--- a/arch/sh/include/mach-common/mach/snapgear.h
+++ b/arch/sh/include/mach-common/mach/secureedge5410.h
@@ -12,30 +12,9 @@
 #ifndef _ASM_SH_IO_SNAPGEAR_H
 #define _ASM_SH_IO_SNAPGEAR_H
 
-#if defined(CONFIG_CPU_SH4)
-/*
- * The external interrupt lines, these take up ints 0 - 15 inclusive
- * depending on the priority for the interrupt.  In fact the priority
- * is the interrupt :-)
- */
-
-#define IRL0_IRQ        2
-#define IRL0_PRIORITY   13
-
-#define IRL1_IRQ        5
-#define IRL1_PRIORITY   10
-
-#define IRL2_IRQ        8
-#define IRL2_PRIORITY   7
-
-#define IRL3_IRQ        11
-#define IRL3_PRIORITY   4
-#endif
-
 #define __IO_PREFIX     snapgear
 #include <asm/io_generic.h>
 
-#ifdef CONFIG_SH_SECUREEDGE5410
 /*
  * We need to remember what was written to the ioport as some bits
  * are shared with other functions and you cannot read back what was
@@ -66,6 +45,5 @@ extern unsigned short secureedge5410_ioport;
                         ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
 #define SECUREEDGE_READ_IOPORT() \
          ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
-#endif
 
 #endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/arch/sh/include/mach-common/mach/systemh7751.h b/arch/sh/include/mach-common/mach/systemh7751.h
deleted file mode 100644
index 4161122c84ef..000000000000
--- a/arch/sh/include/mach-common/mach/systemh7751.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
-#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
-
-/*
- * linux/include/asm-sh/systemh/7751systemh.h
- *
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * Hitachi SystemH support
-
- * Modified for 7751 SystemH by
- * Jonathan Short, 2002.
- */
-
-/* Box specific addresses.  */
-
-#define PA_ROM          0x00000000      /* EPROM */
-#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
-#define PA_FROM         0x01000000      /* EPROM */
-#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
-#define PA_EXT1         0x04000000
-#define PA_EXT1_SIZE    0x04000000
-#define PA_EXT2         0x08000000
-#define PA_EXT2_SIZE    0x04000000
-#define PA_SDRAM        0x0c000000
-#define PA_SDRAM_SIZE   0x04000000
-
-#define PA_EXT4         0x12000000
-#define PA_EXT4_SIZE    0x02000000
-#define PA_EXT5         0x14000000
-#define PA_EXT5_SIZE    0x04000000
-#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
-
-#define PA_DIPSW0       0xb9000000      /* Dip switch 5,6 */
-#define PA_DIPSW1       0xb9000002      /* Dip switch 7,8 */
-#define PA_LED          0xba000000      /* LED */
-#define PA_BCR          0xbb000000      /* FPGA on the MS7751SE01 */
-
-#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
-#define MRSHPC_MODE     (PA_MRSHPC + 4)
-#define MRSHPC_OPTION   (PA_MRSHPC + 6)
-#define MRSHPC_CSR      (PA_MRSHPC + 8)
-#define MRSHPC_ISR      (PA_MRSHPC + 10)
-#define MRSHPC_ICR      (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
-#define MRSHPC_CDCR     (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define BCR_ILCRA       (PA_BCR + 0)
-#define BCR_ILCRB       (PA_BCR + 2)
-#define BCR_ILCRC       (PA_BCR + 4)
-#define BCR_ILCRD       (PA_BCR + 6)
-#define BCR_ILCRE       (PA_BCR + 8)
-#define BCR_ILCRF       (PA_BCR + 10)
-#define BCR_ILCRG       (PA_BCR + 12)
-
-#define IRQ_79C973      13
-
-#define __IO_PREFIX     sh7751systemh
-#include <asm/io_generic.h>
-
-#endif  /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 97661061ff20..fac742e514ee 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -340,6 +340,8 @@ asmlinkage void __cpuinit cpu_init(void)
          */
         current_cpu_data.asid_cache = NO_CONTEXT;
 
+        current_cpu_data.phys_bits = __in_29bit_mode() ? 29 : 32;
+
         speculative_execution_init();
         expmask_init();
 
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index a351ed84eec5..32c825c9488e 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -51,16 +51,20 @@ static inline void set_interrupt_registers(int ip)
                      : "t");
 }
 
-static void mask_imask_irq(unsigned int irq)
+static void mask_imask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
+
         clear_bit(irq, imask_mask);
         if (interrupt_priority < IMASK_PRIORITY - irq)
                 interrupt_priority = IMASK_PRIORITY - irq;
         set_interrupt_registers(interrupt_priority);
 }
 
-static void unmask_imask_irq(unsigned int irq)
+static void unmask_imask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
+
         set_bit(irq, imask_mask);
         interrupt_priority = IMASK_PRIORITY -
                 find_first_zero_bit(imask_mask, IMASK_PRIORITY);
@@ -69,9 +73,9 @@ static void unmask_imask_irq(unsigned int irq)
 
 static struct irq_chip imask_irq_chip = {
         .name           = "SR.IMASK",
-        .mask           = mask_imask_irq,
-        .unmask         = unmask_imask_irq,
-        .mask_ack       = mask_imask_irq,
+        .irq_mask       = mask_imask_irq,
+        .irq_unmask     = unmask_imask_irq,
+        .irq_mask_ack   = mask_imask_irq,
 };
 
 void make_imask_irq(unsigned int irq)
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 96a239583948..5af48f8357e5 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -76,39 +76,11 @@ int intc_evt_to_irq[(0xE20/0x20)+1] = {
 };
 
 static unsigned long intc_virt;
-
-static unsigned int startup_intc_irq(unsigned int irq);
-static void shutdown_intc_irq(unsigned int irq);
-static void enable_intc_irq(unsigned int irq);
-static void disable_intc_irq(unsigned int irq);
-static void mask_and_ack_intc(unsigned int);
-static void end_intc_irq(unsigned int irq);
-
-static struct irq_chip intc_irq_type = {
-        .name = "INTC",
-        .startup = startup_intc_irq,
-        .shutdown = shutdown_intc_irq,
-        .enable = enable_intc_irq,
-        .disable = disable_intc_irq,
-        .ack = mask_and_ack_intc,
-        .end = end_intc_irq
-};
-
 static int irlm;                /* IRL mode */
 
-static unsigned int startup_intc_irq(unsigned int irq)
-{
-        enable_intc_irq(irq);
-        return 0; /* never anything pending */
-}
-
-static void shutdown_intc_irq(unsigned int irq)
-{
-        disable_intc_irq(irq);
-}
-
-static void enable_intc_irq(unsigned int irq)
+static void enable_intc_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long reg;
         unsigned long bitmask;
 
@@ -126,8 +98,9 @@ static void enable_intc_irq(unsigned int irq)
         __raw_writel(bitmask, reg);
 }
 
-static void disable_intc_irq(unsigned int irq)
+static void disable_intc_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long reg;
         unsigned long bitmask;
 
@@ -142,15 +115,11 @@ static void disable_intc_irq(unsigned int irq)
         __raw_writel(bitmask, reg);
 }
 
-static void mask_and_ack_intc(unsigned int irq)
-{
-        disable_intc_irq(irq);
-}
-
-static void end_intc_irq(unsigned int irq)
-{
-        enable_intc_irq(irq);
-}
+static struct irq_chip intc_irq_type = {
+        .name = "INTC",
+        .irq_enable = enable_intc_irq,
+        .irq_disable = disable_intc_irq,
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 9282d965a1b6..7516c35ee514 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -24,25 +24,25 @@
 #include <linux/module.h>
 #include <linux/topology.h>
 
-static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
+static inline struct ipr_desc *get_ipr_desc(struct irq_data *data)
 {
-        struct irq_chip *chip = get_irq_chip(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
         return container_of(chip, struct ipr_desc, chip);
 }
 
-static void disable_ipr_irq(unsigned int irq)
+static void disable_ipr_irq(struct irq_data *data)
 {
-        struct ipr_data *p = get_irq_chip_data(irq);
-        unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
+        struct ipr_data *p = irq_data_get_irq_chip_data(data);
+        unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
         /* Set the priority in IPR to 0 */
         __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
         (void)__raw_readw(addr);        /* Read back to flush write posting */
 }
 
-static void enable_ipr_irq(unsigned int irq)
+static void enable_ipr_irq(struct irq_data *data)
 {
-        struct ipr_data *p = get_irq_chip_data(irq);
-        unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
+        struct ipr_data *p = irq_data_get_irq_chip_data(data);
+        unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
         /* Set priority in IPR back to original value */
         __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
 }
@@ -56,19 +56,18 @@ void register_ipr_controller(struct ipr_desc *desc)
 {
         int i;
 
-        desc->chip.mask = disable_ipr_irq;
-        desc->chip.unmask = enable_ipr_irq;
-        desc->chip.mask_ack = disable_ipr_irq;
+        desc->chip.irq_mask = disable_ipr_irq;
+        desc->chip.irq_unmask = enable_ipr_irq;
 
         for (i = 0; i < desc->nr_irqs; i++) {
                 struct ipr_data *p = desc->ipr_data + i;
-                struct irq_desc *irq_desc;
+                int res;
 
                 BUG_ON(p->ipr_idx >= desc->nr_offsets);
                 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
 
-                irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
-                if (unlikely(!irq_desc)) {
+                res = irq_alloc_desc_at(p->irq, numa_node_id());
+                if (unlikely(res != p->irq && res != -EEXIST)) {
                         printk(KERN_INFO "can not get irq_desc for %d\n",
                                p->irq);
                         continue;
@@ -78,7 +77,7 @@ void register_ipr_controller(struct ipr_desc *desc)
                 set_irq_chip_and_handler_name(p->irq, &desc->chip,
                                       handle_level_irq, "level");
                 set_irq_chip_data(p->irq, p);
-                disable_ipr_irq(p->irq);
+                disable_ipr_irq(irq_get_irq_data(p->irq));
         }
 }
 EXPORT_SYMBOL(register_ipr_controller);
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
index 7f9ecc9c2d02..dbf3b4bb71fe 100644
--- a/arch/sh/kernel/cpu/sh4/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -225,7 +225,7 @@ static void sh7750_pmu_enable_all(void)
 }
 
 static struct sh_pmu sh7750_pmu = {
-        .name           = "SH7750",
+        .name           = "sh7750",
         .num_events     = 2,
         .event_map      = sh7750_event_map,
         .max_events     = ARRAY_SIZE(sh7750_general_events),
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 2d9700c6b53a..0fe2e9329cb2 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -48,7 +48,7 @@ static struct clk r_clk = {
  * Default rate for the root input clock, reset this with clk_set_rate()
  * from the platform code.
  */
-struct clk extal_clk = {
+static struct clk extal_clk = {
         .rate           = 33333333,
 };
 
@@ -111,7 +111,7 @@ static struct clk div3_clk = {
         .parent         = &pll_clk,
 };
 
-struct clk *main_clks[] = {
+static struct clk *main_clks[] = {
         &r_clk,
         &extal_clk,
         &fll_clk,
@@ -156,7 +156,7 @@ struct clk div4_clks[DIV4_NR] = {
 
 enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
 
-struct clk div6_clks[DIV6_NR] = {
+static struct clk div6_clks[DIV6_NR] = {
         [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
         [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
         [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index b8b873d8d6b5..580276525731 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -259,7 +259,7 @@ static void sh4a_pmu_enable_all(void)
 }
 
 static struct sh_pmu sh4a_pmu = {
-        .name           = "SH-4A",
+        .name           = "sh4a",
         .num_events     = 2,
         .event_map      = sh4a_event_map,
         .max_events     = ARRAY_SIZE(sh4a_general_events),
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 9dc447db8a44..68ecbe6c881a 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -56,6 +56,8 @@ int show_interrupts(struct seq_file *p, void *v)
         int i = *(loff_t *)v, j, prec;
         struct irqaction *action;
         struct irq_desc *desc;
+        struct irq_data *data;
+        struct irq_chip *chip;
 
         if (i > nr_irqs)
                 return 0;
@@ -77,6 +79,9 @@ int show_interrupts(struct seq_file *p, void *v)
         if (!desc)
                 return 0;
 
+        data = irq_get_irq_data(i);
+        chip = irq_data_get_irq_chip(data);
+
         raw_spin_lock_irqsave(&desc->lock, flags);
         for_each_online_cpu(j)
                 any_count |= kstat_irqs_cpu(i, j);
@@ -87,7 +92,7 @@ int show_interrupts(struct seq_file *p, void *v)
         seq_printf(p, "%*d: ", prec, i);
         for_each_online_cpu(j)
                 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-        seq_printf(p, " %14s", desc->chip->name);
+        seq_printf(p, " %14s", chip->name);
         seq_printf(p, "-%-8s", desc->name);
 
         if (action) {
@@ -273,12 +278,6 @@ void __init init_IRQ(void)
 {
         plat_irq_setup();
 
-        /*
-         * Pin any of the legacy IRQ vectors that haven't already been
-         * grabbed by the platform
-         */
-        reserve_irq_legacy();
-
         /* Perform the machine specific initialisation */
         if (sh_mv.mv_init_irq)
                 sh_mv.mv_init_irq();
@@ -297,13 +296,16 @@ int __init arch_probe_nr_irqs(void)
 #endif
 
 #ifdef CONFIG_HOTPLUG_CPU
-static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
+static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
 {
+        struct irq_desc *desc = irq_to_desc(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
+
         printk(KERN_INFO "IRQ%u: moving from cpu%u to cpu%u\n",
-               irq, desc->node, cpu);
+               irq, data->node, cpu);
 
         raw_spin_lock_irq(&desc->lock);
-        desc->chip->set_affinity(irq, cpumask_of(cpu));
+        chip->irq_set_affinity(data, cpumask_of(cpu), false);
         raw_spin_unlock_irq(&desc->lock);
 }
 
@@ -314,24 +316,25 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
  */
 void migrate_irqs(void)
 {
-        struct irq_desc *desc;
         unsigned int irq, cpu = smp_processor_id();
 
-        for_each_irq_desc(irq, desc) {
-                if (desc->node == cpu) {
-                        unsigned int newcpu = cpumask_any_and(desc->affinity,
+        for_each_active_irq(irq) {
+                struct irq_data *data = irq_get_irq_data(irq);
+
+                if (data->node == cpu) {
+                        unsigned int newcpu = cpumask_any_and(data->affinity,
                                                               cpu_online_mask);
                         if (newcpu >= nr_cpu_ids) {
                                 if (printk_ratelimit())
                                         printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n",
                                                irq, cpu);
 
-                                cpumask_setall(desc->affinity);
-                                newcpu = cpumask_any_and(desc->affinity,
+                                cpumask_setall(data->affinity);
+                                newcpu = cpumask_any_and(data->affinity,
                                                          cpu_online_mask);
                         }
 
-                        route_irq(desc, irq, newcpu);
+                        route_irq(data, irq, newcpu);
                 }
         }
 }
diff --git a/arch/sh/kernel/irq_64.c b/arch/sh/kernel/irq_64.c
index 32365ba0e039..8fc05b997b6d 100644
--- a/arch/sh/kernel/irq_64.c
+++ b/arch/sh/kernel/irq_64.c
@@ -11,17 +11,17 @@
 #include <linux/module.h>
 #include <cpu/registers.h>
 
-void notrace raw_local_irq_restore(unsigned long flags)
+void notrace arch_local_irq_restore(unsigned long flags)
 {
         unsigned long long __dummy;
 
-        if (flags == RAW_IRQ_DISABLED) {
+        if (flags == ARCH_IRQ_DISABLED) {
                 __asm__ __volatile__ (
                         "getcon " __SR ", %0\n\t"
                         "or     %0, %1, %0\n\t"
                         "putcon %0, " __SR "\n\t"
                         : "=&r" (__dummy)
-                        : "r" (RAW_IRQ_DISABLED)
+                        : "r" (ARCH_IRQ_DISABLED)
                 );
         } else {
                 __asm__ __volatile__ (
@@ -29,13 +29,13 @@ void notrace raw_local_irq_restore(unsigned long flags)
                         "and    %0, %1, %0\n\t"
                         "putcon %0, " __SR "\n\t"
                         : "=&r" (__dummy)
-                        : "r" (~RAW_IRQ_DISABLED)
+                        : "r" (~ARCH_IRQ_DISABLED)
                 );
         }
 }
-EXPORT_SYMBOL(raw_local_irq_restore);
+EXPORT_SYMBOL(arch_local_irq_restore);
 
-unsigned long notrace __raw_local_save_flags(void)
+unsigned long notrace arch_local_save_flags(void)
 {
         unsigned long flags;
 
@@ -43,9 +43,9 @@ unsigned long notrace __raw_local_save_flags(void)
                 "getcon " __SR ", %0\n\t"
                 "and    %0, %1, %0"
                 : "=&r" (flags)
-                : "r" (RAW_IRQ_DISABLED)
+                : "r" (ARCH_IRQ_DISABLED)
         );
 
         return flags;
 }
-EXPORT_SYMBOL(__raw_local_save_flags);
+EXPORT_SYMBOL(arch_local_save_flags);
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 4e278467f76c..d6b018c7ebdc 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -41,6 +41,7 @@
 #include <asm/smp.h>
 #include <asm/mmu_context.h>
 #include <asm/mmzone.h>
+#include <asm/sparsemem.h>
 
 /*
  * Initialize loops_per_jiffy as 10000000 (1000MIPS).
@@ -52,6 +53,7 @@ struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = {
                 .type                   = CPU_SH_NONE,
                 .family                 = CPU_FAMILY_UNKNOWN,
                 .loops_per_jiffy        = 10000000,
+                .phys_bits              = MAX_PHYSMEM_BITS,
         },
 };
 EXPORT_SYMBOL(cpu_data);
@@ -432,6 +434,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         if (c->flags & CPU_HAS_L2_CACHE)
                 show_cacheinfo(m, "scache", c->scache);
 
+        seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
+
         seq_printf(m, "bogomips\t: %lu.%02lu\n",
                      c->loops_per_jiffy/(500000/HZ),
                      (c->loops_per_jiffy/(5000/HZ)) % 100);
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 09370392aff1..c3e61b366493 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -79,7 +79,7 @@ config 29BIT
 
 config 32BIT
         bool
-        default y if CPU_SH5
+        default y if CPU_SH5 || !MMU
 
 config PMB
         bool "Support 32-bit physical addressing through PMB"
diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile
index ab89ea4f9414..150aa326afff 100644
--- a/arch/sh/mm/Makefile
+++ b/arch/sh/mm/Makefile
@@ -15,7 +15,7 @@ cacheops-$(CONFIG_CPU_SHX3)		+= cache-shx3.o
 obj-y                   += $(cacheops-y)
 
 mmu-y                   := nommu.o extable_32.o
-mmu-$(CONFIG_MMU)       := extable_$(BITS).o fault_$(BITS).o \
+mmu-$(CONFIG_MMU)       := extable_$(BITS).o fault_$(BITS).o gup.o \
                            ioremap.o kmap.o pgtable.o tlbflush_$(BITS).o
 
 obj-y                   += $(mmu-y)
diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index 038793286990..40733a952402 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -79,21 +79,20 @@ void dma_generic_free_coherent(struct device *dev, size_t size,
 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                     enum dma_data_direction direction)
 {
-#if defined(CONFIG_CPU_SH5) || defined(CONFIG_PMB)
-        void *p1addr = vaddr;
-#else
-        void *p1addr = (void*) P1SEGADDR((unsigned long)vaddr);
-#endif
+        void *addr;
+
+        addr = __in_29bit_mode() ?
+               (void *)P1SEGADDR((unsigned long)vaddr) : vaddr;
 
         switch (direction) {
         case DMA_FROM_DEVICE:           /* invalidate only */
-                __flush_invalidate_region(p1addr, size);
+                __flush_invalidate_region(addr, size);
                 break;
         case DMA_TO_DEVICE:             /* writeback only */
-                __flush_wback_region(p1addr, size);
+                __flush_wback_region(addr, size);
                 break;
         case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                __flush_purge_region(p1addr, size);
+                __flush_purge_region(addr, size);
                 break;
         default:
                 BUG();
diff --git a/arch/sh/mm/gup.c b/arch/sh/mm/gup.c
new file mode 100644
index 000000000000..bf8daf9d9c9b
--- /dev/null
+++ b/arch/sh/mm/gup.c
@@ -0,0 +1,273 @@
+/*
+ * Lockless get_user_pages_fast for SuperH
+ *
+ * Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * Cloned from the x86 and PowerPC versions, by:
+ *
+ *      Copyright (C) 2008 Nick Piggin
+ *      Copyright (C) 2008 Novell Inc.
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/vmstat.h>
+#include <linux/highmem.h>
+#include <asm/pgtable.h>
+
+static inline pte_t gup_get_pte(pte_t *ptep)
+{
+#ifndef CONFIG_X2TLB
+        return ACCESS_ONCE(*ptep);
+#else
+        /*
+         * With get_user_pages_fast, we walk down the pagetables without
+         * taking any locks.  For this we would like to load the pointers
+         * atomically, but that is not possible with 64-bit PTEs.  What
+         * we do have is the guarantee that a pte will only either go
+         * from not present to present, or present to not present or both
+         * -- it will not switch to a completely different present page
+         * without a TLB flush in between; something that we are blocking
+         * by holding interrupts off.
+         *
+         * Setting ptes from not present to present goes:
+         * ptep->pte_high = h;
+         * smp_wmb();
+         * ptep->pte_low = l;
+         *
+         * And present to not present goes:
+         * ptep->pte_low = 0;
+         * smp_wmb();
+         * ptep->pte_high = 0;
+         *
+         * We must ensure here that the load of pte_low sees l iff pte_high
+         * sees h. We load pte_high *after* loading pte_low, which ensures we
+         * don't see an older value of pte_high.  *Then* we recheck pte_low,
+         * which ensures that we haven't picked up a changed pte high. We might
+         * have got rubbish values from pte_low and pte_high, but we are
+         * guaranteed that pte_low will not have the present bit set *unless*
+         * it is 'l'. And get_user_pages_fast only operates on present ptes, so
+         * we're safe.
+         *
+         * gup_get_pte should not be used or copied outside gup.c without being
+         * very careful -- it does not atomically load the pte or anything that
+         * is likely to be useful for you.
+         */
+        pte_t pte;
+
+retry:
+        pte.pte_low = ptep->pte_low;
+        smp_rmb();
+        pte.pte_high = ptep->pte_high;
+        smp_rmb();
+        if (unlikely(pte.pte_low != ptep->pte_low))
+                goto retry;
+
+        return pte;
+#endif
+}
+
+/*
+ * The performance critical leaf functions are made noinline otherwise gcc
+ * inlines everything into a single function which results in too much
+ * register pressure.
+ */
+static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
+                unsigned long end, int write, struct page **pages, int *nr)
+{
+        u64 mask, result;
+        pte_t *ptep;
+
+#ifdef CONFIG_X2TLB
+        result = _PAGE_PRESENT | _PAGE_EXT(_PAGE_EXT_KERN_READ | _PAGE_EXT_USER_READ);
+        if (write)
+                result |= _PAGE_EXT(_PAGE_EXT_KERN_WRITE | _PAGE_EXT_USER_WRITE);
+#elif defined(CONFIG_SUPERH64)
+        result = _PAGE_PRESENT | _PAGE_USER | _PAGE_READ;
+        if (write)
+                result |= _PAGE_WRITE;
+#else
+        result = _PAGE_PRESENT | _PAGE_USER;
+        if (write)
+                result |= _PAGE_RW;
+#endif
+
+        mask = result | _PAGE_SPECIAL;
+
+        ptep = pte_offset_map(&pmd, addr);
+        do {
+                pte_t pte = gup_get_pte(ptep);
+                struct page *page;
+
+                if ((pte_val(pte) & mask) != result) {
+                        pte_unmap(ptep);
+                        return 0;
+                }
+                VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+                page = pte_page(pte);
+                get_page(page);
+                pages[*nr] = page;
+                (*nr)++;
+
+        } while (ptep++, addr += PAGE_SIZE, addr != end);
+        pte_unmap(ptep - 1);
+
+        return 1;
+}
+
+static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
+                int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pmd_t *pmdp;
+
+        pmdp = pmd_offset(&pud, addr);
+        do {
+                pmd_t pmd = *pmdp;
+
+                next = pmd_addr_end(addr, end);
+                if (pmd_none(pmd))
+                        return 0;
+                if (!gup_pte_range(pmd, addr, next, write, pages, nr))
+                        return 0;
+        } while (pmdp++, addr = next, addr != end);
+
+        return 1;
+}
+
+static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
+                        int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pud_t *pudp;
+
+        pudp = pud_offset(&pgd, addr);
+        do {
+                pud_t pud = *pudp;
+
+                next = pud_addr_end(addr, end);
+                if (pud_none(pud))
+                        return 0;
+                if (!gup_pmd_range(pud, addr, next, write, pages, nr))
+                        return 0;
+        } while (pudp++, addr = next, addr != end);
+
+        return 1;
+}
+
+/*
+ * Like get_user_pages_fast() except its IRQ-safe in that it won't fall
+ * back to the regular GUP.
+ */
+int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
+                          struct page **pages)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr, len, end;
+        unsigned long next;
+        unsigned long flags;
+        pgd_t *pgdp;
+        int nr = 0;
+
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+        end = start + len;
+        if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
+                                        (void __user *)start, len)))
+                return 0;
+
+        /*
+         * This doesn't prevent pagetable teardown, but does prevent
+         * the pagetables and pages from being freed.
+         */
+        local_irq_save(flags);
+        pgdp = pgd_offset(mm, addr);
+        do {
+                pgd_t pgd = *pgdp;
+
+                next = pgd_addr_end(addr, end);
+                if (pgd_none(pgd))
+                        break;
+                if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                        break;
+        } while (pgdp++, addr = next, addr != end);
+        local_irq_restore(flags);
+
+        return nr;
+}
+
+/**
+ * get_user_pages_fast() - pin user pages in memory
+ * @start:      starting user address
+ * @nr_pages:   number of pages from start to pin
+ * @write:      whether pages will be written to
+ * @pages:      array that receives pointers to the pages pinned.
+ *              Should be at least nr_pages long.
+ *
+ * Attempt to pin user pages in memory without taking mm->mmap_sem.
+ * If not successful, it will fall back to taking the lock and
+ * calling get_user_pages().
+ *
+ * Returns number of pages pinned. This may be fewer than the number
+ * requested. If nr_pages is 0 or negative, returns 0. If no pages
+ * were pinned, returns -errno.
+ */
+int get_user_pages_fast(unsigned long start, int nr_pages, int write,
+                        struct page **pages)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr, len, end;
+        unsigned long next;
+        pgd_t *pgdp;
+        int nr = 0;
+
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+
+        end = start + len;
+        if (end < start)
+                goto slow_irqon;
+
+        local_irq_disable();
+        pgdp = pgd_offset(mm, addr);
+        do {
+                pgd_t pgd = *pgdp;
+
+                next = pgd_addr_end(addr, end);
+                if (pgd_none(pgd))
+                        goto slow;
+                if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                        goto slow;
+        } while (pgdp++, addr = next, addr != end);
+        local_irq_enable();
+
+        VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT);
+        return nr;
+
+        {
+                int ret;
+
+slow:
+                local_irq_enable();
+slow_irqon:
+                /* Try to get the remaining pages with get_user_pages */
+                start += nr << PAGE_SHIFT;
+                pages += nr;
+
+                down_read(&mm->mmap_sem);
+                ret = get_user_pages(current, mm, start,
+                        (end - start) >> PAGE_SHIFT, write, 0, pages, NULL);
+                up_read(&mm->mmap_sem);
+
+                /* Have to be a bit careful with return values */
+                if (nr > 0) {
+                        if (ret < 0)
+                                ret = nr;
+                        else
+                                ret += nr;
+                }
+
+                return ret;
+        }
+}
diff --git a/arch/sh/mm/uncached.c b/arch/sh/mm/uncached.c
index 8a4eca551fc0..a7767da815e9 100644
--- a/arch/sh/mm/uncached.c
+++ b/arch/sh/mm/uncached.c
@@ -28,7 +28,7 @@ EXPORT_SYMBOL(virt_addr_uncached);
 
 void __init uncached_init(void)
 {
-#ifdef CONFIG_29BIT
+#if defined(CONFIG_29BIT) || !defined(CONFIG_MMU)
         uncached_start = P2SEG;
 #else
         uncached_start = memory_end;
diff --git a/arch/sh/oprofile/Makefile b/arch/sh/oprofile/Makefile
index e85aae73e3dc..ce3b119021e7 100644
--- a/arch/sh/oprofile/Makefile
+++ b/arch/sh/oprofile/Makefile
@@ -1,5 +1,7 @@
 obj-$(CONFIG_OPROFILE) += oprofile.o
 
+CFLAGS_common.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
+
 DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
                 oprof.o cpu_buffer.o buffer_sync.o \
                 event_buffer.o oprofile_files.o \
diff --git a/arch/sh/oprofile/backtrace.c b/arch/sh/oprofile/backtrace.c
index 2bc74de23f08..37f3a75ea6cb 100644
--- a/arch/sh/oprofile/backtrace.c
+++ b/arch/sh/oprofile/backtrace.c
@@ -91,7 +91,7 @@ void sh_backtrace(struct pt_regs * const regs, unsigned int depth)
         if (depth > backtrace_limit)
                 depth = backtrace_limit;
 
-        stackaddr = (unsigned long *)regs->regs[15];
+        stackaddr = (unsigned long *)kernel_stack_pointer(regs);
         if (!user_mode(regs)) {
                 if (depth)
                         unwind_stack(NULL, regs, stackaddr,
diff --git a/arch/sh/oprofile/common.c b/arch/sh/oprofile/common.c
index e10d89376f9b..b4c2d2b946dd 100644
--- a/arch/sh/oprofile/common.c
+++ b/arch/sh/oprofile/common.c
@@ -1,7 +1,7 @@
 /*
  * arch/sh/oprofile/init.c
  *
- * Copyright (C) 2003 - 2008  Paul Mundt
+ * Copyright (C) 2003 - 2010  Paul Mundt
  *
  * Based on arch/mips/oprofile/common.c:
  *
@@ -18,43 +18,46 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/perf_event.h>
+#include <linux/slab.h>
 #include <asm/processor.h>
 
-#ifdef CONFIG_HW_PERF_EVENTS
 extern void sh_backtrace(struct pt_regs * const regs, unsigned int depth);
 
+#ifdef CONFIG_HW_PERF_EVENTS
+/*
+ * This will need to be reworked when multiple PMUs are supported.
+ */
+static char *sh_pmu_op_name;
+
 char *op_name_from_perf_id(void)
 {
-        const char *pmu;
-        char buf[20];
-        int size;
-
-        pmu = perf_pmu_name();
-        if (!pmu)
-                return NULL;
-
-        size = snprintf(buf, sizeof(buf), "sh/%s", pmu);
-        if (size > -1 && size < sizeof(buf))
-                return buf;
-
-        return NULL;
+        return sh_pmu_op_name;
 }
 
 int __init oprofile_arch_init(struct oprofile_operations *ops)
 {
         ops->backtrace = sh_backtrace;
 
+        if (perf_num_counters() == 0)
+                return -ENODEV;
+
+        sh_pmu_op_name = kasprintf(GFP_KERNEL, "%s/%s",
+                                   UTS_MACHINE, perf_pmu_name());
+        if (unlikely(!sh_pmu_op_name))
+                return -ENOMEM;
+
         return oprofile_perf_init(ops);
 }
 
 void __exit oprofile_arch_exit(void)
 {
         oprofile_perf_exit();
+        kfree(sh_pmu_op_name);
 }
 #else
 int __init oprofile_arch_init(struct oprofile_operations *ops)
 {
-        pr_info("oprofile: hardware counters not available\n");
+        ops->backtrace = sh_backtrace;
         return -ENODEV;
 }
 void __exit oprofile_arch_exit(void) {}
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 9f56eb978024..0e68465e7b50 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -26,7 +26,6 @@ HD64461			HD64461
 7724SE                  SH_7724_SOLUTION_ENGINE
 7751SE                  SH_7751_SOLUTION_ENGINE
 7780SE                  SH_7780_SOLUTION_ENGINE
-7751SYSTEMH             SH_7751_SYSTEMH
 HP6XX                   SH_HP6XX
 DREAMCAST               SH_DREAMCAST
 SNAPGEAR                SH_SECUREEDGE5410
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 8e7bafc5dd0e..45d9c87d083a 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -1,9 +1,3 @@
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux/SPARC Kernel Configuration"
-
 config 64BIT
         bool "64-bit kernel" if ARCH = "sparc"
         default ARCH = "sparc64"
@@ -28,8 +22,6 @@ config SPARC
         select RTC_CLASS
         select RTC_DRV_M48T59
         select HAVE_IRQ_WORK
-        select HAVE_PERF_EVENTS
-        select PERF_USE_VMALLOC
         select HAVE_DMA_ATTRS
         select HAVE_DMA_API_DEBUG
         select HAVE_ARCH_JUMP_LABEL
@@ -56,7 +48,6 @@ config SPARC64
         select RTC_DRV_BQ4802
         select RTC_DRV_SUN4V
         select RTC_DRV_STARFIRE
-        select HAVE_IRQ_WORK
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
 
diff --git a/arch/sparc/include/asm/jump_label.h b/arch/sparc/include/asm/jump_label.h
index d95cf44fb40d..427d4684e0d2 100644
--- a/arch/sparc/include/asm/jump_label.h
+++ b/arch/sparc/include/asm/jump_label.h
@@ -4,7 +4,6 @@
 #ifdef __KERNEL__
 
 #include <linux/types.h>
-#include <asm/system.h>
 
 #define JUMP_LABEL_NOP_SIZE 4
 
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index 0116d8d10def..5ad6e5c5dbb3 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -365,7 +365,7 @@ static int request_fast_irq(unsigned int irq,
         unsigned long flags;
         unsigned int cpu_irq;
         int ret;
-#ifdef CONFIG_SMP
+#if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
         struct tt_entry *trap_table;
         extern struct tt_entry trapbase_cpu1, trapbase_cpu2, trapbase_cpu3;
 #endif
@@ -425,7 +425,7 @@ static int request_fast_irq(unsigned int irq,
         table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP;
 
         INSTANTIATE(sparc_ttable)
-#ifdef CONFIG_SMP
+#if defined CONFIG_SMP && !defined CONFIG_SPARC_LEON
         trap_table = &trapbase_cpu1; INSTANTIATE(trap_table)
         trap_table = &trapbase_cpu2; INSTANTIATE(trap_table)
         trap_table = &trapbase_cpu3; INSTANTIATE(trap_table)
diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c
index e1656fc41ccb..7524689b03d2 100644
--- a/arch/sparc/kernel/leon_smp.c
+++ b/arch/sparc/kernel/leon_smp.c
@@ -56,8 +56,8 @@ void __init leon_configure_cache_smp(void);
 static inline unsigned long do_swap(volatile unsigned long *ptr,
                                     unsigned long val)
 {
-        __asm__ __volatile__("swapa [%1] %2, %0\n\t" : "=&r"(val)
-                             : "r"(ptr), "i"(ASI_LEON_DCACHE_MISS)
+        __asm__ __volatile__("swapa [%2] %3, %0\n\t" : "=&r"(val)
+                             : "0"(val), "r"(ptr), "i"(ASI_LEON_DCACHE_MISS)
                              : "memory");
         return val;
 }
diff --git a/arch/sparc/kernel/rtrap_32.S b/arch/sparc/kernel/rtrap_32.S
index 4da2e1f66290..5f5f74c2c2ca 100644
--- a/arch/sparc/kernel/rtrap_32.S
+++ b/arch/sparc/kernel/rtrap_32.S
@@ -78,9 +78,9 @@ signal_p:
         call    do_notify_resume
          add    %sp, STACKFRAME_SZ, %o0 ! pt_regs ptr
 
-        /* Fall through. */
-        ld      [%sp + STACKFRAME_SZ + PT_PSR], %t_psr
-        clr     %l6
+        b       signal_p
+         ld     [%curptr + TI_FLAGS], %g2
+
 ret_trap_continue:
         sethi   %hi(PSR_SYSCALL), %g1
         andn    %t_psr, %g1, %t_psr
diff --git a/arch/sparc/kernel/rtrap_64.S b/arch/sparc/kernel/rtrap_64.S
index 090b9e9ad5e3..77f1b95e0806 100644
--- a/arch/sparc/kernel/rtrap_64.S
+++ b/arch/sparc/kernel/rtrap_64.S
@@ -34,37 +34,9 @@ __handle_preemption:
 __handle_user_windows:
                 call                    fault_in_user_windows
                  wrpr                   %g0, RTRAP_PSTATE, %pstate
-                wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
-                /* Redo sched+sig checks */
-                ldx                     [%g6 + TI_FLAGS], %l0
-                andcc                   %l0, _TIF_NEED_RESCHED, %g0
-
-                be,pt                   %xcc, 1f
-                 nop
-                call                    schedule
-                 wrpr                   %g0, RTRAP_PSTATE, %pstate
-                wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
-                ldx                     [%g6 + TI_FLAGS], %l0
-
-1:              andcc                   %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
-                be,pt                   %xcc, __handle_user_windows_continue
-                 nop
-                mov                     %l5, %o1
-                add                     %sp, PTREGS_OFF, %o0
-                mov                     %l0, %o2
-
-                call                    do_notify_resume
-                 wrpr                   %g0, RTRAP_PSTATE, %pstate
-                wrpr                    %g0, RTRAP_PSTATE_IRQOFF, %pstate
-                /* Signal delivery can modify pt_regs tstate, so we must
-                 * reload it.
-                 */
-                ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
-                sethi                   %hi(0xf << 20), %l4
-                and                     %l1, %l4, %l4
-                ba,pt                   %xcc, __handle_user_windows_continue
+                ba,pt                   %xcc, __handle_preemption_continue
+                 wrpr                   %g0, RTRAP_PSTATE_IRQOFF, %pstate
 
-                 andn                   %l1, %l4, %l1
 __handle_userfpu:
                 rd                      %fprs, %l5
                 andcc                   %l5, FPRS_FEF, %g0
@@ -87,7 +59,7 @@ __handle_signal:
                 ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
                 sethi                   %hi(0xf << 20), %l4
                 and                     %l1, %l4, %l4
-                ba,pt                   %xcc, __handle_signal_continue
+                ba,pt                   %xcc, __handle_preemption_continue
                  andn                   %l1, %l4, %l1
 
                 /* When returning from a NMI (%pil==15) interrupt we want to
@@ -177,11 +149,9 @@ __handle_preemption_continue:
                 bne,pn                  %xcc, __handle_preemption
                  andcc                  %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
                 bne,pn                  %xcc, __handle_signal
-__handle_signal_continue:
                  ldub                   [%g6 + TI_WSAVED], %o2
                 brnz,pn                 %o2, __handle_user_windows
                  nop
-__handle_user_windows_continue:
                 sethi                   %hi(TSTATE_PEF), %o0
                 andcc                   %l1, %o0, %g0
 
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index bd8601601afa..5b836f5aea90 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -539,6 +539,12 @@ do_sigbus:
         __do_fault_siginfo(BUS_ADRERR, SIGBUS, tsk->thread.kregs, address);
 }
 
+static void check_stack_aligned(unsigned long sp)
+{
+        if (sp & 0x7UL)
+                force_sig(SIGILL, current);
+}
+
 void window_overflow_fault(void)
 {
         unsigned long sp;
@@ -547,6 +553,8 @@ void window_overflow_fault(void)
         if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
                 force_user_fault(sp + 0x38, 1);
         force_user_fault(sp, 1);
+
+        check_stack_aligned(sp);
 }
 
 void window_underflow_fault(unsigned long sp)
@@ -554,6 +562,8 @@ void window_underflow_fault(unsigned long sp)
         if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
                 force_user_fault(sp + 0x38, 0);
         force_user_fault(sp, 0);
+
+        check_stack_aligned(sp);
 }
 
 void window_ret_fault(struct pt_regs *regs)
@@ -564,4 +574,6 @@ void window_ret_fault(struct pt_regs *regs)
         if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
                 force_user_fault(sp + 0x38, 0);
         force_user_fault(sp, 0);
+
+        check_stack_aligned(sp);
 }
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 7e8c2844e093..07ec8a865c1d 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -117,8 +117,6 @@ config TILE
 #       config HUGETLB_PAGE_SIZE_VARIABLE
 
 
-mainmenu "Linux/TILE Kernel Configuration"
-
 # Please note: TILE-Gx support is not yet finalized; this is
 # the preliminary support.  TILE-Gx drivers are only provided
 # with the alpha or beta test versions for Tilera customers.
diff --git a/arch/tile/include/asm/highmem.h b/arch/tile/include/asm/highmem.h
index e0f7ee186721..b2a6c5de79ab 100644
--- a/arch/tile/include/asm/highmem.h
+++ b/arch/tile/include/asm/highmem.h
@@ -23,7 +23,6 @@
 
 #include <linux/interrupt.h>
 #include <linux/threads.h>
-#include <asm/kmap_types.h>
 #include <asm/tlbflush.h>
 #include <asm/homecache.h>
 
diff --git a/arch/tile/include/asm/kmap_types.h b/arch/tile/include/asm/kmap_types.h
index 1480106d1c05..3d0f20246260 100644
--- a/arch/tile/include/asm/kmap_types.h
+++ b/arch/tile/include/asm/kmap_types.h
@@ -16,28 +16,42 @@
 #define _ASM_TILE_KMAP_TYPES_H
 
 /*
- * In TILE Linux each set of four of these uses another 16MB chunk of
- * address space, given 64 tiles and 64KB pages, so we only enable
- * ones that are required by the kernel configuration.
+ * In 32-bit TILE Linux we have to balance the desire to have a lot of
+ * nested atomic mappings with the fact that large page sizes and many
+ * processors chew up address space quickly.  In a typical
+ * 64-processor, 64KB-page layout build, making KM_TYPE_NR one larger
+ * adds 4MB of required address-space.  For now we leave KM_TYPE_NR
+ * set to depth 8.
  */
 enum km_type {
+        KM_TYPE_NR = 8
+};
+
+/*
+ * We provide dummy definitions of all the stray values that used to be
+ * required for kmap_atomic() and no longer are.
+ */
+enum {
         KM_BOUNCE_READ,
         KM_SKB_SUNRPC_DATA,
         KM_SKB_DATA_SOFTIRQ,
         KM_USER0,
         KM_USER1,
         KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
         KM_IRQ0,
         KM_IRQ1,
         KM_SOFTIRQ0,
         KM_SOFTIRQ1,
-        KM_MEMCPY0,
-        KM_MEMCPY1,
-#if defined(CONFIG_HIGHPTE)
-        KM_PTE0,
-        KM_PTE1,
-#endif
-        KM_TYPE_NR
+        KM_SYNC_ICACHE,
+        KM_SYNC_DCACHE,
+        KM_UML_USERCOPY,
+        KM_IRQ_PTE,
+        KM_NMI,
+        KM_NMI_PTE,
+        KM_KDB
 };
 
 #endif /* _ASM_TILE_KMAP_TYPES_H */
diff --git a/arch/tile/include/asm/pgtable.h b/arch/tile/include/asm/pgtable.h
index dc4ccdd855bc..a6604e9485da 100644
--- a/arch/tile/include/asm/pgtable.h
+++ b/arch/tile/include/asm/pgtable.h
@@ -344,10 +344,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 
 #if defined(CONFIG_HIGHPTE)
-extern pte_t *_pte_offset_map(pmd_t *, unsigned long address, enum km_type);
-#define pte_offset_map(dir, address) \
-        _pte_offset_map(dir, address, KM_PTE0)
-#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
+extern pte_t *pte_offset_map(pmd_t *, unsigned long address);
+#define pte_unmap(pte) kunmap_atomic(pte)
 #else
 #define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
 #define pte_unmap(pte) do { } while (0)
diff --git a/arch/tile/include/asm/stat.h b/arch/tile/include/asm/stat.h
index 3dc90fa92c70..b16e5db8f0e7 100644
--- a/arch/tile/include/asm/stat.h
+++ b/arch/tile/include/asm/stat.h
@@ -1 +1,4 @@
+#ifdef CONFIG_COMPAT
+#define __ARCH_WANT_STAT64      /* Used for compat_sys_stat64() etc. */
+#endif
 #include <asm-generic/stat.h>
diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
index f2e3ff485333..b35c2db71199 100644
--- a/arch/tile/include/asm/unistd.h
+++ b/arch/tile/include/asm/unistd.h
@@ -41,6 +41,7 @@ __SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
 #ifdef CONFIG_COMPAT
 #define __ARCH_WANT_SYS_LLSEEK
 #endif
+#define __ARCH_WANT_SYS_NEWFSTATAT
 #endif
 
 #endif /* _ASM_TILE_UNISTD_H */
diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c
index 77739cdd9462..67617a05e602 100644
--- a/arch/tile/kernel/compat.c
+++ b/arch/tile/kernel/compat.c
@@ -148,11 +148,11 @@ long tile_compat_sys_msgrcv(int msqid,
 #define compat_sys_readahead sys32_readahead
 #define compat_sys_sync_file_range compat_sys_sync_file_range2
 
-/* The native 64-bit "struct stat" matches the 32-bit "struct stat64". */
-#define compat_sys_stat64 sys_newstat
-#define compat_sys_lstat64 sys_newlstat
-#define compat_sys_fstat64 sys_newfstat
-#define compat_sys_fstatat64 sys_newfstatat
+/* We leverage the "struct stat64" type for 32-bit time_t/nsec. */
+#define compat_sys_stat64 sys_stat64
+#define compat_sys_lstat64 sys_lstat64
+#define compat_sys_fstat64 sys_fstat64
+#define compat_sys_fstatat64 sys_fstatat64
 
 /* The native sys_ptrace dynamically handles compat binaries. */
 #define compat_sys_ptrace sys_ptrace
diff --git a/arch/tile/kernel/early_printk.c b/arch/tile/kernel/early_printk.c
index 2c54fd43a8a0..493a0e66d916 100644
--- a/arch/tile/kernel/early_printk.c
+++ b/arch/tile/kernel/early_printk.c
@@ -54,7 +54,7 @@ void early_printk(const char *fmt, ...)
 void early_panic(const char *fmt, ...)
 {
         va_list ap;
-        raw_local_irq_disable_all();
+        arch_local_irq_disable_all();
         va_start(ap, fmt);
         early_printk("Kernel panic - not syncing: ");
         early_vprintk(fmt, ap);
diff --git a/arch/tile/kernel/hardwall.c b/arch/tile/kernel/hardwall.c
index 1e54a7843410..e910530436e6 100644
--- a/arch/tile/kernel/hardwall.c
+++ b/arch/tile/kernel/hardwall.c
@@ -151,12 +151,12 @@ enum direction_protect {
 
 static void enable_firewall_interrupts(void)
 {
-        raw_local_irq_unmask_now(INT_UDN_FIREWALL);
+        arch_local_irq_unmask_now(INT_UDN_FIREWALL);
 }
 
 static void disable_firewall_interrupts(void)
 {
-        raw_local_irq_mask_now(INT_UDN_FIREWALL);
+        arch_local_irq_mask_now(INT_UDN_FIREWALL);
 }
 
 /* Set up hardwall on this cpu based on the passed hardwall_info. */
@@ -768,13 +768,13 @@ static int hardwall_release(struct inode *inode, struct file *file)
 }
 
 static const struct file_operations dev_hardwall_fops = {
+        .open           = nonseekable_open,
         .unlocked_ioctl = hardwall_ioctl,
 #ifdef CONFIG_COMPAT
         .compat_ioctl   = hardwall_compat_ioctl,
 #endif
         .flush          = hardwall_flush,
         .release        = hardwall_release,
-        .llseek         = noop_llseek,
 };
 
 static struct cdev hardwall_dev;
diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c
index e63917687e99..128805ef8f2c 100644
--- a/arch/tile/kernel/irq.c
+++ b/arch/tile/kernel/irq.c
@@ -26,7 +26,7 @@
 #define IS_HW_CLEARED 1
 
 /*
- * The set of interrupts we enable for raw_local_irq_enable().
+ * The set of interrupts we enable for arch_local_irq_enable().
  * This is initialized to have just a single interrupt that the kernel
  * doesn't actually use as a sentinel.  During kernel init,
  * interrupts are added as the kernel gets prepared to support them.
@@ -225,7 +225,7 @@ void __cpuinit setup_irq_regs(void)
         /* Enable interrupt delivery. */
         unmask_irqs(~0UL);
 #if CHIP_HAS_IPI()
-        raw_local_irq_unmask(INT_IPI_K);
+        arch_local_irq_unmask(INT_IPI_K);
 #endif
 }
 
diff --git a/arch/tile/kernel/machine_kexec.c b/arch/tile/kernel/machine_kexec.c
index ba7a265d6179..0d8b9e933487 100644
--- a/arch/tile/kernel/machine_kexec.c
+++ b/arch/tile/kernel/machine_kexec.c
@@ -182,13 +182,13 @@ static void kexec_find_and_set_command_line(struct kimage *image)
 
                 if ((entry & IND_SOURCE)) {
                         void *va =
-                                kmap_atomic_pfn(entry >> PAGE_SHIFT, KM_USER0);
+                                kmap_atomic_pfn(entry >> PAGE_SHIFT);
                         r = kexec_bn2cl(va);
                         if (r) {
                                 command_line = r;
                                 break;
                         }
-                        kunmap_atomic(va, KM_USER0);
+                        kunmap_atomic(va);
                 }
         }
 
@@ -198,7 +198,7 @@ static void kexec_find_and_set_command_line(struct kimage *image)
 
                 hverr = hv_set_command_line(
                         (HV_VirtAddr) command_line, strlen(command_line));
-                kunmap_atomic(command_line, KM_USER0);
+                kunmap_atomic(command_line);
         } else {
                 pr_info("%s: no command line found; making empty\n",
                        __func__);
diff --git a/arch/tile/kernel/messaging.c b/arch/tile/kernel/messaging.c
index 997e3933f726..0858ee6b520f 100644
--- a/arch/tile/kernel/messaging.c
+++ b/arch/tile/kernel/messaging.c
@@ -34,7 +34,7 @@ void __cpuinit init_messaging(void)
                 panic("hv_register_message_state: error %d", rc);
 
         /* Make sure downcall interrupts will be enabled. */
-        raw_local_irq_unmask(INT_INTCTRL_K);
+        arch_local_irq_unmask(INT_INTCTRL_K);
 }
 
 void hv_message_intr(struct pt_regs *regs, int intnum)
diff --git a/arch/tile/kernel/ptrace.c b/arch/tile/kernel/ptrace.c
index 9cd29884c09f..e92e40527d6d 100644
--- a/arch/tile/kernel/ptrace.c
+++ b/arch/tile/kernel/ptrace.c
@@ -50,10 +50,10 @@ long arch_ptrace(struct task_struct *child, long request,
 {
         unsigned long __user *datap = (long __user __force *)data;
         unsigned long tmp;
-        int i;
         long ret = -EIO;
-        unsigned long *childregs;
         char *childreg;
+        struct pt_regs copyregs;
+        int ex1_offset;
 
         switch (request) {
 
@@ -80,6 +80,16 @@ long arch_ptrace(struct task_struct *child, long request,
                 if (addr >= PTREGS_SIZE)
                         break;
                 childreg = (char *)task_pt_regs(child) + addr;
+
+                /* Guard against overwrites of the privilege level. */
+                ex1_offset = PTREGS_OFFSET_EX1;
+#if defined(CONFIG_COMPAT) && defined(__BIG_ENDIAN)
+                if (is_compat_task())   /* point at low word */
+                        ex1_offset += sizeof(compat_long_t);
+#endif
+                if (addr == ex1_offset)
+                        data = PL_ICS_EX1(USER_PL, EX1_ICS(data));
+
 #ifdef CONFIG_COMPAT
                 if (is_compat_task()) {
                         if (addr & (sizeof(compat_long_t)-1))
@@ -96,26 +106,19 @@ long arch_ptrace(struct task_struct *child, long request,
                 break;
 
         case PTRACE_GETREGS:  /* Get all registers from the child. */
-                if (!access_ok(VERIFY_WRITE, datap, PTREGS_SIZE))
-                        break;
-                childregs = (long *)task_pt_regs(child);
-                for (i = 0; i < sizeof(struct pt_regs)/sizeof(unsigned long);
-                                ++i) {
-                        ret = __put_user(childregs[i], &datap[i]);
-                        if (ret != 0)
-                                break;
+                if (copy_to_user(datap, task_pt_regs(child),
+                                 sizeof(struct pt_regs)) == 0) {
+                        ret = 0;
                 }
                 break;
 
         case PTRACE_SETREGS:  /* Set all registers in the child. */
-                if (!access_ok(VERIFY_READ, datap, PTREGS_SIZE))
-                        break;
-                childregs = (long *)task_pt_regs(child);
-                for (i = 0; i < sizeof(struct pt_regs)/sizeof(unsigned long);
-                                ++i) {
-                        ret = __get_user(childregs[i], &datap[i]);
-                        if (ret != 0)
-                                break;
+                if (copy_from_user(&copyregs, datap,
+                                   sizeof(struct pt_regs)) == 0) {
+                        copyregs.ex1 =
+                                PL_ICS_EX1(USER_PL, EX1_ICS(copyregs.ex1));
+                        *task_pt_regs(child) = copyregs;
+                        ret = 0;
                 }
                 break;
 
diff --git a/arch/tile/kernel/reboot.c b/arch/tile/kernel/reboot.c
index acd86d20beba..baa3d905fee2 100644
--- a/arch/tile/kernel/reboot.c
+++ b/arch/tile/kernel/reboot.c
@@ -27,7 +27,7 @@
 void machine_halt(void)
 {
         warn_early_printk();
-        raw_local_irq_disable_all();
+        arch_local_irq_disable_all();
         smp_send_stop();
         hv_halt();
 }
@@ -35,14 +35,14 @@ void machine_halt(void)
 void machine_power_off(void)
 {
         warn_early_printk();
-        raw_local_irq_disable_all();
+        arch_local_irq_disable_all();
         smp_send_stop();
         hv_power_off();
 }
 
 void machine_restart(char *cmd)
 {
-        raw_local_irq_disable_all();
+        arch_local_irq_disable_all();
         smp_send_stop();
         hv_restart((HV_VirtAddr) "vmlinux", (HV_VirtAddr) cmd);
 }
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index ae51cad12da0..fb0b3cbeae14 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -868,14 +868,14 @@ void __cpuinit setup_cpu(int boot)
 
         /* Allow asynchronous TLB interrupts. */
 #if CHIP_HAS_TILE_DMA()
-        raw_local_irq_unmask(INT_DMATLB_MISS);
-        raw_local_irq_unmask(INT_DMATLB_ACCESS);
+        arch_local_irq_unmask(INT_DMATLB_MISS);
+        arch_local_irq_unmask(INT_DMATLB_ACCESS);
 #endif
 #if CHIP_HAS_SN_PROC()
-        raw_local_irq_unmask(INT_SNITLB_MISS);
+        arch_local_irq_unmask(INT_SNITLB_MISS);
 #endif
 #ifdef __tilegx__
-        raw_local_irq_unmask(INT_SINGLE_STEP_K);
+        arch_local_irq_unmask(INT_SINGLE_STEP_K);
 #endif
 
         /*
diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c
index fb28e85ae3ae..687719d4abd1 100644
--- a/arch/tile/kernel/signal.c
+++ b/arch/tile/kernel/signal.c
@@ -71,6 +71,9 @@ int restore_sigcontext(struct pt_regs *regs,
         for (i = 0; i < sizeof(struct pt_regs)/sizeof(long); ++i)
                 err |= __get_user(regs->regs[i], &sc->gregs[i]);
 
+        /* Ensure that the PL is always set to USER_PL. */
+        regs->ex1 = PL_ICS_EX1(USER_PL, EX1_ICS(regs->ex1));
+
         regs->faultnum = INT_SWINT_1_SIGRETURN;
 
         err |= __get_user(*pr0, &sc->gregs[0]);
@@ -330,7 +333,7 @@ void do_signal(struct pt_regs *regs)
                         current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
                 }
 
-                return;
+                goto done;
         }
 
         /* Did we come from a system call? */
@@ -358,4 +361,8 @@ void do_signal(struct pt_regs *regs)
                 current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
                 sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
         }
+
+done:
+        /* Avoid double syscall restart if there are nested signals. */
+        regs->faultnum = INT_SWINT_1_SIGRETURN;
 }
diff --git a/arch/tile/kernel/smp.c b/arch/tile/kernel/smp.c
index 75255d90aff3..9575b37a8b75 100644
--- a/arch/tile/kernel/smp.c
+++ b/arch/tile/kernel/smp.c
@@ -115,7 +115,7 @@ static void smp_start_cpu_interrupt(void)
 static void smp_stop_cpu_interrupt(void)
 {
         set_cpu_online(smp_processor_id(), 0);
-        raw_local_irq_disable_all();
+        arch_local_irq_disable_all();
         for (;;)
                 asm("nap");
 }
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
index 6bed820e1421..f2e156e44692 100644
--- a/arch/tile/kernel/time.c
+++ b/arch/tile/kernel/time.c
@@ -132,7 +132,7 @@ static int tile_timer_set_next_event(unsigned long ticks,
 {
         BUG_ON(ticks > MAX_TICK);
         __insn_mtspr(SPR_TILE_TIMER_CONTROL, ticks);
-        raw_local_irq_unmask_now(INT_TILE_TIMER);
+        arch_local_irq_unmask_now(INT_TILE_TIMER);
         return 0;
 }
 
@@ -143,7 +143,7 @@ static int tile_timer_set_next_event(unsigned long ticks,
 static void tile_timer_set_mode(enum clock_event_mode mode,
                                 struct clock_event_device *evt)
 {
-        raw_local_irq_mask_now(INT_TILE_TIMER);
+        arch_local_irq_mask_now(INT_TILE_TIMER);
 }
 
 /*
@@ -172,7 +172,7 @@ void __cpuinit setup_tile_timer(void)
         evt->cpumask = cpumask_of(smp_processor_id());
 
         /* Start out with timer not firing. */
-        raw_local_irq_mask_now(INT_TILE_TIMER);
+        arch_local_irq_mask_now(INT_TILE_TIMER);
 
         /* Register tile timer. */
         clockevents_register_device(evt);
@@ -188,7 +188,7 @@ void do_timer_interrupt(struct pt_regs *regs, int fault_num)
          * Mask the timer interrupt here, since we are a oneshot timer
          * and there are now by definition no events pending.
          */
-        raw_local_irq_mask(INT_TILE_TIMER);
+        arch_local_irq_mask(INT_TILE_TIMER);
 
         /* Track time spent here in an interrupt context */
         irq_enter();
diff --git a/arch/tile/lib/memcpy_tile64.c b/arch/tile/lib/memcpy_tile64.c
index dfedea7b266b..f7d4a6ad61e8 100644
--- a/arch/tile/lib/memcpy_tile64.c
+++ b/arch/tile/lib/memcpy_tile64.c
@@ -54,7 +54,7 @@ typedef unsigned long (*memcpy_t)(void *, const void *, unsigned long);
  * we must run with interrupts disabled to avoid the risk of some
  * other code seeing the incoherent data in our cache.  (Recall that
  * our cache is indexed by PA, so even if the other code doesn't use
- * our KM_MEMCPY virtual addresses, they'll still hit in cache using
+ * our kmap_atomic virtual addresses, they'll still hit in cache using
  * the normal VAs that aren't supposed to hit in cache.)
  */
 static void memcpy_multicache(void *dest, const void *source,
@@ -64,6 +64,7 @@ static void memcpy_multicache(void *dest, const void *source,
         unsigned long flags, newsrc, newdst;
         pmd_t *pmdp;
         pte_t *ptep;
+        int type0, type1;
         int cpu = get_cpu();
 
         /*
@@ -77,7 +78,8 @@ static void memcpy_multicache(void *dest, const void *source,
         sim_allow_multiple_caching(1);
 
         /* Set up the new dest mapping */
-        idx = FIX_KMAP_BEGIN + (KM_TYPE_NR * cpu) + KM_MEMCPY0;
+        type0 = kmap_atomic_idx_push();
+        idx = FIX_KMAP_BEGIN + (KM_TYPE_NR * cpu) + type0;
         newdst = __fix_to_virt(idx) + ((unsigned long)dest & (PAGE_SIZE-1));
         pmdp = pmd_offset(pud_offset(pgd_offset_k(newdst), newdst), newdst);
         ptep = pte_offset_kernel(pmdp, newdst);
@@ -87,7 +89,8 @@ static void memcpy_multicache(void *dest, const void *source,
         }
 
         /* Set up the new source mapping */
-        idx += (KM_MEMCPY0 - KM_MEMCPY1);
+        type1 = kmap_atomic_idx_push();
+        idx += (type0 - type1);
         src_pte = hv_pte_set_nc(src_pte);
         src_pte = hv_pte_clear_writable(src_pte);  /* be paranoid */
         newsrc = __fix_to_virt(idx) + ((unsigned long)source & (PAGE_SIZE-1));
@@ -119,6 +122,8 @@ static void memcpy_multicache(void *dest, const void *source,
          * We're done: notify the simulator that all is back to normal,
          * and re-enable interrupts and pre-emption.
          */
+        kmap_atomic_idx_pop();
+        kmap_atomic_idx_pop();
         sim_allow_multiple_caching(0);
         local_irq_restore(flags);
         put_cpu();
diff --git a/arch/tile/mm/highmem.c b/arch/tile/mm/highmem.c
index abb57331cf6e..31dbbd9afe47 100644
--- a/arch/tile/mm/highmem.c
+++ b/arch/tile/mm/highmem.c
@@ -227,7 +227,7 @@ EXPORT_SYMBOL(kmap_atomic_prot);
 void *__kmap_atomic(struct page *page)
 {
         /* PAGE_NONE is a magic value that tells us to check immutability. */
-        return kmap_atomic_prot(page, type, PAGE_NONE);
+        return kmap_atomic_prot(page, PAGE_NONE);
 }
 EXPORT_SYMBOL(__kmap_atomic);
 
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index 78e1982cb6c9..0b9ce69b0ee5 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -988,8 +988,12 @@ static long __write_once initfree = 1;
 /* Select whether to free (1) or mark unusable (0) the __init pages. */
 static int __init set_initfree(char *str)
 {
-        strict_strtol(str, 0, &initfree);
-        pr_info("initfree: %s free init pages\n", initfree ? "will" : "won't");
+        long val;
+        if (strict_strtol(str, 0, &val)) {
+                initfree = val;
+                pr_info("initfree: %s free init pages\n",
+                        initfree ? "will" : "won't");
+        }
         return 1;
 }
 __setup("initfree=", set_initfree);
diff --git a/arch/tile/mm/pgtable.c b/arch/tile/mm/pgtable.c
index 335c24621c41..1f5430c53d0d 100644
--- a/arch/tile/mm/pgtable.c
+++ b/arch/tile/mm/pgtable.c
@@ -134,9 +134,9 @@ void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t flags)
 }
 
 #if defined(CONFIG_HIGHPTE)
-pte_t *_pte_offset_map(pmd_t *dir, unsigned long address, enum km_type type)
+pte_t *_pte_offset_map(pmd_t *dir, unsigned long address)
 {
-        pte_t *pte = kmap_atomic(pmd_page(*dir), type) +
+        pte_t *pte = kmap_atomic(pmd_page(*dir)) +
                 (pmd_ptfn(*dir) << HV_LOG2_PAGE_TABLE_ALIGN) & ~PAGE_MASK;
         return &pte[pte_index(address)];
 }
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index 7c8e277f6d34..049d048b070d 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -19,8 +19,6 @@ config MMU
 config NO_IOMEM
         def_bool y
 
-mainmenu "Linux/Usermode Kernel Configuration"
-
 config ISA
         bool
 
diff --git a/arch/um/include/asm/ptrace-generic.h b/arch/um/include/asm/ptrace-generic.h
index 2cd899f75a3c..b7c5bab9bd77 100644
--- a/arch/um/include/asm/ptrace-generic.h
+++ b/arch/um/include/asm/ptrace-generic.h
@@ -38,8 +38,8 @@ struct pt_regs {
 
 struct task_struct;
 
-extern long subarch_ptrace(struct task_struct *child, long request, long addr,
-                           long data);
+extern long subarch_ptrace(struct task_struct *child, long request,
+        unsigned long addr, unsigned long data);
 extern unsigned long getreg(struct task_struct *child, int regno);
 extern int putreg(struct task_struct *child, int regno, unsigned long value);
 extern int get_fpregs(struct user_i387_struct __user *buf,
diff --git a/arch/um/kernel/ptrace.c b/arch/um/kernel/ptrace.c
index a5e33f29bbeb..701b672c1122 100644
--- a/arch/um/kernel/ptrace.c
+++ b/arch/um/kernel/ptrace.c
@@ -122,7 +122,7 @@ long arch_ptrace(struct task_struct *child, long request,
                 break;
 
         case PTRACE_SET_THREAD_AREA:
-                ret = ptrace_set_thread_area(child, addr, datavp);
+                ret = ptrace_set_thread_area(child, addr, vp);
                 break;
 
         case PTRACE_FAULTINFO: {
diff --git a/arch/x86/Kbuild b/arch/x86/Kbuild
index ad8ec356fb36..0e103236b754 100644
--- a/arch/x86/Kbuild
+++ b/arch/x86/Kbuild
@@ -14,3 +14,4 @@ obj-y += crypto/
 obj-y += vdso/
 obj-$(CONFIG_IA32_EMULATION) += ia32/
 
+obj-y += platform/
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 299fbc86f570..e8327686d3c5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1,6 +1,3 @@
-# x86 configuration
-mainmenu "Linux Kernel Configuration for x86"
-
 # Select 32 or 64 bit
 config 64BIT
         bool "64-bit kernel" if ARCH = "x86"
@@ -1896,6 +1893,11 @@ config PCI_OLPC
         def_bool y
         depends on PCI && OLPC && (PCI_GOOLPC || PCI_GOANY)
 
+config PCI_XEN
+        def_bool y
+        depends on PCI && XEN
+        select SWIOTLB_XEN
+
 config PCI_DOMAINS
         def_bool y
         depends on PCI
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 92091de11113..55d106b5e31b 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -93,6 +93,9 @@ extern u8 acpi_sci_flags;
 extern int acpi_sci_override_gsi;
 void acpi_pic_sci_set_trigger(unsigned int, u16);
 
+extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
+                                  int trigger, int polarity);
+
 static inline void disable_acpi(void)
 {
         acpi_disabled = 1;
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 286de34b0ed6..f6ce0bda3b98 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -141,13 +141,13 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
 
 static inline u32 native_apic_msr_read(u32 reg)
 {
-        u32 low, high;
+        u64 msr;
 
         if (reg == APIC_DFR)
                 return -1;
 
-        rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
-        return low;
+        rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
+        return (u32)msr;
 }
 
 static inline void native_x2apic_wait_icr_idle(void)
@@ -181,12 +181,12 @@ extern void enable_x2apic(void);
 extern void x2apic_icr_write(u32 low, u32 id);
 static inline int x2apic_enabled(void)
 {
-        int msr, msr2;
+        u64 msr;
 
         if (!cpu_has_x2apic)
                 return 0;
 
-        rdmsr(MSR_IA32_APICBASE, msr, msr2);
+        rdmsrl(MSR_IA32_APICBASE, msr);
         if (msr & X2APIC_ENABLE)
                 return 1;
         return 0;
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index f0203f4791a8..072273082528 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -41,6 +41,8 @@
 #include <asm-generic/int-ll64.h>
 #include <asm/page.h>
 
+#include <xen/xen.h>
+
 #define build_mmio_read(name, size, type, reg, barrier) \
 static inline type name(const volatile void __iomem *addr) \
 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
@@ -351,6 +353,17 @@ extern void early_iounmap(void __iomem *addr, unsigned long size);
 extern void fixup_early_ioremap(void);
 extern bool is_early_ioremap_ptep(pte_t *ptep);
 
+#ifdef CONFIG_XEN
+struct bio_vec;
+
+extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
+                                      const struct bio_vec *vec2);
+
+#define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
+        (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
+         (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
+#endif  /* CONFIG_XEN */
+
 #define IO_SPACE_LIMIT 0xffff
 
 #endif /* _ASM_X86_IO_H */
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index c8be4566c3d2..a6b28d017c2f 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -169,6 +169,7 @@ extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
 extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
 
 extern void probe_nr_irqs_gsi(void);
+extern int get_nr_irqs_gsi(void);
 
 extern void setup_ioapic_ids_from_mpc(void);
 
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 18e3b8a8709f..ef9975812c77 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -824,27 +824,27 @@ static __always_inline void arch_spin_unlock(struct arch_spinlock *lock)
 #define __PV_IS_CALLEE_SAVE(func)                       \
         ((struct paravirt_callee_save) { func })
 
-static inline unsigned long arch_local_save_flags(void)
+static inline notrace unsigned long arch_local_save_flags(void)
 {
         return PVOP_CALLEE0(unsigned long, pv_irq_ops.save_fl);
 }
 
-static inline void arch_local_irq_restore(unsigned long f)
+static inline notrace void arch_local_irq_restore(unsigned long f)
 {
         PVOP_VCALLEE1(pv_irq_ops.restore_fl, f);
 }
 
-static inline void arch_local_irq_disable(void)
+static inline notrace void arch_local_irq_disable(void)
 {
         PVOP_VCALLEE0(pv_irq_ops.irq_disable);
 }
 
-static inline void arch_local_irq_enable(void)
+static inline notrace void arch_local_irq_enable(void)
 {
         PVOP_VCALLEE0(pv_irq_ops.irq_enable);
 }
 
-static inline unsigned long arch_local_irq_save(void)
+static inline notrace unsigned long arch_local_irq_save(void)
 {
         unsigned long f;
 
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index d395540ff894..ca0437c714b2 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -7,6 +7,7 @@
 #include <linux/string.h>
 #include <asm/scatterlist.h>
 #include <asm/io.h>
+#include <asm/x86_init.h>
 
 #ifdef __KERNEL__
 
@@ -94,8 +95,36 @@ static inline void early_quirks(void) { }
 
 extern void pci_iommu_alloc(void);
 
-/* MSI arch hook */
-#define arch_setup_msi_irqs arch_setup_msi_irqs
+#ifdef CONFIG_PCI_MSI
+/* MSI arch specific hooks */
+static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        return x86_msi.setup_msi_irqs(dev, nvec, type);
+}
+
+static inline void x86_teardown_msi_irqs(struct pci_dev *dev)
+{
+        x86_msi.teardown_msi_irqs(dev);
+}
+
+static inline void x86_teardown_msi_irq(unsigned int irq)
+{
+        x86_msi.teardown_msi_irq(irq);
+}
+#define arch_setup_msi_irqs x86_setup_msi_irqs
+#define arch_teardown_msi_irqs x86_teardown_msi_irqs
+#define arch_teardown_msi_irq x86_teardown_msi_irq
+/* implemented in arch/x86/kernel/apic/io_apic. */
+int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
+void native_teardown_msi_irq(unsigned int irq);
+/* default to the implementation in drivers/lib/msi.c */
+#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
+void default_teardown_msi_irqs(struct pci_dev *dev);
+#else
+#define native_setup_msi_irqs           NULL
+#define native_teardown_msi_irq         NULL
+#define default_teardown_msi_irqs       NULL
+#endif
 
 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
 
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index 49c7219826f9..704526734bef 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -47,6 +47,7 @@ enum pci_bf_sort_state {
 extern unsigned int pcibios_max_latency;
 
 void pcibios_resource_survey(void);
+void pcibios_set_cache_line_size(void);
 
 /* pci-pc.c */
 
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index bf6b88ef8eeb..e969f691cbfd 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -5,7 +5,7 @@
  *
  * SGI UV architectural definitions
  *
- * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
  */
 
 #ifndef _ASM_X86_UV_UV_HUB_H
@@ -77,7 +77,8 @@
  *
  *              1111110000000000
  *              5432109876543210
- *              pppppppppplc0cch
+ *              pppppppppplc0cch        Nehalem-EX
+ *              ppppppppplcc0cch        Westmere-EX
  *              sssssssssss
  *
  *                      p  = pnode bits
@@ -148,12 +149,25 @@ struct uv_hub_info_s {
         unsigned char           m_val;
         unsigned char           n_val;
         struct uv_scir_s        scir;
+        unsigned char           apic_pnode_shift;
 };
 
 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 #define uv_hub_info             (&__get_cpu_var(__uv_hub_info))
 #define uv_cpu_hub_info(cpu)    (&per_cpu(__uv_hub_info, cpu))
 
+union uvh_apicid {
+    unsigned long       v;
+    struct uvh_apicid_s {
+        unsigned long   local_apic_mask  : 24;
+        unsigned long   local_apic_shift :  5;
+        unsigned long   unused1          :  3;
+        unsigned long   pnode_mask       : 24;
+        unsigned long   pnode_shift      :  5;
+        unsigned long   unused2          :  3;
+    } s;
+};
+
 /*
  * Local & Global MMR space macros.
  *      Note: macros are intended to be used ONLY by inline functions
@@ -182,6 +196,7 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 #define UV_GLOBAL_MMR64_PNODE_BITS(p)                                   \
         (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
 
+#define UVH_APICID              0x002D0E00L
 #define UV_APIC_PNODE_SHIFT     6
 
 /* Local Bus from cpu's perspective */
@@ -280,7 +295,7 @@ static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
  */
 static inline int uv_apicid_to_pnode(int apicid)
 {
-        return (apicid >> UV_APIC_PNODE_SHIFT);
+        return (apicid >> uv_hub_info->apic_pnode_shift);
 }
 
 /*
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index b2f2d2e05cec..6d90adf4428a 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -806,6 +806,78 @@ union uvh_node_present_table_u {
 };
 
 /* ========================================================================= */
+/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR                  */
+/* ========================================================================= */
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
+
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
+        unsigned long   rsvd_0_23: 24;  /*    */
+        unsigned long   base    :  8;  /* RW */
+        unsigned long   rsvd_32_47: 16;  /*    */
+        unsigned long   m_alias :  5;  /* RW */
+        unsigned long   rsvd_53_62: 10;  /*    */
+        unsigned long   enable  :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR                  */
+/* ========================================================================= */
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
+
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
+        unsigned long   rsvd_0_23: 24;  /*    */
+        unsigned long   base    :  8;  /* RW */
+        unsigned long   rsvd_32_47: 16;  /*    */
+        unsigned long   m_alias :  5;  /* RW */
+        unsigned long   rsvd_53_62: 10;  /*    */
+        unsigned long   enable  :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
+/*                 UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR                  */
+/* ========================================================================= */
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
+
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
+#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
+
+union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
+        unsigned long   rsvd_0_23: 24;  /*    */
+        unsigned long   base    :  8;  /* RW */
+        unsigned long   rsvd_32_47: 16;  /*    */
+        unsigned long   m_alias :  5;  /* RW */
+        unsigned long   rsvd_53_62: 10;  /*    */
+        unsigned long   enable  :  1;  /* RW */
+    } s;
+};
+
+/* ========================================================================= */
 /*                UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR                  */
 /* ========================================================================= */
 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
@@ -857,6 +929,29 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
 };
 
 /* ========================================================================= */
+/*                          UVH_RH_GAM_CONFIG_MMR                            */
+/* ========================================================================= */
+#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
+
+#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
+#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
+#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
+#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
+#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
+#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
+
+union uvh_rh_gam_config_mmr_u {
+    unsigned long       v;
+    struct uvh_rh_gam_config_mmr_s {
+        unsigned long   m_skt     :  6;  /* RW */
+        unsigned long   n_skt     :  4;  /* RW */
+        unsigned long   rsvd_10_11:  2;  /*    */
+        unsigned long   mmiol_cfg :  1;  /* RW */
+        unsigned long   rsvd_13_63: 51;  /*    */
+    } s;
+};
+
+/* ========================================================================= */
 /*                    UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR                      */
 /* ========================================================================= */
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
@@ -987,97 +1082,5 @@ union uvh_rtc1_int_config_u {
     } s;
 };
 
-/* ========================================================================= */
-/*                          UVH_SI_ADDR_MAP_CONFIG                           */
-/* ========================================================================= */
-#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
-
-#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
-#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
-#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
-#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
-
-union uvh_si_addr_map_config_u {
-    unsigned long       v;
-    struct uvh_si_addr_map_config_s {
-        unsigned long   m_skt :  6;  /* RW */
-        unsigned long   rsvd_6_7:  2;  /*    */
-        unsigned long   n_skt :  4;  /* RW */
-        unsigned long   rsvd_12_63: 52;  /*    */
-    } s;
-};
-
-/* ========================================================================= */
-/*                       UVH_SI_ALIAS0_OVERLAY_CONFIG                        */
-/* ========================================================================= */
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
-
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
-#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_si_alias0_overlay_config_u {
-    unsigned long       v;
-    struct uvh_si_alias0_overlay_config_s {
-        unsigned long   rsvd_0_23: 24;  /*    */
-        unsigned long   base    :  8;  /* RW */
-        unsigned long   rsvd_32_47: 16;  /*    */
-        unsigned long   m_alias :  5;  /* RW */
-        unsigned long   rsvd_53_62: 10;  /*    */
-        unsigned long   enable  :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                       UVH_SI_ALIAS1_OVERLAY_CONFIG                        */
-/* ========================================================================= */
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
-
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
-#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_si_alias1_overlay_config_u {
-    unsigned long       v;
-    struct uvh_si_alias1_overlay_config_s {
-        unsigned long   rsvd_0_23: 24;  /*    */
-        unsigned long   base    :  8;  /* RW */
-        unsigned long   rsvd_32_47: 16;  /*    */
-        unsigned long   m_alias :  5;  /* RW */
-        unsigned long   rsvd_53_62: 10;  /*    */
-        unsigned long   enable  :  1;  /* RW */
-    } s;
-};
-
-/* ========================================================================= */
-/*                       UVH_SI_ALIAS2_OVERLAY_CONFIG                        */
-/* ========================================================================= */
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
-
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
-#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
-
-union uvh_si_alias2_overlay_config_u {
-    unsigned long       v;
-    struct uvh_si_alias2_overlay_config_s {
-        unsigned long   rsvd_0_23: 24;  /*    */
-        unsigned long   base    :  8;  /* RW */
-        unsigned long   rsvd_32_47: 16;  /*    */
-        unsigned long   m_alias :  5;  /* RW */
-        unsigned long   rsvd_53_62: 10;  /*    */
-        unsigned long   enable  :  1;  /* RW */
-    } s;
-};
-
 
-#endif /* _ASM_X86_UV_UV_MMRS_H */
+#endif /* __ASM_UV_MMRS_X86_H__ */
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index baa579c8e038..64642ad019fb 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -154,9 +154,18 @@ struct x86_platform_ops {
         int (*i8042_detect)(void);
 };
 
+struct pci_dev;
+
+struct x86_msi_ops {
+        int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
+        void (*teardown_msi_irq)(unsigned int irq);
+        void (*teardown_msi_irqs)(struct pci_dev *dev);
+};
+
 extern struct x86_init_ops x86_init;
 extern struct x86_cpuinit_ops x86_cpuinit;
 extern struct x86_platform_ops x86_platform;
+extern struct x86_msi_ops x86_msi;
 
 extern void x86_init_noop(void);
 extern void x86_init_uint_noop(unsigned int unused);
diff --git a/arch/x86/include/asm/xen/pci.h b/arch/x86/include/asm/xen/pci.h
new file mode 100644
index 000000000000..2329b3eaf8d3
--- /dev/null
+++ b/arch/x86/include/asm/xen/pci.h
@@ -0,0 +1,65 @@
+#ifndef _ASM_X86_XEN_PCI_H
+#define _ASM_X86_XEN_PCI_H
+
+#if defined(CONFIG_PCI_XEN)
+extern int __init pci_xen_init(void);
+extern int __init pci_xen_hvm_init(void);
+#define pci_xen 1
+#else
+#define pci_xen 0
+#define pci_xen_init (0)
+static inline int pci_xen_hvm_init(void)
+{
+        return -1;
+}
+#endif
+#if defined(CONFIG_XEN_DOM0)
+void __init xen_setup_pirqs(void);
+#else
+static inline void __init xen_setup_pirqs(void)
+{
+}
+#endif
+
+#if defined(CONFIG_PCI_MSI)
+#if defined(CONFIG_PCI_XEN)
+/* The drivers/pci/xen-pcifront.c sets this structure to
+ * its own functions.
+ */
+struct xen_pci_frontend_ops {
+        int (*enable_msi)(struct pci_dev *dev, int **vectors);
+        void (*disable_msi)(struct pci_dev *dev);
+        int (*enable_msix)(struct pci_dev *dev, int **vectors, int nvec);
+        void (*disable_msix)(struct pci_dev *dev);
+};
+
+extern struct xen_pci_frontend_ops *xen_pci_frontend;
+
+static inline int xen_pci_frontend_enable_msi(struct pci_dev *dev,
+                                              int **vectors)
+{
+        if (xen_pci_frontend && xen_pci_frontend->enable_msi)
+                return xen_pci_frontend->enable_msi(dev, vectors);
+        return -ENODEV;
+}
+static inline void xen_pci_frontend_disable_msi(struct pci_dev *dev)
+{
+        if (xen_pci_frontend && xen_pci_frontend->disable_msi)
+                        xen_pci_frontend->disable_msi(dev);
+}
+static inline int xen_pci_frontend_enable_msix(struct pci_dev *dev,
+                                               int **vectors, int nvec)
+{
+        if (xen_pci_frontend && xen_pci_frontend->enable_msix)
+                return xen_pci_frontend->enable_msix(dev, vectors, nvec);
+        return -ENODEV;
+}
+static inline void xen_pci_frontend_disable_msix(struct pci_dev *dev)
+{
+        if (xen_pci_frontend && xen_pci_frontend->disable_msix)
+                        xen_pci_frontend->disable_msix(dev);
+}
+#endif /* CONFIG_PCI_XEN */
+#endif /* CONFIG_PCI_MSI */
+
+#endif  /* _ASM_X86_XEN_PCI_H */
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 2c833d8c4141..9e13763b6092 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -36,7 +36,6 @@ obj-y			+= traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o
 obj-y                   += time.o ioport.o ldt.o dumpstack.o
 obj-y                   += setup.o x86_init.o i8259.o irqinit.o jump_label.o
 obj-$(CONFIG_IRQ_WORK)  += irq_work.o
-obj-$(CONFIG_X86_VISWS) += visws_quirks.o
 obj-$(CONFIG_X86_32)    += probe_roms_32.o
 obj-$(CONFIG_X86_32)    += sys_i386_32.o i386_ksyms_32.o
 obj-$(CONFIG_X86_64)    += sys_x86_64.o x8664_ksyms_64.o
@@ -58,7 +57,6 @@ obj-$(CONFIG_INTEL_TXT)		+= tboot.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-y                           += cpu/
 obj-y                           += acpi/
-obj-$(CONFIG_SFI)               += sfi.o
 obj-y                           += reboot.o
 obj-$(CONFIG_MCA)               += mca_32.o
 obj-$(CONFIG_X86_MSR)           += msr.o
@@ -82,7 +80,6 @@ obj-$(CONFIG_KEXEC)		+= relocate_kernel_$(BITS).o crash.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump_$(BITS).o
 obj-$(CONFIG_KPROBES)           += kprobes.o
 obj-$(CONFIG_MODULES)           += module.o
-obj-$(CONFIG_EFI)               += efi.o efi_$(BITS).o efi_stub_$(BITS).o
 obj-$(CONFIG_DOUBLEFAULT)       += doublefault_32.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_VM86)              += vm86_32.o
@@ -104,14 +101,6 @@ obj-$(CONFIG_PARAVIRT_CLOCK)	+= pvclock.o
 
 obj-$(CONFIG_PCSPKR_PLATFORM)   += pcspeaker.o
 
-obj-$(CONFIG_SCx200)            += scx200.o
-scx200-y                        += scx200_32.o
-
-obj-$(CONFIG_OLPC)              += olpc.o
-obj-$(CONFIG_OLPC_XO1)          += olpc-xo1.o
-obj-$(CONFIG_OLPC_OPENFIRMWARE) += olpc_ofw.o
-obj-$(CONFIG_X86_MRST)          += mrst.o
-
 microcode-y                             := microcode_core.o
 microcode-$(CONFIG_MICROCODE_INTEL)     += microcode_intel.o
 microcode-$(CONFIG_MICROCODE_AMD)       += microcode_amd.o
@@ -124,7 +113,6 @@ obj-$(CONFIG_SWIOTLB)			+= pci-swiotlb.o
 ###
 # 64 bit specific files
 ifeq ($(CONFIG_X86_64),y)
-        obj-$(CONFIG_X86_UV)            += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o
         obj-$(CONFIG_AUDIT)             += audit_64.o
 
         obj-$(CONFIG_GART_IOMMU)        += pci-gart_64.o aperture_64.o
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index c05872aa3ce0..71232b941b6c 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -513,35 +513,62 @@ int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi)
         return 0;
 }
 
-/*
- * success: return IRQ number (>=0)
- * failure: return < 0
- */
-int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
+static int acpi_register_gsi_pic(struct device *dev, u32 gsi,
+                                 int trigger, int polarity)
 {
-        unsigned int irq;
-        unsigned int plat_gsi = gsi;
-
 #ifdef CONFIG_PCI
         /*
          * Make sure all (legacy) PCI IRQs are set as level-triggered.
          */
-        if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
-                if (trigger == ACPI_LEVEL_SENSITIVE)
-                        eisa_set_level_irq(gsi);
-        }
+        if (trigger == ACPI_LEVEL_SENSITIVE)
+                eisa_set_level_irq(gsi);
 #endif
 
+        return gsi;
+}
+
+static int acpi_register_gsi_ioapic(struct device *dev, u32 gsi,
+                                    int trigger, int polarity)
+{
 #ifdef CONFIG_X86_IO_APIC
-        if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
-                plat_gsi = mp_register_gsi(dev, gsi, trigger, polarity);
-        }
+        gsi = mp_register_gsi(dev, gsi, trigger, polarity);
 #endif
+
+        return gsi;
+}
+
+int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
+                           int trigger, int polarity) = acpi_register_gsi_pic;
+
+/*
+ * success: return IRQ number (>=0)
+ * failure: return < 0
+ */
+int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
+{
+        unsigned int irq;
+        unsigned int plat_gsi = gsi;
+
+        plat_gsi = (*__acpi_register_gsi)(dev, gsi, trigger, polarity);
         irq = gsi_to_irq(plat_gsi);
 
         return irq;
 }
 
+void __init acpi_set_irq_model_pic(void)
+{
+        acpi_irq_model = ACPI_IRQ_MODEL_PIC;
+        __acpi_register_gsi = acpi_register_gsi_pic;
+        acpi_ioapic = 0;
+}
+
+void __init acpi_set_irq_model_ioapic(void)
+{
+        acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
+        __acpi_register_gsi = acpi_register_gsi_ioapic;
+        acpi_ioapic = 1;
+}
+
 /*
  *  ACPI based hotplug support for CPU
  */
@@ -1259,8 +1286,7 @@ static void __init acpi_process_madt(void)
                          */
                         error = acpi_parse_madt_ioapic_entries();
                         if (!error) {
-                                acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
-                                acpi_ioapic = 1;
+                                acpi_set_irq_model_ioapic();
 
                                 smp_found_config = 1;
                         }
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 0b30214282a8..5079f24c955a 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -638,7 +638,7 @@ void *__kprobes text_poke_smp(void *addr, const void *opcode, size_t len)
         atomic_set(&stop_machine_first, 1);
         wrote_text = 0;
         /* Use __stop_machine() because the caller already got online_cpus. */
-        __stop_machine(stop_machine_text_poke, (void *)&tpp, NULL);
+        __stop_machine(stop_machine_text_poke, (void *)&tpp, cpu_online_mask);
         return addr;
 }
 
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 850657d1b0ed..3f838d537392 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -52,7 +52,6 @@
 #include <asm/mce.h>
 #include <asm/kvm_para.h>
 #include <asm/tsc.h>
-#include <asm/atomic.h>
 
 unsigned int num_processors;
 
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
index cefd6942f0e9..62f6e1e55b90 100644
--- a/arch/x86/kernel/apic/hw_nmi.c
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -17,15 +17,16 @@
 #include <linux/nmi.h>
 #include <linux/module.h>
 
-/* For reliability, we're prepared to waste bits here. */
-static DECLARE_BITMAP(backtrace_mask, NR_CPUS) __read_mostly;
-
 u64 hw_nmi_get_sample_period(void)
 {
         return (u64)(cpu_khz) * 1000 * 60;
 }
 
 #ifdef ARCH_HAS_NMI_WATCHDOG
+
+/* For reliability, we're prepared to waste bits here. */
+static DECLARE_BITMAP(backtrace_mask, NR_CPUS) __read_mostly;
+
 void arch_trigger_all_cpu_backtrace(void)
 {
         int i;
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 8ae808d110f4..7cc0a721f628 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -3109,7 +3109,7 @@ void destroy_irq(unsigned int irq)
 
         irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
 
-        if (intr_remapping_enabled)
+        if (irq_remapped(cfg))
                 free_irte(irq);
         raw_spin_lock_irqsave(&vector_lock, flags);
         __clear_irq_vector(irq, cfg);
@@ -3331,7 +3331,7 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
         return 0;
 }
 
-int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 {
         int node, ret, sub_handle, index = 0;
         unsigned int irq, irq_want;
@@ -3389,7 +3389,7 @@ error:
         return ret;
 }
 
-void arch_teardown_msi_irq(unsigned int irq)
+void native_teardown_msi_irq(unsigned int irq)
 {
         destroy_irq(irq);
 }
@@ -3650,6 +3650,11 @@ void __init probe_nr_irqs_gsi(void)
         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
 }
 
+int get_nr_irqs_gsi(void)
+{
+        return nr_irqs_gsi;
+}
+
 #ifdef CONFIG_SPARSE_IRQ
 int __init arch_probe_nr_irqs(void)
 {
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index f744f54cb248..194539aea175 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -5,7 +5,7 @@
  *
  * SGI UV APIC functions (note: not an Intel compatible APIC)
  *
- * Copyright (C) 2007-2009 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
  */
 #include <linux/cpumask.h>
 #include <linux/hardirq.h>
@@ -41,6 +41,7 @@ DEFINE_PER_CPU(int, x2apic_extra_bits);
 
 static enum uv_system_type uv_system_type;
 static u64 gru_start_paddr, gru_end_paddr;
+static union uvh_apicid uvh_apicid;
 int uv_min_hub_revision_id;
 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
 static DEFINE_SPINLOCK(uv_nmi_lock);
@@ -70,12 +71,27 @@ static int early_get_nodeid(void)
         return node_id.s.node_id;
 }
 
+static void __init early_get_apic_pnode_shift(void)
+{
+        unsigned long *mmr;
+
+        mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_APICID, sizeof(*mmr));
+        uvh_apicid.v = *mmr;
+        early_iounmap(mmr, sizeof(*mmr));
+        if (!uvh_apicid.v)
+                /*
+                 * Old bios, use default value
+                 */
+                uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
+}
+
 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
         int nodeid;
 
         if (!strcmp(oem_id, "SGI")) {
                 nodeid = early_get_nodeid();
+                early_get_apic_pnode_shift();
                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
                 x86_platform.nmi_init = uv_nmi_init;
                 if (!strcmp(oem_table_id, "UVL"))
@@ -84,7 +100,7 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
                         uv_system_type = UV_X2APIC;
                 else if (!strcmp(oem_table_id, "UVH")) {
                         __get_cpu_var(x2apic_extra_bits) =
-                                nodeid << (UV_APIC_PNODE_SHIFT - 1);
+                                nodeid << (uvh_apicid.s.pnode_shift - 1);
                         uv_system_type = UV_NON_UNIQUE_APIC;
                         return 1;
                 }
@@ -363,14 +379,14 @@ struct redir_addr {
 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
 static __initdata struct redir_addr redir_addrs[] = {
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
-        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
+        {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
 };
 
 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 {
-        union uvh_si_alias0_overlay_config_u alias;
+        union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
         int i;
 
@@ -644,7 +660,7 @@ void uv_nmi_init(void)
 
 void __init uv_system_init(void)
 {
-        union uvh_si_addr_map_config_u m_n_config;
+        union uvh_rh_gam_config_mmr_u  m_n_config;
         union uvh_node_id_u node_id;
         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
@@ -654,7 +670,7 @@ void __init uv_system_init(void)
 
         map_low_mmrs();
 
-        m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
+        m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
         m_val = m_n_config.s.m_skt;
         n_val = m_n_config.s.n_skt;
         mmr_base =
@@ -716,6 +732,10 @@ void __init uv_system_init(void)
                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 
                 nid = cpu_to_node(cpu);
+                /*
+                 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
+                 */
+                uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
                 pnode = uv_apicid_to_pnode(apicid);
                 blade = boot_pnode_to_blade(pnode);
                 lcpu = uv_blade_info[blade].nr_possible_cpus;
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 46d58448c3af..e421b8cd6944 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -280,11 +280,11 @@ static struct amd_nb *amd_alloc_nb(int cpu, int nb_id)
         struct amd_nb *nb;
         int i;
 
-        nb = kmalloc(sizeof(struct amd_nb), GFP_KERNEL);
+        nb = kmalloc_node(sizeof(struct amd_nb), GFP_KERNEL | __GFP_ZERO,
+                          cpu_to_node(cpu));
         if (!nb)
                 return NULL;
 
-        memset(nb, 0, sizeof(*nb));
         nb->nb_id = nb_id;
 
         /*
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 64668dbf00a4..96656f207751 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -17,6 +17,7 @@
 #include <linux/delay.h>
 #include <linux/uaccess.h>
 #include <linux/percpu.h>
+#include <linux/mm.h>
 
 #include <asm/apic.h>
 
@@ -125,7 +126,9 @@ void __cpuinit irq_ctx_init(int cpu)
         if (per_cpu(hardirq_ctx, cpu))
                 return;
 
-        irqctx = (union irq_ctx *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER);
+        irqctx = page_address(alloc_pages_node(cpu_to_node(cpu),
+                                               THREAD_FLAGS,
+                                               THREAD_ORDER));
         irqctx->tinfo.task              = NULL;
         irqctx->tinfo.exec_domain       = NULL;
         irqctx->tinfo.cpu               = cpu;
@@ -134,7 +137,9 @@ void __cpuinit irq_ctx_init(int cpu)
 
         per_cpu(hardirq_ctx, cpu) = irqctx;
 
-        irqctx = (union irq_ctx *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER);
+        irqctx = page_address(alloc_pages_node(cpu_to_node(cpu),
+                                               THREAD_FLAGS,
+                                               THREAD_ORDER));
         irqctx->tinfo.task              = NULL;
         irqctx->tinfo.exec_domain       = NULL;
         irqctx->tinfo.cpu               = cpu;
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index d81cfebb848f..ec592caac4b4 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -387,7 +387,7 @@ kgdb_set_hw_break(unsigned long addr, int len, enum kgdb_bptype bptype)
  *      disable hardware debugging while it is processing gdb packets or
  *      handling exception.
  */
-void kgdb_disable_hw_debug(struct pt_regs *regs)
+static void kgdb_disable_hw_debug(struct pt_regs *regs)
 {
         int i;
         int cpu = raw_smp_processor_id();
@@ -724,6 +724,7 @@ struct kgdb_arch arch_kgdb_ops = {
         .flags                  = KGDB_HW_BREAKPOINT,
         .set_hw_breakpoint      = kgdb_set_hw_break,
         .remove_hw_breakpoint   = kgdb_remove_hw_break,
+        .disable_hw_break       = kgdb_disable_hw_debug,
         .remove_all_hw_break    = kgdb_remove_all_hw_break,
         .correct_hw_break       = kgdb_correct_hw_break,
 };
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index e1af7c055c7d..ce0cb4721c9a 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -212,7 +212,7 @@ static int install_equiv_cpu_table(const u8 *buf)
                 return 0;
         }
 
-        equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size);
+        equiv_cpu_table = vmalloc(size);
         if (!equiv_cpu_table) {
                 pr_err("failed to allocate equivalent CPU table\n");
                 return 0;
diff --git a/arch/x86/kernel/mmconf-fam10h_64.c b/arch/x86/kernel/mmconf-fam10h_64.c
index 71825806cd44..6da143c2a6b8 100644
--- a/arch/x86/kernel/mmconf-fam10h_64.c
+++ b/arch/x86/kernel/mmconf-fam10h_64.c
@@ -217,13 +217,13 @@ void __cpuinit fam10h_check_enable_mmcfg(void)
         wrmsrl(address, val);
 }
 
-static int __devinit set_check_enable_amd_mmconf(const struct dmi_system_id *d)
+static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
 {
         pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
         return 0;
 }
 
-static const struct dmi_system_id __cpuinitconst mmconf_dmi_table[] = {
+static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
         {
                 .callback = set_check_enable_amd_mmconf,
                 .ident = "Sun Microsystems Machine",
@@ -234,7 +234,8 @@ static const struct dmi_system_id __cpuinitconst mmconf_dmi_table[] = {
         {}
 };
 
-void __cpuinit check_enable_amd_mmconf_dmi(void)
+/* Called from a __cpuinit function, but only on the BSP. */
+void __ref check_enable_amd_mmconf_dmi(void)
 {
         dmi_check_system(mmconf_dmi_table);
 }
diff --git a/arch/x86/kernel/pvclock.c b/arch/x86/kernel/pvclock.c
index bab3b9e6f66d..008b91eefa18 100644
--- a/arch/x86/kernel/pvclock.c
+++ b/arch/x86/kernel/pvclock.c
@@ -41,44 +41,6 @@ void pvclock_set_flags(u8 flags)
         valid_flags = flags;
 }
 
-/*
- * Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
- * yielding a 64-bit result.
- */
-static inline u64 scale_delta(u64 delta, u32 mul_frac, int shift)
-{
-        u64 product;
-#ifdef __i386__
-        u32 tmp1, tmp2;
-#endif
-
-        if (shift < 0)
-                delta >>= -shift;
-        else
-                delta <<= shift;
-
-#ifdef __i386__
-        __asm__ (
-                "mul  %5       ; "
-                "mov  %4,%%eax ; "
-                "mov  %%edx,%4 ; "
-                "mul  %5       ; "
-                "xor  %5,%5    ; "
-                "add  %4,%%eax ; "
-                "adc  %5,%%edx ; "
-                : "=A" (product), "=r" (tmp1), "=r" (tmp2)
-                : "a" ((u32)delta), "1" ((u32)(delta >> 32)), "2" (mul_frac) );
-#elif defined(__x86_64__)
-        __asm__ (
-                "mul %%rdx ; shrd $32,%%rdx,%%rax"
-                : "=a" (product) : "0" (delta), "d" ((u64)mul_frac) );
-#else
-#error implement me!
-#endif
-
-        return product;
-}
-
 static u64 pvclock_get_nsec_offset(struct pvclock_shadow_time *shadow)
 {
         u64 delta = native_read_tsc() - shadow->tsc_timestamp;
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 95a32746fbf9..21c6746338af 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -769,6 +769,8 @@ void __init setup_arch(char **cmdline_p)
 
         x86_init.oem.arch_setup();
 
+        resource_alloc_from_bottom = 0;
+        iomem_resource.end = (1ULL << boot_cpu_data.x86_phys_bits) - 1;
         setup_memory_map();
         parse_setup_data();
         /* update the e820_saved too */
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index cd6da6bf3eca..ceb2911aa439 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -6,10 +6,12 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/module.h>
+#include <linux/pci.h>
 
 #include <asm/bios_ebda.h>
 #include <asm/paravirt.h>
 #include <asm/pci_x86.h>
+#include <asm/pci.h>
 #include <asm/mpspec.h>
 #include <asm/setup.h>
 #include <asm/apic.h>
@@ -99,3 +101,8 @@ struct x86_platform_ops x86_platform = {
 };
 
 EXPORT_SYMBOL_GPL(x86_platform);
+struct x86_msi_ops x86_msi = {
+        .setup_msi_irqs = native_setup_msi_irqs,
+        .teardown_msi_irq = native_teardown_msi_irq,
+        .teardown_msi_irqs = default_teardown_msi_irqs,
+};
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 908ea5464a51..fb8b376bf28c 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -720,7 +720,7 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
         }
 }
 
-static void set_spte_track_bits(u64 *sptep, u64 new_spte)
+static int set_spte_track_bits(u64 *sptep, u64 new_spte)
 {
         pfn_t pfn;
         u64 old_spte = *sptep;
@@ -731,19 +731,20 @@ static void set_spte_track_bits(u64 *sptep, u64 new_spte)
                 old_spte = __xchg_spte(sptep, new_spte);
 
         if (!is_rmap_spte(old_spte))
-                return;
+                return 0;
 
         pfn = spte_to_pfn(old_spte);
         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
                 kvm_set_pfn_accessed(pfn);
         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
                 kvm_set_pfn_dirty(pfn);
+        return 1;
 }
 
 static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
 {
-        set_spte_track_bits(sptep, new_spte);
-        rmap_remove(kvm, sptep);
+        if (set_spte_track_bits(sptep, new_spte))
+                rmap_remove(kvm, sptep);
 }
 
 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 2288ad829b32..cdac9e592aa5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2560,6 +2560,7 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
                 !kvm_exception_is_soft(vcpu->arch.exception.nr);
         events->exception.nr = vcpu->arch.exception.nr;
         events->exception.has_error_code = vcpu->arch.exception.has_error_code;
+        events->exception.pad = 0;
         events->exception.error_code = vcpu->arch.exception.error_code;
 
         events->interrupt.injected =
@@ -2573,12 +2574,14 @@ static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
         events->nmi.injected = vcpu->arch.nmi_injected;
         events->nmi.pending = vcpu->arch.nmi_pending;
         events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
+        events->nmi.pad = 0;
 
         events->sipi_vector = vcpu->arch.sipi_vector;
 
         events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
                          | KVM_VCPUEVENT_VALID_SIPI_VECTOR
                          | KVM_VCPUEVENT_VALID_SHADOW);
+        memset(&events->reserved, 0, sizeof(events->reserved));
 }
 
 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
@@ -2623,6 +2626,7 @@ static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
         dbgregs->dr6 = vcpu->arch.dr6;
         dbgregs->dr7 = vcpu->arch.dr7;
         dbgregs->flags = 0;
+        memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
 }
 
 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
@@ -3106,6 +3110,7 @@ static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
                 sizeof(ps->channels));
         ps->flags = kvm->arch.vpit->pit_state.flags;
         mutex_unlock(&kvm->arch.vpit->pit_state.lock);
+        memset(&ps->reserved, 0, sizeof(ps->reserved));
         return r;
 }
 
@@ -3169,10 +3174,6 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
                 struct kvm_memslots *slots, *old_slots;
                 unsigned long *dirty_bitmap;
 
-                spin_lock(&kvm->mmu_lock);
-                kvm_mmu_slot_remove_write_access(kvm, log->slot);
-                spin_unlock(&kvm->mmu_lock);
-
                 r = -ENOMEM;
                 dirty_bitmap = vmalloc(n);
                 if (!dirty_bitmap)
@@ -3194,6 +3195,10 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
                 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
                 kfree(old_slots);
 
+                spin_lock(&kvm->mmu_lock);
+                kvm_mmu_slot_remove_write_access(kvm, log->slot);
+                spin_unlock(&kvm->mmu_lock);
+
                 r = -EFAULT;
                 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
                         vfree(dirty_bitmap);
@@ -3486,6 +3491,7 @@ long kvm_arch_vm_ioctl(struct file *filp,
                 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
                 local_irq_enable();
                 user_ns.flags = 0;
+                memset(&user_ns.pad, 0, sizeof(user_ns.pad));
 
                 r = -EFAULT;
                 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
@@ -3972,8 +3978,10 @@ int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
                 return X86EMUL_CONTINUE;
 
         if (kvm_x86_ops->has_wbinvd_exit()) {
+                preempt_disable();
                 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
                                 wbinvd_ipi, NULL, 1);
+                preempt_enable();
                 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
         }
         wbinvd();
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index 60f498511dd6..7ffc9b727efd 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -178,11 +178,8 @@ static void * __init early_node_mem(int nodeid, unsigned long start,
 
         /* extend the search scope */
         end = max_pfn_mapped << PAGE_SHIFT;
-        if (end > (MAX_DMA32_PFN<<PAGE_SHIFT))
-                start = MAX_DMA32_PFN<<PAGE_SHIFT;
-        else
-                start = MAX_DMA_PFN<<PAGE_SHIFT;
-        mem = memblock_x86_find_in_range_node(nodeid, start, end, size, align);
+        start = MAX_DMA_PFN << PAGE_SHIFT;
+        mem = memblock_find_in_range(start, end, size, align);
         if (mem != MEMBLOCK_ERROR)
                 return __va(mem);
 
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 49358481c733..12cdbb17ad18 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -251,7 +251,7 @@ static void __cpuinit calculate_tlb_offset(void)
         }
 }
 
-static int tlb_cpuhp_notify(struct notifier_block *n,
+static int __cpuinit tlb_cpuhp_notify(struct notifier_block *n,
                 unsigned long action, void *hcpu)
 {
         switch (action & 0xf) {
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index a0207a7fdf39..effd96e33f16 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_PCI_BIOS)		+= pcbios.o
 obj-$(CONFIG_PCI_MMCONFIG)      += mmconfig_$(BITS).o direct.o mmconfig-shared.o
 obj-$(CONFIG_PCI_DIRECT)        += direct.o
 obj-$(CONFIG_PCI_OLPC)          += olpc.o
+obj-$(CONFIG_PCI_XEN)           += xen.o
 
 obj-y                           += fixup.o
 obj-$(CONFIG_ACPI)              += acpi.o
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 15466c096ba5..0972315c3860 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -138,7 +138,6 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
         struct acpi_resource_address64 addr;
         acpi_status status;
         unsigned long flags;
-        struct resource *root, *conflict;
         u64 start, end;
 
         status = resource_to_addr(acpi_res, &addr);
@@ -146,12 +145,10 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
                 return AE_OK;
 
         if (addr.resource_type == ACPI_MEMORY_RANGE) {
-                root = &iomem_resource;
                 flags = IORESOURCE_MEM;
                 if (addr.info.mem.caching == ACPI_PREFETCHABLE_MEMORY)
                         flags |= IORESOURCE_PREFETCH;
         } else if (addr.resource_type == ACPI_IO_RANGE) {
-                root = &ioport_resource;
                 flags = IORESOURCE_IO;
         } else
                 return AE_OK;
@@ -172,25 +169,90 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
                 return AE_OK;
         }
 
-        conflict = insert_resource_conflict(root, res);
-        if (conflict) {
-                dev_err(&info->bridge->dev,
-                        "address space collision: host bridge window %pR "
-                        "conflicts with %s %pR\n",
-                        res, conflict->name, conflict);
-        } else {
-                pci_bus_add_resource(info->bus, res, 0);
-                info->res_num++;
-                if (addr.translation_offset)
-                        dev_info(&info->bridge->dev, "host bridge window %pR "
-                                 "(PCI address [%#llx-%#llx])\n",
-                                 res, res->start - addr.translation_offset,
-                                 res->end - addr.translation_offset);
+        info->res_num++;
+        if (addr.translation_offset)
+                dev_info(&info->bridge->dev, "host bridge window %pR "
+                         "(PCI address [%#llx-%#llx])\n",
+                         res, res->start - addr.translation_offset,
+                         res->end - addr.translation_offset);
+        else
+                dev_info(&info->bridge->dev, "host bridge window %pR\n", res);
+
+        return AE_OK;
+}
+
+static bool resource_contains(struct resource *res, resource_size_t point)
+{
+        if (res->start <= point && point <= res->end)
+                return true;
+        return false;
+}
+
+static void coalesce_windows(struct pci_root_info *info, int type)
+{
+        int i, j;
+        struct resource *res1, *res2;
+
+        for (i = 0; i < info->res_num; i++) {
+                res1 = &info->res[i];
+                if (!(res1->flags & type))
+                        continue;
+
+                for (j = i + 1; j < info->res_num; j++) {
+                        res2 = &info->res[j];
+                        if (!(res2->flags & type))
+                                continue;
+
+                        /*
+                         * I don't like throwing away windows because then
+                         * our resources no longer match the ACPI _CRS, but
+                         * the kernel resource tree doesn't allow overlaps.
+                         */
+                        if (resource_contains(res1, res2->start) ||
+                            resource_contains(res1, res2->end) ||
+                            resource_contains(res2, res1->start) ||
+                            resource_contains(res2, res1->end)) {
+                                res1->start = min(res1->start, res2->start);
+                                res1->end = max(res1->end, res2->end);
+                                dev_info(&info->bridge->dev,
+                                         "host bridge window expanded to %pR; %pR ignored\n",
+                                         res1, res2);
+                                res2->flags = 0;
+                        }
+                }
+        }
+}
+
+static void add_resources(struct pci_root_info *info)
+{
+        int i;
+        struct resource *res, *root, *conflict;
+
+        if (!pci_use_crs)
+                return;
+
+        coalesce_windows(info, IORESOURCE_MEM);
+        coalesce_windows(info, IORESOURCE_IO);
+
+        for (i = 0; i < info->res_num; i++) {
+                res = &info->res[i];
+
+                if (res->flags & IORESOURCE_MEM)
+                        root = &iomem_resource;
+                else if (res->flags & IORESOURCE_IO)
+                        root = &ioport_resource;
                 else
-                        dev_info(&info->bridge->dev,
-                                 "host bridge window %pR\n", res);
+                        continue;
+
+                conflict = insert_resource_conflict(root, res);
+                if (conflict)
+                        dev_err(&info->bridge->dev,
+                                "address space collision: host bridge window %pR "
+                                "conflicts with %s %pR\n",
+                                res, conflict->name, conflict);
+                else
+                        pci_bus_add_resource(info->bus, res, 0);
         }
-        return AE_OK;
 }
 
 static void
@@ -224,6 +286,7 @@ get_current_resources(struct acpi_device *device, int busnum,
         acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
                                 &info);
 
+        add_resources(&info);
         return;
 
 name_alloc_fail:
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index a0772af64efb..f7c8a399978c 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -421,16 +421,10 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
 
         return bus;
 }
-
-int __init pcibios_init(void)
+void __init pcibios_set_cache_line_size(void)
 {
         struct cpuinfo_x86 *c = &boot_cpu_data;
 
-        if (!raw_pci_ops) {
-                printk(KERN_WARNING "PCI: System does not support PCI\n");
-                return 0;
-        }
-
         /*
          * Set PCI cacheline size to that of the CPU if the CPU has reported it.
          * (For older CPUs that don't support cpuid, we se it to 32 bytes
@@ -445,7 +439,16 @@ int __init pcibios_init(void)
                 pci_dfl_cache_line_size = 32 >> 2;
                 printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
         }
+}
+
+int __init pcibios_init(void)
+{
+        if (!raw_pci_ops) {
+                printk(KERN_WARNING "PCI: System does not support PCI\n");
+                return 0;
+        }
 
+        pcibios_set_cache_line_size();
         pcibios_resource_survey();
 
         if (pci_bf_sort >= pci_force_bf)
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 55253095be84..c4bb261c106e 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -65,16 +65,21 @@ pcibios_align_resource(void *data, const struct resource *res,
                         resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
-        resource_size_t start = res->start;
+        resource_size_t start = round_down(res->end - size + 1, align);
 
         if (res->flags & IORESOURCE_IO) {
-                if (skip_isa_ioresource_align(dev))
-                        return start;
-                if (start & 0x300)
-                        start = (start + 0x3ff) & ~0x3ff;
+
+                /*
+                 * If we're avoiding ISA aliases, the largest contiguous I/O
+                 * port space is 256 bytes.  Clearing bits 9 and 10 preserves
+                 * all 256-byte and smaller alignments, so the result will
+                 * still be correctly aligned.
+                 */
+                if (!skip_isa_ioresource_align(dev))
+                        start &= ~0x300;
         } else if (res->flags & IORESOURCE_MEM) {
                 if (start < BIOS_END)
-                        start = BIOS_END;
+                        start = res->end;       /* fail; no space */
         }
         return start;
 }
@@ -311,6 +316,8 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                  */
                 prot |= _PAGE_CACHE_UC_MINUS;
 
+        prot |= _PAGE_IOMAP;    /* creating a mapping for IO */
+
         vma->vm_page_prot = __pgprot(prot);
 
         if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index f547ee05f715..9f9bfb705cf9 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -584,27 +584,28 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
         case PCI_DEVICE_ID_INTEL_ICH9_3:
         case PCI_DEVICE_ID_INTEL_ICH9_4:
         case PCI_DEVICE_ID_INTEL_ICH9_5:
-        case PCI_DEVICE_ID_INTEL_TOLAPAI_0:
+        case PCI_DEVICE_ID_INTEL_EP80579_0:
         case PCI_DEVICE_ID_INTEL_ICH10_0:
         case PCI_DEVICE_ID_INTEL_ICH10_1:
         case PCI_DEVICE_ID_INTEL_ICH10_2:
         case PCI_DEVICE_ID_INTEL_ICH10_3:
+        case PCI_DEVICE_ID_INTEL_PATSBURG_LPC:
                 r->name = "PIIX/ICH";
                 r->get = pirq_piix_get;
                 r->set = pirq_piix_set;
                 return 1;
         }
 
-        if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) && 
-                (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) {
+        if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN) && 
+                (device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)) {
                 r->name = "PIIX/ICH";
                 r->get = pirq_piix_get;
                 r->set = pirq_piix_set;
                 return 1;
         }
 
-        if ((device >= PCI_DEVICE_ID_INTEL_CPT_LPC_MIN) && 
-                (device <= PCI_DEVICE_ID_INTEL_CPT_LPC_MAX)) {
+        if ((device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN) && 
+                (device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)) {
                 r->name = "PIIX/ICH";
                 r->get = pirq_piix_get;
                 r->set = pirq_piix_set;
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index a918553ebc75..e282886616a0 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -65,7 +65,6 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
                                                         int end, u64 addr)
 {
         struct pci_mmcfg_region *new;
-        int num_buses;
         struct resource *res;
 
         if (addr == 0)
@@ -82,10 +81,9 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
 
         list_add_sorted(new);
 
-        num_buses = end - start + 1;
         res = &new->res;
         res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
-        res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
+        res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
         res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
         snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
                  "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
new file mode 100644
index 000000000000..d7b5109f7a9c
--- /dev/null
+++ b/arch/x86/pci/xen.c
@@ -0,0 +1,416 @@
+/*
+ * Xen PCI Frontend Stub - puts some "dummy" functions in to the Linux
+ *                         x86 PCI core to support the Xen PCI Frontend
+ *
+ *   Author: Ryan Wilson <hap9@epoch.ncsc.mil>
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/acpi.h>
+
+#include <linux/io.h>
+#include <asm/io_apic.h>
+#include <asm/pci_x86.h>
+
+#include <asm/xen/hypervisor.h>
+
+#include <xen/features.h>
+#include <xen/events.h>
+#include <asm/xen/pci.h>
+
+#ifdef CONFIG_ACPI
+static int xen_hvm_register_pirq(u32 gsi, int triggering)
+{
+        int rc, irq;
+        struct physdev_map_pirq map_irq;
+        int shareable = 0;
+        char *name;
+
+        if (!xen_hvm_domain())
+                return -1;
+
+        map_irq.domid = DOMID_SELF;
+        map_irq.type = MAP_PIRQ_TYPE_GSI;
+        map_irq.index = gsi;
+        map_irq.pirq = -1;
+
+        rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
+        if (rc) {
+                printk(KERN_WARNING "xen map irq failed %d\n", rc);
+                return -1;
+        }
+
+        if (triggering == ACPI_EDGE_SENSITIVE) {
+                shareable = 0;
+                name = "ioapic-edge";
+        } else {
+                shareable = 1;
+                name = "ioapic-level";
+        }
+
+        irq = xen_map_pirq_gsi(map_irq.pirq, gsi, shareable, name);
+
+        printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
+
+        return irq;
+}
+
+static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
+                                 int trigger, int polarity)
+{
+        return xen_hvm_register_pirq(gsi, trigger);
+}
+#endif
+
+#if defined(CONFIG_PCI_MSI)
+#include <linux/msi.h>
+#include <asm/msidef.h>
+
+struct xen_pci_frontend_ops *xen_pci_frontend;
+EXPORT_SYMBOL_GPL(xen_pci_frontend);
+
+static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
+                struct msi_msg *msg)
+{
+        /* We set vector == 0 to tell the hypervisor we don't care about it,
+         * but we want a pirq setup instead.
+         * We use the dest_id field to pass the pirq that we want. */
+        msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq);
+        msg->address_lo =
+                MSI_ADDR_BASE_LO |
+                MSI_ADDR_DEST_MODE_PHYSICAL |
+                MSI_ADDR_REDIRECTION_CPU |
+                MSI_ADDR_DEST_ID(pirq);
+
+        msg->data =
+                MSI_DATA_TRIGGER_EDGE |
+                MSI_DATA_LEVEL_ASSERT |
+                /* delivery mode reserved */
+                (3 << 8) |
+                MSI_DATA_VECTOR(0);
+}
+
+static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        int irq, pirq, ret = 0;
+        struct msi_desc *msidesc;
+        struct msi_msg msg;
+
+        list_for_each_entry(msidesc, &dev->msi_list, list) {
+                xen_allocate_pirq_msi((type == PCI_CAP_ID_MSIX) ?
+                                "msi-x" : "msi", &irq, &pirq);
+                if (irq < 0 || pirq < 0)
+                        goto error;
+                printk(KERN_DEBUG "xen: msi --> irq=%d, pirq=%d\n", irq, pirq);
+                xen_msi_compose_msg(dev, pirq, &msg);
+                ret = set_irq_msi(irq, msidesc);
+                if (ret < 0)
+                        goto error_while;
+                write_msi_msg(irq, &msg);
+        }
+        return 0;
+
+error_while:
+        unbind_from_irqhandler(irq, NULL);
+error:
+        if (ret == -ENODEV)
+                dev_err(&dev->dev, "Xen PCI frontend has not registered" \
+                                " MSI/MSI-X support!\n");
+
+        return ret;
+}
+
+/*
+ * For MSI interrupts we have to use drivers/xen/event.s functions to
+ * allocate an irq_desc and setup the right */
+
+
+static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        int irq, ret, i;
+        struct msi_desc *msidesc;
+        int *v;
+
+        v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
+        if (!v)
+                return -ENOMEM;
+
+        if (type == PCI_CAP_ID_MSIX)
+                ret = xen_pci_frontend_enable_msix(dev, &v, nvec);
+        else
+                ret = xen_pci_frontend_enable_msi(dev, &v);
+        if (ret)
+                goto error;
+        i = 0;
+        list_for_each_entry(msidesc, &dev->msi_list, list) {
+                irq = xen_allocate_pirq(v[i], 0, /* not sharable */
+                        (type == PCI_CAP_ID_MSIX) ?
+                        "pcifront-msi-x" : "pcifront-msi");
+                if (irq < 0) {
+                        ret = -1;
+                        goto free;
+                }
+
+                ret = set_irq_msi(irq, msidesc);
+                if (ret)
+                        goto error_while;
+                i++;
+        }
+        kfree(v);
+        return 0;
+
+error_while:
+        unbind_from_irqhandler(irq, NULL);
+error:
+        if (ret == -ENODEV)
+                dev_err(&dev->dev, "Xen PCI frontend has not registered" \
+                        " MSI/MSI-X support!\n");
+free:
+        kfree(v);
+        return ret;
+}
+
+static void xen_teardown_msi_irqs(struct pci_dev *dev)
+{
+        struct msi_desc *msidesc;
+
+        msidesc = list_entry(dev->msi_list.next, struct msi_desc, list);
+        if (msidesc->msi_attrib.is_msix)
+                xen_pci_frontend_disable_msix(dev);
+        else
+                xen_pci_frontend_disable_msi(dev);
+}
+
+static void xen_teardown_msi_irq(unsigned int irq)
+{
+        xen_destroy_irq(irq);
+}
+
+static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        int irq, ret;
+        struct msi_desc *msidesc;
+
+        list_for_each_entry(msidesc, &dev->msi_list, list) {
+                irq = xen_create_msi_irq(dev, msidesc, type);
+                if (irq < 0)
+                        return -1;
+
+                ret = set_irq_msi(irq, msidesc);
+                if (ret)
+                        goto error;
+        }
+        return 0;
+
+error:
+        xen_destroy_irq(irq);
+        return ret;
+}
+#endif
+
+static int xen_pcifront_enable_irq(struct pci_dev *dev)
+{
+        int rc;
+        int share = 1;
+
+        dev_info(&dev->dev, "Xen PCI enabling IRQ: %d\n", dev->irq);
+
+        if (dev->irq < 0)
+                return -EINVAL;
+
+        if (dev->irq < NR_IRQS_LEGACY)
+                share = 0;
+
+        rc = xen_allocate_pirq(dev->irq, share, "pcifront");
+        if (rc < 0) {
+                dev_warn(&dev->dev, "Xen PCI IRQ: %d, failed to register:%d\n",
+                         dev->irq, rc);
+                return rc;
+        }
+        return 0;
+}
+
+int __init pci_xen_init(void)
+{
+        if (!xen_pv_domain() || xen_initial_domain())
+                return -ENODEV;
+
+        printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
+
+        pcibios_set_cache_line_size();
+
+        pcibios_enable_irq = xen_pcifront_enable_irq;
+        pcibios_disable_irq = NULL;
+
+#ifdef CONFIG_ACPI
+        /* Keep ACPI out of the picture */
+        acpi_noirq = 1;
+#endif
+
+#ifdef CONFIG_PCI_MSI
+        x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
+        x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
+        x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
+#endif
+        return 0;
+}
+
+int __init pci_xen_hvm_init(void)
+{
+        if (!xen_feature(XENFEAT_hvm_pirqs))
+                return 0;
+
+#ifdef CONFIG_ACPI
+        /*
+         * We don't want to change the actual ACPI delivery model,
+         * just how GSIs get registered.
+         */
+        __acpi_register_gsi = acpi_register_gsi_xen_hvm;
+#endif
+
+#ifdef CONFIG_PCI_MSI
+        x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
+        x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
+#endif
+        return 0;
+}
+
+#ifdef CONFIG_XEN_DOM0
+static int xen_register_pirq(u32 gsi, int triggering)
+{
+        int rc, irq;
+        struct physdev_map_pirq map_irq;
+        int shareable = 0;
+        char *name;
+
+        if (!xen_pv_domain())
+                return -1;
+
+        if (triggering == ACPI_EDGE_SENSITIVE) {
+                shareable = 0;
+                name = "ioapic-edge";
+        } else {
+                shareable = 1;
+                name = "ioapic-level";
+        }
+
+        irq = xen_allocate_pirq(gsi, shareable, name);
+
+        printk(KERN_DEBUG "xen: --> irq=%d\n", irq);
+
+        if (irq < 0)
+                goto out;
+
+        map_irq.domid = DOMID_SELF;
+        map_irq.type = MAP_PIRQ_TYPE_GSI;
+        map_irq.index = gsi;
+        map_irq.pirq = irq;
+
+        rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
+        if (rc) {
+                printk(KERN_WARNING "xen map irq failed %d\n", rc);
+                return -1;
+        }
+
+out:
+        return irq;
+}
+
+static int xen_register_gsi(u32 gsi, int triggering, int polarity)
+{
+        int rc, irq;
+        struct physdev_setup_gsi setup_gsi;
+
+        if (!xen_pv_domain())
+                return -1;
+
+        printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
+                        gsi, triggering, polarity);
+
+        irq = xen_register_pirq(gsi, triggering);
+
+        setup_gsi.gsi = gsi;
+        setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
+        setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
+
+        rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
+        if (rc == -EEXIST)
+                printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
+        else if (rc) {
+                printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
+                                gsi, rc);
+        }
+
+        return irq;
+}
+
+static __init void xen_setup_acpi_sci(void)
+{
+        int rc;
+        int trigger, polarity;
+        int gsi = acpi_sci_override_gsi;
+
+        if (!gsi)
+                return;
+
+        rc = acpi_get_override_irq(gsi, &trigger, &polarity);
+        if (rc) {
+                printk(KERN_WARNING "xen: acpi_get_override_irq failed for acpi"
+                                " sci, rc=%d\n", rc);
+                return;
+        }
+        trigger = trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
+        polarity = polarity ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
+        
+        printk(KERN_INFO "xen: sci override: global_irq=%d trigger=%d "
+                        "polarity=%d\n", gsi, trigger, polarity);
+
+        gsi = xen_register_gsi(gsi, trigger, polarity);
+        printk(KERN_INFO "xen: acpi sci %d\n", gsi);
+
+        return;
+}
+
+static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
+                                 int trigger, int polarity)
+{
+        return xen_register_gsi(gsi, trigger, polarity);
+}
+
+static int __init pci_xen_initial_domain(void)
+{
+#ifdef CONFIG_PCI_MSI
+        x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
+        x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
+#endif
+        xen_setup_acpi_sci();
+        __acpi_register_gsi = acpi_register_gsi_xen;
+
+        return 0;
+}
+
+void __init xen_setup_pirqs(void)
+{
+        int irq;
+
+        pci_xen_initial_domain();
+
+        if (0 == nr_ioapics) {
+                for (irq = 0; irq < NR_IRQS_LEGACY; irq++)
+                        xen_allocate_pirq(irq, 0, "xt-pic");
+                return;
+        }
+
+        /* Pre-allocate legacy irqs */
+        for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
+                int trigger, polarity;
+
+                if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
+                        continue;
+
+                xen_register_pirq(irq,
+                        trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE);
+        }
+}
+#endif
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
new file mode 100644
index 000000000000..7bf70b812fa2
--- /dev/null
+++ b/arch/x86/platform/Makefile
@@ -0,0 +1,8 @@
+# Platform specific code goes here
+obj-y   += efi/
+obj-y   += mrst/
+obj-y   += olpc/
+obj-y   += scx200/
+obj-y   += sfi/
+obj-y   += visws/
+obj-y   += uv/
diff --git a/arch/x86/platform/efi/Makefile b/arch/x86/platform/efi/Makefile
new file mode 100644
index 000000000000..73b8be0f3675
--- /dev/null
+++ b/arch/x86/platform/efi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_EFI)               += efi.o efi_$(BITS).o efi_stub_$(BITS).o
diff --git a/arch/x86/kernel/efi.c b/arch/x86/platform/efi/efi.c
index 0fe27d7c6258..0fe27d7c6258 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/platform/efi/efi.c
diff --git a/arch/x86/kernel/efi_32.c b/arch/x86/platform/efi/efi_32.c
index 5cab48ee61a4..5cab48ee61a4 100644
--- a/arch/x86/kernel/efi_32.c
+++ b/arch/x86/platform/efi/efi_32.c
diff --git a/arch/x86/kernel/efi_64.c b/arch/x86/platform/efi/efi_64.c
index ac0621a7ac3d..ac0621a7ac3d 100644
--- a/arch/x86/kernel/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
diff --git a/arch/x86/kernel/efi_stub_32.S b/arch/x86/platform/efi/efi_stub_32.S
index fbe66e626c09..fbe66e626c09 100644
--- a/arch/x86/kernel/efi_stub_32.S
+++ b/arch/x86/platform/efi/efi_stub_32.S
diff --git a/arch/x86/kernel/efi_stub_64.S b/arch/x86/platform/efi/efi_stub_64.S
index 4c07ccab8146..4c07ccab8146 100644
--- a/arch/x86/kernel/efi_stub_64.S
+++ b/arch/x86/platform/efi/efi_stub_64.S
diff --git a/arch/x86/platform/mrst/Makefile b/arch/x86/platform/mrst/Makefile
new file mode 100644
index 000000000000..efbbc552fa95
--- /dev/null
+++ b/arch/x86/platform/mrst/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_X86_MRST)          += mrst.o
diff --git a/arch/x86/kernel/mrst.c b/arch/x86/platform/mrst/mrst.c
index 79ae68154e87..79ae68154e87 100644
--- a/arch/x86/kernel/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
diff --git a/arch/x86/platform/olpc/Makefile b/arch/x86/platform/olpc/Makefile
new file mode 100644
index 000000000000..c31b8fcb5a86
--- /dev/null
+++ b/arch/x86/platform/olpc/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_OLPC)              += olpc.o
+obj-$(CONFIG_OLPC_XO1)          += olpc-xo1.o
+obj-$(CONFIG_OLPC_OPENFIRMWARE) += olpc_ofw.o
diff --git a/arch/x86/kernel/olpc-xo1.c b/arch/x86/platform/olpc/olpc-xo1.c
index f5442c03abc3..f5442c03abc3 100644
--- a/arch/x86/kernel/olpc-xo1.c
+++ b/arch/x86/platform/olpc/olpc-xo1.c
diff --git a/arch/x86/kernel/olpc.c b/arch/x86/platform/olpc/olpc.c
index edaf3fe8dc5e..edaf3fe8dc5e 100644
--- a/arch/x86/kernel/olpc.c
+++ b/arch/x86/platform/olpc/olpc.c
diff --git a/arch/x86/kernel/olpc_ofw.c b/arch/x86/platform/olpc/olpc_ofw.c
index 787320464379..787320464379 100644
--- a/arch/x86/kernel/olpc_ofw.c
+++ b/arch/x86/platform/olpc/olpc_ofw.c
diff --git a/arch/x86/platform/scx200/Makefile b/arch/x86/platform/scx200/Makefile
new file mode 100644
index 000000000000..762b4c7f4314
--- /dev/null
+++ b/arch/x86/platform/scx200/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_SCx200)            += scx200.o
+scx200-y                        += scx200_32.o
diff --git a/arch/x86/kernel/scx200_32.c b/arch/x86/platform/scx200/scx200_32.c
index 7e004acbe526..7e004acbe526 100644
--- a/arch/x86/kernel/scx200_32.c
+++ b/arch/x86/platform/scx200/scx200_32.c
diff --git a/arch/x86/platform/sfi/Makefile b/arch/x86/platform/sfi/Makefile
new file mode 100644
index 000000000000..cc5db1168a5e
--- /dev/null
+++ b/arch/x86/platform/sfi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SFI)               += sfi.o
diff --git a/arch/x86/kernel/sfi.c b/arch/x86/platform/sfi/sfi.c
index dd4c281ffe57..dd4c281ffe57 100644
--- a/arch/x86/kernel/sfi.c
+++ b/arch/x86/platform/sfi/sfi.c
diff --git a/arch/x86/platform/uv/Makefile b/arch/x86/platform/uv/Makefile
new file mode 100644
index 000000000000..6c40995fefb8
--- /dev/null
+++ b/arch/x86/platform/uv/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_X86_UV)            += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o
diff --git a/arch/x86/kernel/bios_uv.c b/arch/x86/platform/uv/bios_uv.c
index 8bc57baaa9ad..8bc57baaa9ad 100644
--- a/arch/x86/kernel/bios_uv.c
+++ b/arch/x86/platform/uv/bios_uv.c
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 20ea20a39e2a..a318194002b5 100644
--- a/arch/x86/kernel/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -1343,8 +1343,8 @@ uv_activation_descriptor_init(int node, int pnode)
          * each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR)
          * per cpu; and up to 32 (UV_ADP_SIZE) cpu's per uvhub
          */
-        bau_desc = (struct bau_desc *)kmalloc_node(sizeof(struct bau_desc)*
-                UV_ADP_SIZE*UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
+        bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE
+                                * UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
         BUG_ON(!bau_desc);
 
         pa = uv_gpa(bau_desc); /* need the real nasid*/
@@ -1402,9 +1402,9 @@ uv_payload_queue_init(int node, int pnode)
         struct bau_payload_queue_entry *pqp_malloc;
         struct bau_control *bcp;
 
-        pqp = (struct bau_payload_queue_entry *) kmalloc_node(
-                (DEST_Q_SIZE + 1) * sizeof(struct bau_payload_queue_entry),
-                GFP_KERNEL, node);
+        pqp = kmalloc_node((DEST_Q_SIZE + 1)
+                           * sizeof(struct bau_payload_queue_entry),
+                           GFP_KERNEL, node);
         BUG_ON(!pqp);
         pqp_malloc = pqp;
 
@@ -1520,8 +1520,7 @@ static void __init uv_init_per_cpu(int nuvhubs)
 
         timeout_us = calculate_destination_timeout();
 
-        uvhub_descs = (struct uvhub_desc *)
-                kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
+        uvhub_descs = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
         memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
         uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
         for_each_present_cpu(cpu) {
diff --git a/arch/x86/kernel/uv_irq.c b/arch/x86/platform/uv/uv_irq.c
index 7b24460917d5..7b24460917d5 100644
--- a/arch/x86/kernel/uv_irq.c
+++ b/arch/x86/platform/uv/uv_irq.c
diff --git a/arch/x86/kernel/uv_sysfs.c b/arch/x86/platform/uv/uv_sysfs.c
index 309c70fb7759..309c70fb7759 100644
--- a/arch/x86/kernel/uv_sysfs.c
+++ b/arch/x86/platform/uv/uv_sysfs.c
diff --git a/arch/x86/kernel/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 56e421bc379b..56e421bc379b 100644
--- a/arch/x86/kernel/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
diff --git a/arch/x86/platform/visws/Makefile b/arch/x86/platform/visws/Makefile
new file mode 100644
index 000000000000..91bc17ab2fd5
--- /dev/null
+++ b/arch/x86/platform/visws/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_X86_VISWS) += visws_quirks.o
diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c
index 3371bd053b89..3371bd053b89 100644
--- a/arch/x86/kernel/visws_quirks.c
+++ b/arch/x86/platform/visws/visws_quirks.c
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 90a7f5ad6916..5b54892e4bc3 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -13,6 +13,16 @@ config XEN
           kernel to boot in a paravirtualized environment under the
           Xen hypervisor.
 
+config XEN_DOM0
+        def_bool y
+        depends on XEN && PCI_XEN && SWIOTLB_XEN
+        depends on X86_LOCAL_APIC && X86_IO_APIC && ACPI && PCI
+
+# Dummy symbol since people have come to rely on the PRIVILEGED_GUEST
+# name in tools.
+config XEN_PRIVILEGED_GUEST
+        def_bool XEN_DOM0
+
 config XEN_PVHVM
         def_bool y
         depends on XEN
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 70ddeaeb1ef3..235c0f4d3861 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -46,6 +46,7 @@
 #include <asm/paravirt.h>
 #include <asm/apic.h>
 #include <asm/page.h>
+#include <asm/xen/pci.h>
 #include <asm/xen/hypercall.h>
 #include <asm/xen/hypervisor.h>
 #include <asm/fixmap.h>
@@ -236,6 +237,7 @@ static __init void xen_init_cpuid_mask(void)
         cpuid_leaf1_edx_mask =
                 ~((1 << X86_FEATURE_MCE)  |  /* disable MCE */
                   (1 << X86_FEATURE_MCA)  |  /* disable MCA */
+                  (1 << X86_FEATURE_MTRR) |  /* disable MTRR */
                   (1 << X86_FEATURE_ACC));   /* thermal monitoring */
 
         if (!xen_initial_domain())
@@ -1184,6 +1186,7 @@ asmlinkage void __init xen_start_kernel(void)
 
         xen_raw_console_write("mapping kernel into physical memory\n");
         pgd = xen_setup_kernel_pagetable(pgd, xen_start_info->nr_pages);
+        xen_ident_map_ISA();
 
         /* Allocate and initialize top and mid mfn levels for p2m structure */
         xen_build_mfn_list_list();
@@ -1222,6 +1225,8 @@ asmlinkage void __init xen_start_kernel(void)
                 add_preferred_console("xenboot", 0, NULL);
                 add_preferred_console("tty", 0, NULL);
                 add_preferred_console("hvc", 0, NULL);
+                if (pci_xen)
+                        x86_init.pci.arch_init = pci_xen_init;
         } else {
                 /* Make sure ACS will be enabled */
                 pci_request_acs();
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 9631c90907eb..21ed8d7f75a5 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -1975,6 +1975,7 @@ static void *m2v(phys_addr_t maddr)
         return __ka(m2p(maddr));
 }
 
+/* Set the page permissions on an identity-mapped pages */
 static void set_page_prot(void *addr, pgprot_t prot)
 {
         unsigned long pfn = __pa(addr) >> PAGE_SHIFT;
@@ -2125,7 +2126,7 @@ __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd,
 {
         pmd_t *kernel_pmd;
 
-        level2_kernel_pgt = extend_brk(sizeof(pmd_t *) * PTRS_PER_PMD, PAGE_SIZE);
+        level2_kernel_pgt = extend_brk(sizeof(pmd_t) * PTRS_PER_PMD, PAGE_SIZE);
 
         max_pfn_mapped = PFN_DOWN(__pa(xen_start_info->pt_base) +
                                   xen_start_info->nr_pt_frames * PAGE_SIZE +
@@ -2159,6 +2160,8 @@ __init pgd_t *xen_setup_kernel_pagetable(pgd_t *pgd,
 }
 #endif  /* CONFIG_X86_64 */
 
+static unsigned char dummy_mapping[PAGE_SIZE] __page_aligned_bss;
+
 static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
 {
         pte_t pte;
@@ -2179,15 +2182,28 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
 #else
         case VSYSCALL_LAST_PAGE ... VSYSCALL_FIRST_PAGE:
 #endif
-#ifdef CONFIG_X86_LOCAL_APIC
-        case FIX_APIC_BASE:     /* maps dummy local APIC */
-#endif
         case FIX_TEXT_POKE0:
         case FIX_TEXT_POKE1:
                 /* All local page mappings */
                 pte = pfn_pte(phys, prot);
                 break;
 
+#ifdef CONFIG_X86_LOCAL_APIC
+        case FIX_APIC_BASE:     /* maps dummy local APIC */
+                pte = pfn_pte(PFN_DOWN(__pa(dummy_mapping)), PAGE_KERNEL);
+                break;
+#endif
+
+#ifdef CONFIG_X86_IO_APIC
+        case FIX_IO_APIC_BASE_0 ... FIX_IO_APIC_BASE_END:
+                /*
+                 * We just don't map the IO APIC - all access is via
+                 * hypercalls.  Keep the address in the pte for reference.
+                 */
+                pte = pfn_pte(PFN_DOWN(__pa(dummy_mapping)), PAGE_KERNEL);
+                break;
+#endif
+
         case FIX_PARAVIRT_BOOTMAP:
                 /* This is an MFN, but it isn't an IO mapping from the
                    IO domain */
@@ -2212,6 +2228,29 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
 #endif
 }
 
+__init void xen_ident_map_ISA(void)
+{
+        unsigned long pa;
+
+        /*
+         * If we're dom0, then linear map the ISA machine addresses into
+         * the kernel's address space.
+         */
+        if (!xen_initial_domain())
+                return;
+
+        xen_raw_printk("Xen: setup ISA identity maps\n");
+
+        for (pa = ISA_START_ADDRESS; pa < ISA_END_ADDRESS; pa += PAGE_SIZE) {
+                pte_t pte = mfn_pte(PFN_DOWN(pa), PAGE_KERNEL_IO);
+
+                if (HYPERVISOR_update_va_mapping(PAGE_OFFSET + pa, pte, 0))
+                        BUG();
+        }
+
+        xen_flush_tlb();
+}
+
 static __init void xen_post_allocator_init(void)
 {
         pv_mmu_ops.set_pte = xen_set_pte;
@@ -2320,6 +2359,8 @@ void __init xen_init_mmu_ops(void)
         pv_mmu_ops = xen_mmu_ops;
 
         vmap_lazy_unmap = false;
+
+        memset(dummy_mapping, 0xff, PAGE_SIZE);
 }
 
 /* Protected by xen_reservation_lock. */
diff --git a/arch/x86/xen/pci-swiotlb-xen.c b/arch/x86/xen/pci-swiotlb-xen.c
index 22471001b74c..bfd0632fe65e 100644
--- a/arch/x86/xen/pci-swiotlb-xen.c
+++ b/arch/x86/xen/pci-swiotlb-xen.c
@@ -1,6 +1,7 @@
 /* Glue code to lib/swiotlb-xen.c */
 
 #include <linux/dma-mapping.h>
+#include <linux/pci.h>
 #include <xen/swiotlb-xen.h>
 
 #include <asm/xen/hypervisor.h>
@@ -55,6 +56,9 @@ void __init pci_xen_swiotlb_init(void)
         if (xen_swiotlb) {
                 xen_swiotlb_init(1);
                 dma_ops = &xen_swiotlb_dma_ops;
+
+                /* Make sure ACS will be enabled */
+                pci_request_acs();
         }
 }
 IOMMU_INIT_FINISH(pci_xen_swiotlb_detect,
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index 105db2501050..769c4b01fa32 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -118,16 +118,18 @@ static unsigned long __init xen_return_unused_memory(unsigned long max_pfn,
                                                      const struct e820map *e820)
 {
         phys_addr_t max_addr = PFN_PHYS(max_pfn);
-        phys_addr_t last_end = 0;
+        phys_addr_t last_end = ISA_END_ADDRESS;
         unsigned long released = 0;
         int i;
 
+        /* Free any unused memory above the low 1Mbyte. */
         for (i = 0; i < e820->nr_map && last_end < max_addr; i++) {
                 phys_addr_t end = e820->map[i].addr;
                 end = min(max_addr, end);
 
-                released += xen_release_chunk(last_end, end);
-                last_end = e820->map[i].addr + e820->map[i].size;
+                if (last_end < end)
+                        released += xen_release_chunk(last_end, end);
+                last_end = max(last_end, e820->map[i].addr + e820->map[i].size);
         }
 
         if (last_end < max_addr)
@@ -164,6 +166,7 @@ char * __init xen_memory_setup(void)
                 XENMEM_memory_map;
         rc = HYPERVISOR_memory_op(op, &memmap);
         if (rc == -ENOSYS) {
+                BUG_ON(xen_initial_domain());
                 memmap.nr_entries = 1;
                 map[0].addr = 0ULL;
                 map[0].size = mem_end;
@@ -201,9 +204,13 @@ char * __init xen_memory_setup(void)
         }
 
         /*
-         * Even though this is normal, usable memory under Xen, reserve
-         * ISA memory anyway because too many things think they can poke
+         * In domU, the ISA region is normal, usable memory, but we
+         * reserve ISA memory anyway because too many things poke
          * about in there.
+         *
+         * In Dom0, the host E820 information can leave gaps in the
+         * ISA range, which would cause us to release those pages.  To
+         * avoid this, we unconditionally reserve them here.
          */
         e820_add_region(ISA_START_ADDRESS, ISA_END_ADDRESS - ISA_START_ADDRESS,
                         E820_RESERVED);
@@ -367,7 +374,5 @@ void __init xen_arch_setup(void)
 
         pm_idle = xen_idle;
 
-        paravirt_disable_iospace();
-
         fiddle_vdso();
 }
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index f4d010031465..72a4c7959045 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -28,6 +28,7 @@
 #include <asm/xen/interface.h>
 #include <asm/xen/hypercall.h>
 
+#include <xen/xen.h>
 #include <xen/page.h>
 #include <xen/events.h>
 
@@ -156,11 +157,35 @@ static void __init xen_fill_possible_map(void)
 {
         int i, rc;
 
+        if (xen_initial_domain())
+                return;
+
+        for (i = 0; i < nr_cpu_ids; i++) {
+                rc = HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL);
+                if (rc >= 0) {
+                        num_processors++;
+                        set_cpu_possible(i, true);
+                }
+        }
+}
+
+static void __init xen_filter_cpu_maps(void)
+{
+        int i, rc;
+
+        if (!xen_initial_domain())
+                return;
+
+        num_processors = 0;
+        disabled_cpus = 0;
         for (i = 0; i < nr_cpu_ids; i++) {
                 rc = HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL);
                 if (rc >= 0) {
                         num_processors++;
                         set_cpu_possible(i, true);
+                } else {
+                        set_cpu_possible(i, false);
+                        set_cpu_present(i, false);
                 }
         }
 }
@@ -174,6 +199,7 @@ static void __init xen_smp_prepare_boot_cpu(void)
            old memory can be recycled */
         make_lowmem_page_readwrite(xen_initial_gdt);
 
+        xen_filter_cpu_maps();
         xen_setup_vcpu_info_placement();
 }
 
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 0859bfd8ae93..d373d159e75e 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -1,8 +1,3 @@
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-
-mainmenu "Linux/Xtensa Kernel Configuration"
-
 config FRAME_POINTER
         def_bool n