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-rw-r--r--arch/tile/include/arch/icache.h94
-rw-r--r--arch/tile/include/asm/cacheflush.h9
-rw-r--r--arch/tile/lib/Makefile2
-rw-r--r--arch/tile/lib/__invalidate_icache.S106
-rw-r--r--arch/tile/lib/cacheflush.c23
5 files changed, 120 insertions, 114 deletions
diff --git a/arch/tile/include/arch/icache.h b/arch/tile/include/arch/icache.h
new file mode 100644
index 000000000000..5c87c9016338
--- /dev/null
+++ b/arch/tile/include/arch/icache.h
@@ -0,0 +1,94 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16/**
17 * @file
18 *
19 * Support for invalidating bytes in the instruction
20 */
21
22#ifndef __ARCH_ICACHE_H__
23#define __ARCH_ICACHE_H__
24
25#include <arch/chip.h>
26
27
28/**
29 * Invalidate the instruction cache for the given range of memory.
30 *
31 * @param addr The start of memory to be invalidated.
32 * @param size The number of bytes to be invalidated.
33 * @param page_size The system's page size, typically the PAGE_SIZE constant
34 * in sys/page.h. This value must be a power of two no larger
35 * than the page containing the code to be invalidated. If the value
36 * is smaller than the actual page size, this function will still
37 * work, but may run slower than necessary.
38 */
39static __inline void
40invalidate_icache(const void* addr, unsigned long size,
41 unsigned long page_size)
42{
43 const unsigned long cache_way_size =
44 CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
45 unsigned long max_useful_size;
46 const char* start, *end;
47 long num_passes;
48
49 if (__builtin_expect(size == 0, 0))
50 return;
51
52#ifdef __tilegx__
53 /* Limit the number of bytes visited to avoid redundant iterations. */
54 max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
55
56 /* No PA aliasing is possible, so one pass always suffices. */
57 num_passes = 1;
58#else
59 /* Limit the number of bytes visited to avoid redundant iterations. */
60 max_useful_size = cache_way_size;
61
62 /*
63 * Compute how many passes we need (we'll treat 0 as if it were 1).
64 * This works because we know the page size is a power of two.
65 */
66 num_passes = cache_way_size >> __builtin_ctzl(page_size);
67#endif
68
69 if (__builtin_expect(size > max_useful_size, 0))
70 size = max_useful_size;
71
72 /* Locate the first and last bytes to be invalidated. */
73 start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
74 end = (const char*)addr + size - 1;
75
76 __insn_mf();
77
78 do
79 {
80 const char* p;
81
82 for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
83 __insn_icoh(p);
84
85 start += page_size;
86 end += page_size;
87 }
88 while (--num_passes > 0);
89
90 __insn_drain();
91}
92
93
94#endif /* __ARCH_ICACHE_H__ */
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index 7e2096a4ef7d..c5741da4eeac 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -21,6 +21,7 @@
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/cache.h> 22#include <linux/cache.h>
23#include <asm/system.h> 23#include <asm/system.h>
24#include <arch/icache.h>
24 25
25/* Caches are physically-indexed and so don't need special treatment */ 26/* Caches are physically-indexed and so don't need special treatment */
26#define flush_cache_all() do { } while (0) 27#define flush_cache_all() do { } while (0)
@@ -37,14 +38,8 @@
37#define flush_icache_page(vma, pg) do { } while (0) 38#define flush_icache_page(vma, pg) do { } while (0)
38#define flush_icache_user_range(vma, pg, adr, len) do { } while (0) 39#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
39 40
40/* See "arch/tile/lib/__invalidate_icache.S". */
41extern void __invalidate_icache(unsigned long start, unsigned long size);
42
43/* Flush the icache just on this cpu */ 41/* Flush the icache just on this cpu */
44static inline void __flush_icache_range(unsigned long start, unsigned long end) 42extern void __flush_icache_range(unsigned long start, unsigned long end);
45{
46 __invalidate_icache(start, end - start);
47}
48 43
49/* Flush the entire icache on this cpu. */ 44/* Flush the entire icache on this cpu. */
50#define __flush_icache() __flush_icache_range(0, CHIP_L1I_CACHE_SIZE()) 45#define __flush_icache() __flush_icache_range(0, CHIP_L1I_CACHE_SIZE())
diff --git a/arch/tile/lib/Makefile b/arch/tile/lib/Makefile
index ea9c209d33fb..438af38bc9eb 100644
--- a/arch/tile/lib/Makefile
+++ b/arch/tile/lib/Makefile
@@ -2,7 +2,7 @@
2# Makefile for TILE-specific library files.. 2# Makefile for TILE-specific library files..
3# 3#
4 4
5lib-y = checksum.o cpumask.o delay.o __invalidate_icache.o \ 5lib-y = cacheflush.o checksum.o cpumask.o delay.o \
6 mb_incoherent.o uaccess.o \ 6 mb_incoherent.o uaccess.o \
7 memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \ 7 memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \
8 strchr_$(BITS).o strlen_$(BITS).o 8 strchr_$(BITS).o strlen_$(BITS).o
diff --git a/arch/tile/lib/__invalidate_icache.S b/arch/tile/lib/__invalidate_icache.S
deleted file mode 100644
index 92e705059127..000000000000
--- a/arch/tile/lib/__invalidate_icache.S
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 * A routine for synchronizing the instruction and data caches.
14 * Useful for self-modifying code.
15 *
16 * r0 holds the buffer address
17 * r1 holds the size in bytes
18 */
19
20#include <arch/chip.h>
21#include <feedback.h>
22
23#if defined(__NEWLIB__) || defined(__BME__)
24#include <sys/page.h>
25#else
26#include <asm/page.h>
27#endif
28
29#ifdef __tilegx__
30/* Share code among Tile family chips but adjust opcodes appropriately. */
31#define slt cmpltu
32#define bbst blbst
33#define bnezt bnzt
34#endif
35
36#if defined(__tilegx__) && __SIZEOF_POINTER__ == 4
37/* Force 32-bit ops so pointers wrap around appropriately. */
38#define ADD_PTR addx
39#define ADDI_PTR addxi
40#else
41#define ADD_PTR add
42#define ADDI_PTR addi
43#endif
44
45 .section .text.__invalidate_icache, "ax"
46 .global __invalidate_icache
47 .type __invalidate_icache,@function
48 .hidden __invalidate_icache
49 .align 8
50__invalidate_icache:
51 FEEDBACK_ENTER(__invalidate_icache)
52 {
53 ADD_PTR r1, r0, r1 /* end of buffer */
54 blez r1, .Lexit /* skip out if size <= 0 */
55 }
56 {
57 ADDI_PTR r1, r1, -1 /* point to last byte to flush */
58 andi r0, r0, -CHIP_L1I_LINE_SIZE() /* align to cache-line size */
59 }
60 {
61 andi r1, r1, -CHIP_L1I_LINE_SIZE() /* last cache line to flush */
62 mf
63 }
64#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
65 {
66 moveli r4, CHIP_L1I_CACHE_SIZE() / PAGE_SIZE /* loop counter */
67 move r2, r0 /* remember starting address */
68 }
69#endif
70 drain
71 {
72 slt r3, r0, r1 /* set up loop invariant */
73#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
74 moveli r6, PAGE_SIZE
75#endif
76 }
77.Lentry:
78 {
79 icoh r0
80 ADDI_PTR r0, r0, CHIP_L1I_LINE_SIZE() /* advance buffer */
81 }
82 {
83 slt r3, r0, r1 /* check if buffer < buffer + size */
84 bbst r3, .Lentry /* loop if buffer < buffer + size */
85 }
86#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
87 {
88 ADD_PTR r2, r2, r6
89 ADD_PTR r1, r1, r6
90 }
91 {
92 move r0, r2
93 addi r4, r4, -1
94 }
95 {
96 slt r3, r0, r1 /* set up loop invariant */
97 bnezt r4, .Lentry
98 }
99#endif
100 drain
101.Lexit:
102 jrp lr
103
104.Lend___invalidate_icache:
105 .size __invalidate_icache, \
106 .Lend___invalidate_icache - __invalidate_icache
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
new file mode 100644
index 000000000000..11b6164c2097
--- /dev/null
+++ b/arch/tile/lib/cacheflush.c
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <asm/page.h>
16#include <asm/cacheflush.h>
17#include <arch/icache.h>
18
19
20void __flush_icache_range(unsigned long start, unsigned long end)
21{
22 invalidate_icache((const void *)start, end - start, PAGE_SIZE);
23}
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