diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-33xx.h | 158 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/control.h | 1 |
2 files changed, 145 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index 532027ee3d8d..adf7bb79b18f 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h | |||
| @@ -25,263 +25,328 @@ | |||
| 25 | * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER | 25 | * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER |
| 26 | */ | 26 | */ |
| 27 | #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 | 27 | #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 |
| 28 | #define AM33XX_AUTO_DPLL_MODE_WIDTH 3 | ||
| 28 | #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) | 29 | #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) |
| 29 | 30 | ||
| 30 | /* Used by CM_WKUP_CLKSTCTRL */ | 31 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 31 | #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 | 32 | #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 |
| 33 | #define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 | ||
| 32 | #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) | 34 | #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) |
| 33 | 35 | ||
| 34 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 36 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 35 | #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 | 37 | #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 |
| 38 | #define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 | ||
| 36 | #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) | 39 | #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) |
| 37 | 40 | ||
| 38 | /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ | 41 | /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ |
| 39 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 | 42 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 |
| 43 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 | ||
| 40 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) | 44 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) |
| 41 | 45 | ||
| 42 | /* Used by CM_PER_CPSW_CLKSTCTRL */ | 46 | /* Used by CM_PER_CPSW_CLKSTCTRL */ |
| 43 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 | 47 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 |
| 48 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 | ||
| 44 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) | 49 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) |
| 45 | 50 | ||
| 46 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | 51 | /* Used by CM_PER_L4HS_CLKSTCTRL */ |
| 47 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 | 52 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 |
| 53 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 | ||
| 48 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) | 54 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) |
| 49 | 55 | ||
| 50 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | 56 | /* Used by CM_PER_L4HS_CLKSTCTRL */ |
| 51 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 | 57 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 |
| 58 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 | ||
| 52 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) | 59 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) |
| 53 | 60 | ||
| 54 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | 61 | /* Used by CM_PER_L4HS_CLKSTCTRL */ |
| 55 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 | 62 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 |
| 63 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 | ||
| 56 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) | 64 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) |
| 57 | 65 | ||
| 58 | /* Used by CM_PER_L3_CLKSTCTRL */ | 66 | /* Used by CM_PER_L3_CLKSTCTRL */ |
| 59 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 | 67 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 |
| 68 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 | ||
| 60 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) | 69 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) |
| 61 | 70 | ||
| 62 | /* Used by CM_CEFUSE_CLKSTCTRL */ | 71 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| 63 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 | 72 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 |
| 73 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 | ||
| 64 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) | 74 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) |
| 65 | 75 | ||
| 66 | /* Used by CM_L3_AON_CLKSTCTRL */ | 76 | /* Used by CM_L3_AON_CLKSTCTRL */ |
| 67 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 | 77 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 |
| 78 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 | ||
| 68 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) | 79 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) |
| 69 | 80 | ||
| 70 | /* Used by CM_L3_AON_CLKSTCTRL */ | 81 | /* Used by CM_L3_AON_CLKSTCTRL */ |
| 71 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 | 82 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 |
| 83 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 | ||
| 72 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) | 84 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) |
| 73 | 85 | ||
| 74 | /* Used by CM_PER_L3_CLKSTCTRL */ | 86 | /* Used by CM_PER_L3_CLKSTCTRL */ |
| 75 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 | 87 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 |
| 88 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 | ||
| 76 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) | 89 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) |
| 77 | 90 | ||
| 78 | /* Used by CM_GFX_L3_CLKSTCTRL */ | 91 | /* Used by CM_GFX_L3_CLKSTCTRL */ |
| 79 | #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 | 92 | #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 |
| 93 | #define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 | ||
| 80 | #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) | 94 | #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) |
| 81 | 95 | ||
| 82 | /* Used by CM_GFX_L3_CLKSTCTRL */ | 96 | /* Used by CM_GFX_L3_CLKSTCTRL */ |
| 83 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 | 97 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 |
| 98 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 | ||
| 84 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) | 99 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) |
| 85 | 100 | ||
| 86 | /* Used by CM_WKUP_CLKSTCTRL */ | 101 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 87 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 | 102 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 |
| 103 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 | ||
| 88 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) | 104 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) |
| 89 | 105 | ||
| 90 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 106 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 91 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 | 107 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 |
| 108 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 | ||
| 92 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) | 109 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) |
| 93 | 110 | ||
| 94 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 111 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 95 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 | 112 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 |
| 113 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 | ||
| 96 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) | 114 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) |
| 97 | 115 | ||
| 98 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 116 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 99 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 | 117 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 |
| 118 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 | ||
| 100 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) | 119 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) |
| 101 | 120 | ||
| 102 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 121 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 103 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 | 122 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 |
| 123 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 | ||
| 104 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) | 124 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) |
| 105 | 125 | ||
| 106 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 126 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 107 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 | 127 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 |
| 128 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 | ||
| 108 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) | 129 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) |
| 109 | 130 | ||
| 110 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 131 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 111 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 | 132 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 |
| 133 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 | ||
| 112 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) | 134 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) |
| 113 | 135 | ||
| 114 | /* Used by CM_WKUP_CLKSTCTRL */ | 136 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 115 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 | 137 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 |
| 138 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 | ||
| 116 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) | 139 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) |
| 117 | 140 | ||
| 118 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 141 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 119 | #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 | 142 | #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 |
| 143 | #define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 | ||
| 120 | #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) | 144 | #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) |
| 121 | 145 | ||
| 122 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | 146 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ |
| 123 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 | 147 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 |
| 148 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 | ||
| 124 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) | 149 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) |
| 125 | 150 | ||
| 126 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | 151 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ |
| 127 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 | 152 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 |
| 153 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 | ||
| 128 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) | 154 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) |
| 129 | 155 | ||
| 130 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | 156 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ |
| 131 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 | 157 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 |
| 158 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 | ||
| 132 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) | 159 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) |
| 133 | 160 | ||
| 134 | /* Used by CM_PER_L3S_CLKSTCTRL */ | 161 | /* Used by CM_PER_L3S_CLKSTCTRL */ |
| 135 | #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 | 162 | #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 |
| 163 | #define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 | ||
| 136 | #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) | 164 | #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) |
| 137 | 165 | ||
| 138 | /* Used by CM_L3_AON_CLKSTCTRL */ | 166 | /* Used by CM_L3_AON_CLKSTCTRL */ |
| 139 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 | 167 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 |
| 168 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 | ||
| 140 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) | 169 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) |
| 141 | 170 | ||
| 142 | /* Used by CM_PER_L3_CLKSTCTRL */ | 171 | /* Used by CM_PER_L3_CLKSTCTRL */ |
| 143 | #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 | 172 | #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 |
| 173 | #define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 | ||
| 144 | #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) | 174 | #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) |
| 145 | 175 | ||
| 146 | /* Used by CM_PER_L4FW_CLKSTCTRL */ | 176 | /* Used by CM_PER_L4FW_CLKSTCTRL */ |
| 147 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 | 177 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 |
| 178 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 | ||
| 148 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) | 179 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) |
| 149 | 180 | ||
| 150 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | 181 | /* Used by CM_PER_L4HS_CLKSTCTRL */ |
| 151 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 | 182 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 |
| 183 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 | ||
| 152 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) | 184 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) |
| 153 | 185 | ||
| 154 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 186 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 155 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 | 187 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 |
| 188 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 | ||
| 156 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) | 189 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) |
| 157 | 190 | ||
| 158 | /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ | 191 | /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ |
| 159 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 | 192 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 |
| 193 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 | ||
| 160 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) | 194 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) |
| 161 | 195 | ||
| 162 | /* Used by CM_CEFUSE_CLKSTCTRL */ | 196 | /* Used by CM_CEFUSE_CLKSTCTRL */ |
| 163 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 | 197 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 |
| 198 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 | ||
| 164 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) | 199 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) |
| 165 | 200 | ||
| 166 | /* Used by CM_RTC_CLKSTCTRL */ | 201 | /* Used by CM_RTC_CLKSTCTRL */ |
| 167 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 | 202 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 |
| 203 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 | ||
| 168 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) | 204 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) |
| 169 | 205 | ||
| 170 | /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ | 206 | /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ |
| 171 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 | 207 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 |
| 208 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 | ||
| 172 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) | 209 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) |
| 173 | 210 | ||
| 174 | /* Used by CM_WKUP_CLKSTCTRL */ | 211 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 175 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 | 212 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 |
| 213 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 | ||
| 176 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) | 214 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) |
| 177 | 215 | ||
| 178 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 216 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 179 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 | 217 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 |
| 218 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 | ||
| 180 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) | 219 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) |
| 181 | 220 | ||
| 182 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | 221 | /* Used by CM_PER_LCDC_CLKSTCTRL */ |
| 183 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 | 222 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 |
| 223 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 | ||
| 184 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) | 224 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) |
| 185 | 225 | ||
| 186 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | 226 | /* Used by CM_PER_LCDC_CLKSTCTRL */ |
| 187 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 | 227 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 |
| 228 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 | ||
| 188 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) | 229 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) |
| 189 | 230 | ||
| 190 | /* Used by CM_PER_L3_CLKSTCTRL */ | 231 | /* Used by CM_PER_L3_CLKSTCTRL */ |
| 191 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 | 232 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 |
| 233 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 | ||
| 192 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) | 234 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) |
| 193 | 235 | ||
| 194 | /* Used by CM_PER_L3_CLKSTCTRL */ | 236 | /* Used by CM_PER_L3_CLKSTCTRL */ |
| 195 | #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 | 237 | #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 |
| 238 | #define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 | ||
| 196 | #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) | 239 | #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) |
| 197 | 240 | ||
| 198 | /* Used by CM_MPU_CLKSTCTRL */ | 241 | /* Used by CM_MPU_CLKSTCTRL */ |
| 199 | #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 | 242 | #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 |
| 243 | #define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 | ||
| 200 | #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) | 244 | #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) |
| 201 | 245 | ||
| 202 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | 246 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ |
| 203 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 | 247 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 |
| 248 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 | ||
| 204 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) | 249 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) |
| 205 | 250 | ||
| 206 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | 251 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ |
| 207 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 | 252 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 |
| 253 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 | ||
| 208 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) | 254 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) |
| 209 | 255 | ||
| 210 | /* Used by CM_RTC_CLKSTCTRL */ | 256 | /* Used by CM_RTC_CLKSTCTRL */ |
| 211 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 | 257 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 |
| 258 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 | ||
| 212 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) | 259 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) |
| 213 | 260 | ||
| 214 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 261 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 215 | #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 | 262 | #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 |
| 263 | #define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 | ||
| 216 | #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) | 264 | #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) |
| 217 | 265 | ||
| 218 | /* Used by CM_WKUP_CLKSTCTRL */ | 266 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 219 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 | 267 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 |
| 268 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 | ||
| 220 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) | 269 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) |
| 221 | 270 | ||
| 222 | /* Used by CM_WKUP_CLKSTCTRL */ | 271 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 223 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 | 272 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 |
| 273 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 | ||
| 224 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) | 274 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) |
| 225 | 275 | ||
| 226 | /* Used by CM_WKUP_CLKSTCTRL */ | 276 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 227 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 | 277 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 |
| 278 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 | ||
| 228 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) | 279 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) |
| 229 | 280 | ||
| 230 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 281 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 231 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 | 282 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 |
| 283 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 | ||
| 232 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) | 284 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) |
| 233 | 285 | ||
| 234 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 286 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 235 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 | 287 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 |
| 288 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 | ||
| 236 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) | 289 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) |
| 237 | 290 | ||
| 238 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 291 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 239 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 | 292 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 |
| 293 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 | ||
| 240 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) | 294 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) |
| 241 | 295 | ||
| 242 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 296 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 243 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 | 297 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 |
| 298 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 | ||
| 244 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) | 299 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) |
| 245 | 300 | ||
| 246 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 301 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 247 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 | 302 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 |
| 303 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 | ||
| 248 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) | 304 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) |
| 249 | 305 | ||
| 250 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 306 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 251 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 | 307 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 |
| 308 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 | ||
| 252 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) | 309 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) |
| 253 | 310 | ||
| 254 | /* Used by CM_WKUP_CLKSTCTRL */ | 311 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 255 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 | 312 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 |
| 313 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 | ||
| 256 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) | 314 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) |
| 257 | 315 | ||
| 258 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | 316 | /* Used by CM_PER_L4LS_CLKSTCTRL */ |
| 259 | #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 | 317 | #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 |
| 318 | #define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 | ||
| 260 | #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) | 319 | #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) |
| 261 | 320 | ||
| 262 | /* Used by CM_WKUP_CLKSTCTRL */ | 321 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 263 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 | 322 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 |
| 323 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 | ||
| 264 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) | 324 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) |
| 265 | 325 | ||
| 266 | /* Used by CM_WKUP_CLKSTCTRL */ | 326 | /* Used by CM_WKUP_CLKSTCTRL */ |
| 267 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 | 327 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 |
| 328 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 | ||
| 268 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) | 329 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) |
| 269 | 330 | ||
| 270 | /* Used by CLKSEL_GFX_FCLK */ | 331 | /* Used by CLKSEL_GFX_FCLK */ |
| 271 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 | 332 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 |
| 333 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 | ||
| 272 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) | 334 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) |
| 273 | 335 | ||
| 274 | /* Used by CM_CLKOUT_CTRL */ | 336 | /* Used by CM_CLKOUT_CTRL */ |
| 275 | #define AM33XX_CLKOUT2DIV_SHIFT 3 | 337 | #define AM33XX_CLKOUT2DIV_SHIFT 3 |
| 276 | #define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) | 338 | #define AM33XX_CLKOUT2DIV_WIDTH 3 |
| 339 | #define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) | ||
| 277 | 340 | ||
| 278 | /* Used by CM_CLKOUT_CTRL */ | 341 | /* Used by CM_CLKOUT_CTRL */ |
| 279 | #define AM33XX_CLKOUT2EN_SHIFT 7 | 342 | #define AM33XX_CLKOUT2EN_SHIFT 7 |
| 343 | #define AM33XX_CLKOUT2EN_WIDTH 1 | ||
| 280 | #define AM33XX_CLKOUT2EN_MASK (1 << 7) | 344 | #define AM33XX_CLKOUT2EN_MASK (1 << 7) |
| 281 | 345 | ||
| 282 | /* Used by CM_CLKOUT_CTRL */ | 346 | /* Used by CM_CLKOUT_CTRL */ |
| 283 | #define AM33XX_CLKOUT2SOURCE_SHIFT 0 | 347 | #define AM33XX_CLKOUT2SOURCE_SHIFT 0 |
| 284 | #define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) | 348 | #define AM33XX_CLKOUT2SOURCE_WIDTH 3 |
| 349 | #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) | ||
| 285 | 350 | ||
| 286 | /* | 351 | /* |
| 287 | * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, | 352 | * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, |
| @@ -289,6 +354,7 @@ | |||
| 289 | * CLKSEL_TIMER7_CLK | 354 | * CLKSEL_TIMER7_CLK |
| 290 | */ | 355 | */ |
| 291 | #define AM33XX_CLKSEL_SHIFT 0 | 356 | #define AM33XX_CLKSEL_SHIFT 0 |
| 357 | #define AM33XX_CLKSEL_WIDTH 1 | ||
| 292 | #define AM33XX_CLKSEL_MASK (0x01 << 0) | 358 | #define AM33XX_CLKSEL_MASK (0x01 << 0) |
| 293 | 359 | ||
| 294 | /* | 360 | /* |
| @@ -296,17 +362,21 @@ | |||
| 296 | * CM_CPTS_RFT_CLKSEL | 362 | * CM_CPTS_RFT_CLKSEL |
| 297 | */ | 363 | */ |
| 298 | #define AM33XX_CLKSEL_0_0_SHIFT 0 | 364 | #define AM33XX_CLKSEL_0_0_SHIFT 0 |
| 365 | #define AM33XX_CLKSEL_0_0_WIDTH 1 | ||
| 299 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) | 366 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) |
| 300 | 367 | ||
| 301 | #define AM33XX_CLKSEL_0_1_SHIFT 0 | 368 | #define AM33XX_CLKSEL_0_1_SHIFT 0 |
| 369 | #define AM33XX_CLKSEL_0_1_WIDTH 2 | ||
| 302 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) | 370 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) |
| 303 | 371 | ||
| 304 | /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ | 372 | /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ |
| 305 | #define AM33XX_CLKSEL_0_2_SHIFT 0 | 373 | #define AM33XX_CLKSEL_0_2_SHIFT 0 |
| 374 | #define AM33XX_CLKSEL_0_2_WIDTH 3 | ||
| 306 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) | 375 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) |
| 307 | 376 | ||
| 308 | /* Used by CLKSEL_GFX_FCLK */ | 377 | /* Used by CLKSEL_GFX_FCLK */ |
| 309 | #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 | 378 | #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 |
| 379 | #define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1 | ||
| 310 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) | 380 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) |
| 311 | 381 | ||
| 312 | /* | 382 | /* |
| @@ -318,6 +388,7 @@ | |||
| 318 | * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL | 388 | * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL |
| 319 | */ | 389 | */ |
| 320 | #define AM33XX_CLKTRCTRL_SHIFT 0 | 390 | #define AM33XX_CLKTRCTRL_SHIFT 0 |
| 391 | #define AM33XX_CLKTRCTRL_WIDTH 2 | ||
| 321 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) | 392 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) |
| 322 | 393 | ||
| 323 | /* | 394 | /* |
| @@ -326,34 +397,42 @@ | |||
| 326 | * CM_SSC_DELTAMSTEP_DPLL_PER | 397 | * CM_SSC_DELTAMSTEP_DPLL_PER |
| 327 | */ | 398 | */ |
| 328 | #define AM33XX_DELTAMSTEP_SHIFT 0 | 399 | #define AM33XX_DELTAMSTEP_SHIFT 0 |
| 329 | #define AM33XX_DELTAMSTEP_MASK (0x19 << 0) | 400 | #define AM33XX_DELTAMSTEP_WIDTH 20 |
| 401 | #define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) | ||
| 330 | 402 | ||
| 331 | /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ | 403 | /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ |
| 332 | #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 | 404 | #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 |
| 405 | #define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 | ||
| 333 | #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) | 406 | #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) |
| 334 | 407 | ||
| 335 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | 408 | /* Used by CM_CLKDCOLDO_DPLL_PER */ |
| 336 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 | 409 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 |
| 410 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 | ||
| 337 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) | 411 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) |
| 338 | 412 | ||
| 339 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | 413 | /* Used by CM_CLKDCOLDO_DPLL_PER */ |
| 340 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 | 414 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 |
| 415 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 | ||
| 341 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) | 416 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) |
| 342 | 417 | ||
| 343 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | 418 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ |
| 344 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 | 419 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 |
| 420 | #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 | ||
| 345 | #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | 421 | #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
| 346 | 422 | ||
| 347 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ | 423 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ |
| 348 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 | 424 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 |
| 349 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) | 425 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 |
| 426 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) | ||
| 350 | 427 | ||
| 351 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | 428 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ |
| 352 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 | 429 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 |
| 430 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 | ||
| 353 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) | 431 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) |
| 354 | 432 | ||
| 355 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ | 433 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ |
| 356 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 | 434 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 |
| 435 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 | ||
| 357 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) | 436 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) |
| 358 | 437 | ||
| 359 | /* | 438 | /* |
| @@ -361,6 +440,7 @@ | |||
| 361 | * CM_DIV_M2_DPLL_PER | 440 | * CM_DIV_M2_DPLL_PER |
| 362 | */ | 441 | */ |
| 363 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 | 442 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 |
| 443 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 | ||
| 364 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | 444 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) |
| 365 | 445 | ||
| 366 | /* | 446 | /* |
| @@ -368,19 +448,22 @@ | |||
| 368 | * CM_CLKSEL_DPLL_MPU | 448 | * CM_CLKSEL_DPLL_MPU |
| 369 | */ | 449 | */ |
| 370 | #define AM33XX_DPLL_DIV_SHIFT 0 | 450 | #define AM33XX_DPLL_DIV_SHIFT 0 |
| 451 | #define AM33XX_DPLL_DIV_WIDTH 7 | ||
| 371 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) | 452 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) |
| 372 | 453 | ||
| 373 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) | 454 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) |
| 374 | 455 | ||
| 375 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ | 456 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ |
| 376 | #define AM33XX_DPLL_DIV_0_7_SHIFT 0 | 457 | #define AM33XX_DPLL_DIV_0_7_SHIFT 0 |
| 377 | #define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) | 458 | #define AM33XX_DPLL_DIV_0_7_WIDTH 8 |
| 459 | #define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) | ||
| 378 | 460 | ||
| 379 | /* | 461 | /* |
| 380 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | 462 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, |
| 381 | * CM_CLKMODE_DPLL_MPU | 463 | * CM_CLKMODE_DPLL_MPU |
| 382 | */ | 464 | */ |
| 383 | #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 | 465 | #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 |
| 466 | #define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 | ||
| 384 | #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | 467 | #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) |
| 385 | 468 | ||
| 386 | /* | 469 | /* |
| @@ -388,6 +471,7 @@ | |||
| 388 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | 471 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER |
| 389 | */ | 472 | */ |
| 390 | #define AM33XX_DPLL_EN_SHIFT 0 | 473 | #define AM33XX_DPLL_EN_SHIFT 0 |
| 474 | #define AM33XX_DPLL_EN_WIDTH 3 | ||
| 391 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) | 475 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) |
| 392 | 476 | ||
| 393 | /* | 477 | /* |
| @@ -395,6 +479,7 @@ | |||
| 395 | * CM_CLKMODE_DPLL_MPU | 479 | * CM_CLKMODE_DPLL_MPU |
| 396 | */ | 480 | */ |
| 397 | #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 | 481 | #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 |
| 482 | #define AM33XX_DPLL_LPMODE_EN_WIDTH 1 | ||
| 398 | #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) | 483 | #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) |
| 399 | 484 | ||
| 400 | /* | 485 | /* |
| @@ -402,10 +487,12 @@ | |||
| 402 | * CM_CLKSEL_DPLL_MPU | 487 | * CM_CLKSEL_DPLL_MPU |
| 403 | */ | 488 | */ |
| 404 | #define AM33XX_DPLL_MULT_SHIFT 8 | 489 | #define AM33XX_DPLL_MULT_SHIFT 8 |
| 490 | #define AM33XX_DPLL_MULT_WIDTH 11 | ||
| 405 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) | 491 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) |
| 406 | 492 | ||
| 407 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ | 493 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ |
| 408 | #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 | 494 | #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 |
| 495 | #define AM33XX_DPLL_MULT_PERIPH_WIDTH 12 | ||
| 409 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) | 496 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) |
| 410 | 497 | ||
| 411 | /* | 498 | /* |
| @@ -413,17 +500,20 @@ | |||
| 413 | * CM_CLKMODE_DPLL_MPU | 500 | * CM_CLKMODE_DPLL_MPU |
| 414 | */ | 501 | */ |
| 415 | #define AM33XX_DPLL_REGM4XEN_SHIFT 11 | 502 | #define AM33XX_DPLL_REGM4XEN_SHIFT 11 |
| 503 | #define AM33XX_DPLL_REGM4XEN_WIDTH 1 | ||
| 416 | #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) | 504 | #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) |
| 417 | 505 | ||
| 418 | /* Used by CM_CLKSEL_DPLL_PERIPH */ | 506 | /* Used by CM_CLKSEL_DPLL_PERIPH */ |
| 419 | #define AM33XX_DPLL_SD_DIV_SHIFT 24 | 507 | #define AM33XX_DPLL_SD_DIV_SHIFT 24 |
| 420 | #define AM33XX_DPLL_SD_DIV_MASK (24, 31) | 508 | #define AM33XX_DPLL_SD_DIV_WIDTH 8 |
| 509 | #define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) | ||
| 421 | 510 | ||
| 422 | /* | 511 | /* |
| 423 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | 512 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, |
| 424 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | 513 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER |
| 425 | */ | 514 | */ |
| 426 | #define AM33XX_DPLL_SSC_ACK_SHIFT 13 | 515 | #define AM33XX_DPLL_SSC_ACK_SHIFT 13 |
| 516 | #define AM33XX_DPLL_SSC_ACK_WIDTH 1 | ||
| 427 | #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) | 517 | #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) |
| 428 | 518 | ||
| 429 | /* | 519 | /* |
| @@ -431,6 +521,7 @@ | |||
| 431 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | 521 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER |
| 432 | */ | 522 | */ |
| 433 | #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 | 523 | #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 |
| 524 | #define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 | ||
| 434 | #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | 525 | #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) |
| 435 | 526 | ||
| 436 | /* | 527 | /* |
| @@ -438,54 +529,67 @@ | |||
| 438 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | 529 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER |
| 439 | */ | 530 | */ |
| 440 | #define AM33XX_DPLL_SSC_EN_SHIFT 12 | 531 | #define AM33XX_DPLL_SSC_EN_SHIFT 12 |
| 532 | #define AM33XX_DPLL_SSC_EN_WIDTH 1 | ||
| 441 | #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) | 533 | #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) |
| 442 | 534 | ||
| 443 | /* Used by CM_DIV_M4_DPLL_CORE */ | 535 | /* Used by CM_DIV_M4_DPLL_CORE */ |
| 444 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 | 536 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 |
| 537 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 | ||
| 445 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) | 538 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) |
| 446 | 539 | ||
| 447 | /* Used by CM_DIV_M4_DPLL_CORE */ | 540 | /* Used by CM_DIV_M4_DPLL_CORE */ |
| 448 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 | 541 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 |
| 542 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 | ||
| 449 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) | 543 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) |
| 450 | 544 | ||
| 451 | /* Used by CM_DIV_M4_DPLL_CORE */ | 545 | /* Used by CM_DIV_M4_DPLL_CORE */ |
| 452 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 | 546 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 |
| 547 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 | ||
| 453 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) | 548 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) |
| 454 | 549 | ||
| 455 | /* Used by CM_DIV_M4_DPLL_CORE */ | 550 | /* Used by CM_DIV_M4_DPLL_CORE */ |
| 456 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 | 551 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 |
| 552 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 | ||
| 457 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) | 553 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) |
| 458 | 554 | ||
| 459 | /* Used by CM_DIV_M5_DPLL_CORE */ | 555 | /* Used by CM_DIV_M5_DPLL_CORE */ |
| 460 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 | 556 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 |
| 557 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 | ||
| 461 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) | 558 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) |
| 462 | 559 | ||
| 463 | /* Used by CM_DIV_M5_DPLL_CORE */ | 560 | /* Used by CM_DIV_M5_DPLL_CORE */ |
| 464 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 | 561 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 |
| 562 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 | ||
| 465 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) | 563 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) |
| 466 | 564 | ||
| 467 | /* Used by CM_DIV_M5_DPLL_CORE */ | 565 | /* Used by CM_DIV_M5_DPLL_CORE */ |
| 468 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 | 566 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 |
| 567 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 | ||
| 469 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) | 568 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) |
| 470 | 569 | ||
| 471 | /* Used by CM_DIV_M5_DPLL_CORE */ | 570 | /* Used by CM_DIV_M5_DPLL_CORE */ |
| 472 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 | 571 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 |
| 572 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 | ||
| 473 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) | 573 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) |
| 474 | 574 | ||
| 475 | /* Used by CM_DIV_M6_DPLL_CORE */ | 575 | /* Used by CM_DIV_M6_DPLL_CORE */ |
| 476 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 | 576 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 |
| 477 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) | 577 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 |
| 578 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) | ||
| 478 | 579 | ||
| 479 | /* Used by CM_DIV_M6_DPLL_CORE */ | 580 | /* Used by CM_DIV_M6_DPLL_CORE */ |
| 480 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 | 581 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 |
| 582 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 | ||
| 481 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) | 583 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) |
| 482 | 584 | ||
| 483 | /* Used by CM_DIV_M6_DPLL_CORE */ | 585 | /* Used by CM_DIV_M6_DPLL_CORE */ |
| 484 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 | 586 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 |
| 587 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 | ||
| 485 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) | 588 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) |
| 486 | 589 | ||
| 487 | /* Used by CM_DIV_M6_DPLL_CORE */ | 590 | /* Used by CM_DIV_M6_DPLL_CORE */ |
| 488 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 | 591 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 |
| 592 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 | ||
| 489 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) | 593 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) |
| 490 | 594 | ||
| 491 | /* | 595 | /* |
| @@ -522,11 +626,12 @@ | |||
| 522 | * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL | 626 | * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL |
| 523 | */ | 627 | */ |
| 524 | #define AM33XX_IDLEST_SHIFT 16 | 628 | #define AM33XX_IDLEST_SHIFT 16 |
| 629 | #define AM33XX_IDLEST_WIDTH 2 | ||
| 525 | #define AM33XX_IDLEST_MASK (0x3 << 16) | 630 | #define AM33XX_IDLEST_MASK (0x3 << 16) |
| 526 | #define AM33XX_IDLEST_VAL 0x3 | ||
| 527 | 631 | ||
| 528 | /* Used by CM_MAC_CLKSEL */ | 632 | /* Used by CM_MAC_CLKSEL */ |
| 529 | #define AM33XX_MII_CLK_SEL_SHIFT 2 | 633 | #define AM33XX_MII_CLK_SEL_SHIFT 2 |
| 634 | #define AM33XX_MII_CLK_SEL_WIDTH 1 | ||
| 530 | #define AM33XX_MII_CLK_SEL_MASK (1 << 2) | 635 | #define AM33XX_MII_CLK_SEL_MASK (1 << 2) |
| 531 | 636 | ||
| 532 | /* | 637 | /* |
| @@ -535,7 +640,8 @@ | |||
| 535 | * CM_SSC_MODFREQDIV_DPLL_PER | 640 | * CM_SSC_MODFREQDIV_DPLL_PER |
| 536 | */ | 641 | */ |
| 537 | #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 | 642 | #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 |
| 538 | #define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) | 643 | #define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 |
| 644 | #define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) | ||
| 539 | 645 | ||
| 540 | /* | 646 | /* |
| 541 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | 647 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, |
| @@ -543,7 +649,8 @@ | |||
| 543 | * CM_SSC_MODFREQDIV_DPLL_PER | 649 | * CM_SSC_MODFREQDIV_DPLL_PER |
| 544 | */ | 650 | */ |
| 545 | #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 | 651 | #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 |
| 546 | #define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) | 652 | #define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 |
| 653 | #define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) | ||
| 547 | 654 | ||
| 548 | /* | 655 | /* |
| 549 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | 656 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, |
| @@ -580,42 +687,52 @@ | |||
| 580 | * CM_CEFUSE_CEFUSE_CLKCTRL | 687 | * CM_CEFUSE_CEFUSE_CLKCTRL |
| 581 | */ | 688 | */ |
| 582 | #define AM33XX_MODULEMODE_SHIFT 0 | 689 | #define AM33XX_MODULEMODE_SHIFT 0 |
| 690 | #define AM33XX_MODULEMODE_WIDTH 2 | ||
| 583 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) | 691 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) |
| 584 | 692 | ||
| 585 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | 693 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ |
| 586 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 | 694 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 |
| 695 | #define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 | ||
| 587 | #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) | 696 | #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) |
| 588 | 697 | ||
| 589 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | 698 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ |
| 590 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 | 699 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 |
| 700 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 | ||
| 591 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) | 701 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) |
| 592 | 702 | ||
| 593 | /* Used by CM_WKUP_GPIO0_CLKCTRL */ | 703 | /* Used by CM_WKUP_GPIO0_CLKCTRL */ |
| 594 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 | 704 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 |
| 705 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 | ||
| 595 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) | 706 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) |
| 596 | 707 | ||
| 597 | /* Used by CM_PER_GPIO1_CLKCTRL */ | 708 | /* Used by CM_PER_GPIO1_CLKCTRL */ |
| 598 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 | 709 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 |
| 710 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 | ||
| 599 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) | 711 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) |
| 600 | 712 | ||
| 601 | /* Used by CM_PER_GPIO2_CLKCTRL */ | 713 | /* Used by CM_PER_GPIO2_CLKCTRL */ |
| 602 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 | 714 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 |
| 715 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 | ||
| 603 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) | 716 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) |
| 604 | 717 | ||
| 605 | /* Used by CM_PER_GPIO3_CLKCTRL */ | 718 | /* Used by CM_PER_GPIO3_CLKCTRL */ |
| 606 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 | 719 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 |
| 720 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 | ||
| 607 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) | 721 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) |
| 608 | 722 | ||
| 609 | /* Used by CM_PER_GPIO4_CLKCTRL */ | 723 | /* Used by CM_PER_GPIO4_CLKCTRL */ |
| 610 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 | 724 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 |
| 725 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 | ||
| 611 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) | 726 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) |
| 612 | 727 | ||
| 613 | /* Used by CM_PER_GPIO5_CLKCTRL */ | 728 | /* Used by CM_PER_GPIO5_CLKCTRL */ |
| 614 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 | 729 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 |
| 730 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 | ||
| 615 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) | 731 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) |
| 616 | 732 | ||
| 617 | /* Used by CM_PER_GPIO6_CLKCTRL */ | 733 | /* Used by CM_PER_GPIO6_CLKCTRL */ |
| 618 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 | 734 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 |
| 735 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 | ||
| 619 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) | 736 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) |
| 620 | 737 | ||
| 621 | /* | 738 | /* |
| @@ -627,25 +744,30 @@ | |||
| 627 | * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL | 744 | * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL |
| 628 | */ | 745 | */ |
| 629 | #define AM33XX_STBYST_SHIFT 18 | 746 | #define AM33XX_STBYST_SHIFT 18 |
| 747 | #define AM33XX_STBYST_WIDTH 1 | ||
| 630 | #define AM33XX_STBYST_MASK (1 << 18) | 748 | #define AM33XX_STBYST_MASK (1 << 18) |
| 631 | 749 | ||
| 632 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | 750 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ |
| 633 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 | 751 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 |
| 634 | #define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) | 752 | #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 |
| 753 | #define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) | ||
| 635 | 754 | ||
| 636 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | 755 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ |
| 637 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 | 756 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 |
| 638 | #define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) | 757 | #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 |
| 758 | #define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) | ||
| 639 | 759 | ||
| 640 | /* | 760 | /* |
| 641 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | 761 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, |
| 642 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | 762 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER |
| 643 | */ | 763 | */ |
| 644 | #define AM33XX_ST_DPLL_CLK_SHIFT 0 | 764 | #define AM33XX_ST_DPLL_CLK_SHIFT 0 |
| 765 | #define AM33XX_ST_DPLL_CLK_WIDTH 1 | ||
| 645 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) | 766 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) |
| 646 | 767 | ||
| 647 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | 768 | /* Used by CM_CLKDCOLDO_DPLL_PER */ |
| 648 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 | 769 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 |
| 770 | #define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 | ||
| 649 | #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) | 771 | #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) |
| 650 | 772 | ||
| 651 | /* | 773 | /* |
| @@ -653,18 +775,22 @@ | |||
| 653 | * CM_DIV_M2_DPLL_PER | 775 | * CM_DIV_M2_DPLL_PER |
| 654 | */ | 776 | */ |
| 655 | #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 | 777 | #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 |
| 778 | #define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 | ||
| 656 | #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) | 779 | #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) |
| 657 | 780 | ||
| 658 | /* Used by CM_DIV_M4_DPLL_CORE */ | 781 | /* Used by CM_DIV_M4_DPLL_CORE */ |
| 659 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 | 782 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 |
| 783 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 | ||
| 660 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) | 784 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) |
| 661 | 785 | ||
| 662 | /* Used by CM_DIV_M5_DPLL_CORE */ | 786 | /* Used by CM_DIV_M5_DPLL_CORE */ |
| 663 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 | 787 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 |
| 788 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 | ||
| 664 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) | 789 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) |
| 665 | 790 | ||
| 666 | /* Used by CM_DIV_M6_DPLL_CORE */ | 791 | /* Used by CM_DIV_M6_DPLL_CORE */ |
| 667 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 | 792 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 |
| 793 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 | ||
| 668 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) | 794 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) |
| 669 | 795 | ||
| 670 | /* | 796 | /* |
| @@ -672,16 +798,20 @@ | |||
| 672 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | 798 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER |
| 673 | */ | 799 | */ |
| 674 | #define AM33XX_ST_MN_BYPASS_SHIFT 8 | 800 | #define AM33XX_ST_MN_BYPASS_SHIFT 8 |
| 801 | #define AM33XX_ST_MN_BYPASS_WIDTH 1 | ||
| 675 | #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) | 802 | #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) |
| 676 | 803 | ||
| 677 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | 804 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ |
| 678 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 | 805 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 |
| 679 | #define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) | 806 | #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 |
| 807 | #define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) | ||
| 680 | 808 | ||
| 681 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | 809 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ |
| 682 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 | 810 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 |
| 683 | #define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) | 811 | #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 |
| 812 | #define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) | ||
| 684 | 813 | ||
| 685 | /* Used by CONTROL_SEC_CLK_CTRL */ | 814 | /* Used by CONTROL_SEC_CLK_CTRL */ |
| 815 | #define AM33XX_TIMER0_CLKSEL_WIDTH 2 | ||
| 686 | #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) | 816 | #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) |
| 687 | #endif | 817 | #endif |
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index c1a5cab0f236..5594b42372ee 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h | |||
| @@ -354,6 +354,7 @@ | |||
| 354 | 354 | ||
| 355 | /* AM33XX CONTROL_STATUS bitfields (partial) */ | 355 | /* AM33XX CONTROL_STATUS bitfields (partial) */ |
| 356 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 | 356 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 |
| 357 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH 0x2 | ||
| 357 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) | 358 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) |
| 358 | 359 | ||
| 359 | /* CONTROL OMAP STATUS register to identify OMAP3 features */ | 360 | /* CONTROL OMAP STATUS register to identify OMAP3 features */ |