diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/m32r/kernel/irq.c | 10 | ||||
-rw-r--r-- | arch/m32r/platforms/m32104ut/setup.c | 20 | ||||
-rw-r--r-- | arch/m32r/platforms/m32700ut/setup.c | 74 | ||||
-rw-r--r-- | arch/m32r/platforms/mappi/setup.c | 41 | ||||
-rw-r--r-- | arch/m32r/platforms/mappi2/setup.c | 50 | ||||
-rw-r--r-- | arch/m32r/platforms/mappi3/setup.c | 50 | ||||
-rw-r--r-- | arch/m32r/platforms/oaks32r/setup.c | 30 | ||||
-rw-r--r-- | arch/m32r/platforms/opsput/setup.c | 70 | ||||
-rw-r--r-- | arch/m32r/platforms/usrv/setup.c | 45 |
9 files changed, 83 insertions, 307 deletions
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c index 7db26f1f082d..f745c1287f3a 100644 --- a/arch/m32r/kernel/irq.c +++ b/arch/m32r/kernel/irq.c | |||
@@ -40,8 +40,10 @@ int show_interrupts(struct seq_file *p, void *v) | |||
40 | } | 40 | } |
41 | 41 | ||
42 | if (i < NR_IRQS) { | 42 | if (i < NR_IRQS) { |
43 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | 43 | struct irq_desc *desc = irq_to_desc(i); |
44 | action = irq_desc[i].action; | 44 | |
45 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
46 | action = desc->action; | ||
45 | if (!action) | 47 | if (!action) |
46 | goto skip; | 48 | goto skip; |
47 | seq_printf(p, "%3d: ",i); | 49 | seq_printf(p, "%3d: ",i); |
@@ -51,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
51 | for_each_online_cpu(j) | 53 | for_each_online_cpu(j) |
52 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | 54 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); |
53 | #endif | 55 | #endif |
54 | seq_printf(p, " %14s", irq_desc[i].chip->name); | 56 | seq_printf(p, " %14s", desc->irq_data.chip->name); |
55 | seq_printf(p, " %s", action->name); | 57 | seq_printf(p, " %s", action->name); |
56 | 58 | ||
57 | for (action=action->next; action; action = action->next) | 59 | for (action=action->next; action; action = action->next) |
@@ -59,7 +61,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
59 | 61 | ||
60 | seq_putc(p, '\n'); | 62 | seq_putc(p, '\n'); |
61 | skip: | 63 | skip: |
62 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | 64 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
63 | } | 65 | } |
64 | return 0; | 66 | return 0; |
65 | } | 67 | } |
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c index 402a59d7219b..962f38e58acc 100644 --- a/arch/m32r/platforms/m32104ut/setup.c +++ b/arch/m32r/platforms/m32104ut/setup.c | |||
@@ -85,36 +85,24 @@ void __init init_IRQ(void) | |||
85 | 85 | ||
86 | #if defined(CONFIG_SMC91X) | 86 | #if defined(CONFIG_SMC91X) |
87 | /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ | 87 | /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ |
88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 88 | set_irq_chip(M32R_IRQ_INT0, &m32104ut_irq_type); |
89 | irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; | ||
90 | irq_desc[M32R_IRQ_INT0].action = 0; | ||
91 | irq_desc[M32R_IRQ_INT0].depth = 1; | ||
92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ | 89 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ |
93 | disable_m32104ut_irq(M32R_IRQ_INT0); | 90 | disable_m32104ut_irq(M32R_IRQ_INT0); |
94 | #endif /* CONFIG_SMC91X */ | 91 | #endif /* CONFIG_SMC91X */ |
95 | 92 | ||
96 | /* MFT2 : system timer */ | 93 | /* MFT2 : system timer */ |
97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 94 | set_irq_chip(M32R_IRQ_MFT2, &m32104ut_irq_type); |
98 | irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; | ||
99 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
100 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 95 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
102 | disable_m32104ut_irq(M32R_IRQ_MFT2); | 96 | disable_m32104ut_irq(M32R_IRQ_MFT2); |
103 | 97 | ||
104 | #ifdef CONFIG_SERIAL_M32R_SIO | 98 | #ifdef CONFIG_SERIAL_M32R_SIO |
105 | /* SIO0_R : uart receive data */ | 99 | /* SIO0_R : uart receive data */ |
106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 100 | set_irq_chip(M32R_IRQ_SIO0_R, &m32104ut_irq_type); |
107 | irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; | ||
108 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
110 | icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; | 101 | icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; |
111 | disable_m32104ut_irq(M32R_IRQ_SIO0_R); | 102 | disable_m32104ut_irq(M32R_IRQ_SIO0_R); |
112 | 103 | ||
113 | /* SIO0_S : uart send data */ | 104 | /* SIO0_S : uart send data */ |
114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 105 | set_irq_chip(M32R_IRQ_SIO0_S, &m32104ut_irq_type); |
115 | irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; | ||
116 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
118 | icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; | 106 | icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; |
119 | disable_m32104ut_irq(M32R_IRQ_SIO0_S); | 107 | disable_m32104ut_irq(M32R_IRQ_SIO0_S); |
120 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 108 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c index 80b1a026795a..433bcbca2c3a 100644 --- a/arch/m32r/platforms/m32700ut/setup.c +++ b/arch/m32r/platforms/m32700ut/setup.c | |||
@@ -299,101 +299,65 @@ void __init init_IRQ(void) | |||
299 | { | 299 | { |
300 | #if defined(CONFIG_SMC91X) | 300 | #if defined(CONFIG_SMC91X) |
301 | /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ | 301 | /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ |
302 | irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; | 302 | set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type); |
303 | irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type; | ||
304 | irq_desc[M32700UT_LAN_IRQ_LAN].action = 0; | ||
305 | irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ | ||
306 | lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ | 303 | lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
307 | disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); | 304 | disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); |
308 | #endif /* CONFIG_SMC91X */ | 305 | #endif /* CONFIG_SMC91X */ |
309 | 306 | ||
310 | /* MFT2 : system timer */ | 307 | /* MFT2 : system timer */ |
311 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 308 | set_irq_chip(M32R_IRQ_MFT2, &m32700ut_irq_type); |
312 | irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type; | ||
313 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
314 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
315 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 309 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
316 | disable_m32700ut_irq(M32R_IRQ_MFT2); | 310 | disable_m32700ut_irq(M32R_IRQ_MFT2); |
317 | 311 | ||
318 | /* SIO0 : receive */ | 312 | /* SIO0 : receive */ |
319 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 313 | set_irq_chip(M32R_IRQ_SIO0_R, &m32700ut_irq_type); |
320 | irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type; | ||
321 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
322 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
323 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 314 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
324 | disable_m32700ut_irq(M32R_IRQ_SIO0_R); | 315 | disable_m32700ut_irq(M32R_IRQ_SIO0_R); |
325 | 316 | ||
326 | /* SIO0 : send */ | 317 | /* SIO0 : send */ |
327 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 318 | set_irq_chip(M32R_IRQ_SIO0_S, &m32700ut_irq_type); |
328 | irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type; | ||
329 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
330 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
331 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 319 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
332 | disable_m32700ut_irq(M32R_IRQ_SIO0_S); | 320 | disable_m32700ut_irq(M32R_IRQ_SIO0_S); |
333 | 321 | ||
334 | /* SIO1 : receive */ | 322 | /* SIO1 : receive */ |
335 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 323 | set_irq_chip(M32R_IRQ_SIO1_R, &m32700ut_irq_type); |
336 | irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type; | ||
337 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
338 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
339 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 324 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
340 | disable_m32700ut_irq(M32R_IRQ_SIO1_R); | 325 | disable_m32700ut_irq(M32R_IRQ_SIO1_R); |
341 | 326 | ||
342 | /* SIO1 : send */ | 327 | /* SIO1 : send */ |
343 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 328 | set_irq_chip(M32R_IRQ_SIO1_S, &m32700ut_irq_type); |
344 | irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type; | ||
345 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
346 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
347 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 329 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
348 | disable_m32700ut_irq(M32R_IRQ_SIO1_S); | 330 | disable_m32700ut_irq(M32R_IRQ_SIO1_S); |
349 | 331 | ||
350 | /* DMA1 : */ | 332 | /* DMA1 : */ |
351 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; | 333 | set_irq_chip(M32R_IRQ_DMA1, &m32700ut_irq_type); |
352 | irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type; | ||
353 | irq_desc[M32R_IRQ_DMA1].action = 0; | ||
354 | irq_desc[M32R_IRQ_DMA1].depth = 1; | ||
355 | icu_data[M32R_IRQ_DMA1].icucr = 0; | 334 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
356 | disable_m32700ut_irq(M32R_IRQ_DMA1); | 335 | disable_m32700ut_irq(M32R_IRQ_DMA1); |
357 | 336 | ||
358 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | 337 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
359 | /* INT#1: SIO0 Receive on PLD */ | 338 | /* INT#1: SIO0 Receive on PLD */ |
360 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; | 339 | set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type); |
361 | irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type; | ||
362 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; | ||
363 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ | ||
364 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 340 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
365 | disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); | 341 | disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); |
366 | 342 | ||
367 | /* INT#1: SIO0 Send on PLD */ | 343 | /* INT#1: SIO0 Send on PLD */ |
368 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; | 344 | set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type); |
369 | irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type; | ||
370 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; | ||
371 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ | ||
372 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 345 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
373 | disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); | 346 | disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); |
374 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ | 347 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ |
375 | 348 | ||
376 | /* INT#1: CFC IREQ on PLD */ | 349 | /* INT#1: CFC IREQ on PLD */ |
377 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 350 | set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type); |
378 | irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type; | ||
379 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | ||
380 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | ||
381 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 351 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
382 | disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); | 352 | disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); |
383 | 353 | ||
384 | /* INT#1: CFC Insert on PLD */ | 354 | /* INT#1: CFC Insert on PLD */ |
385 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 355 | set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type); |
386 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type; | ||
387 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | ||
388 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | ||
389 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ | 356 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
390 | disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); | 357 | disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); |
391 | 358 | ||
392 | /* INT#1: CFC Eject on PLD */ | 359 | /* INT#1: CFC Eject on PLD */ |
393 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; | 360 | set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type); |
394 | irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type; | ||
395 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; | ||
396 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ | ||
397 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ | 361 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
398 | disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); | 362 | disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); |
399 | 363 | ||
@@ -413,13 +377,10 @@ void __init init_IRQ(void) | |||
413 | 377 | ||
414 | #if defined(CONFIG_USB) | 378 | #if defined(CONFIG_USB) |
415 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ | 379 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
380 | set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type); | ||
416 | 381 | ||
417 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; | 382 | lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
418 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type; | 383 | disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); |
419 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; | ||
420 | irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; | ||
421 | lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ | ||
422 | disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1); | ||
423 | #endif | 384 | #endif |
424 | /* | 385 | /* |
425 | * INT2# is used for BAT, USB, AUDIO | 386 | * INT2# is used for BAT, USB, AUDIO |
@@ -432,10 +393,7 @@ void __init init_IRQ(void) | |||
432 | /* | 393 | /* |
433 | * INT3# is used for AR | 394 | * INT3# is used for AR |
434 | */ | 395 | */ |
435 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 396 | set_irq_chip(M32R_IRQ_INT3, &m32700ut_irq_type); |
436 | irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type; | ||
437 | irq_desc[M32R_IRQ_INT3].action = 0; | ||
438 | irq_desc[M32R_IRQ_INT3].depth = 1; | ||
439 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 397 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
440 | disable_m32700ut_irq(M32R_IRQ_INT3); | 398 | disable_m32700ut_irq(M32R_IRQ_INT3); |
441 | #endif /* CONFIG_VIDEO_M32R_AR */ | 399 | #endif /* CONFIG_VIDEO_M32R_AR */ |
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index ea00c84d6b1b..bc3fdaf21ca2 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c | |||
@@ -45,7 +45,6 @@ static void mask_and_ack_mappi(unsigned int irq) | |||
45 | 45 | ||
46 | static void end_mappi_irq(unsigned int irq) | 46 | static void end_mappi_irq(unsigned int irq) |
47 | { | 47 | { |
48 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | ||
49 | enable_mappi_irq(irq); | 48 | enable_mappi_irq(irq); |
50 | } | 49 | } |
51 | 50 | ||
@@ -85,70 +84,46 @@ void __init init_IRQ(void) | |||
85 | 84 | ||
86 | #ifdef CONFIG_NE2000 | 85 | #ifdef CONFIG_NE2000 |
87 | /* INT0 : LAN controller (RTL8019AS) */ | 86 | /* INT0 : LAN controller (RTL8019AS) */ |
88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 87 | set_irq_chip(M32R_IRQ_INT0, &mappi_irq_type); |
89 | irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; | ||
90 | irq_desc[M32R_IRQ_INT0].action = NULL; | ||
91 | irq_desc[M32R_IRQ_INT0].depth = 1; | ||
92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; | 88 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; |
93 | disable_mappi_irq(M32R_IRQ_INT0); | 89 | disable_mappi_irq(M32R_IRQ_INT0); |
94 | #endif /* CONFIG_M32R_NE2000 */ | 90 | #endif /* CONFIG_M32R_NE2000 */ |
95 | 91 | ||
96 | /* MFT2 : system timer */ | 92 | /* MFT2 : system timer */ |
97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 93 | set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); |
98 | irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; | ||
99 | irq_desc[M32R_IRQ_MFT2].action = NULL; | ||
100 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 94 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
102 | disable_mappi_irq(M32R_IRQ_MFT2); | 95 | disable_mappi_irq(M32R_IRQ_MFT2); |
103 | 96 | ||
104 | #ifdef CONFIG_SERIAL_M32R_SIO | 97 | #ifdef CONFIG_SERIAL_M32R_SIO |
105 | /* SIO0_R : uart receive data */ | 98 | /* SIO0_R : uart receive data */ |
106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 99 | set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); |
107 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; | ||
108 | irq_desc[M32R_IRQ_SIO0_R].action = NULL; | ||
109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
110 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 100 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
111 | disable_mappi_irq(M32R_IRQ_SIO0_R); | 101 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
112 | 102 | ||
113 | /* SIO0_S : uart send data */ | 103 | /* SIO0_S : uart send data */ |
114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 104 | set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); |
115 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; | ||
116 | irq_desc[M32R_IRQ_SIO0_S].action = NULL; | ||
117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
118 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 105 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
119 | disable_mappi_irq(M32R_IRQ_SIO0_S); | 106 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
120 | 107 | ||
121 | /* SIO1_R : uart receive data */ | 108 | /* SIO1_R : uart receive data */ |
122 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 109 | set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); |
123 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; | ||
124 | irq_desc[M32R_IRQ_SIO1_R].action = NULL; | ||
125 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
126 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 110 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
127 | disable_mappi_irq(M32R_IRQ_SIO1_R); | 111 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
128 | 112 | ||
129 | /* SIO1_S : uart send data */ | 113 | /* SIO1_S : uart send data */ |
130 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 114 | set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); |
131 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; | ||
132 | irq_desc[M32R_IRQ_SIO1_S].action = NULL; | ||
133 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
134 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 115 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
135 | disable_mappi_irq(M32R_IRQ_SIO1_S); | 116 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
136 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 117 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
137 | 118 | ||
138 | #if defined(CONFIG_M32R_PCC) | 119 | #if defined(CONFIG_M32R_PCC) |
139 | /* INT1 : pccard0 interrupt */ | 120 | /* INT1 : pccard0 interrupt */ |
140 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; | 121 | set_irq_chip(M32R_IRQ_INT1, &mappi_irq_type); |
141 | irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; | ||
142 | irq_desc[M32R_IRQ_INT1].action = NULL; | ||
143 | irq_desc[M32R_IRQ_INT1].depth = 1; | ||
144 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 122 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
145 | disable_mappi_irq(M32R_IRQ_INT1); | 123 | disable_mappi_irq(M32R_IRQ_INT1); |
146 | 124 | ||
147 | /* INT2 : pccard1 interrupt */ | 125 | /* INT2 : pccard1 interrupt */ |
148 | irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; | 126 | set_irq_chip(M32R_IRQ_INT2, &mappi_irq_type); |
149 | irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; | ||
150 | irq_desc[M32R_IRQ_INT2].action = NULL; | ||
151 | irq_desc[M32R_IRQ_INT2].depth = 1; | ||
152 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 127 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
153 | disable_mappi_irq(M32R_IRQ_INT2); | 128 | disable_mappi_irq(M32R_IRQ_INT2); |
154 | #endif /* CONFIG_M32RPCC */ | 129 | #endif /* CONFIG_M32RPCC */ |
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c index c049376d0270..87bba1e01719 100644 --- a/arch/m32r/platforms/mappi2/setup.c +++ b/arch/m32r/platforms/mappi2/setup.c | |||
@@ -85,87 +85,57 @@ void __init init_IRQ(void) | |||
85 | { | 85 | { |
86 | #if defined(CONFIG_SMC91X) | 86 | #if defined(CONFIG_SMC91X) |
87 | /* INT0 : LAN controller (SMC91111) */ | 87 | /* INT0 : LAN controller (SMC91111) */ |
88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 88 | set_irq_chip(M32R_IRQ_INT0, &mappi2_irq_type); |
89 | irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; | ||
90 | irq_desc[M32R_IRQ_INT0].action = 0; | ||
91 | irq_desc[M32R_IRQ_INT0].depth = 1; | ||
92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 89 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
93 | disable_mappi2_irq(M32R_IRQ_INT0); | 90 | disable_mappi2_irq(M32R_IRQ_INT0); |
94 | #endif /* CONFIG_SMC91X */ | 91 | #endif /* CONFIG_SMC91X */ |
95 | 92 | ||
96 | /* MFT2 : system timer */ | 93 | /* MFT2 : system timer */ |
97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 94 | set_irq_chip(M32R_IRQ_MFT2, &mappi2_irq_type); |
98 | irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; | ||
99 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
100 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 95 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
102 | disable_mappi2_irq(M32R_IRQ_MFT2); | 96 | disable_mappi2_irq(M32R_IRQ_MFT2); |
103 | 97 | ||
104 | #ifdef CONFIG_SERIAL_M32R_SIO | 98 | #ifdef CONFIG_SERIAL_M32R_SIO |
105 | /* SIO0_R : uart receive data */ | 99 | /* SIO0_R : uart receive data */ |
106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 100 | set_irq_chip(M32R_IRQ_SIO0_R, &mappi2_irq_type); |
107 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; | ||
108 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
110 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 101 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
111 | disable_mappi2_irq(M32R_IRQ_SIO0_R); | 102 | disable_mappi2_irq(M32R_IRQ_SIO0_R); |
112 | 103 | ||
113 | /* SIO0_S : uart send data */ | 104 | /* SIO0_S : uart send data */ |
114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 105 | set_irq_chip(M32R_IRQ_SIO0_S, &mappi2_irq_type); |
115 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; | ||
116 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
118 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 106 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
119 | disable_mappi2_irq(M32R_IRQ_SIO0_S); | 107 | disable_mappi2_irq(M32R_IRQ_SIO0_S); |
120 | /* SIO1_R : uart receive data */ | 108 | /* SIO1_R : uart receive data */ |
121 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 109 | set_irq_chip(M32R_IRQ_SIO1_R, &mappi2_irq_type); |
122 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; | ||
123 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
124 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
125 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 110 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
126 | disable_mappi2_irq(M32R_IRQ_SIO1_R); | 111 | disable_mappi2_irq(M32R_IRQ_SIO1_R); |
127 | 112 | ||
128 | /* SIO1_S : uart send data */ | 113 | /* SIO1_S : uart send data */ |
129 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 114 | set_irq_chip(M32R_IRQ_SIO1_S, &mappi2_irq_type); |
130 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; | ||
131 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
132 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
133 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 115 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
134 | disable_mappi2_irq(M32R_IRQ_SIO1_S); | 116 | disable_mappi2_irq(M32R_IRQ_SIO1_S); |
135 | #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ | 117 | #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ |
136 | 118 | ||
137 | #if defined(CONFIG_USB) | 119 | #if defined(CONFIG_USB) |
138 | /* INT1 : USB Host controller interrupt */ | 120 | /* INT1 : USB Host controller interrupt */ |
139 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; | 121 | set_irq_chip(M32R_IRQ_INT1, &mappi2_irq_type); |
140 | irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; | ||
141 | irq_desc[M32R_IRQ_INT1].action = 0; | ||
142 | irq_desc[M32R_IRQ_INT1].depth = 1; | ||
143 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; | 122 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
144 | disable_mappi2_irq(M32R_IRQ_INT1); | 123 | disable_mappi2_irq(M32R_IRQ_INT1); |
145 | #endif /* CONFIG_USB */ | 124 | #endif /* CONFIG_USB */ |
146 | 125 | ||
147 | /* ICUCR40: CFC IREQ */ | 126 | /* ICUCR40: CFC IREQ */ |
148 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 127 | set_irq_chip(PLD_IRQ_CFIREQ, &mappi2_irq_type); |
149 | irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; | ||
150 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | ||
151 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | ||
152 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; | 128 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
153 | disable_mappi2_irq(PLD_IRQ_CFIREQ); | 129 | disable_mappi2_irq(PLD_IRQ_CFIREQ); |
154 | 130 | ||
155 | #if defined(CONFIG_M32R_CFC) | 131 | #if defined(CONFIG_M32R_CFC) |
156 | /* ICUCR41: CFC Insert */ | 132 | /* ICUCR41: CFC Insert */ |
157 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 133 | set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi2_irq_type); |
158 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; | ||
159 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | ||
160 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | ||
161 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; | 134 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
162 | disable_mappi2_irq(PLD_IRQ_CFC_INSERT); | 135 | disable_mappi2_irq(PLD_IRQ_CFC_INSERT); |
163 | 136 | ||
164 | /* ICUCR42: CFC Eject */ | 137 | /* ICUCR42: CFC Eject */ |
165 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; | 138 | set_irq_chip(PLD_IRQ_CFC_EJECT, &mappi2_irq_type); |
166 | irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; | ||
167 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; | ||
168 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ | ||
169 | icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 139 | icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
170 | disable_mappi2_irq(PLD_IRQ_CFC_EJECT); | 140 | disable_mappi2_irq(PLD_IRQ_CFC_EJECT); |
171 | #endif /* CONFIG_MAPPI2_CFC */ | 141 | #endif /* CONFIG_MAPPI2_CFC */ |
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c index 882de25c6e8c..74098142cb2c 100644 --- a/arch/m32r/platforms/mappi3/setup.c +++ b/arch/m32r/platforms/mappi3/setup.c | |||
@@ -85,89 +85,59 @@ void __init init_IRQ(void) | |||
85 | { | 85 | { |
86 | #if defined(CONFIG_SMC91X) | 86 | #if defined(CONFIG_SMC91X) |
87 | /* INT0 : LAN controller (SMC91111) */ | 87 | /* INT0 : LAN controller (SMC91111) */ |
88 | irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; | 88 | set_irq_chip(M32R_IRQ_INT0, &mappi3_irq_type); |
89 | irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; | ||
90 | irq_desc[M32R_IRQ_INT0].action = 0; | ||
91 | irq_desc[M32R_IRQ_INT0].depth = 1; | ||
92 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 89 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
93 | disable_mappi3_irq(M32R_IRQ_INT0); | 90 | disable_mappi3_irq(M32R_IRQ_INT0); |
94 | #endif /* CONFIG_SMC91X */ | 91 | #endif /* CONFIG_SMC91X */ |
95 | 92 | ||
96 | /* MFT2 : system timer */ | 93 | /* MFT2 : system timer */ |
97 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 94 | set_irq_chip(M32R_IRQ_MFT2, &mappi3_irq_type); |
98 | irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; | ||
99 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
100 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
101 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 95 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
102 | disable_mappi3_irq(M32R_IRQ_MFT2); | 96 | disable_mappi3_irq(M32R_IRQ_MFT2); |
103 | 97 | ||
104 | #ifdef CONFIG_SERIAL_M32R_SIO | 98 | #ifdef CONFIG_SERIAL_M32R_SIO |
105 | /* SIO0_R : uart receive data */ | 99 | /* SIO0_R : uart receive data */ |
106 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 100 | set_irq_chip(M32R_IRQ_SIO0_R, &mappi3_irq_type); |
107 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; | ||
108 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
109 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
110 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 101 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
111 | disable_mappi3_irq(M32R_IRQ_SIO0_R); | 102 | disable_mappi3_irq(M32R_IRQ_SIO0_R); |
112 | 103 | ||
113 | /* SIO0_S : uart send data */ | 104 | /* SIO0_S : uart send data */ |
114 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 105 | set_irq_chip(M32R_IRQ_SIO0_S, &mappi3_irq_type); |
115 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; | ||
116 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
117 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
118 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 106 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
119 | disable_mappi3_irq(M32R_IRQ_SIO0_S); | 107 | disable_mappi3_irq(M32R_IRQ_SIO0_S); |
120 | /* SIO1_R : uart receive data */ | 108 | /* SIO1_R : uart receive data */ |
121 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 109 | set_irq_chip(M32R_IRQ_SIO1_R, &mappi3_irq_type); |
122 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; | ||
123 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
124 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
125 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 110 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
126 | disable_mappi3_irq(M32R_IRQ_SIO1_R); | 111 | disable_mappi3_irq(M32R_IRQ_SIO1_R); |
127 | 112 | ||
128 | /* SIO1_S : uart send data */ | 113 | /* SIO1_S : uart send data */ |
129 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 114 | set_irq_chip(M32R_IRQ_SIO1_S, &mappi3_irq_type); |
130 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; | ||
131 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
132 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
133 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 115 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
134 | disable_mappi3_irq(M32R_IRQ_SIO1_S); | 116 | disable_mappi3_irq(M32R_IRQ_SIO1_S); |
135 | #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ | 117 | #endif /* CONFIG_M32R_USE_DBG_CONSOLE */ |
136 | 118 | ||
137 | #if defined(CONFIG_USB) | 119 | #if defined(CONFIG_USB) |
138 | /* INT1 : USB Host controller interrupt */ | 120 | /* INT1 : USB Host controller interrupt */ |
139 | irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; | 121 | set_irq_chip(M32R_IRQ_INT1, &mappi3_irq_type); |
140 | irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; | ||
141 | irq_desc[M32R_IRQ_INT1].action = 0; | ||
142 | irq_desc[M32R_IRQ_INT1].depth = 1; | ||
143 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; | 122 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; |
144 | disable_mappi3_irq(M32R_IRQ_INT1); | 123 | disable_mappi3_irq(M32R_IRQ_INT1); |
145 | #endif /* CONFIG_USB */ | 124 | #endif /* CONFIG_USB */ |
146 | 125 | ||
147 | /* CFC IREQ */ | 126 | /* CFC IREQ */ |
148 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 127 | set_irq_chip(PLD_IRQ_CFIREQ, &mappi3_irq_type); |
149 | irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; | ||
150 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | ||
151 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | ||
152 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; | 128 | icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; |
153 | disable_mappi3_irq(PLD_IRQ_CFIREQ); | 129 | disable_mappi3_irq(PLD_IRQ_CFIREQ); |
154 | 130 | ||
155 | #if defined(CONFIG_M32R_CFC) | 131 | #if defined(CONFIG_M32R_CFC) |
156 | /* ICUCR41: CFC Insert & eject */ | 132 | /* ICUCR41: CFC Insert & eject */ |
157 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 133 | set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi3_irq_type); |
158 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; | ||
159 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | ||
160 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | ||
161 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; | 134 | icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; |
162 | disable_mappi3_irq(PLD_IRQ_CFC_INSERT); | 135 | disable_mappi3_irq(PLD_IRQ_CFC_INSERT); |
163 | 136 | ||
164 | #endif /* CONFIG_M32R_CFC */ | 137 | #endif /* CONFIG_M32R_CFC */ |
165 | 138 | ||
166 | /* IDE IREQ */ | 139 | /* IDE IREQ */ |
167 | irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; | 140 | set_irq_chip(PLD_IRQ_IDEIREQ, &mappi3_irq_type); |
168 | irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; | ||
169 | irq_desc[PLD_IRQ_IDEIREQ].action = 0; | ||
170 | irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */ | ||
171 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 141 | icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
172 | disable_mappi3_irq(PLD_IRQ_IDEIREQ); | 142 | disable_mappi3_irq(PLD_IRQ_IDEIREQ); |
173 | 143 | ||
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index d11d93bf74f5..43bf5a0c9515 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c | |||
@@ -83,52 +83,34 @@ void __init init_IRQ(void) | |||
83 | 83 | ||
84 | #ifdef CONFIG_NE2000 | 84 | #ifdef CONFIG_NE2000 |
85 | /* INT3 : LAN controller (RTL8019AS) */ | 85 | /* INT3 : LAN controller (RTL8019AS) */ |
86 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 86 | set_irq_chip(M32R_IRQ_INT3, &oaks32r_irq_type); |
87 | irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; | ||
88 | irq_desc[M32R_IRQ_INT3].action = 0; | ||
89 | irq_desc[M32R_IRQ_INT3].depth = 1; | ||
90 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 87 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
91 | disable_oaks32r_irq(M32R_IRQ_INT3); | 88 | disable_oaks32r_irq(M32R_IRQ_INT3); |
92 | #endif /* CONFIG_M32R_NE2000 */ | 89 | #endif /* CONFIG_M32R_NE2000 */ |
93 | 90 | ||
94 | /* MFT2 : system timer */ | 91 | /* MFT2 : system timer */ |
95 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 92 | set_irq_chip(M32R_IRQ_MFT2, &oaks32r_irq_type); |
96 | irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; | ||
97 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
98 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
99 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 93 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
100 | disable_oaks32r_irq(M32R_IRQ_MFT2); | 94 | disable_oaks32r_irq(M32R_IRQ_MFT2); |
101 | 95 | ||
102 | #ifdef CONFIG_SERIAL_M32R_SIO | 96 | #ifdef CONFIG_SERIAL_M32R_SIO |
103 | /* SIO0_R : uart receive data */ | 97 | /* SIO0_R : uart receive data */ |
104 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 98 | set_irq_chip(M32R_IRQ_SIO0_R, &oaks32r_irq_type); |
105 | irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; | ||
106 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
107 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
108 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 99 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
109 | disable_oaks32r_irq(M32R_IRQ_SIO0_R); | 100 | disable_oaks32r_irq(M32R_IRQ_SIO0_R); |
110 | 101 | ||
111 | /* SIO0_S : uart send data */ | 102 | /* SIO0_S : uart send data */ |
112 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 103 | set_irq_chip(M32R_IRQ_SIO0_S, &oaks32r_irq_type); |
113 | irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; | ||
114 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
115 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
116 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 104 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
117 | disable_oaks32r_irq(M32R_IRQ_SIO0_S); | 105 | disable_oaks32r_irq(M32R_IRQ_SIO0_S); |
118 | 106 | ||
119 | /* SIO1_R : uart receive data */ | 107 | /* SIO1_R : uart receive data */ |
120 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 108 | set_irq_chip(M32R_IRQ_SIO1_R, &oaks32r_irq_type); |
121 | irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; | ||
122 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
123 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
124 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 109 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
125 | disable_oaks32r_irq(M32R_IRQ_SIO1_R); | 110 | disable_oaks32r_irq(M32R_IRQ_SIO1_R); |
126 | 111 | ||
127 | /* SIO1_S : uart send data */ | 112 | /* SIO1_S : uart send data */ |
128 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 113 | set_irq_chip(M32R_IRQ_SIO1_S, &oaks32r_irq_type); |
129 | irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; | ||
130 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
131 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
132 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 114 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
133 | disable_oaks32r_irq(M32R_IRQ_SIO1_S); | 115 | disable_oaks32r_irq(M32R_IRQ_SIO1_S); |
134 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 116 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c index 5f3402a2fbaf..a16a7fe0e6f9 100644 --- a/arch/m32r/platforms/opsput/setup.c +++ b/arch/m32r/platforms/opsput/setup.c | |||
@@ -300,101 +300,65 @@ void __init init_IRQ(void) | |||
300 | { | 300 | { |
301 | #if defined(CONFIG_SMC91X) | 301 | #if defined(CONFIG_SMC91X) |
302 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ | 302 | /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ |
303 | irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; | 303 | set_irq_chip(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type); |
304 | irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; | ||
305 | irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; | ||
306 | irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ | ||
307 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ | 304 | lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ |
308 | disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); | 305 | disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); |
309 | #endif /* CONFIG_SMC91X */ | 306 | #endif /* CONFIG_SMC91X */ |
310 | 307 | ||
311 | /* MFT2 : system timer */ | 308 | /* MFT2 : system timer */ |
312 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 309 | set_irq_chip(M32R_IRQ_MFT2, &opsput_irq_type); |
313 | irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; | ||
314 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
315 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
316 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 310 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
317 | disable_opsput_irq(M32R_IRQ_MFT2); | 311 | disable_opsput_irq(M32R_IRQ_MFT2); |
318 | 312 | ||
319 | /* SIO0 : receive */ | 313 | /* SIO0 : receive */ |
320 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 314 | set_irq_chip(M32R_IRQ_SIO0_R, &opsput_irq_type); |
321 | irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; | ||
322 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
323 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
324 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 315 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
325 | disable_opsput_irq(M32R_IRQ_SIO0_R); | 316 | disable_opsput_irq(M32R_IRQ_SIO0_R); |
326 | 317 | ||
327 | /* SIO0 : send */ | 318 | /* SIO0 : send */ |
328 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 319 | set_irq_chip(M32R_IRQ_SIO0_S, &opsput_irq_type); |
329 | irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; | ||
330 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
331 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
332 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 320 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
333 | disable_opsput_irq(M32R_IRQ_SIO0_S); | 321 | disable_opsput_irq(M32R_IRQ_SIO0_S); |
334 | 322 | ||
335 | /* SIO1 : receive */ | 323 | /* SIO1 : receive */ |
336 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 324 | set_irq_chip(M32R_IRQ_SIO1_R, &opsput_irq_type); |
337 | irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; | ||
338 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
339 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
340 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 325 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
341 | disable_opsput_irq(M32R_IRQ_SIO1_R); | 326 | disable_opsput_irq(M32R_IRQ_SIO1_R); |
342 | 327 | ||
343 | /* SIO1 : send */ | 328 | /* SIO1 : send */ |
344 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 329 | set_irq_chip(M32R_IRQ_SIO1_S, &opsput_irq_type); |
345 | irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; | ||
346 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
347 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
348 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 330 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
349 | disable_opsput_irq(M32R_IRQ_SIO1_S); | 331 | disable_opsput_irq(M32R_IRQ_SIO1_S); |
350 | 332 | ||
351 | /* DMA1 : */ | 333 | /* DMA1 : */ |
352 | irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; | 334 | set_irq_chip(M32R_IRQ_DMA1, &opsput_irq_type); |
353 | irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; | ||
354 | irq_desc[M32R_IRQ_DMA1].action = 0; | ||
355 | irq_desc[M32R_IRQ_DMA1].depth = 1; | ||
356 | icu_data[M32R_IRQ_DMA1].icucr = 0; | 335 | icu_data[M32R_IRQ_DMA1].icucr = 0; |
357 | disable_opsput_irq(M32R_IRQ_DMA1); | 336 | disable_opsput_irq(M32R_IRQ_DMA1); |
358 | 337 | ||
359 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | 338 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
360 | /* INT#1: SIO0 Receive on PLD */ | 339 | /* INT#1: SIO0 Receive on PLD */ |
361 | irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; | 340 | set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type); |
362 | irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; | ||
363 | irq_desc[PLD_IRQ_SIO0_RCV].action = 0; | ||
364 | irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ | ||
365 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 341 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
366 | disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); | 342 | disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); |
367 | 343 | ||
368 | /* INT#1: SIO0 Send on PLD */ | 344 | /* INT#1: SIO0 Send on PLD */ |
369 | irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; | 345 | set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type); |
370 | irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; | ||
371 | irq_desc[PLD_IRQ_SIO0_SND].action = 0; | ||
372 | irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ | ||
373 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; | 346 | pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; |
374 | disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); | 347 | disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); |
375 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ | 348 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ |
376 | 349 | ||
377 | /* INT#1: CFC IREQ on PLD */ | 350 | /* INT#1: CFC IREQ on PLD */ |
378 | irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; | 351 | set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type); |
379 | irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; | ||
380 | irq_desc[PLD_IRQ_CFIREQ].action = 0; | ||
381 | irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ | ||
382 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 352 | pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
383 | disable_opsput_pld_irq(PLD_IRQ_CFIREQ); | 353 | disable_opsput_pld_irq(PLD_IRQ_CFIREQ); |
384 | 354 | ||
385 | /* INT#1: CFC Insert on PLD */ | 355 | /* INT#1: CFC Insert on PLD */ |
386 | irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; | 356 | set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type); |
387 | irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; | ||
388 | irq_desc[PLD_IRQ_CFC_INSERT].action = 0; | ||
389 | irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ | ||
390 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ | 357 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ |
391 | disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); | 358 | disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); |
392 | 359 | ||
393 | /* INT#1: CFC Eject on PLD */ | 360 | /* INT#1: CFC Eject on PLD */ |
394 | irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; | 361 | set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type); |
395 | irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; | ||
396 | irq_desc[PLD_IRQ_CFC_EJECT].action = 0; | ||
397 | irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ | ||
398 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ | 362 | pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ |
399 | disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); | 363 | disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); |
400 | 364 | ||
@@ -415,10 +379,7 @@ void __init init_IRQ(void) | |||
415 | #if defined(CONFIG_USB) | 379 | #if defined(CONFIG_USB) |
416 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ | 380 | outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ |
417 | 381 | ||
418 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; | 382 | set_irq_chip(OPSPUT_LCD_IRQ_USB_INT1, &opsput_lcdpld_irq_type); |
419 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; | ||
420 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; | ||
421 | irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; | ||
422 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ | 383 | lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ |
423 | disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); | 384 | disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); |
424 | #endif | 385 | #endif |
@@ -433,10 +394,7 @@ void __init init_IRQ(void) | |||
433 | /* | 394 | /* |
434 | * INT3# is used for AR | 395 | * INT3# is used for AR |
435 | */ | 396 | */ |
436 | irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; | 397 | set_irq_chip(M32R_IRQ_INT3, &opsput_irq_type); |
437 | irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; | ||
438 | irq_desc[M32R_IRQ_INT3].action = 0; | ||
439 | irq_desc[M32R_IRQ_INT3].depth = 1; | ||
440 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; | 398 | icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; |
441 | disable_opsput_irq(M32R_IRQ_INT3); | 399 | disable_opsput_irq(M32R_IRQ_INT3); |
442 | #endif /* CONFIG_VIDEO_M32R_AR */ | 400 | #endif /* CONFIG_VIDEO_M32R_AR */ |
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index 1beac7a51ed4..d6eb586a099e 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c | |||
@@ -156,53 +156,35 @@ void __init init_IRQ(void) | |||
156 | once++; | 156 | once++; |
157 | 157 | ||
158 | /* MFT2 : system timer */ | 158 | /* MFT2 : system timer */ |
159 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 159 | set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); |
160 | irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; | ||
161 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
162 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
163 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 160 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
164 | disable_mappi_irq(M32R_IRQ_MFT2); | 161 | disable_mappi_irq(M32R_IRQ_MFT2); |
165 | 162 | ||
166 | #if defined(CONFIG_SERIAL_M32R_SIO) | 163 | #if defined(CONFIG_SERIAL_M32R_SIO) |
167 | /* SIO0_R : uart receive data */ | 164 | /* SIO0_R : uart receive data */ |
168 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 165 | set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); |
169 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; | ||
170 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
171 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
172 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 166 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
173 | disable_mappi_irq(M32R_IRQ_SIO0_R); | 167 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
174 | 168 | ||
175 | /* SIO0_S : uart send data */ | 169 | /* SIO0_S : uart send data */ |
176 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 170 | set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); |
177 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; | ||
178 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
179 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
180 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 171 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
181 | disable_mappi_irq(M32R_IRQ_SIO0_S); | 172 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
182 | 173 | ||
183 | /* SIO1_R : uart receive data */ | 174 | /* SIO1_R : uart receive data */ |
184 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 175 | set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); |
185 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; | ||
186 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
187 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
188 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 176 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
189 | disable_mappi_irq(M32R_IRQ_SIO1_R); | 177 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
190 | 178 | ||
191 | /* SIO1_S : uart send data */ | 179 | /* SIO1_S : uart send data */ |
192 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 180 | set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); |
193 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; | ||
194 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
195 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
196 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 181 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
197 | disable_mappi_irq(M32R_IRQ_SIO1_S); | 182 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
198 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 183 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
199 | 184 | ||
200 | /* INT#67-#71: CFC#0 IREQ on PLD */ | 185 | /* INT#67-#71: CFC#0 IREQ on PLD */ |
201 | for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { | 186 | for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { |
202 | irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; | 187 | set_irq_chip(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type); |
203 | irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; | ||
204 | irq_desc[PLD_IRQ_CF0 + i].action = 0; | ||
205 | irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */ | ||
206 | pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr | 188 | pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr |
207 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 189 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
208 | disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); | 190 | disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); |
@@ -210,19 +192,13 @@ void __init init_IRQ(void) | |||
210 | 192 | ||
211 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | 193 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
212 | /* INT#76: 16552D#0 IREQ on PLD */ | 194 | /* INT#76: 16552D#0 IREQ on PLD */ |
213 | irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; | 195 | set_irq_chip(PLD_IRQ_UART0, &m32700ut_pld_irq_type); |
214 | irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; | ||
215 | irq_desc[PLD_IRQ_UART0].action = 0; | ||
216 | irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */ | ||
217 | pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr | 196 | pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr |
218 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ | 197 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ |
219 | disable_m32700ut_pld_irq(PLD_IRQ_UART0); | 198 | disable_m32700ut_pld_irq(PLD_IRQ_UART0); |
220 | 199 | ||
221 | /* INT#77: 16552D#1 IREQ on PLD */ | 200 | /* INT#77: 16552D#1 IREQ on PLD */ |
222 | irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; | 201 | set_irq_chip(PLD_IRQ_UART1, &m32700ut_pld_irq_type); |
223 | irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; | ||
224 | irq_desc[PLD_IRQ_UART1].action = 0; | ||
225 | irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */ | ||
226 | pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr | 202 | pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr |
227 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ | 203 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ |
228 | disable_m32700ut_pld_irq(PLD_IRQ_UART1); | 204 | disable_m32700ut_pld_irq(PLD_IRQ_UART1); |
@@ -230,10 +206,7 @@ void __init init_IRQ(void) | |||
230 | 206 | ||
231 | #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) | 207 | #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) |
232 | /* INT#80: AK4524 IREQ on PLD */ | 208 | /* INT#80: AK4524 IREQ on PLD */ |
233 | irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; | 209 | set_irq_chip(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type); |
234 | irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; | ||
235 | irq_desc[PLD_IRQ_SNDINT].action = 0; | ||
236 | irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */ | ||
237 | pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr | 210 | pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr |
238 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 211 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
239 | disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); | 212 | disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); |