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-rw-r--r--arch/mn10300/include/asm/debugger.h8
-rw-r--r--arch/mn10300/kernel/Makefile4
-rw-r--r--arch/mn10300/kernel/entry.S31
-rw-r--r--arch/mn10300/kernel/gdb-cache.S105
-rw-r--r--arch/mn10300/kernel/gdb-stub.c4
-rw-r--r--arch/mn10300/mm/Kconfig.cache46
-rw-r--r--arch/mn10300/mm/Makefile9
-rw-r--r--arch/mn10300/mm/cache-dbg-flush-by-reg.S160
-rw-r--r--arch/mn10300/mm/cache-dbg-flush-by-tag.S114
-rw-r--r--arch/mn10300/mm/cache-dbg-inv-by-reg.S69
-rw-r--r--arch/mn10300/mm/cache-dbg-inv-by-tag.S120
-rw-r--r--arch/mn10300/mm/cache-dbg-inv.S47
-rw-r--r--arch/mn10300/mm/cache-flush-by-tag.S13
-rw-r--r--arch/mn10300/mm/cache-inv-by-reg.S9
-rw-r--r--arch/mn10300/mm/cache-inv-by-tag.S9
-rw-r--r--arch/mn10300/proc-mn103e010/include/proc/cache.h1
-rw-r--r--arch/mn10300/proc-mn2ws0050/include/proc/cache.h1
17 files changed, 592 insertions, 158 deletions
diff --git a/arch/mn10300/include/asm/debugger.h b/arch/mn10300/include/asm/debugger.h
index 4816f0dc28b5..4517f839a999 100644
--- a/arch/mn10300/include/asm/debugger.h
+++ b/arch/mn10300/include/asm/debugger.h
@@ -14,6 +14,14 @@
14 14
15#if defined(CONFIG_KERNEL_DEBUGGER) 15#if defined(CONFIG_KERNEL_DEBUGGER)
16 16
17#ifndef CONFIG_MN10300_DEBUGGER_CACHE_NO_FLUSH
18extern void debugger_local_cache_flushinv(void);
19extern void debugger_local_cache_flushinv_one(u8 *);
20#else
21static inline void debugger_local_cache_flushinv(void) {}
22static inline void debugger_local_cache_flushinv_one(u8 *addr) {}
23#endif
24
17#else /* CONFIG_KERNEL_DEBUGGER */ 25#else /* CONFIG_KERNEL_DEBUGGER */
18 26
19#endif /* CONFIG_KERNEL_DEBUGGER */ 27#endif /* CONFIG_KERNEL_DEBUGGER */
diff --git a/arch/mn10300/kernel/Makefile b/arch/mn10300/kernel/Makefile
index a06a2e10051d..48ab4017434d 100644
--- a/arch/mn10300/kernel/Makefile
+++ b/arch/mn10300/kernel/Makefile
@@ -21,10 +21,6 @@ obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-low.o
21obj-$(CONFIG_GDBSTUB_ON_TTYSx) += gdb-io-serial.o gdb-io-serial-low.o 21obj-$(CONFIG_GDBSTUB_ON_TTYSx) += gdb-io-serial.o gdb-io-serial-low.o
22obj-$(CONFIG_GDBSTUB_ON_TTYSMx) += gdb-io-ttysm.o gdb-io-ttysm-low.o 22obj-$(CONFIG_GDBSTUB_ON_TTYSMx) += gdb-io-ttysm.o gdb-io-ttysm-low.o
23 23
24ifeq ($(CONFIG_MN10300_CACHE_ENABLED),y)
25obj-$(CONFIG_GDBSTUB) += gdb-cache.o
26endif
27
28obj-$(CONFIG_MN10300_RTC) += rtc.o 24obj-$(CONFIG_MN10300_RTC) += rtc.o
29obj-$(CONFIG_PROFILE) += profile.o profile-low.o 25obj-$(CONFIG_PROFILE) += profile.o profile-low.o
30obj-$(CONFIG_MODULES) += module.o 26obj-$(CONFIG_MODULES) += module.o
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
index f00b9bafcd3e..8e79a04f1cb0 100644
--- a/arch/mn10300/kernel/entry.S
+++ b/arch/mn10300/kernel/entry.S
@@ -306,36 +306,7 @@ ENTRY(nmi_handler)
306 movbu d0,(GxICR(GDB_NMI_IPI)) 306 movbu d0,(GxICR(GDB_NMI_IPI))
307 movhu (GxICR(GDB_NMI_IPI)),d0 307 movhu (GxICR(GDB_NMI_IPI)),d0
308 and ~EPSW_NMID,epsw # enable NMI 308 and ~EPSW_NMID,epsw # enable NMI
309#ifdef CONFIG_MN10300_CACHE_ENABLED 309
310 mov (gdbstub_nmi_opr_type),d0
311 cmp GDBSTUB_NMI_CACHE_PURGE,d0
312 bne 4f # if not gdb cache purge, jump
313
314 # gdb cache purge nmi ipi
315 add -20,sp
316 mov d1,(4,sp)
317 mov a0,(8,sp)
318 mov a1,(12,sp)
319 mov mdr,d0
320 mov d0,(16,sp)
321 call gdbstub_local_purge_cache[],0
322 mov 0x1,d0
323 mov (CPUID),d1
324 asl d1,d0
325 mov gdbstub_nmi_cpumask,a0
326 bclr d0,(a0)
327 mov (4,sp),d1
328 mov (8,sp),a0
329 mov (12,sp),a1
330 mov (16,sp),d0
331 mov d0,mdr
332 add 20,sp
333 mov (sp),d0
334 add 4,sp
335 rti
3364:
337#endif /* CONFIG_MN10300_CACHE_ENABLED */
338 # gdb wait nmi ipi
339 mov (sp),d0 310 mov (sp),d0
340 SAVE_ALL 311 SAVE_ALL
341 call gdbstub_nmi_wait[],0 312 call gdbstub_nmi_wait[],0
diff --git a/arch/mn10300/kernel/gdb-cache.S b/arch/mn10300/kernel/gdb-cache.S
deleted file mode 100644
index 1108badc3d32..000000000000
--- a/arch/mn10300/kernel/gdb-cache.S
+++ /dev/null
@@ -1,105 +0,0 @@
1###############################################################################
2#
3# MN10300 Low-level cache purging routines for gdbstub
4#
5# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
6# Written by David Howells (dhowells@redhat.com)
7#
8# This program is free software; you can redistribute it and/or
9# modify it under the terms of the GNU General Public Licence
10# as published by the Free Software Foundation; either version
11# 2 of the Licence, or (at your option) any later version.
12#
13###############################################################################
14#include <linux/sys.h>
15#include <linux/linkage.h>
16#include <asm/smp.h>
17#include <asm/cache.h>
18#include <asm/cpu-regs.h>
19#include <asm/exceptions.h>
20#include <asm/frame.inc>
21#include <asm/serial-regs.h>
22
23 .text
24
25###############################################################################
26#
27# GDB stub cache purge
28#
29###############################################################################
30 .type gdbstub_purge_cache,@function
31ENTRY(gdbstub_purge_cache)
32 #######################################################################
33 # read the addresses tagged in the cache's tag RAM and attempt to flush
34 # those addresses specifically
35 # - we rely on the hardware to filter out invalid tag entry addresses
36 mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
37 mov DCACHE_PURGE(0,0),a1 # dcache purge request address
38 mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries
39
40mn10300_dcache_flush_loop:
41 mov (a0),d0
42 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0
43 or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
44 # cache
45 mov d0,(a1) # conditional purge
46
47mn10300_dcache_flush_skip:
48 add L1_CACHE_BYTES,a0
49 add L1_CACHE_BYTES,a1
50 add -1,d1
51 bne mn10300_dcache_flush_loop
52
53;; # unconditionally flush and invalidate the dcache
54;; mov DCACHE_PURGE(0,0),a1 # dcache purge request address
55;; mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of
56;; # entries
57;;
58;; gdbstub_purge_cache__dcache_loop:
59;; mov (a1),d0 # unconditional purge
60;;
61;; add L1_CACHE_BYTES,a1
62;; add -1,d1
63;; bne gdbstub_purge_cache__dcache_loop
64
65 #######################################################################
66 # now invalidate the icache
67 mov CHCTR,a0
68 movhu (a0),a1
69
70 mov epsw,d1
71 and ~EPSW_IE,epsw
72 nop
73 nop
74
75 # disable the icache
76 and ~CHCTR_ICEN,d0
77 movhu d0,(a0)
78
79 # and wait for it to calm down
80 setlb
81 movhu (a0),d0
82 btst CHCTR_ICBUSY,d0
83 lne
84
85 # invalidate
86 or CHCTR_ICINV,d0
87 movhu d0,(a0)
88
89 # wait for the cache to finish
90 mov CHCTR,a0
91 setlb
92 movhu (a0),d0
93 btst CHCTR_ICBUSY,d0
94 lne
95
96 # and reenable it
97 movhu a1,(a0)
98 movhu (a0),d0 # read back to flush
99 # (SIGILLs all over without this)
100
101 mov d1,epsw
102
103 ret [],0
104
105 .size gdbstub_purge_cache,.-gdbstub_purge_cache
diff --git a/arch/mn10300/kernel/gdb-stub.c b/arch/mn10300/kernel/gdb-stub.c
index a9c1e916687f..1e8f24f00637 100644
--- a/arch/mn10300/kernel/gdb-stub.c
+++ b/arch/mn10300/kernel/gdb-stub.c
@@ -133,7 +133,7 @@
133#include <asm/system.h> 133#include <asm/system.h>
134#include <asm/gdb-stub.h> 134#include <asm/gdb-stub.h>
135#include <asm/exceptions.h> 135#include <asm/exceptions.h>
136#include <asm/cacheflush.h> 136#include <asm/debugger.h>
137#include <asm/serial-regs.h> 137#include <asm/serial-regs.h>
138#include <asm/busctl-regs.h> 138#include <asm/busctl-regs.h>
139#include <unit/leds.h> 139#include <unit/leds.h>
@@ -1665,7 +1665,7 @@ done:
1665 * NB: We flush both caches, just to be sure... 1665 * NB: We flush both caches, just to be sure...
1666 */ 1666 */
1667 if (gdbstub_flush_caches) 1667 if (gdbstub_flush_caches)
1668 gdbstub_purge_cache(); 1668 debugger_local_cache_flushinv();
1669 1669
1670 gdbstub_load_fpu(); 1670 gdbstub_load_fpu();
1671 mn10300_set_gdbleds(0); 1671 mn10300_set_gdbleds(0);
diff --git a/arch/mn10300/mm/Kconfig.cache b/arch/mn10300/mm/Kconfig.cache
index c4fd923a55a0..bfbe52691f2c 100644
--- a/arch/mn10300/mm/Kconfig.cache
+++ b/arch/mn10300/mm/Kconfig.cache
@@ -99,3 +99,49 @@ config MN10300_CACHE_INV_ICACHE
99 help 99 help
100 Set if we need the icache to be invalidated, even if the dcache is in 100 Set if we need the icache to be invalidated, even if the dcache is in
101 write-through mode and doesn't need flushing. 101 write-through mode and doesn't need flushing.
102
103#
104# The kernel debugger gets its own separate cache flushing functions
105#
106config MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG
107 def_bool y if KERNEL_DEBUGGER && \
108 MN10300_CACHE_WBACK && \
109 !MN10300_CACHE_SNOOP && \
110 MN10300_CACHE_MANAGE_BY_TAG
111 help
112 Set if the debugger needs to flush the dcache and invalidate the
113 icache using the cache tag registers to make breakpoints work.
114
115config MN10300_DEBUGGER_CACHE_FLUSH_BY_REG
116 def_bool y if KERNEL_DEBUGGER && \
117 MN10300_CACHE_WBACK && \
118 !MN10300_CACHE_SNOOP && \
119 MN10300_CACHE_MANAGE_BY_REG
120 help
121 Set if the debugger needs to flush the dcache and invalidate the
122 icache using automatic purge registers to make breakpoints work.
123
124config MN10300_DEBUGGER_CACHE_INV_BY_TAG
125 def_bool y if KERNEL_DEBUGGER && \
126 MN10300_CACHE_WTHRU && \
127 !MN10300_CACHE_SNOOP && \
128 MN10300_CACHE_MANAGE_BY_TAG
129 help
130 Set if the debugger needs to invalidate the icache using the cache
131 tag registers to make breakpoints work.
132
133config MN10300_DEBUGGER_CACHE_INV_BY_REG
134 def_bool y if KERNEL_DEBUGGER && \
135 MN10300_CACHE_WTHRU && \
136 !MN10300_CACHE_SNOOP && \
137 MN10300_CACHE_MANAGE_BY_REG
138 help
139 Set if the debugger needs to invalidate the icache using automatic
140 purge registers to make breakpoints work.
141
142config MN10300_DEBUGGER_CACHE_NO_FLUSH
143 def_bool y if KERNEL_DEBUGGER && \
144 (MN10300_CACHE_DISABLED || MN10300_CACHE_SNOOP)
145 help
146 Set if the debugger does not need to flush the dcache and/or
147 invalidate the icache to make breakpoints work.
diff --git a/arch/mn10300/mm/Makefile b/arch/mn10300/mm/Makefile
index 203fee23f7d7..11f38466ac28 100644
--- a/arch/mn10300/mm/Makefile
+++ b/arch/mn10300/mm/Makefile
@@ -13,6 +13,15 @@ cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
13cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o 13cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_TAG) += cache-flush-by-tag.o
14cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o 14cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_BY_REG) += cache-flush-by-reg.o
15 15
16cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_TAG) += \
17 cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o
18cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_FLUSH_BY_REG) += \
19 cache-dbg-flush-by-reg.o
20cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG) += \
21 cache-dbg-inv-by-tag.o cache-dbg-inv.o
22cacheflush-$(CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_REG) += \
23 cache-dbg-inv-by-reg.o cache-dbg-inv.o
24
16cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o 25cacheflush-$(CONFIG_MN10300_CACHE_DISABLED) := cache-disabled.o
17 26
18obj-y := \ 27obj-y := \
diff --git a/arch/mn10300/mm/cache-dbg-flush-by-reg.S b/arch/mn10300/mm/cache-dbg-flush-by-reg.S
new file mode 100644
index 000000000000..665919f2ab62
--- /dev/null
+++ b/arch/mn10300/mm/cache-dbg-flush-by-reg.S
@@ -0,0 +1,160 @@
1/* MN10300 CPU cache invalidation routines, using automatic purge registers
2 *
3 * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#include <linux/sys.h>
12#include <linux/linkage.h>
13#include <asm/smp.h>
14#include <asm/page.h>
15#include <asm/cache.h>
16#include <asm/irqflags.h>
17#include <asm/cacheflush.h>
18#include "cache.inc"
19
20 .am33_2
21
22###############################################################################
23#
24# void debugger_local_cache_flushinv(void)
25# Flush the entire data cache back to RAM and invalidate the icache
26#
27###############################################################################
28 ALIGN
29 .globl debugger_local_cache_flushinv
30 .type debugger_local_cache_flushinv,@function
31debugger_local_cache_flushinv:
32 #
33 # firstly flush the dcache
34 #
35 movhu (CHCTR),d0
36 btst CHCTR_DCEN|CHCTR_ICEN,d0
37 beq debugger_local_cache_flushinv_end
38
39 mov DCPGCR,a0
40
41 mov epsw,d1
42 and ~EPSW_IE,epsw
43 or EPSW_NMID,epsw
44 nop
45
46 btst CHCTR_DCEN,d0
47 beq debugger_local_cache_flushinv_no_dcache
48
49 # wait for busy bit of area purge
50 setlb
51 mov (a0),d0
52 btst DCPGCR_DCPGBSY,d0
53 lne
54
55 # set mask
56 clr d0
57 mov d0,(DCPGMR)
58
59 # area purge
60 #
61 # DCPGCR = DCPGCR_DCP
62 #
63 mov DCPGCR_DCP,d0
64 mov d0,(a0)
65
66 # wait for busy bit of area purge
67 setlb
68 mov (a0),d0
69 btst DCPGCR_DCPGBSY,d0
70 lne
71
72debugger_local_cache_flushinv_no_dcache:
73 #
74 # secondly, invalidate the icache if it is enabled
75 #
76 mov CHCTR,a0
77 movhu (a0),d0
78 btst CHCTR_ICEN,d0
79 beq debugger_local_cache_flushinv_done
80
81 invalidate_icache 0
82
83debugger_local_cache_flushinv_done:
84 mov d1,epsw
85
86debugger_local_cache_flushinv_end:
87 ret [],0
88 .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv
89
90###############################################################################
91#
92# void debugger_local_cache_flushinv_one(u8 *addr)
93#
94# Invalidate one particular cacheline if it's in the icache
95#
96###############################################################################
97 ALIGN
98 .globl debugger_local_cache_flushinv_one
99 .type debugger_local_cache_flushinv_one,@function
100debugger_local_cache_flushinv_one:
101 movhu (CHCTR),d1
102 btst CHCTR_DCEN|CHCTR_ICEN,d1
103 beq debugger_local_cache_flushinv_one_end
104 btst CHCTR_DCEN,d1
105 beq debugger_local_cache_flushinv_one_no_dcache
106
107 # round cacheline addr down
108 and L1_CACHE_TAG_MASK,d0
109 mov d0,a1
110 mov d0,d1
111
112 # determine the dcache purge control reg address
113 mov DCACHE_PURGE(0,0),a0
114 and L1_CACHE_TAG_ENTRY,d0
115 add d0,a0
116
117 # retain valid entries in the cache
118 or L1_CACHE_TAG_VALID,d1
119
120 # conditionally purge this line in all ways
121 mov d1,(L1_CACHE_WAYDISP*0,a0)
122
123debugger_local_cache_flushinv_no_dcache:
124 #
125 # now try to flush the icache
126 #
127 mov CHCTR,a0
128 movhu (a0),d0
129 btst CHCTR_ICEN,d0
130 beq mn10300_local_icache_inv_range_reg_end
131
132 LOCAL_CLI_SAVE(d1)
133
134 mov ICIVCR,a0
135
136 # wait for the invalidator to quiesce
137 setlb
138 mov (a0),d0
139 btst ICIVCR_ICIVBSY,d0
140 lne
141
142 # set the mask
143 mov L1_CACHE_TAG_MASK,d0
144 mov d0,(ICIVMR)
145
146 # invalidate the cache line at the given address
147 or ICIVCR_ICI,a1
148 mov a1,(a0)
149
150 # wait for the invalidator to quiesce again
151 setlb
152 mov (a0),d0
153 btst ICIVCR_ICIVBSY,d0
154 lne
155
156 LOCAL_IRQ_RESTORE(d1)
157
158debugger_local_cache_flushinv_one_end:
159 ret [],0
160 .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one
diff --git a/arch/mn10300/mm/cache-dbg-flush-by-tag.S b/arch/mn10300/mm/cache-dbg-flush-by-tag.S
new file mode 100644
index 000000000000..bf56930e6e70
--- /dev/null
+++ b/arch/mn10300/mm/cache-dbg-flush-by-tag.S
@@ -0,0 +1,114 @@
1/* MN10300 CPU cache invalidation routines, using direct tag flushing
2 *
3 * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#include <linux/sys.h>
12#include <linux/linkage.h>
13#include <asm/smp.h>
14#include <asm/page.h>
15#include <asm/cache.h>
16#include <asm/irqflags.h>
17#include <asm/cacheflush.h>
18#include "cache.inc"
19
20 .am33_2
21
22###############################################################################
23#
24# void debugger_local_cache_flushinv(void)
25#
26# Flush the entire data cache back to RAM and invalidate the icache
27#
28###############################################################################
29 ALIGN
30 .globl debugger_local_cache_flushinv
31 .type debugger_local_cache_flushinv,@function
32debugger_local_cache_flushinv:
33 #
34 # firstly flush the dcache
35 #
36 movhu (CHCTR),d0
37 btst CHCTR_DCEN|CHCTR_ICEN,d0
38 beq debugger_local_cache_flushinv_end
39
40 btst CHCTR_DCEN,d0
41 beq debugger_local_cache_flushinv_no_dcache
42
43 # read the addresses tagged in the cache's tag RAM and attempt to flush
44 # those addresses specifically
45 # - we rely on the hardware to filter out invalid tag entry addresses
46 mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
47 mov DCACHE_PURGE(0,0),a1 # dcache purge request address
48 mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,e0 # total number of entries
49
50mn10300_local_dcache_flush_loop:
51 mov (a0),d0
52 and L1_CACHE_TAG_MASK,d0
53 or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
54 # cache
55 mov d0,(a1) # conditional purge
56
57 add L1_CACHE_BYTES,a0
58 add L1_CACHE_BYTES,a1
59 add -1,e0
60 bne mn10300_local_dcache_flush_loop
61
62debugger_local_cache_flushinv_no_dcache:
63 #
64 # secondly, invalidate the icache if it is enabled
65 #
66 mov CHCTR,a0
67 movhu (a0),d0
68 btst CHCTR_ICEN,d0
69 beq debugger_local_cache_flushinv_end
70
71 invalidate_icache 1
72
73debugger_local_cache_flushinv_end:
74 ret [],0
75 .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv
76
77###############################################################################
78#
79# void debugger_local_cache_flushinv_one(u8 *addr)
80#
81# Invalidate one particular cacheline if it's in the icache
82#
83###############################################################################
84 ALIGN
85 .globl debugger_local_cache_flushinv_one
86 .type debugger_local_cache_flushinv_one,@function
87debugger_local_cache_flushinv_one:
88 movhu (CHCTR),d1
89 btst CHCTR_DCEN|CHCTR_ICEN,d1
90 beq debugger_local_cache_flushinv_one_end
91 btst CHCTR_DCEN,d1
92 beq debugger_local_cache_flushinv_one_icache
93
94 # round cacheline addr down
95 and L1_CACHE_TAG_MASK,d0
96 mov d0,a1
97
98 # determine the dcache purge control reg address
99 mov DCACHE_PURGE(0,0),a0
100 and L1_CACHE_TAG_ENTRY,d0
101 add d0,a0
102
103 # retain valid entries in the cache
104 or L1_CACHE_TAG_VALID,a1
105
106 # conditionally purge this line in all ways
107 mov a1,(L1_CACHE_WAYDISP*0,a0)
108
109 # now go and do the icache
110 bra debugger_local_cache_flushinv_one_icache
111
112debugger_local_cache_flushinv_one_end:
113 ret [],0
114 .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one
diff --git a/arch/mn10300/mm/cache-dbg-inv-by-reg.S b/arch/mn10300/mm/cache-dbg-inv-by-reg.S
new file mode 100644
index 000000000000..c4e6252941b1
--- /dev/null
+++ b/arch/mn10300/mm/cache-dbg-inv-by-reg.S
@@ -0,0 +1,69 @@
1/* MN10300 CPU cache invalidation routines, using automatic purge registers
2 *
3 * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#include <linux/sys.h>
12#include <linux/linkage.h>
13#include <asm/cache.h>
14#include <asm/irqflags.h>
15#include <asm/cacheflush.h>
16#include "cache.inc"
17
18 .am33_2
19
20 .globl debugger_local_cache_flushinv_one
21
22###############################################################################
23#
24# void debugger_local_cache_flushinv_one(u8 *addr)
25#
26# Invalidate one particular cacheline if it's in the icache
27#
28###############################################################################
29 ALIGN
30 .globl debugger_local_cache_flushinv_one
31 .type debugger_local_cache_flushinv_one,@function
32debugger_local_cache_flushinv_one:
33 mov d0,a1
34
35 mov CHCTR,a0
36 movhu (a0),d0
37 btst CHCTR_ICEN,d0
38 beq mn10300_local_icache_inv_range_reg_end
39
40 LOCAL_CLI_SAVE(d1)
41
42 mov ICIVCR,a0
43
44 # wait for the invalidator to quiesce
45 setlb
46 mov (a0),d0
47 btst ICIVCR_ICIVBSY,d0
48 lne
49
50 # set the mask
51 mov ~L1_CACHE_TAG_MASK,d0
52 mov d0,(ICIVMR)
53
54 # invalidate the cache line at the given address
55 and ~L1_CACHE_TAG_MASK,a1
56 or ICIVCR_ICI,a1
57 mov a1,(a0)
58
59 # wait for the invalidator to quiesce again
60 setlb
61 mov (a0),d0
62 btst ICIVCR_ICIVBSY,d0
63 lne
64
65 LOCAL_IRQ_RESTORE(d1)
66
67mn10300_local_icache_inv_range_reg_end:
68 ret [],0
69 .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one
diff --git a/arch/mn10300/mm/cache-dbg-inv-by-tag.S b/arch/mn10300/mm/cache-dbg-inv-by-tag.S
new file mode 100644
index 000000000000..d8ec821e5f88
--- /dev/null
+++ b/arch/mn10300/mm/cache-dbg-inv-by-tag.S
@@ -0,0 +1,120 @@
1/* MN10300 CPU cache invalidation routines, using direct tag flushing
2 *
3 * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#include <linux/sys.h>
12#include <linux/linkage.h>
13#include <asm/smp.h>
14#include <asm/page.h>
15#include <asm/cache.h>
16#include <asm/irqflags.h>
17#include <asm/cacheflush.h>
18#include "cache.inc"
19
20 .am33_2
21
22 .globl debugger_local_cache_flushinv_one_icache
23
24###############################################################################
25#
26# void debugger_local_cache_flushinv_one(u8 *addr)
27#
28# Invalidate one particular cacheline if it's in the icache
29#
30###############################################################################
31 ALIGN
32 .globl debugger_local_cache_flushinv_one_icache
33 .type debugger_local_cache_flushinv_one_icache,@function
34debugger_local_cache_flushinv_one_icache:
35 movm [d3,a2],(sp)
36
37 mov CHCTR,a2
38 movhu (a2),d0
39 btst CHCTR_ICEN,d0
40 beq debugger_local_cache_flushinv_one_icache_end
41
42 mov d0,a1
43 and L1_CACHE_TAG_MASK,a1
44
45 # read the tags from the tag RAM, and if they indicate a matching valid
46 # cache line then we invalidate that line
47 mov ICACHE_TAG(0,0),a0
48 mov a1,d0
49 and L1_CACHE_TAG_ENTRY,d0
50 add d0,a0 # starting icache tag RAM
51 # access address
52
53 and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base
54 or L1_CACHE_TAG_VALID,a1
55 mov L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_VALID,d1
56
57 LOCAL_CLI_SAVE(d3)
58
59 # disable the icache
60 movhu (a2),d0
61 and ~CHCTR_ICEN,d0
62 movhu d0,(a2)
63
64 # and wait for it to calm down
65 setlb
66 movhu (a2),d0
67 btst CHCTR_ICBUSY,d0
68 lne
69
70 # check all the way tags for this cache entry
71 mov (a0),d0 # read the tag in the way 0 slot
72 xor a1,d0
73 and d1,d0
74 beq debugger_local_icache_kill # jump if matched
75
76 add L1_CACHE_WAYDISP,a0
77 mov (a0),d0 # read the tag in the way 1 slot
78 xor a1,d0
79 and d1,d0
80 beq debugger_local_icache_kill # jump if matched
81
82 add L1_CACHE_WAYDISP,a0
83 mov (a0),d0 # read the tag in the way 2 slot
84 xor a1,d0
85 and d1,d0
86 beq debugger_local_icache_kill # jump if matched
87
88 add L1_CACHE_WAYDISP,a0
89 mov (a0),d0 # read the tag in the way 3 slot
90 xor a1,d0
91 and d1,d0
92 bne debugger_local_icache_finish # jump if not matched
93
94debugger_local_icache_kill:
95 mov d0,(a0) # kill the tag (D0 is 0 at this point)
96
97debugger_local_icache_finish:
98 # wait for the cache to finish what it's doing
99 setlb
100 movhu (a2),d0
101 btst CHCTR_ICBUSY,d0
102 lne
103
104 # and reenable it
105 or CHCTR_ICEN,d0
106 movhu d0,(a2)
107 movhu (a2),d0
108
109 # re-enable interrupts
110 LOCAL_IRQ_RESTORE(d3)
111
112debugger_local_cache_flushinv_one_icache_end:
113 ret [d3,a2],8
114 .size debugger_local_cache_flushinv_one_icache,.-debugger_local_cache_flushinv_one_icache
115
116#ifdef CONFIG_MN10300_DEBUGGER_CACHE_INV_BY_TAG
117 .globl debugger_local_cache_flushinv_one
118 .type debugger_local_cache_flushinv_one,@function
119debugger_local_cache_flushinv_one = debugger_local_cache_flushinv_one_icache
120#endif
diff --git a/arch/mn10300/mm/cache-dbg-inv.S b/arch/mn10300/mm/cache-dbg-inv.S
new file mode 100644
index 000000000000..eba2d6dca066
--- /dev/null
+++ b/arch/mn10300/mm/cache-dbg-inv.S
@@ -0,0 +1,47 @@
1/* MN10300 CPU cache invalidation routines
2 *
3 * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#include <linux/sys.h>
12#include <linux/linkage.h>
13#include <asm/smp.h>
14#include <asm/page.h>
15#include <asm/cache.h>
16#include <asm/irqflags.h>
17#include <asm/cacheflush.h>
18#include "cache.inc"
19
20 .am33_2
21
22 .globl debugger_local_cache_flushinv
23
24###############################################################################
25#
26# void debugger_local_cache_flushinv(void)
27#
28# Invalidate the entire icache
29#
30###############################################################################
31 ALIGN
32 .globl debugger_local_cache_flushinv
33 .type debugger_local_cache_flushinv,@function
34debugger_local_cache_flushinv:
35 #
36 # we only need to invalidate the icache in this cache mode
37 #
38 mov CHCTR,a0
39 movhu (a0),d0
40 btst CHCTR_ICEN,d0
41 beq debugger_local_cache_flushinv_end
42
43 invalidate_icache 1
44
45debugger_local_cache_flushinv_end:
46 ret [],0
47 .size debugger_local_cache_flushinv,.-debugger_local_cache_flushinv
diff --git a/arch/mn10300/mm/cache-flush-by-tag.S b/arch/mn10300/mm/cache-flush-by-tag.S
index 5cd6a27dd63e..1ddc06849242 100644
--- a/arch/mn10300/mm/cache-flush-by-tag.S
+++ b/arch/mn10300/mm/cache-flush-by-tag.S
@@ -62,7 +62,7 @@ mn10300_local_dcache_flush:
62 62
63mn10300_local_dcache_flush_loop: 63mn10300_local_dcache_flush_loop:
64 mov (a0),d0 64 mov (a0),d0
65 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 65 and L1_CACHE_TAG_MASK,d0
66 or L1_CACHE_TAG_VALID,d0 # retain valid entries in the 66 or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
67 # cache 67 # cache
68 mov d0,(a1) # conditional purge 68 mov d0,(a1) # conditional purge
@@ -112,11 +112,11 @@ mn10300_local_dcache_flush_range:
1121: 1121:
113 113
114 # round start addr down 114 # round start addr down
115 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 115 and L1_CACHE_TAG_MASK,d0
116 mov d0,a1 116 mov d0,a1
117 117
118 add L1_CACHE_BYTES,d1 # round end addr up 118 add L1_CACHE_BYTES,d1 # round end addr up
119 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 119 and L1_CACHE_TAG_MASK,d1
120 120
121 # write a request to flush all instances of an address from the cache 121 # write a request to flush all instances of an address from the cache
122 mov DCACHE_PURGE(0,0),a0 122 mov DCACHE_PURGE(0,0),a0
@@ -215,12 +215,11 @@ mn10300_local_dcache_flush_inv_range:
215 bra mn10300_local_dcache_flush_inv 215 bra mn10300_local_dcache_flush_inv
2161: 2161:
217 217
218 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start 218 and L1_CACHE_TAG_MASK,d0 # round start addr down
219 # addr down
220 mov d0,a1 219 mov d0,a1
221 220
222 add L1_CACHE_BYTES,d1 # round end addr up 221 add L1_CACHE_BYTES,d1 # round end addr up
223 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 222 and L1_CACHE_TAG_MASK,d1
224 223
225 # write a request to flush and invalidate all instances of an address 224 # write a request to flush and invalidate all instances of an address
226 # from the cache 225 # from the cache
diff --git a/arch/mn10300/mm/cache-inv-by-reg.S b/arch/mn10300/mm/cache-inv-by-reg.S
index d1f363a8d36b..a60825b91e77 100644
--- a/arch/mn10300/mm/cache-inv-by-reg.S
+++ b/arch/mn10300/mm/cache-inv-by-reg.S
@@ -116,9 +116,9 @@ mn10300_local_dcache_inv_range:
116 # and if they're not cacheline-aligned, we must flush any bits outside 116 # and if they're not cacheline-aligned, we must flush any bits outside
117 # the range that share cachelines with stuff inside the range 117 # the range that share cachelines with stuff inside the range
118#ifdef CONFIG_MN10300_CACHE_WBACK 118#ifdef CONFIG_MN10300_CACHE_WBACK
119 btst ~(L1_CACHE_BYTES-1),d0 119 btst ~L1_CACHE_TAG_MASK,d0
120 bne 1f 120 bne 1f
121 btst ~(L1_CACHE_BYTES-1),d1 121 btst ~L1_CACHE_TAG_MASK,d1
122 beq 2f 122 beq 2f
1231: 1231:
124 bra mn10300_local_dcache_flush_inv_range 124 bra mn10300_local_dcache_flush_inv_range
@@ -136,12 +136,11 @@ mn10300_local_dcache_inv_range:
136 # writeback mode, in which case we would be in flush and invalidate by 136 # writeback mode, in which case we would be in flush and invalidate by
137 # now 137 # now
138#ifndef CONFIG_MN10300_CACHE_WBACK 138#ifndef CONFIG_MN10300_CACHE_WBACK
139 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start 139 and L1_CACHE_TAG_MASK,d0 # round start addr down
140 # addr down
141 140
142 mov L1_CACHE_BYTES-1,d2 141 mov L1_CACHE_BYTES-1,d2
143 add d2,d1 142 add d2,d1
144 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 # round end addr up 143 and L1_CACHE_TAG_MASK,d1 # round end addr up
145#endif /* !CONFIG_MN10300_CACHE_WBACK */ 144#endif /* !CONFIG_MN10300_CACHE_WBACK */
146 145
147 sub d0,d1,d2 # calculate the total size 146 sub d0,d1,d2 # calculate the total size
diff --git a/arch/mn10300/mm/cache-inv-by-tag.S b/arch/mn10300/mm/cache-inv-by-tag.S
index c5c80322eefb..ccedce9c144d 100644
--- a/arch/mn10300/mm/cache-inv-by-tag.S
+++ b/arch/mn10300/mm/cache-inv-by-tag.S
@@ -124,9 +124,9 @@ mn10300_local_dcache_inv_range:
124 # and if they're not cacheline-aligned, we must flush any bits outside 124 # and if they're not cacheline-aligned, we must flush any bits outside
125 # the range that share cachelines with stuff inside the range 125 # the range that share cachelines with stuff inside the range
126#ifdef CONFIG_MN10300_CACHE_WBACK 126#ifdef CONFIG_MN10300_CACHE_WBACK
127 btst ~(L1_CACHE_BYTES-1),d0 127 btst ~L1_CACHE_TAG_MASK,d0
128 bne 1f 128 bne 1f
129 btst ~(L1_CACHE_BYTES-1),d1 129 btst ~L1_CACHE_TAG_MASK,d1
130 beq 2f 130 beq 2f
1311: 1311:
132 bra mn10300_local_dcache_flush_inv_range 132 bra mn10300_local_dcache_flush_inv_range
@@ -141,11 +141,10 @@ mn10300_local_dcache_inv_range:
141 beq mn10300_local_dcache_inv_range_end 141 beq mn10300_local_dcache_inv_range_end
142 142
143#ifndef CONFIG_MN10300_CACHE_WBACK 143#ifndef CONFIG_MN10300_CACHE_WBACK
144 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start 144 and L1_CACHE_TAG_MASK,d0 # round start addr down
145 # addr down
146 145
147 add L1_CACHE_BYTES,d1 # round end addr up 146 add L1_CACHE_BYTES,d1 # round end addr up
148 and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1 147 and L1_CACHE_TAG_MASK,d1
149#endif /* !CONFIG_MN10300_CACHE_WBACK */ 148#endif /* !CONFIG_MN10300_CACHE_WBACK */
150 mov d0,a1 149 mov d0,a1
151 150
diff --git a/arch/mn10300/proc-mn103e010/include/proc/cache.h b/arch/mn10300/proc-mn103e010/include/proc/cache.h
index c1528004163c..967d144f307e 100644
--- a/arch/mn10300/proc-mn103e010/include/proc/cache.h
+++ b/arch/mn10300/proc-mn103e010/include/proc/cache.h
@@ -23,6 +23,7 @@
23#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ 23#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
24#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */ 24#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */
25#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ 25#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
26#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY)
26 27
27/* 28/*
28 * specification of the interval between interrupt checking intervals whilst 29 * specification of the interval between interrupt checking intervals whilst
diff --git a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h
index cafd7b5b55b4..bcb5df2d892f 100644
--- a/arch/mn10300/proc-mn2ws0050/include/proc/cache.h
+++ b/arch/mn10300/proc-mn2ws0050/include/proc/cache.h
@@ -29,6 +29,7 @@
29#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */ 29#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
30#define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */ 30#define L1_CACHE_TAG_ENTRY 0x00000fe0 /* cache tag entry address mask */
31#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */ 31#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
32#define L1_CACHE_TAG_MASK +(L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY)
32 33
33/* 34/*
34 * specification of the interval between interrupt checking intervals whilst 35 * specification of the interval between interrupt checking intervals whilst
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 01:32:48 -0400