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-rw-r--r--arch/arm/mach-davinci/clock.h4
-rw-r--r--arch/arm/mach-davinci/da850.c40
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h1
3 files changed, 43 insertions, 2 deletions
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a75d3f70b351..d45dc6960a94 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -69,9 +69,9 @@ struct clk {
69 const char *name; 69 const char *name;
70 unsigned long rate; 70 unsigned long rate;
71 u8 usecount; 71 u8 usecount;
72 u8 flags;
73 u8 lpsc; 72 u8 lpsc;
74 u8 psc_ctlr; 73 u8 psc_ctlr;
74 u32 flags;
75 struct clk *parent; 75 struct clk *parent;
76 struct list_head children; /* list of children */ 76 struct list_head children; /* list of children */
77 struct list_head childnode; /* parent's child list node */ 77 struct list_head childnode; /* parent's child list node */
@@ -82,7 +82,7 @@ struct clk {
82 int (*round_rate) (struct clk *clk, unsigned long rate); 82 int (*round_rate) (struct clk *clk, unsigned long rate);
83}; 83};
84 84
85/* Clock flags */ 85/* Clock flags: SoC-specific flags start at BIT(16) */
86#define ALWAYS_ENABLED BIT(1) 86#define ALWAYS_ENABLED BIT(1)
87#define CLK_PSC BIT(2) 87#define CLK_PSC BIT(2)
88#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ 88#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index f5c3a6a71315..575e9ccbb25f 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -30,12 +30,17 @@
30#include "clock.h" 30#include "clock.h"
31#include "mux.h" 31#include "mux.h"
32 32
33/* SoC specific clock flags */
34#define DA850_CLK_ASYNC3 BIT(16)
35
33#define DA850_PLL1_BASE 0x01e1a000 36#define DA850_PLL1_BASE 0x01e1a000
34#define DA850_TIMER64P2_BASE 0x01f0c000 37#define DA850_TIMER64P2_BASE 0x01f0c000
35#define DA850_TIMER64P3_BASE 0x01f0d000 38#define DA850_TIMER64P3_BASE 0x01f0d000
36 39
37#define DA850_REF_FREQ 24000000 40#define DA850_REF_FREQ 24000000
38 41
42#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
43
39static struct pll_data pll0_data = { 44static struct pll_data pll0_data = {
40 .num = 1, 45 .num = 1,
41 .phys_base = DA8XX_PLL0_BASE, 46 .phys_base = DA8XX_PLL0_BASE,
@@ -232,6 +237,7 @@ static struct clk uart1_clk = {
232 .name = "uart1", 237 .name = "uart1",
233 .parent = &pll0_sysclk2, 238 .parent = &pll0_sysclk2,
234 .lpsc = DA8XX_LPSC1_UART1, 239 .lpsc = DA8XX_LPSC1_UART1,
240 .flags = DA850_CLK_ASYNC3,
235 .psc_ctlr = 1, 241 .psc_ctlr = 1,
236}; 242};
237 243
@@ -239,6 +245,7 @@ static struct clk uart2_clk = {
239 .name = "uart2", 245 .name = "uart2",
240 .parent = &pll0_sysclk2, 246 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC1_UART2, 247 .lpsc = DA8XX_LPSC1_UART2,
248 .flags = DA850_CLK_ASYNC3,
242 .psc_ctlr = 1, 249 .psc_ctlr = 1,
243}; 250};
244 251
@@ -790,6 +797,30 @@ static struct davinci_timer_info da850_timer_info = {
790 .clocksource_id = T0_TOP, 797 .clocksource_id = T0_TOP,
791}; 798};
792 799
800static void da850_set_async3_src(int pllnum)
801{
802 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
803 struct davinci_clk *c;
804 unsigned int v;
805 int ret;
806
807 for (c = da850_clks; c->lk.clk; c++) {
808 clk = c->lk.clk;
809 if (clk->flags & DA850_CLK_ASYNC3) {
810 ret = clk_set_parent(clk, newparent);
811 WARN(ret, "DA850: unable to re-parent clock %s",
812 clk->name);
813 }
814 }
815
816 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
817 if (pllnum)
818 v |= CFGCHIP3_ASYNC3_CLKSRC;
819 else
820 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
821 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
822}
823
793static struct davinci_soc_info davinci_soc_info_da850 = { 824static struct davinci_soc_info davinci_soc_info_da850 = {
794 .io_desc = da850_io_desc, 825 .io_desc = da850_io_desc,
795 .io_desc_num = ARRAY_SIZE(da850_io_desc), 826 .io_desc_num = ARRAY_SIZE(da850_io_desc),
@@ -823,4 +854,13 @@ void __init da850_init(void)
823 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120); 854 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
824 855
825 davinci_common_init(&davinci_soc_info_da850); 856 davinci_common_init(&davinci_soc_info_da850);
857
858 /*
859 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
860 * This helps keeping the peripherals on this domain insulated
861 * from CPU frequency changes caused by DVFS. The firmware sets
862 * both PLL0 and PLL1 to the same frequency so, there should not
863 * be any noticible change even in non-DVFS use cases.
864 */
865 da850_set_async3_src(1);
826} 866}
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 6f036506bc68..ec2821bc38d2 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -34,6 +34,7 @@ extern void __iomem *da8xx_syscfg_base;
34#define DA8XX_SYSCFG_BASE (IO_PHYS + 0x14000) 34#define DA8XX_SYSCFG_BASE (IO_PHYS + 0x14000)
35#define DA8XX_SYSCFG_VIRT(x) (da8xx_syscfg_base + (x)) 35#define DA8XX_SYSCFG_VIRT(x) (da8xx_syscfg_base + (x))
36#define DA8XX_JTAG_ID_REG 0x18 36#define DA8XX_JTAG_ID_REG 0x18
37#define DA8XX_CFGCHIP3_REG 0x188
37 38
38#define DA8XX_PSC0_BASE 0x01c10000 39#define DA8XX_PSC0_BASE 0x01c10000
39#define DA8XX_PLL0_BASE 0x01c11000 40#define DA8XX_PLL0_BASE 0x01c11000