diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/m68k/include/asm/dma.h | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h index 3b85f6e6c098..6fbdfe895104 100644 --- a/arch/m68k/include/asm/dma.h +++ b/arch/m68k/include/asm/dma.h | |||
@@ -177,21 +177,21 @@ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | |||
177 | dmabp = (unsigned char *) dma_base_addr[dmanr]; | 177 | dmabp = (unsigned char *) dma_base_addr[dmanr]; |
178 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | 178 | dmawp = (unsigned short *) dma_base_addr[dmanr]; |
179 | 179 | ||
180 | // Clear config errors | 180 | /* Clear config errors */ |
181 | dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE; | 181 | dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE; |
182 | 182 | ||
183 | // Set command register | 183 | /* Set command register */ |
184 | dmawp[MCFDMA_DCR] = | 184 | dmawp[MCFDMA_DCR] = |
185 | MCFDMA_DCR_INT | // Enable completion irq | 185 | MCFDMA_DCR_INT | /* Enable completion irq */ |
186 | MCFDMA_DCR_CS | // Force one xfer per request | 186 | MCFDMA_DCR_CS | /* Force one xfer per request */ |
187 | MCFDMA_DCR_AA | // Enable auto alignment | 187 | MCFDMA_DCR_AA | /* Enable auto alignment */ |
188 | // single-address-mode | 188 | /* single-address-mode */ |
189 | ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) | | 189 | ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) | |
190 | // sets s_rw (-> r/w) high if Memory to I/0 | 190 | /* sets s_rw (-> r/w) high if Memory to I/0 */ |
191 | ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) | | 191 | ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) | |
192 | // Memory to I/O or I/O to Memory | 192 | /* Memory to I/O or I/O to Memory */ |
193 | ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) | | 193 | ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) | |
194 | // 32 bit, 16 bit or 8 bit transfers | 194 | /* 32 bit, 16 bit or 8 bit transfers */ |
195 | ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD : | 195 | ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD : |
196 | ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG : | 196 | ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG : |
197 | MCFDMA_DCR_SSIZE_BYTE)) | | 197 | MCFDMA_DCR_SSIZE_BYTE)) | |
@@ -219,16 +219,16 @@ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) | |||
219 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | 219 | dmawp = (unsigned short *) dma_base_addr[dmanr]; |
220 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | 220 | dmalp = (unsigned int *) dma_base_addr[dmanr]; |
221 | 221 | ||
222 | // Determine which address registers are used for memory/device accesses | 222 | /* Determine which address registers are used for memory/device accesses */ |
223 | if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) { | 223 | if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) { |
224 | // Source incrementing, must be memory | 224 | /* Source incrementing, must be memory */ |
225 | dmalp[MCFDMA_SAR] = a; | 225 | dmalp[MCFDMA_SAR] = a; |
226 | // Set dest address, must be device | 226 | /* Set dest address, must be device */ |
227 | dmalp[MCFDMA_DAR] = dma_device_address[dmanr]; | 227 | dmalp[MCFDMA_DAR] = dma_device_address[dmanr]; |
228 | } else { | 228 | } else { |
229 | // Destination incrementing, must be memory | 229 | /* Destination incrementing, must be memory */ |
230 | dmalp[MCFDMA_DAR] = a; | 230 | dmalp[MCFDMA_DAR] = a; |
231 | // Set source address, must be device | 231 | /* Set source address, must be device */ |
232 | dmalp[MCFDMA_SAR] = dma_device_address[dmanr]; | 232 | dmalp[MCFDMA_SAR] = dma_device_address[dmanr]; |
233 | } | 233 | } |
234 | 234 | ||
@@ -367,19 +367,19 @@ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) | |||
367 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | 367 | dmalp = (unsigned int *) dma_base_addr[dmanr]; |
368 | dmawp = (unsigned short *) dma_base_addr[dmanr]; | 368 | dmawp = (unsigned short *) dma_base_addr[dmanr]; |
369 | 369 | ||
370 | // Clear config errors | 370 | /* Clear config errors */ |
371 | dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; | 371 | dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; |
372 | 372 | ||
373 | // Set command register | 373 | /* Set command register */ |
374 | dmalp[MCFDMA_DMR] = | 374 | dmalp[MCFDMA_DMR] = |
375 | MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting | 375 | MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */ |
376 | MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data. | 376 | MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */ |
377 | MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data. | 377 | MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */ |
378 | // source static-address-mode | 378 | /* source static-address-mode */ |
379 | ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) | | 379 | ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) | |
380 | // dest static-address-mode | 380 | /* dest static-address-mode */ |
381 | ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) | | 381 | ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) | |
382 | // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 | 382 | /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */ |
383 | (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) | | 383 | (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) | |
384 | (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF); | 384 | (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF); |
385 | 385 | ||
@@ -403,16 +403,16 @@ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) | |||
403 | 403 | ||
404 | dmalp = (unsigned int *) dma_base_addr[dmanr]; | 404 | dmalp = (unsigned int *) dma_base_addr[dmanr]; |
405 | 405 | ||
406 | // Determine which address registers are used for memory/device accesses | 406 | /* Determine which address registers are used for memory/device accesses */ |
407 | if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) { | 407 | if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) { |
408 | // Source incrementing, must be memory | 408 | /* Source incrementing, must be memory */ |
409 | dmalp[MCFDMA_DSAR] = a; | 409 | dmalp[MCFDMA_DSAR] = a; |
410 | // Set dest address, must be device | 410 | /* Set dest address, must be device */ |
411 | dmalp[MCFDMA_DDAR] = dma_device_address[dmanr]; | 411 | dmalp[MCFDMA_DDAR] = dma_device_address[dmanr]; |
412 | } else { | 412 | } else { |
413 | // Destination incrementing, must be memory | 413 | /* Destination incrementing, must be memory */ |
414 | dmalp[MCFDMA_DDAR] = a; | 414 | dmalp[MCFDMA_DDAR] = a; |
415 | // Set source address, must be device | 415 | /* Set source address, must be device */ |
416 | dmalp[MCFDMA_DSAR] = dma_device_address[dmanr]; | 416 | dmalp[MCFDMA_DSAR] = dma_device_address[dmanr]; |
417 | } | 417 | } |
418 | 418 | ||