aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/configs/s3c6400_defconfig130
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-core.h34
-rw-r--r--arch/arm/mach-s3c2410/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-s3c2410/include/mach/map.h3
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c7
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c6
-rw-r--r--arch/arm/mach-s3c2410/mach-otom.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2410.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-tct_hammer.c4
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c4
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c9
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c4
-rw-r--r--arch/arm/mach-s3c2412/mach-vstms.c4
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c4
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c5
-rw-r--r--arch/arm/mach-s3c2440/mach-nexcoder.c4
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c5
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c4
-rw-r--r--arch/arm/mach-s3c2443/Kconfig1
-rw-r--r--arch/arm/mach-s3c2443/mach-smdk2443.c6
-rw-r--r--arch/arm/mach-s3c24a0/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c6400/include/mach/gpio-core.h21
-rw-r--r--arch/arm/mach-s3c6400/include/mach/gpio.h76
-rw-r--r--arch/arm/mach-s3c6400/include/mach/map.h15
-rw-r--r--arch/arm/mach-s3c6400/include/mach/regs-fb.h259
-rw-r--r--arch/arm/mach-s3c6410/Kconfig41
-rw-r--r--arch/arm/mach-s3c6410/Makefile4
-rw-r--r--arch/arm/mach-s3c6410/cpu.c10
-rw-r--r--arch/arm/mach-s3c6410/mach-smdk6410.c96
-rw-r--r--arch/arm/mach-s3c6410/setup-sdhci.c102
-rw-r--r--arch/arm/plat-s3c/Kconfig70
-rw-r--r--arch/arm/plat-s3c/Makefile12
-rw-r--r--arch/arm/plat-s3c/dev-fb.c72
-rw-r--r--arch/arm/plat-s3c/dev-hsmmc.c68
-rw-r--r--arch/arm/plat-s3c/dev-hsmmc1.c68
-rw-r--r--arch/arm/plat-s3c/dev-i2c0.c71
-rw-r--r--arch/arm/plat-s3c/dev-i2c1.c68
-rw-r--r--arch/arm/plat-s3c/gpio-config.c163
-rw-r--r--arch/arm/plat-s3c/gpio.c147
-rw-r--r--arch/arm/plat-s3c/include/plat/devs.h8
-rw-r--r--arch/arm/plat-s3c/include/plat/fb.h73
-rw-r--r--arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h176
-rw-r--r--arch/arm/plat-s3c/include/plat/gpio-cfg.h110
-rw-r--r--arch/arm/plat-s3c/include/plat/gpio-core.h77
-rw-r--r--arch/arm/plat-s3c/include/plat/iic-core.h35
-rw-r--r--arch/arm/plat-s3c/include/plat/iic.h24
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-fb.h366
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-sdhci.h87
-rw-r--r--arch/arm/plat-s3c/include/plat/sdhci.h108
-rw-r--r--arch/arm/plat-s3c24xx/Makefile3
-rw-r--r--arch/arm/plat-s3c24xx/devs.c55
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c125
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/map.h1
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.c2
-rw-r--r--arch/arm/plat-s3c24xx/setup-i2c.c25
-rw-r--r--arch/arm/plat-s3c64xx/Kconfig25
-rw-r--r--arch/arm/plat-s3c64xx/Makefile7
-rw-r--r--arch/arm/plat-s3c64xx/gpiolib.c420
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h48
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h60
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h53
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h49
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h44
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h71
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h42
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h74
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h40
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h36
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h54
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h70
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h69
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h46
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/irqs.h5
-rw-r--r--arch/arm/plat-s3c64xx/include/plat/regs-gpio.h35
-rw-r--r--arch/arm/plat-s3c64xx/setup-fb-24bpp.c37
-rw-r--r--arch/arm/plat-s3c64xx/setup-i2c0.c31
-rw-r--r--arch/arm/plat-s3c64xx/setup-i2c1.c31
81 files changed, 4027 insertions, 218 deletions
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index 3a50716d443b..cf3c1b5d7048 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.27 3# Linux kernel version: 2.6.28-rc3
4# Fri Oct 17 09:20:54 2008 4# Mon Nov 3 10:10:30 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -116,6 +116,7 @@ CONFIG_DEFAULT_CFQ=y
116# CONFIG_DEFAULT_NOOP is not set 116# CONFIG_DEFAULT_NOOP is not set
117CONFIG_DEFAULT_IOSCHED="cfq" 117CONFIG_DEFAULT_IOSCHED="cfq"
118CONFIG_CLASSIC_RCU=y 118CONFIG_CLASSIC_RCU=y
119# CONFIG_FREEZER is not set
119 120
120# 121#
121# System Type 122# System Type
@@ -152,16 +153,17 @@ CONFIG_CLASSIC_RCU=y
152# CONFIG_ARCH_RPC is not set 153# CONFIG_ARCH_RPC is not set
153# CONFIG_ARCH_SA1100 is not set 154# CONFIG_ARCH_SA1100 is not set
154# CONFIG_ARCH_S3C2410 is not set 155# CONFIG_ARCH_S3C2410 is not set
155# CONFIG_ARCH_S3C24A0 is not set
156CONFIG_ARCH_S3C64XX=y 156CONFIG_ARCH_S3C64XX=y
157# CONFIG_ARCH_SHARK is not set 157# CONFIG_ARCH_SHARK is not set
158# CONFIG_ARCH_LH7A40X is not set 158# CONFIG_ARCH_LH7A40X is not set
159# CONFIG_ARCH_DAVINCI is not set 159# CONFIG_ARCH_DAVINCI is not set
160# CONFIG_ARCH_OMAP is not set 160# CONFIG_ARCH_OMAP is not set
161# CONFIG_ARCH_MSM7X00A is not set 161# CONFIG_ARCH_MSM is not set
162CONFIG_PLAT_S3C64XX=y 162CONFIG_PLAT_S3C64XX=y
163CONFIG_CPU_S3C6400_INIT=y 163CONFIG_CPU_S3C6400_INIT=y
164CONFIG_CPU_S3C6400_CLOCK=y 164CONFIG_CPU_S3C6400_CLOCK=y
165CONFIG_S3C64XX_SETUP_I2C0=y
166CONFIG_S3C64XX_SETUP_I2C1=y
165CONFIG_PLAT_S3C=y 167CONFIG_PLAT_S3C=y
166 168
167# 169#
@@ -173,8 +175,19 @@ CONFIG_S3C_BOOT_ERROR_RESET=y
173# Power management 175# Power management
174# 176#
175CONFIG_S3C_LOWLEVEL_UART_PORT=0 177CONFIG_S3C_LOWLEVEL_UART_PORT=0
178CONFIG_S3C_GPIO_SPACE=0
179CONFIG_S3C_GPIO_TRACK=y
180CONFIG_S3C_GPIO_PULL_UPDOWN=y
181CONFIG_S3C_GPIO_CFG_S3C24XX=y
182CONFIG_S3C_GPIO_CFG_S3C64XX=y
183CONFIG_S3C_DEV_HSMMC=y
184CONFIG_S3C_DEV_HSMMC1=y
185CONFIG_S3C_DEV_I2C1=y
176CONFIG_CPU_S3C6410=y 186CONFIG_CPU_S3C6410=y
187CONFIG_S3C6410_SETUP_SDHCI=y
177CONFIG_MACH_SMDK6410=y 188CONFIG_MACH_SMDK6410=y
189CONFIG_SMDK6410_SD_CH0=y
190# CONFIG_SMDK6410_SD_CH1 is not set
178 191
179# 192#
180# Processor Type 193# Processor Type
@@ -233,8 +246,10 @@ CONFIG_FLAT_NODE_MEM_MAP=y
233CONFIG_PAGEFLAGS_EXTENDED=y 246CONFIG_PAGEFLAGS_EXTENDED=y
234CONFIG_SPLIT_PTLOCK_CPUS=4 247CONFIG_SPLIT_PTLOCK_CPUS=4
235# CONFIG_RESOURCES_64BIT is not set 248# CONFIG_RESOURCES_64BIT is not set
249# CONFIG_PHYS_ADDR_T_64BIT is not set
236CONFIG_ZONE_DMA_FLAG=0 250CONFIG_ZONE_DMA_FLAG=0
237CONFIG_VIRT_TO_BUS=y 251CONFIG_VIRT_TO_BUS=y
252CONFIG_UNEVICTABLE_LRU=y
238CONFIG_ALIGNMENT_TRAP=y 253CONFIG_ALIGNMENT_TRAP=y
239 254
240# 255#
@@ -266,6 +281,7 @@ CONFIG_VFP=y
266# Userspace binary formats 281# Userspace binary formats
267# 282#
268CONFIG_BINFMT_ELF=y 283CONFIG_BINFMT_ELF=y
284# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
269CONFIG_HAVE_AOUT=y 285CONFIG_HAVE_AOUT=y
270# CONFIG_BINFMT_AOUT is not set 286# CONFIG_BINFMT_AOUT is not set
271# CONFIG_BINFMT_MISC is not set 287# CONFIG_BINFMT_MISC is not set
@@ -356,6 +372,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
356CONFIG_MOUSE_PS2_SYNAPTICS=y 372CONFIG_MOUSE_PS2_SYNAPTICS=y
357CONFIG_MOUSE_PS2_LIFEBOOK=y 373CONFIG_MOUSE_PS2_LIFEBOOK=y
358CONFIG_MOUSE_PS2_TRACKPOINT=y 374CONFIG_MOUSE_PS2_TRACKPOINT=y
375# CONFIG_MOUSE_PS2_ELANTECH is not set
359# CONFIG_MOUSE_PS2_TOUCHKIT is not set 376# CONFIG_MOUSE_PS2_TOUCHKIT is not set
360# CONFIG_MOUSE_SERIAL is not set 377# CONFIG_MOUSE_SERIAL is not set
361# CONFIG_MOUSE_APPLETOUCH is not set 378# CONFIG_MOUSE_APPLETOUCH is not set
@@ -400,6 +417,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
400# Non-8250 serial port support 417# Non-8250 serial port support
401# 418#
402CONFIG_SERIAL_SAMSUNG=y 419CONFIG_SERIAL_SAMSUNG=y
420CONFIG_SERIAL_SAMSUNG_UARTS=4
403# CONFIG_SERIAL_SAMSUNG_DEBUG is not set 421# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
404CONFIG_SERIAL_SAMSUNG_CONSOLE=y 422CONFIG_SERIAL_SAMSUNG_CONSOLE=y
405CONFIG_SERIAL_S3C6400=y 423CONFIG_SERIAL_S3C6400=y
@@ -414,7 +432,52 @@ CONFIG_HW_RANDOM=y
414# CONFIG_R3964 is not set 432# CONFIG_R3964 is not set
415# CONFIG_RAW_DRIVER is not set 433# CONFIG_RAW_DRIVER is not set
416# CONFIG_TCG_TPM is not set 434# CONFIG_TCG_TPM is not set
417# CONFIG_I2C is not set 435CONFIG_I2C=y
436CONFIG_I2C_BOARDINFO=y
437CONFIG_I2C_CHARDEV=y
438CONFIG_I2C_HELPER_AUTO=y
439
440#
441# I2C Hardware Bus support
442#
443
444#
445# I2C system bus drivers (mostly embedded / system-on-chip)
446#
447# CONFIG_I2C_GPIO is not set
448# CONFIG_I2C_OCORES is not set
449CONFIG_I2C_S3C2410=y
450# CONFIG_I2C_SIMTEC is not set
451
452#
453# External I2C/SMBus adapter drivers
454#
455# CONFIG_I2C_PARPORT_LIGHT is not set
456# CONFIG_I2C_TAOS_EVM is not set
457
458#
459# Other I2C/SMBus bus drivers
460#
461# CONFIG_I2C_PCA_PLATFORM is not set
462# CONFIG_I2C_STUB is not set
463
464#
465# Miscellaneous I2C Chip support
466#
467# CONFIG_DS1682 is not set
468CONFIG_AT24=y
469# CONFIG_SENSORS_EEPROM is not set
470# CONFIG_SENSORS_PCF8574 is not set
471# CONFIG_PCF8575 is not set
472# CONFIG_SENSORS_PCA9539 is not set
473# CONFIG_SENSORS_PCF8591 is not set
474# CONFIG_TPS65010 is not set
475# CONFIG_SENSORS_MAX6875 is not set
476# CONFIG_SENSORS_TSL2550 is not set
477# CONFIG_I2C_DEBUG_CORE is not set
478# CONFIG_I2C_DEBUG_ALGO is not set
479# CONFIG_I2C_DEBUG_BUS is not set
480# CONFIG_I2C_DEBUG_CHIP is not set
418# CONFIG_SPI is not set 481# CONFIG_SPI is not set
419CONFIG_ARCH_REQUIRE_GPIOLIB=y 482CONFIG_ARCH_REQUIRE_GPIOLIB=y
420CONFIG_GPIOLIB=y 483CONFIG_GPIOLIB=y
@@ -424,6 +487,9 @@ CONFIG_GPIOLIB=y
424# 487#
425# I2C GPIO expanders: 488# I2C GPIO expanders:
426# 489#
490# CONFIG_GPIO_MAX732X is not set
491# CONFIG_GPIO_PCA953X is not set
492# CONFIG_GPIO_PCF857X is not set
427 493
428# 494#
429# PCI GPIO expanders: 495# PCI GPIO expanders:
@@ -436,14 +502,52 @@ CONFIG_GPIOLIB=y
436# CONFIG_POWER_SUPPLY is not set 502# CONFIG_POWER_SUPPLY is not set
437CONFIG_HWMON=y 503CONFIG_HWMON=y
438# CONFIG_HWMON_VID is not set 504# CONFIG_HWMON_VID is not set
505# CONFIG_SENSORS_AD7414 is not set
506# CONFIG_SENSORS_AD7418 is not set
507# CONFIG_SENSORS_ADM1021 is not set
508# CONFIG_SENSORS_ADM1025 is not set
509# CONFIG_SENSORS_ADM1026 is not set
510# CONFIG_SENSORS_ADM1029 is not set
511# CONFIG_SENSORS_ADM1031 is not set
512# CONFIG_SENSORS_ADM9240 is not set
513# CONFIG_SENSORS_ADT7470 is not set
514# CONFIG_SENSORS_ADT7473 is not set
515# CONFIG_SENSORS_ATXP1 is not set
516# CONFIG_SENSORS_DS1621 is not set
439# CONFIG_SENSORS_F71805F is not set 517# CONFIG_SENSORS_F71805F is not set
440# CONFIG_SENSORS_F71882FG is not set 518# CONFIG_SENSORS_F71882FG is not set
519# CONFIG_SENSORS_F75375S is not set
520# CONFIG_SENSORS_GL518SM is not set
521# CONFIG_SENSORS_GL520SM is not set
441# CONFIG_SENSORS_IT87 is not set 522# CONFIG_SENSORS_IT87 is not set
523# CONFIG_SENSORS_LM63 is not set
524# CONFIG_SENSORS_LM75 is not set
525# CONFIG_SENSORS_LM77 is not set
526# CONFIG_SENSORS_LM78 is not set
527# CONFIG_SENSORS_LM80 is not set
528# CONFIG_SENSORS_LM83 is not set
529# CONFIG_SENSORS_LM85 is not set
530# CONFIG_SENSORS_LM87 is not set
531# CONFIG_SENSORS_LM90 is not set
532# CONFIG_SENSORS_LM92 is not set
533# CONFIG_SENSORS_LM93 is not set
534# CONFIG_SENSORS_MAX1619 is not set
535# CONFIG_SENSORS_MAX6650 is not set
442# CONFIG_SENSORS_PC87360 is not set 536# CONFIG_SENSORS_PC87360 is not set
443# CONFIG_SENSORS_PC87427 is not set 537# CONFIG_SENSORS_PC87427 is not set
538# CONFIG_SENSORS_DME1737 is not set
444# CONFIG_SENSORS_SMSC47M1 is not set 539# CONFIG_SENSORS_SMSC47M1 is not set
540# CONFIG_SENSORS_SMSC47M192 is not set
445# CONFIG_SENSORS_SMSC47B397 is not set 541# CONFIG_SENSORS_SMSC47B397 is not set
542# CONFIG_SENSORS_ADS7828 is not set
543# CONFIG_SENSORS_THMC50 is not set
446# CONFIG_SENSORS_VT1211 is not set 544# CONFIG_SENSORS_VT1211 is not set
545# CONFIG_SENSORS_W83781D is not set
546# CONFIG_SENSORS_W83791D is not set
547# CONFIG_SENSORS_W83792D is not set
548# CONFIG_SENSORS_W83793 is not set
549# CONFIG_SENSORS_W83L785TS is not set
550# CONFIG_SENSORS_W83L786NG is not set
447# CONFIG_SENSORS_W83627HF is not set 551# CONFIG_SENSORS_W83627HF is not set
448# CONFIG_SENSORS_W83627EHF is not set 552# CONFIG_SENSORS_W83627EHF is not set
449# CONFIG_HWMON_DEBUG_CHIP is not set 553# CONFIG_HWMON_DEBUG_CHIP is not set
@@ -465,12 +569,13 @@ CONFIG_SSB_POSSIBLE=y
465# CONFIG_MFD_ASIC3 is not set 569# CONFIG_MFD_ASIC3 is not set
466# CONFIG_HTC_EGPIO is not set 570# CONFIG_HTC_EGPIO is not set
467# CONFIG_HTC_PASIC3 is not set 571# CONFIG_HTC_PASIC3 is not set
468# CONFIG_UCB1400_CORE is not set
469# CONFIG_MFD_TMIO is not set 572# CONFIG_MFD_TMIO is not set
470# CONFIG_MFD_T7L66XB is not set 573# CONFIG_MFD_T7L66XB is not set
471# CONFIG_MFD_TC6387XB is not set 574# CONFIG_MFD_TC6387XB is not set
472# CONFIG_MFD_TC6393XB is not set 575# CONFIG_MFD_TC6393XB is not set
576# CONFIG_PMIC_DA903X is not set
473# CONFIG_MFD_WM8400 is not set 577# CONFIG_MFD_WM8400 is not set
578# CONFIG_MFD_WM8350_I2C is not set
474 579
475# 580#
476# Multimedia devices 581# Multimedia devices
@@ -546,6 +651,7 @@ CONFIG_SDIO_UART=y
546# MMC/SD/SDIO Host Controller Drivers 651# MMC/SD/SDIO Host Controller Drivers
547# 652#
548CONFIG_MMC_SDHCI=y 653CONFIG_MMC_SDHCI=y
654CONFIG_MMC_SDHCI_S3C=y
549# CONFIG_MEMSTICK is not set 655# CONFIG_MEMSTICK is not set
550# CONFIG_ACCESSIBILITY is not set 656# CONFIG_ACCESSIBILITY is not set
551# CONFIG_NEW_LEDS is not set 657# CONFIG_NEW_LEDS is not set
@@ -691,11 +797,17 @@ CONFIG_FRAME_POINTER=y
691# CONFIG_FAULT_INJECTION is not set 797# CONFIG_FAULT_INJECTION is not set
692# CONFIG_LATENCYTOP is not set 798# CONFIG_LATENCYTOP is not set
693CONFIG_SYSCTL_SYSCALL_CHECK=y 799CONFIG_SYSCTL_SYSCALL_CHECK=y
694CONFIG_HAVE_FTRACE=y 800CONFIG_HAVE_FUNCTION_TRACER=y
695CONFIG_HAVE_DYNAMIC_FTRACE=y 801
696# CONFIG_FTRACE is not set 802#
803# Tracers
804#
805# CONFIG_FUNCTION_TRACER is not set
697# CONFIG_SCHED_TRACER is not set 806# CONFIG_SCHED_TRACER is not set
698# CONFIG_CONTEXT_SWITCH_TRACER is not set 807# CONFIG_CONTEXT_SWITCH_TRACER is not set
808# CONFIG_BOOT_TRACER is not set
809# CONFIG_STACK_TRACER is not set
810# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
699# CONFIG_SAMPLES is not set 811# CONFIG_SAMPLES is not set
700CONFIG_HAVE_ARCH_KGDB=y 812CONFIG_HAVE_ARCH_KGDB=y
701# CONFIG_KGDB is not set 813# CONFIG_KGDB is not set
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
new file mode 100644
index 000000000000..6c9fbb99ef14
--- /dev/null
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h
@@ -0,0 +1,34 @@
1/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C2410 - GPIO core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_GPIO_CORE_H
16#define __ASM_ARCH_GPIO_CORE_H __FILE__
17
18#include <plat/gpio-core.h>
19#include <mach/regs-gpio.h>
20
21extern struct s3c_gpio_chip s3c24xx_gpios[];
22
23static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
24{
25 struct s3c_gpio_chip *chip;
26
27 if (pin > S3C2410_GPG10)
28 return NULL;
29
30 chip = &s3c24xx_gpios[pin/32];
31 return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
32}
33
34#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 950c71bf1489..fa8764b05692 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -134,6 +134,8 @@
134#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ 134#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
135#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ 135#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
136 136
137#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
138
137#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) 139#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
138#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) 140#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
139#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) 141#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 918e3463297f..255fdfeaf957 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -92,7 +92,6 @@
92#define S3C24XX_PA_TIMER S3C2410_PA_TIMER 92#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
93#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV 93#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
94#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG 94#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
95#define S3C24XX_PA_IIC S3C2410_PA_IIC
96#define S3C24XX_PA_IIS S3C2410_PA_IIS 95#define S3C24XX_PA_IIS S3C2410_PA_IIS
97#define S3C24XX_PA_GPIO S3C2410_PA_GPIO 96#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
98#define S3C24XX_PA_RTC S3C2410_PA_RTC 97#define S3C24XX_PA_RTC S3C2410_PA_RTC
@@ -101,6 +100,8 @@
101#define S3C24XX_PA_SDI S3C2410_PA_SDI 100#define S3C24XX_PA_SDI S3C2410_PA_SDI
102#define S3C24XX_PA_NAND S3C2410_PA_NAND 101#define S3C24XX_PA_NAND S3C2410_PA_NAND
103 102
103#define S3C_PA_IIC S3C2410_PA_IIC
104#define S3C_PA_UART S3C24XX_PA_UART 104#define S3C_PA_UART S3C24XX_PA_UART
105#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
105 106
106#endif /* __ASM_ARCH_MAP_H */ 107#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index d061fea01900..6d6995afeb43 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -52,6 +52,7 @@
52#include <mach/regs-lcd.h> 52#include <mach/regs-lcd.h>
53#include <mach/regs-gpio.h> 53#include <mach/regs-gpio.h>
54 54
55#include <plat/iic.h>
55#include <plat/devs.h> 56#include <plat/devs.h>
56#include <plat/cpu.h> 57#include <plat/cpu.h>
57 58
@@ -150,7 +151,7 @@ static struct platform_device *amlm5900_devices[] __initdata = {
150#endif 151#endif
151 &s3c_device_adc, 152 &s3c_device_adc,
152 &s3c_device_wdt, 153 &s3c_device_wdt,
153 &s3c_device_i2c, 154 &s3c_device_i2c0,
154 &s3c_device_usb, 155 &s3c_device_usb,
155 &s3c_device_rtc, 156 &s3c_device_rtc,
156 &s3c_device_usbgadget, 157 &s3c_device_usbgadget,
@@ -233,6 +234,7 @@ static void __init amlm5900_init(void)
233#ifdef CONFIG_FB_S3C2410 234#ifdef CONFIG_FB_S3C2410
234 s3c24xx_fb_set_platdata(&amlm5900_fb_info); 235 s3c24xx_fb_set_platdata(&amlm5900_fb_info);
235#endif 236#endif
237 s3c_i2c0_set_platdata(NULL);
236 platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); 238 platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
237} 239}
238 240
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index c04c24444e0d..01bd76725b92 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -406,7 +406,7 @@ static struct platform_device bast_sio = {
406 * standard 100KHz i2c bus frequency 406 * standard 100KHz i2c bus frequency
407*/ 407*/
408 408
409static struct s3c2410_platform_i2c bast_i2c_info = { 409static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
410 .flags = 0, 410 .flags = 0,
411 .slave_addr = 0x10, 411 .slave_addr = 0x10,
412 .bus_freq = 100*1000, 412 .bus_freq = 100*1000,
@@ -553,7 +553,7 @@ static struct platform_device *bast_devices[] __initdata = {
553 &s3c_device_usb, 553 &s3c_device_usb,
554 &s3c_device_lcd, 554 &s3c_device_lcd,
555 &s3c_device_wdt, 555 &s3c_device_wdt,
556 &s3c_device_i2c, 556 &s3c_device_i2c0,
557 &s3c_device_rtc, 557 &s3c_device_rtc,
558 &s3c_device_nand, 558 &s3c_device_nand,
559 &bast_device_dm9k, 559 &bast_device_dm9k,
@@ -588,7 +588,8 @@ static void __init bast_map_io(void)
588 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); 588 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
589 589
590 s3c_device_nand.dev.platform_data = &bast_nand_info; 590 s3c_device_nand.dev.platform_data = &bast_nand_info;
591 s3c_device_i2c.dev.platform_data = &bast_i2c_info; 591
592 s3c_i2c0_set_platdata(&bast_i2c_info);
592 593
593 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); 594 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
594 s3c24xx_init_clocks(0); 595 s3c24xx_init_clocks(0);
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 836508b829bb..821a1668c3ac 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -39,6 +39,7 @@
39#include <mach/h1940-latch.h> 39#include <mach/h1940-latch.h>
40#include <mach/fb.h> 40#include <mach/fb.h>
41#include <plat/udc.h> 41#include <plat/udc.h>
42#include <plat/iic.h>
42 43
43#include <plat/clock.h> 44#include <plat/clock.h>
44#include <plat/devs.h> 45#include <plat/devs.h>
@@ -184,7 +185,7 @@ static struct platform_device *h1940_devices[] __initdata = {
184 &s3c_device_usb, 185 &s3c_device_usb,
185 &s3c_device_lcd, 186 &s3c_device_lcd,
186 &s3c_device_wdt, 187 &s3c_device_wdt,
187 &s3c_device_i2c, 188 &s3c_device_i2c0,
188 &s3c_device_iis, 189 &s3c_device_iis,
189 &s3c_device_usbgadget, 190 &s3c_device_usbgadget,
190 &s3c_device_leds, 191 &s3c_device_leds,
@@ -216,6 +217,7 @@ static void __init h1940_init(void)
216 217
217 s3c24xx_fb_set_platdata(&h1940_fb_info); 218 s3c24xx_fb_set_platdata(&h1940_fb_info);
218 s3c24xx_udc_set_platdata(&h1940_udc_cfg); 219 s3c24xx_udc_set_platdata(&h1940_udc_cfg);
220 s3c_i2c0_set_platdata(NULL);
219 221
220 /* Turn off suspend on both USB ports, and switch the 222 /* Turn off suspend on both USB ports, and switch the
221 * selectable USB port to USB device mode. */ 223 * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 7a7c45d28fe7..1269e59d2940 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -320,7 +320,7 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
320static struct platform_device *n30_devices[] __initdata = { 320static struct platform_device *n30_devices[] __initdata = {
321 &s3c_device_lcd, 321 &s3c_device_lcd,
322 &s3c_device_wdt, 322 &s3c_device_wdt,
323 &s3c_device_i2c, 323 &s3c_device_i2c0,
324 &s3c_device_iis, 324 &s3c_device_iis,
325 &s3c_device_usb, 325 &s3c_device_usb,
326 &s3c_device_usbgadget, 326 &s3c_device_usbgadget,
@@ -332,7 +332,7 @@ static struct platform_device *n30_devices[] __initdata = {
332static struct platform_device *n35_devices[] __initdata = { 332static struct platform_device *n35_devices[] __initdata = {
333 &s3c_device_lcd, 333 &s3c_device_lcd,
334 &s3c_device_wdt, 334 &s3c_device_wdt,
335 &s3c_device_i2c, 335 &s3c_device_i2c0,
336 &s3c_device_iis, 336 &s3c_device_iis,
337 &s3c_device_usbgadget, 337 &s3c_device_usbgadget,
338 &n35_button_device, 338 &n35_button_device,
@@ -501,7 +501,7 @@ static void __init n30_init_irq(void)
501static void __init n30_init(void) 501static void __init n30_init(void)
502{ 502{
503 s3c24xx_fb_set_platdata(&n30_fb_info); 503 s3c24xx_fb_set_platdata(&n30_fb_info);
504 s3c_device_i2c.dev.platform_data = &n30_i2ccfg; 504 s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
505 s3c24xx_udc_set_platdata(&n30_udc_cfg); 505 s3c24xx_udc_set_platdata(&n30_udc_cfg);
506 506
507 /* Turn off suspend on both USB ports, and switch the 507 /* Turn off suspend on both USB ports, and switch the
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index d8255cf87e44..f6c7261a4a12 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -35,6 +35,7 @@
35#include <plat/s3c2410.h> 35#include <plat/s3c2410.h>
36#include <plat/clock.h> 36#include <plat/clock.h>
37#include <plat/devs.h> 37#include <plat/devs.h>
38#include <plat/iic.h>
38#include <plat/cpu.h> 39#include <plat/cpu.h>
39 40
40static struct map_desc otom11_iodesc[] __initdata = { 41static struct map_desc otom11_iodesc[] __initdata = {
@@ -94,7 +95,7 @@ static struct platform_device *otom11_devices[] __initdata = {
94 &s3c_device_usb, 95 &s3c_device_usb,
95 &s3c_device_lcd, 96 &s3c_device_lcd,
96 &s3c_device_wdt, 97 &s3c_device_wdt,
97 &s3c_device_i2c, 98 &s3c_device_i2c0,
98 &s3c_device_iis, 99 &s3c_device_iis,
99 &s3c_device_rtc, 100 &s3c_device_rtc,
100 &otom_device_nor, 101 &otom_device_nor,
@@ -109,6 +110,7 @@ static void __init otom11_map_io(void)
109 110
110static void __init otom11_init(void) 111static void __init otom11_init(void)
111{ 112{
113 s3c_i2c0_set_platdata(NULL);
112 platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices)); 114 platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
113} 115}
114 116
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index ef868472f6a4..9678a53ceeb1 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -54,6 +54,7 @@
54#include <plat/udc.h> 54#include <plat/udc.h>
55#include <mach/spi.h> 55#include <mach/spi.h>
56#include <mach/spi-gpio.h> 56#include <mach/spi-gpio.h>
57#include <plat/iic.h>
57 58
58#include <plat/common-smdk.h> 59#include <plat/common-smdk.h>
59#include <plat/devs.h> 60#include <plat/devs.h>
@@ -247,7 +248,7 @@ static struct platform_device *qt2410_devices[] __initdata = {
247 &s3c_device_usb, 248 &s3c_device_usb,
248 &s3c_device_lcd, 249 &s3c_device_lcd,
249 &s3c_device_wdt, 250 &s3c_device_wdt,
250 &s3c_device_i2c, 251 &s3c_device_i2c0,
251 &s3c_device_iis, 252 &s3c_device_iis,
252 &s3c_device_sdi, 253 &s3c_device_sdi,
253 &s3c_device_usbgadget, 254 &s3c_device_usbgadget,
@@ -349,6 +350,7 @@ static void __init qt2410_machine_init(void)
349 s3c2410_gpio_setpin(S3C2410_GPB0, 1); 350 s3c2410_gpio_setpin(S3C2410_GPB0, 1);
350 351
351 s3c24xx_udc_set_platdata(&qt2410_udc_cfg); 352 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
353 s3c_i2c0_set_platdata(NULL);
352 354
353 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); 355 s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
354 356
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 152527bb2872..c49126ccb1d5 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -47,6 +47,7 @@
47#include <asm/mach-types.h> 47#include <asm/mach-types.h>
48 48
49#include <plat/regs-serial.h> 49#include <plat/regs-serial.h>
50#include <plat/iic.h>
50 51
51#include <plat/devs.h> 52#include <plat/devs.h>
52#include <plat/cpu.h> 53#include <plat/cpu.h>
@@ -89,7 +90,7 @@ static struct platform_device *smdk2410_devices[] __initdata = {
89 &s3c_device_usb, 90 &s3c_device_usb,
90 &s3c_device_lcd, 91 &s3c_device_lcd,
91 &s3c_device_wdt, 92 &s3c_device_wdt,
92 &s3c_device_i2c, 93 &s3c_device_i2c0,
93 &s3c_device_iis, 94 &s3c_device_iis,
94}; 95};
95 96
@@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void)
102 103
103static void __init smdk2410_init(void) 104static void __init smdk2410_init(void)
104{ 105{
106 s3c_i2c0_set_platdata(NULL);
105 platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices)); 107 platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
106 smdk_machine_init(); 108 smdk_machine_init();
107} 109}
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index 309dcf4c870a..8fdb0430bd48 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -45,6 +45,7 @@
45#include <asm/mach-types.h> 45#include <asm/mach-types.h>
46 46
47#include <plat/regs-serial.h> 47#include <plat/regs-serial.h>
48#include <plat/iic.h>
48#include <plat/devs.h> 49#include <plat/devs.h>
49#include <plat/cpu.h> 50#include <plat/cpu.h>
50 51
@@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
127static struct platform_device *tct_hammer_devices[] __initdata = { 128static struct platform_device *tct_hammer_devices[] __initdata = {
128 &s3c_device_adc, 129 &s3c_device_adc,
129 &s3c_device_wdt, 130 &s3c_device_wdt,
130 &s3c_device_i2c, 131 &s3c_device_i2c0,
131 &s3c_device_usb, 132 &s3c_device_usb,
132 &s3c_device_rtc, 133 &s3c_device_rtc,
133 &s3c_device_usbgadget, 134 &s3c_device_usbgadget,
@@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(void)
146 147
147static void __init tct_hammer_init(void) 148static void __init tct_hammer_init(void)
148{ 149{
150 s3c_i2c0_set_platdata(NULL);
149 platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); 151 platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
150} 152}
151 153
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 941353af16dc..61a1ea9c5c5c 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -47,6 +47,7 @@
47#include <plat/clock.h> 47#include <plat/clock.h>
48#include <plat/devs.h> 48#include <plat/devs.h>
49#include <plat/cpu.h> 49#include <plat/cpu.h>
50#include <plat/iic.h>
50 51
51#include "usb-simtec.h" 52#include "usb-simtec.h"
52#include "nor-simtec.h" 53#include "nor-simtec.h"
@@ -334,7 +335,7 @@ static struct platform_device *vr1000_devices[] __initdata = {
334 &s3c_device_usb, 335 &s3c_device_usb,
335 &s3c_device_lcd, 336 &s3c_device_lcd,
336 &s3c_device_wdt, 337 &s3c_device_wdt,
337 &s3c_device_i2c, 338 &s3c_device_i2c0,
338 &s3c_device_adc, 339 &s3c_device_adc,
339 &serial_device, 340 &serial_device,
340 &vr1000_dm9k0, 341 &vr1000_dm9k0,
@@ -384,6 +385,7 @@ static void __init vr1000_map_io(void)
384 385
385static void __init vr1000_init(void) 386static void __init vr1000_init(void)
386{ 387{
388 s3c_i2c0_set_platdata(NULL);
387 platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); 389 platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
388 390
389 i2c_register_board_info(0, vr1000_i2c_devs, 391 i2c_register_board_info(0, vr1000_i2c_devs,
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 5e758cf8bf82..2cd4044797cf 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -53,6 +53,7 @@
53#include <plat/cpu.h> 53#include <plat/cpu.h>
54#include <plat/pm.h> 54#include <plat/pm.h>
55#include <plat/udc.h> 55#include <plat/udc.h>
56#include <plat/iic.h>
56 57
57static struct map_desc jive_iodesc[] __initdata = { 58static struct map_desc jive_iodesc[] __initdata = {
58}; 59};
@@ -452,14 +453,14 @@ static struct spi_board_info __initdata jive_spi_devs[] = {
452 453
453/* I2C bus and device configuration. */ 454/* I2C bus and device configuration. */
454 455
455static struct s3c2410_platform_i2c jive_i2c_cfg = { 456static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
456 .max_freq = 80 * 1000, 457 .max_freq = 80 * 1000,
457 .bus_freq = 50 * 1000, 458 .bus_freq = 50 * 1000,
458 .flags = S3C_IICFLG_FILTER, 459 .flags = S3C_IICFLG_FILTER,
459 .sda_delay = 2, 460 .sda_delay = 2,
460}; 461};
461 462
462static struct i2c_board_info jive_i2c_devs[] = { 463static struct i2c_board_info jive_i2c_devs[] __initdata = {
463 [0] = { 464 [0] = {
464 I2C_BOARD_INFO("lis302dl", 0x1c), 465 I2C_BOARD_INFO("lis302dl", 0x1c),
465 .irq = IRQ_EINT14, 466 .irq = IRQ_EINT14,
@@ -472,7 +473,7 @@ static struct platform_device *jive_devices[] __initdata = {
472 &s3c_device_usb, 473 &s3c_device_usb,
473 &s3c_device_rtc, 474 &s3c_device_rtc,
474 &s3c_device_wdt, 475 &s3c_device_wdt,
475 &s3c_device_i2c, 476 &s3c_device_i2c0,
476 &s3c_device_lcd, 477 &s3c_device_lcd,
477 &jive_device_lcdspi, 478 &jive_device_lcdspi,
478 &jive_device_wm8750, 479 &jive_device_wm8750,
@@ -665,7 +666,7 @@ static void __init jive_machine_init(void)
665 666
666 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs)); 667 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
667 668
668 s3c_device_i2c.dev.platform_data = &jive_i2c_cfg; 669 s3c_i2c0_set_platdata(&jive_i2c_cfg);
669 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs)); 670 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
670 671
671 pm_power_off = jive_power_off; 672 pm_power_off = jive_power_off;
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 8fd17b8d5679..eba66aa6bd20 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -38,6 +38,7 @@
38 38
39#include <mach/idle.h> 39#include <mach/idle.h>
40#include <plat/udc.h> 40#include <plat/udc.h>
41#include <plat/iic.h>
41#include <mach/fb.h> 42#include <mach/fb.h>
42 43
43#include <plat/s3c2410.h> 44#include <plat/s3c2410.h>
@@ -105,7 +106,7 @@ static struct platform_device *smdk2413_devices[] __initdata = {
105 &s3c_device_usb, 106 &s3c_device_usb,
106 //&s3c_device_lcd, 107 //&s3c_device_lcd,
107 &s3c_device_wdt, 108 &s3c_device_wdt,
108 &s3c_device_i2c, 109 &s3c_device_i2c0,
109 &s3c_device_iis, 110 &s3c_device_iis,
110 &s3c_device_usbgadget, 111 &s3c_device_usbgadget,
111}; 112};
@@ -142,6 +143,7 @@ static void __init smdk2413_machine_init(void)
142 143
143 144
144 s3c24xx_udc_set_platdata(&smdk2413_udc_cfg); 145 s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
146 s3c_i2c0_set_platdata(NULL);
145 147
146 platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices)); 148 platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
147 smdk_machine_init(); 149 smdk_machine_init();
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index da32a6cb17ae..11e8ad49fc7b 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -39,6 +39,7 @@
39#include <mach/idle.h> 39#include <mach/idle.h>
40#include <mach/fb.h> 40#include <mach/fb.h>
41 41
42#include <plat/iic.h>
42#include <plat/nand.h> 43#include <plat/nand.h>
43 44
44#include <plat/s3c2410.h> 45#include <plat/s3c2410.h>
@@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstms_nand_info = {
122static struct platform_device *vstms_devices[] __initdata = { 123static struct platform_device *vstms_devices[] __initdata = {
123 &s3c_device_usb, 124 &s3c_device_usb,
124 &s3c_device_wdt, 125 &s3c_device_wdt,
125 &s3c_device_i2c, 126 &s3c_device_i2c0,
126 &s3c_device_iis, 127 &s3c_device_iis,
127 &s3c_device_rtc, 128 &s3c_device_rtc,
128 &s3c_device_nand, 129 &s3c_device_nand,
@@ -151,6 +152,7 @@ static void __init vstms_map_io(void)
151 152
152static void __init vstms_init(void) 153static void __init vstms_init(void)
153{ 154{
155 s3c_i2c0_set_platdata(NULL);
154 platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); 156 platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
155} 157}
156 158
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index f151f8939929..b05d56e230a1 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -40,6 +40,7 @@
40#include <mach/regs-mem.h> 40#include <mach/regs-mem.h>
41#include <mach/regs-lcd.h> 41#include <mach/regs-lcd.h>
42#include <plat/nand.h> 42#include <plat/nand.h>
43#include <plat/iic.h>
43 44
44#include <linux/mtd/mtd.h> 45#include <linux/mtd/mtd.h>
45#include <linux/mtd/nand.h> 46#include <linux/mtd/nand.h>
@@ -409,7 +410,7 @@ static struct platform_device *anubis_devices[] __initdata = {
409 &s3c_device_usb, 410 &s3c_device_usb,
410 &s3c_device_wdt, 411 &s3c_device_wdt,
411 &s3c_device_adc, 412 &s3c_device_adc,
412 &s3c_device_i2c, 413 &s3c_device_i2c0,
413 &s3c_device_rtc, 414 &s3c_device_rtc,
414 &s3c_device_nand, 415 &s3c_device_nand,
415 &anubis_device_ide0, 416 &anubis_device_ide0,
@@ -473,6 +474,7 @@ static void __init anubis_map_io(void)
473 474
474static void __init anubis_init(void) 475static void __init anubis_init(void)
475{ 476{
477 s3c_i2c0_set_platdata(NULL);
476 platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); 478 platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
477 479
478 i2c_register_board_info(0, anubis_i2c_devs, 480 i2c_register_board_info(0, anubis_i2c_devs,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 4539b1d95877..0a6d0a5d961b 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -37,6 +37,7 @@
37#include <mach/regs-mem.h> 37#include <mach/regs-mem.h>
38#include <mach/regs-lcd.h> 38#include <mach/regs-lcd.h>
39#include <plat/nand.h> 39#include <plat/nand.h>
40#include <plat/iic.h>
40 41
41#include <linux/mtd/mtd.h> 42#include <linux/mtd/mtd.h>
42#include <linux/mtd/nand.h> 43#include <linux/mtd/nand.h>
@@ -205,7 +206,7 @@ static struct platform_device *at2440evb_devices[] __initdata = {
205 &s3c_device_usb, 206 &s3c_device_usb,
206 &s3c_device_wdt, 207 &s3c_device_wdt,
207 &s3c_device_adc, 208 &s3c_device_adc,
208 &s3c_device_i2c, 209 &s3c_device_i2c0,
209 &s3c_device_rtc, 210 &s3c_device_rtc,
210 &s3c_device_nand, 211 &s3c_device_nand,
211 &s3c_device_sdi, 212 &s3c_device_sdi,
@@ -227,6 +228,8 @@ static void __init at2440evb_map_io(void)
227static void __init at2440evb_init(void) 228static void __init at2440evb_init(void)
228{ 229{
229 s3c24xx_fb_set_platdata(&at2440evb_fb_info); 230 s3c24xx_fb_set_platdata(&at2440evb_fb_info);
231 s3c_i2c0_set_platdata(NULL);
232
230 platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); 233 platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
231} 234}
232 235
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index a546307fd53d..7aeaa972d7f5 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -37,6 +37,7 @@
37//#include <asm/debug-ll.h> 37//#include <asm/debug-ll.h>
38#include <mach/regs-gpio.h> 38#include <mach/regs-gpio.h>
39#include <plat/regs-serial.h> 39#include <plat/regs-serial.h>
40#include <plat/iic.h>
40 41
41#include <plat/s3c2410.h> 42#include <plat/s3c2410.h>
42#include <plat/s3c2440.h> 43#include <plat/s3c2440.h>
@@ -107,7 +108,7 @@ static struct platform_device *nexcoder_devices[] __initdata = {
107 &s3c_device_usb, 108 &s3c_device_usb,
108 &s3c_device_lcd, 109 &s3c_device_lcd,
109 &s3c_device_wdt, 110 &s3c_device_wdt,
110 &s3c_device_i2c, 111 &s3c_device_i2c0,
111 &s3c_device_iis, 112 &s3c_device_iis,
112 &s3c_device_rtc, 113 &s3c_device_rtc,
113 &s3c_device_camif, 114 &s3c_device_camif,
@@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void)
142 143
143static void __init nexcoder_init(void) 144static void __init nexcoder_init(void)
144{ 145{
146 s3c_i2c0_set_platdata(NULL);
145 platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices)); 147 platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
146}; 148};
147 149
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 884a3c7ae75f..41a00f57e5da 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -38,6 +38,7 @@
38#include <mach/regs-mem.h> 38#include <mach/regs-mem.h>
39#include <mach/regs-lcd.h> 39#include <mach/regs-lcd.h>
40#include <plat/nand.h> 40#include <plat/nand.h>
41#include <plat/iic.h>
41 42
42#include <linux/mtd/mtd.h> 43#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h> 44#include <linux/mtd/nand.h>
@@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = {
335/* Standard Osiris devices */ 336/* Standard Osiris devices */
336 337
337static struct platform_device *osiris_devices[] __initdata = { 338static struct platform_device *osiris_devices[] __initdata = {
338 &s3c_device_i2c, 339 &s3c_device_i2c0,
339 &s3c_device_wdt, 340 &s3c_device_wdt,
340 &s3c_device_nand, 341 &s3c_device_nand,
341 &osiris_pcmcia, 342 &osiris_pcmcia,
@@ -398,6 +399,8 @@ static void __init osiris_init(void)
398 sysdev_class_register(&osiris_pm_sysclass); 399 sysdev_class_register(&osiris_pm_sysclass);
399 sysdev_register(&osiris_pm_sysdev); 400 sysdev_register(&osiris_pm_sysdev);
400 401
402 s3c_i2c0_set_platdata(NULL);
403
401 i2c_register_board_info(0, osiris_i2c_devs, 404 i2c_register_board_info(0, osiris_i2c_devs,
402 ARRAY_SIZE(osiris_i2c_devs)); 405 ARRAY_SIZE(osiris_i2c_devs));
403 406
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index fbd081de592f..12d378f84ad2 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -179,7 +179,7 @@ static struct platform_device *rx3715_devices[] __initdata = {
179 &s3c_device_usb, 179 &s3c_device_usb,
180 &s3c_device_lcd, 180 &s3c_device_lcd,
181 &s3c_device_wdt, 181 &s3c_device_wdt,
182 &s3c_device_i2c, 182 &s3c_device_i2c0,
183 &s3c_device_iis, 183 &s3c_device_iis,
184 &s3c_device_nand, 184 &s3c_device_nand,
185}; 185};
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index fefeaaa4155f..db6eafbd4d90 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -37,6 +37,7 @@
37 37
38#include <mach/idle.h> 38#include <mach/idle.h>
39#include <mach/fb.h> 39#include <mach/fb.h>
40#include <plat/iic.h>
40 41
41#include <plat/s3c2410.h> 42#include <plat/s3c2410.h>
42#include <plat/s3c2440.h> 43#include <plat/s3c2440.h>
@@ -152,7 +153,7 @@ static struct platform_device *smdk2440_devices[] __initdata = {
152 &s3c_device_usb, 153 &s3c_device_usb,
153 &s3c_device_lcd, 154 &s3c_device_lcd,
154 &s3c_device_wdt, 155 &s3c_device_wdt,
155 &s3c_device_i2c, 156 &s3c_device_i2c0,
156 &s3c_device_iis, 157 &s3c_device_iis,
157}; 158};
158 159
@@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void)
166static void __init smdk2440_machine_init(void) 167static void __init smdk2440_machine_init(void)
167{ 168{
168 s3c24xx_fb_set_platdata(&smdk2440_fb_info); 169 s3c24xx_fb_set_platdata(&smdk2440_fb_info);
170 s3c_i2c0_set_platdata(NULL);
169 171
170 platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices)); 172 platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
171 smdk_machine_init(); 173 smdk_machine_init();
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index 14252f573754..212141baebec 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -24,6 +24,7 @@ config MACH_SMDK2443
24 bool "SMDK2443" 24 bool "SMDK2443"
25 select CPU_S3C2443 25 select CPU_S3C2443
26 select MACH_SMDK 26 select MACH_SMDK
27 select S3C_DEV_HSMMC
27 help 28 help
28 Say Y here if you are using an SMDK2443 29 Say Y here if you are using an SMDK2443
29 30
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index a7fe65f3dcc1..039a46243105 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -37,6 +37,7 @@
37 37
38#include <mach/idle.h> 38#include <mach/idle.h>
39#include <mach/fb.h> 39#include <mach/fb.h>
40#include <plat/iic.h>
40 41
41#include <plat/s3c2410.h> 42#include <plat/s3c2410.h>
42#include <plat/s3c2440.h> 43#include <plat/s3c2440.h>
@@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
103 104
104static struct platform_device *smdk2443_devices[] __initdata = { 105static struct platform_device *smdk2443_devices[] __initdata = {
105 &s3c_device_wdt, 106 &s3c_device_wdt,
106 &s3c_device_i2c, 107 &s3c_device_i2c0,
107 &s3c_device_hsmmc, 108 &s3c_device_hsmmc0,
108}; 109};
109 110
110static void __init smdk2443_map_io(void) 111static void __init smdk2443_map_io(void)
@@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void)
116 117
117static void __init smdk2443_machine_init(void) 118static void __init smdk2443_machine_init(void)
118{ 119{
120 s3c_i2c0_set_platdata(NULL);
119 platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices)); 121 platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
120 smdk_machine_init(); 122 smdk_machine_init();
121} 123}
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
index 6667355a47a1..a01132717e34 100644
--- a/arch/arm/mach-s3c24a0/include/mach/map.h
+++ b/arch/arm/mach-s3c24a0/include/mach/map.h
@@ -71,7 +71,6 @@
71#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER 71#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
72#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV 72#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
73#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG 73#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
74#define S3C24XX_PA_IIC S3C24A0_PA_IIC
75#define S3C24XX_PA_IIS S3C24A0_PA_IIS 74#define S3C24XX_PA_IIS S3C24A0_PA_IIS
76#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO 75#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
77#define S3C24XX_PA_RTC S3C24A0_PA_RTC 76#define S3C24XX_PA_RTC S3C24A0_PA_RTC
@@ -81,5 +80,6 @@
81#define S3C24XX_PA_NAND S3C24A0_PA_NAND 80#define S3C24XX_PA_NAND S3C24A0_PA_NAND
82 81
83#define S3C_PA_UART S3C24A0_PA_UART 82#define S3C_PA_UART S3C24A0_PA_UART
83#define S3C_PA_IIC S3C24A0_PA_IIC
84 84
85#endif /* __ASM_ARCH_24A0_MAP_H */ 85#endif /* __ASM_ARCH_24A0_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/gpio-core.h b/arch/arm/mach-s3c6400/include/mach/gpio-core.h
new file mode 100644
index 000000000000..d89aae68b0a5
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/gpio-core.h
@@ -0,0 +1,21 @@
1/* arch/arm/mach-s3c6400/include/mach/gpio-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIO core support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_GPIO_CORE_H
16#define __ASM_ARCH_GPIO_CORE_H __FILE__
17
18/* currently we just include the platform support */
19#include <plat/gpio-core.h>
20
21#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/gpio.h b/arch/arm/mach-s3c6400/include/mach/gpio.h
index 8b4254a23d9a..e8e35e8fe731 100644
--- a/arch/arm/mach-s3c6400/include/mach/gpio.h
+++ b/arch/arm/mach-s3c6400/include/mach/gpio.h
@@ -17,6 +17,80 @@
17#define gpio_cansleep __gpio_cansleep 17#define gpio_cansleep __gpio_cansleep
18#define gpio_to_irq __gpio_to_irq 18#define gpio_to_irq __gpio_to_irq
19 19
20#define ARCH_NR_GPIOS 188 20/* GPIO bank sizes */
21#define S3C64XX_GPIO_A_NR (8)
22#define S3C64XX_GPIO_B_NR (7)
23#define S3C64XX_GPIO_C_NR (8)
24#define S3C64XX_GPIO_D_NR (5)
25#define S3C64XX_GPIO_E_NR (5)
26#define S3C64XX_GPIO_F_NR (16)
27#define S3C64XX_GPIO_G_NR (7)
28#define S3C64XX_GPIO_H_NR (10)
29#define S3C64XX_GPIO_I_NR (16)
30#define S3C64XX_GPIO_J_NR (12)
31#define S3C64XX_GPIO_K_NR (16)
32#define S3C64XX_GPIO_L_NR (15)
33#define S3C64XX_GPIO_M_NR (6)
34#define S3C64XX_GPIO_N_NR (16)
35#define S3C64XX_GPIO_O_NR (16)
36#define S3C64XX_GPIO_P_NR (15)
37#define S3C64XX_GPIO_Q_NR (9)
38
39/* GPIO bank numbes */
40
41/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
42 * space for debugging purposes so that any accidental
43 * change from one gpio bank to another can be caught.
44*/
45
46#define S3C64XX_GPIO_NEXT(__gpio) \
47 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
48
49enum s3c_gpio_number {
50 S3C64XX_GPIO_A_START = 0,
51 S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
52 S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
53 S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
54 S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
55 S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
56 S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
57 S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
58 S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
59 S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
60 S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
61 S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
62 S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
63 S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
64 S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
65 S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
66 S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
67};
68
69/* S3C64XX GPIO number definitions. */
70
71#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
72#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
73#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
74#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
75#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
76#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
77#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
78#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
79#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
80#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
81#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
82#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
83#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
84#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
85#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
86#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
87#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
88
89/* the end of the S3C64XX specific gpios */
90#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
91#define S3C_GPIO_END S3C64XX_GPIO_END
92
93/* define the number of gpios we need to the one after the GPQ() range */
94#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
21 95
22#include <asm-generic/gpio.h> 96#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 618f09d637b2..cff27d813fc6 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -17,6 +17,12 @@
17 17
18#include <plat/map-base.h> 18#include <plat/map-base.h>
19 19
20/* HSMMC units */
21#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
22#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
23#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
24#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
25
20#define S3C_PA_UART (0x7F005000) 26#define S3C_PA_UART (0x7F005000)
21#define S3C_PA_UART0 (S3C_PA_UART + 0x00) 27#define S3C_PA_UART0 (S3C_PA_UART + 0x00)
22#define S3C_PA_UART1 (S3C_PA_UART + 0x400) 28#define S3C_PA_UART1 (S3C_PA_UART + 0x400)
@@ -32,8 +38,11 @@
32#define S3C_VA_UART2 S3C_VA_UARTx(2) 38#define S3C_VA_UART2 S3C_VA_UARTx(2)
33#define S3C_VA_UART3 S3C_VA_UARTx(3) 39#define S3C_VA_UART3 S3C_VA_UARTx(3)
34 40
41#define S3C64XX_PA_FB (0x77100000)
35#define S3C64XX_PA_SYSCON (0x7E00F000) 42#define S3C64XX_PA_SYSCON (0x7E00F000)
36#define S3C64XX_PA_TIMER (0x7F006000) 43#define S3C64XX_PA_TIMER (0x7F006000)
44#define S3C64XX_PA_IIC0 (0x7F004000)
45#define S3C64XX_PA_IIC1 (0x7F00F000)
37 46
38#define S3C64XX_PA_GPIO (0x7F008000) 47#define S3C64XX_PA_GPIO (0x7F008000)
39#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000) 48#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000)
@@ -49,5 +58,11 @@
49 58
50/* compatibiltiy defines. */ 59/* compatibiltiy defines. */
51#define S3C_PA_TIMER S3C64XX_PA_TIMER 60#define S3C_PA_TIMER S3C64XX_PA_TIMER
61#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
62#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
63#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
64#define S3C_PA_IIC S3C64XX_PA_IIC0
65#define S3C_PA_IIC1 S3C64XX_PA_IIC1
66#define S3C_PA_FB S3C64XX_PA_FB
52 67
53#endif /* __ASM_ARCH_6400_MAP_H */ 68#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
new file mode 100644
index 000000000000..47019795ce06
--- /dev/null
+++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
@@ -0,0 +1,259 @@
1/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C64XX - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
13 *
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
16 * that are the same.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21*/
22
23/* include the core definitions here, in case we really do need to
24 * override them at a later date.
25*/
26
27#include <plat/regs-fb.h>
28
29#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31
32/* Video timing controls */
33#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18)
36
37/* Window position controls */
38
39#define WINCON(_win) (0x20 + ((_win) * 4))
40
41/* OSD1 and OSD4 do not have register D */
42
43#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
44#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
45#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
46#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
47
48/* Video buffer addresses */
49
50#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
51#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
52#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
53#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
54#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
55
56#define VIDINTCON0 (0x130)
57
58#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
59
60/* WINCONx */
61
62#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
63#define WINCONx_CSCWIDTH_SHIFT (26)
64#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
65#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
66
67#define WINCONx_ENLOCAL (1 << 22)
68#define WINCONx_BUFSTATUS (1 << 21)
69#define WINCONx_BUFSEL (1 << 20)
70#define WINCONx_BUFAUTOEN (1 << 19)
71#define WINCONx_YCbCr (1 << 13)
72
73#define WINCON1_LOCALSEL_CAMIF (1 << 23)
74
75#define WINCON2_LOCALSEL_CAMIF (1 << 23)
76#define WINCON2_BLD_PIX (1 << 6)
77
78#define WINCON2_ALPHA_SEL (1 << 1)
79#define WINCON2_BPPMODE_MASK (0xf << 2)
80#define WINCON2_BPPMODE_SHIFT (2)
81#define WINCON2_BPPMODE_1BPP (0x0 << 2)
82#define WINCON2_BPPMODE_2BPP (0x1 << 2)
83#define WINCON2_BPPMODE_4BPP (0x2 << 2)
84#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
85#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
86#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
87#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
88#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
89#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
90#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
91#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
92#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
93#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
94#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
95
96#define WINCON3_BLD_PIX (1 << 6)
97
98#define WINCON3_ALPHA_SEL (1 << 1)
99#define WINCON3_BPPMODE_MASK (0xf << 2)
100#define WINCON3_BPPMODE_SHIFT (2)
101#define WINCON3_BPPMODE_1BPP (0x0 << 2)
102#define WINCON3_BPPMODE_2BPP (0x1 << 2)
103#define WINCON3_BPPMODE_4BPP (0x2 << 2)
104#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
105#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
106#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
107#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
108#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
109#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
110#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
111#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
112#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
113#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
114
115#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
116#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
117#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
118
119#define DITHMODE (0x170)
120#define WINxMAP(_win) (0x180 + ((_win) * 4))
121
122
123#define DITHMODE_R_POS_MASK (0x3 << 5)
124#define DITHMODE_R_POS_SHIFT (5)
125#define DITHMODE_R_POS_8BIT (0x0 << 5)
126#define DITHMODE_R_POS_6BIT (0x1 << 5)
127#define DITHMODE_R_POS_5BIT (0x2 << 5)
128
129#define DITHMODE_G_POS_MASK (0x3 << 3)
130#define DITHMODE_G_POS_SHIFT (3)
131#define DITHMODE_G_POS_8BIT (0x0 << 3)
132#define DITHMODE_G_POS_6BIT (0x1 << 3)
133#define DITHMODE_G_POS_5BIT (0x2 << 3)
134
135#define DITHMODE_B_POS_MASK (0x3 << 1)
136#define DITHMODE_B_POS_SHIFT (1)
137#define DITHMODE_B_POS_8BIT (0x0 << 1)
138#define DITHMODE_B_POS_6BIT (0x1 << 1)
139#define DITHMODE_B_POS_5BIT (0x2 << 1)
140
141#define DITHMODE_DITH_EN (1 << 0)
142
143#define WPALCON (0x1A0)
144
145#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
146#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
147#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
148
149/* Palette registers */
150
151#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
152#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
153#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
154#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
155#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
156
157/* system specific implementation code for palette sizes, and other
158 * information that changes depending on which architecture is being
159 * compiled.
160*/
161
162/* return true if window _win has OSD register D */
163#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
164
165static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
166{
167 if (win < 2)
168 return 256;
169 if (win < 4)
170 return 16;
171 if (win == 4)
172 return 4;
173
174 BUG(); /* shouldn't get here */
175}
176
177static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
178{
179 /* all windows can do 1/2 bpp */
180
181 if ((bpp == 25 || bpp == 19) && win == 0)
182 return 0; /* win 0 does not have 19 or 25bpp modes */
183
184 if (bpp == 4 && win == 4)
185 return 0;
186
187 if (bpp == 8 && (win >= 3))
188 return 0; /* win 3/4 cannot do 8bpp in any mode */
189
190 return 1;
191}
192
193static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
194{
195 switch (window) {
196 case 0: return WIN0_PAL(reg);
197 case 1: return WIN1_PAL(reg);
198 case 2: return WIN2_PAL(reg);
199 case 3: return WIN3_PAL(reg);
200 case 4: return WIN4_PAL(reg);
201 }
202
203 BUG();
204}
205
206static inline int s3c_fb_pal_is16(unsigned int window)
207{
208 return window > 1;
209}
210
211struct s3c_fb_palette {
212 struct fb_bitfield r;
213 struct fb_bitfield g;
214 struct fb_bitfield b;
215 struct fb_bitfield a;
216};
217
218static inline void s3c_fb_init_palette(unsigned int window,
219 struct s3c_fb_palette *palette)
220{
221 if (window < 2) {
222 /* Windows 0/1 are 8/8/8 or A/8/8/8 */
223 palette->r.offset = 16;
224 palette->r.length = 8;
225 palette->g.offset = 8;
226 palette->g.length = 8;
227 palette->b.offset = 0;
228 palette->b.length = 8;
229 } else {
230 /* currently we assume RGB 5/6/5 */
231 palette->r.offset = 11;
232 palette->r.length = 5;
233 palette->g.offset = 5;
234 palette->g.length = 6;
235 palette->b.offset = 0;
236 palette->b.length = 5;
237 }
238}
239
240/* Notes on per-window bpp settings
241 *
242 * Value Win0 Win1 Win2 Win3 Win 4
243 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
244 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
245 * 0010 4(P) 4(P) 4(P) 4(P) -none-
246 * 0011 8(P) 8(P) -none- -none- -none-
247 * 0100 -none- 8(A232) 8(A232) -none- -none-
248 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
249 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
250 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
251 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
252 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
253 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
254 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
255 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
256 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
257 * 1110 -none- -none- -none- -none- -none-
258 * 1111 -none- -none- -none- -none- -none-
259*/
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
index 75b1244cf8ab..1d5010070027 100644
--- a/arch/arm/mach-s3c6410/Kconfig
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -14,8 +14,49 @@ config CPU_S3C6410
14 help 14 help
15 Enable S3C6410 CPU support 15 Enable S3C6410 CPU support
16 16
17config S3C6410_SETUP_SDHCI
18 bool
19 help
20 Internal helper functions for S3C6410 based SDHCI systems
21
17config MACH_SMDK6410 22config MACH_SMDK6410
18 bool "SMDK6410" 23 bool "SMDK6410"
19 select CPU_S3C6410 24 select CPU_S3C6410
25 select S3C_DEV_HSMMC
26 select S3C_DEV_HSMMC1
27 select S3C_DEV_I2C1
28 select S3C_DEV_FB
29 select S3C6410_SETUP_SDHCI
30 select S3C64XX_SETUP_I2C1
31 select S3C64XX_SETUP_FB_24BPP
20 help 32 help
21 Machine support for the Samsung SMDK6410 33 Machine support for the Samsung SMDK6410
34
35# At least some of the SMDK6410s were shipped with the card detect
36# for the MMC/SD slots connected to the same input. This means that
37# either the boards need to be altered to have channel0 to an alternate
38# configuration or that only one slot can be used.
39
40choice
41 prompt "SMDK6410 MMC/SD slot setup"
42 depends on MACH_SMDK6410
43
44config SMDK6410_SD_CH0
45 bool "Use channel 0 only"
46 depends on MACH_SMDK6410
47 help
48 Select CON7 (channel 0) as the MMC/SD slot, as
49 at least some SMDK6410 boards come with the
50 resistors fitted so that the card detects for
51 channels 0 and 1 are the same.
52
53config SMDK6410_SD_CH1
54 bool "Use channel 1 only"
55 depends on MACH_SMDK6410
56 help
57 Select CON6 (channel 1) as the MMC/SD slot, as
58 at least some SMDK6410 boards come with the
59 resistors fitted so that the card detects for
60 channels 0 and 1 are the same.
61
62endchoice
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
index 4a20a009990a..2cd4f189036b 100644
--- a/arch/arm/mach-s3c6410/Makefile
+++ b/arch/arm/mach-s3c6410/Makefile
@@ -14,6 +14,10 @@ obj- :=
14 14
15obj-$(CONFIG_CPU_S3C6410) += cpu.o 15obj-$(CONFIG_CPU_S3C6410) += cpu.o
16 16
17# Helper and device support
18
19obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
20
17# machine support 21# machine support
18 22
19obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o 23obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index 975cf88f0e84..6a73ca6b7a3a 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -35,6 +35,8 @@
35#include <plat/cpu.h> 35#include <plat/cpu.h>
36#include <plat/devs.h> 36#include <plat/devs.h>
37#include <plat/clock.h> 37#include <plat/clock.h>
38#include <plat/sdhci.h>
39#include <plat/iic-core.h>
38#include <plat/s3c6400.h> 40#include <plat/s3c6400.h>
39#include <plat/s3c6410.h> 41#include <plat/s3c6410.h>
40 42
@@ -51,6 +53,14 @@ static struct map_desc s3c6410_iodesc[] __initdata = {
51void __init s3c6410_map_io(void) 53void __init s3c6410_map_io(void)
52{ 54{
53 iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc)); 55 iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
56
57 /* initialise device information early */
58 s3c6410_default_sdhci0();
59 s3c6410_default_sdhci1();
60
61 /* the i2c devices are directly compatible with s3c2440 */
62 s3c_i2c0_setname("s3c2440-i2c");
63 s3c_i2c1_setname("s3c2440-i2c");
54} 64}
55 65
56void __init s3c6410_init_clocks(int xtal) 66void __init s3c6410_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 9213a8ba283b..3c4d47145c83 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -20,18 +20,27 @@
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/i2c.h>
24#include <linux/fb.h>
25#include <linux/gpio.h>
26#include <linux/delay.h>
27
28#include <video/platform_lcd.h>
23 29
24#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 31#include <asm/mach/map.h>
26#include <asm/mach/irq.h> 32#include <asm/mach/irq.h>
27 33
28#include <mach/hardware.h> 34#include <mach/hardware.h>
35#include <mach/regs-fb.h>
29#include <mach/map.h> 36#include <mach/map.h>
30 37
31#include <asm/irq.h> 38#include <asm/irq.h>
32#include <asm/mach-types.h> 39#include <asm/mach-types.h>
33 40
34#include <plat/regs-serial.h> 41#include <plat/regs-serial.h>
42#include <plat/iic.h>
43#include <plat/fb.h>
35 44
36#include <plat/s3c6410.h> 45#include <plat/s3c6410.h>
37#include <plat/clock.h> 46#include <plat/clock.h>
@@ -59,9 +68,89 @@ static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
59 }, 68 },
60}; 69};
61 70
71/* framebuffer and LCD setup. */
72
73/* GPF15 = LCD backlight control
74 * GPF13 => Panel power
75 * GPN5 = LCD nRESET signal
76 * PWM_TOUT1 => backlight brightness
77 */
78
79static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
80 unsigned int power)
81{
82 if (power) {
83 gpio_direction_output(S3C64XX_GPF(13), 1);
84 gpio_direction_output(S3C64XX_GPF(15), 1);
85
86 /* fire nRESET on power up */
87 gpio_direction_output(S3C64XX_GPN(5), 0);
88 msleep(10);
89 gpio_direction_output(S3C64XX_GPN(5), 1);
90 msleep(1);
91 } else {
92 gpio_direction_output(S3C64XX_GPF(15), 0);
93 gpio_direction_output(S3C64XX_GPF(13), 0);
94 }
95}
96
97static struct plat_lcd_data smdk6410_lcd_power_data = {
98 .set_power = smdk6410_lcd_power_set,
99};
100
101static struct platform_device smdk6410_lcd_powerdev = {
102 .name = "platform-lcd",
103 .dev.parent = &s3c_device_fb.dev,
104 .dev.platform_data = &smdk6410_lcd_power_data,
105};
106
107static struct s3c_fb_pd_win smdk6410_fb_win0 = {
108 /* this is to ensure we use win0 */
109 .win_mode = {
110 .pixclock = 41094,
111 .left_margin = 8,
112 .right_margin = 13,
113 .upper_margin = 7,
114 .lower_margin = 5,
115 .hsync_len = 3,
116 .vsync_len = 1,
117 .xres = 800,
118 .yres = 480,
119 },
120 .max_bpp = 32,
121 .default_bpp = 16,
122};
123
124/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
125static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
126 .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
127 .win[0] = &smdk6410_fb_win0,
128 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
129 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
130};
131
62struct map_desc smdk6410_iodesc[] = {}; 132struct map_desc smdk6410_iodesc[] = {};
63 133
64static struct platform_device *smdk6410_devices[] __initdata = { 134static struct platform_device *smdk6410_devices[] __initdata = {
135#ifdef CONFIG_SMDK6410_SD_CH0
136 &s3c_device_hsmmc0,
137#endif
138#ifdef CONFIG_SMDK6410_SD_CH1
139 &s3c_device_hsmmc1,
140#endif
141 &s3c_device_i2c0,
142 &s3c_device_i2c1,
143 &s3c_device_fb,
144 &smdk6410_lcd_powerdev,
145};
146
147static struct i2c_board_info i2c_devs0[] __initdata = {
148 { I2C_BOARD_INFO("24c08", 0x50), },
149 { I2C_BOARD_INFO("WM8580", 0X1b), },
150};
151
152static struct i2c_board_info i2c_devs1[] __initdata = {
153 { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
65}; 154};
66 155
67static void __init smdk6410_map_io(void) 156static void __init smdk6410_map_io(void)
@@ -73,6 +162,13 @@ static void __init smdk6410_map_io(void)
73 162
74static void __init smdk6410_machine_init(void) 163static void __init smdk6410_machine_init(void)
75{ 164{
165 s3c_i2c0_set_platdata(NULL);
166 s3c_i2c1_set_platdata(NULL);
167 s3c_fb_set_platdata(&smdk6410_lcd_pdata);
168
169 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
170 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
171
76 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); 172 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
77} 173}
78 174
diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c
new file mode 100644
index 000000000000..0b5788bd5985
--- /dev/null
+++ b/arch/arm/mach-s3c6410/setup-sdhci.c
@@ -0,0 +1,102 @@
1/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/platform_device.h>
19#include <linux/io.h>
20
21#include <linux/mmc/card.h>
22#include <linux/mmc/host.h>
23
24#include <mach/gpio.h>
25#include <plat/gpio-cfg.h>
26#include <plat/regs-sdhci.h>
27#include <plat/sdhci.h>
28
29/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
30
31char *s3c6410_hsmmc_clksrcs[4] = {
32 [0] = "hsmmc",
33 [1] = "hsmmc",
34 [2] = "mmc_bus",
35 /* [3] = "48m", - note not succesfully used yet */
36};
37
38void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
39{
40 unsigned int gpio;
41 unsigned int end;
42
43 end = S3C64XX_GPG(2 + width);
44
45 /* Set all the necessary GPG pins to special-function 0 */
46 for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
47 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
48 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
49 }
50
51 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
52 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
53}
54
55void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
56 void __iomem *r,
57 struct mmc_ios *ios,
58 struct mmc_card *card)
59{
60 u32 ctrl2, ctrl3;
61
62 /* don't need to alter anything acording to card-type */
63
64 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
65
66 ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
67 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
68 ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
69 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
70 S3C_SDHCI_CTRL2_ENFBCLKRX |
71 S3C_SDHCI_CTRL2_DFCNT_NONE |
72 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
73
74 if (ios->clock < 25 * 1000000)
75 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
76 S3C_SDHCI_CTRL3_FCSEL2 |
77 S3C_SDHCI_CTRL3_FCSEL1 |
78 S3C_SDHCI_CTRL3_FCSEL0);
79 else
80 ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
81
82 printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
83 writel(ctrl2, r + S3C_SDHCI_CONTROL2);
84 writel(ctrl3, r + S3C_SDHCI_CONTROL3);
85}
86
87void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
88{
89 unsigned int gpio;
90 unsigned int end;
91
92 end = S3C64XX_GPH(2 + width);
93
94 /* Set all the necessary GPG pins to special-function 0 */
95 for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
96 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
97 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
98 }
99
100 s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
101 s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
102}
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index adb9060ec910..def0bb457ca3 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -110,3 +110,73 @@ config S3C_LOWLEVEL_UART_PORT
110 such as the `Uncompressing...` at start time. The value of 110 such as the `Uncompressing...` at start time. The value of
111 this configuration should be between zero and two. The port 111 this configuration should be between zero and two. The port
112 must have been initialised by the boot-loader before use. 112 must have been initialised by the boot-loader before use.
113
114# options for gpiolib support
115
116config S3C_GPIO_SPACE
117 int "Space between gpio banks"
118 default 0
119 help
120 Add a number of spare GPIO entries between each bank for debugging
121 purposes. This allows any problems where an counter overflows from
122 one bank to another to be caught, at the expense of using a little
123 more memory.
124
125config S3C_GPIO_TRACK
126 bool
127 help
128 Internal configuration option to enable the s3c specific gpio
129 chip tracking if the platform requires it.
130
131config S3C_GPIO_PULL_UPDOWN
132 bool
133 help
134 Internal configuration to enable the correct GPIO pull helper
135
136config S3C_GPIO_PULL_DOWN
137 bool
138 help
139 Internal configuration to enable the correct GPIO pull helper
140
141config S3C_GPIO_PULL_UP
142 bool
143 help
144 Internal configuration to enable the correct GPIO pull helper
145
146config S3C_GPIO_CFG_S3C24XX
147 bool
148 help
149 Internal configuration to enable S3C24XX style GPIO configuration
150 functions.
151
152config S3C_GPIO_CFG_S3C64XX
153 bool
154 help
155 Internal configuration to enable S3C64XX style GPIO configuration
156 functions.
157
158# device definitions to compile in
159
160config S3C_DEV_HSMMC
161 bool
162 depends on PLAT_S3C
163 help
164 Compile in platform device definitions for HSMMC code
165
166config S3C_DEV_HSMMC1
167 bool
168 depends on PLAT_S3C
169 help
170 Compile in platform device definitions for HSMMC channel 1
171
172config S3C_DEV_I2C1
173 bool
174 depends on PLAT_S3C
175 help
176 Compile in platform device definitions for I2C channel 1
177
178config S3C_DEV_FB
179 bool
180 depends on PLAT_S3C
181 help
182 Compile in platform device definition for framebuffer
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index a2fe3c77564e..39195f972d5e 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -14,4 +14,14 @@ obj- :=
14obj-y += init.o 14obj-y += init.o
15obj-y += time.o 15obj-y += time.o
16obj-y += clock.o 16obj-y += clock.o
17obj-y += pwm-clock.o \ No newline at end of file 17obj-y += pwm-clock.o
18obj-y += gpio.o
19obj-y += gpio-config.o
20
21# devices
22
23obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
24obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
25obj-y += dev-i2c0.o
26obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
27obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-s3c/dev-fb.c
new file mode 100644
index 000000000000..0454b8ec02e2
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-fb.c
@@ -0,0 +1,72 @@
1/* linux/arch/arm/plat-s3c/dev-fb.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for framebuffer device
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17#include <linux/fb.h>
18
19#include <mach/map.h>
20#include <mach/regs-fb.h>
21
22#include <plat/fb.h>
23#include <plat/devs.h>
24#include <plat/cpu.h>
25
26static struct resource s3c_fb_resource[] = {
27 [0] = {
28 .start = S3C_PA_FB,
29 .end = S3C_PA_FB + SZ_16K - 1,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = IRQ_LCD_VSYNC,
34 .end = IRQ_LCD_VSYNC,
35 .flags = IORESOURCE_IRQ,
36 },
37 [2] = {
38 .start = IRQ_LCD_FIFO,
39 .end = IRQ_LCD_FIFO,
40 .flags = IORESOURCE_IRQ,
41 },
42 [3] = {
43 .start = IRQ_LCD_SYSTEM,
44 .end = IRQ_LCD_SYSTEM,
45 .flags = IORESOURCE_IRQ,
46 },
47};
48
49struct platform_device s3c_device_fb = {
50 .name = "s3c-fb",
51 .id = -1,
52 .num_resources = ARRAY_SIZE(s3c_fb_resource),
53 .resource = s3c_fb_resource,
54 .dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask,
55 .dev.coherent_dma_mask = 0xffffffffUL,
56};
57
58void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
59{
60 struct s3c_fb_platdata *npd;
61
62 if (!pd) {
63 printk(KERN_ERR "%s: no platform data\n", __func__);
64 return;
65 }
66
67 npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
68 if (!npd)
69 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
70
71 s3c_device_fb.dev.platform_data = npd;
72}
diff --git a/arch/arm/plat-s3c/dev-hsmmc.c b/arch/arm/plat-s3c/dev-hsmmc.c
new file mode 100644
index 000000000000..4c05b39810e2
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-hsmmc.c
@@ -0,0 +1,68 @@
1/* linux/arch/arm/plat-s3c/dev-hsmmc.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for hsmmc devices
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mmc/host.h>
17
18#include <mach/map.h>
19#include <plat/sdhci.h>
20#include <plat/devs.h>
21#include <plat/cpu.h>
22
23#define S3C_SZ_HSMMC (0x1000)
24
25static struct resource s3c_hsmmc_resource[] = {
26 [0] = {
27 .start = S3C_PA_HSMMC0,
28 .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_HSMMC0,
33 .end = IRQ_HSMMC0,
34 .flags = IORESOURCE_IRQ,
35 }
36};
37
38static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
39
40struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
41 .max_width = 4,
42 .host_caps = (MMC_CAP_4_BIT_DATA |
43 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
44};
45
46struct platform_device s3c_device_hsmmc0 = {
47 .name = "s3c-sdhci",
48 .id = 0,
49 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
50 .resource = s3c_hsmmc_resource,
51 .dev = {
52 .dma_mask = &s3c_device_hsmmc_dmamask,
53 .coherent_dma_mask = 0xffffffffUL,
54 .platform_data = &s3c_hsmmc0_def_platdata,
55 },
56};
57
58void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
59{
60 struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
61
62 set->max_width = pd->max_width;
63
64 if (pd->cfg_gpio)
65 set->cfg_gpio = pd->cfg_gpio;
66 if (pd->cfg_card)
67 set->cfg_card = pd->cfg_card;
68}
diff --git a/arch/arm/plat-s3c/dev-hsmmc1.c b/arch/arm/plat-s3c/dev-hsmmc1.c
new file mode 100644
index 000000000000..e49bc4cd0ee6
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-hsmmc1.c
@@ -0,0 +1,68 @@
1/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for hsmmc device 1
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mmc/host.h>
17
18#include <mach/map.h>
19#include <plat/sdhci.h>
20#include <plat/devs.h>
21#include <plat/cpu.h>
22
23#define S3C_SZ_HSMMC (0x1000)
24
25static struct resource s3c_hsmmc1_resource[] = {
26 [0] = {
27 .start = S3C_PA_HSMMC1,
28 .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_HSMMC1,
33 .end = IRQ_HSMMC1,
34 .flags = IORESOURCE_IRQ,
35 }
36};
37
38static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
39
40struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
41 .max_width = 4,
42 .host_caps = (MMC_CAP_4_BIT_DATA |
43 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
44};
45
46struct platform_device s3c_device_hsmmc1 = {
47 .name = "s3c-sdhci",
48 .id = 1,
49 .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
50 .resource = s3c_hsmmc1_resource,
51 .dev = {
52 .dma_mask = &s3c_device_hsmmc1_dmamask,
53 .coherent_dma_mask = 0xffffffffUL,
54 .platform_data = &s3c_hsmmc1_def_platdata,
55 },
56};
57
58void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
59{
60 struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
61
62 set->max_width = pd->max_width;
63
64 if (pd->cfg_gpio)
65 set->cfg_gpio = pd->cfg_gpio;
66 if (pd->cfg_card)
67 set->cfg_card = pd->cfg_card;
68}
diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c
new file mode 100644
index 000000000000..2c0128c77c6e
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-i2c0.c
@@ -0,0 +1,71 @@
1/* linux/arch/arm/plat-s3c/dev-i2c0.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for i2c device 0
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/map.h>
19
20#include <plat/regs-iic.h>
21#include <plat/iic.h>
22#include <plat/devs.h>
23#include <plat/cpu.h>
24
25static struct resource s3c_i2c_resource[] = {
26 [0] = {
27 .start = S3C_PA_IIC,
28 .end = S3C_PA_IIC + SZ_4K - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_IIC,
33 .end = IRQ_IIC,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38struct platform_device s3c_device_i2c0 = {
39 .name = "s3c2410-i2c",
40#ifdef CONFIG_S3C_DEV_I2C1
41 .id = 0,
42#else
43 .id = -1,
44#endif
45 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
46 .resource = s3c_i2c_resource,
47};
48
49static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
50 .flags = 0,
51 .slave_addr = 0x10,
52 .bus_freq = 100*1000,
53 .max_freq = 400*1000,
54 .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
55};
56
57void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
58{
59 struct s3c2410_platform_i2c *npd;
60
61 if (!pd)
62 pd = &default_i2c_data0;
63
64 npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
65 if (!npd)
66 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
67 else if (!npd->cfg_gpio)
68 npd->cfg_gpio = s3c_i2c0_cfg_gpio;
69
70 s3c_device_i2c0.dev.platform_data = npd;
71}
diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c
new file mode 100644
index 000000000000..9658fb0aec95
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-i2c1.c
@@ -0,0 +1,68 @@
1/* linux/arch/arm/plat-s3c/dev-i2c1.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series device definition for i2c device 1
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/string.h>
16#include <linux/platform_device.h>
17
18#include <mach/map.h>
19
20#include <plat/regs-iic.h>
21#include <plat/iic.h>
22#include <plat/devs.h>
23#include <plat/cpu.h>
24
25static struct resource s3c_i2c_resource[] = {
26 [0] = {
27 .start = S3C_PA_IIC1,
28 .end = S3C_PA_IIC1 + SZ_4K - 1,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = IRQ_IIC1,
33 .end = IRQ_IIC1,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38struct platform_device s3c_device_i2c1 = {
39 .name = "s3c2410-i2c",
40 .id = 1,
41 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
42 .resource = s3c_i2c_resource,
43};
44
45static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
46 .flags = 0,
47 .bus_num = 1,
48 .slave_addr = 0x10,
49 .bus_freq = 100*1000,
50 .max_freq = 400*1000,
51 .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
52};
53
54void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
55{
56 struct s3c2410_platform_i2c *npd;
57
58 if (!pd)
59 pd = &default_i2c_data1;
60
61 npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
62 if (!npd)
63 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
64 else if (!npd->cfg_gpio)
65 npd->cfg_gpio = s3c_i2c1_cfg_gpio;
66
67 s3c_device_i2c1.dev.platform_data = npd;
68}
diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c
new file mode 100644
index 000000000000..7642b975a998
--- /dev/null
+++ b/arch/arm/plat-s3c/gpio-config.c
@@ -0,0 +1,163 @@
1/* linux/arch/arm/plat-s3c/gpio-config.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C series GPIO configuration core
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/gpio.h>
17#include <linux/io.h>
18
19#include <mach/gpio-core.h>
20#include <plat/gpio-cfg.h>
21#include <plat/gpio-cfg-helpers.h>
22
23int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
24{
25 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
26 unsigned long flags;
27 int offset;
28 int ret;
29
30 if (!chip)
31 return -EINVAL;
32
33 offset = pin - chip->chip.base;
34
35 local_irq_save(flags);
36 ret = s3c_gpio_do_setcfg(chip, offset, config);
37 local_irq_restore(flags);
38
39 return ret;
40}
41
42int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
43{
44 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
45 unsigned long flags;
46 int offset, ret;
47
48 if (!chip)
49 return -EINVAL;
50
51 offset = pin - chip->chip.base;
52
53 local_irq_save(flags);
54 ret = s3c_gpio_do_setpull(chip, offset, pull);
55 local_irq_restore(flags);
56
57 return ret;
58}
59
60#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
61int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
62 unsigned int off, unsigned int cfg)
63{
64 void __iomem *reg = chip->base;
65 unsigned int shift = off;
66 u32 con;
67
68 if (s3c_gpio_is_cfg_special(cfg)) {
69 cfg &= 0xf;
70
71 /* Map output to 0, and SFN2 to 1 */
72 cfg -= 1;
73 if (cfg > 1)
74 return -EINVAL;
75
76 cfg <<= shift;
77 }
78
79 con = __raw_readl(reg);
80 con &= ~(0x1 << shift);
81 con |= cfg;
82 __raw_writel(con, reg);
83
84 return 0;
85}
86
87int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
88 unsigned int off, unsigned int cfg)
89{
90 void __iomem *reg = chip->base;
91 unsigned int shift = off * 2;
92 u32 con;
93
94 if (s3c_gpio_is_cfg_special(cfg)) {
95 cfg &= 0xf;
96 if (cfg > 3)
97 return -EINVAL;
98
99 cfg <<= shift;
100 }
101
102 con = __raw_readl(reg);
103 con &= ~(0x3 << shift);
104 con |= cfg;
105 __raw_writel(con, reg);
106
107 return 0;
108}
109#endif
110
111#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
112int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
113 unsigned int off, unsigned int cfg)
114{
115 void __iomem *reg = chip->base;
116 unsigned int shift = (off & 7) * 4;
117 u32 con;
118
119 if (off < 8 && chip->chip.ngpio >= 8)
120 reg -= 4;
121
122 if (s3c_gpio_is_cfg_special(cfg)) {
123 cfg &= 0xf;
124 cfg <<= shift;
125 }
126
127 con = __raw_readl(reg);
128 con &= ~(0xf << shift);
129 con |= cfg;
130 __raw_writel(con, reg);
131
132 return 0;
133}
134#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
135
136#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
137int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
138 unsigned int off, s3c_gpio_pull_t pull)
139{
140 void __iomem *reg = chip->base + 0x08;
141 int shift = off * 2;
142 u32 pup;
143
144 pup = __raw_readl(reg);
145 pup &= ~(3 << shift);
146 pup |= pull << shift;
147 __raw_writel(pup, reg);
148
149 return 0;
150}
151
152s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
153 unsigned int off)
154{
155 void __iomem *reg = chip->base + 0x08;
156 int shift = off * 2;
157 u32 pup = __raw_readl(reg);
158
159 pup >>= shift;
160 pup &= 0x3;
161 return (__force s3c_gpio_pull_t)pup;
162}
163#endif
diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c
new file mode 100644
index 000000000000..d71dd6d9ce5c
--- /dev/null
+++ b/arch/arm/plat-s3c/gpio.c
@@ -0,0 +1,147 @@
1/* linux/arch/arm/plat-s3c/gpio.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C series GPIO core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <plat/gpio-core.h>
20
21#ifdef CONFIG_S3C_GPIO_TRACK
22struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
23
24static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
25{
26 unsigned int gpn;
27 int i;
28
29 gpn = chip->chip.base;
30 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
31 BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
32 s3c_gpios[gpn] = chip;
33 }
34}
35#endif /* CONFIG_S3C_GPIO_TRACK */
36
37/* Default routines for controlling GPIO, based on the original S3C24XX
38 * GPIO functions which deal with the case where each gpio bank of the
39 * chip is as following:
40 *
41 * base + 0x00: Control register, 2 bits per gpio
42 * gpio n: 2 bits starting at (2*n)
43 * 00 = input, 01 = output, others mean special-function
44 * base + 0x04: Data register, 1 bit per gpio
45 * bit n: data bit n
46*/
47
48static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
49{
50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
51 void __iomem *base = ourchip->base;
52 unsigned long flags;
53 unsigned long con;
54
55 local_irq_save(flags);
56
57 con = __raw_readl(base + 0x00);
58 con &= ~(3 << (offset * 2));
59
60 __raw_writel(con, base + 0x00);
61
62 local_irq_restore(flags);
63 return 0;
64}
65
66static int s3c_gpiolib_output(struct gpio_chip *chip,
67 unsigned offset, int value)
68{
69 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
70 void __iomem *base = ourchip->base;
71 unsigned long flags;
72 unsigned long dat;
73 unsigned long con;
74
75 local_irq_save(flags);
76
77 dat = __raw_readl(base + 0x04);
78 dat &= ~(1 << offset);
79 if (value)
80 dat |= 1 << offset;
81 __raw_writel(dat, base + 0x04);
82
83 con = __raw_readl(base + 0x00);
84 con &= ~(3 << (offset * 2));
85 con |= 1 << (offset * 2);
86
87 __raw_writel(con, base + 0x00);
88 __raw_writel(dat, base + 0x04);
89
90 local_irq_restore(flags);
91 return 0;
92}
93
94static void s3c_gpiolib_set(struct gpio_chip *chip,
95 unsigned offset, int value)
96{
97 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
98 void __iomem *base = ourchip->base;
99 unsigned long flags;
100 unsigned long dat;
101
102 local_irq_save(flags);
103
104 dat = __raw_readl(base + 0x04);
105 dat &= ~(1 << offset);
106 if (value)
107 dat |= 1 << offset;
108 __raw_writel(dat, base + 0x04);
109
110 local_irq_restore(flags);
111}
112
113static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
114{
115 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
116 unsigned long val;
117
118 val = __raw_readl(ourchip->base + 0x04);
119 val >>= offset;
120 val &= 1;
121
122 return val;
123}
124
125__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
126{
127 struct gpio_chip *gc = &chip->chip;
128 int ret;
129
130 BUG_ON(!chip->base);
131 BUG_ON(!gc->label);
132 BUG_ON(!gc->ngpio);
133
134 if (!gc->direction_input)
135 gc->direction_input = s3c_gpiolib_input;
136 if (!gc->direction_output)
137 gc->direction_output = s3c_gpiolib_output;
138 if (!gc->set)
139 gc->set = s3c_gpiolib_set;
140 if (!gc->get)
141 gc->get = s3c_gpiolib_get;
142
143 /* gpiochip_add() prints own failure message on error. */
144 ret = gpiochip_add(gc);
145 if (ret >= 0)
146 s3c_gpiolib_track(chip);
147}
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index a689c7c5ac23..6b1b5231511c 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -24,15 +24,19 @@ extern struct platform_device *s3c24xx_uart_src[];
24 24
25extern struct platform_device s3c_device_timer[]; 25extern struct platform_device s3c_device_timer[];
26 26
27extern struct platform_device s3c_device_fb;
27extern struct platform_device s3c_device_usb; 28extern struct platform_device s3c_device_usb;
28extern struct platform_device s3c_device_lcd; 29extern struct platform_device s3c_device_lcd;
29extern struct platform_device s3c_device_wdt; 30extern struct platform_device s3c_device_wdt;
30extern struct platform_device s3c_device_i2c; 31extern struct platform_device s3c_device_i2c0;
32extern struct platform_device s3c_device_i2c1;
31extern struct platform_device s3c_device_iis; 33extern struct platform_device s3c_device_iis;
32extern struct platform_device s3c_device_rtc; 34extern struct platform_device s3c_device_rtc;
33extern struct platform_device s3c_device_adc; 35extern struct platform_device s3c_device_adc;
34extern struct platform_device s3c_device_sdi; 36extern struct platform_device s3c_device_sdi;
35extern struct platform_device s3c_device_hsmmc; 37extern struct platform_device s3c_device_hsmmc0;
38extern struct platform_device s3c_device_hsmmc1;
39extern struct platform_device s3c_device_hsmmc2;
36 40
37extern struct platform_device s3c_device_spi0; 41extern struct platform_device s3c_device_spi0;
38extern struct platform_device s3c_device_spi1; 42extern struct platform_device s3c_device_spi1;
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h
new file mode 100644
index 000000000000..214ff561b0dd
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/fb.h
@@ -0,0 +1,73 @@
1/* linux/arch/arm/plat-s3c/include/plat/fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - FB platform data definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_FB_H
16#define __PLAT_S3C_FB_H __FILE__
17
18/**
19 * struct s3c_fb_pd_win - per window setup data
20 * @win_mode: The display parameters to initialise (not for window 0)
21 * @virtual_x: The virtual X size.
22 * @virtual_y: The virtual Y size.
23 */
24struct s3c_fb_pd_win {
25 struct fb_videomode win_mode;
26
27 unsigned short default_bpp;
28 unsigned short max_bpp;
29 unsigned short virtual_x;
30 unsigned short virtual_y;
31};
32
33/**
34 * struct s3c_fb_platdata - S3C driver platform specific information
35 * @setup_gpio: Setup the external GPIO pins to the right state to transfer
36 * the data from the display system to the connected display
37 * device.
38 * @vidcon0: The base vidcon0 values to control the panel data format.
39 * @vidcon1: The base vidcon1 values to control the panel data output.
40 * @win: The setup data for each hardware window, or NULL for unused.
41 * @display_mode: The LCD output display mode.
42 *
43 * The platform data supplies the video driver with all the information
44 * it requires to work with the display(s) attached to the machine. It
45 * controls the initial mode, the number of display windows (0 is always
46 * the base framebuffer) that are initialised etc.
47 *
48 */
49struct s3c_fb_platdata {
50 void (*setup_gpio)(void);
51
52 struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
53
54 u32 vidcon0;
55 u32 vidcon1;
56};
57
58/**
59 * s3c_fb_set_platdata() - Setup the FB device with platform data.
60 * @pd: The platform data to set. The data is copied from the passed structure
61 * so the machine data can mark the data __initdata so that any unused
62 * machines will end up dumping their data at runtime.
63 */
64extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
65
66/**
67 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
68 *
69 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
70 */
71extern void s3c64xx_fb_gpio_setup_24bpp(void);
72
73#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h
new file mode 100644
index 000000000000..652e2bbdaa20
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h
@@ -0,0 +1,176 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - GPIO pin configuration helper definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* This is meant for core cpu support, machine or other driver files
16 * should not be including this header.
17 */
18
19#ifndef __PLAT_GPIO_CFG_HELPERS_H
20#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
21
22/* As a note, all gpio configuration functions are entered exclusively, either
23 * with the relevant lock held or the system prevented from doing anything else
24 * by disabling interrupts.
25*/
26
27static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
28 unsigned int off, unsigned int config)
29{
30 return (chip->config->set_config)(chip, off, config);
31}
32
33static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
34 unsigned int off, s3c_gpio_pull_t pull)
35{
36 return (chip->config->set_pull)(chip, off, pull);
37}
38
39/**
40 * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
41 * @chip: The gpio chip that is being configured.
42 * @off: The offset for the GPIO being configured.
43 * @cfg: The configuration value to set.
44 *
45 * This helper deal with the GPIO cases where the control register
46 * has two bits of configuration per gpio, which have the following
47 * functions:
48 * 00 = input
49 * 01 = output
50 * 1x = special function
51*/
52extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
53 unsigned int off, unsigned int cfg);
54
55/**
56 * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
57 * @chip: The gpio chip that is being configured.
58 * @off: The offset for the GPIO being configured.
59 * @cfg: The configuration value to set.
60 *
61 * This helper deal with the GPIO cases where the control register
62 * has one bit of configuration for the gpio, where setting the bit
63 * means the pin is in special function mode and unset means output.
64*/
65extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
66 unsigned int off, unsigned int cfg);
67
68/**
69 * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
70 * @chip: The gpio chip that is being configured.
71 * @off: The offset for the GPIO being configured.
72 * @cfg: The configuration value to set.
73 *
74 * This helper deal with the GPIO cases where the control register has 4 bits
75 * of control per GPIO, generally in the form of:
76 * 0000 = Input
77 * 0001 = Output
78 * others = Special functions (dependant on bank)
79 *
80 * Note, since the code to deal with the case where there are two control
81 * registers instead of one, we do not have a seperate set of functions for
82 * each case.
83*/
84extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
85 unsigned int off, unsigned int cfg);
86
87
88/* Pull-{up,down} resistor controls.
89 *
90 * S3C2410,S3C2440,S3C24A0 = Pull-UP,
91 * S3C2412,S3C2413 = Pull-Down
92 * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
93 * S3C2443 = Pull-Both [not same as S3C6400]
94 */
95
96/**
97 * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
98 * @chip: The gpio chip that is being configured.
99 * @off: The offset for the GPIO being configured.
100 * @param: pull: The pull mode being requested.
101 *
102 * This is a helper function for the case where we have GPIOs with one
103 * bit configuring the presence of a pull-up resistor.
104 */
105extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
106 unsigned int off, s3c_gpio_pull_t pull);
107
108/**
109 * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
110 * @chip: The gpio chip that is being configured
111 * @off: The offset for the GPIO being configured
112 * @param: pull: The pull mode being requested
113 *
114 * This is a helper function for the case where we have GPIOs with one
115 * bit configuring the presence of a pull-down resistor.
116 */
117extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
118 unsigned int off, s3c_gpio_pull_t pull);
119
120/**
121 * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
122 * @chip: The gpio chip that is being configured.
123 * @off: The offset for the GPIO being configured.
124 * @param: pull: The pull mode being requested.
125 *
126 * This is a helper function for the case where we have GPIOs with two
127 * bits configuring the presence of a pull resistor, in the following
128 * order:
129 * 00 = No pull resistor connected
130 * 01 = Pull-up resistor connected
131 * 10 = Pull-down resistor connected
132 */
133extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
134 unsigned int off, s3c_gpio_pull_t pull);
135
136
137/**
138 * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
139 * @chip: The gpio chip that the GPIO pin belongs to
140 * @off: The offset to the pin to get the configuration of.
141 *
142 * This helper function reads the state of the pull-{up,down} resistor for the
143 * given GPIO in the same case as s3c_gpio_setpull_upown.
144*/
145extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
146 unsigned int off);
147
148/**
149 * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
150 * @chip: The gpio chip that is being configured.
151 * @off: The offset for the GPIO being configured.
152 * @param: pull: The pull mode being requested.
153 *
154 * This is a helper function for the case where we have GPIOs with two
155 * bits configuring the presence of a pull resistor, in the following
156 * order:
157 * 00 = Pull-up resistor connected
158 * 10 = Pull-down resistor connected
159 * x1 = No pull up resistor
160 */
161extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
162 unsigned int off, s3c_gpio_pull_t pull);
163
164/**
165 * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
166 * @chip: The gpio chip that the GPIO pin belongs to.
167 * @off: The offset to the pin to get the configuration of.
168 *
169 * This helper function reads the state of the pull-{up,down} resistor for the
170 * given GPIO in the same case as s3c_gpio_setpull_upown.
171*/
172extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
173 unsigned int off);
174
175#endif /* __PLAT_GPIO_CFG_HELPERS_H */
176
diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg.h b/arch/arm/plat-s3c/include/plat/gpio-cfg.h
new file mode 100644
index 000000000000..29cd6a86cade
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/gpio-cfg.h
@@ -0,0 +1,110 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - GPIO pin configuration
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* This file contains the necessary definitions to get the basic gpio
16 * pin configuration done such as setting a pin to input or output or
17 * changing the pull-{up,down} configurations.
18 */
19
20/* Note, this interface is being added to the s3c64xx arch first and will
21 * be added to the s3c24xx systems later.
22 */
23
24#ifndef __PLAT_GPIO_CFG_H
25#define __PLAT_GPIO_CFG_H __FILE__
26
27typedef unsigned int __bitwise__ s3c_gpio_pull_t;
28
29/* forward declaration if gpio-core.h hasn't been included */
30struct s3c_gpio_chip;
31
32/**
33 * struct s3c_gpio_cfg GPIO configuration
34 * @cfg_eint: Configuration setting when used for external interrupt source
35 * @get_pull: Read the current pull configuration for the GPIO
36 * @set_pull: Set the current pull configuraiton for the GPIO
37 * @set_config: Set the current configuration for the GPIO
38 * @get_config: Read the current configuration for the GPIO
39 *
40 * Each chip can have more than one type of GPIO bank available and some
41 * have different capabilites even when they have the same control register
42 * layouts. Provide an point to vector control routine and provide any
43 * per-bank configuration information that other systems such as the
44 * external interrupt code will need.
45 */
46struct s3c_gpio_cfg {
47 unsigned int cfg_eint;
48
49 s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
50 int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
51 s3c_gpio_pull_t pull);
52
53 unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
54 int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
55 unsigned config);
56};
57
58#define S3C_GPIO_SPECIAL_MARK (0xfffffff0)
59#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x))
60
61/* Defines for generic pin configurations */
62#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
63#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
64#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
65
66#define s3c_gpio_is_cfg_special(_cfg) \
67 (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
68
69/**
70 * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
71 * @pin pin The pin number to configure.
72 * @pin to The configuration for the pin's function.
73 *
74 * Configure which function is actually connected to the external
75 * pin, such as an gpio input, output or some form of special function
76 * connected to an internal peripheral block.
77 */
78extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
79
80/* Define values for the pull-{up,down} available for each gpio pin.
81 *
82 * These values control the state of the weak pull-{up,down} resistors
83 * available on most pins on the S3C series. Not all chips support both
84 * up or down settings, and it may be dependant on the chip that is being
85 * used to whether the particular mode is available.
86 */
87#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
88#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01)
89#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02)
90
91/**
92 * s3c_gpio_setpull() - set the state of a gpio pin pull resistor
93 * @pin: The pin number to configure the pull resistor.
94 * @pull: The configuration for the pull resistor.
95 *
96 * This function sets the state of the pull-{up,down} resistor for the
97 * specified pin. It will return 0 if successfull, or a negative error
98 * code if the pin cannot support the requested pull setting.
99*/
100extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
101
102/**
103 * s3c_gpio_getpull() - get the pull resistor state of a gpio pin
104 * @pin: The pin number to get the settings for
105 *
106 * Read the pull resistor value for the specified pin.
107*/
108extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
109
110#endif /* __PLAT_GPIO_CFG_H */
diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h
new file mode 100644
index 000000000000..2fc60a580ac8
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/gpio-core.h
@@ -0,0 +1,77 @@
1/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C Platform - GPIO core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* Define the core gpiolib support functions that the s3c platforms may
15 * need to extend or change depending on the hardware and the s3c chip
16 * selected at build or found at run time.
17 *
18 * These definitions are not intended for driver inclusion, there is
19 * nothing here that should not live outside the platform and core
20 * specific code.
21*/
22
23struct s3c_gpio_cfg;
24
25/**
26 * struct s3c_gpio_chip - wrapper for specific implementation of gpio
27 * @chip: The chip structure to be exported via gpiolib.
28 * @base: The base pointer to the gpio configuration registers.
29 * @config: special function and pull-resistor control information.
30 *
31 * This wrapper provides the necessary information for the Samsung
32 * specific gpios being registered with gpiolib.
33 */
34struct s3c_gpio_chip {
35 struct gpio_chip chip;
36 struct s3c_gpio_cfg *config;
37 void __iomem *base;
38};
39
40static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
41{
42 return container_of(gpc, struct s3c_gpio_chip, chip);
43}
44
45/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
46 * @chip: The chip to register
47 *
48 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
49 * information and makes the necessary alterations for the platform and
50 * notes the information for use with the configuration systems and any
51 * other parts of the system.
52 */
53extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
54
55/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
56 * for use with the configuration calls, and other parts of the s3c gpiolib
57 * support code.
58 *
59 * Not all s3c support code will need this, as some configurations of cpu
60 * may only support one or two different configuration options and have an
61 * easy gpio to s3c_gpio_chip mapping function. If this is the case, then
62 * the machine support file should provide its own s3c_gpiolib_getchip()
63 * and any other necessary functions.
64 */
65
66#ifdef CONFIG_S3C_GPIO_TRACK
67extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
68
69static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
70{
71 return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
72}
73#else
74/* machine specific code should provide s3c_gpiolib_getchip */
75
76static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
77#endif
diff --git a/arch/arm/plat-s3c/include/plat/iic-core.h b/arch/arm/plat-s3c/include/plat/iic-core.h
new file mode 100644
index 000000000000..36397ca20962
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/iic-core.h
@@ -0,0 +1,35 @@
1/* arch/arm/mach-s3c2410/include/mach/iic-core.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C - I2C Controller core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_IIC_CORE_H
15#define __ASM_ARCH_IIC_CORE_H __FILE__
16
17/* These functions are only for use with the core support code, such as
18 * the cpu specific initialisation code
19 */
20
21/* re-define device name depending on support. */
22static inline void s3c_i2c0_setname(char *name)
23{
24 /* currently this device is always compiled in */
25 s3c_device_i2c0.name = name;
26}
27
28static inline void s3c_i2c1_setname(char *name)
29{
30#ifdef CONFIG_S3C_DEV_I2C1
31 s3c_device_i2c1.name = name;
32#endif
33}
34
35#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h
index 5106acaa1d0e..dc1dfcb9bc6c 100644
--- a/arch/arm/plat-s3c/include/plat/iic.h
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -28,6 +28,30 @@ struct s3c2410_platform_i2c {
28 unsigned long max_freq; /* max frequency for the bus */ 28 unsigned long max_freq; /* max frequency for the bus */
29 unsigned long min_freq; /* min frequency for the bus */ 29 unsigned long min_freq; /* min frequency for the bus */
30 unsigned int sda_delay; /* pclks (s3c2440 only) */ 30 unsigned int sda_delay; /* pclks (s3c2440 only) */
31
32 void (*cfg_gpio)(struct platform_device *dev);
31}; 33};
32 34
35/**
36 * s3c_i2c0_set_platdata - set platform data for i2c0 device
37 * @i2c: The platform data to set, or NULL for default data.
38 *
39 * Register the given platform data for use with the i2c0 device. This
40 * call copies the platform data, so the caller can use __initdata for
41 * their copy.
42 *
43 * This call will set cfg_gpio if is null to the default platform
44 * implementation.
45 *
46 * Any user of s3c_device_i2c0 should call this, even if it is with
47 * NULL to ensure that the device is given the default platform data
48 * as the driver will no longer carry defaults.
49 */
50extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
51extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
52
53/* defined by architecture to configure gpio */
54extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
55extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
56
33#endif /* __ASM_ARCH_IIC_H */ 57#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb.h b/arch/arm/plat-s3c/include/plat/regs-fb.h
new file mode 100644
index 000000000000..e9ee599d430e
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-fb.h
@@ -0,0 +1,366 @@
1/* arch/arm/plat-s3c/include/plat/regs-fb.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - new-style framebuffer register definitions
9 *
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards into the S3C2416, S3C2450 and the
12 * S3C64XX series such as the S3C6400 and S3C6410.
13 *
14 * The file does not contain the cpu specific items which are based on
15 * whichever architecture is selected, it only contains the core of the
16 * register set. See <mach/regs-fb.h> to get the specifics.
17 *
18 * Note, we changed to using regs-fb.h as it avoids any clashes with
19 * the original regs-lcd.h so out of the way of regs-lcd.h as well as
20 * indicating the newer block is much more than just an LCD interface.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25*/
26
27/* Please do not include this file directly, use <mach/regs-fb.h> to
28 * ensure all the localised SoC support is included as necessary.
29*/
30
31/* VIDCON0 */
32
33#define VIDCON0 (0x00)
34#define VIDCON0_INTERLACE (1 << 29)
35#define VIDCON0_VIDOUT_MASK (0x3 << 26)
36#define VIDCON0_VIDOUT_SHIFT (26)
37#define VIDCON0_VIDOUT_RGB (0x0 << 26)
38#define VIDCON0_VIDOUT_TV (0x1 << 26)
39#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
40#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
41
42#define VIDCON0_L1_DATA_MASK (0x7 << 23)
43#define VIDCON0_L1_DATA_SHIFT (23)
44#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
45#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
46#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
47#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
48#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
49#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
50
51#define VIDCON0_L0_DATA_MASK (0x7 << 20)
52#define VIDCON0_L0_DATA_SHIFT (20)
53#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
54#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
55#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
56#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
57#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
58#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
59
60#define VIDCON0_PNRMODE_MASK (0x3 << 17)
61#define VIDCON0_PNRMODE_SHIFT (17)
62#define VIDCON0_PNRMODE_RGB (0x0 << 17)
63#define VIDCON0_PNRMODE_BGR (0x1 << 17)
64#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
65#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
66
67#define VIDCON0_CLKVALUP (1 << 16)
68#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
69#define VIDCON0_CLKVAL_F_SHIFT (6)
70#define VIDCON0_CLKVAL_F_LIMIT (0xff)
71#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
72#define VIDCON0_VLCKFREE (1 << 5)
73#define VIDCON0_CLKDIR (1 << 4)
74
75#define VIDCON0_CLKSEL_MASK (0x3 << 2)
76#define VIDCON0_CLKSEL_SHIFT (2)
77#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
78#define VIDCON0_CLKSEL_LCD (0x1 << 2)
79#define VIDCON0_CLKSEL_27M (0x3 << 2)
80
81#define VIDCON0_ENVID (1 << 1)
82#define VIDCON0_ENVID_F (1 << 0)
83
84#define VIDCON1 (0x04)
85#define VIDCON1_LINECNT_MASK (0x7ff << 16)
86#define VIDCON1_LINECNT_SHIFT (16)
87#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
88#define VIDCON1_VSTATUS_MASK (0x3 << 13)
89#define VIDCON1_VSTATUS_SHIFT (13)
90#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
91#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
92#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
93#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
94
95#define VIDCON1_INV_VCLK (1 << 7)
96#define VIDCON1_INV_HSYNC (1 << 6)
97#define VIDCON1_INV_VSYNC (1 << 5)
98#define VIDCON1_INV_VDEN (1 << 4)
99
100/* VIDCON2 */
101
102#define VIDCON2 (0x08)
103#define VIDCON2_EN601 (1 << 23)
104#define VIDCON2_TVFMTSEL_SW (1 << 14)
105
106#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
107#define VIDCON2_TVFMTSEL1_SHIFT (12)
108#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
109#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
110#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
111
112#define VIDCON2_ORGYCbCr (1 << 8)
113#define VIDCON2_YUVORDCrCb (1 << 7)
114
115/* VIDTCON0 */
116
117#define VIDTCON0_VBPDE_MASK (0xff << 24)
118#define VIDTCON0_VBPDE_SHIFT (24)
119#define VIDTCON0_VBPDE_LIMIT (0xff)
120#define VIDTCON0_VBPDE(_x) ((_x) << 24)
121
122#define VIDTCON0_VBPD_MASK (0xff << 16)
123#define VIDTCON0_VBPD_SHIFT (16)
124#define VIDTCON0_VBPD_LIMIT (0xff)
125#define VIDTCON0_VBPD(_x) ((_x) << 16)
126
127#define VIDTCON0_VFPD_MASK (0xff << 8)
128#define VIDTCON0_VFPD_SHIFT (8)
129#define VIDTCON0_VFPD_LIMIT (0xff)
130#define VIDTCON0_VFPD(_x) ((_x) << 8)
131
132#define VIDTCON0_VSPW_MASK (0xff << 0)
133#define VIDTCON0_VSPW_SHIFT (0)
134#define VIDTCON0_VSPW_LIMIT (0xff)
135#define VIDTCON0_VSPW(_x) ((_x) << 0)
136
137/* VIDTCON1 */
138
139#define VIDTCON1_VFPDE_MASK (0xff << 24)
140#define VIDTCON1_VFPDE_SHIFT (24)
141#define VIDTCON1_VFPDE_LIMIT (0xff)
142#define VIDTCON1_VFPDE(_x) ((_x) << 24)
143
144#define VIDTCON1_HBPD_MASK (0xff << 16)
145#define VIDTCON1_HBPD_SHIFT (16)
146#define VIDTCON1_HBPD_LIMIT (0xff)
147#define VIDTCON1_HBPD(_x) ((_x) << 16)
148
149#define VIDTCON1_HFPD_MASK (0xff << 8)
150#define VIDTCON1_HFPD_SHIFT (8)
151#define VIDTCON1_HFPD_LIMIT (0xff)
152#define VIDTCON1_HFPD(_x) ((_x) << 8)
153
154#define VIDTCON1_HSPW_MASK (0xff << 0)
155#define VIDTCON1_HSPW_SHIFT (0)
156#define VIDTCON1_HSPW_LIMIT (0xff)
157#define VIDTCON1_HSPW(_x) ((_x) << 0)
158
159#define VIDTCON2 (0x18)
160#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
161#define VIDTCON2_LINEVAL_SHIFT (11)
162#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
163#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
164
165#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
166#define VIDTCON2_HOZVAL_SHIFT (0)
167#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
168#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
169
170/* WINCONx */
171
172
173#define WINCONx_BITSWP (1 << 18)
174#define WINCONx_BYTSWP (1 << 17)
175#define WINCONx_HAWSWP (1 << 16)
176#define WINCONx_BURSTLEN_MASK (0x3 << 9)
177#define WINCONx_BURSTLEN_SHIFT (9)
178#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
179#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
180#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
181
182#define WINCONx_ENWIN (1 << 0)
183#define WINCON0_BPPMODE_MASK (0xf << 2)
184#define WINCON0_BPPMODE_SHIFT (2)
185#define WINCON0_BPPMODE_1BPP (0x0 << 2)
186#define WINCON0_BPPMODE_2BPP (0x1 << 2)
187#define WINCON0_BPPMODE_4BPP (0x2 << 2)
188#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
189#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
190#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
191#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
192#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
193
194#define WINCON1_BLD_PIX (1 << 6)
195
196#define WINCON1_ALPHA_SEL (1 << 1)
197#define WINCON1_BPPMODE_MASK (0xf << 2)
198#define WINCON1_BPPMODE_SHIFT (2)
199#define WINCON1_BPPMODE_1BPP (0x0 << 2)
200#define WINCON1_BPPMODE_2BPP (0x1 << 2)
201#define WINCON1_BPPMODE_4BPP (0x2 << 2)
202#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
203#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
204#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
205#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
206#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
207#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
208#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
209#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
210#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
211#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
212#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
213#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
214
215
216#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
217#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
218#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
219#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
220
221#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
222#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
223#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
224#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
225
226#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
227#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
228#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
229#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
230
231#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
232#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
233#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
234#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
235
236/* For VIDOSD[1..4]C */
237#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
238#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
239#define VIDISD14C_ALPHA0_G_SHIFT (16)
240#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
241#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
242#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
243#define VIDISD14C_ALPHA0_B_SHIFT (12)
244#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
245#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
246#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
247#define VIDISD14C_ALPHA1_R_SHIFT (8)
248#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
249#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
250#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
251#define VIDISD14C_ALPHA1_G_SHIFT (4)
252#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
253#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
254#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
255#define VIDISD14C_ALPHA1_B_SHIFT (0)
256#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
257#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
258
259/* Video buffer addresses */
260#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
261#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
262#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
263#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
264#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
265
266#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
267#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
268#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
269#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
270
271#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
272#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
273#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
274#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
275
276/* Interrupt controls and status */
277
278#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
279#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
280#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
281#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
282
283#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
284#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
285#define VIDINTCON0_INT_I80IFDONE (1 << 17)
286
287#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
288#define VIDINTCON0_FRAMESEL0_SHIFT (15)
289#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
290#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
291#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
292#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
293
294#define VIDINTCON0_FRAMESEL1 (1 << 14)
295#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
296#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
297#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
298#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
299
300#define VIDINTCON0_INT_FRAME (1 << 12)
301#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
302#define VIDINTCON0_FIFIOSEL_SHIFT (5)
303#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
304#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
305
306#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
307#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
308#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
309#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
310#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
311#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
312#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
313
314#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
315#define VIDINTCON0_INT_FIFO_SHIFT (0)
316#define VIDINTCON0_INT_ENABLE (1 << 0)
317
318#define VIDINTCON1 (0x134)
319#define VIDINTCON1_INT_I180 (1 << 2)
320#define VIDINTCON1_INT_FRAME (1 << 1)
321#define VIDINTCON1_INT_FIFO (1 << 0)
322
323/* Window colour-key control registers */
324
325#define WxKEYCON0_KEYBL_EN (1 << 26)
326#define WxKEYCON0_KEYEN_F (1 << 25)
327#define WxKEYCON0_DIRCON (1 << 24)
328#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
329#define WxKEYCON0_COMPKEY_SHIFT (0)
330#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
331#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
332#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
333#define WxKEYCON1_COLVAL_SHIFT (0)
334#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
335#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
336
337
338/* Window blanking (MAP) */
339
340#define WINxMAP_MAP (1 << 24)
341#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
342#define WINxMAP_MAP_COLOUR_SHIFT (0)
343#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
344#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
345
346#define WPALCON_PAL_UPDATE (1 << 9)
347#define WPALCON_W1PAL_MASK (0x7 << 3)
348#define WPALCON_W1PAL_SHIFT (3)
349#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
350#define WPALCON_W1PAL_24BPP (0x1 << 3)
351#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
352#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
353#define WPALCON_W1PAL_18BPP (0x4 << 3)
354#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
355#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
356
357#define WPALCON_W0PAL_MASK (0x7 << 0)
358#define WPALCON_W0PAL_SHIFT (0)
359#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
360#define WPALCON_W0PAL_24BPP (0x1 << 0)
361#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
362#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
363#define WPALCON_W0PAL_18BPP (0x4 << 0)
364#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
365#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
366
diff --git a/arch/arm/plat-s3c/include/plat/regs-sdhci.h b/arch/arm/plat-s3c/include/plat/regs-sdhci.h
new file mode 100644
index 000000000000..e34049ad44cc
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-sdhci.h
@@ -0,0 +1,87 @@
1/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - SDHCI (HSMMC) register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_SDHCI_REGS_H
16#define __PLAT_S3C_SDHCI_REGS_H __FILE__
17
18#define S3C_SDHCI_CONTROL2 (0x80)
19#define S3C_SDHCI_CONTROL3 (0x84)
20#define S3C64XX_SDHCI_CONTROL4 (0x8C)
21
22#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
23#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
24#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
25#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
26
27#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
28#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
29#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
30
31#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
32#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
33#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
34
35#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
36#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
37#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
38#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
39#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
40
41#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
42#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
43#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
44#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
45#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
46#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
47
48#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
49#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
50#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
51#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
52#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
53#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
54#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
55#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
56
57#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
58#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
59#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
60#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
61
62#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
63#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
64#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
65
66#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
67#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
68#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
69
70#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
71#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
72#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
73
74#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
75#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
76#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
77
78#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
79#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
80#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
81#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
82#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
83#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
84
85#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
86
87#endif /* __PLAT_S3C_SDHCI_REGS_H */
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
new file mode 100644
index 000000000000..c4ca3920ca4b
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -0,0 +1,108 @@
1/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - SDHCI (HSMMC) platform data definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_SDHCI_H
16#define __PLAT_S3C_SDHCI_H __FILE__
17
18struct platform_device;
19struct mmc_host;
20struct mmc_card;
21struct mmc_ios;
22
23/**
24 * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
25 * @max_width: The maximum number of data bits supported.
26 * @host_caps: Standard MMC host capabilities bit field.
27 * @cfg_gpio: Configure the GPIO for a specific card bit-width
28 * @cfg_card: Configure the interface for a specific card and speed. This
29 * is necessary the controllers and/or GPIO blocks require the
30 * changing of driver-strength and other controls dependant on
31 * the card and speed of operation.
32 *
33 * Initialisation data specific to either the machine or the platform
34 * for the device driver to use or call-back when configuring gpio or
35 * card speed information.
36*/
37struct s3c_sdhci_platdata {
38 unsigned int max_width;
39 unsigned int host_caps;
40
41 char **clocks; /* set of clock sources */
42
43 void (*cfg_gpio)(struct platform_device *dev, int width);
44 void (*cfg_card)(struct platform_device *dev,
45 void __iomem *regbase,
46 struct mmc_ios *ios,
47 struct mmc_card *card);
48};
49
50/**
51 * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
52 * @pd: Platform data to register to device.
53 *
54 * Register the given platform data for use withe S3C SDHCI device.
55 * The call will copy the platform data, so the board definitions can
56 * make the structure itself __initdata.
57 */
58extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
59extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
60
61/* Default platform data, exported so that per-cpu initialisation can
62 * set the correct one when there are more than one cpu type selected.
63*/
64
65extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
66extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
67
68/* Helper function availablity */
69
70#ifdef CONFIG_S3C6410_SETUP_SDHCI
71extern char *s3c6410_hsmmc_clksrcs[4];
72
73extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
74extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
75
76extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
77 void __iomem *r,
78 struct mmc_ios *ios,
79 struct mmc_card *card);
80
81#ifdef CONFIG_S3C_DEV_HSMMC
82static inline void s3c6410_default_sdhci0(void)
83{
84 s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
85 s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
86 s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
87}
88#else
89static inline void s3c6410_default_sdhci0(void) { }
90#endif /* CONFIG_S3C_DEV_HSMMC */
91
92#ifdef CONFIG_S3C_DEV_HSMMC1
93static inline void s3c6410_default_sdhci1(void)
94{
95 s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
96 s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
97 s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
98}
99#else
100static inline void s3c6410_default_sdhci1(void) { }
101#endif /* CONFIG_S3C_DEV_HSMMC1 */
102
103#else
104static inline void s3c6410_default_sdhci0(void) { }
105static inline void s3c6410_default_sdhci1(void) { }
106#endif /* CONFIG_S3C6410_SETUP_SDHCI */
107
108#endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index a8cfdefc29e9..1e0767b266b8 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -33,6 +33,9 @@ obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
33obj-$(CONFIG_S3C2410_DMA) += dma.o 33obj-$(CONFIG_S3C2410_DMA) += dma.o
34obj-$(CONFIG_S3C24XX_ADC) += adc.o 34obj-$(CONFIG_S3C24XX_ADC) += adc.o
35 35
36# device specific setup and/or initialisation
37obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
38
36# SPI gpio central GPIO functions 39# SPI gpio central GPIO functions
37 40
38obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o 41obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 9826efb91e48..14d4f0bc1253 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -271,31 +271,6 @@ struct platform_device s3c_device_wdt = {
271 271
272EXPORT_SYMBOL(s3c_device_wdt); 272EXPORT_SYMBOL(s3c_device_wdt);
273 273
274/* I2C */
275
276static struct resource s3c_i2c_resource[] = {
277 [0] = {
278 .start = S3C24XX_PA_IIC,
279 .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
280 .flags = IORESOURCE_MEM,
281 },
282 [1] = {
283 .start = IRQ_IIC,
284 .end = IRQ_IIC,
285 .flags = IORESOURCE_IRQ,
286 }
287
288};
289
290struct platform_device s3c_device_i2c = {
291 .name = "s3c2410-i2c",
292 .id = -1,
293 .num_resources = ARRAY_SIZE(s3c_i2c_resource),
294 .resource = s3c_i2c_resource,
295};
296
297EXPORT_SYMBOL(s3c_device_i2c);
298
299/* IIS */ 274/* IIS */
300 275
301static struct resource s3c_iis_resource[] = { 276static struct resource s3c_iis_resource[] = {
@@ -411,36 +386,6 @@ struct platform_device s3c_device_sdi = {
411 386
412EXPORT_SYMBOL(s3c_device_sdi); 387EXPORT_SYMBOL(s3c_device_sdi);
413 388
414/* High-speed MMC/SD */
415
416static struct resource s3c_hsmmc_resource[] = {
417 [0] = {
418 .start = S3C2443_PA_HSMMC,
419 .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
420 .flags = IORESOURCE_MEM,
421 },
422 [1] = {
423 .start = IRQ_S3C2443_HSMMC,
424 .end = IRQ_S3C2443_HSMMC,
425 .flags = IORESOURCE_IRQ,
426 }
427};
428
429static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
430
431struct platform_device s3c_device_hsmmc = {
432 .name = "s3c-sdhci",
433 .id = -1,
434 .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
435 .resource = s3c_hsmmc_resource,
436 .dev = {
437 .dma_mask = &s3c_device_hsmmc_dmamask,
438 .coherent_dma_mask = 0xffffffffUL
439 }
440};
441
442
443
444/* SPI (0) */ 389/* SPI (0) */
445 390
446static struct resource s3c_spi0_resource[] = { 391static struct resource s3c_spi0_resource[] = {
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index b07c2d0dd533..f95c6c9d9f1a 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -19,104 +19,12 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21 21
22#include <plat/gpio-core.h>
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23#include <asm/irq.h> 24#include <asm/irq.h>
24 25
25#include <mach/regs-gpio.h> 26#include <mach/regs-gpio.h>
26 27
27struct s3c24xx_gpio_chip {
28 struct gpio_chip chip;
29 void __iomem *base;
30};
31
32static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
33{
34 return container_of(gpc, struct s3c24xx_gpio_chip, chip);
35}
36
37/* these routines are exported for use by other parts of the platform
38 * and system support, but are not intended to be used directly by the
39 * drivers themsevles.
40 */
41
42static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
43{
44 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
45 void __iomem *base = ourchip->base;
46 unsigned long flags;
47 unsigned long con;
48
49 local_irq_save(flags);
50
51 con = __raw_readl(base + 0x00);
52 con &= ~(3 << (offset * 2));
53 con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
54
55 __raw_writel(con, base + 0x00);
56
57 local_irq_restore(flags);
58 return 0;
59}
60
61static int s3c24xx_gpiolib_output(struct gpio_chip *chip,
62 unsigned offset, int value)
63{
64 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
65 void __iomem *base = ourchip->base;
66 unsigned long flags;
67 unsigned long dat;
68 unsigned long con;
69
70 local_irq_save(flags);
71
72 dat = __raw_readl(base + 0x04);
73 dat &= ~(1 << offset);
74 if (value)
75 dat |= 1 << offset;
76 __raw_writel(dat, base + 0x04);
77
78 con = __raw_readl(base + 0x00);
79 con &= ~(3 << (offset * 2));
80 con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
81
82 __raw_writel(con, base + 0x00);
83 __raw_writel(dat, base + 0x04);
84
85 local_irq_restore(flags);
86 return 0;
87}
88
89static void s3c24xx_gpiolib_set(struct gpio_chip *chip,
90 unsigned offset, int value)
91{
92 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
93 void __iomem *base = ourchip->base;
94 unsigned long flags;
95 unsigned long dat;
96
97 local_irq_save(flags);
98
99 dat = __raw_readl(base + 0x04);
100 dat &= ~(1 << offset);
101 if (value)
102 dat |= 1 << offset;
103 __raw_writel(dat, base + 0x04);
104
105 local_irq_restore(flags);
106}
107
108static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
109{
110 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
111 unsigned long val;
112
113 val = __raw_readl(ourchip->base + 0x04);
114 val >>= offset;
115 val &= 1;
116
117 return val;
118}
119
120static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) 28static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
121{ 29{
122 return -EINVAL; 30 return -EINVAL;
@@ -125,7 +33,7 @@ static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
125static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, 33static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
126 unsigned offset, int value) 34 unsigned offset, int value)
127{ 35{
128 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); 36 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
129 void __iomem *base = ourchip->base; 37 void __iomem *base = ourchip->base;
130 unsigned long flags; 38 unsigned long flags;
131 unsigned long dat; 39 unsigned long dat;
@@ -151,7 +59,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
151 return 0; 59 return 0;
152} 60}
153 61
154static struct s3c24xx_gpio_chip gpios[] = { 62struct s3c_gpio_chip s3c24xx_gpios[] = {
155 [0] = { 63 [0] = {
156 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), 64 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
157 .chip = { 65 .chip = {
@@ -219,34 +127,13 @@ static struct s3c24xx_gpio_chip gpios[] = {
219 }, 127 },
220}; 128};
221 129
222static __init void s3c24xx_gpiolib_add(struct s3c24xx_gpio_chip *chip)
223{
224 struct gpio_chip *gc = &chip->chip;
225
226 BUG_ON(!chip->base);
227 BUG_ON(!gc->label);
228 BUG_ON(!gc->ngpio);
229
230 if (!gc->direction_input)
231 gc->direction_input = s3c24xx_gpiolib_input;
232 if (!gc->direction_output)
233 gc->direction_output = s3c24xx_gpiolib_output;
234 if (!gc->set)
235 gc->set = s3c24xx_gpiolib_set;
236 if (!gc->get)
237 gc->get = s3c24xx_gpiolib_get;
238
239 /* gpiochip_add() prints own failure message on error. */
240 gpiochip_add(gc);
241}
242
243static __init int s3c24xx_gpiolib_init(void) 130static __init int s3c24xx_gpiolib_init(void)
244{ 131{
245 struct s3c24xx_gpio_chip *chip = gpios; 132 struct s3c_gpio_chip *chip = s3c24xx_gpios;
246 int gpn; 133 int gpn;
247 134
248 for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++) 135 for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
249 s3c24xx_gpiolib_add(chip); 136 s3c_gpiolib_add(chip);
250 137
251 return 0; 138 return 0;
252} 139}
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h
index e7be0c0d3702..fef8ea8b8e1e 100644
--- a/arch/arm/plat-s3c24xx/include/plat/map.h
+++ b/arch/arm/plat-s3c24xx/include/plat/map.h
@@ -51,7 +51,6 @@
51 51
52/* Standard size definitions for peripheral blocks. */ 52/* Standard size definitions for peripheral blocks. */
53 53
54#define S3C24XX_SZ_IIC SZ_1M
55#define S3C24XX_SZ_IIS SZ_1M 54#define S3C24XX_SZ_IIS SZ_1M
56#define S3C24XX_SZ_ADC SZ_1M 55#define S3C24XX_SZ_ADC SZ_1M
57#define S3C24XX_SZ_SPI SZ_1M 56#define S3C24XX_SZ_SPI SZ_1M
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index 494368403055..c1de6bb0101b 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -68,7 +68,7 @@ void __init s3c244x_map_io(void)
68 /* rename any peripherals used differing from the s3c2410 */ 68 /* rename any peripherals used differing from the s3c2410 */
69 69
70 s3c_device_sdi.name = "s3c2440-sdi"; 70 s3c_device_sdi.name = "s3c2440-sdi";
71 s3c_device_i2c.name = "s3c2440-i2c"; 71 s3c_device_i2c0.name = "s3c2440-i2c";
72 s3c_device_nand.name = "s3c2440-nand"; 72 s3c_device_nand.name = "s3c2440-nand";
73 s3c_device_usbgadget.name = "s3c2440-usbgadget"; 73 s3c_device_usbgadget.name = "s3c2440-usbgadget";
74} 74}
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c
new file mode 100644
index 000000000000..d62b7e7fb355
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/setup-i2c.c
@@ -0,0 +1,25 @@
1/* linux/arch/arm/plat-s3c24xx/setup-i2c.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C24XX Base setup for i2c device
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14
15struct platform_device;
16
17#include <plat/iic.h>
18#include <mach/hardware.h>
19#include <mach/regs-gpio.h>
20
21void s3c_i2c0_cfg_gpio(struct platform_device *dev)
22{
23 s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
24 s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
25}
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index bd832ba0cf77..203dd730d1ca 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -14,6 +14,10 @@ config PLAT_S3C64XX
14 default y 14 default y
15 select NO_IOPORT 15 select NO_IOPORT
16 select ARCH_REQUIRE_GPIOLIB 16 select ARCH_REQUIRE_GPIOLIB
17 select S3C_GPIO_TRACK
18 select S3C_GPIO_PULL_UPDOWN
19 select S3C_GPIO_CFG_S3C24XX
20 select S3C_GPIO_CFG_S3C64XX
17 help 21 help
18 Base platform code for any Samsung S3C64XX device 22 Base platform code for any Samsung S3C64XX device
19 23
@@ -33,4 +37,25 @@ config CPU_S3C6400_CLOCK
33 Common clock support code for the S3C6400 that is shared 37 Common clock support code for the S3C6400 that is shared
34 by other CPUs in the series, such as the S3C6410. 38 by other CPUs in the series, such as the S3C6410.
35 39
40# platform specific device setup
41
42config S3C64XX_SETUP_I2C0
43 bool
44 default y
45 help
46 Common setup code for i2c bus 0.
47
48 Note, currently since i2c0 is always compiled, this setup helper
49 is always compiled with it.
50
51config S3C64XX_SETUP_I2C1
52 bool
53 help
54 Common setup code for i2c bus 1.
55
56config S3C64XX_SETUP_FB_24BPP
57 bool
58 help
59 Common setup code for S3C64XX with an 24bpp RGB display helper.
60
36endif 61endif
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 9c09b0819805..2e6d79bf8f33 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -17,8 +17,15 @@ obj-y += cpu.o
17obj-y += irq.o 17obj-y += irq.o
18obj-y += irq-eint.o 18obj-y += irq-eint.o
19obj-y += clock.o 19obj-y += clock.o
20obj-y += gpiolib.o
20 21
21# CPU support 22# CPU support
22 23
23obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o 24obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
24obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o 25obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
26
27# Device setup
28
29obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
30obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
31obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
new file mode 100644
index 000000000000..cc62941d7b5c
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -0,0 +1,420 @@
1/* arch/arm/plat-s3c64xx/gpiolib.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIOlib support
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/irq.h>
17#include <linux/io.h>
18
19#include <mach/map.h>
20#include <mach/gpio.h>
21#include <mach/gpio-core.h>
22
23#include <plat/gpio-cfg.h>
24#include <plat/gpio-cfg-helpers.h>
25#include <plat/regs-gpio.h>
26
27/* GPIO bank summary:
28 *
29 * Bank GPIOs Style SlpCon ExtInt Group
30 * A 8 4Bit Yes 1
31 * B 7 4Bit Yes 1
32 * C 8 4Bit Yes 2
33 * D 5 4Bit Yes 3
34 * E 5 4Bit Yes None
35 * F 16 2Bit Yes 4 [1]
36 * G 7 4Bit Yes 5
37 * H 10 4Bit[2] Yes 6
38 * I 16 2Bit Yes None
39 * J 12 2Bit Yes None
40 * K 16 4Bit[2] No None
41 * L 15 4Bit[2] No None
42 * M 6 4Bit No IRQ_EINT
43 * N 16 2Bit No IRQ_EINT
44 * O 16 2Bit Yes 7
45 * P 15 2Bit Yes 8
46 * Q 9 2Bit Yes 9
47 *
48 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
49 * [2] BANK has two control registers, GPxCON0 and GPxCON1
50 */
51
52#define OFF_GPCON (0x00)
53#define OFF_GPDAT (0x04)
54
55#define con_4bit_shift(__off) ((__off) * 4)
56
57#if 1
58#define gpio_dbg(x...) do { } while(0)
59#else
60#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
61#endif
62
63/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
64 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
65 * following example:
66 *
67 * base + 0x00: Control register, 4 bits per gpio
68 * gpio n: 4 bits starting at (4*n)
69 * 0000 = input, 0001 = output, others mean special-function
70 * base + 0x04: Data register, 1 bit per gpio
71 * bit n: data bit n
72 *
73 * Note, since the data register is one bit per gpio and is at base + 0x4
74 * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
75 * the output.
76*/
77
78static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
79{
80 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
81 void __iomem *base = ourchip->base;
82 unsigned long con;
83
84 con = __raw_readl(base + OFF_GPCON);
85 con &= ~(0xf << con_4bit_shift(offset));
86 __raw_writel(con, base + OFF_GPCON);
87
88 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
89
90 return 0;
91}
92
93static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
94 unsigned offset, int value)
95{
96 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
97 void __iomem *base = ourchip->base;
98 unsigned long con;
99 unsigned long dat;
100
101 con = __raw_readl(base + OFF_GPCON);
102 con &= ~(0xf << con_4bit_shift(offset));
103 con |= 0x1 << con_4bit_shift(offset);
104
105 dat = __raw_readl(base + OFF_GPDAT);
106 if (value)
107 dat |= 1 << offset;
108 else
109 dat &= ~(1 << offset);
110
111 __raw_writel(dat, base + OFF_GPDAT);
112 __raw_writel(con, base + OFF_GPCON);
113 __raw_writel(dat, base + OFF_GPDAT);
114
115 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
116
117 return 0;
118}
119
120/* The next set of routines are for the case where the GPIO configuration
121 * registers are 4 bits per GPIO but there is more than one register (the
122 * bank has more than 8 GPIOs.
123 *
124 * This case is the similar to the 4 bit case, but the registers are as
125 * follows:
126 *
127 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
128 * gpio n: 4 bits starting at (4*n)
129 * 0000 = input, 0001 = output, others mean special-function
130 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
131 * gpio n: 4 bits starting at (4*n)
132 * 0000 = input, 0001 = output, others mean special-function
133 * base + 0x08: Data register, 1 bit per gpio
134 * bit n: data bit n
135 *
136 * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
137 * store the 'base + 0x4' address so that these routines see the data
138 * register at ourchip->base + 0x04.
139*/
140
141static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
142{
143 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
144 void __iomem *base = ourchip->base;
145 void __iomem *regcon = base;
146 unsigned long con;
147
148 if (offset > 7)
149 offset -= 8;
150 else
151 regcon -= 4;
152
153 con = __raw_readl(regcon);
154 con &= ~(0xf << con_4bit_shift(offset));
155 __raw_writel(con, regcon);
156
157 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
158
159 return 0;
160
161}
162
163static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
164 unsigned offset, int value)
165{
166 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
167 void __iomem *base = ourchip->base;
168 void __iomem *regcon = base;
169 unsigned long con;
170 unsigned long dat;
171
172 if (offset > 7)
173 offset -= 8;
174 else
175 regcon -= 4;
176
177 con = __raw_readl(regcon);
178 con &= ~(0xf << con_4bit_shift(offset));
179 con |= 0x1 << con_4bit_shift(offset);
180
181 dat = __raw_readl(base + OFF_GPDAT);
182 if (value)
183 dat |= 1 << offset;
184 else
185 dat &= ~(1 << offset);
186
187 __raw_writel(dat, base + OFF_GPDAT);
188 __raw_writel(con, regcon);
189 __raw_writel(dat, base + OFF_GPDAT);
190
191 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
192
193 return 0;
194}
195
196static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
197 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
198 .set_pull = s3c_gpio_setpull_updown,
199 .get_pull = s3c_gpio_getpull_updown,
200};
201
202static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
203 .cfg_eint = 7,
204 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
205 .set_pull = s3c_gpio_setpull_updown,
206 .get_pull = s3c_gpio_getpull_updown,
207};
208
209static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
210 .cfg_eint = 3,
211 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
212 .set_pull = s3c_gpio_setpull_updown,
213 .get_pull = s3c_gpio_getpull_updown,
214};
215
216static struct s3c_gpio_chip gpio_4bit[] = {
217 {
218 .base = S3C64XX_GPA_BASE,
219 .config = &gpio_4bit_cfg_eint0111,
220 .chip = {
221 .base = S3C64XX_GPA(0),
222 .ngpio = S3C64XX_GPIO_A_NR,
223 .label = "GPA",
224 },
225 }, {
226 .base = S3C64XX_GPB_BASE,
227 .config = &gpio_4bit_cfg_eint0111,
228 .chip = {
229 .base = S3C64XX_GPB(0),
230 .ngpio = S3C64XX_GPIO_B_NR,
231 .label = "GPB",
232 },
233 }, {
234 .base = S3C64XX_GPC_BASE,
235 .config = &gpio_4bit_cfg_eint0111,
236 .chip = {
237 .base = S3C64XX_GPC(0),
238 .ngpio = S3C64XX_GPIO_C_NR,
239 .label = "GPC",
240 },
241 }, {
242 .base = S3C64XX_GPD_BASE,
243 .config = &gpio_4bit_cfg_eint0111,
244 .chip = {
245 .base = S3C64XX_GPD(0),
246 .ngpio = S3C64XX_GPIO_D_NR,
247 .label = "GPD",
248 },
249 }, {
250 .base = S3C64XX_GPE_BASE,
251 .config = &gpio_4bit_cfg_noint,
252 .chip = {
253 .base = S3C64XX_GPE(0),
254 .ngpio = S3C64XX_GPIO_E_NR,
255 .label = "GPE",
256 },
257 }, {
258 .base = S3C64XX_GPG_BASE,
259 .config = &gpio_4bit_cfg_eint0111,
260 .chip = {
261 .base = S3C64XX_GPG(0),
262 .ngpio = S3C64XX_GPIO_G_NR,
263 .label = "GPG",
264 },
265 }, {
266 .base = S3C64XX_GPM_BASE,
267 .config = &gpio_4bit_cfg_eint0011,
268 .chip = {
269 .base = S3C64XX_GPM(0),
270 .ngpio = S3C64XX_GPIO_M_NR,
271 .label = "GPM",
272 },
273 },
274};
275
276static struct s3c_gpio_chip gpio_4bit2[] = {
277 {
278 .base = S3C64XX_GPH_BASE + 0x4,
279 .config = &gpio_4bit_cfg_eint0111,
280 .chip = {
281 .base = S3C64XX_GPH(0),
282 .ngpio = S3C64XX_GPIO_H_NR,
283 .label = "GPH",
284 },
285 }, {
286 .base = S3C64XX_GPK_BASE + 0x4,
287 .config = &gpio_4bit_cfg_noint,
288 .chip = {
289 .base = S3C64XX_GPK(0),
290 .ngpio = S3C64XX_GPIO_K_NR,
291 .label = "GPK",
292 },
293 }, {
294 .base = S3C64XX_GPL_BASE + 0x4,
295 .config = &gpio_4bit_cfg_eint0011,
296 .chip = {
297 .base = S3C64XX_GPL(0),
298 .ngpio = S3C64XX_GPIO_L_NR,
299 .label = "GPL",
300 },
301 },
302};
303
304static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
305 .set_config = s3c_gpio_setcfg_s3c24xx,
306 .set_pull = s3c_gpio_setpull_updown,
307 .get_pull = s3c_gpio_getpull_updown,
308};
309
310static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
311 .cfg_eint = 2,
312 .set_config = s3c_gpio_setcfg_s3c24xx,
313 .set_pull = s3c_gpio_setpull_updown,
314 .get_pull = s3c_gpio_getpull_updown,
315};
316
317static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
318 .cfg_eint = 3,
319 .set_config = s3c_gpio_setcfg_s3c24xx,
320 .set_pull = s3c_gpio_setpull_updown,
321 .get_pull = s3c_gpio_getpull_updown,
322};
323
324static struct s3c_gpio_chip gpio_2bit[] = {
325 {
326 .base = S3C64XX_GPF_BASE,
327 .config = &gpio_2bit_cfg_eint11,
328 .chip = {
329 .base = S3C64XX_GPF(0),
330 .ngpio = S3C64XX_GPIO_F_NR,
331 .label = "GPF",
332 },
333 }, {
334 .base = S3C64XX_GPI_BASE,
335 .config = &gpio_2bit_cfg_noint,
336 .chip = {
337 .base = S3C64XX_GPI(0),
338 .ngpio = S3C64XX_GPIO_I_NR,
339 .label = "GPI",
340 },
341 }, {
342 .base = S3C64XX_GPJ_BASE,
343 .config = &gpio_2bit_cfg_noint,
344 .chip = {
345 .base = S3C64XX_GPJ(0),
346 .ngpio = S3C64XX_GPIO_J_NR,
347 .label = "GPJ",
348 },
349 }, {
350 .base = S3C64XX_GPN_BASE,
351 .config = &gpio_2bit_cfg_eint10,
352 .chip = {
353 .base = S3C64XX_GPN(0),
354 .ngpio = S3C64XX_GPIO_N_NR,
355 .label = "GPN",
356 },
357 }, {
358 .base = S3C64XX_GPO_BASE,
359 .config = &gpio_2bit_cfg_eint11,
360 .chip = {
361 .base = S3C64XX_GPO(0),
362 .ngpio = S3C64XX_GPIO_O_NR,
363 .label = "GPO",
364 },
365 }, {
366 .base = S3C64XX_GPP_BASE,
367 .config = &gpio_2bit_cfg_eint11,
368 .chip = {
369 .base = S3C64XX_GPP(0),
370 .ngpio = S3C64XX_GPIO_P_NR,
371 .label = "GPP",
372 },
373 }, {
374 .base = S3C64XX_GPQ_BASE,
375 .config = &gpio_2bit_cfg_eint11,
376 .chip = {
377 .base = S3C64XX_GPQ(0),
378 .ngpio = S3C64XX_GPIO_Q_NR,
379 .label = "GPQ",
380 },
381 },
382};
383
384static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
385{
386 chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
387 chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
388}
389
390static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
391{
392 chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
393 chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
394}
395
396static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
397 int nr_chips,
398 void (*fn)(struct s3c_gpio_chip *))
399{
400 for (; nr_chips > 0; nr_chips--, chips++) {
401 if (fn)
402 (fn)(chips);
403 s3c_gpiolib_add(chips);
404 }
405}
406
407static __init int s3c64xx_gpiolib_init(void)
408{
409 s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
410 s3c64xx_gpiolib_add_4bit);
411
412 s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
413 s3c64xx_gpiolib_add_4bit2);
414
415 s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
416
417 return 0;
418}
419
420arch_initcall(s3c64xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
new file mode 100644
index 000000000000..9aa0e427d113
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
@@ -0,0 +1,48 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank A register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00)
16#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04)
17#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08)
18#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c)
19#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10)
20
21#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0)
26#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0)
27
28#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4)
29#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4)
30
31#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8)
32#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8)
33
34#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12)
35#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12)
36
37#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16)
38#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16)
39
40#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20)
41#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20)
42
43#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24)
44#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24)
45
46#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28)
47#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28)
48
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
new file mode 100644
index 000000000000..3933adb4d50a
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
@@ -0,0 +1,60 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank B register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00)
16#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04)
17#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08)
18#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c)
19#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10)
20
21#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0)
26#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0)
27#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0)
28#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0)
29#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0)
30
31#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4)
32#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4)
33#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4)
34#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4)
35#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4)
36
37#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8)
38#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8)
39#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8)
40#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8)
41#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8)
42#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8)
43
44#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12)
45#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12)
46#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12)
47#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12)
48#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12)
49
50#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16)
51#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16)
52#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16)
53#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16)
54
55#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20)
56#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20)
57
58#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24)
59#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24)
60
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
new file mode 100644
index 000000000000..c47daf7e2723
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
@@ -0,0 +1,53 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank C register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00)
16#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04)
17#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08)
18#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c)
19#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10)
20
21#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0)
26#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0)
27
28#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4)
29#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4)
30
31#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8)
32#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8)
33
34#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12)
35#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12)
36
37#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
38#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
39#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16)
40#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
41
42#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
43#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
44#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20)
45#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
46
47#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
48#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
49
50#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
51#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28)
52#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)
53
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
new file mode 100644
index 000000000000..6fe4a49c26f0
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
@@ -0,0 +1,49 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank D register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00)
16#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04)
17#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08)
18#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c)
19#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10)
20
21#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0)
26#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0)
27#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0)
28#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0)
29
30#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4)
31#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4)
32#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4)
33#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4)
34
35#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8)
36#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8)
37#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8)
38#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8)
39
40#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12)
41#define S3C64XX_GPD3_I2S0_DI (0x03 << 12)
42#define S3C64XX_GPD3_AC97_SDI (0x04 << 12)
43#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12)
44
45#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16)
46#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16)
47#define S3C64XX_GPD4_AC97_SDO (0x04 << 16)
48#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16)
49
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
new file mode 100644
index 000000000000..7fcf3d8e0a48
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
@@ -0,0 +1,44 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank E register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00)
16#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04)
17#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08)
18#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c)
19#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10)
20
21#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0)
26#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0)
27#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0)
28
29#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4)
30#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4)
31#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4)
32
33#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8)
34#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8)
35#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8)
36
37#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12)
38#define S3C64XX_GPE3_I2S1_DI (0x03 << 12)
39#define S3C64XX_GPE3_AC97_SDI (0x04 << 12)
40
41#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16)
42#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16)
43#define S3C64XX_GPE4_AC97_SDO (0x04 << 16)
44
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
new file mode 100644
index 000000000000..f3faff974a18
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
@@ -0,0 +1,71 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank F register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
16#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
17#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
18#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
19#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
20
21#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
26#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
27
28#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
29#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
30
31#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
32#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
33
34#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
35#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
36
37#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
38#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
39
40#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
41#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
42
43#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
44#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
45
46#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
47#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
48
49#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
50#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
51
52#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
53#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
54
55#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
56#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
57
58#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
59#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
60
61#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
62#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
63
64#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
65#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
66
67#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
68#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
69
70#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)
71
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
new file mode 100644
index 000000000000..35bbd2378e55
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank G register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
16#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
17#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
18#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
19#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
20
21#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
22#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
23#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
24
25#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
26#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
27
28#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
29#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
30
31#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
32#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
33
34#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
35#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
36
37#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
38#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
39
40#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
41#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)
42
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
new file mode 100644
index 000000000000..81549516572f
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
@@ -0,0 +1,74 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank H register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
16#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
17#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
18#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
19#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
20#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
21
22#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
23#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
24#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
25
26#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
27#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
28#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
29
30#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
31#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
32#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
33
34#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
35#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
36#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
37
38#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
39#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
40#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
41
42#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
43#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
44#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
45
46#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
47#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
48#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
49
50#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
51#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
52#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
53#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
54#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
55#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
56
57#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
58#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
59#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
60#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
61#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
62#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
63
64#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
65#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
66#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
67#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
68#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
69
70#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
71#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
72#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
73#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)
74
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
new file mode 100644
index 000000000000..ce9ebe335566
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
@@ -0,0 +1,40 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank I register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00)
16#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04)
17#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08)
18#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c)
19#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10)
20
21#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPI0_VD0 (0x02 << 0)
26#define S3C64XX_GPI1_VD1 (0x02 << 2)
27#define S3C64XX_GPI2_VD2 (0x02 << 4)
28#define S3C64XX_GPI3_VD3 (0x02 << 6)
29#define S3C64XX_GPI4_VD4 (0x02 << 8)
30#define S3C64XX_GPI5_VD5 (0x02 << 10)
31#define S3C64XX_GPI6_VD6 (0x02 << 12)
32#define S3C64XX_GPI7_VD7 (0x02 << 14)
33#define S3C64XX_GPI8_VD8 (0x02 << 16)
34#define S3C64XX_GPI9_VD9 (0x02 << 18)
35#define S3C64XX_GPI10_VD10 (0x02 << 20)
36#define S3C64XX_GPI11_VD11 (0x02 << 22)
37#define S3C64XX_GPI12_VD12 (0x02 << 24)
38#define S3C64XX_GPI13_VD13 (0x02 << 26)
39#define S3C64XX_GPI14_VD14 (0x02 << 28)
40#define S3C64XX_GPI15_VD15 (0x02 << 30)
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
new file mode 100644
index 000000000000..21a906299d30
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
@@ -0,0 +1,36 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank J register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00)
16#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04)
17#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08)
18#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c)
19#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10)
20
21#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPJ0_VD16 (0x02 << 0)
26#define S3C64XX_GPJ1_VD17 (0x02 << 2)
27#define S3C64XX_GPJ2_VD18 (0x02 << 4)
28#define S3C64XX_GPJ3_VD19 (0x02 << 6)
29#define S3C64XX_GPJ4_VD20 (0x02 << 8)
30#define S3C64XX_GPJ5_VD21 (0x02 << 10)
31#define S3C64XX_GPJ6_VD22 (0x02 << 12)
32#define S3C64XX_GPJ7_VD23 (0x02 << 14)
33#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16)
34#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18)
35#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20)
36#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22)
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
new file mode 100644
index 000000000000..569e76120881
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
@@ -0,0 +1,54 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank N register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
16#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
17#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08)
18
19#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
20#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2))
21#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
22
23#define S3C64XX_GPN0_EINT0 (0x02 << 0)
24#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0)
25
26#define S3C64XX_GPN1_EINT1 (0x02 << 2)
27#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2)
28
29#define S3C64XX_GPN2_EINT2 (0x02 << 4)
30#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4)
31
32#define S3C64XX_GPN3_EINT3 (0x02 << 6)
33#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6)
34
35#define S3C64XX_GPN4_EINT4 (0x02 << 8)
36#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8)
37
38#define S3C64XX_GPN5_EINT5 (0x02 << 10)
39#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10)
40
41#define S3C64XX_GPN6_EINT6 (0x02 << 12)
42#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12)
43
44#define S3C64XX_GPN7_EINT7 (0x02 << 14)
45#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14)
46
47#define S3C64XX_GPN8_EINT8 (0x02 << 16)
48#define S3C64XX_GPN9_EINT9 (0x02 << 18)
49#define S3C64XX_GPN10_EINT10 (0x02 << 20)
50#define S3C64XX_GPN11_EINT11 (0x02 << 22)
51#define S3C64XX_GPN12_EINT12 (0x02 << 24)
52#define S3C64XX_GPN13_EINT13 (0x02 << 26)
53#define S3C64XX_GPN14_EINT14 (0x02 << 28)
54#define S3C64XX_GPN15_EINT15 (0x02 << 30)
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
new file mode 100644
index 000000000000..b09e12954b57
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
@@ -0,0 +1,70 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank O register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00)
16#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04)
17#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08)
18#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c)
19#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10)
20
21#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0)
26#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0)
27
28#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2)
29#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2)
30
31#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4)
32#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4)
33
34#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6)
35#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6)
36
37#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8)
38
39#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10)
40
41#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12)
42#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12)
43
44#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14)
45#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14)
46
47#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16)
48#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16)
49
50#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18)
51#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18)
52
53#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20)
54#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20)
55
56#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22)
57#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22)
58
59#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24)
60#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24)
61
62#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26)
63#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26)
64
65#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28)
66#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28)
67
68#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30)
69#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30)
70
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
new file mode 100644
index 000000000000..92f00517926b
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
@@ -0,0 +1,69 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank P register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
16#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
17#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
18#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
19#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
20
21#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
26#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
27
28#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
29#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
30
31#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
32#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
33
34#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
35#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
36
37#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
38#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
39
40#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
41#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
42
43#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
44#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
45
46#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
47#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
48
49#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
50#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
51
52#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
53#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
54
55#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
56#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
57
58#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
59#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
60
61#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
62#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
63
64#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
65#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
66
67#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
68#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)
69
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
new file mode 100644
index 000000000000..565e60aaee47
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
@@ -0,0 +1,46 @@
1/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * GPIO Bank Q register and configuration definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00)
16#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04)
17#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08)
18#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c)
19#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10)
20
21#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
22#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
23#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
24
25#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0)
26#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0)
27
28#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2)
29#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2)
30
31#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4)
32
33#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6)
34
35#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8)
36
37#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10)
38
39#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12)
40
41#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
42#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14)
43
44#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
45#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16)
46
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h
index bc25689c3f83..02e8dd4c97d5 100644
--- a/arch/arm/plat-s3c64xx/include/plat/irqs.h
+++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h
@@ -70,6 +70,7 @@
70#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) 70#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
71#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) 71#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
72#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) 72#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
73#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
73#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) 74#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
74#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) 75#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
75#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) 76#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
@@ -144,6 +145,10 @@
144#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) 145#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
145#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) 146#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
146 147
148/* compatibility for device defines */
149
150#define IRQ_IIC1 IRQ_S3C6410_IIC1
151
147/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series 152/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
148 * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE 153 * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
149 * which we place after the pair of VICs. */ 154 * which we place after the pair of VICs. */
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
new file mode 100644
index 000000000000..75b873d82808
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h
@@ -0,0 +1,35 @@
1/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C64XX - GPIO register definitions
9 */
10
11#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
12#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
13
14/* Base addresses for each of the banks */
15
16#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000)
17#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020)
18#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040)
19#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060)
20#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080)
21#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0)
22#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0)
23#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0)
24#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100)
25#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120)
26#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800)
27#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810)
28#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820)
29#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830)
30#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140)
31#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160)
32#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180)
33
34#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
35
diff --git a/arch/arm/plat-s3c64xx/setup-fb-24bpp.c b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
new file mode 100644
index 000000000000..8e28e448dd20
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
@@ -0,0 +1,37 @@
1/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Base S3C64XX setup information for 24bpp LCD framebuffer
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/fb.h>
18
19#include <mach/regs-fb.h>
20#include <mach/gpio.h>
21#include <plat/fb.h>
22#include <plat/gpio-cfg.h>
23
24extern void s3c64xx_fb_gpio_setup_24bpp(void)
25{
26 unsigned int gpio;
27
28 for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
29 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
30 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
31 }
32
33 for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
34 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
35 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
36 }
37}
diff --git a/arch/arm/plat-s3c64xx/setup-i2c0.c b/arch/arm/plat-s3c64xx/setup-i2c0.c
new file mode 100644
index 000000000000..364480763728
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-i2c0.c
@@ -0,0 +1,31 @@
1/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Base S3C64XX I2C bus 0 gpio configuration
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <mach/gpio.h>
21#include <plat/iic.h>
22#include <plat/gpio-bank-b.h>
23#include <plat/gpio-cfg.h>
24
25void s3c_i2c0_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
28 s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
29 s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
30 s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
31}
diff --git a/arch/arm/plat-s3c64xx/setup-i2c1.c b/arch/arm/plat-s3c64xx/setup-i2c1.c
new file mode 100644
index 000000000000..bbe229bd90ca
--- /dev/null
+++ b/arch/arm/plat-s3c64xx/setup-i2c1.c
@@ -0,0 +1,31 @@
1/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * Base S3C64XX I2C bus 1 gpio configuration
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <mach/gpio.h>
21#include <plat/iic.h>
22#include <plat/gpio-bank-b.h>
23#include <plat/gpio-cfg.h>
24
25void s3c_i2c1_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
28 s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
29 s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
30 s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
31}