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-rw-r--r--arch/arm/include/asm/sizes.h1
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c23
2 files changed, 13 insertions, 11 deletions
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 503843db1565..c10d1aa4b487 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -43,6 +43,7 @@
43#define SZ_8M 0x00800000 43#define SZ_8M 0x00800000
44#define SZ_16M 0x01000000 44#define SZ_16M 0x01000000
45#define SZ_32M 0x02000000 45#define SZ_32M 0x02000000
46#define SZ_48M 0x03000000
46#define SZ_64M 0x04000000 47#define SZ_64M 0x04000000
47#define SZ_128M 0x08000000 48#define SZ_128M 0x08000000
48#define SZ_256M 0x10000000 49#define SZ_256M 0x10000000
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index d816c51320c7..2d0f09e9819d 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -366,7 +366,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
366} 366}
367 367
368void __init ixp4xx_pci_preinit(void) 368void __init ixp4xx_pci_preinit(void)
369{ 369{
370 unsigned long cpuid = read_cpuid_id(); 370 unsigned long cpuid = read_cpuid_id();
371 371
372 /* 372 /*
@@ -386,17 +386,17 @@ void __init ixp4xx_pci_preinit(void)
386 386
387 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); 387 pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
388 388
389 /* 389 /*
390 * We use identity AHB->PCI address translation 390 * We use identity AHB->PCI address translation
391 * in the 0x48000000 to 0x4bffffff address space 391 * in the 0x48000000 to 0x4bffffff address space
392 */ 392 */
393 *PCI_PCIMEMBASE = 0x48494A4B; 393 *PCI_PCIMEMBASE = 0x48494A4B;
394 394
395 /* 395 /*
396 * We also use identity PCI->AHB address translation 396 * We also use identity PCI->AHB address translation
397 * in 4 16MB BARs that begin at the physical memory start 397 * in 4 16MB BARs that begin at the physical memory start
398 */ 398 */
399 *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + 399 *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
400 ((PHYS_OFFSET & 0xFF000000) >> 8) + 400 ((PHYS_OFFSET & 0xFF000000) >> 8) +
401 ((PHYS_OFFSET & 0xFF000000) >> 16) + 401 ((PHYS_OFFSET & 0xFF000000) >> 16) +
402 ((PHYS_OFFSET & 0xFF000000) >> 24) + 402 ((PHYS_OFFSET & 0xFF000000) >> 24) +
@@ -408,18 +408,19 @@ void __init ixp4xx_pci_preinit(void)
408 pr_debug("setup BARs in controller\n"); 408 pr_debug("setup BARs in controller\n");
409 409
410 /* 410 /*
411 * We configure the PCI inbound memory windows to be 411 * We configure the PCI inbound memory windows to be
412 * 1:1 mapped to SDRAM 412 * 1:1 mapped to SDRAM
413 */ 413 */
414 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000); 414 local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
415 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000); 415 local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
416 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000); 416 local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
417 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000); 417 local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);
418 418
419 /* 419 /*
420 * Enable CSR window at 0xff000000. 420 * Enable CSR window at 64 MiB to allow PCI masters
421 * to continue prefetching past 64 MiB boundary.
421 */ 422 */
422 local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008); 423 local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
423 424
424 /* 425 /*
425 * Enable the IO window to be way up high, at 0xfffffc00 426 * Enable the IO window to be way up high, at 0xfffffc00