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-rw-r--r--arch/sh/Kconfig10
-rw-r--r--arch/sh/Makefile3
-rw-r--r--arch/sh/boards/mpc1211/pci.c2
-rw-r--r--arch/sh/boards/renesas/r7780rp/setup.c54
-rw-r--r--arch/sh/boards/renesas/rts7751r2d/setup.c3
-rw-r--r--arch/sh/boards/se/7722/irq.c96
-rw-r--r--arch/sh/boards/se/7722/setup.c5
-rw-r--r--arch/sh/cchips/hd6446x/Makefile2
-rw-r--r--arch/sh/cchips/hd6446x/hd64461.c (renamed from arch/sh/cchips/hd6446x/hd64461/setup.c)1
-rw-r--r--arch/sh/cchips/hd6446x/hd64461/Makefile6
-rw-r--r--arch/sh/cchips/hd6446x/hd64461/io.c150
-rw-r--r--arch/sh/configs/landisk_defconfig2
-rw-r--r--arch/sh/configs/lboxre2_defconfig2
-rw-r--r--arch/sh/configs/r7780mp_defconfig2
-rw-r--r--arch/sh/configs/r7780rp_defconfig2
-rw-r--r--arch/sh/configs/rts7751r2d_defconfig8
-rw-r--r--arch/sh/configs/se7722_defconfig4
-rw-r--r--arch/sh/configs/se7750_defconfig2
-rw-r--r--arch/sh/configs/se7780_defconfig1
-rw-r--r--arch/sh/drivers/dma/Kconfig3
-rw-r--r--arch/sh/drivers/heartbeat.c2
-rw-r--r--arch/sh/drivers/pci/Makefile1
-rw-r--r--arch/sh/drivers/pci/ops-sh4.c2
-rw-r--r--arch/sh/drivers/pci/pci-st40.c2
-rw-r--r--arch/sh/drivers/pci/pci.c2
-rw-r--r--arch/sh/drivers/push-switch.c2
-rw-r--r--arch/sh/kernel/cpu/clock.c16
-rw-r--r--arch/sh/kernel/cpu/irq/Makefile1
-rw-r--r--arch/sh/kernel/cpu/irq/intc.c405
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c2
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7709.c2
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c255
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c15
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c178
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c221
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c2
-rw-r--r--arch/sh/kernel/cpufreq.c215
-rw-r--r--arch/sh/kernel/head.S3
-rw-r--r--arch/sh/kernel/irq.c9
-rw-r--r--arch/sh/kernel/setup.c7
-rw-r--r--arch/sh/kernel/sh_bios.c3
-rw-r--r--arch/sh/kernel/sh_ksyms.c35
-rw-r--r--arch/sh/kernel/syscalls.S1
-rw-r--r--arch/sh/kernel/vmlinux.lds.S1
-rw-r--r--arch/sh/mm/Kconfig16
50 files changed, 1229 insertions, 543 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index d8ed6676ae86..f87f429e0b24 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -178,6 +178,9 @@ config CPU_HAS_PINT_IRQ
178config CPU_HAS_MASKREG_IRQ 178config CPU_HAS_MASKREG_IRQ
179 bool 179 bool
180 180
181config CPU_HAS_INTC_IRQ
182 bool
183
181config CPU_HAS_INTC2_IRQ 184config CPU_HAS_INTC2_IRQ
182 bool 185 bool
183 186
@@ -209,6 +212,7 @@ config SOLUTION_ENGINE
209config SH_SOLUTION_ENGINE 212config SH_SOLUTION_ENGINE
210 bool "SolutionEngine" 213 bool "SolutionEngine"
211 select SOLUTION_ENGINE 214 select SOLUTION_ENGINE
215 select CPU_HAS_IPR_IRQ
212 depends on CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750 216 depends on CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750
213 help 217 help
214 Select SolutionEngine if configuring for a Hitachi SH7709 218 Select SolutionEngine if configuring for a Hitachi SH7709
@@ -241,6 +245,7 @@ config SH_7722_SOLUTION_ENGINE
241config SH_7751_SOLUTION_ENGINE 245config SH_7751_SOLUTION_ENGINE
242 bool "SolutionEngine7751" 246 bool "SolutionEngine7751"
243 select SOLUTION_ENGINE 247 select SOLUTION_ENGINE
248 select CPU_HAS_IPR_IRQ
244 depends on CPU_SUBTYPE_SH7751 249 depends on CPU_SUBTYPE_SH7751
245 help 250 help
246 Select 7751 SolutionEngine if configuring for a Hitachi SH7751 251 Select 7751 SolutionEngine if configuring for a Hitachi SH7751
@@ -250,6 +255,7 @@ config SH_7780_SOLUTION_ENGINE
250 bool "SolutionEngine7780" 255 bool "SolutionEngine7780"
251 select SOLUTION_ENGINE 256 select SOLUTION_ENGINE
252 select SYS_SUPPORTS_PCI 257 select SYS_SUPPORTS_PCI
258 select CPU_HAS_INTC2_IRQ
253 depends on CPU_SUBTYPE_SH7780 259 depends on CPU_SUBTYPE_SH7780
254 help 260 help
255 Select 7780 SolutionEngine if configuring for a Renesas SH7780 261 Select 7780 SolutionEngine if configuring for a Renesas SH7780
@@ -317,6 +323,7 @@ config SH_MPC1211
317config SH_SH03 323config SH_SH03
318 bool "Interface CTP/PCI-SH03" 324 bool "Interface CTP/PCI-SH03"
319 depends on CPU_SUBTYPE_SH7751 && BROKEN 325 depends on CPU_SUBTYPE_SH7751 && BROKEN
326 select CPU_HAS_IPR_IRQ
320 select SYS_SUPPORTS_PCI 327 select SYS_SUPPORTS_PCI
321 help 328 help
322 CTP/PCI-SH03 is a CPU module computer that is produced 329 CTP/PCI-SH03 is a CPU module computer that is produced
@@ -326,6 +333,7 @@ config SH_SH03
326config SH_SECUREEDGE5410 333config SH_SECUREEDGE5410
327 bool "SecureEdge5410" 334 bool "SecureEdge5410"
328 depends on CPU_SUBTYPE_SH7751R 335 depends on CPU_SUBTYPE_SH7751R
336 select CPU_HAS_IPR_IRQ
329 select SYS_SUPPORTS_PCI 337 select SYS_SUPPORTS_PCI
330 help 338 help
331 Select SecureEdge5410 if configuring for a SnapGear SH board. 339 Select SecureEdge5410 if configuring for a SnapGear SH board.
@@ -380,6 +388,7 @@ config SH_LANDISK
380config SH_TITAN 388config SH_TITAN
381 bool "TITAN" 389 bool "TITAN"
382 depends on CPU_SUBTYPE_SH7751R 390 depends on CPU_SUBTYPE_SH7751R
391 select CPU_HAS_IPR_IRQ
383 select SYS_SUPPORTS_PCI 392 select SYS_SUPPORTS_PCI
384 help 393 help
385 Select Titan if you are configuring for a Nimble Microsystems 394 Select Titan if you are configuring for a Nimble Microsystems
@@ -388,6 +397,7 @@ config SH_TITAN
388config SH_SHMIN 397config SH_SHMIN
389 bool "SHMIN" 398 bool "SHMIN"
390 depends on CPU_SUBTYPE_SH7706 399 depends on CPU_SUBTYPE_SH7706
400 select CPU_HAS_IPR_IRQ
391 help 401 help
392 Select SHMIN if configuring for the SHMIN board. 402 Select SHMIN if configuring for the SHMIN board.
393 403
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 77fecc62a056..0016609d1eba 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -121,8 +121,7 @@ core-y += $(addprefix arch/sh/boards/, \
121endif 121endif
122 122
123# Companion chips 123# Companion chips
124core-$(CONFIG_HD64461) += arch/sh/cchips/hd6446x/hd64461/ 124core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/
125core-$(CONFIG_HD64465) += arch/sh/cchips/hd6446x/hd64465/
126core-$(CONFIG_VOYAGERGX) += arch/sh/cchips/voyagergx/ 125core-$(CONFIG_VOYAGERGX) += arch/sh/cchips/voyagergx/
127 126
128cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2 127cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2
diff --git a/arch/sh/boards/mpc1211/pci.c b/arch/sh/boards/mpc1211/pci.c
index 4ed1a95c6d56..23849f70f133 100644
--- a/arch/sh/boards/mpc1211/pci.c
+++ b/arch/sh/boards/mpc1211/pci.c
@@ -187,7 +187,7 @@ char * __devinit pcibios_setup(char *str)
187 * are examined. 187 * are examined.
188 */ 188 */
189 189
190void __init pcibios_fixup_bus(struct pci_bus *b) 190void __devinit pcibios_fixup_bus(struct pci_bus *b)
191{ 191{
192 pci_read_bridge_bases(b); 192 pci_read_bridge_bases(b);
193} 193}
diff --git a/arch/sh/boards/renesas/r7780rp/setup.c b/arch/sh/boards/renesas/r7780rp/setup.c
index 5afb864a1ec5..adb529d01bae 100644
--- a/arch/sh/boards/renesas/r7780rp/setup.c
+++ b/arch/sh/boards/renesas/r7780rp/setup.c
@@ -21,6 +21,58 @@
21#include <asm/clock.h> 21#include <asm/clock.h>
22#include <asm/io.h> 22#include <asm/io.h>
23 23
24static struct resource r8a66597_usb_host_resources[] = {
25 [0] = {
26 .name = "r8a66597_hcd",
27 .start = 0xA4200000,
28 .end = 0xA42000FF,
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .name = "r8a66597_hcd",
33 .start = 11, /* irq number */
34 .end = 11,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39static struct platform_device r8a66597_usb_host_device = {
40 .name = "r8a66597_hcd",
41 .id = -1,
42 .dev = {
43 .dma_mask = NULL, /* don't use dma */
44 .coherent_dma_mask = 0xffffffff,
45 },
46 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
47 .resource = r8a66597_usb_host_resources,
48};
49
50static struct resource m66592_usb_peripheral_resources[] = {
51 [0] = {
52 .name = "m66592_udc",
53 .start = 0xb0000000,
54 .end = 0xb00000FF,
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .name = "m66592_udc",
59 .start = 9, /* irq number */
60 .end = 9,
61 .flags = IORESOURCE_IRQ,
62 },
63};
64
65static struct platform_device m66592_usb_peripheral_device = {
66 .name = "m66592_udc",
67 .id = -1,
68 .dev = {
69 .dma_mask = NULL, /* don't use dma */
70 .coherent_dma_mask = 0xffffffff,
71 },
72 .num_resources = ARRAY_SIZE(m66592_usb_peripheral_resources),
73 .resource = m66592_usb_peripheral_resources,
74};
75
24static struct resource cf_ide_resources[] = { 76static struct resource cf_ide_resources[] = {
25 [0] = { 77 [0] = {
26 .start = PA_AREA5_IO + 0x1000, 78 .start = PA_AREA5_IO + 0x1000,
@@ -81,6 +133,8 @@ static struct platform_device heartbeat_device = {
81}; 133};
82 134
83static struct platform_device *r7780rp_devices[] __initdata = { 135static struct platform_device *r7780rp_devices[] __initdata = {
136 &r8a66597_usb_host_device,
137 &m66592_usb_peripheral_device,
84 &cf_ide_device, 138 &cf_ide_device,
85 &heartbeat_device, 139 &heartbeat_device,
86}; 140};
diff --git a/arch/sh/boards/renesas/rts7751r2d/setup.c b/arch/sh/boards/renesas/rts7751r2d/setup.c
index 656fda30ef70..e165d85c03b5 100644
--- a/arch/sh/boards/renesas/rts7751r2d/setup.c
+++ b/arch/sh/boards/renesas/rts7751r2d/setup.c
@@ -86,7 +86,8 @@ static struct plat_serial8250_port uart_platform_data[] = {
86 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 86 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
87 .regshift = 2, 87 .regshift = 2,
88 .uartclk = (9600 * 16), 88 .uartclk = (9600 * 16),
89 } 89 },
90 { 0 },
90}; 91};
91 92
92static struct platform_device uart_device = { 93static struct platform_device uart_device = {
diff --git a/arch/sh/boards/se/7722/irq.c b/arch/sh/boards/se/7722/irq.c
index 26cff0efda40..0b03f3f610b8 100644
--- a/arch/sh/boards/se/7722/irq.c
+++ b/arch/sh/boards/se/7722/irq.c
@@ -16,95 +16,61 @@
16#include <asm/io.h> 16#include <asm/io.h>
17#include <asm/se7722.h> 17#include <asm/se7722.h>
18 18
19#define INTC_INTMSK0 0xFFD00044
20#define INTC_INTMSKCLR0 0xFFD00064
21
22struct se7722_data {
23 unsigned char irq;
24 unsigned char ipr_idx;
25 unsigned char shift;
26 unsigned short priority;
27 unsigned long addr;
28};
29
30
31static void disable_se7722_irq(unsigned int irq) 19static void disable_se7722_irq(unsigned int irq)
32{ 20{
33 struct se7722_data *p = get_irq_chip_data(irq); 21 unsigned int bit = irq - SE7722_FPGA_IRQ_BASE;
34 ctrl_outw( ctrl_inw( p->addr ) | p->priority , p->addr ); 22 ctrl_outw(ctrl_inw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
35} 23}
36 24
37static void enable_se7722_irq(unsigned int irq) 25static void enable_se7722_irq(unsigned int irq)
38{ 26{
39 struct se7722_data *p = get_irq_chip_data(irq); 27 unsigned int bit = irq - SE7722_FPGA_IRQ_BASE;
40 ctrl_outw( ctrl_inw( p->addr ) & ~p->priority , p->addr ); 28 ctrl_outw(ctrl_inw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
41} 29}
42 30
43static struct irq_chip se7722_irq_chip __read_mostly = { 31static struct irq_chip se7722_irq_chip __read_mostly = {
44 .name = "SE7722", 32 .name = "SE7722-FPGA",
45 .mask = disable_se7722_irq, 33 .mask = disable_se7722_irq,
46 .unmask = enable_se7722_irq, 34 .unmask = enable_se7722_irq,
47 .mask_ack = disable_se7722_irq, 35 .mask_ack = disable_se7722_irq,
48}; 36};
49 37
50static struct se7722_data ipr_irq_table[] = { 38static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
51 /* irq ,idx,sft, priority , addr */
52 { MRSHPC_IRQ0 , 0 , 0 , MRSHPC_BIT0 , IRQ01_MASK } ,
53 { MRSHPC_IRQ1 , 0 , 0 , MRSHPC_BIT1 , IRQ01_MASK } ,
54 { MRSHPC_IRQ2 , 0 , 0 , MRSHPC_BIT2 , IRQ01_MASK } ,
55 { MRSHPC_IRQ3 , 0 , 0 , MRSHPC_BIT3 , IRQ01_MASK } ,
56 { SMC_IRQ , 0 , 0 , SMC_BIT , IRQ01_MASK } ,
57 { EXT_IRQ , 0 , 0 , EXT_BIT , IRQ01_MASK } ,
58};
59
60int se7722_irq_demux(int irq)
61{ 39{
40 unsigned short intv = ctrl_inw(IRQ01_STS);
41 struct irq_desc *ext_desc;
42 unsigned int ext_irq = SE7722_FPGA_IRQ_BASE;
43
44 intv &= (1 << SE7722_FPGA_IRQ_NR) - 1;
62 45
63 if ((irq == IRQ0_IRQ)||(irq == IRQ1_IRQ)) { 46 while (intv) {
64 volatile unsigned short intv = 47 if (intv & 1) {
65 *(volatile unsigned short *)IRQ01_STS; 48 ext_desc = irq_desc + ext_irq;
66 if (irq == IRQ0_IRQ){ 49 handle_level_irq(ext_irq, ext_desc);
67 if(intv & SMC_BIT ) {
68 return SMC_IRQ;
69 } else if(intv & USB_BIT) {
70 return USB_IRQ;
71 } else {
72 printk("intv =%04x\n", intv);
73 return SMC_IRQ;
74 }
75 } else if(irq == IRQ1_IRQ){
76 if(intv & MRSHPC_BIT0) {
77 return MRSHPC_IRQ0;
78 } else if(intv & MRSHPC_BIT1) {
79 return MRSHPC_IRQ1;
80 } else if(intv & MRSHPC_BIT2) {
81 return MRSHPC_IRQ2;
82 } else if(intv & MRSHPC_BIT3) {
83 return MRSHPC_IRQ3;
84 } else {
85 printk("BIT_EXTENTION =%04x\n", intv);
86 return EXT_IRQ;
87 }
88 } 50 }
51 intv >>= 1;
52 ext_irq++;
89 } 53 }
90 return irq;
91
92} 54}
55
93/* 56/*
94 * Initialize IRQ setting 57 * Initialize IRQ setting
95 */ 58 */
96void __init init_se7722_IRQ(void) 59void __init init_se7722_IRQ(void)
97{ 60{
98 int i = 0; 61 int i;
62
63 ctrl_outw(0, IRQ01_MASK); /* disable all irqs */
99 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ 64 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
100 ctrl_outl((3 << ((7 - 0) * 4))|(3 << ((7 - 1) * 4)), INTC_INTPRI0); /* irq0 pri=3,irq1,pri=3 */
101 ctrl_outw((2 << ((7 - 0) * 2))|(2 << ((7 - 1) * 2)), INTC_ICR1); /* irq0,1 low-level irq */
102 65
103 for (i = 0; i < ARRAY_SIZE(ipr_irq_table); i++) { 66 for (i = 0; i < SE7722_FPGA_IRQ_NR; i++)
104 disable_irq_nosync(ipr_irq_table[i].irq); 67 set_irq_chip_and_handler_name(SE7722_FPGA_IRQ_BASE + i,
105 set_irq_chip_and_handler_name( ipr_irq_table[i].irq, &se7722_irq_chip, 68 &se7722_irq_chip,
106 handle_level_irq, "level"); 69 handle_level_irq, "level");
107 set_irq_chip_data( ipr_irq_table[i].irq, &ipr_irq_table[i] ); 70
108 disable_se7722_irq(ipr_irq_table[i].irq); 71 set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux);
109 } 72 set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
73
74 set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux);
75 set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
110} 76}
diff --git a/arch/sh/boards/se/7722/setup.c b/arch/sh/boards/se/7722/setup.c
index 6cca6cbc8069..495fc7e2b60f 100644
--- a/arch/sh/boards/se/7722/setup.c
+++ b/arch/sh/boards/se/7722/setup.c
@@ -77,6 +77,7 @@ static struct resource cf_ide_resources[] = {
77 }, 77 },
78 [2] = { 78 [2] = {
79 .start = MRSHPC_IRQ0, 79 .start = MRSHPC_IRQ0,
80 .end = MRSHPC_IRQ0,
80 .flags = IORESOURCE_IRQ, 81 .flags = IORESOURCE_IRQ,
81 }, 82 },
82}; 83};
@@ -140,8 +141,6 @@ static void __init se7722_setup(char **cmdline_p)
140static struct sh_machine_vector mv_se7722 __initmv = { 141static struct sh_machine_vector mv_se7722 __initmv = {
141 .mv_name = "Solution Engine 7722" , 142 .mv_name = "Solution Engine 7722" ,
142 .mv_setup = se7722_setup , 143 .mv_setup = se7722_setup ,
143 .mv_nr_irqs = 109 , 144 .mv_nr_irqs = SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_NR,
144 .mv_init_irq = init_se7722_IRQ, 145 .mv_init_irq = init_se7722_IRQ,
145 .mv_irq_demux = se7722_irq_demux,
146
147}; 146};
diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile
new file mode 100644
index 000000000000..a106dd9db986
--- /dev/null
+++ b/arch/sh/cchips/hd6446x/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_HD64461) += hd64461.o
2obj-$(CONFIG_HD64465) += hd64465/
diff --git a/arch/sh/cchips/hd6446x/hd64461/setup.c b/arch/sh/cchips/hd6446x/hd64461.c
index 4d49b5cbcc13..97f6512aa1b7 100644
--- a/arch/sh/cchips/hd6446x/hd64461/setup.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -1,5 +1,4 @@
1/* 1/*
2 * $Id: setup.c,v 1.5 2004/03/16 00:07:50 lethal Exp $
3 * Copyright (C) 2000 YAEGASHI Takeshi 2 * Copyright (C) 2000 YAEGASHI Takeshi
4 * Hitachi HD64461 companion chip support 3 * Hitachi HD64461 companion chip support
5 */ 4 */
diff --git a/arch/sh/cchips/hd6446x/hd64461/Makefile b/arch/sh/cchips/hd6446x/hd64461/Makefile
deleted file mode 100644
index bff4b92e388c..000000000000
--- a/arch/sh/cchips/hd6446x/hd64461/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
1#
2# Makefile for the HD64461
3#
4
5obj-y := setup.o io.o
6
diff --git a/arch/sh/cchips/hd6446x/hd64461/io.c b/arch/sh/cchips/hd6446x/hd64461/io.c
deleted file mode 100644
index 7909a1b7b512..000000000000
--- a/arch/sh/cchips/hd6446x/hd64461/io.c
+++ /dev/null
@@ -1,150 +0,0 @@
1/*
2 * Copyright (C) 2000 YAEGASHI Takeshi
3 * Typical I/O routines for HD64461 system.
4 */
5
6#include <asm/io.h>
7#include <asm/hd64461.h>
8
9#define MEM_BASE (CONFIG_HD64461_IOBASE - HD64461_STBCR)
10
11static __inline__ unsigned long PORT2ADDR(unsigned long port)
12{
13 /* 16550A: HD64461 internal */
14 if (0x3f8<=port && port<=0x3ff)
15 return CONFIG_HD64461_IOBASE + 0x8000 + ((port-0x3f8)<<1);
16 if (0x2f8<=port && port<=0x2ff)
17 return CONFIG_HD64461_IOBASE + 0x7000 + ((port-0x2f8)<<1);
18
19#ifdef CONFIG_HD64461_ENABLER
20 /* NE2000: HD64461 PCMCIA channel 0 (I/O) */
21 if (0x300<=port && port<=0x31f)
22 return 0xba000000 + port;
23
24 /* ide0: HD64461 PCMCIA channel 1 (memory) */
25 /* On HP690, CF in slot 1 is configured as a memory card
26 device. See CF+ and CompactFlash Specification for the
27 detail of CF's memory mapped addressing. */
28 if (0x1f0<=port && port<=0x1f7) return 0xb5000000 + port;
29 if (port == 0x3f6) return 0xb50001fe;
30 if (port == 0x3f7) return 0xb50001ff;
31
32 /* ide1 */
33 if (0x170<=port && port<=0x177) return 0xba000000 + port;
34 if (port == 0x376) return 0xba000376;
35 if (port == 0x377) return 0xba000377;
36#endif
37
38 /* ??? */
39 if (port < 0xf000) return 0xa0000000 + port;
40 /* PCMCIA channel 0, I/O (0xba000000) */
41 if (port < 0x10000) return 0xba000000 + port - 0xf000;
42
43 /* HD64461 internal devices (0xb0000000) */
44 if (port < 0x20000) return CONFIG_HD64461_IOBASE + port - 0x10000;
45
46 /* PCMCIA channel 0, I/O (0xba000000) */
47 if (port < 0x30000) return 0xba000000 + port - 0x20000;
48
49 /* PCMCIA channel 1, memory (0xb5000000) */
50 if (port < 0x40000) return 0xb5000000 + port - 0x30000;
51
52 /* Whole physical address space (0xa0000000) */
53 return 0xa0000000 + (port & 0x1fffffff);
54}
55
56unsigned char hd64461_inb(unsigned long port)
57{
58 return *(volatile unsigned char*)PORT2ADDR(port);
59}
60
61unsigned char hd64461_inb_p(unsigned long port)
62{
63 unsigned long v = *(volatile unsigned char*)PORT2ADDR(port);
64 ctrl_delay();
65 return v;
66}
67
68unsigned short hd64461_inw(unsigned long port)
69{
70 return *(volatile unsigned short*)PORT2ADDR(port);
71}
72
73unsigned int hd64461_inl(unsigned long port)
74{
75 return *(volatile unsigned long*)PORT2ADDR(port);
76}
77
78void hd64461_outb(unsigned char b, unsigned long port)
79{
80 *(volatile unsigned char*)PORT2ADDR(port) = b;
81}
82
83void hd64461_outb_p(unsigned char b, unsigned long port)
84{
85 *(volatile unsigned char*)PORT2ADDR(port) = b;
86 ctrl_delay();
87}
88
89void hd64461_outw(unsigned short b, unsigned long port)
90{
91 *(volatile unsigned short*)PORT2ADDR(port) = b;
92}
93
94void hd64461_outl(unsigned int b, unsigned long port)
95{
96 *(volatile unsigned long*)PORT2ADDR(port) = b;
97}
98
99void hd64461_insb(unsigned long port, void *buffer, unsigned long count)
100{
101 volatile unsigned char* addr=(volatile unsigned char*)PORT2ADDR(port);
102 unsigned char *buf=buffer;
103 while(count--) *buf++=*addr;
104}
105
106void hd64461_insw(unsigned long port, void *buffer, unsigned long count)
107{
108 volatile unsigned short* addr=(volatile unsigned short*)PORT2ADDR(port);
109 unsigned short *buf=buffer;
110 while(count--) *buf++=*addr;
111}
112
113void hd64461_insl(unsigned long port, void *buffer, unsigned long count)
114{
115 volatile unsigned long* addr=(volatile unsigned long*)PORT2ADDR(port);
116 unsigned long *buf=buffer;
117 while(count--) *buf++=*addr;
118}
119
120void hd64461_outsb(unsigned long port, const void *buffer, unsigned long count)
121{
122 volatile unsigned char* addr=(volatile unsigned char*)PORT2ADDR(port);
123 const unsigned char *buf=buffer;
124 while(count--) *addr=*buf++;
125}
126
127void hd64461_outsw(unsigned long port, const void *buffer, unsigned long count)
128{
129 volatile unsigned short* addr=(volatile unsigned short*)PORT2ADDR(port);
130 const unsigned short *buf=buffer;
131 while(count--) *addr=*buf++;
132}
133
134void hd64461_outsl(unsigned long port, const void *buffer, unsigned long count)
135{
136 volatile unsigned long* addr=(volatile unsigned long*)PORT2ADDR(port);
137 const unsigned long *buf=buffer;
138 while(count--) *addr=*buf++;
139}
140
141unsigned short hd64461_readw(void __iomem *addr)
142{
143 return ctrl_inw(MEM_BASE+(unsigned long __force)addr);
144}
145
146void hd64461_writew(unsigned short b, void __iomem *addr)
147{
148 ctrl_outw(b, MEM_BASE+(unsigned long __force)addr);
149}
150
diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig
index e7f8ddb0ada4..07310fa03250 100644
--- a/arch/sh/configs/landisk_defconfig
+++ b/arch/sh/configs/landisk_defconfig
@@ -217,7 +217,7 @@ CONFIG_SH_FPU=y
217# CONFIG_SH_DSP is not set 217# CONFIG_SH_DSP is not set
218# CONFIG_SH_STORE_QUEUES is not set 218# CONFIG_SH_STORE_QUEUES is not set
219CONFIG_CPU_HAS_INTEVT=y 219CONFIG_CPU_HAS_INTEVT=y
220CONFIG_CPU_HAS_IPR_IRQ=y 220CONFIG_CPU_HAS_INTC_IRQ=y
221CONFIG_CPU_HAS_SR_RB=y 221CONFIG_CPU_HAS_SR_RB=y
222CONFIG_CPU_HAS_PTEA=y 222CONFIG_CPU_HAS_PTEA=y
223 223
diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig
index be86414dcc87..fa09d68d057a 100644
--- a/arch/sh/configs/lboxre2_defconfig
+++ b/arch/sh/configs/lboxre2_defconfig
@@ -222,7 +222,7 @@ CONFIG_SH_FPU=y
222# CONFIG_SH_DSP is not set 222# CONFIG_SH_DSP is not set
223# CONFIG_SH_STORE_QUEUES is not set 223# CONFIG_SH_STORE_QUEUES is not set
224CONFIG_CPU_HAS_INTEVT=y 224CONFIG_CPU_HAS_INTEVT=y
225CONFIG_CPU_HAS_IPR_IRQ=y 225CONFIG_CPU_HAS_INTC_IRQ=y
226CONFIG_CPU_HAS_SR_RB=y 226CONFIG_CPU_HAS_SR_RB=y
227CONFIG_CPU_HAS_PTEA=y 227CONFIG_CPU_HAS_PTEA=y
228 228
diff --git a/arch/sh/configs/r7780mp_defconfig b/arch/sh/configs/r7780mp_defconfig
index 17f7402b31d8..ac4de4973b60 100644
--- a/arch/sh/configs/r7780mp_defconfig
+++ b/arch/sh/configs/r7780mp_defconfig
@@ -191,7 +191,7 @@ CONFIG_SH_FPU=y
191CONFIG_SH_STORE_QUEUES=y 191CONFIG_SH_STORE_QUEUES=y
192CONFIG_SPECULATIVE_EXECUTION=y 192CONFIG_SPECULATIVE_EXECUTION=y
193CONFIG_CPU_HAS_INTEVT=y 193CONFIG_CPU_HAS_INTEVT=y
194CONFIG_CPU_HAS_INTC2_IRQ=y 194CONFIG_CPU_HAS_INTC_IRQ=y
195CONFIG_CPU_HAS_SR_RB=y 195CONFIG_CPU_HAS_SR_RB=y
196 196
197# 197#
diff --git a/arch/sh/configs/r7780rp_defconfig b/arch/sh/configs/r7780rp_defconfig
index 48c6a2194c98..12cc01910cf8 100644
--- a/arch/sh/configs/r7780rp_defconfig
+++ b/arch/sh/configs/r7780rp_defconfig
@@ -241,7 +241,7 @@ CONFIG_SH_FPU=y
241CONFIG_SH_STORE_QUEUES=y 241CONFIG_SH_STORE_QUEUES=y
242CONFIG_SPECULATIVE_EXECUTION=y 242CONFIG_SPECULATIVE_EXECUTION=y
243CONFIG_CPU_HAS_INTEVT=y 243CONFIG_CPU_HAS_INTEVT=y
244CONFIG_CPU_HAS_INTC2_IRQ=y 244CONFIG_CPU_HAS_INTC_IRQ=y
245CONFIG_CPU_HAS_SR_RB=y 245CONFIG_CPU_HAS_SR_RB=y
246 246
247# 247#
diff --git a/arch/sh/configs/rts7751r2d_defconfig b/arch/sh/configs/rts7751r2d_defconfig
index a59bb78bd071..f1e979b1e495 100644
--- a/arch/sh/configs/rts7751r2d_defconfig
+++ b/arch/sh/configs/rts7751r2d_defconfig
@@ -155,7 +155,7 @@ CONFIG_CPU_SH4=y
155# CONFIG_CPU_SUBTYPE_SH7091 is not set 155# CONFIG_CPU_SUBTYPE_SH7091 is not set
156# CONFIG_CPU_SUBTYPE_SH7750R is not set 156# CONFIG_CPU_SUBTYPE_SH7750R is not set
157# CONFIG_CPU_SUBTYPE_SH7750S is not set 157# CONFIG_CPU_SUBTYPE_SH7750S is not set
158CONFIG_CPU_SUBTYPE_SH7751=y 158# CONFIG_CPU_SUBTYPE_SH7751 is not set
159CONFIG_CPU_SUBTYPE_SH7751R=y 159CONFIG_CPU_SUBTYPE_SH7751R=y
160# CONFIG_CPU_SUBTYPE_SH7760 is not set 160# CONFIG_CPU_SUBTYPE_SH7760 is not set
161# CONFIG_CPU_SUBTYPE_SH4_202 is not set 161# CONFIG_CPU_SUBTYPE_SH4_202 is not set
@@ -218,7 +218,7 @@ CONFIG_SH_FPU=y
218# CONFIG_SH_DSP is not set 218# CONFIG_SH_DSP is not set
219# CONFIG_SH_STORE_QUEUES is not set 219# CONFIG_SH_STORE_QUEUES is not set
220CONFIG_CPU_HAS_INTEVT=y 220CONFIG_CPU_HAS_INTEVT=y
221CONFIG_CPU_HAS_IPR_IRQ=y 221CONFIG_CPU_HAS_INTC_IRQ=y
222CONFIG_CPU_HAS_SR_RB=y 222CONFIG_CPU_HAS_SR_RB=y
223CONFIG_CPU_HAS_PTEA=y 223CONFIG_CPU_HAS_PTEA=y
224 224
@@ -280,7 +280,7 @@ CONFIG_ZERO_PAGE_OFFSET=0x00010000
280CONFIG_BOOT_LINK_OFFSET=0x00800000 280CONFIG_BOOT_LINK_OFFSET=0x00800000
281# CONFIG_UBC_WAKEUP is not set 281# CONFIG_UBC_WAKEUP is not set
282CONFIG_CMDLINE_BOOL=y 282CONFIG_CMDLINE_BOOL=y
283CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1" 283CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=bios"
284 284
285# 285#
286# Bus options 286# Bus options
@@ -1323,7 +1323,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1323# CONFIG_DEBUG_KERNEL is not set 1323# CONFIG_DEBUG_KERNEL is not set
1324CONFIG_LOG_BUF_SHIFT=14 1324CONFIG_LOG_BUF_SHIFT=14
1325# CONFIG_DEBUG_BUGVERBOSE is not set 1325# CONFIG_DEBUG_BUGVERBOSE is not set
1326# CONFIG_SH_STANDARD_BIOS is not set 1326CONFIG_SH_STANDARD_BIOS=y
1327CONFIG_EARLY_SCIF_CONSOLE=y 1327CONFIG_EARLY_SCIF_CONSOLE=y
1328CONFIG_EARLY_SCIF_CONSOLE_PORT=0xffe80000 1328CONFIG_EARLY_SCIF_CONSOLE_PORT=0xffe80000
1329CONFIG_EARLY_PRINTK=y 1329CONFIG_EARLY_PRINTK=y
diff --git a/arch/sh/configs/se7722_defconfig b/arch/sh/configs/se7722_defconfig
index 764b813c4051..8e6a6baf5d27 100644
--- a/arch/sh/configs/se7722_defconfig
+++ b/arch/sh/configs/se7722_defconfig
@@ -200,7 +200,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y
200CONFIG_SH_DSP=y 200CONFIG_SH_DSP=y
201CONFIG_SH_STORE_QUEUES=y 201CONFIG_SH_STORE_QUEUES=y
202CONFIG_CPU_HAS_INTEVT=y 202CONFIG_CPU_HAS_INTEVT=y
203CONFIG_CPU_HAS_IPR_IRQ=y 203CONFIG_CPU_HAS_INTC_IRQ=y
204CONFIG_CPU_HAS_SR_RB=y 204CONFIG_CPU_HAS_SR_RB=y
205CONFIG_CPU_HAS_PTEA=y 205CONFIG_CPU_HAS_PTEA=y
206 206
@@ -565,7 +565,7 @@ CONFIG_SERIO_LIBPS2=y
565# Non-8250 serial port support 565# Non-8250 serial port support
566# 566#
567CONFIG_SERIAL_SH_SCI=y 567CONFIG_SERIAL_SH_SCI=y
568CONFIG_SERIAL_SH_SCI_NR_UARTS=2 568CONFIG_SERIAL_SH_SCI_NR_UARTS=3
569CONFIG_SERIAL_SH_SCI_CONSOLE=y 569CONFIG_SERIAL_SH_SCI_CONSOLE=y
570CONFIG_SERIAL_CORE=y 570CONFIG_SERIAL_CORE=y
571CONFIG_SERIAL_CORE_CONSOLE=y 571CONFIG_SERIAL_CORE_CONSOLE=y
diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig
index 4e6e77fa4ce7..c60b6fd4fc42 100644
--- a/arch/sh/configs/se7750_defconfig
+++ b/arch/sh/configs/se7750_defconfig
@@ -226,7 +226,7 @@ CONFIG_SH_FPU=y
226# CONFIG_SH_DSP is not set 226# CONFIG_SH_DSP is not set
227# CONFIG_SH_STORE_QUEUES is not set 227# CONFIG_SH_STORE_QUEUES is not set
228CONFIG_CPU_HAS_INTEVT=y 228CONFIG_CPU_HAS_INTEVT=y
229CONFIG_CPU_HAS_IPR_IRQ=y 229CONFIG_CPU_HAS_INTC_IRQ=y
230CONFIG_CPU_HAS_SR_RB=y 230CONFIG_CPU_HAS_SR_RB=y
231CONFIG_CPU_HAS_PTEA=y 231CONFIG_CPU_HAS_PTEA=y
232 232
diff --git a/arch/sh/configs/se7780_defconfig b/arch/sh/configs/se7780_defconfig
index 538661e98793..f68743dc3931 100644
--- a/arch/sh/configs/se7780_defconfig
+++ b/arch/sh/configs/se7780_defconfig
@@ -218,6 +218,7 @@ CONFIG_SH_FPU=y
218# CONFIG_SH_STORE_QUEUES is not set 218# CONFIG_SH_STORE_QUEUES is not set
219CONFIG_CPU_HAS_INTEVT=y 219CONFIG_CPU_HAS_INTEVT=y
220CONFIG_CPU_HAS_INTC2_IRQ=y 220CONFIG_CPU_HAS_INTC2_IRQ=y
221CONFIG_CPU_HAS_INTC_IRQ=y
221CONFIG_CPU_HAS_SR_RB=y 222CONFIG_CPU_HAS_SR_RB=y
222 223
223# 224#
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 333898077c7c..ee711431e504 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -5,12 +5,13 @@ config SH_DMA_API
5 5
6config SH_DMA 6config SH_DMA
7 bool "SuperH on-chip DMA controller (DMAC) support" 7 bool "SuperH on-chip DMA controller (DMAC) support"
8 depends on CPU_SH3 || CPU_SH4
8 select SH_DMA_API 9 select SH_DMA_API
9 default n 10 default n
10 11
11config NR_ONCHIP_DMA_CHANNELS 12config NR_ONCHIP_DMA_CHANNELS
13 int
12 depends on SH_DMA 14 depends on SH_DMA
13 int "Number of on-chip DMAC channels"
14 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R 15 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
15 default "12" if CPU_SUBTYPE_SH7780 16 default "12" if CPU_SUBTYPE_SH7780
16 default "4" 17 default "4"
diff --git a/arch/sh/drivers/heartbeat.c b/arch/sh/drivers/heartbeat.c
index 23dd6080422f..10c1828c9ff5 100644
--- a/arch/sh/drivers/heartbeat.c
+++ b/arch/sh/drivers/heartbeat.c
@@ -78,7 +78,7 @@ static int heartbeat_drv_probe(struct platform_device *pdev)
78 hd->bit_pos[i] = i; 78 hd->bit_pos[i] = i;
79 } 79 }
80 80
81 hd->base = (void __iomem *)res->start; 81 hd->base = (void __iomem *)(unsigned long)res->start;
82 82
83 setup_timer(&hd->timer, heartbeat_timer, (unsigned long)hd); 83 setup_timer(&hd->timer, heartbeat_timer, (unsigned long)hd);
84 platform_set_drvdata(pdev, hd); 84 platform_set_drvdata(pdev, hd);
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 0e9b532b9fbc..2f65ac72f48a 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
7 7
8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o 8obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
12 13
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 54232f13e406..710a3b0306e5 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -153,7 +153,7 @@ static void __init pci_fixup_ide_bases(struct pci_dev *d)
153} 153}
154DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); 154DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
155 155
156char * __init pcibios_setup(char *str) 156char * __devinit pcibios_setup(char *str)
157{ 157{
158 if (!strcmp(str, "off")) { 158 if (!strcmp(str, "off")) {
159 pci_probe = 0; 159 pci_probe = 0;
diff --git a/arch/sh/drivers/pci/pci-st40.c b/arch/sh/drivers/pci/pci-st40.c
index 543417ff8314..1502a14386b6 100644
--- a/arch/sh/drivers/pci/pci-st40.c
+++ b/arch/sh/drivers/pci/pci-st40.c
@@ -328,7 +328,7 @@ int __init st40pci_init(unsigned memStart, unsigned memSize)
328 return 1; 328 return 1;
329} 329}
330 330
331char * __init pcibios_setup(char *str) 331char * __devinit pcibios_setup(char *str)
332{ 332{
333 return str; 333 return str;
334} 334}
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index d439336d2e18..ccaba368ac9b 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -71,7 +71,7 @@ subsys_initcall(pcibios_init);
71 * Called after each bus is probed, but before its children 71 * Called after each bus is probed, but before its children
72 * are examined. 72 * are examined.
73 */ 73 */
74void __init pcibios_fixup_bus(struct pci_bus *bus) 74void __devinit pcibios_fixup_bus(struct pci_bus *bus)
75{ 75{
76 pci_read_bridge_bases(bus); 76 pci_read_bridge_bases(bus);
77} 77}
diff --git a/arch/sh/drivers/push-switch.c b/arch/sh/drivers/push-switch.c
index b3d20c0e021f..725be6de589b 100644
--- a/arch/sh/drivers/push-switch.c
+++ b/arch/sh/drivers/push-switch.c
@@ -138,4 +138,4 @@ module_exit(switch_exit);
138 138
139MODULE_VERSION(DRV_VERSION); 139MODULE_VERSION(DRV_VERSION);
140MODULE_AUTHOR("Paul Mundt"); 140MODULE_AUTHOR("Paul Mundt");
141MODULE_LICENSE("GPLv2"); 141MODULE_LICENSE("GPL v2");
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 63251549e9a8..92807ffa8e20 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -229,6 +229,22 @@ void clk_recalc_rate(struct clk *clk)
229} 229}
230EXPORT_SYMBOL_GPL(clk_recalc_rate); 230EXPORT_SYMBOL_GPL(clk_recalc_rate);
231 231
232long clk_round_rate(struct clk *clk, unsigned long rate)
233{
234 if (likely(clk->ops && clk->ops->round_rate)) {
235 unsigned long flags, rounded;
236
237 spin_lock_irqsave(&clock_lock, flags);
238 rounded = clk->ops->round_rate(clk, rate);
239 spin_unlock_irqrestore(&clock_lock, flags);
240
241 return rounded;
242 }
243
244 return clk_get_rate(clk);
245}
246EXPORT_SYMBOL_GPL(clk_round_rate);
247
232/* 248/*
233 * Returns a clock. Note that we first try to use device id on the bus 249 * Returns a clock. Note that we first try to use device id on the bus
234 * and clock name. If this fails, we try to use clock name only. 250 * and clock name. If this fails, we try to use clock name only.
diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile
index 1c23308cfc25..9ddb446ac930 100644
--- a/arch/sh/kernel/cpu/irq/Makefile
+++ b/arch/sh/kernel/cpu/irq/Makefile
@@ -6,4 +6,5 @@ obj-y += imask.o
6obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o 6obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
7obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o 7obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
8obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o 8obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
9obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o
9obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o 10obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
new file mode 100644
index 000000000000..9345a7130e9e
--- /dev/null
+++ b/arch/sh/kernel/cpu/irq/intc.c
@@ -0,0 +1,405 @@
1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/interrupt.h>
23
24#define _INTC_MK(fn, idx, bit, value) \
25 ((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
26#define _INTC_FN(h) (h >> 24)
27#define _INTC_VALUE(h) ((h >> 16) & 0xff)
28#define _INTC_IDX(h) ((h >> 8) & 0xff)
29#define _INTC_BIT(h) (h & 0xff)
30
31#define _INTC_PTR(desc, member, data) \
32 (desc->member + _INTC_IDX(data))
33
34static inline struct intc_desc *get_intc_desc(unsigned int irq)
35{
36 struct irq_chip *chip = get_irq_chip(irq);
37 return (void *)((char *)chip - offsetof(struct intc_desc, chip));
38}
39
40static inline unsigned int set_field(unsigned int value,
41 unsigned int field_value,
42 unsigned int width,
43 unsigned int shift)
44{
45 value &= ~(((1 << width) - 1) << shift);
46 value |= field_value << shift;
47 return value;
48}
49
50static inline unsigned int set_prio_field(struct intc_desc *desc,
51 unsigned int value,
52 unsigned int priority,
53 unsigned int data)
54{
55 unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
56
57 return set_field(value, priority, width, _INTC_BIT(data));
58}
59
60static void disable_prio_16(struct intc_desc *desc, unsigned int data)
61{
62 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
63
64 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
65}
66
67static void enable_prio_16(struct intc_desc *desc, unsigned int data)
68{
69 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
70 unsigned int prio = _INTC_VALUE(data);
71
72 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
73}
74
75static void disable_prio_32(struct intc_desc *desc, unsigned int data)
76{
77 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
78
79 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
80}
81
82static void enable_prio_32(struct intc_desc *desc, unsigned int data)
83{
84 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
85 unsigned int prio = _INTC_VALUE(data);
86
87 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
88}
89
90static void disable_mask_8(struct intc_desc *desc, unsigned int data)
91{
92 ctrl_outb(1 << _INTC_BIT(data),
93 _INTC_PTR(desc, mask_regs, data)->set_reg);
94}
95
96static void enable_mask_8(struct intc_desc *desc, unsigned int data)
97{
98 ctrl_outb(1 << _INTC_BIT(data),
99 _INTC_PTR(desc, mask_regs, data)->clr_reg);
100}
101
102static void disable_mask_32(struct intc_desc *desc, unsigned int data)
103{
104 ctrl_outl(1 << _INTC_BIT(data),
105 _INTC_PTR(desc, mask_regs, data)->set_reg);
106}
107
108static void enable_mask_32(struct intc_desc *desc, unsigned int data)
109{
110 ctrl_outl(1 << _INTC_BIT(data),
111 _INTC_PTR(desc, mask_regs, data)->clr_reg);
112}
113
114enum { REG_FN_ERROR=0,
115 REG_FN_MASK_8, REG_FN_MASK_32,
116 REG_FN_PRIO_16, REG_FN_PRIO_32 };
117
118static struct {
119 void (*enable)(struct intc_desc *, unsigned int);
120 void (*disable)(struct intc_desc *, unsigned int);
121} intc_reg_fns[] = {
122 [REG_FN_MASK_8] = { enable_mask_8, disable_mask_8 },
123 [REG_FN_MASK_32] = { enable_mask_32, disable_mask_32 },
124 [REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
125 [REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
126};
127
128static void intc_enable(unsigned int irq)
129{
130 struct intc_desc *desc = get_intc_desc(irq);
131 unsigned int data = (unsigned int) get_irq_chip_data(irq);
132
133 intc_reg_fns[_INTC_FN(data)].enable(desc, data);
134}
135
136static void intc_disable(unsigned int irq)
137{
138 struct intc_desc *desc = get_intc_desc(irq);
139 unsigned int data = (unsigned int) get_irq_chip_data(irq);
140
141 intc_reg_fns[_INTC_FN(data)].disable(desc, data);
142}
143
144static void set_sense_16(struct intc_desc *desc, unsigned int data)
145{
146 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
147 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
148 unsigned int bit = _INTC_BIT(data);
149 unsigned int value = _INTC_VALUE(data);
150
151 ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
152}
153
154static void set_sense_32(struct intc_desc *desc, unsigned int data)
155{
156 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
157 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
158 unsigned int bit = _INTC_BIT(data);
159 unsigned int value = _INTC_VALUE(data);
160
161 ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
162}
163
164#define VALID(x) (x | 0x80)
165
166static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
167 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
168 [IRQ_TYPE_EDGE_RISING] = VALID(1),
169 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
170 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
171};
172
173static int intc_set_sense(unsigned int irq, unsigned int type)
174{
175 struct intc_desc *desc = get_intc_desc(irq);
176 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
177 unsigned int i, j, data, bit;
178 intc_enum enum_id = 0;
179
180 for (i = 0; i < desc->nr_vectors; i++) {
181 struct intc_vect *vect = desc->vectors + i;
182
183 if (evt2irq(vect->vect) != irq)
184 continue;
185
186 enum_id = vect->enum_id;
187 break;
188 }
189
190 if (!enum_id || !value)
191 return -EINVAL;
192
193 value ^= VALID(0);
194
195 for (i = 0; i < desc->nr_sense_regs; i++) {
196 struct intc_sense_reg *sr = desc->sense_regs + i;
197
198 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
199 if (sr->enum_ids[j] != enum_id)
200 continue;
201
202 bit = sr->reg_width - ((j + 1) * sr->field_width);
203 data = _INTC_MK(0, i, bit, value);
204
205 switch(sr->reg_width) {
206 case 16:
207 set_sense_16(desc, data);
208 break;
209 case 32:
210 set_sense_32(desc, data);
211 break;
212 }
213
214 return 0;
215 }
216 }
217
218 return -EINVAL;
219}
220
221static unsigned int __init intc_find_mask_handler(unsigned int width)
222{
223 switch (width) {
224 case 8:
225 return REG_FN_MASK_8;
226 case 32:
227 return REG_FN_MASK_32;
228 }
229
230 BUG();
231 return REG_FN_ERROR;
232}
233
234static unsigned int __init intc_find_prio_handler(unsigned int width)
235{
236 switch (width) {
237 case 16:
238 return REG_FN_PRIO_16;
239 case 32:
240 return REG_FN_PRIO_32;
241 }
242
243 BUG();
244 return REG_FN_ERROR;
245}
246
247static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id)
248{
249 struct intc_group *g = desc->groups;
250 unsigned int i, j;
251
252 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
253 g = desc->groups + i;
254
255 for (j = 0; g->enum_ids[j]; j++) {
256 if (g->enum_ids[j] != enum_id)
257 continue;
258
259 return g->enum_id;
260 }
261 }
262
263 return 0;
264}
265
266static unsigned int __init intc_prio_value(struct intc_desc *desc,
267 intc_enum enum_id, int do_grps)
268{
269 struct intc_prio *p = desc->priorities;
270 unsigned int i;
271
272 for (i = 0; p && enum_id && i < desc->nr_priorities; i++) {
273 p = desc->priorities + i;
274
275 if (p->enum_id != enum_id)
276 continue;
277
278 return p->priority;
279 }
280
281 if (do_grps)
282 return intc_prio_value(desc, intc_grp_id(desc, enum_id), 0);
283
284 /* default to the lowest priority possible if no priority is set
285 * - this needs to be at least 2 for 5-bit priorities on 7780
286 */
287
288 return 2;
289}
290
291static unsigned int __init intc_mask_data(struct intc_desc *desc,
292 intc_enum enum_id, int do_grps)
293{
294 struct intc_mask_reg *mr = desc->mask_regs;
295 unsigned int i, j, fn;
296
297 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
298 mr = desc->mask_regs + i;
299
300 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
301 if (mr->enum_ids[j] != enum_id)
302 continue;
303
304 fn = intc_find_mask_handler(mr->reg_width);
305 if (fn == REG_FN_ERROR)
306 return 0;
307
308 return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
309 }
310 }
311
312 if (do_grps)
313 return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0);
314
315 return 0;
316}
317
318static unsigned int __init intc_prio_data(struct intc_desc *desc,
319 intc_enum enum_id, int do_grps)
320{
321 struct intc_prio_reg *pr = desc->prio_regs;
322 unsigned int i, j, fn, bit, prio;
323
324 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
325 pr = desc->prio_regs + i;
326
327 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
328 if (pr->enum_ids[j] != enum_id)
329 continue;
330
331 fn = intc_find_prio_handler(pr->reg_width);
332 if (fn == REG_FN_ERROR)
333 return 0;
334
335 prio = intc_prio_value(desc, enum_id, 1);
336 bit = pr->reg_width - ((j + 1) * pr->field_width);
337
338 BUG_ON(bit < 0);
339
340 return _INTC_MK(fn, i, bit, prio);
341 }
342 }
343
344 if (do_grps)
345 return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0);
346
347 return 0;
348}
349
350static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
351 unsigned int irq)
352{
353 unsigned int data[2], primary;
354
355 /* Prefer single interrupt source bitmap over other combinations:
356 * 1. bitmap, single interrupt source
357 * 2. priority, single interrupt source
358 * 3. bitmap, multiple interrupt sources (groups)
359 * 4. priority, multiple interrupt sources (groups)
360 */
361
362 data[0] = intc_mask_data(desc, enum_id, 0);
363 data[1] = intc_prio_data(desc, enum_id, 0);
364
365 primary = 0;
366 if (!data[0] && data[1])
367 primary = 1;
368
369 data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1);
370 data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1);
371
372 if (!data[primary])
373 primary ^= 1;
374
375 BUG_ON(!data[primary]); /* must have primary masking method */
376
377 disable_irq_nosync(irq);
378 set_irq_chip_and_handler_name(irq, &desc->chip,
379 handle_level_irq, "level");
380 set_irq_chip_data(irq, (void *)data[primary]);
381
382 /* enable secondary masking method if present */
383 if (data[!primary])
384 intc_reg_fns[_INTC_FN(data[!primary])].enable(desc,
385 data[!primary]);
386
387 /* irq should be disabled by default */
388 desc->chip.mask(irq);
389}
390
391void __init register_intc_controller(struct intc_desc *desc)
392{
393 unsigned int i;
394
395 desc->chip.mask = intc_disable;
396 desc->chip.unmask = intc_enable;
397 desc->chip.mask_ack = intc_disable;
398 desc->chip.set_type = intc_set_sense;
399
400 for (i = 0; i < desc->nr_vectors; i++) {
401 struct intc_vect *vect = desc->vectors + i;
402
403 intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));
404 }
405}
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 1a107fe22dde..a979b981e6a3 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -88,7 +88,7 @@ static struct ipr_desc ipr_irq_desc = {
88 }, 88 },
89}; 89};
90 90
91void __init init_IRQ_ipr(void) 91void __init plat_irq_setup(void)
92{ 92{
93 register_ipr_controller(&ipr_irq_desc); 93 register_ipr_controller(&ipr_irq_desc);
94} 94}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index b6e3a6351fa6..deab16500167 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -107,7 +107,7 @@ static struct ipr_desc ipr_irq_desc = {
107 }, 107 },
108}; 108};
109 109
110void __init init_IRQ_ipr(void) 110void __init plat_irq_setup(void)
111{ 111{
112 register_ipr_controller(&ipr_irq_desc); 112 register_ipr_controller(&ipr_irq_desc);
113} 113}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index a55b8ce2c54c..ebd9d06d8bdd 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -92,7 +92,7 @@ static struct ipr_desc ipr_irq_desc = {
92 }, 92 },
93}; 93};
94 94
95void __init init_IRQ_ipr(void) 95void __init plat_irq_setup(void)
96{ 96{
97 register_ipr_controller(&ipr_irq_desc); 97 register_ipr_controller(&ipr_irq_desc);
98} 98}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7709.c b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
index d79ec0c0522f..086f8e2545af 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7709.c
@@ -139,7 +139,7 @@ static struct ipr_desc ipr_irq_desc = {
139 }, 139 },
140}; 140};
141 141
142void __init init_IRQ_ipr(void) 142void __init plat_irq_setup(void)
143{ 143{
144 register_ipr_controller(&ipr_irq_desc); 144 register_ipr_controller(&ipr_irq_desc);
145} 145}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index f40e6dac337d..132284893373 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -101,7 +101,7 @@ static struct ipr_desc ipr_irq_desc = {
101 }, 101 },
102}; 102};
103 103
104void __init init_IRQ_ipr(void) 104void __init plat_irq_setup(void)
105{ 105{
106 register_ipr_controller(&ipr_irq_desc); 106 register_ipr_controller(&ipr_irq_desc);
107} 107}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index da153bcdfeb2..f2286de22bd5 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -82,88 +82,213 @@ static int __init sh7750_devices_setup(void)
82} 82}
83__initcall(sh7750_devices_setup); 83__initcall(sh7750_devices_setup);
84 84
85static struct ipr_data ipr_irq_table[] = { 85enum {
86 /* IRQ, IPR-idx, shift, priority */ 86 UNUSED = 0,
87 { 16, 0, 12, 2 }, /* TMU0 TUNI*/ 87
88 { 17, 0, 12, 2 }, /* TMU1 TUNI */ 88 /* interrupt sources */
89 { 18, 0, 4, 2 }, /* TMU2 TUNI */ 89 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
90 { 19, 0, 4, 2 }, /* TMU2 TIPCI */ 90 HUDI, GPIOI,
91 { 27, 1, 12, 2 }, /* WDT ITI */ 91 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
92 { 20, 0, 0, 2 }, /* RTC ATI (alarm) */ 92 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
93 { 21, 0, 0, 2 }, /* RTC PRI (period) */ 93 DMAC_DMAE,
94 { 22, 0, 0, 2 }, /* RTC CUI (carry) */ 94 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
95 { 23, 1, 4, 3 }, /* SCI ERI */ 95 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
96 { 24, 1, 4, 3 }, /* SCI RXI */ 96 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
97 { 25, 1, 4, 3 }, /* SCI TXI */ 97 RTC_ATI, RTC_PRI, RTC_CUI,
98 { 40, 2, 4, 3 }, /* SCIF ERI */ 98 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
99 { 41, 2, 4, 3 }, /* SCIF RXI */ 99 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
100 { 42, 2, 4, 3 }, /* SCIF BRI */ 100 WDT,
101 { 43, 2, 4, 3 }, /* SCIF TXI */ 101 REF_RCMI, REF_ROVI,
102 { 34, 2, 8, 7 }, /* DMAC DMTE0 */ 102
103 { 35, 2, 8, 7 }, /* DMAC DMTE1 */ 103 /* interrupt groups */
104 { 36, 2, 8, 7 }, /* DMAC DMTE2 */ 104 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
105 { 37, 2, 8, 7 }, /* DMAC DMTE3 */
106 { 38, 2, 8, 7 }, /* DMAC DMAE */
107};
108
109static unsigned long ipr_offsets[] = {
110 0xffd00004UL, /* 0: IPRA */
111 0xffd00008UL, /* 1: IPRB */
112 0xffd0000cUL, /* 2: IPRC */
113 0xffd00010UL, /* 3: IPRD */
114};
115
116static struct ipr_desc ipr_irq_desc = {
117 .ipr_offsets = ipr_offsets,
118 .nr_offsets = ARRAY_SIZE(ipr_offsets),
119
120 .ipr_data = ipr_irq_table,
121 .nr_irqs = ARRAY_SIZE(ipr_irq_table),
122
123 .chip = {
124 .name = "IPR-sh7750",
125 },
126}; 105};
127 106
128#ifdef CONFIG_CPU_SUBTYPE_SH7751 107static struct intc_vect vectors[] = {
129static struct ipr_data ipr_irq_table_sh7751[] = { 108 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
130 { 44, 2, 8, 7 }, /* DMAC DMTE4 */ 109 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
131 { 45, 2, 8, 7 }, /* DMAC DMTE5 */ 110 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
132 { 46, 2, 8, 7 }, /* DMAC DMTE6 */ 111 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
133 { 47, 2, 8, 7 }, /* DMAC DMTE7 */ 112 INTC_VECT(RTC_CUI, 0x4c0),
134 /* The following use INTC_INPRI00 for masking, which is a 32-bit 113 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
135 register, not a 16-bit register like the IPRx registers, so it 114 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
136 would need special support */ 115 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
137 /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */ 116 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
138 /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */ 117 INTC_VECT(WDT, 0x560),
118 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
139}; 119};
140 120
141static struct ipr_desc ipr_irq_desc_sh7751 = { 121static struct intc_group groups[] = {
142 .ipr_offsets = ipr_offsets, 122 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
143 .nr_offsets = ARRAY_SIZE(ipr_offsets), 123 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
124 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
125 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
126 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
127};
144 128
145 .ipr_data = ipr_irq_table_sh7751, 129static struct intc_prio priorities[] = {
146 .nr_irqs = ARRAY_SIZE(ipr_irq_table_sh7751), 130 INTC_PRIO(SCIF, 3),
131 INTC_PRIO(SCI1, 3),
132 INTC_PRIO(DMAC, 7),
133};
147 134
148 .chip = { 135static struct intc_prio_reg prio_registers[] = {
149 .name = "IPR-sh7751", 136 { 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
150 }, 137 { 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
138 { 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
139 { 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
140 { 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
141 TMU4, TMU3,
142 PCIC1, PCIC0_PCISERR } },
143};
144
145static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
146 priorities, NULL, prio_registers, NULL);
147
148/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
149#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
150 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
151 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
152 defined(CONFIG_CPU_SUBTYPE_SH7091)
153static struct intc_vect vectors_dma4[] = {
154 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
155 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
156 INTC_VECT(DMAC_DMAE, 0x6c0),
157};
158
159static struct intc_group groups_dma4[] = {
160 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
161 DMAC_DMTE3, DMAC_DMAE),
162};
163
164static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
165 vectors_dma4, groups_dma4,
166 priorities, NULL, prio_registers, NULL);
167#endif
168
169/* SH7750R and SH7751R both have 8-channel DMA controllers */
170#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
171static struct intc_vect vectors_dma8[] = {
172 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
173 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
174 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
175 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
176 INTC_VECT(DMAC_DMAE, 0x6c0),
177};
178
179static struct intc_group groups_dma8[] = {
180 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
181 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
182 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
183};
184
185static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
186 vectors_dma8, groups_dma8,
187 priorities, NULL, prio_registers, NULL);
188#endif
189
190/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
191#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
193 defined(CONFIG_CPU_SUBTYPE_SH7751R)
194static struct intc_vect vectors_tmu34[] = {
195 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
151}; 196};
197
198static struct intc_mask_reg mask_registers[] = {
199 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
200 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 0, 0, 0, 0, 0, 0, TMU4, TMU3,
202 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
203 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
204 PCIC1_PCIDMA3, PCIC0_PCISERR } },
205};
206
207static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
208 vectors_tmu34, NULL, priorities,
209 mask_registers, prio_registers, NULL);
152#endif 210#endif
153 211
154void __init init_IRQ_ipr(void) 212/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
213static struct intc_vect vectors_irlm[] = {
214 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
215 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
216};
217
218static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
219 priorities, NULL, prio_registers, NULL);
220
221/* SH7751 and SH7751R both have PCI */
222#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
223static struct intc_vect vectors_pci[] = {
224 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
225 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
226 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
227 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
228};
229
230static struct intc_group groups_pci[] = {
231 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
232 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
233};
234
235static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
236 priorities, mask_registers, prio_registers, NULL);
237#endif
238
239#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
240 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
241 defined(CONFIG_CPU_SUBTYPE_SH7091)
242void __init plat_irq_setup(void)
155{ 243{
156 register_ipr_controller(&ipr_irq_desc); 244 /*
157#ifdef CONFIG_CPU_SUBTYPE_SH7751 245 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
158 register_ipr_controller(&ipr_irq_desc_sh7751); 246 * see below..
247 */
248 register_intc_controller(&intc_desc);
249 register_intc_controller(&intc_desc_dma4);
250}
159#endif 251#endif
252
253#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
254void __init plat_irq_setup(void)
255{
256 register_intc_controller(&intc_desc);
257 register_intc_controller(&intc_desc_dma8);
258 register_intc_controller(&intc_desc_tmu34);
160} 259}
260#endif
261
262#if defined(CONFIG_CPU_SUBTYPE_SH7751)
263void __init plat_irq_setup(void)
264{
265 register_intc_controller(&intc_desc);
266 register_intc_controller(&intc_desc_dma4);
267 register_intc_controller(&intc_desc_tmu34);
268 register_intc_controller(&intc_desc_pci);
269}
270#endif
271
272#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
273void __init plat_irq_setup(void)
274{
275 register_intc_controller(&intc_desc);
276 register_intc_controller(&intc_desc_dma8);
277 register_intc_controller(&intc_desc_tmu34);
278 register_intc_controller(&intc_desc_pci);
279}
280#endif
161 281
162#define INTC_ICR 0xffd00000UL 282#define INTC_ICR 0xffd00000UL
163#define INTC_ICR_IRLM (1<<7) 283#define INTC_ICR_IRLM (1<<7)
164 284
165/* enable individual interrupt mode for external interupts */ 285/* enable individual interrupt mode for external interupts */
166void ipr_irq_enable_irlm(void) 286void __init ipr_irq_enable_irlm(void)
167{ 287{
288#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
289 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
290#endif
291 register_intc_controller(&intc_desc_irlm);
292
168 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 293 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
169} 294}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 3df169755673..47fa27056253 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -109,11 +109,6 @@ static struct intc2_desc intc2_irq_desc __read_mostly = {
109 }, 109 },
110}; 110};
111 111
112void __init init_IRQ_intc2(void)
113{
114 register_intc2_controller(&intc2_irq_desc);
115}
116
117static struct ipr_data ipr_irq_table[] = { 112static struct ipr_data ipr_irq_table[] = {
118 /* IRQ, IPR-idx, shift, priority */ 113 /* IRQ, IPR-idx, shift, priority */
119 { 16, 0, 12, 2 }, /* TMU0 TUNI*/ 114 { 16, 0, 12, 2 }, /* TMU0 TUNI*/
@@ -163,7 +158,8 @@ static struct ipr_desc ipr_irq_desc = {
163 }, 158 },
164}; 159};
165 160
166void __init init_IRQ_ipr(void) 161void __init plat_irq_setup(void)
167{ 162{
163 register_intc2_controller(&intc2_irq_desc);
168 register_ipr_controller(&ipr_irq_desc); 164 register_ipr_controller(&ipr_irq_desc);
169} 165}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 51b386d454de..a0fd8bb21f7c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -387,9 +387,24 @@ out_err:
387 return err; 387 return err;
388} 388}
389 389
390static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate)
391{
392 unsigned long parent_rate = clk->parent->rate;
393 int div;
394
395 /* look for multiplier/divisor pair */
396 div = sh7722_find_divisors(parent_rate, rate);
397 if (div < 0)
398 return clk->rate;
399
400 /* calculate new value of clock rate */
401 return parent_rate * 2 / div;
402}
403
390static struct clk_ops sh7722_frqcr_clk_ops = { 404static struct clk_ops sh7722_frqcr_clk_ops = {
391 .recalc = sh7722_frqcr_recalc, 405 .recalc = sh7722_frqcr_recalc,
392 .set_rate = sh7722_frqcr_set_rate, 406 .set_rate = sh7722_frqcr_set_rate,
407 .round_rate = sh7722_frqcr_round_rate,
393}; 408};
394 409
395/* 410/*
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index a3e159ef6dfe..25b913e07e2c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -19,8 +19,21 @@ static struct plat_sci_port sci_platform_data[] = {
19 .mapbase = 0xffe00000, 19 .mapbase = 0xffe00000,
20 .flags = UPF_BOOT_AUTOCONF, 20 .flags = UPF_BOOT_AUTOCONF,
21 .type = PORT_SCIF, 21 .type = PORT_SCIF,
22 .irqs = { 80, 81, 83, 82 }, 22 .irqs = { 80, 80, 80, 80 },
23 }, { 23 },
24 {
25 .mapbase = 0xffe10000,
26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF,
28 .irqs = { 81, 81, 81, 81 },
29 },
30 {
31 .mapbase = 0xffe20000,
32 .flags = UPF_BOOT_AUTOCONF,
33 .type = PORT_SCIF,
34 .irqs = { 82, 82, 82, 82 },
35 },
36 {
24 .flags = 0, 37 .flags = 0,
25 } 38 }
26}; 39};
@@ -44,46 +57,145 @@ static int __init sh7722_devices_setup(void)
44} 57}
45__initcall(sh7722_devices_setup); 58__initcall(sh7722_devices_setup);
46 59
47static struct ipr_data ipr_irq_table[] = { 60enum {
48 /* IRQ, IPR-idx, shift, prio */ 61 UNUSED=0,
49 { 16, 0, 12, 2 }, /* TMU0 */ 62
50 { 17, 0, 8, 2 }, /* TMU1 */ 63 /* interrupt sources */
51 { 80, 6, 12, 3 }, /* SCIF ERI */ 64 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
52 { 81, 6, 12, 3 }, /* SCIF RXI */ 65 HUDI,
53 { 82, 6, 12, 3 }, /* SCIF BRI */ 66 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
54 { 83, 6, 12, 3 }, /* SCIF TXI */ 67 RTC_ATI, RTC_PRI, RTC_CUI,
68 DMAC0, DMAC1, DMAC2, DMAC3,
69 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
70 VPU, TPU,
71 USB_USBI0, USB_USBI1,
72 DMAC4, DMAC5, DMAC_DADERR,
73 KEYSC,
74 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
75 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
76 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
77 SDHI0, SDHI1, SDHI2, SDHI3,
78 CMT, TSIF, SIU, TWODG,
79 TMU0, TMU1, TMU2,
80 IRDA, JPU, LCDC,
81
82 /* interrupt groups */
83
84 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
55}; 85};
56 86
57static unsigned long ipr_offsets[] = { 87static struct intc_vect vectors[] = {
58 0xa4080000, /* 0: IPRA */ 88 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
59 0xa4080004, /* 1: IPRB */ 89 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
60 0xa4080008, /* 2: IPRC */ 90 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
61 0xa408000c, /* 3: IPRD */ 91 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
62 0xa4080010, /* 4: IPRE */ 92 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
63 0xa4080014, /* 5: IPRF */ 93 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
64 0xa4080018, /* 6: IPRG */ 94 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
65 0xa408001c, /* 7: IPRH */ 95 INTC_VECT(RTC_CUI, 0x7c0),
66 0xa4080020, /* 8: IPRI */ 96 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
67 0xa4080024, /* 9: IPRJ */ 97 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
68 0xa4080028, /* 10: IPRK */ 98 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
69 0xa408002c, /* 11: IPRL */ 99 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
100 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
101 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
102 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
103 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
104 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
105 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
106 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
107 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
108 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
109 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
110 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
111 INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
112 INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
113 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
114 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
115 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
116 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
117 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
70}; 118};
71 119
72static struct ipr_desc ipr_irq_desc = { 120static struct intc_group groups[] = {
73 .ipr_offsets = ipr_offsets, 121 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
74 .nr_offsets = ARRAY_SIZE(ipr_offsets), 122 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
123 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
124 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
125 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
126 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
127 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
128 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
129 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
130 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
131};
75 132
76 .ipr_data = ipr_irq_table, 133static struct intc_prio priorities[] = {
77 .nr_irqs = ARRAY_SIZE(ipr_irq_table), 134 INTC_PRIO(SCIF0, 3),
135 INTC_PRIO(SCIF1, 3),
136 INTC_PRIO(SCIF2, 3),
137 INTC_PRIO(TMU0, 2),
138 INTC_PRIO(TMU1, 2),
139};
78 140
79 .chip = { 141static struct intc_mask_reg mask_registers[] = {
80 .name = "IPR-sh7722", 142 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
81 }, 143 { } },
144 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
145 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
146 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
147 { 0, 0, 0, VPU, } },
148 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
149 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
150 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
151 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
152 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
153 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
154 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
155 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
156 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
157 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
158 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
159 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
160 { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
161 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
162 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
163 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
164 { } },
165 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
166 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
167 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
168 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
82}; 169};
83 170
84void __init init_IRQ_ipr(void) 171static struct intc_prio_reg prio_registers[] = {
172 { 0xa4080000, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
173 { 0xa4080004, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
174 { 0xa4080008, 16, 4, /* IPRC */ { } },
175 { 0xa408000c, 16, 4, /* IPRD */ { } },
176 { 0xa4080010, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
177 { 0xa4080014, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
178 { 0xa4080018, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
179 { 0xa408001c, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
180 { 0xa4080020, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
181 { 0xa4080024, 16, 4, /* IPRJ */ { 0, 0, SIU } },
182 { 0xa4080028, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
183 { 0xa408002c, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
184 { 0xa4140010, 32, 4, /* INTPRI00 */
185 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
186};
187
188static struct intc_sense_reg sense_registers[] = {
189 { 0xa414001c, 16, 2, /* ICR1 */
190 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
191};
192
193static DECLARE_INTC_DESC(intc_desc, "sh7722", vectors, groups, priorities,
194 mask_registers, prio_registers, sense_registers);
195
196void __init plat_irq_setup(void)
85{ 197{
86 register_ipr_controller(&ipr_irq_desc); 198 register_intc_controller(&intc_desc);
87} 199}
88 200
89void __init plat_mem_setup(void) 201void __init plat_mem_setup(void)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index b57c760bffde..a4127ec15203 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -30,7 +30,7 @@ static struct resource rtc_resources[] = {
30 }, 30 },
31 [3] = { 31 [3] = {
32 /* Alarm IRQ */ 32 /* Alarm IRQ */
33 .start = 23, 33 .start = 20,
34 .flags = IORESOURCE_IRQ, 34 .flags = IORESOURCE_IRQ,
35 }, 35 },
36}; 36};
@@ -78,44 +78,205 @@ static int __init sh7780_devices_setup(void)
78} 78}
79__initcall(sh7780_devices_setup); 79__initcall(sh7780_devices_setup);
80 80
81static struct intc2_data intc2_irq_table[] = { 81enum {
82 { 28, 0, 24, 0, 0, 2 }, /* TMU0 */ 82 UNUSED = 0,
83 83
84 { 21, 1, 0, 0, 2, 2 }, 84 /* interrupt sources */
85 { 22, 1, 1, 0, 2, 2 },
86 { 23, 1, 2, 0, 2, 2 },
87 85
88 { 40, 8, 24, 0, 3, 3 }, /* SCIF0 ERI */ 86 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
89 { 41, 8, 24, 0, 3, 3 }, /* SCIF0 RXI */ 87 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
90 { 42, 8, 24, 0, 3, 3 }, /* SCIF0 BRI */ 88 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
91 { 43, 8, 24, 0, 3, 3 }, /* SCIF0 TXI */ 89 IRL_HHLL, IRL_HHLH, IRL_HHHL,
92 90
93 { 76, 8, 16, 0, 4, 3 }, /* SCIF1 ERI */ 91 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
94 { 77, 8, 16, 0, 4, 3 }, /* SCIF1 RXI */ 92 RTC_ATI, RTC_PRI, RTC_CUI,
95 { 78, 8, 16, 0, 4, 3 }, /* SCIF1 BRI */ 93 WDT,
96 { 79, 8, 16, 0, 4, 3 }, /* SCIF1 TXI */ 94 TMU0, TMU1, TMU2, TMU2_TICPI,
95 HUDI,
96 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
97 SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
98 DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
99 CMT, HAC,
100 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
101 PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
102 SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
103 SIOF, HSPI,
104 MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
105 DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
106 TMU3, TMU4, TMU5,
107 SSI,
108 FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
109 GPIOI0, GPIOI1, GPIOI2, GPIOI3,
97 110
98 { 64, 0x10, 8, 0, 14, 2 }, /* PCIC0 */ 111 /* interrupt groups */
99 { 65, 0x10, 0, 0, 15, 2 }, /* PCIC1 */ 112
100 { 66, 0x14, 24, 0, 16, 2 }, /* PCIC2 */ 113 RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1,
101 { 67, 0x14, 16, 0, 17, 2 }, /* PCIC3 */ 114 PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
102 { 68, 0x14, 8, 0, 18, 2 }, /* PCIC4 */
103}; 115};
104 116
105static struct intc2_desc intc2_irq_desc __read_mostly = { 117static struct intc_vect vectors[] = {
106 .prio_base = 0xffd40000, 118 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
107 .msk_base = 0xffd40038, 119 INTC_VECT(RTC_CUI, 0x4c0),
108 .mskclr_base = 0xffd4003c, 120 INTC_VECT(WDT, 0x560),
121 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
122 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
123 INTC_VECT(HUDI, 0x600),
124 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
125 INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
126 INTC_VECT(DMAC0_DMAE, 0x6c0),
127 INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
128 INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
129 INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
130 INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0),
131 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
132 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
133 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
134 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
135 INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
136 INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
137 INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
138 INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
139 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
140 INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
141 INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
142 INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0),
143 INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0),
144 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
145 INTC_VECT(TMU5, 0xe40),
146 INTC_VECT(SSI, 0xe80),
147 INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
148 INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
149 INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
150 INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
151};
109 152
110 .intc2_data = intc2_irq_table, 153static struct intc_group groups[] = {
111 .nr_irqs = ARRAY_SIZE(intc2_irq_table), 154 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
155 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
156 INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
157 DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
158 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
159 INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
160 DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
161 INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
162 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
163 INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
164 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
165 INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
166 FLCTL_FLTRQ0, FLCTL_FLTRQ1),
167 INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
168};
112 169
113 .chip = { 170static struct intc_prio priorities[] = {
114 .name = "INTC2-sh7780", 171 INTC_PRIO(SCIF0, 3),
115 }, 172 INTC_PRIO(SCIF1, 3),
173};
174
175static struct intc_mask_reg mask_registers[] = {
176 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
177 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
178 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
179 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
180 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
181};
182
183static struct intc_prio_reg prio_registers[] = {
184 { 0xffd40000, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, TMU2, TMU2_TICPI } },
185 { 0xffd40004, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
186 { 0xffd40008, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
187 { 0xffd4000c, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
188 { 0xffd40010, 32, 8, /* INT2PRI4 */ { CMT, HAC, PCISERR, PCIINTA, } },
189 { 0xffd40014, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
190 PCIINTD, PCIC5 } },
191 { 0xffd40018, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
192 { 0xffd4001c, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
193};
194
195static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities,
196 mask_registers, prio_registers, NULL);
197
198/* Support for external interrupt pins in IRQ mode */
199
200static struct intc_vect irq_vectors[] = {
201 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
202 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
203 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
204 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
205};
206
207static struct intc_mask_reg irq_mask_registers[] = {
208 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
209 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
210};
211
212static struct intc_prio_reg irq_prio_registers[] = {
213 { 0xffd00010, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
214 IRQ4, IRQ5, IRQ6, IRQ7 } },
116}; 215};
117 216
118void __init init_IRQ_intc2(void) 217static struct intc_sense_reg irq_sense_registers[] = {
218 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
219 IRQ4, IRQ5, IRQ6, IRQ7 } },
220};
221
222static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
223 NULL, NULL, irq_mask_registers, irq_prio_registers,
224 irq_sense_registers);
225
226/* External interrupt pins in IRL mode */
227
228static struct intc_vect irl_vectors[] = {
229 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
230 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
231 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
232 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
233 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
234 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
235 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
236 INTC_VECT(IRL_HHHL, 0x3c0),
237};
238
239static struct intc_mask_reg irl3210_mask_registers[] = {
240 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
241 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
242 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
243 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
244 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
245};
246
247static struct intc_mask_reg irl7654_mask_registers[] = {
248 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
249 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
251 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
252 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
253 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
254};
255
256static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
257 NULL, NULL, irl7654_mask_registers, NULL, NULL);
258
259static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
260 NULL, NULL, irl3210_mask_registers, NULL, NULL);
261
262void __init plat_irq_setup(void)
119{ 263{
120 register_intc2_controller(&intc2_irq_desc); 264 register_intc_controller(&intc_desc);
265}
266
267void __init plat_irq_setup_pins(int mode)
268{
269 switch (mode) {
270 case IRQ_MODE_IRQ:
271 register_intc_controller(&intc_irq_desc);
272 break;
273 case IRQ_MODE_IRL7654:
274 register_intc_controller(&intc_irl7654_desc);
275 break;
276 case IRQ_MODE_IRL3210:
277 register_intc_controller(&intc_irl3210_desc);
278 break;
279 default:
280 BUG();
281 }
121} 282}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index ce10ec5d6914..cf047562e43f 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -110,7 +110,7 @@ static struct intc2_desc intc2_irq_desc __read_mostly = {
110 }, 110 },
111}; 111};
112 112
113void __init init_IRQ_intc2(void) 113void __init plat_irq_setup(void)
114{ 114{
115 register_intc2_controller(&intc2_irq_desc); 115 register_intc2_controller(&intc2_irq_desc);
116} 116}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 70683ea12b83..704c064f70dc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -79,7 +79,7 @@ static struct intc2_desc intc2_irq_desc __read_mostly = {
79 }, 79 },
80}; 80};
81 81
82void __init init_IRQ_intc2(void) 82void __init plat_irq_setup(void)
83{ 83{
84 register_intc2_controller(&intc2_irq_desc); 84 register_intc2_controller(&intc2_irq_desc);
85} 85}
diff --git a/arch/sh/kernel/cpufreq.c b/arch/sh/kernel/cpufreq.c
index 47abf6e49dfb..e61890217c50 100644
--- a/arch/sh/kernel/cpufreq.c
+++ b/arch/sh/kernel/cpufreq.c
@@ -3,89 +3,46 @@
3 * 3 *
4 * cpufreq driver for the SuperH processors. 4 * cpufreq driver for the SuperH processors.
5 * 5 *
6 * Copyright (C) 2002, 2003, 2004, 2005 Paul Mundt 6 * Copyright (C) 2002 - 2007 Paul Mundt
7 * Copyright (C) 2002 M. R. Brown 7 * Copyright (C) 2002 M. R. Brown
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * Clock framework bits from arch/avr32/mach-at32ap/cpufreq.c
10 * under the terms of the GNU General Public License as published by the 10 *
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Copyright (C) 2004-2007 Atmel Corporation
12 * option) any later version. 12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
13 */ 16 */
14#include <linux/types.h> 17#include <linux/types.h>
15#include <linux/cpufreq.h> 18#include <linux/cpufreq.h>
16#include <linux/kernel.h> 19#include <linux/kernel.h>
17#include <linux/module.h> 20#include <linux/module.h>
18#include <linux/slab.h>
19#include <linux/init.h> 21#include <linux/init.h>
20#include <linux/delay.h> 22#include <linux/err.h>
21#include <linux/cpumask.h> 23#include <linux/cpumask.h>
22#include <linux/smp.h> 24#include <linux/smp.h>
23#include <linux/sched.h> /* set_cpus_allowed() */ 25#include <linux/sched.h> /* set_cpus_allowed() */
26#include <linux/clk.h>
24 27
25#include <asm/processor.h> 28static struct clk *cpuclk;
26#include <asm/watchdog.h>
27#include <asm/freq.h>
28#include <asm/io.h>
29
30/*
31 * For SuperH, each policy change requires that we change the IFC, BFC, and
32 * PFC at the same time. Here we define sane values that won't trash the
33 * system.
34 *
35 * Note the max set is computed at runtime, we use the divisors that we booted
36 * with to setup our maximum operating frequencies.
37 */
38struct clock_set {
39 unsigned int ifc;
40 unsigned int bfc;
41 unsigned int pfc;
42} clock_sets[] = {
43#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH2)
44 { 0, 0, 0 }, /* not implemented yet */
45#elif defined(CONFIG_CPU_SH4)
46 { 4, 8, 8 }, /* min - IFC: 1/4, BFC: 1/8, PFC: 1/8 */
47 { 1, 2, 2 }, /* max - IFC: 1, BFC: 1/2, PFC: 1/2 */
48#endif
49};
50
51#define MIN_CLOCK_SET 0
52#define MAX_CLOCK_SET (ARRAY_SIZE(clock_sets) - 1)
53
54/*
55 * For the time being, we only support two frequencies, which in turn are
56 * aimed at the POWERSAVE and PERFORMANCE policies, which in turn are derived
57 * directly from the respective min/max clock sets. Technically we could
58 * support a wider range of frequencies, but these vary far too much for each
59 * CPU subtype (and we'd have to construct a frequency table for each subtype).
60 *
61 * Maybe something to implement in the future..
62 */
63#define SH_FREQ_MAX 0
64#define SH_FREQ_MIN 1
65
66static struct cpufreq_frequency_table sh_freqs[] = {
67 { SH_FREQ_MAX, 0 },
68 { SH_FREQ_MIN, 0 },
69 { 0, CPUFREQ_TABLE_END },
70};
71 29
72static void sh_cpufreq_update_clocks(unsigned int set) 30static unsigned int sh_cpufreq_get(unsigned int cpu)
73{ 31{
74 current_cpu_data.cpu_clock = current_cpu_data.master_clock / clock_sets[set].ifc; 32 return (clk_get_rate(cpuclk) + 500) / 1000;
75 current_cpu_data.bus_clock = current_cpu_data.master_clock / clock_sets[set].bfc;
76 current_cpu_data.module_clock = current_cpu_data.master_clock / clock_sets[set].pfc;
77 current_cpu_data.loops_per_jiffy = loops_per_jiffy;
78} 33}
79 34
80/* XXX: This needs to be split out per CPU and CPU subtype. */
81/* 35/*
82 * Here we notify other drivers of the proposed change and the final change. 36 * Here we notify other drivers of the proposed change and the final change.
83 */ 37 */
84static int sh_cpufreq_setstate(unsigned int cpu, unsigned int set) 38static int sh_cpufreq_target(struct cpufreq_policy *policy,
39 unsigned int target_freq,
40 unsigned int relation)
85{ 41{
86 unsigned short frqcr = ctrl_inw(FRQCR); 42 unsigned int cpu = policy->cpu;
87 cpumask_t cpus_allowed; 43 cpumask_t cpus_allowed;
88 struct cpufreq_freqs freqs; 44 struct cpufreq_freqs freqs;
45 long freq;
89 46
90 if (!cpu_online(cpu)) 47 if (!cpu_online(cpu))
91 return -ENODEV; 48 return -ENODEV;
@@ -95,125 +52,109 @@ static int sh_cpufreq_setstate(unsigned int cpu, unsigned int set)
95 52
96 BUG_ON(smp_processor_id() != cpu); 53 BUG_ON(smp_processor_id() != cpu);
97 54
98 freqs.cpu = cpu; 55 /* Convert target_freq from kHz to Hz */
99 freqs.old = current_cpu_data.cpu_clock / 1000; 56 freq = clk_round_rate(cpuclk, target_freq * 1000);
100 freqs.new = (current_cpu_data.master_clock / clock_sets[set].ifc) / 1000;
101 57
102 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 58 if (freq < (policy->min * 1000) || freq > (policy->max * 1000))
103#if defined(CONFIG_CPU_SH3) 59 return -EINVAL;
104 frqcr |= (newstate & 0x4000) << 14; 60
105 frqcr |= (newstate & 0x000c) << 2; 61 pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
106#elif defined(CONFIG_CPU_SH4)
107 /*
108 * FRQCR.PLL2EN is 1, we need to allow the PLL to stabilize by
109 * initializing the WDT.
110 */
111 if (frqcr & (1 << 9)) {
112 __u8 csr;
113
114 /*
115 * Set the overflow period to the highest available,
116 * in this case a 1/4096 division ratio yields a 5.25ms
117 * overflow period. See asm-sh/watchdog.h for more
118 * information and a range of other divisors.
119 */
120 csr = sh_wdt_read_csr();
121 csr |= WTCSR_CKS_4096;
122 sh_wdt_write_csr(csr);
123
124 sh_wdt_write_cnt(0);
125 }
126 frqcr &= 0x0e00; /* Clear ifc, bfc, pfc */
127 frqcr |= get_ifc_value(clock_sets[set].ifc) << 6;
128 frqcr |= get_bfc_value(clock_sets[set].bfc) << 3;
129 frqcr |= get_pfc_value(clock_sets[set].pfc);
130#endif
131 ctrl_outw(frqcr, FRQCR);
132 sh_cpufreq_update_clocks(set);
133 62
63 freqs.cpu = cpu;
64 freqs.old = sh_cpufreq_get(cpu);
65 freqs.new = (freq + 500) / 1000;
66 freqs.flags = 0;
67
68 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
134 set_cpus_allowed(current, cpus_allowed); 69 set_cpus_allowed(current, cpus_allowed);
70 clk_set_rate(cpuclk, freq);
135 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 71 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
136 72
73 pr_debug("cpufreq: set frequency %lu Hz\n", freq);
74
137 return 0; 75 return 0;
138} 76}
139 77
140static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy) 78static int sh_cpufreq_cpu_init(struct cpufreq_policy *policy)
141{ 79{
142 unsigned int min_freq, max_freq; 80 printk(KERN_INFO "cpufreq: SuperH CPU frequency driver.\n");
143 unsigned int ifc, bfc, pfc;
144 81
145 if (!cpu_online(policy->cpu)) 82 if (!cpu_online(policy->cpu))
146 return -ENODEV; 83 return -ENODEV;
147 84
148 /* Update our maximum clock set */ 85 cpuclk = clk_get(NULL, "cpu_clk");
149 get_current_frequency_divisors(&ifc, &bfc, &pfc); 86 if (IS_ERR(cpuclk)) {
150 clock_sets[MAX_CLOCK_SET].ifc = ifc; 87 printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
151 clock_sets[MAX_CLOCK_SET].bfc = bfc; 88 return PTR_ERR(cpuclk);
152 clock_sets[MAX_CLOCK_SET].pfc = pfc; 89 }
153
154 /* Convert from Hz to kHz */
155 max_freq = current_cpu_data.cpu_clock / 1000;
156 min_freq = (current_cpu_data.master_clock / clock_sets[MIN_CLOCK_SET].ifc) / 1000;
157
158 sh_freqs[SH_FREQ_MAX].frequency = max_freq;
159 sh_freqs[SH_FREQ_MIN].frequency = min_freq;
160 90
161 /* cpuinfo and default policy values */ 91 /* cpuinfo and default policy values */
162 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 92 policy->cpuinfo.min_freq = (clk_round_rate(cpuclk, 1) + 500) / 1000;
93 policy->cpuinfo.max_freq = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000;
163 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; 94 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
164 policy->cur = max_freq;
165 95
166 return cpufreq_frequency_table_cpuinfo(policy, &sh_freqs[0]); 96 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
167} 97 policy->cur = sh_cpufreq_get(policy->cpu);
98 policy->min = policy->cpuinfo.min_freq;
99 policy->max = policy->cpuinfo.max_freq;
168 100
169static int sh_cpufreq_verify(struct cpufreq_policy *policy)
170{
171 return cpufreq_frequency_table_verify(policy, &sh_freqs[0]);
172}
173 101
174static int sh_cpufreq_target(struct cpufreq_policy *policy, 102 /*
175 unsigned int target_freq, 103 * Catch the cases where the clock framework hasn't been wired up
176 unsigned int relation) 104 * properly to support scaling.
177{ 105 */
178 unsigned int set, idx = 0; 106 if (unlikely(policy->min == policy->max)) {
107 printk(KERN_ERR "cpufreq: clock framework rate rounding "
108 "not supported on this CPU.\n");
179 109
180 if (cpufreq_frequency_table_target(policy, &sh_freqs[0], target_freq, relation, &idx)) 110 clk_put(cpuclk);
181 return -EINVAL; 111 return -EINVAL;
112 }
182 113
183 set = (idx == SH_FREQ_MIN) ? MIN_CLOCK_SET : MAX_CLOCK_SET; 114 printk(KERN_INFO "cpufreq: Frequencies - Minimum %u.%03u MHz, "
115 "Maximum %u.%03u MHz.\n",
116 policy->min / 1000, policy->min % 1000,
117 policy->max / 1000, policy->max % 1000);
184 118
185 sh_cpufreq_setstate(policy->cpu, set); 119 return 0;
120}
186 121
122static int sh_cpufreq_verify(struct cpufreq_policy *policy)
123{
124 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
125 policy->cpuinfo.max_freq);
126 return 0;
127}
128
129static int sh_cpufreq_exit(struct cpufreq_policy *policy)
130{
131 clk_put(cpuclk);
187 return 0; 132 return 0;
188} 133}
189 134
190static struct cpufreq_driver sh_cpufreq_driver = { 135static struct cpufreq_driver sh_cpufreq_driver = {
191 .owner = THIS_MODULE, 136 .owner = THIS_MODULE,
192 .name = "SH cpufreq", 137 .name = "sh",
193 .init = sh_cpufreq_cpu_init, 138 .init = sh_cpufreq_cpu_init,
194 .verify = sh_cpufreq_verify, 139 .verify = sh_cpufreq_verify,
195 .target = sh_cpufreq_target, 140 .target = sh_cpufreq_target,
141 .get = sh_cpufreq_get,
142 .exit = sh_cpufreq_exit,
196}; 143};
197 144
198static int __init sh_cpufreq_init(void) 145static int __init sh_cpufreq_module_init(void)
199{ 146{
200 if (!current_cpu_data.cpu_clock) 147 return cpufreq_register_driver(&sh_cpufreq_driver);
201 return -EINVAL;
202 if (cpufreq_register_driver(&sh_cpufreq_driver))
203 return -EINVAL;
204
205 return 0;
206} 148}
207 149
208static void __exit sh_cpufreq_exit(void) 150static void __exit sh_cpufreq_module_exit(void)
209{ 151{
210 cpufreq_unregister_driver(&sh_cpufreq_driver); 152 cpufreq_unregister_driver(&sh_cpufreq_driver);
211} 153}
212 154
213module_init(sh_cpufreq_init); 155module_init(sh_cpufreq_module_init);
214module_exit(sh_cpufreq_exit); 156module_exit(sh_cpufreq_module_exit);
215 157
216MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>"); 158MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
217MODULE_DESCRIPTION("cpufreq driver for SuperH"); 159MODULE_DESCRIPTION("cpufreq driver for SuperH");
218MODULE_LICENSE("GPL"); 160MODULE_LICENSE("GPL");
219
diff --git a/arch/sh/kernel/head.S b/arch/sh/kernel/head.S
index 71a3ad7d283e..0bccc0ca5a0f 100644
--- a/arch/sh/kernel/head.S
+++ b/arch/sh/kernel/head.S
@@ -36,7 +36,8 @@ ENTRY(empty_zero_page)
361: 361:
37 .skip PAGE_SIZE - empty_zero_page - 1b 37 .skip PAGE_SIZE - empty_zero_page - 1b
38 38
39 .text 39 .section .text.head, "ax"
40
40/* 41/*
41 * Condition at the entry of _stext: 42 * Condition at the entry of _stext:
42 * 43 *
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 27897798867a..03404987528d 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -253,14 +253,7 @@ void __init init_IRQ(void)
253#ifdef CONFIG_CPU_HAS_PINT_IRQ 253#ifdef CONFIG_CPU_HAS_PINT_IRQ
254 init_IRQ_pint(); 254 init_IRQ_pint();
255#endif 255#endif
256 256 plat_irq_setup();
257#ifdef CONFIG_CPU_HAS_INTC2_IRQ
258 init_IRQ_intc2();
259#endif
260
261#ifdef CONFIG_CPU_HAS_IPR_IRQ
262 init_IRQ_ipr();
263#endif
264 257
265 /* Perform the machine specific initialisation */ 258 /* Perform the machine specific initialisation */
266 if (sh_mv.mv_init_irq) 259 if (sh_mv.mv_init_irq)
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index de8e6e2f2c87..c14a3e95d0b1 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -21,6 +21,7 @@
21#include <linux/fs.h> 21#include <linux/fs.h>
22#include <linux/mm.h> 22#include <linux/mm.h>
23#include <linux/kexec.h> 23#include <linux/kexec.h>
24#include <linux/module.h>
24#include <asm/uaccess.h> 25#include <asm/uaccess.h>
25#include <asm/io.h> 26#include <asm/io.h>
26#include <asm/page.h> 27#include <asm/page.h>
@@ -78,7 +79,11 @@ static char __initdata command_line[COMMAND_LINE_SIZE] = { 0, };
78static struct resource code_resource = { .name = "Kernel code", }; 79static struct resource code_resource = { .name = "Kernel code", };
79static struct resource data_resource = { .name = "Kernel data", }; 80static struct resource data_resource = { .name = "Kernel data", };
80 81
81unsigned long memory_start, memory_end; 82unsigned long memory_start;
83EXPORT_SYMBOL(memory_start);
84
85unsigned long memory_end;
86EXPORT_SYMBOL(memory_end);
82 87
83static int __init early_parse_mem(char *p) 88static int __init early_parse_mem(char *p)
84{ 89{
diff --git a/arch/sh/kernel/sh_bios.c b/arch/sh/kernel/sh_bios.c
index 5b53e10bb9cd..d1bcac4fa269 100644
--- a/arch/sh/kernel/sh_bios.c
+++ b/arch/sh/kernel/sh_bios.c
@@ -5,7 +5,7 @@
5 * Copyright (C) 2000 Greg Banks, Mitch Davis 5 * Copyright (C) 2000 Greg Banks, Mitch Davis
6 * 6 *
7 */ 7 */
8 8#include <linux/module.h>
9#include <asm/sh_bios.h> 9#include <asm/sh_bios.h>
10 10
11#define BIOS_CALL_CONSOLE_WRITE 0 11#define BIOS_CALL_CONSOLE_WRITE 0
@@ -63,6 +63,7 @@ void sh_bios_gdb_detach(void)
63{ 63{
64 sh_bios_call(BIOS_CALL_GDB_DETACH, 0, 0, 0, 0); 64 sh_bios_call(BIOS_CALL_GDB_DETACH, 0, 0, 0, 0);
65} 65}
66EXPORT_SYMBOL(sh_bios_gdb_detach);
66 67
67void sh_bios_get_node_addr (unsigned char *node_addr) 68void sh_bios_get_node_addr (unsigned char *node_addr)
68{ 69{
diff --git a/arch/sh/kernel/sh_ksyms.c b/arch/sh/kernel/sh_ksyms.c
index c968dcf09eee..37aef0a85197 100644
--- a/arch/sh/kernel/sh_ksyms.c
+++ b/arch/sh/kernel/sh_ksyms.c
@@ -63,10 +63,43 @@ EXPORT_SYMBOL(__const_udelay);
63/* These symbols are generated by the compiler itself */ 63/* These symbols are generated by the compiler itself */
64DECLARE_EXPORT(__udivsi3); 64DECLARE_EXPORT(__udivsi3);
65DECLARE_EXPORT(__sdivsi3); 65DECLARE_EXPORT(__sdivsi3);
66DECLARE_EXPORT(__ashrsi3);
67DECLARE_EXPORT(__ashlsi3);
66DECLARE_EXPORT(__ashrdi3); 68DECLARE_EXPORT(__ashrdi3);
67DECLARE_EXPORT(__ashldi3); 69DECLARE_EXPORT(__ashldi3);
70DECLARE_EXPORT(__ashiftrt_r4_6);
71DECLARE_EXPORT(__ashiftrt_r4_7);
72DECLARE_EXPORT(__ashiftrt_r4_8);
73DECLARE_EXPORT(__ashiftrt_r4_9);
74DECLARE_EXPORT(__ashiftrt_r4_10);
75DECLARE_EXPORT(__ashiftrt_r4_11);
76DECLARE_EXPORT(__ashiftrt_r4_12);
77DECLARE_EXPORT(__ashiftrt_r4_13);
78DECLARE_EXPORT(__ashiftrt_r4_14);
79DECLARE_EXPORT(__ashiftrt_r4_15);
80DECLARE_EXPORT(__ashiftrt_r4_20);
81DECLARE_EXPORT(__ashiftrt_r4_21);
82DECLARE_EXPORT(__ashiftrt_r4_22);
83DECLARE_EXPORT(__ashiftrt_r4_23);
84DECLARE_EXPORT(__ashiftrt_r4_24);
85DECLARE_EXPORT(__ashiftrt_r4_27);
86DECLARE_EXPORT(__ashiftrt_r4_30);
87DECLARE_EXPORT(__lshrsi3);
68DECLARE_EXPORT(__lshrdi3); 88DECLARE_EXPORT(__lshrdi3);
89DECLARE_EXPORT(__movstrSI8);
90DECLARE_EXPORT(__movstrSI12);
69DECLARE_EXPORT(__movstrSI16); 91DECLARE_EXPORT(__movstrSI16);
92DECLARE_EXPORT(__movstrSI20);
93DECLARE_EXPORT(__movstrSI24);
94DECLARE_EXPORT(__movstrSI28);
95DECLARE_EXPORT(__movstrSI32);
96DECLARE_EXPORT(__movstrSI36);
97DECLARE_EXPORT(__movstrSI40);
98DECLARE_EXPORT(__movstrSI44);
99DECLARE_EXPORT(__movstrSI48);
100DECLARE_EXPORT(__movstrSI52);
101DECLARE_EXPORT(__movstrSI56);
102DECLARE_EXPORT(__movstrSI60);
70#if __GNUC__ == 4 103#if __GNUC__ == 4
71DECLARE_EXPORT(__movmem); 104DECLARE_EXPORT(__movmem);
72#else 105#else
@@ -115,7 +148,9 @@ EXPORT_SYMBOL(synchronize_irq);
115#endif 148#endif
116 149
117EXPORT_SYMBOL(csum_partial); 150EXPORT_SYMBOL(csum_partial);
151EXPORT_SYMBOL(csum_partial_copy_generic);
118#ifdef CONFIG_IPV6 152#ifdef CONFIG_IPV6
119EXPORT_SYMBOL(csum_ipv6_magic); 153EXPORT_SYMBOL(csum_ipv6_magic);
120#endif 154#endif
121EXPORT_SYMBOL(clear_page); 155EXPORT_SYMBOL(clear_page);
156EXPORT_SYMBOL(__clear_user);
diff --git a/arch/sh/kernel/syscalls.S b/arch/sh/kernel/syscalls.S
index ff5656e60c05..91fb7024e06f 100644
--- a/arch/sh/kernel/syscalls.S
+++ b/arch/sh/kernel/syscalls.S
@@ -358,3 +358,4 @@ ENTRY(sys_call_table)
358 .long sys_signalfd 358 .long sys_signalfd
359 .long sys_timerfd 359 .long sys_timerfd
360 .long sys_eventfd 360 .long sys_eventfd
361 .long sys_fallocate
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index 5ba216180b30..9cb95af7b090 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -22,6 +22,7 @@ SECTIONS
22 *(.empty_zero_page) 22 *(.empty_zero_page)
23 } = 0 23 } = 0
24 .text : { 24 .text : {
25 *(.text.head)
25 TEXT_TEXT 26 TEXT_TEXT
26 SCHED_TEXT 27 SCHED_TEXT
27 LOCK_TEXT 28 LOCK_TEXT
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 28d79a474cde..70da1c8d407e 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -120,14 +120,14 @@ config CPU_SUBTYPE_SH7712
120config CPU_SUBTYPE_SH7750 120config CPU_SUBTYPE_SH7750
121 bool "Support SH7750 processor" 121 bool "Support SH7750 processor"
122 select CPU_SH4 122 select CPU_SH4
123 select CPU_HAS_IPR_IRQ 123 select CPU_HAS_INTC_IRQ
124 help 124 help
125 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. 125 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
126 126
127config CPU_SUBTYPE_SH7091 127config CPU_SUBTYPE_SH7091
128 bool "Support SH7091 processor" 128 bool "Support SH7091 processor"
129 select CPU_SH4 129 select CPU_SH4
130 select CPU_HAS_IPR_IRQ 130 select CPU_HAS_INTC_IRQ
131 help 131 help
132 Select SH7091 if you have an SH-4 based Sega device (such as 132 Select SH7091 if you have an SH-4 based Sega device (such as
133 the Dreamcast, Naomi, and Naomi 2). 133 the Dreamcast, Naomi, and Naomi 2).
@@ -135,17 +135,17 @@ config CPU_SUBTYPE_SH7091
135config CPU_SUBTYPE_SH7750R 135config CPU_SUBTYPE_SH7750R
136 bool "Support SH7750R processor" 136 bool "Support SH7750R processor"
137 select CPU_SH4 137 select CPU_SH4
138 select CPU_HAS_IPR_IRQ 138 select CPU_HAS_INTC_IRQ
139 139
140config CPU_SUBTYPE_SH7750S 140config CPU_SUBTYPE_SH7750S
141 bool "Support SH7750S processor" 141 bool "Support SH7750S processor"
142 select CPU_SH4 142 select CPU_SH4
143 select CPU_HAS_IPR_IRQ 143 select CPU_HAS_INTC_IRQ
144 144
145config CPU_SUBTYPE_SH7751 145config CPU_SUBTYPE_SH7751
146 bool "Support SH7751 processor" 146 bool "Support SH7751 processor"
147 select CPU_SH4 147 select CPU_SH4
148 select CPU_HAS_IPR_IRQ 148 select CPU_HAS_INTC_IRQ
149 help 149 help
150 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, 150 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
151 or if you have a HD6417751R CPU. 151 or if you have a HD6417751R CPU.
@@ -153,7 +153,7 @@ config CPU_SUBTYPE_SH7751
153config CPU_SUBTYPE_SH7751R 153config CPU_SUBTYPE_SH7751R
154 bool "Support SH7751R processor" 154 bool "Support SH7751R processor"
155 select CPU_SH4 155 select CPU_SH4
156 select CPU_HAS_IPR_IRQ 156 select CPU_HAS_INTC_IRQ
157 157
158config CPU_SUBTYPE_SH7760 158config CPU_SUBTYPE_SH7760
159 bool "Support SH7760 processor" 159 bool "Support SH7760 processor"
@@ -189,7 +189,7 @@ config CPU_SUBTYPE_SH7770
189config CPU_SUBTYPE_SH7780 189config CPU_SUBTYPE_SH7780
190 bool "Support SH7780 processor" 190 bool "Support SH7780 processor"
191 select CPU_SH4A 191 select CPU_SH4A
192 select CPU_HAS_INTC2_IRQ 192 select CPU_HAS_INTC_IRQ
193 193
194config CPU_SUBTYPE_SH7785 194config CPU_SUBTYPE_SH7785
195 bool "Support SH7785 processor" 195 bool "Support SH7785 processor"
@@ -217,7 +217,7 @@ config CPU_SUBTYPE_SH7722
217 bool "Support SH7722 processor" 217 bool "Support SH7722 processor"
218 select CPU_SH4AL_DSP 218 select CPU_SH4AL_DSP
219 select CPU_SHX2 219 select CPU_SHX2
220 select CPU_HAS_IPR_IRQ 220 select CPU_HAS_INTC_IRQ
221 select ARCH_SPARSEMEM_ENABLE 221 select ARCH_SPARSEMEM_ENABLE
222 select SYS_SUPPORTS_NUMA 222 select SYS_SUPPORTS_NUMA
223 223
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 05:50:09 -0500