diff options
Diffstat (limited to 'arch')
537 files changed, 4028 insertions, 3995 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index cc31bec2e316..9808998cc073 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig | |||
@@ -11,7 +11,7 @@ config ALPHA | |||
11 | select HAVE_GENERIC_HARDIRQS | 11 | select HAVE_GENERIC_HARDIRQS |
12 | select GENERIC_IRQ_PROBE | 12 | select GENERIC_IRQ_PROBE |
13 | select AUTO_IRQ_AFFINITY if SMP | 13 | select AUTO_IRQ_AFFINITY if SMP |
14 | select GENERIC_HARDIRQS_NO_DEPRECATED | 14 | select GENERIC_IRQ_SHOW |
15 | help | 15 | help |
16 | The Alpha is a 64-bit general-purpose processor designed and | 16 | The Alpha is a 64-bit general-purpose processor designed and |
17 | marketed by the Digital Equipment Corporation of blessed memory, | 17 | marketed by the Digital Equipment Corporation of blessed memory, |
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c index a19d60082299..381431a2d6d9 100644 --- a/arch/alpha/kernel/irq.c +++ b/arch/alpha/kernel/irq.c | |||
@@ -67,68 +67,21 @@ int irq_select_affinity(unsigned int irq) | |||
67 | } | 67 | } |
68 | #endif /* CONFIG_SMP */ | 68 | #endif /* CONFIG_SMP */ |
69 | 69 | ||
70 | int | 70 | int arch_show_interrupts(struct seq_file *p, int prec) |
71 | show_interrupts(struct seq_file *p, void *v) | ||
72 | { | 71 | { |
73 | int j; | 72 | int j; |
74 | int irq = *(loff_t *) v; | ||
75 | struct irqaction * action; | ||
76 | struct irq_desc *desc; | ||
77 | unsigned long flags; | ||
78 | 73 | ||
79 | #ifdef CONFIG_SMP | 74 | #ifdef CONFIG_SMP |
80 | if (irq == 0) { | 75 | seq_puts(p, "IPI: "); |
81 | seq_puts(p, " "); | 76 | for_each_online_cpu(j) |
82 | for_each_online_cpu(j) | 77 | seq_printf(p, "%10lu ", cpu_data[j].ipi_count); |
83 | seq_printf(p, "CPU%d ", j); | 78 | seq_putc(p, '\n'); |
84 | seq_putc(p, '\n'); | ||
85 | } | ||
86 | #endif | ||
87 | |||
88 | if (irq < ACTUAL_NR_IRQS) { | ||
89 | desc = irq_to_desc(irq); | ||
90 | |||
91 | if (!desc) | ||
92 | return 0; | ||
93 | |||
94 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
95 | action = desc->action; | ||
96 | if (!action) | ||
97 | goto unlock; | ||
98 | seq_printf(p, "%3d: ", irq); | ||
99 | #ifndef CONFIG_SMP | ||
100 | seq_printf(p, "%10u ", kstat_irqs(irq)); | ||
101 | #else | ||
102 | for_each_online_cpu(j) | ||
103 | seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j)); | ||
104 | #endif | 79 | #endif |
105 | seq_printf(p, " %14s", get_irq_desc_chip(desc)->name); | 80 | seq_puts(p, "PMI: "); |
106 | seq_printf(p, " %c%s", | 81 | for_each_online_cpu(j) |
107 | (action->flags & IRQF_DISABLED)?'+':' ', | 82 | seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j)); |
108 | action->name); | 83 | seq_puts(p, " Performance Monitoring\n"); |
109 | 84 | seq_printf(p, "ERR: %10lu\n", irq_err_count); | |
110 | for (action=action->next; action; action = action->next) { | ||
111 | seq_printf(p, ", %c%s", | ||
112 | (action->flags & IRQF_DISABLED)?'+':' ', | ||
113 | action->name); | ||
114 | } | ||
115 | |||
116 | seq_putc(p, '\n'); | ||
117 | unlock: | ||
118 | raw_spin_unlock_irqrestore(&desc->lock, flags); | ||
119 | } else if (irq == ACTUAL_NR_IRQS) { | ||
120 | #ifdef CONFIG_SMP | ||
121 | seq_puts(p, "IPI: "); | ||
122 | for_each_online_cpu(j) | ||
123 | seq_printf(p, "%10lu ", cpu_data[j].ipi_count); | ||
124 | seq_putc(p, '\n'); | ||
125 | #endif | ||
126 | seq_puts(p, "PMI: "); | ||
127 | for_each_online_cpu(j) | ||
128 | seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j)); | ||
129 | seq_puts(p, " Performance Monitoring\n"); | ||
130 | seq_printf(p, "ERR: %10lu\n", irq_err_count); | ||
131 | } | ||
132 | return 0; | 85 | return 0; |
133 | } | 86 | } |
134 | 87 | ||
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c index 411ca11d0a18..1479dc6ebd97 100644 --- a/arch/alpha/kernel/irq_alpha.c +++ b/arch/alpha/kernel/irq_alpha.c | |||
@@ -228,7 +228,7 @@ struct irqaction timer_irqaction = { | |||
228 | void __init | 228 | void __init |
229 | init_rtc_irq(void) | 229 | init_rtc_irq(void) |
230 | { | 230 | { |
231 | set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip, | 231 | irq_set_chip_and_handler_name(RTC_IRQ, &no_irq_chip, |
232 | handle_simple_irq, "RTC"); | 232 | handle_simple_irq, "RTC"); |
233 | setup_irq(RTC_IRQ, &timer_irqaction); | 233 | setup_irq(RTC_IRQ, &timer_irqaction); |
234 | } | 234 | } |
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c index c7cc9813e45f..e1861c77dabc 100644 --- a/arch/alpha/kernel/irq_i8259.c +++ b/arch/alpha/kernel/irq_i8259.c | |||
@@ -92,7 +92,7 @@ init_i8259a_irqs(void) | |||
92 | outb(0xff, 0xA1); /* mask all of 8259A-2 */ | 92 | outb(0xff, 0xA1); /* mask all of 8259A-2 */ |
93 | 93 | ||
94 | for (i = 0; i < 16; i++) { | 94 | for (i = 0; i < 16; i++) { |
95 | set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); | 95 | irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq); |
96 | } | 96 | } |
97 | 97 | ||
98 | setup_irq(2, &cascade); | 98 | setup_irq(2, &cascade); |
diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c index b30227fa7f5f..13c97a5b31e8 100644 --- a/arch/alpha/kernel/irq_pyxis.c +++ b/arch/alpha/kernel/irq_pyxis.c | |||
@@ -102,7 +102,7 @@ init_pyxis_irqs(unsigned long ignore_mask) | |||
102 | for (i = 16; i < 48; ++i) { | 102 | for (i = 16; i < 48; ++i) { |
103 | if ((ignore_mask >> i) & 1) | 103 | if ((ignore_mask >> i) & 1) |
104 | continue; | 104 | continue; |
105 | set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); | 105 | irq_set_chip_and_handler(i, &pyxis_irq_type, handle_level_irq); |
106 | irq_set_status_flags(i, IRQ_LEVEL); | 106 | irq_set_status_flags(i, IRQ_LEVEL); |
107 | } | 107 | } |
108 | 108 | ||
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c index 82a47bba41c4..a79fa30e7552 100644 --- a/arch/alpha/kernel/irq_srm.c +++ b/arch/alpha/kernel/irq_srm.c | |||
@@ -51,7 +51,7 @@ init_srm_irqs(long max, unsigned long ignore_mask) | |||
51 | for (i = 16; i < max; ++i) { | 51 | for (i = 16; i < max; ++i) { |
52 | if (i < 64 && ((ignore_mask >> i) & 1)) | 52 | if (i < 64 && ((ignore_mask >> i) & 1)) |
53 | continue; | 53 | continue; |
54 | set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq); | 54 | irq_set_chip_and_handler(i, &srm_irq_type, handle_level_irq); |
55 | irq_set_status_flags(i, IRQ_LEVEL); | 55 | irq_set_status_flags(i, IRQ_LEVEL); |
56 | } | 56 | } |
57 | } | 57 | } |
diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c index 88d95e872f55..0e1439904cdb 100644 --- a/arch/alpha/kernel/sys_alcor.c +++ b/arch/alpha/kernel/sys_alcor.c | |||
@@ -125,7 +125,7 @@ alcor_init_irq(void) | |||
125 | on while IRQ probing. */ | 125 | on while IRQ probing. */ |
126 | if (i >= 16+20 && i <= 16+30) | 126 | if (i >= 16+20 && i <= 16+30) |
127 | continue; | 127 | continue; |
128 | set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq); | 128 | irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq); |
129 | irq_set_status_flags(i, IRQ_LEVEL); | 129 | irq_set_status_flags(i, IRQ_LEVEL); |
130 | } | 130 | } |
131 | i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq; | 131 | i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq; |
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c index 57eb6307bc27..c8c112d51584 100644 --- a/arch/alpha/kernel/sys_cabriolet.c +++ b/arch/alpha/kernel/sys_cabriolet.c | |||
@@ -105,8 +105,8 @@ common_init_irq(void (*srm_dev_int)(unsigned long v)) | |||
105 | outb(0xff, 0x806); | 105 | outb(0xff, 0x806); |
106 | 106 | ||
107 | for (i = 16; i < 35; ++i) { | 107 | for (i = 16; i < 35; ++i) { |
108 | set_irq_chip_and_handler(i, &cabriolet_irq_type, | 108 | irq_set_chip_and_handler(i, &cabriolet_irq_type, |
109 | handle_level_irq); | 109 | handle_level_irq); |
110 | irq_set_status_flags(i, IRQ_LEVEL); | 110 | irq_set_status_flags(i, IRQ_LEVEL); |
111 | } | 111 | } |
112 | } | 112 | } |
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c index 481df4ecb651..5ac00fd4cd0c 100644 --- a/arch/alpha/kernel/sys_dp264.c +++ b/arch/alpha/kernel/sys_dp264.c | |||
@@ -270,7 +270,7 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) | |||
270 | { | 270 | { |
271 | long i; | 271 | long i; |
272 | for (i = imin; i <= imax; ++i) { | 272 | for (i = imin; i <= imax; ++i) { |
273 | set_irq_chip_and_handler(i, ops, handle_level_irq); | 273 | irq_set_chip_and_handler(i, ops, handle_level_irq); |
274 | irq_set_status_flags(i, IRQ_LEVEL); | 274 | irq_set_status_flags(i, IRQ_LEVEL); |
275 | } | 275 | } |
276 | } | 276 | } |
diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c index 402e908ffb3e..a7a23b40eec5 100644 --- a/arch/alpha/kernel/sys_eb64p.c +++ b/arch/alpha/kernel/sys_eb64p.c | |||
@@ -118,7 +118,7 @@ eb64p_init_irq(void) | |||
118 | init_i8259a_irqs(); | 118 | init_i8259a_irqs(); |
119 | 119 | ||
120 | for (i = 16; i < 32; ++i) { | 120 | for (i = 16; i < 32; ++i) { |
121 | set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); | 121 | irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq); |
122 | irq_set_status_flags(i, IRQ_LEVEL); | 122 | irq_set_status_flags(i, IRQ_LEVEL); |
123 | } | 123 | } |
124 | 124 | ||
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c index 0b44a54c1522..a60cd5b2621e 100644 --- a/arch/alpha/kernel/sys_eiger.c +++ b/arch/alpha/kernel/sys_eiger.c | |||
@@ -138,7 +138,7 @@ eiger_init_irq(void) | |||
138 | init_i8259a_irqs(); | 138 | init_i8259a_irqs(); |
139 | 139 | ||
140 | for (i = 16; i < 128; ++i) { | 140 | for (i = 16; i < 128; ++i) { |
141 | set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq); | 141 | irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq); |
142 | irq_set_status_flags(i, IRQ_LEVEL); | 142 | irq_set_status_flags(i, IRQ_LEVEL); |
143 | } | 143 | } |
144 | } | 144 | } |
diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c index 00341b75c8b2..7f1a87f176e2 100644 --- a/arch/alpha/kernel/sys_jensen.c +++ b/arch/alpha/kernel/sys_jensen.c | |||
@@ -171,11 +171,11 @@ jensen_init_irq(void) | |||
171 | { | 171 | { |
172 | init_i8259a_irqs(); | 172 | init_i8259a_irqs(); |
173 | 173 | ||
174 | set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); | 174 | irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq); |
175 | set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); | 175 | irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq); |
176 | set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); | 176 | irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq); |
177 | set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); | 177 | irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq); |
178 | set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); | 178 | irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq); |
179 | 179 | ||
180 | common_init_isa_dma(); | 180 | common_init_isa_dma(); |
181 | } | 181 | } |
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index e61910734e41..388b99d1779d 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c | |||
@@ -276,7 +276,7 @@ init_io7_irqs(struct io7 *io7, | |||
276 | 276 | ||
277 | /* Set up the lsi irqs. */ | 277 | /* Set up the lsi irqs. */ |
278 | for (i = 0; i < 128; ++i) { | 278 | for (i = 0; i < 128; ++i) { |
279 | set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq); | 279 | irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq); |
280 | irq_set_status_flags(i, IRQ_LEVEL); | 280 | irq_set_status_flags(i, IRQ_LEVEL); |
281 | } | 281 | } |
282 | 282 | ||
@@ -290,7 +290,7 @@ init_io7_irqs(struct io7 *io7, | |||
290 | 290 | ||
291 | /* Set up the msi irqs. */ | 291 | /* Set up the msi irqs. */ |
292 | for (i = 128; i < (128 + 512); ++i) { | 292 | for (i = 128; i < (128 + 512); ++i) { |
293 | set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq); | 293 | irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq); |
294 | irq_set_status_flags(i, IRQ_LEVEL); | 294 | irq_set_status_flags(i, IRQ_LEVEL); |
295 | } | 295 | } |
296 | 296 | ||
@@ -308,8 +308,8 @@ marvel_init_irq(void) | |||
308 | 308 | ||
309 | /* Reserve the legacy irqs. */ | 309 | /* Reserve the legacy irqs. */ |
310 | for (i = 0; i < 16; ++i) { | 310 | for (i = 0; i < 16; ++i) { |
311 | set_irq_chip_and_handler(i, &marvel_legacy_irq_type, | 311 | irq_set_chip_and_handler(i, &marvel_legacy_irq_type, |
312 | handle_level_irq); | 312 | handle_level_irq); |
313 | } | 313 | } |
314 | 314 | ||
315 | /* Init the io7 irqs. */ | 315 | /* Init the io7 irqs. */ |
diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c index cf7f43dd3147..0e6e4697a025 100644 --- a/arch/alpha/kernel/sys_mikasa.c +++ b/arch/alpha/kernel/sys_mikasa.c | |||
@@ -98,7 +98,8 @@ mikasa_init_irq(void) | |||
98 | mikasa_update_irq_hw(0); | 98 | mikasa_update_irq_hw(0); |
99 | 99 | ||
100 | for (i = 16; i < 32; ++i) { | 100 | for (i = 16; i < 32; ++i) { |
101 | set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq); | 101 | irq_set_chip_and_handler(i, &mikasa_irq_type, |
102 | handle_level_irq); | ||
102 | irq_set_status_flags(i, IRQ_LEVEL); | 103 | irq_set_status_flags(i, IRQ_LEVEL); |
103 | } | 104 | } |
104 | 105 | ||
diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c index 92bc188e94a9..a00ac7087167 100644 --- a/arch/alpha/kernel/sys_noritake.c +++ b/arch/alpha/kernel/sys_noritake.c | |||
@@ -127,7 +127,8 @@ noritake_init_irq(void) | |||
127 | outw(0, 0x54c); | 127 | outw(0, 0x54c); |
128 | 128 | ||
129 | for (i = 16; i < 48; ++i) { | 129 | for (i = 16; i < 48; ++i) { |
130 | set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq); | 130 | irq_set_chip_and_handler(i, &noritake_irq_type, |
131 | handle_level_irq); | ||
131 | irq_set_status_flags(i, IRQ_LEVEL); | 132 | irq_set_status_flags(i, IRQ_LEVEL); |
132 | } | 133 | } |
133 | 134 | ||
diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c index 936d4140ed5f..7f52161f3d88 100644 --- a/arch/alpha/kernel/sys_rawhide.c +++ b/arch/alpha/kernel/sys_rawhide.c | |||
@@ -180,7 +180,8 @@ rawhide_init_irq(void) | |||
180 | } | 180 | } |
181 | 181 | ||
182 | for (i = 16; i < 128; ++i) { | 182 | for (i = 16; i < 128; ++i) { |
183 | set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq); | 183 | irq_set_chip_and_handler(i, &rawhide_irq_type, |
184 | handle_level_irq); | ||
184 | irq_set_status_flags(i, IRQ_LEVEL); | 185 | irq_set_status_flags(i, IRQ_LEVEL); |
185 | } | 186 | } |
186 | 187 | ||
diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c index cea22a62913b..216d94d9c0c1 100644 --- a/arch/alpha/kernel/sys_rx164.c +++ b/arch/alpha/kernel/sys_rx164.c | |||
@@ -99,7 +99,7 @@ rx164_init_irq(void) | |||
99 | 99 | ||
100 | rx164_update_irq_hw(0); | 100 | rx164_update_irq_hw(0); |
101 | for (i = 16; i < 40; ++i) { | 101 | for (i = 16; i < 40; ++i) { |
102 | set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq); | 102 | irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq); |
103 | irq_set_status_flags(i, IRQ_LEVEL); | 103 | irq_set_status_flags(i, IRQ_LEVEL); |
104 | } | 104 | } |
105 | 105 | ||
diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c index a349538aabc9..da714e427c5f 100644 --- a/arch/alpha/kernel/sys_sable.c +++ b/arch/alpha/kernel/sys_sable.c | |||
@@ -518,8 +518,8 @@ sable_lynx_init_irq(int nr_of_irqs) | |||
518 | long i; | 518 | long i; |
519 | 519 | ||
520 | for (i = 0; i < nr_of_irqs; ++i) { | 520 | for (i = 0; i < nr_of_irqs; ++i) { |
521 | set_irq_chip_and_handler(i, &sable_lynx_irq_type, | 521 | irq_set_chip_and_handler(i, &sable_lynx_irq_type, |
522 | handle_level_irq); | 522 | handle_level_irq); |
523 | irq_set_status_flags(i, IRQ_LEVEL); | 523 | irq_set_status_flags(i, IRQ_LEVEL); |
524 | } | 524 | } |
525 | 525 | ||
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c index 42a5331f13c4..a31f8cd9bd6b 100644 --- a/arch/alpha/kernel/sys_takara.c +++ b/arch/alpha/kernel/sys_takara.c | |||
@@ -138,7 +138,8 @@ takara_init_irq(void) | |||
138 | takara_update_irq_hw(i, -1); | 138 | takara_update_irq_hw(i, -1); |
139 | 139 | ||
140 | for (i = 16; i < 128; ++i) { | 140 | for (i = 16; i < 128; ++i) { |
141 | set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq); | 141 | irq_set_chip_and_handler(i, &takara_irq_type, |
142 | handle_level_irq); | ||
142 | irq_set_status_flags(i, IRQ_LEVEL); | 143 | irq_set_status_flags(i, IRQ_LEVEL); |
143 | } | 144 | } |
144 | 145 | ||
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c index 8c13a0c77830..fea0e4620994 100644 --- a/arch/alpha/kernel/sys_titan.c +++ b/arch/alpha/kernel/sys_titan.c | |||
@@ -179,7 +179,7 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax) | |||
179 | { | 179 | { |
180 | long i; | 180 | long i; |
181 | for (i = imin; i <= imax; ++i) { | 181 | for (i = imin; i <= imax; ++i) { |
182 | set_irq_chip_and_handler(i, ops, handle_level_irq); | 182 | irq_set_chip_and_handler(i, ops, handle_level_irq); |
183 | irq_set_status_flags(i, IRQ_LEVEL); | 183 | irq_set_status_flags(i, IRQ_LEVEL); |
184 | } | 184 | } |
185 | } | 185 | } |
diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c index ca60a387ef0a..d3cb28bb8eb0 100644 --- a/arch/alpha/kernel/sys_wildfire.c +++ b/arch/alpha/kernel/sys_wildfire.c | |||
@@ -183,17 +183,17 @@ wildfire_init_irq_per_pca(int qbbno, int pcano) | |||
183 | for (i = 0; i < 16; ++i) { | 183 | for (i = 0; i < 16; ++i) { |
184 | if (i == 2) | 184 | if (i == 2) |
185 | continue; | 185 | continue; |
186 | set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, | 186 | irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, |
187 | handle_level_irq); | 187 | handle_level_irq); |
188 | irq_set_status_flags(i + irq_bias, IRQ_LEVEL); | 188 | irq_set_status_flags(i + irq_bias, IRQ_LEVEL); |
189 | } | 189 | } |
190 | 190 | ||
191 | set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type, | 191 | irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type, |
192 | handle_level_irq); | 192 | handle_level_irq); |
193 | irq_set_status_flags(36 + irq_bias, IRQ_LEVEL); | 193 | irq_set_status_flags(36 + irq_bias, IRQ_LEVEL); |
194 | for (i = 40; i < 64; ++i) { | 194 | for (i = 40; i < 64; ++i) { |
195 | set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type, | 195 | irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type, |
196 | handle_level_irq); | 196 | handle_level_irq); |
197 | irq_set_status_flags(i + irq_bias, IRQ_LEVEL); | 197 | irq_set_status_flags(i + irq_bias, IRQ_LEVEL); |
198 | } | 198 | } |
199 | 199 | ||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index efe06e004714..5b9f78b570e8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -28,6 +28,7 @@ config ARM | |||
28 | select HAVE_C_RECORDMCOUNT | 28 | select HAVE_C_RECORDMCOUNT |
29 | select HAVE_GENERIC_HARDIRQS | 29 | select HAVE_GENERIC_HARDIRQS |
30 | select HAVE_SPARSE_IRQ | 30 | select HAVE_SPARSE_IRQ |
31 | select GENERIC_IRQ_SHOW | ||
31 | help | 32 | help |
32 | The ARM series is a line of low-power-consumption RISC chip designs | 33 | The ARM series is a line of low-power-consumption RISC chip designs |
33 | licensed by ARM Ltd and targeted at embedded applications and | 34 | licensed by ARM Ltd and targeted at embedded applications and |
@@ -365,6 +366,7 @@ config ARCH_MXC | |||
365 | select GENERIC_CLOCKEVENTS | 366 | select GENERIC_CLOCKEVENTS |
366 | select ARCH_REQUIRE_GPIOLIB | 367 | select ARCH_REQUIRE_GPIOLIB |
367 | select CLKDEV_LOOKUP | 368 | select CLKDEV_LOOKUP |
369 | select HAVE_SCHED_CLOCK | ||
368 | help | 370 | help |
369 | Support for Freescale MXC/iMX-based family of processors | 371 | Support for Freescale MXC/iMX-based family of processors |
370 | 372 | ||
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 84ac4d656310..adf583cd0c35 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
@@ -21,20 +21,12 @@ | |||
21 | 21 | ||
22 | #if defined(CONFIG_DEBUG_ICEDCC) | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
23 | 23 | ||
24 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) | 24 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) |
25 | .macro loadsp, rb, tmp | 25 | .macro loadsp, rb, tmp |
26 | .endm | 26 | .endm |
27 | .macro writeb, ch, rb | 27 | .macro writeb, ch, rb |
28 | mcr p14, 0, \ch, c0, c5, 0 | 28 | mcr p14, 0, \ch, c0, c5, 0 |
29 | .endm | 29 | .endm |
30 | #elif defined(CONFIG_CPU_V7) | ||
31 | .macro loadsp, rb, tmp | ||
32 | .endm | ||
33 | .macro writeb, ch, rb | ||
34 | wait: mrc p14, 0, pc, c0, c1, 0 | ||
35 | bcs wait | ||
36 | mcr p14, 0, \ch, c0, c5, 0 | ||
37 | .endm | ||
38 | #elif defined(CONFIG_CPU_XSCALE) | 30 | #elif defined(CONFIG_CPU_XSCALE) |
39 | .macro loadsp, rb, tmp | 31 | .macro loadsp, rb, tmp |
40 | .endm | 32 | .endm |
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 4657e877bf8f..2df38263124c 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c | |||
@@ -36,7 +36,7 @@ extern void error(char *x); | |||
36 | 36 | ||
37 | #ifdef CONFIG_DEBUG_ICEDCC | 37 | #ifdef CONFIG_DEBUG_ICEDCC |
38 | 38 | ||
39 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) | 39 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) |
40 | 40 | ||
41 | static void icedcc_putc(int ch) | 41 | static void icedcc_putc(int ch) |
42 | { | 42 | { |
@@ -52,16 +52,6 @@ static void icedcc_putc(int ch) | |||
52 | asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); | 52 | asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); |
53 | } | 53 | } |
54 | 54 | ||
55 | #elif defined(CONFIG_CPU_V7) | ||
56 | |||
57 | static void icedcc_putc(int ch) | ||
58 | { | ||
59 | asm( | ||
60 | "wait: mrc p14, 0, pc, c0, c1, 0 \n\ | ||
61 | bcs wait \n\ | ||
62 | mcr p14, 0, %0, c0, c5, 0 " | ||
63 | : : "r" (ch)); | ||
64 | } | ||
65 | 55 | ||
66 | #elif defined(CONFIG_CPU_XSCALE) | 56 | #elif defined(CONFIG_CPU_XSCALE) |
67 | 57 | ||
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index cb6b041c39d2..f70ec7dadebb 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) | |||
213 | 213 | ||
214 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | 214 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
215 | { | 215 | { |
216 | struct gic_chip_data *chip_data = get_irq_data(irq); | 216 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
217 | struct irq_chip *chip = get_irq_chip(irq); | 217 | struct irq_chip *chip = irq_get_chip(irq); |
218 | unsigned int cascade_irq, gic_irq; | 218 | unsigned int cascade_irq, gic_irq; |
219 | unsigned long status; | 219 | unsigned long status; |
220 | 220 | ||
@@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) | |||
257 | { | 257 | { |
258 | if (gic_nr >= MAX_GIC_NR) | 258 | if (gic_nr >= MAX_GIC_NR) |
259 | BUG(); | 259 | BUG(); |
260 | if (set_irq_data(irq, &gic_data[gic_nr]) != 0) | 260 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
261 | BUG(); | 261 | BUG(); |
262 | set_irq_chained_handler(irq, gic_handle_cascade_irq); | 262 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
263 | } | 263 | } |
264 | 264 | ||
265 | static void __init gic_dist_init(struct gic_chip_data *gic, | 265 | static void __init gic_dist_init(struct gic_chip_data *gic, |
@@ -319,9 +319,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic, | |||
319 | * Setup the Linux IRQ subsystem. | 319 | * Setup the Linux IRQ subsystem. |
320 | */ | 320 | */ |
321 | for (i = irq_start; i < irq_limit; i++) { | 321 | for (i = irq_start; i < irq_limit; i++) { |
322 | set_irq_chip(i, &gic_chip); | 322 | irq_set_chip_and_handler(i, &gic_chip, handle_level_irq); |
323 | set_irq_chip_data(i, gic); | 323 | irq_set_chip_data(i, gic); |
324 | set_irq_handler(i, handle_level_irq); | ||
325 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 324 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
326 | } | 325 | } |
327 | 326 | ||
@@ -382,7 +381,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq) | |||
382 | unsigned long flags; | 381 | unsigned long flags; |
383 | 382 | ||
384 | local_irq_save(flags); | 383 | local_irq_save(flags); |
385 | irq_to_desc(irq)->status |= IRQ_NOPROBE; | 384 | irq_set_status_flags(irq, IRQ_NOPROBE); |
386 | gic_unmask_irq(irq_get_irq_data(irq)); | 385 | gic_unmask_irq(irq_get_irq_data(irq)); |
387 | local_irq_restore(flags); | 386 | local_irq_restore(flags); |
388 | } | 387 | } |
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c index fcddd48fe9da..7a21927c52e1 100644 --- a/arch/arm/common/it8152.c +++ b/arch/arm/common/it8152.c | |||
@@ -88,8 +88,8 @@ void it8152_init_irq(void) | |||
88 | __raw_writel((0), IT8152_INTC_LDCNIRR); | 88 | __raw_writel((0), IT8152_INTC_LDCNIRR); |
89 | 89 | ||
90 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { | 90 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { |
91 | set_irq_chip(irq, &it8152_irq_chip); | 91 | irq_set_chip_and_handler(irq, &it8152_irq_chip, |
92 | set_irq_handler(irq, handle_level_irq); | 92 | handle_level_irq); |
93 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 93 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
94 | } | 94 | } |
95 | } | 95 | } |
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index a026a6bf4892..b55c3625d7ee 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c | |||
@@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = { | |||
140 | 140 | ||
141 | static void locomo_handler(unsigned int irq, struct irq_desc *desc) | 141 | static void locomo_handler(unsigned int irq, struct irq_desc *desc) |
142 | { | 142 | { |
143 | struct locomo *lchip = get_irq_chip_data(irq); | 143 | struct locomo *lchip = irq_get_chip_data(irq); |
144 | int req, i; | 144 | int req, i; |
145 | 145 | ||
146 | /* Acknowledge the parent IRQ */ | 146 | /* Acknowledge the parent IRQ */ |
@@ -197,15 +197,14 @@ static void locomo_setup_irq(struct locomo *lchip) | |||
197 | /* | 197 | /* |
198 | * Install handler for IRQ_LOCOMO_HW. | 198 | * Install handler for IRQ_LOCOMO_HW. |
199 | */ | 199 | */ |
200 | set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); | 200 | irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); |
201 | set_irq_chip_data(lchip->irq, lchip); | 201 | irq_set_chip_data(lchip->irq, lchip); |
202 | set_irq_chained_handler(lchip->irq, locomo_handler); | 202 | irq_set_chained_handler(lchip->irq, locomo_handler); |
203 | 203 | ||
204 | /* Install handlers for IRQ_LOCOMO_* */ | 204 | /* Install handlers for IRQ_LOCOMO_* */ |
205 | for ( ; irq <= lchip->irq_base + 3; irq++) { | 205 | for ( ; irq <= lchip->irq_base + 3; irq++) { |
206 | set_irq_chip(irq, &locomo_chip); | 206 | irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq); |
207 | set_irq_chip_data(irq, lchip); | 207 | irq_set_chip_data(irq, lchip); |
208 | set_irq_handler(irq, handle_level_irq); | ||
209 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 208 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
210 | } | 209 | } |
211 | } | 210 | } |
@@ -476,8 +475,8 @@ static void __locomo_remove(struct locomo *lchip) | |||
476 | device_for_each_child(lchip->dev, NULL, locomo_remove_child); | 475 | device_for_each_child(lchip->dev, NULL, locomo_remove_child); |
477 | 476 | ||
478 | if (lchip->irq != NO_IRQ) { | 477 | if (lchip->irq != NO_IRQ) { |
479 | set_irq_chained_handler(lchip->irq, NULL); | 478 | irq_set_chained_handler(lchip->irq, NULL); |
480 | set_irq_data(lchip->irq, NULL); | 479 | irq_set_handler_data(lchip->irq, NULL); |
481 | } | 480 | } |
482 | 481 | ||
483 | iounmap(lchip->base); | 482 | iounmap(lchip->base); |
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index eb9796b0dab2..a12b33c0dc42 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c | |||
@@ -202,7 +202,7 @@ static void | |||
202 | sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) | 202 | sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) |
203 | { | 203 | { |
204 | unsigned int stat0, stat1, i; | 204 | unsigned int stat0, stat1, i; |
205 | struct sa1111 *sachip = get_irq_data(irq); | 205 | struct sa1111 *sachip = irq_get_handler_data(irq); |
206 | void __iomem *mapbase = sachip->base + SA1111_INTC; | 206 | void __iomem *mapbase = sachip->base + SA1111_INTC; |
207 | 207 | ||
208 | stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); | 208 | stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); |
@@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip) | |||
472 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); | 472 | sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); |
473 | 473 | ||
474 | for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { | 474 | for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { |
475 | set_irq_chip(irq, &sa1111_low_chip); | 475 | irq_set_chip_and_handler(irq, &sa1111_low_chip, |
476 | set_irq_chip_data(irq, sachip); | 476 | handle_edge_irq); |
477 | set_irq_handler(irq, handle_edge_irq); | 477 | irq_set_chip_data(irq, sachip); |
478 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 478 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
479 | } | 479 | } |
480 | 480 | ||
481 | for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { | 481 | for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { |
482 | set_irq_chip(irq, &sa1111_high_chip); | 482 | irq_set_chip_and_handler(irq, &sa1111_high_chip, |
483 | set_irq_chip_data(irq, sachip); | 483 | handle_edge_irq); |
484 | set_irq_handler(irq, handle_edge_irq); | 484 | irq_set_chip_data(irq, sachip); |
485 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 485 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
486 | } | 486 | } |
487 | 487 | ||
488 | /* | 488 | /* |
489 | * Register SA1111 interrupt | 489 | * Register SA1111 interrupt |
490 | */ | 490 | */ |
491 | set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); | 491 | irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); |
492 | set_irq_data(sachip->irq, sachip); | 492 | irq_set_handler_data(sachip->irq, sachip); |
493 | set_irq_chained_handler(sachip->irq, sa1111_irq_handler); | 493 | irq_set_chained_handler(sachip->irq, sa1111_irq_handler); |
494 | } | 494 | } |
495 | 495 | ||
496 | /* | 496 | /* |
@@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip) | |||
815 | clk_disable(sachip->clk); | 815 | clk_disable(sachip->clk); |
816 | 816 | ||
817 | if (sachip->irq != NO_IRQ) { | 817 | if (sachip->irq != NO_IRQ) { |
818 | set_irq_chained_handler(sachip->irq, NULL); | 818 | irq_set_chained_handler(sachip->irq, NULL); |
819 | set_irq_data(sachip->irq, NULL); | 819 | irq_set_handler_data(sachip->irq, NULL); |
820 | 820 | ||
821 | release_mem_region(sachip->phys + SA1111_INTC, 512); | 821 | release_mem_region(sachip->phys + SA1111_INTC, 512); |
822 | } | 822 | } |
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index ae5fe7292e0d..113085a77123 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c | |||
@@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base, | |||
305 | if (vic_sources & (1 << i)) { | 305 | if (vic_sources & (1 << i)) { |
306 | unsigned int irq = irq_start + i; | 306 | unsigned int irq = irq_start + i; |
307 | 307 | ||
308 | set_irq_chip(irq, &vic_chip); | 308 | irq_set_chip_and_handler(irq, &vic_chip, |
309 | set_irq_chip_data(irq, base); | 309 | handle_level_irq); |
310 | set_irq_handler(irq, handle_level_irq); | 310 | irq_set_chip_data(irq, base); |
311 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 311 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
312 | } | 312 | } |
313 | } | 313 | } |
diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h index 5586b7c8ef6f..a71b417b1856 100644 --- a/arch/arm/include/asm/hw_irq.h +++ b/arch/arm/include/asm/hw_irq.h | |||
@@ -10,14 +10,6 @@ static inline void ack_bad_irq(int irq) | |||
10 | irq_err_count++; | 10 | irq_err_count++; |
11 | } | 11 | } |
12 | 12 | ||
13 | /* | ||
14 | * Obsolete inline function for calling irq descriptor handlers. | ||
15 | */ | ||
16 | static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc) | ||
17 | { | ||
18 | desc->handle_irq(irq, desc); | ||
19 | } | ||
20 | |||
21 | void set_irq_flags(unsigned int irq, unsigned int flags); | 13 | void set_irq_flags(unsigned int irq, unsigned int flags); |
22 | 14 | ||
23 | #define IRQF_VALID (1 << 0) | 15 | #define IRQF_VALID (1 << 0) |
diff --git a/arch/arm/include/asm/mach/udc_pxa2xx.h b/arch/arm/include/asm/mach/udc_pxa2xx.h index 833306ee9e7f..ea297ac70bc6 100644 --- a/arch/arm/include/asm/mach/udc_pxa2xx.h +++ b/arch/arm/include/asm/mach/udc_pxa2xx.h | |||
@@ -20,8 +20,6 @@ struct pxa2xx_udc_mach_info { | |||
20 | * VBUS IRQ and omit the methods above. Store the GPIO number | 20 | * VBUS IRQ and omit the methods above. Store the GPIO number |
21 | * here. Note that sometimes the signals go through inverters... | 21 | * here. Note that sometimes the signals go through inverters... |
22 | */ | 22 | */ |
23 | bool gpio_vbus_inverted; | ||
24 | int gpio_vbus; /* high == vbus present */ | ||
25 | bool gpio_pullup_inverted; | 23 | bool gpio_pullup_inverted; |
26 | int gpio_pullup; /* high == pullup activated */ | 24 | int gpio_pullup; /* high == pullup activated */ |
27 | }; | 25 | }; |
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index d86fcd44b220..e4ee050aad7d 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c | |||
@@ -159,31 +159,6 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev) | |||
159 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); | 159 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285); |
160 | 160 | ||
161 | /* | 161 | /* |
162 | * Same as above. The PrPMC800 carrier board for the PrPMC1100 | ||
163 | * card maps the host-bridge @ 00:01:00 for some reason and it | ||
164 | * ends up getting scanned. Note that we only want to do this | ||
165 | * fixup when we find the IXP4xx on a PrPMC system, which is why | ||
166 | * we check the machine type. We could be running on a board | ||
167 | * with an IXP4xx target device and we don't want to kill the | ||
168 | * resources in that case. | ||
169 | */ | ||
170 | static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev) | ||
171 | { | ||
172 | int i; | ||
173 | |||
174 | if (machine_is_prpmc1100()) { | ||
175 | dev->class &= 0xff; | ||
176 | dev->class |= PCI_CLASS_BRIDGE_HOST << 8; | ||
177 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | ||
178 | dev->resource[i].start = 0; | ||
179 | dev->resource[i].end = 0; | ||
180 | dev->resource[i].flags = 0; | ||
181 | } | ||
182 | } | ||
183 | } | ||
184 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100); | ||
185 | |||
186 | /* | ||
187 | * PCI IDE controllers use non-standard I/O port decoding, respect it. | 162 | * PCI IDE controllers use non-standard I/O port decoding, respect it. |
188 | */ | 163 | */ |
189 | static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) | 164 | static void __devinit pci_fixup_ide_bases(struct pci_dev *dev) |
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index d2d983be096d..bcd66e00bdbe 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S | |||
@@ -25,7 +25,7 @@ | |||
25 | .macro addruart, rp, rv | 25 | .macro addruart, rp, rv |
26 | .endm | 26 | .endm |
27 | 27 | ||
28 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) | 28 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) |
29 | 29 | ||
30 | .macro senduart, rd, rx | 30 | .macro senduart, rd, rx |
31 | mcr p14, 0, \rd, c0, c5, 0 | 31 | mcr p14, 0, \rd, c0, c5, 0 |
@@ -49,23 +49,6 @@ | |||
49 | 1002: | 49 | 1002: |
50 | .endm | 50 | .endm |
51 | 51 | ||
52 | #elif defined(CONFIG_CPU_V7) | ||
53 | |||
54 | .macro senduart, rd, rx | ||
55 | mcr p14, 0, \rd, c0, c5, 0 | ||
56 | .endm | ||
57 | |||
58 | .macro busyuart, rd, rx | ||
59 | busy: mrc p14, 0, pc, c0, c1, 0 | ||
60 | bcs busy | ||
61 | .endm | ||
62 | |||
63 | .macro waituart, rd, rx | ||
64 | wait: mrc p14, 0, pc, c0, c1, 0 | ||
65 | bcs wait | ||
66 | |||
67 | .endm | ||
68 | |||
69 | #elif defined(CONFIG_CPU_XSCALE) | 52 | #elif defined(CONFIG_CPU_XSCALE) |
70 | 53 | ||
71 | .macro senduart, rd, rx | 54 | .macro senduart, rd, rx |
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index 2ad62df37730..d16500110ee9 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c | |||
@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type) | |||
1043 | */ | 1043 | */ |
1044 | if (slot < 8) { | 1044 | if (slot < 8) { |
1045 | ec->irq = 32 + slot; | 1045 | ec->irq = 32 + slot; |
1046 | set_irq_chip(ec->irq, &ecard_chip); | 1046 | irq_set_chip_and_handler(ec->irq, &ecard_chip, |
1047 | set_irq_handler(ec->irq, handle_level_irq); | 1047 | handle_level_irq); |
1048 | set_irq_flags(ec->irq, IRQF_VALID); | 1048 | set_irq_flags(ec->irq, IRQF_VALID); |
1049 | } | 1049 | } |
1050 | 1050 | ||
@@ -1103,7 +1103,7 @@ static int __init ecard_init(void) | |||
1103 | 1103 | ||
1104 | irqhw = ecard_probeirqhw(); | 1104 | irqhw = ecard_probeirqhw(); |
1105 | 1105 | ||
1106 | set_irq_chained_handler(IRQ_EXPANSIONCARD, | 1106 | irq_set_chained_handler(IRQ_EXPANSIONCARD, |
1107 | irqhw ? ecard_irqexp_handler : ecard_irq_handler); | 1107 | irqhw ? ecard_irqexp_handler : ecard_irq_handler); |
1108 | 1108 | ||
1109 | ecard_proc_init(); | 1109 | ecard_proc_init(); |
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c index 052b509e2d5f..1bec8b5f22f0 100644 --- a/arch/arm/kernel/etm.c +++ b/arch/arm/kernel/etm.c | |||
@@ -338,7 +338,7 @@ static struct miscdevice etb_miscdev = { | |||
338 | .fops = &etb_fops, | 338 | .fops = &etb_fops, |
339 | }; | 339 | }; |
340 | 340 | ||
341 | static int __init etb_probe(struct amba_device *dev, const struct amba_id *id) | 341 | static int __devinit etb_probe(struct amba_device *dev, const struct amba_id *id) |
342 | { | 342 | { |
343 | struct tracectx *t = &tracer; | 343 | struct tracectx *t = &tracer; |
344 | int ret = 0; | 344 | int ret = 0; |
@@ -530,7 +530,7 @@ static ssize_t trace_mode_store(struct kobject *kobj, | |||
530 | static struct kobj_attribute trace_mode_attr = | 530 | static struct kobj_attribute trace_mode_attr = |
531 | __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store); | 531 | __ATTR(trace_mode, 0644, trace_mode_show, trace_mode_store); |
532 | 532 | ||
533 | static int __init etm_probe(struct amba_device *dev, const struct amba_id *id) | 533 | static int __devinit etm_probe(struct amba_device *dev, const struct amba_id *id) |
534 | { | 534 | { |
535 | struct tracectx *t = &tracer; | 535 | struct tracectx *t = &tracer; |
536 | int ret = 0; | 536 | int ret = 0; |
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 3535d3793e65..83bbad03fcc6 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
@@ -51,63 +51,18 @@ | |||
51 | 51 | ||
52 | unsigned long irq_err_count; | 52 | unsigned long irq_err_count; |
53 | 53 | ||
54 | int show_interrupts(struct seq_file *p, void *v) | 54 | int arch_show_interrupts(struct seq_file *p, int prec) |
55 | { | 55 | { |
56 | int i = *(loff_t *) v, cpu; | ||
57 | struct irq_desc *desc; | ||
58 | struct irqaction * action; | ||
59 | unsigned long flags; | ||
60 | int prec, n; | ||
61 | |||
62 | for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++) | ||
63 | n *= 10; | ||
64 | |||
65 | #ifdef CONFIG_SMP | ||
66 | if (prec < 4) | ||
67 | prec = 4; | ||
68 | #endif | ||
69 | |||
70 | if (i == 0) { | ||
71 | char cpuname[12]; | ||
72 | |||
73 | seq_printf(p, "%*s ", prec, ""); | ||
74 | for_each_present_cpu(cpu) { | ||
75 | sprintf(cpuname, "CPU%d", cpu); | ||
76 | seq_printf(p, " %10s", cpuname); | ||
77 | } | ||
78 | seq_putc(p, '\n'); | ||
79 | } | ||
80 | |||
81 | if (i < nr_irqs) { | ||
82 | desc = irq_to_desc(i); | ||
83 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
84 | action = desc->action; | ||
85 | if (!action) | ||
86 | goto unlock; | ||
87 | |||
88 | seq_printf(p, "%*d: ", prec, i); | ||
89 | for_each_present_cpu(cpu) | ||
90 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); | ||
91 | seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); | ||
92 | seq_printf(p, " %s", action->name); | ||
93 | for (action = action->next; action; action = action->next) | ||
94 | seq_printf(p, ", %s", action->name); | ||
95 | |||
96 | seq_putc(p, '\n'); | ||
97 | unlock: | ||
98 | raw_spin_unlock_irqrestore(&desc->lock, flags); | ||
99 | } else if (i == nr_irqs) { | ||
100 | #ifdef CONFIG_FIQ | 56 | #ifdef CONFIG_FIQ |
101 | show_fiq_list(p, prec); | 57 | show_fiq_list(p, prec); |
102 | #endif | 58 | #endif |
103 | #ifdef CONFIG_SMP | 59 | #ifdef CONFIG_SMP |
104 | show_ipi_list(p, prec); | 60 | show_ipi_list(p, prec); |
105 | #endif | 61 | #endif |
106 | #ifdef CONFIG_LOCAL_TIMERS | 62 | #ifdef CONFIG_LOCAL_TIMERS |
107 | show_local_irqs(p, prec); | 63 | show_local_irqs(p, prec); |
108 | #endif | 64 | #endif |
109 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); | 65 | seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); |
110 | } | ||
111 | return 0; | 66 | return 0; |
112 | } | 67 | } |
113 | 68 | ||
@@ -144,24 +99,21 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |||
144 | 99 | ||
145 | void set_irq_flags(unsigned int irq, unsigned int iflags) | 100 | void set_irq_flags(unsigned int irq, unsigned int iflags) |
146 | { | 101 | { |
147 | struct irq_desc *desc; | 102 | unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
148 | unsigned long flags; | ||
149 | 103 | ||
150 | if (irq >= nr_irqs) { | 104 | if (irq >= nr_irqs) { |
151 | printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); | 105 | printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq); |
152 | return; | 106 | return; |
153 | } | 107 | } |
154 | 108 | ||
155 | desc = irq_to_desc(irq); | ||
156 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
157 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | ||
158 | if (iflags & IRQF_VALID) | 109 | if (iflags & IRQF_VALID) |
159 | desc->status &= ~IRQ_NOREQUEST; | 110 | clr |= IRQ_NOREQUEST; |
160 | if (iflags & IRQF_PROBE) | 111 | if (iflags & IRQF_PROBE) |
161 | desc->status &= ~IRQ_NOPROBE; | 112 | clr |= IRQ_NOPROBE; |
162 | if (!(iflags & IRQF_NOAUTOEN)) | 113 | if (!(iflags & IRQF_NOAUTOEN)) |
163 | desc->status &= ~IRQ_NOAUTOEN; | 114 | clr |= IRQ_NOAUTOEN; |
164 | raw_spin_unlock_irqrestore(&desc->lock, flags); | 115 | /* Order is clear bits in "clr" then set bits in "set" */ |
116 | irq_modify_status(irq, clr, set & ~clr); | ||
165 | } | 117 | } |
166 | 118 | ||
167 | void __init init_IRQ(void) | 119 | void __init init_IRQ(void) |
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c index 8f6ed43861f1..23891317dc4b 100644 --- a/arch/arm/kernel/kprobes-decode.c +++ b/arch/arm/kernel/kprobes-decode.c | |||
@@ -594,7 +594,8 @@ static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs) | |||
594 | long cpsr = regs->ARM_cpsr; | 594 | long cpsr = regs->ARM_cpsr; |
595 | 595 | ||
596 | fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn); | 596 | fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn); |
597 | regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */ | 597 | if (rn != 15) |
598 | regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */ | ||
598 | rdv = fnr.r1; | 599 | rdv = fnr.r1; |
599 | 600 | ||
600 | if (rd == 15) { | 601 | if (rd == 15) { |
@@ -622,10 +623,11 @@ static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs) | |||
622 | long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd]; | 623 | long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd]; |
623 | long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn]; | 624 | long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn]; |
624 | long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */ | 625 | long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */ |
626 | long rnv_wb; | ||
625 | 627 | ||
626 | /* Save Rn in case of writeback. */ | 628 | rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn); |
627 | regs->uregs[rn] = | 629 | if (rn != 15) |
628 | insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn); | 630 | regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */ |
629 | } | 631 | } |
630 | 632 | ||
631 | static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs) | 633 | static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs) |
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c index 22e194eb8536..69cfee0fe00f 100644 --- a/arch/arm/kernel/perf_event.c +++ b/arch/arm/kernel/perf_event.c | |||
@@ -79,6 +79,7 @@ struct arm_pmu { | |||
79 | void (*write_counter)(int idx, u32 val); | 79 | void (*write_counter)(int idx, u32 val); |
80 | void (*start)(void); | 80 | void (*start)(void); |
81 | void (*stop)(void); | 81 | void (*stop)(void); |
82 | void (*reset)(void *); | ||
82 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] | 83 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
83 | [PERF_COUNT_HW_CACHE_OP_MAX] | 84 | [PERF_COUNT_HW_CACHE_OP_MAX] |
84 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | 85 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; |
@@ -204,11 +205,9 @@ armpmu_event_set_period(struct perf_event *event, | |||
204 | static u64 | 205 | static u64 |
205 | armpmu_event_update(struct perf_event *event, | 206 | armpmu_event_update(struct perf_event *event, |
206 | struct hw_perf_event *hwc, | 207 | struct hw_perf_event *hwc, |
207 | int idx) | 208 | int idx, int overflow) |
208 | { | 209 | { |
209 | int shift = 64 - 32; | 210 | u64 delta, prev_raw_count, new_raw_count; |
210 | s64 prev_raw_count, new_raw_count; | ||
211 | u64 delta; | ||
212 | 211 | ||
213 | again: | 212 | again: |
214 | prev_raw_count = local64_read(&hwc->prev_count); | 213 | prev_raw_count = local64_read(&hwc->prev_count); |
@@ -218,8 +217,13 @@ again: | |||
218 | new_raw_count) != prev_raw_count) | 217 | new_raw_count) != prev_raw_count) |
219 | goto again; | 218 | goto again; |
220 | 219 | ||
221 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | 220 | new_raw_count &= armpmu->max_period; |
222 | delta >>= shift; | 221 | prev_raw_count &= armpmu->max_period; |
222 | |||
223 | if (overflow) | ||
224 | delta = armpmu->max_period - prev_raw_count + new_raw_count; | ||
225 | else | ||
226 | delta = new_raw_count - prev_raw_count; | ||
223 | 227 | ||
224 | local64_add(delta, &event->count); | 228 | local64_add(delta, &event->count); |
225 | local64_sub(delta, &hwc->period_left); | 229 | local64_sub(delta, &hwc->period_left); |
@@ -236,7 +240,7 @@ armpmu_read(struct perf_event *event) | |||
236 | if (hwc->idx < 0) | 240 | if (hwc->idx < 0) |
237 | return; | 241 | return; |
238 | 242 | ||
239 | armpmu_event_update(event, hwc, hwc->idx); | 243 | armpmu_event_update(event, hwc, hwc->idx, 0); |
240 | } | 244 | } |
241 | 245 | ||
242 | static void | 246 | static void |
@@ -254,7 +258,7 @@ armpmu_stop(struct perf_event *event, int flags) | |||
254 | if (!(hwc->state & PERF_HES_STOPPED)) { | 258 | if (!(hwc->state & PERF_HES_STOPPED)) { |
255 | armpmu->disable(hwc, hwc->idx); | 259 | armpmu->disable(hwc, hwc->idx); |
256 | barrier(); /* why? */ | 260 | barrier(); /* why? */ |
257 | armpmu_event_update(event, hwc, hwc->idx); | 261 | armpmu_event_update(event, hwc, hwc->idx, 0); |
258 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; | 262 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
259 | } | 263 | } |
260 | } | 264 | } |
@@ -624,6 +628,19 @@ static struct pmu pmu = { | |||
624 | #include "perf_event_v6.c" | 628 | #include "perf_event_v6.c" |
625 | #include "perf_event_v7.c" | 629 | #include "perf_event_v7.c" |
626 | 630 | ||
631 | /* | ||
632 | * Ensure the PMU has sane values out of reset. | ||
633 | * This requires SMP to be available, so exists as a separate initcall. | ||
634 | */ | ||
635 | static int __init | ||
636 | armpmu_reset(void) | ||
637 | { | ||
638 | if (armpmu && armpmu->reset) | ||
639 | return on_each_cpu(armpmu->reset, NULL, 1); | ||
640 | return 0; | ||
641 | } | ||
642 | arch_initcall(armpmu_reset); | ||
643 | |||
627 | static int __init | 644 | static int __init |
628 | init_hw_perf_events(void) | 645 | init_hw_perf_events(void) |
629 | { | 646 | { |
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index 6fc2d228db55..f1e8dd94afe8 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c | |||
@@ -474,7 +474,7 @@ armv6pmu_handle_irq(int irq_num, | |||
474 | continue; | 474 | continue; |
475 | 475 | ||
476 | hwc = &event->hw; | 476 | hwc = &event->hw; |
477 | armpmu_event_update(event, hwc, idx); | 477 | armpmu_event_update(event, hwc, idx, 1); |
478 | data.period = event->hw.last_period; | 478 | data.period = event->hw.last_period; |
479 | if (!armpmu_event_set_period(event, hwc, idx)) | 479 | if (!armpmu_event_set_period(event, hwc, idx)) |
480 | continue; | 480 | continue; |
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index 2e1402556fa0..4960686afb58 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c | |||
@@ -466,6 +466,7 @@ static inline unsigned long armv7_pmnc_read(void) | |||
466 | static inline void armv7_pmnc_write(unsigned long val) | 466 | static inline void armv7_pmnc_write(unsigned long val) |
467 | { | 467 | { |
468 | val &= ARMV7_PMNC_MASK; | 468 | val &= ARMV7_PMNC_MASK; |
469 | isb(); | ||
469 | asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); | 470 | asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); |
470 | } | 471 | } |
471 | 472 | ||
@@ -502,6 +503,7 @@ static inline int armv7_pmnc_select_counter(unsigned int idx) | |||
502 | 503 | ||
503 | val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; | 504 | val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; |
504 | asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); | 505 | asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); |
506 | isb(); | ||
505 | 507 | ||
506 | return idx; | 508 | return idx; |
507 | } | 509 | } |
@@ -780,7 +782,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) | |||
780 | continue; | 782 | continue; |
781 | 783 | ||
782 | hwc = &event->hw; | 784 | hwc = &event->hw; |
783 | armpmu_event_update(event, hwc, idx); | 785 | armpmu_event_update(event, hwc, idx, 1); |
784 | data.period = event->hw.last_period; | 786 | data.period = event->hw.last_period; |
785 | if (!armpmu_event_set_period(event, hwc, idx)) | 787 | if (!armpmu_event_set_period(event, hwc, idx)) |
786 | continue; | 788 | continue; |
@@ -847,6 +849,18 @@ static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, | |||
847 | } | 849 | } |
848 | } | 850 | } |
849 | 851 | ||
852 | static void armv7pmu_reset(void *info) | ||
853 | { | ||
854 | u32 idx, nb_cnt = armpmu->num_events; | ||
855 | |||
856 | /* The counter and interrupt enable registers are unknown at reset. */ | ||
857 | for (idx = 1; idx < nb_cnt; ++idx) | ||
858 | armv7pmu_disable_event(NULL, idx); | ||
859 | |||
860 | /* Initialize & Reset PMNC: C and P bits */ | ||
861 | armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); | ||
862 | } | ||
863 | |||
850 | static struct arm_pmu armv7pmu = { | 864 | static struct arm_pmu armv7pmu = { |
851 | .handle_irq = armv7pmu_handle_irq, | 865 | .handle_irq = armv7pmu_handle_irq, |
852 | .enable = armv7pmu_enable_event, | 866 | .enable = armv7pmu_enable_event, |
@@ -856,17 +870,15 @@ static struct arm_pmu armv7pmu = { | |||
856 | .get_event_idx = armv7pmu_get_event_idx, | 870 | .get_event_idx = armv7pmu_get_event_idx, |
857 | .start = armv7pmu_start, | 871 | .start = armv7pmu_start, |
858 | .stop = armv7pmu_stop, | 872 | .stop = armv7pmu_stop, |
873 | .reset = armv7pmu_reset, | ||
859 | .raw_event_mask = 0xFF, | 874 | .raw_event_mask = 0xFF, |
860 | .max_period = (1LLU << 32) - 1, | 875 | .max_period = (1LLU << 32) - 1, |
861 | }; | 876 | }; |
862 | 877 | ||
863 | static u32 __init armv7_reset_read_pmnc(void) | 878 | static u32 __init armv7_read_num_pmnc_events(void) |
864 | { | 879 | { |
865 | u32 nb_cnt; | 880 | u32 nb_cnt; |
866 | 881 | ||
867 | /* Initialize & Reset PMNC: C and P bits */ | ||
868 | armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); | ||
869 | |||
870 | /* Read the nb of CNTx counters supported from PMNC */ | 882 | /* Read the nb of CNTx counters supported from PMNC */ |
871 | nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; | 883 | nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; |
872 | 884 | ||
@@ -880,7 +892,7 @@ static const struct arm_pmu *__init armv7_a8_pmu_init(void) | |||
880 | armv7pmu.name = "ARMv7 Cortex-A8"; | 892 | armv7pmu.name = "ARMv7 Cortex-A8"; |
881 | armv7pmu.cache_map = &armv7_a8_perf_cache_map; | 893 | armv7pmu.cache_map = &armv7_a8_perf_cache_map; |
882 | armv7pmu.event_map = &armv7_a8_perf_map; | 894 | armv7pmu.event_map = &armv7_a8_perf_map; |
883 | armv7pmu.num_events = armv7_reset_read_pmnc(); | 895 | armv7pmu.num_events = armv7_read_num_pmnc_events(); |
884 | return &armv7pmu; | 896 | return &armv7pmu; |
885 | } | 897 | } |
886 | 898 | ||
@@ -890,7 +902,7 @@ static const struct arm_pmu *__init armv7_a9_pmu_init(void) | |||
890 | armv7pmu.name = "ARMv7 Cortex-A9"; | 902 | armv7pmu.name = "ARMv7 Cortex-A9"; |
891 | armv7pmu.cache_map = &armv7_a9_perf_cache_map; | 903 | armv7pmu.cache_map = &armv7_a9_perf_cache_map; |
892 | armv7pmu.event_map = &armv7_a9_perf_map; | 904 | armv7pmu.event_map = &armv7_a9_perf_map; |
893 | armv7pmu.num_events = armv7_reset_read_pmnc(); | 905 | armv7pmu.num_events = armv7_read_num_pmnc_events(); |
894 | return &armv7pmu; | 906 | return &armv7pmu; |
895 | } | 907 | } |
896 | #else | 908 | #else |
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index 28cd3b025bc3..39affbe4fdb2 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c | |||
@@ -246,7 +246,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev) | |||
246 | continue; | 246 | continue; |
247 | 247 | ||
248 | hwc = &event->hw; | 248 | hwc = &event->hw; |
249 | armpmu_event_update(event, hwc, idx); | 249 | armpmu_event_update(event, hwc, idx, 1); |
250 | data.period = event->hw.last_period; | 250 | data.period = event->hw.last_period; |
251 | if (!armpmu_event_set_period(event, hwc, idx)) | 251 | if (!armpmu_event_set_period(event, hwc, idx)) |
252 | continue; | 252 | continue; |
@@ -578,7 +578,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev) | |||
578 | continue; | 578 | continue; |
579 | 579 | ||
580 | hwc = &event->hw; | 580 | hwc = &event->hw; |
581 | armpmu_event_update(event, hwc, idx); | 581 | armpmu_event_update(event, hwc, idx, 1); |
582 | data.period = event->hw.last_period; | 582 | data.period = event->hw.last_period; |
583 | if (!armpmu_event_set_period(event, hwc, idx)) | 583 | if (!armpmu_event_set_period(event, hwc, idx)) |
584 | continue; | 584 | continue; |
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index bfad698a02e7..6398ead9d1c0 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S | |||
@@ -119,11 +119,19 @@ ENTRY(cpu_resume) | |||
119 | #else | 119 | #else |
120 | ldr r0, sleep_save_sp @ stack phys addr | 120 | ldr r0, sleep_save_sp @ stack phys addr |
121 | #endif | 121 | #endif |
122 | msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off | 122 | setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off |
123 | #ifdef MULTI_CPU | 123 | #ifdef MULTI_CPU |
124 | ldmia r0!, {r1, sp, lr, pc} @ load v:p, stack, return fn, resume fn | 124 | @ load v:p, stack, return fn, resume fn |
125 | ARM( ldmia r0!, {r1, sp, lr, pc} ) | ||
126 | THUMB( ldmia r0!, {r1, r2, r3, r4} ) | ||
127 | THUMB( mov sp, r2 ) | ||
128 | THUMB( mov lr, r3 ) | ||
129 | THUMB( bx r4 ) | ||
125 | #else | 130 | #else |
126 | ldmia r0!, {r1, sp, lr} @ load v:p, stack, return fn | 131 | @ load v:p, stack, return fn |
132 | ARM( ldmia r0!, {r1, sp, lr} ) | ||
133 | THUMB( ldmia r0!, {r1, r2, lr} ) | ||
134 | THUMB( mov sp, r2 ) | ||
127 | b cpu_do_resume | 135 | b cpu_do_resume |
128 | #endif | 136 | #endif |
129 | ENDPROC(cpu_resume) | 137 | ENDPROC(cpu_resume) |
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c index d1f775e86353..9ffbf3a2dfea 100644 --- a/arch/arm/mach-at91/at91cap9_devices.c +++ b/arch/arm/mach-at91/at91cap9_devices.c | |||
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) | |||
72 | return; | 72 | return; |
73 | 73 | ||
74 | if (cpu_is_at91cap9_revB()) | 74 | if (cpu_is_at91cap9_revB()) |
75 | set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); | 75 | irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); |
76 | 76 | ||
77 | /* Enable VBus control for UHP ports */ | 77 | /* Enable VBus control for UHP ports */ |
78 | for (i = 0; i < data->ports; i++) { | 78 | for (i = 0; i < data->ports; i++) { |
@@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = { | |||
157 | void __init at91_add_device_usba(struct usba_platform_data *data) | 157 | void __init at91_add_device_usba(struct usba_platform_data *data) |
158 | { | 158 | { |
159 | if (cpu_is_at91cap9_revB()) { | 159 | if (cpu_is_at91cap9_revB()) { |
160 | set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); | 160 | irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); |
161 | at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | | 161 | at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | |
162 | AT91_MATRIX_UDPHS_BYPASS_LOCK); | 162 | AT91_MATRIX_UDPHS_BYPASS_LOCK); |
163 | } | 163 | } |
@@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |||
861 | return; | 861 | return; |
862 | 862 | ||
863 | if (cpu_is_at91cap9_revB()) | 863 | if (cpu_is_at91cap9_revB()) |
864 | set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); | 864 | irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); |
865 | 865 | ||
866 | at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ | 866 | at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ |
867 | at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ | 867 | at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ |
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index af818a21587c..4615528205c8 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
@@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) | |||
287 | else | 287 | else |
288 | wakeups[bank] &= ~mask; | 288 | wakeups[bank] &= ~mask; |
289 | 289 | ||
290 | set_irq_wake(gpio_chip[bank].bank->id, state); | 290 | irq_set_irq_wake(gpio_chip[bank].bank->id, state); |
291 | 291 | ||
292 | return 0; | 292 | return 0; |
293 | } | 293 | } |
@@ -375,6 +375,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) | |||
375 | 375 | ||
376 | static struct irq_chip gpio_irqchip = { | 376 | static struct irq_chip gpio_irqchip = { |
377 | .name = "GPIO", | 377 | .name = "GPIO", |
378 | .irq_disable = gpio_irq_mask, | ||
378 | .irq_mask = gpio_irq_mask, | 379 | .irq_mask = gpio_irq_mask, |
379 | .irq_unmask = gpio_irq_unmask, | 380 | .irq_unmask = gpio_irq_unmask, |
380 | .irq_set_type = gpio_irq_type, | 381 | .irq_set_type = gpio_irq_type, |
@@ -384,16 +385,14 @@ static struct irq_chip gpio_irqchip = { | |||
384 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 385 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
385 | { | 386 | { |
386 | unsigned pin; | 387 | unsigned pin; |
387 | struct irq_desc *gpio; | 388 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
388 | struct at91_gpio_chip *at91_gpio; | 389 | struct irq_chip *chip = irq_data_get_irq_chip(idata); |
389 | void __iomem *pio; | 390 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); |
391 | void __iomem *pio = at91_gpio->regbase; | ||
390 | u32 isr; | 392 | u32 isr; |
391 | 393 | ||
392 | at91_gpio = get_irq_chip_data(irq); | ||
393 | pio = at91_gpio->regbase; | ||
394 | |||
395 | /* temporarily mask (level sensitive) parent IRQ */ | 394 | /* temporarily mask (level sensitive) parent IRQ */ |
396 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 395 | chip->irq_ack(idata); |
397 | for (;;) { | 396 | for (;;) { |
398 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | 397 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
399 | * When there none are pending, we're finished unless we need | 398 | * When there none are pending, we're finished unless we need |
@@ -409,27 +408,15 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
409 | } | 408 | } |
410 | 409 | ||
411 | pin = at91_gpio->chip.base; | 410 | pin = at91_gpio->chip.base; |
412 | gpio = &irq_desc[pin]; | ||
413 | 411 | ||
414 | while (isr) { | 412 | while (isr) { |
415 | if (isr & 1) { | 413 | if (isr & 1) |
416 | if (unlikely(gpio->depth)) { | 414 | generic_handle_irq(pin); |
417 | /* | ||
418 | * The core ARM interrupt handler lazily disables IRQs so | ||
419 | * another IRQ must be generated before it actually gets | ||
420 | * here to be disabled on the GPIO controller. | ||
421 | */ | ||
422 | gpio_irq_mask(irq_get_irq_data(pin)); | ||
423 | } | ||
424 | else | ||
425 | generic_handle_irq(pin); | ||
426 | } | ||
427 | pin++; | 415 | pin++; |
428 | gpio++; | ||
429 | isr >>= 1; | 416 | isr >>= 1; |
430 | } | 417 | } |
431 | } | 418 | } |
432 | desc->irq_data.chip->irq_unmask(&desc->irq_data); | 419 | chip->irq_unmask(idata); |
433 | /* now it may re-trigger */ | 420 | /* now it may re-trigger */ |
434 | } | 421 | } |
435 | 422 | ||
@@ -518,14 +505,14 @@ void __init at91_gpio_irq_setup(void) | |||
518 | __raw_writel(~0, this->regbase + PIO_IDR); | 505 | __raw_writel(~0, this->regbase + PIO_IDR); |
519 | 506 | ||
520 | for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { | 507 | for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { |
521 | lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); | 508 | irq_set_lockdep_class(pin, &gpio_lock_class); |
522 | 509 | ||
523 | /* | 510 | /* |
524 | * Can use the "simple" and not "edge" handler since it's | 511 | * Can use the "simple" and not "edge" handler since it's |
525 | * shorter, and the AIC handles interrupts sanely. | 512 | * shorter, and the AIC handles interrupts sanely. |
526 | */ | 513 | */ |
527 | set_irq_chip(pin, &gpio_irqchip); | 514 | irq_set_chip_and_handler(pin, &gpio_irqchip, |
528 | set_irq_handler(pin, handle_simple_irq); | 515 | handle_simple_irq); |
529 | set_irq_flags(pin, IRQF_VALID); | 516 | set_irq_flags(pin, IRQF_VALID); |
530 | } | 517 | } |
531 | 518 | ||
@@ -536,8 +523,8 @@ void __init at91_gpio_irq_setup(void) | |||
536 | if (prev && prev->next == this) | 523 | if (prev && prev->next == this) |
537 | continue; | 524 | continue; |
538 | 525 | ||
539 | set_irq_chip_data(id, this); | 526 | irq_set_chip_data(id, this); |
540 | set_irq_chained_handler(id, gpio_irq_handler); | 527 | irq_set_chained_handler(id, gpio_irq_handler); |
541 | } | 528 | } |
542 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); | 529 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); |
543 | } | 530 | } |
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h index 2d9b0af9c4d5..be510cfc56be 100644 --- a/arch/arm/mach-at91/include/mach/at572d940hf.h +++ b/arch/arm/mach-at91/include/mach/at572d940hf.h | |||
@@ -89,7 +89,7 @@ | |||
89 | /* | 89 | /* |
90 | * System Peripherals (offset from AT91_BASE_SYS) | 90 | * System Peripherals (offset from AT91_BASE_SYS) |
91 | */ | 91 | */ |
92 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | 92 | #define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) |
93 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | 93 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) |
94 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | 94 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
95 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | 95 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index b56d6b3a4087..9665265ec757 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c | |||
@@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) | |||
143 | /* Active Low interrupt, with the specified priority */ | 143 | /* Active Low interrupt, with the specified priority */ |
144 | at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); | 144 | at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); |
145 | 145 | ||
146 | set_irq_chip(i, &at91_aic_chip); | 146 | irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); |
147 | set_irq_handler(i, handle_level_irq); | ||
148 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 147 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
149 | 148 | ||
150 | /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ | 149 | /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ |
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c index 84dcda0d1d9a..c48feaf4e8e9 100644 --- a/arch/arm/mach-bcmring/irq.c +++ b/arch/arm/mach-bcmring/irq.c | |||
@@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip, | |||
93 | unsigned int i; | 93 | unsigned int i; |
94 | for (i = 0; i < 32; i++) { | 94 | for (i = 0; i < 32; i++) { |
95 | unsigned int irq = irq_start + i; | 95 | unsigned int irq = irq_start + i; |
96 | set_irq_chip(irq, chip); | 96 | irq_set_chip(irq, chip); |
97 | set_irq_chip_data(irq, base); | 97 | irq_set_chip_data(irq, base); |
98 | 98 | ||
99 | if (vic_sources & (1 << i)) { | 99 | if (vic_sources & (1 << i)) { |
100 | set_irq_handler(irq, handle_level_irq); | 100 | irq_set_handler(irq, handle_level_irq); |
101 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 101 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
102 | } | 102 | } |
103 | } | 103 | } |
@@ -119,9 +119,9 @@ void __init bcmring_init_irq(void) | |||
119 | 119 | ||
120 | /* special cases */ | 120 | /* special cases */ |
121 | if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { | 121 | if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { |
122 | set_irq_handler(IRQ_GPIO0, handle_simple_irq); | 122 | irq_set_handler(IRQ_GPIO0, handle_simple_irq); |
123 | } | 123 | } |
124 | if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { | 124 | if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { |
125 | set_irq_handler(IRQ_GPIO1, handle_simple_irq); | 125 | irq_set_handler(IRQ_GPIO1, handle_simple_irq); |
126 | } | 126 | } |
127 | } | 127 | } |
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c index 86da7a1b2bbe..c2eceee645e3 100644 --- a/arch/arm/mach-clps711x/irq.c +++ b/arch/arm/mach-clps711x/irq.c | |||
@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void) | |||
112 | 112 | ||
113 | for (i = 0; i < NR_IRQS; i++) { | 113 | for (i = 0; i < NR_IRQS; i++) { |
114 | if (INT1_IRQS & (1 << i)) { | 114 | if (INT1_IRQS & (1 << i)) { |
115 | set_irq_handler(i, handle_level_irq); | 115 | irq_set_chip_and_handler(i, &int1_chip, |
116 | set_irq_chip(i, &int1_chip); | 116 | handle_level_irq); |
117 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 117 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
118 | } | 118 | } |
119 | if (INT2_IRQS & (1 << i)) { | 119 | if (INT2_IRQS & (1 << i)) { |
120 | set_irq_handler(i, handle_level_irq); | 120 | irq_set_chip_and_handler(i, &int2_chip, |
121 | set_irq_chip(i, &int2_chip); | 121 | handle_level_irq); |
122 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 122 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
123 | } | 123 | } |
124 | } | 124 | } |
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index 9abc80a86a22..f83152d643c5 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c | |||
@@ -167,9 +167,9 @@ void __init cp_intc_init(void) | |||
167 | 167 | ||
168 | /* Set up genirq dispatching for cp_intc */ | 168 | /* Set up genirq dispatching for cp_intc */ |
169 | for (i = 0; i < num_irq; i++) { | 169 | for (i = 0; i < num_irq; i++) { |
170 | set_irq_chip(i, &cp_intc_irq_chip); | 170 | irq_set_chip(i, &cp_intc_irq_chip); |
171 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 171 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
172 | set_irq_handler(i, handle_edge_irq); | 172 | irq_set_handler(i, handle_edge_irq); |
173 | } | 173 | } |
174 | 174 | ||
175 | /* Enable global interrupt */ | 175 | /* Enable global interrupt */ |
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 20d66e5e4663..a0b838894ac9 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c | |||
@@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) | |||
62 | { | 62 | { |
63 | struct davinci_gpio_regs __iomem *g; | 63 | struct davinci_gpio_regs __iomem *g; |
64 | 64 | ||
65 | g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); | 65 | g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); |
66 | 66 | ||
67 | return g; | 67 | return g; |
68 | } | 68 | } |
@@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup); | |||
208 | static void gpio_irq_disable(struct irq_data *d) | 208 | static void gpio_irq_disable(struct irq_data *d) |
209 | { | 209 | { |
210 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 210 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
211 | u32 mask = (u32) irq_data_get_irq_data(d); | 211 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
212 | 212 | ||
213 | __raw_writel(mask, &g->clr_falling); | 213 | __raw_writel(mask, &g->clr_falling); |
214 | __raw_writel(mask, &g->clr_rising); | 214 | __raw_writel(mask, &g->clr_rising); |
@@ -217,8 +217,8 @@ static void gpio_irq_disable(struct irq_data *d) | |||
217 | static void gpio_irq_enable(struct irq_data *d) | 217 | static void gpio_irq_enable(struct irq_data *d) |
218 | { | 218 | { |
219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 219 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
220 | u32 mask = (u32) irq_data_get_irq_data(d); | 220 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
221 | unsigned status = irq_desc[d->irq].status; | 221 | unsigned status = irqd_get_trigger_type(d); |
222 | 222 | ||
223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; | 223 | status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; |
224 | if (!status) | 224 | if (!status) |
@@ -233,21 +233,11 @@ static void gpio_irq_enable(struct irq_data *d) | |||
233 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) | 233 | static int gpio_irq_type(struct irq_data *d, unsigned trigger) |
234 | { | 234 | { |
235 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 235 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
236 | u32 mask = (u32) irq_data_get_irq_data(d); | 236 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
237 | 237 | ||
238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 238 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
239 | return -EINVAL; | 239 | return -EINVAL; |
240 | 240 | ||
241 | irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK; | ||
242 | irq_desc[d->irq].status |= trigger; | ||
243 | |||
244 | /* don't enable the IRQ if it's currently disabled */ | ||
245 | if (irq_desc[d->irq].depth == 0) { | ||
246 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) | ||
247 | ? &g->set_falling : &g->clr_falling); | ||
248 | __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) | ||
249 | ? &g->set_rising : &g->clr_rising); | ||
250 | } | ||
251 | return 0; | 241 | return 0; |
252 | } | 242 | } |
253 | 243 | ||
@@ -256,6 +246,7 @@ static struct irq_chip gpio_irqchip = { | |||
256 | .irq_enable = gpio_irq_enable, | 246 | .irq_enable = gpio_irq_enable, |
257 | .irq_disable = gpio_irq_disable, | 247 | .irq_disable = gpio_irq_disable, |
258 | .irq_set_type = gpio_irq_type, | 248 | .irq_set_type = gpio_irq_type, |
249 | .flags = IRQCHIP_SET_TYPE_MASKED, | ||
259 | }; | 250 | }; |
260 | 251 | ||
261 | static void | 252 | static void |
@@ -285,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
285 | status >>= 16; | 276 | status >>= 16; |
286 | 277 | ||
287 | /* now demux them to the right lowlevel handler */ | 278 | /* now demux them to the right lowlevel handler */ |
288 | n = (int)get_irq_data(irq); | 279 | n = (int)irq_get_handler_data(irq); |
289 | while (status) { | 280 | while (status) { |
290 | res = ffs(status); | 281 | res = ffs(status); |
291 | n += res; | 282 | n += res; |
@@ -323,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |||
323 | static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) | 314 | static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) |
324 | { | 315 | { |
325 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); | 316 | struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); |
326 | u32 mask = (u32) irq_data_get_irq_data(d); | 317 | u32 mask = (u32) irq_data_get_irq_handler_data(d); |
327 | 318 | ||
328 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 319 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
329 | return -EINVAL; | 320 | return -EINVAL; |
@@ -395,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
395 | 386 | ||
396 | /* AINTC handles mask/unmask; GPIO handles triggering */ | 387 | /* AINTC handles mask/unmask; GPIO handles triggering */ |
397 | irq = bank_irq; | 388 | irq = bank_irq; |
398 | gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq)); | 389 | gpio_irqchip_unbanked = *irq_get_chip(irq); |
399 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; | 390 | gpio_irqchip_unbanked.name = "GPIO-AINTC"; |
400 | gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; | 391 | gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; |
401 | 392 | ||
@@ -406,10 +397,10 @@ static int __init davinci_gpio_irq_setup(void) | |||
406 | 397 | ||
407 | /* set the direct IRQs up to use that irqchip */ | 398 | /* set the direct IRQs up to use that irqchip */ |
408 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | 399 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { |
409 | set_irq_chip(irq, &gpio_irqchip_unbanked); | 400 | irq_set_chip(irq, &gpio_irqchip_unbanked); |
410 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | 401 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); |
411 | set_irq_chip_data(irq, (__force void *) g); | 402 | irq_set_chip_data(irq, (__force void *)g); |
412 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; | 403 | irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); |
413 | } | 404 | } |
414 | 405 | ||
415 | goto done; | 406 | goto done; |
@@ -430,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void) | |||
430 | __raw_writel(~0, &g->clr_rising); | 421 | __raw_writel(~0, &g->clr_rising); |
431 | 422 | ||
432 | /* set up all irqs in this bank */ | 423 | /* set up all irqs in this bank */ |
433 | set_irq_chained_handler(bank_irq, gpio_irq_handler); | 424 | irq_set_chained_handler(bank_irq, gpio_irq_handler); |
434 | set_irq_chip_data(bank_irq, (__force void *) g); | 425 | irq_set_chip_data(bank_irq, (__force void *)g); |
435 | set_irq_data(bank_irq, (void *) irq); | 426 | irq_set_handler_data(bank_irq, (void *)irq); |
436 | 427 | ||
437 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { | 428 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
438 | set_irq_chip(irq, &gpio_irqchip); | 429 | irq_set_chip(irq, &gpio_irqchip); |
439 | set_irq_chip_data(irq, (__force void *) g); | 430 | irq_set_chip_data(irq, (__force void *)g); |
440 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | 431 | irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); |
441 | set_irq_handler(irq, handle_simple_irq); | 432 | irq_set_handler(irq, handle_simple_irq); |
442 | set_irq_flags(irq, IRQF_VALID); | 433 | set_irq_flags(irq, IRQF_VALID); |
443 | } | 434 | } |
444 | 435 | ||
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 5e05c9b64e1f..e6269a6e0014 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c | |||
@@ -154,11 +154,11 @@ void __init davinci_irq_init(void) | |||
154 | 154 | ||
155 | /* set up genirq dispatch for ARM INTC */ | 155 | /* set up genirq dispatch for ARM INTC */ |
156 | for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { | 156 | for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { |
157 | set_irq_chip(i, &davinci_irq_chip_0); | 157 | irq_set_chip(i, &davinci_irq_chip_0); |
158 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 158 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
159 | if (i != IRQ_TINT1_TINT34) | 159 | if (i != IRQ_TINT1_TINT34) |
160 | set_irq_handler(i, handle_edge_irq); | 160 | irq_set_handler(i, handle_edge_irq); |
161 | else | 161 | else |
162 | set_irq_handler(i, handle_level_irq); | 162 | irq_set_handler(i, handle_level_irq); |
163 | } | 163 | } |
164 | } | 164 | } |
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h index e5fcdd3f5bf5..b20ec9af7882 100644 --- a/arch/arm/mach-dove/include/mach/dove.h +++ b/arch/arm/mach-dove/include/mach/dove.h | |||
@@ -136,7 +136,7 @@ | |||
136 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) | 136 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) |
137 | #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) | 137 | #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) |
138 | #define DOVE_NAND_GPIO_EN (1 << 0) | 138 | #define DOVE_NAND_GPIO_EN (1 << 0) |
139 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) | 139 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) |
140 | #define DOVE_SPI_GPIO_SEL (1 << 5) | 140 | #define DOVE_SPI_GPIO_SEL (1 << 5) |
141 | #define DOVE_UART1_GPIO_SEL (1 << 4) | 141 | #define DOVE_UART1_GPIO_SEL (1 << 4) |
142 | #define DOVE_AU1_GPIO_SEL (1 << 3) | 142 | #define DOVE_AU1_GPIO_SEL (1 << 3) |
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 101707fa2e2c..f07fd16e0c9b 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c | |||
@@ -86,8 +86,7 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
86 | if (!(cause & (1 << irq))) | 86 | if (!(cause & (1 << irq))) |
87 | continue; | 87 | continue; |
88 | irq = pmu_to_irq(irq); | 88 | irq = pmu_to_irq(irq); |
89 | desc = irq_desc + irq; | 89 | generic_handle_irq(irq); |
90 | desc_handle_irq(irq, desc); | ||
91 | } | 90 | } |
92 | } | 91 | } |
93 | 92 | ||
@@ -103,14 +102,14 @@ void __init dove_init_irq(void) | |||
103 | */ | 102 | */ |
104 | orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, | 103 | orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, |
105 | IRQ_DOVE_GPIO_START); | 104 | IRQ_DOVE_GPIO_START); |
106 | set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); | 105 | irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); |
107 | set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); | 106 | irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); |
108 | set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); | 107 | irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); |
109 | set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); | 108 | irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); |
110 | 109 | ||
111 | orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, | 110 | orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, |
112 | IRQ_DOVE_GPIO_START + 32); | 111 | IRQ_DOVE_GPIO_START + 32); |
113 | set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); | 112 | irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); |
114 | 113 | ||
115 | orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, | 114 | orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, |
116 | IRQ_DOVE_GPIO_START + 64); | 115 | IRQ_DOVE_GPIO_START + 64); |
@@ -122,10 +121,9 @@ void __init dove_init_irq(void) | |||
122 | writel(0, PMU_INTERRUPT_CAUSE); | 121 | writel(0, PMU_INTERRUPT_CAUSE); |
123 | 122 | ||
124 | for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { | 123 | for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { |
125 | set_irq_chip(i, &pmu_irq_chip); | 124 | irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); |
126 | set_irq_handler(i, handle_level_irq); | 125 | irq_set_status_flags(i, IRQ_LEVEL); |
127 | irq_desc[i].status |= IRQ_LEVEL; | ||
128 | set_irq_flags(i, IRQF_VALID); | 126 | set_irq_flags(i, IRQF_VALID); |
129 | } | 127 | } |
130 | set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); | 128 | irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); |
131 | } | 129 | } |
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c index 71db2bdf2f28..c66c76346904 100644 --- a/arch/arm/mach-dove/mpp.c +++ b/arch/arm/mach-dove/mpp.c | |||
@@ -147,9 +147,6 @@ void __init dove_mpp_conf(unsigned int *mpp_list) | |||
147 | u32 pmu_sig_ctrl[PMU_SIG_REGS]; | 147 | u32 pmu_sig_ctrl[PMU_SIG_REGS]; |
148 | int i; | 148 | int i; |
149 | 149 | ||
150 | /* Initialize gpiolib. */ | ||
151 | orion_gpio_init(); | ||
152 | |||
153 | for (i = 0; i < MPP_NR_REGS; i++) | 150 | for (i = 0; i < MPP_NR_REGS; i++) |
154 | mpp_ctrl[i] = readl(MPP_CTRL(i)); | 151 | mpp_ctrl[i] = readl(MPP_CTRL(i)); |
155 | 152 | ||
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c index 7df083f37fa7..087bc771ac23 100644 --- a/arch/arm/mach-ebsa110/core.c +++ b/arch/arm/mach-ebsa110/core.c | |||
@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void) | |||
66 | local_irq_restore(flags); | 66 | local_irq_restore(flags); |
67 | 67 | ||
68 | for (irq = 0; irq < NR_IRQS; irq++) { | 68 | for (irq = 0; irq < NR_IRQS; irq++) { |
69 | set_irq_chip(irq, &ebsa110_irq_chip); | 69 | irq_set_chip_and_handler(irq, &ebsa110_irq_chip, |
70 | set_irq_handler(irq, handle_level_irq); | 70 | handle_level_irq); |
71 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 71 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
72 | } | 72 | } |
73 | } | 73 | } |
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index 34e071d79761..180b8a9d0d21 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c | |||
@@ -117,7 +117,7 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) | |||
117 | int port = line >> 3; | 117 | int port = line >> 3; |
118 | int port_mask = 1 << (line & 7); | 118 | int port_mask = 1 << (line & 7); |
119 | 119 | ||
120 | if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | 120 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
121 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 121 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
122 | ep93xx_gpio_update_int_params(port); | 122 | ep93xx_gpio_update_int_params(port); |
123 | } | 123 | } |
@@ -131,7 +131,7 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) | |||
131 | int port = line >> 3; | 131 | int port = line >> 3; |
132 | int port_mask = 1 << (line & 7); | 132 | int port_mask = 1 << (line & 7); |
133 | 133 | ||
134 | if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) | 134 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) |
135 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ | 135 | gpio_int_type2[port] ^= port_mask; /* switch edge direction */ |
136 | 136 | ||
137 | gpio_int_unmasked[port] &= ~port_mask; | 137 | gpio_int_unmasked[port] &= ~port_mask; |
@@ -165,10 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) | |||
165 | */ | 165 | */ |
166 | static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) | 166 | static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) |
167 | { | 167 | { |
168 | struct irq_desc *desc = irq_desc + d->irq; | ||
169 | const int gpio = irq_to_gpio(d->irq); | 168 | const int gpio = irq_to_gpio(d->irq); |
170 | const int port = gpio >> 3; | 169 | const int port = gpio >> 3; |
171 | const int port_mask = 1 << (gpio & 7); | 170 | const int port_mask = 1 << (gpio & 7); |
171 | irq_flow_handler_t handler; | ||
172 | 172 | ||
173 | gpio_direction_input(gpio); | 173 | gpio_direction_input(gpio); |
174 | 174 | ||
@@ -176,22 +176,22 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) | |||
176 | case IRQ_TYPE_EDGE_RISING: | 176 | case IRQ_TYPE_EDGE_RISING: |
177 | gpio_int_type1[port] |= port_mask; | 177 | gpio_int_type1[port] |= port_mask; |
178 | gpio_int_type2[port] |= port_mask; | 178 | gpio_int_type2[port] |= port_mask; |
179 | desc->handle_irq = handle_edge_irq; | 179 | handler = handle_edge_irq; |
180 | break; | 180 | break; |
181 | case IRQ_TYPE_EDGE_FALLING: | 181 | case IRQ_TYPE_EDGE_FALLING: |
182 | gpio_int_type1[port] |= port_mask; | 182 | gpio_int_type1[port] |= port_mask; |
183 | gpio_int_type2[port] &= ~port_mask; | 183 | gpio_int_type2[port] &= ~port_mask; |
184 | desc->handle_irq = handle_edge_irq; | 184 | handler = handle_edge_irq; |
185 | break; | 185 | break; |
186 | case IRQ_TYPE_LEVEL_HIGH: | 186 | case IRQ_TYPE_LEVEL_HIGH: |
187 | gpio_int_type1[port] &= ~port_mask; | 187 | gpio_int_type1[port] &= ~port_mask; |
188 | gpio_int_type2[port] |= port_mask; | 188 | gpio_int_type2[port] |= port_mask; |
189 | desc->handle_irq = handle_level_irq; | 189 | handler = handle_level_irq; |
190 | break; | 190 | break; |
191 | case IRQ_TYPE_LEVEL_LOW: | 191 | case IRQ_TYPE_LEVEL_LOW: |
192 | gpio_int_type1[port] &= ~port_mask; | 192 | gpio_int_type1[port] &= ~port_mask; |
193 | gpio_int_type2[port] &= ~port_mask; | 193 | gpio_int_type2[port] &= ~port_mask; |
194 | desc->handle_irq = handle_level_irq; | 194 | handler = handle_level_irq; |
195 | break; | 195 | break; |
196 | case IRQ_TYPE_EDGE_BOTH: | 196 | case IRQ_TYPE_EDGE_BOTH: |
197 | gpio_int_type1[port] |= port_mask; | 197 | gpio_int_type1[port] |= port_mask; |
@@ -200,17 +200,16 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) | |||
200 | gpio_int_type2[port] &= ~port_mask; /* falling */ | 200 | gpio_int_type2[port] &= ~port_mask; /* falling */ |
201 | else | 201 | else |
202 | gpio_int_type2[port] |= port_mask; /* rising */ | 202 | gpio_int_type2[port] |= port_mask; /* rising */ |
203 | desc->handle_irq = handle_edge_irq; | 203 | handler = handle_edge_irq; |
204 | break; | 204 | break; |
205 | default: | 205 | default: |
206 | pr_err("failed to set irq type %d for gpio %d\n", type, gpio); | 206 | pr_err("failed to set irq type %d for gpio %d\n", type, gpio); |
207 | return -EINVAL; | 207 | return -EINVAL; |
208 | } | 208 | } |
209 | 209 | ||
210 | gpio_int_enabled[port] |= port_mask; | 210 | __irq_set_handler_locked(d->irq, handler); |
211 | 211 | ||
212 | desc->status &= ~IRQ_TYPE_SENSE_MASK; | 212 | gpio_int_enabled[port] |= port_mask; |
213 | desc->status |= type & IRQ_TYPE_SENSE_MASK; | ||
214 | 213 | ||
215 | ep93xx_gpio_update_int_params(port); | 214 | ep93xx_gpio_update_int_params(port); |
216 | 215 | ||
@@ -232,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void) | |||
232 | 231 | ||
233 | for (gpio_irq = gpio_to_irq(0); | 232 | for (gpio_irq = gpio_to_irq(0); |
234 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { | 233 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { |
235 | set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); | 234 | irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, |
236 | set_irq_handler(gpio_irq, handle_level_irq); | 235 | handle_level_irq); |
237 | set_irq_flags(gpio_irq, IRQF_VALID); | 236 | set_irq_flags(gpio_irq, IRQF_VALID); |
238 | } | 237 | } |
239 | 238 | ||
240 | set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); | 239 | irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, |
241 | set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); | 240 | ep93xx_gpio_ab_irq_handler); |
242 | set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); | 241 | irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, |
243 | set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); | 242 | ep93xx_gpio_f_irq_handler); |
244 | set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); | 243 | irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, |
245 | set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); | 244 | ep93xx_gpio_f_irq_handler); |
246 | set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); | 245 | irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, |
247 | set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); | 246 | ep93xx_gpio_f_irq_handler); |
248 | set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); | 247 | irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, |
248 | ep93xx_gpio_f_irq_handler); | ||
249 | irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, | ||
250 | ep93xx_gpio_f_irq_handler); | ||
251 | irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, | ||
252 | ep93xx_gpio_f_irq_handler); | ||
253 | irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, | ||
254 | ep93xx_gpio_f_irq_handler); | ||
255 | irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, | ||
256 | ep93xx_gpio_f_irq_handler); | ||
249 | } | 257 | } |
250 | 258 | ||
251 | 259 | ||
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c index 31618d91ce15..f488b66d6806 100644 --- a/arch/arm/mach-exynos4/irq-combiner.c +++ b/arch/arm/mach-exynos4/irq-combiner.c | |||
@@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data) | |||
54 | 54 | ||
55 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | 55 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
56 | { | 56 | { |
57 | struct combiner_chip_data *chip_data = get_irq_data(irq); | 57 | struct combiner_chip_data *chip_data = irq_get_handler_data(irq); |
58 | struct irq_chip *chip = get_irq_chip(irq); | 58 | struct irq_chip *chip = irq_get_chip(irq); |
59 | unsigned int cascade_irq, combiner_irq; | 59 | unsigned int cascade_irq, combiner_irq; |
60 | unsigned long status; | 60 | unsigned long status; |
61 | 61 | ||
@@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) | |||
93 | { | 93 | { |
94 | if (combiner_nr >= MAX_COMBINER_NR) | 94 | if (combiner_nr >= MAX_COMBINER_NR) |
95 | BUG(); | 95 | BUG(); |
96 | if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) | 96 | if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) |
97 | BUG(); | 97 | BUG(); |
98 | set_irq_chained_handler(irq, combiner_handle_cascade_irq); | 98 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); |
99 | } | 99 | } |
100 | 100 | ||
101 | void __init combiner_init(unsigned int combiner_nr, void __iomem *base, | 101 | void __init combiner_init(unsigned int combiner_nr, void __iomem *base, |
@@ -119,9 +119,8 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, | |||
119 | 119 | ||
120 | for (i = irq_start; i < combiner_data[combiner_nr].irq_offset | 120 | for (i = irq_start; i < combiner_data[combiner_nr].irq_offset |
121 | + MAX_IRQ_IN_COMBINER; i++) { | 121 | + MAX_IRQ_IN_COMBINER; i++) { |
122 | set_irq_chip(i, &combiner_chip); | 122 | irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq); |
123 | set_irq_chip_data(i, &combiner_data[combiner_nr]); | 123 | irq_set_chip_data(i, &combiner_data[combiner_nr]); |
124 | set_irq_handler(i, handle_level_irq); | ||
125 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 124 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
126 | } | 125 | } |
127 | } | 126 | } |
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c index 4f7ad4a796e4..9d87d2ac7f68 100644 --- a/arch/arm/mach-exynos4/irq-eint.c +++ b/arch/arm/mach-exynos4/irq-eint.c | |||
@@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | |||
190 | 190 | ||
191 | static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) | 191 | static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) |
192 | { | 192 | { |
193 | u32 *irq_data = get_irq_data(irq); | 193 | u32 *irq_data = irq_get_handler_data(irq); |
194 | struct irq_chip *chip = get_irq_chip(irq); | 194 | struct irq_chip *chip = irq_get_chip(irq); |
195 | 195 | ||
196 | chip->irq_mask(&desc->irq_data); | 196 | chip->irq_mask(&desc->irq_data); |
197 | 197 | ||
@@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void) | |||
208 | int irq; | 208 | int irq; |
209 | 209 | ||
210 | for (irq = 0 ; irq <= 31 ; irq++) { | 210 | for (irq = 0 ; irq <= 31 ; irq++) { |
211 | set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); | 211 | irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, |
212 | set_irq_handler(IRQ_EINT(irq), handle_level_irq); | 212 | handle_level_irq); |
213 | set_irq_flags(IRQ_EINT(irq), IRQF_VALID); | 213 | set_irq_flags(IRQ_EINT(irq), IRQF_VALID); |
214 | } | 214 | } |
215 | 215 | ||
216 | set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); | 216 | irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); |
217 | 217 | ||
218 | for (irq = 0 ; irq <= 15 ; irq++) { | 218 | for (irq = 0 ; irq <= 15 ; irq++) { |
219 | eint0_15_data[irq] = IRQ_EINT(irq); | 219 | eint0_15_data[irq] = IRQ_EINT(irq); |
220 | 220 | ||
221 | set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); | 221 | irq_set_handler_data(exynos4_get_irq_nr(irq), |
222 | set_irq_chained_handler(exynos4_get_irq_nr(irq), | 222 | &eint0_15_data[irq]); |
223 | irq_set_chained_handler(exynos4_get_irq_nr(irq), | ||
223 | exynos4_irq_eint0_15); | 224 | exynos4_irq_eint0_15); |
224 | } | 225 | } |
225 | 226 | ||
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 84c5f258f2d8..38a44f9b9da2 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c | |||
@@ -102,8 +102,7 @@ static void __init __fb_init_irq(void) | |||
102 | *CSR_FIQ_DISABLE = -1; | 102 | *CSR_FIQ_DISABLE = -1; |
103 | 103 | ||
104 | for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { | 104 | for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { |
105 | set_irq_chip(irq, &fb_chip); | 105 | irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq); |
106 | set_irq_handler(irq, handle_level_irq); | ||
107 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 106 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
108 | } | 107 | } |
109 | } | 108 | } |
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index a921fe92b858..5f1f9867fc70 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c | |||
@@ -30,7 +30,7 @@ static int cksrc_dc21285_enable(struct clocksource *cs) | |||
30 | return 0; | 30 | return 0; |
31 | } | 31 | } |
32 | 32 | ||
33 | static int cksrc_dc21285_disable(struct clocksource *cs) | 33 | static void cksrc_dc21285_disable(struct clocksource *cs) |
34 | { | 34 | { |
35 | *CSR_TIMER2_CNTL = 0; | 35 | *CSR_TIMER2_CNTL = 0; |
36 | } | 36 | } |
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index de7a5cb5dbe1..c3a0abbc9049 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c | |||
@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq) | |||
151 | 151 | ||
152 | if (host_irq != (unsigned int)-1) { | 152 | if (host_irq != (unsigned int)-1) { |
153 | for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { | 153 | for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { |
154 | set_irq_chip(irq, &isa_lo_chip); | 154 | irq_set_chip_and_handler(irq, &isa_lo_chip, |
155 | set_irq_handler(irq, handle_level_irq); | 155 | handle_level_irq); |
156 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 156 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
157 | } | 157 | } |
158 | 158 | ||
159 | for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { | 159 | for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { |
160 | set_irq_chip(irq, &isa_hi_chip); | 160 | irq_set_chip_and_handler(irq, &isa_hi_chip, |
161 | set_irq_handler(irq, handle_level_irq); | 161 | handle_level_irq); |
162 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 162 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
163 | } | 163 | } |
164 | 164 | ||
@@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq) | |||
166 | request_resource(&ioport_resource, &pic2_resource); | 166 | request_resource(&ioport_resource, &pic2_resource); |
167 | setup_irq(IRQ_ISA_CASCADE, &irq_cascade); | 167 | setup_irq(IRQ_ISA_CASCADE, &irq_cascade); |
168 | 168 | ||
169 | set_irq_chained_handler(host_irq, isa_irq_handler); | 169 | irq_set_chained_handler(host_irq, isa_irq_handler); |
170 | 170 | ||
171 | /* | 171 | /* |
172 | * On the NetWinder, don't automatically | 172 | * On the NetWinder, don't automatically |
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index fa3d333f21e1..fdc7ef1391d3 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c | |||
@@ -127,8 +127,8 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type) | |||
127 | 127 | ||
128 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 128 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
129 | { | 129 | { |
130 | unsigned int port = (unsigned int)irq_desc_get_handler_data(desc); | ||
130 | unsigned int gpio_irq_no, irq_stat; | 131 | unsigned int gpio_irq_no, irq_stat; |
131 | unsigned int port = (unsigned int)get_irq_data(irq); | ||
132 | 132 | ||
133 | irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); | 133 | irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT); |
134 | 134 | ||
@@ -138,9 +138,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
138 | if ((irq_stat & 1) == 0) | 138 | if ((irq_stat & 1) == 0) |
139 | continue; | 139 | continue; |
140 | 140 | ||
141 | BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); | 141 | generic_handle_irq(gpio_irq_no); |
142 | irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, | ||
143 | &irq_desc[gpio_irq_no]); | ||
144 | } | 142 | } |
145 | } | 143 | } |
146 | 144 | ||
@@ -219,13 +217,13 @@ void __init gemini_gpio_init(void) | |||
219 | 217 | ||
220 | for (j = GPIO_IRQ_BASE + i * 32; | 218 | for (j = GPIO_IRQ_BASE + i * 32; |
221 | j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { | 219 | j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { |
222 | set_irq_chip(j, &gpio_irq_chip); | 220 | irq_set_chip_and_handler(j, &gpio_irq_chip, |
223 | set_irq_handler(j, handle_edge_irq); | 221 | handle_edge_irq); |
224 | set_irq_flags(j, IRQF_VALID); | 222 | set_irq_flags(j, IRQF_VALID); |
225 | } | 223 | } |
226 | 224 | ||
227 | set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); | 225 | irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler); |
228 | set_irq_data(IRQ_GPIO(i), (void *)i); | 226 | irq_set_handler_data(IRQ_GPIO(i), (void *)i); |
229 | } | 227 | } |
230 | 228 | ||
231 | BUG_ON(gpiochip_add(&gemini_gpio_chip)); | 229 | BUG_ON(gpiochip_add(&gemini_gpio_chip)); |
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c index 96bc227dd849..9485a8fdf851 100644 --- a/arch/arm/mach-gemini/irq.c +++ b/arch/arm/mach-gemini/irq.c | |||
@@ -81,13 +81,13 @@ void __init gemini_init_irq(void) | |||
81 | request_resource(&iomem_resource, &irq_resource); | 81 | request_resource(&iomem_resource, &irq_resource); |
82 | 82 | ||
83 | for (i = 0; i < NR_IRQS; i++) { | 83 | for (i = 0; i < NR_IRQS; i++) { |
84 | set_irq_chip(i, &gemini_irq_chip); | 84 | irq_set_chip(i, &gemini_irq_chip); |
85 | if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { | 85 | if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { |
86 | set_irq_handler(i, handle_edge_irq); | 86 | irq_set_handler(i, handle_edge_irq); |
87 | mode |= 1 << i; | 87 | mode |= 1 << i; |
88 | level |= 1 << i; | 88 | level |= 1 << i; |
89 | } else { | 89 | } else { |
90 | set_irq_handler(i, handle_level_irq); | 90 | irq_set_handler(i, handle_level_irq); |
91 | } | 91 | } |
92 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 92 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
93 | } | 93 | } |
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c index 1f28c90932c7..51d4e44ab973 100644 --- a/arch/arm/mach-h720x/common.c +++ b/arch/arm/mach-h720x/common.c | |||
@@ -199,29 +199,29 @@ void __init h720x_init_irq (void) | |||
199 | 199 | ||
200 | /* Initialize global IRQ's, fast path */ | 200 | /* Initialize global IRQ's, fast path */ |
201 | for (irq = 0; irq < NR_GLBL_IRQS; irq++) { | 201 | for (irq = 0; irq < NR_GLBL_IRQS; irq++) { |
202 | set_irq_chip(irq, &h720x_global_chip); | 202 | irq_set_chip_and_handler(irq, &h720x_global_chip, |
203 | set_irq_handler(irq, handle_level_irq); | 203 | handle_level_irq); |
204 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 204 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
205 | } | 205 | } |
206 | 206 | ||
207 | /* Initialize multiplexed IRQ's, slow path */ | 207 | /* Initialize multiplexed IRQ's, slow path */ |
208 | for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { | 208 | for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { |
209 | set_irq_chip(irq, &h720x_gpio_chip); | 209 | irq_set_chip_and_handler(irq, &h720x_gpio_chip, |
210 | set_irq_handler(irq, handle_edge_irq); | 210 | handle_edge_irq); |
211 | set_irq_flags(irq, IRQF_VALID ); | 211 | set_irq_flags(irq, IRQF_VALID ); |
212 | } | 212 | } |
213 | set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); | 213 | irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); |
214 | set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); | 214 | irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); |
215 | set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); | 215 | irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); |
216 | set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); | 216 | irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); |
217 | 217 | ||
218 | #ifdef CONFIG_CPU_H7202 | 218 | #ifdef CONFIG_CPU_H7202 |
219 | for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { | 219 | for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { |
220 | set_irq_chip(irq, &h720x_gpio_chip); | 220 | irq_set_chip_and_handler(irq, &h720x_gpio_chip, |
221 | set_irq_handler(irq, handle_edge_irq); | 221 | handle_edge_irq); |
222 | set_irq_flags(irq, IRQF_VALID ); | 222 | set_irq_flags(irq, IRQF_VALID ); |
223 | } | 223 | } |
224 | set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); | 224 | irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); |
225 | #endif | 225 | #endif |
226 | 226 | ||
227 | /* Enable multiplexed irq's */ | 227 | /* Enable multiplexed irq's */ |
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c index ac3f91442376..c37d570b852d 100644 --- a/arch/arm/mach-h720x/cpu-h7202.c +++ b/arch/arm/mach-h720x/cpu-h7202.c | |||
@@ -141,13 +141,18 @@ h7202_timer_interrupt(int irq, void *dev_id) | |||
141 | /* | 141 | /* |
142 | * mask multiplexed timer IRQs | 142 | * mask multiplexed timer IRQs |
143 | */ | 143 | */ |
144 | static void inline mask_timerx_irq(struct irq_data *d) | 144 | static void inline __mask_timerx_irq(unsigned int irq) |
145 | { | 145 | { |
146 | unsigned int bit; | 146 | unsigned int bit; |
147 | bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1)); | 147 | bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1)); |
148 | CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; | 148 | CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; |
149 | } | 149 | } |
150 | 150 | ||
151 | static void inline mask_timerx_irq(struct irq_data *d) | ||
152 | { | ||
153 | __mask_timerx_irq(d->irq); | ||
154 | } | ||
155 | |||
151 | /* | 156 | /* |
152 | * unmask multiplexed timer IRQs | 157 | * unmask multiplexed timer IRQs |
153 | */ | 158 | */ |
@@ -196,12 +201,12 @@ void __init h7202_init_irq (void) | |||
196 | 201 | ||
197 | for (irq = IRQ_TIMER1; | 202 | for (irq = IRQ_TIMER1; |
198 | irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { | 203 | irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { |
199 | mask_timerx_irq(irq); | 204 | __mask_timerx_irq(irq); |
200 | set_irq_chip(irq, &h7202_timerx_chip); | 205 | irq_set_chip_and_handler(irq, &h7202_timerx_chip, |
201 | set_irq_handler(irq, handle_edge_irq); | 206 | handle_edge_irq); |
202 | set_irq_flags(irq, IRQF_VALID ); | 207 | set_irq_flags(irq, IRQF_VALID ); |
203 | } | 208 | } |
204 | set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); | 209 | irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); |
205 | 210 | ||
206 | h720x_init_irq(); | 211 | h720x_init_irq(); |
207 | } | 212 | } |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 5eec099e0c72..56b930a13443 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
@@ -255,6 +255,7 @@ config MACH_IMX27_VISSTRIM_M10 | |||
255 | bool "Vista Silicon i.MX27 Visstrim_m10" | 255 | bool "Vista Silicon i.MX27 Visstrim_m10" |
256 | select SOC_IMX27 | 256 | select SOC_IMX27 |
257 | select IMX_HAVE_PLATFORM_IMX_I2C | 257 | select IMX_HAVE_PLATFORM_IMX_I2C |
258 | select IMX_HAVE_PLATFORM_IMX_SSI | ||
258 | select IMX_HAVE_PLATFORM_IMX_UART | 259 | select IMX_HAVE_PLATFORM_IMX_UART |
259 | select IMX_HAVE_PLATFORM_MXC_MMC | 260 | select IMX_HAVE_PLATFORM_MXC_MMC |
260 | select IMX_HAVE_PLATFORM_MXC_EHCI | 261 | select IMX_HAVE_PLATFORM_MXC_EHCI |
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c index cb705c28de02..6269053505f7 100644 --- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c +++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <mach/mx25.h> | 34 | #include <mach/mx25.h> |
35 | #include <mach/imx-uart.h> | 35 | #include <mach/imx-uart.h> |
36 | #include <mach/audmux.h> | 36 | #include <mach/audmux.h> |
37 | #include <mach/esdhc.h> | ||
37 | 38 | ||
38 | #include "devices-imx25.h" | 39 | #include "devices-imx25.h" |
39 | 40 | ||
@@ -242,6 +243,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { | |||
242 | .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, | 243 | .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, |
243 | }; | 244 | }; |
244 | 245 | ||
246 | static struct esdhc_platform_data sd1_pdata = { | ||
247 | .cd_gpio = GPIO_SD1CD, | ||
248 | .wp_gpio = -EINVAL, | ||
249 | }; | ||
250 | |||
245 | /* | 251 | /* |
246 | * system init for baseboard usage. Will be called by cpuimx25 init. | 252 | * system init for baseboard usage. Will be called by cpuimx25 init. |
247 | * | 253 | * |
@@ -275,7 +281,7 @@ void __init eukrea_mbimxsd25_baseboard_init(void) | |||
275 | imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); | 281 | imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); |
276 | 282 | ||
277 | imx25_add_flexcan1(NULL); | 283 | imx25_add_flexcan1(NULL); |
278 | imx25_add_sdhci_esdhc_imx(0, NULL); | 284 | imx25_add_sdhci_esdhc_imx(0, &sd1_pdata); |
279 | 285 | ||
280 | gpio_request(GPIO_LED1, "LED1"); | 286 | gpio_request(GPIO_LED1, "LED1"); |
281 | gpio_direction_output(GPIO_LED1, 1); | 287 | gpio_direction_output(GPIO_LED1, 1); |
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c index a233470dd10c..bc739701c301 100644 --- a/arch/arm/mach-iop13xx/irq.c +++ b/arch/arm/mach-iop13xx/irq.c | |||
@@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void) | |||
224 | 224 | ||
225 | for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { | 225 | for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { |
226 | if (i < 32) | 226 | if (i < 32) |
227 | set_irq_chip(i, &iop13xx_irqchip1); | 227 | irq_set_chip(i, &iop13xx_irqchip1); |
228 | else if (i < 64) | 228 | else if (i < 64) |
229 | set_irq_chip(i, &iop13xx_irqchip2); | 229 | irq_set_chip(i, &iop13xx_irqchip2); |
230 | else if (i < 96) | 230 | else if (i < 96) |
231 | set_irq_chip(i, &iop13xx_irqchip3); | 231 | irq_set_chip(i, &iop13xx_irqchip3); |
232 | else | 232 | else |
233 | set_irq_chip(i, &iop13xx_irqchip4); | 233 | irq_set_chip(i, &iop13xx_irqchip4); |
234 | 234 | ||
235 | set_irq_handler(i, handle_level_irq); | 235 | irq_set_handler(i, handle_level_irq); |
236 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 236 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
237 | } | 237 | } |
238 | 238 | ||
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c index c9c02e3698bc..560d5b2dec22 100644 --- a/arch/arm/mach-iop13xx/msi.c +++ b/arch/arm/mach-iop13xx/msi.c | |||
@@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) | |||
118 | 118 | ||
119 | void __init iop13xx_msi_init(void) | 119 | void __init iop13xx_msi_init(void) |
120 | { | 120 | { |
121 | set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); | 121 | irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); |
122 | } | 122 | } |
123 | 123 | ||
124 | /* | 124 | /* |
@@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |||
178 | if (irq < 0) | 178 | if (irq < 0) |
179 | return irq; | 179 | return irq; |
180 | 180 | ||
181 | set_irq_msi(irq, desc); | 181 | irq_set_msi_desc(irq, desc); |
182 | 182 | ||
183 | msg.address_hi = 0x0; | 183 | msg.address_hi = 0x0; |
184 | msg.address_lo = IOP13XX_MU_MIMR_PCI; | 184 | msg.address_lo = IOP13XX_MU_MIMR_PCI; |
@@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |||
187 | msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); | 187 | msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); |
188 | 188 | ||
189 | write_msi_msg(irq, &msg); | 189 | write_msi_msg(irq, &msg); |
190 | set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); | 190 | irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); |
191 | 191 | ||
192 | return 0; | 192 | return 0; |
193 | } | 193 | } |
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index d3426a120599..d7ee2789d890 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c | |||
@@ -68,8 +68,7 @@ void __init iop32x_init_irq(void) | |||
68 | *IOP3XX_PCIIRSR = 0x0f; | 68 | *IOP3XX_PCIIRSR = 0x0f; |
69 | 69 | ||
70 | for (i = 0; i < NR_IRQS; i++) { | 70 | for (i = 0; i < NR_IRQS; i++) { |
71 | set_irq_chip(i, &ext_chip); | 71 | irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); |
72 | set_irq_handler(i, handle_level_irq); | ||
73 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 72 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
74 | } | 73 | } |
75 | } | 74 | } |
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c index 0ff2f74363a5..f7f5d3e451c7 100644 --- a/arch/arm/mach-iop33x/irq.c +++ b/arch/arm/mach-iop33x/irq.c | |||
@@ -110,8 +110,9 @@ void __init iop33x_init_irq(void) | |||
110 | *IOP3XX_PCIIRSR = 0x0f; | 110 | *IOP3XX_PCIIRSR = 0x0f; |
111 | 111 | ||
112 | for (i = 0; i < NR_IRQS; i++) { | 112 | for (i = 0; i < NR_IRQS; i++) { |
113 | set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); | 113 | irq_set_chip_and_handler(i, |
114 | set_irq_handler(i, handle_level_irq); | 114 | (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2, |
115 | handle_level_irq); | ||
115 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 116 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
116 | } | 117 | } |
117 | } | 118 | } |
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c index 5fc4e064b650..4068166c8993 100644 --- a/arch/arm/mach-ixp2000/core.c +++ b/arch/arm/mach-ixp2000/core.c | |||
@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void) | |||
476 | */ | 476 | */ |
477 | for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { | 477 | for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { |
478 | if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { | 478 | if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { |
479 | set_irq_chip(irq, &ixp2000_irq_chip); | 479 | irq_set_chip_and_handler(irq, &ixp2000_irq_chip, |
480 | set_irq_handler(irq, handle_level_irq); | 480 | handle_level_irq); |
481 | set_irq_flags(irq, IRQF_VALID); | 481 | set_irq_flags(irq, IRQF_VALID); |
482 | } else set_irq_flags(irq, 0); | 482 | } else set_irq_flags(irq, 0); |
483 | } | 483 | } |
@@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void) | |||
485 | for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { | 485 | for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { |
486 | if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & | 486 | if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & |
487 | IXP2000_VALID_ERR_IRQ_MASK) { | 487 | IXP2000_VALID_ERR_IRQ_MASK) { |
488 | set_irq_chip(irq, &ixp2000_err_irq_chip); | 488 | irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip, |
489 | set_irq_handler(irq, handle_level_irq); | 489 | handle_level_irq); |
490 | set_irq_flags(irq, IRQF_VALID); | 490 | set_irq_flags(irq, IRQF_VALID); |
491 | } | 491 | } |
492 | else | 492 | else |
493 | set_irq_flags(irq, 0); | 493 | set_irq_flags(irq, 0); |
494 | } | 494 | } |
495 | set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); | 495 | irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); |
496 | 496 | ||
497 | for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { | 497 | for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { |
498 | set_irq_chip(irq, &ixp2000_GPIO_irq_chip); | 498 | irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip, |
499 | set_irq_handler(irq, handle_level_irq); | 499 | handle_level_irq); |
500 | set_irq_flags(irq, IRQF_VALID); | 500 | set_irq_flags(irq, IRQF_VALID); |
501 | } | 501 | } |
502 | set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); | 502 | irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); |
503 | 503 | ||
504 | /* | 504 | /* |
505 | * Enable PCI irqs. The actual PCI[AB] decoding is done in | 505 | * Enable PCI irqs. The actual PCI[AB] decoding is done in |
@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void) | |||
508 | */ | 508 | */ |
509 | ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); | 509 | ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); |
510 | for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { | 510 | for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { |
511 | set_irq_chip(irq, &ixp2000_pci_irq_chip); | 511 | irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip, |
512 | set_irq_handler(irq, handle_level_irq); | 512 | handle_level_irq); |
513 | set_irq_flags(irq, IRQF_VALID); | 513 | set_irq_flags(irq, IRQF_VALID); |
514 | } | 514 | } |
515 | } | 515 | } |
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 7d90d3f13ee8..235638f800e5 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c | |||
@@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne | |||
158 | *board_irq_mask = 0xffffffff; | 158 | *board_irq_mask = 0xffffffff; |
159 | 159 | ||
160 | for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { | 160 | for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { |
161 | set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); | 161 | irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, |
162 | set_irq_handler(irq, handle_level_irq); | 162 | handle_level_irq); |
163 | set_irq_flags(irq, IRQF_VALID); | 163 | set_irq_flags(irq, IRQF_VALID); |
164 | } | 164 | } |
165 | 165 | ||
166 | /* Hook into PCI interrupt */ | 166 | /* Hook into PCI interrupt */ |
167 | set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); | 167 | irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); |
168 | } | 168 | } |
169 | 169 | ||
170 | /************************************************************************* | 170 | /************************************************************************* |
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index 34b1b2af37c8..84835b209557 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c | |||
@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void) | |||
115 | 115 | ||
116 | for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { | 116 | for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { |
117 | if (irq & valid_irq_mask) { | 117 | if (irq & valid_irq_mask) { |
118 | set_irq_chip(irq, &ixdp2x01_irq_chip); | 118 | irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip, |
119 | set_irq_handler(irq, handle_level_irq); | 119 | handle_level_irq); |
120 | set_irq_flags(irq, IRQF_VALID); | 120 | set_irq_flags(irq, IRQF_VALID); |
121 | } else { | 121 | } else { |
122 | set_irq_flags(irq, 0); | 122 | set_irq_flags(irq, 0); |
@@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void) | |||
124 | } | 124 | } |
125 | 125 | ||
126 | /* Hook into PCI interrupts */ | 126 | /* Hook into PCI interrupts */ |
127 | set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); | 127 | irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); |
128 | } | 128 | } |
129 | 129 | ||
130 | 130 | ||
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c index 9c8a33903216..a1bee33d183e 100644 --- a/arch/arm/mach-ixp23xx/core.c +++ b/arch/arm/mach-ixp23xx/core.c | |||
@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) | |||
289 | { | 289 | { |
290 | switch (type) { | 290 | switch (type) { |
291 | case IXP23XX_IRQ_LEVEL: | 291 | case IXP23XX_IRQ_LEVEL: |
292 | set_irq_chip(irq, &ixp23xx_irq_level_chip); | 292 | irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip, |
293 | set_irq_handler(irq, handle_level_irq); | 293 | handle_level_irq); |
294 | break; | 294 | break; |
295 | case IXP23XX_IRQ_EDGE: | 295 | case IXP23XX_IRQ_EDGE: |
296 | set_irq_chip(irq, &ixp23xx_irq_edge_chip); | 296 | irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip, |
297 | set_irq_handler(irq, handle_edge_irq); | 297 | handle_edge_irq); |
298 | break; | 298 | break; |
299 | } | 299 | } |
300 | set_irq_flags(irq, IRQF_VALID); | 300 | set_irq_flags(irq, IRQF_VALID); |
@@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void) | |||
324 | } | 324 | } |
325 | 325 | ||
326 | for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { | 326 | for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { |
327 | set_irq_chip(irq, &ixp23xx_pci_irq_chip); | 327 | irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip, |
328 | set_irq_handler(irq, handle_level_irq); | 328 | handle_level_irq); |
329 | set_irq_flags(irq, IRQF_VALID); | 329 | set_irq_flags(irq, IRQF_VALID); |
330 | } | 330 | } |
331 | 331 | ||
332 | set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); | 332 | irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); |
333 | } | 333 | } |
334 | 334 | ||
335 | 335 | ||
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c index 181116aa6591..8dcba17c81e7 100644 --- a/arch/arm/mach-ixp23xx/ixdp2351.c +++ b/arch/arm/mach-ixp23xx/ixdp2351.c | |||
@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void) | |||
136 | irq++) { | 136 | irq++) { |
137 | if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { | 137 | if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { |
138 | set_irq_flags(irq, IRQF_VALID); | 138 | set_irq_flags(irq, IRQF_VALID); |
139 | set_irq_handler(irq, handle_level_irq); | 139 | irq_set_chip_and_handler(irq, &ixdp2351_inta_chip, |
140 | set_irq_chip(irq, &ixdp2351_inta_chip); | 140 | handle_level_irq); |
141 | } | 141 | } |
142 | } | 142 | } |
143 | 143 | ||
@@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void) | |||
147 | irq++) { | 147 | irq++) { |
148 | if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { | 148 | if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { |
149 | set_irq_flags(irq, IRQF_VALID); | 149 | set_irq_flags(irq, IRQF_VALID); |
150 | set_irq_handler(irq, handle_level_irq); | 150 | irq_set_chip_and_handler(irq, &ixdp2351_intb_chip, |
151 | set_irq_chip(irq, &ixdp2351_intb_chip); | 151 | handle_level_irq); |
152 | } | 152 | } |
153 | } | 153 | } |
154 | 154 | ||
155 | set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); | 155 | irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); |
156 | set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); | 156 | irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); |
157 | } | 157 | } |
158 | 158 | ||
159 | /* | 159 | /* |
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c index 76c61ba73218..8fe0c6273262 100644 --- a/arch/arm/mach-ixp23xx/roadrunner.c +++ b/arch/arm/mach-ixp23xx/roadrunner.c | |||
@@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) | |||
110 | 110 | ||
111 | static void __init roadrunner_pci_preinit(void) | 111 | static void __init roadrunner_pci_preinit(void) |
112 | { | 112 | { |
113 | set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); | 113 | irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); |
114 | set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); | 114 | irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); |
115 | 115 | ||
116 | ixp23xx_pci_preinit(); | 116 | ixp23xx_pci_preinit(); |
117 | } | 117 | } |
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c index 845e1b500548..162043ff29ff 100644 --- a/arch/arm/mach-ixp4xx/avila-pci.c +++ b/arch/arm/mach-ixp4xx/avila-pci.c | |||
@@ -39,10 +39,10 @@ | |||
39 | 39 | ||
40 | void __init avila_pci_preinit(void) | 40 | void __init avila_pci_preinit(void) |
41 | { | 41 | { |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
43 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 43 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
44 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 44 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
45 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 45 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
46 | ixp4xx_pci_preinit(); | 46 | ixp4xx_pci_preinit(); |
47 | } | 47 | } |
48 | 48 | ||
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 9fd894271d5d..ed19bc314318 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c | |||
@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void) | |||
252 | 252 | ||
253 | /* Default to all level triggered */ | 253 | /* Default to all level triggered */ |
254 | for(i = 0; i < NR_IRQS; i++) { | 254 | for(i = 0; i < NR_IRQS; i++) { |
255 | set_irq_chip(i, &ixp4xx_irq_chip); | 255 | irq_set_chip_and_handler(i, &ixp4xx_irq_chip, |
256 | set_irq_handler(i, handle_level_irq); | 256 | handle_level_irq); |
257 | set_irq_flags(i, IRQF_VALID); | 257 | set_irq_flags(i, IRQF_VALID); |
258 | } | 258 | } |
259 | } | 259 | } |
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c index b978ea8bd6f0..37fda7d6e83d 100644 --- a/arch/arm/mach-ixp4xx/coyote-pci.c +++ b/arch/arm/mach-ixp4xx/coyote-pci.c | |||
@@ -32,8 +32,8 @@ | |||
32 | 32 | ||
33 | void __init coyote_pci_preinit(void) | 33 | void __init coyote_pci_preinit(void) |
34 | { | 34 | { |
35 | set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); | 35 | irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); |
37 | ixp4xx_pci_preinit(); | 37 | ixp4xx_pci_preinit(); |
38 | } | 38 | } |
39 | 39 | ||
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c index fa70fed462ba..c7612010b3fc 100644 --- a/arch/arm/mach-ixp4xx/dsmg600-pci.c +++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c | |||
@@ -35,12 +35,12 @@ | |||
35 | 35 | ||
36 | void __init dsmg600_pci_preinit(void) | 36 | void __init dsmg600_pci_preinit(void) |
37 | { | 37 | { |
38 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 38 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
39 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 39 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
40 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 40 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
41 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 41 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); |
43 | set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); | 43 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); |
44 | ixp4xx_pci_preinit(); | 44 | ixp4xx_pci_preinit(); |
45 | } | 45 | } |
46 | 46 | ||
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c index 5a810c930624..44ccde9d4879 100644 --- a/arch/arm/mach-ixp4xx/fsg-pci.c +++ b/arch/arm/mach-ixp4xx/fsg-pci.c | |||
@@ -32,9 +32,9 @@ | |||
32 | 32 | ||
33 | void __init fsg_pci_preinit(void) | 33 | void __init fsg_pci_preinit(void) |
34 | { | 34 | { |
35 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 35 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
37 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 37 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
38 | ixp4xx_pci_preinit(); | 38 | ixp4xx_pci_preinit(); |
39 | } | 39 | } |
40 | 40 | ||
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c index 7e93a0975c4d..fc1124168874 100644 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c | |||
@@ -29,8 +29,8 @@ | |||
29 | 29 | ||
30 | void __init gateway7001_pci_preinit(void) | 30 | void __init gateway7001_pci_preinit(void) |
31 | { | 31 | { |
32 | set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); | 32 | irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); | 33 | irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index d0e4861ac03d..3e8c0e33b59c 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c | |||
@@ -420,8 +420,8 @@ static void __init gmlr_init(void) | |||
420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); | 420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); |
421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); | 421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); |
422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); | 422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); |
423 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); | 423 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); |
424 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); | 424 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); |
425 | 425 | ||
426 | set_control(CONTROL_HSS0_DTR_N, 1); | 426 | set_control(CONTROL_HSS0_DTR_N, 1); |
427 | set_control(CONTROL_HSS1_DTR_N, 1); | 427 | set_control(CONTROL_HSS1_DTR_N, 1); |
@@ -441,10 +441,10 @@ static void __init gmlr_init(void) | |||
441 | #ifdef CONFIG_PCI | 441 | #ifdef CONFIG_PCI |
442 | static void __init gmlr_pci_preinit(void) | 442 | static void __init gmlr_pci_preinit(void) |
443 | { | 443 | { |
444 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); | 444 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); |
445 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); | 445 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); |
446 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); | 446 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); |
447 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); | 447 | irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); |
448 | ixp4xx_pci_preinit(); | 448 | ixp4xx_pci_preinit(); |
449 | } | 449 | } |
450 | 450 | ||
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c index 25d2c333c204..38cc0725dbd8 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c | |||
@@ -43,8 +43,8 @@ | |||
43 | */ | 43 | */ |
44 | void __init gtwx5715_pci_preinit(void) | 44 | void __init gtwx5715_pci_preinit(void) |
45 | { | 45 | { |
46 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 46 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
47 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 47 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
48 | ixp4xx_pci_preinit(); | 48 | ixp4xx_pci_preinit(); |
49 | } | 49 | } |
50 | 50 | ||
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c index 1ba165a6edac..58f400417eaf 100644 --- a/arch/arm/mach-ixp4xx/ixdp425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c | |||
@@ -36,10 +36,10 @@ | |||
36 | 36 | ||
37 | void __init ixdp425_pci_preinit(void) | 37 | void __init ixdp425_pci_preinit(void) |
38 | { | 38 | { |
39 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 39 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
40 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 40 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
41 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 41 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
43 | ixp4xx_pci_preinit(); | 43 | ixp4xx_pci_preinit(); |
44 | } | 44 | } |
45 | 45 | ||
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c index 4ed7ac614920..e64f6d041488 100644 --- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c +++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c | |||
@@ -25,8 +25,8 @@ | |||
25 | 25 | ||
26 | void __init ixdpg425_pci_preinit(void) | 26 | void __init ixdpg425_pci_preinit(void) |
27 | { | 27 | { |
28 | set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); | 28 | irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); |
29 | set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); | 29 | irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); |
30 | 30 | ||
31 | ixp4xx_pci_preinit(); | 31 | ixp4xx_pci_preinit(); |
32 | } | 32 | } |
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c index d0cea34cf61e..428d1202b799 100644 --- a/arch/arm/mach-ixp4xx/nas100d-pci.c +++ b/arch/arm/mach-ixp4xx/nas100d-pci.c | |||
@@ -33,11 +33,11 @@ | |||
33 | 33 | ||
34 | void __init nas100d_pci_preinit(void) | 34 | void __init nas100d_pci_preinit(void) |
35 | { | 35 | { |
36 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
37 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 37 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
38 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 38 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
39 | set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | 39 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); |
40 | set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | 40 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); |
41 | ixp4xx_pci_preinit(); | 41 | ixp4xx_pci_preinit(); |
42 | } | 42 | } |
43 | 43 | ||
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c index 1eb5a90470bc..2e85f76b950d 100644 --- a/arch/arm/mach-ixp4xx/nslu2-pci.c +++ b/arch/arm/mach-ixp4xx/nslu2-pci.c | |||
@@ -32,9 +32,9 @@ | |||
32 | 32 | ||
33 | void __init nslu2_pci_preinit(void) | 33 | void __init nslu2_pci_preinit(void) |
34 | { | 34 | { |
35 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 35 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
36 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 36 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
37 | set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | 37 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); |
38 | ixp4xx_pci_preinit(); | 38 | ixp4xx_pci_preinit(); |
39 | } | 39 | } |
40 | 40 | ||
diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c index f3111c6840ef..03bdec5140a7 100644 --- a/arch/arm/mach-ixp4xx/vulcan-pci.c +++ b/arch/arm/mach-ixp4xx/vulcan-pci.c | |||
@@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void) | |||
38 | pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", | 38 | pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", |
39 | (int)(pci_cardbus_mem_size >> 20)); | 39 | (int)(pci_cardbus_mem_size >> 20)); |
40 | #endif | 40 | #endif |
41 | set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); | 41 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
42 | set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | 42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); |
43 | ixp4xx_pci_preinit(); | 43 | ixp4xx_pci_preinit(); |
44 | } | 44 | } |
45 | 45 | ||
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c index 9b59ed03b151..17f3cf59a31b 100644 --- a/arch/arm/mach-ixp4xx/wg302v2-pci.c +++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c | |||
@@ -29,8 +29,8 @@ | |||
29 | 29 | ||
30 | void __init wg302v2_pci_preinit(void) | 30 | void __init wg302v2_pci_preinit(void) |
31 | { | 31 | { |
32 | set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); | 32 | irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); |
33 | set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); | 33 | irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); |
34 | 34 | ||
35 | ixp4xx_pci_preinit(); | 35 | ixp4xx_pci_preinit(); |
36 | } | 36 | } |
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c index cbdb5863d13b..05d193a25b25 100644 --- a/arch/arm/mach-kirkwood/irq.c +++ b/arch/arm/mach-kirkwood/irq.c | |||
@@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void) | |||
35 | */ | 35 | */ |
36 | orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, | 36 | orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, |
37 | IRQ_KIRKWOOD_GPIO_START); | 37 | IRQ_KIRKWOOD_GPIO_START); |
38 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); | 38 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); |
39 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); | 39 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); |
40 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); | 40 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); |
41 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); | 41 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); |
42 | 42 | ||
43 | orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, | 43 | orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, |
44 | IRQ_KIRKWOOD_GPIO_START + 32); | 44 | IRQ_KIRKWOOD_GPIO_START + 32); |
45 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); | 45 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); |
46 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); | 46 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); |
47 | set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); | 47 | irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, |
48 | gpio_irq_handler); | ||
48 | } | 49 | } |
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index 0a95063f6d32..17de0bf53c08 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c | |||
@@ -58,6 +58,12 @@ static struct mvsdio_platform_data sheeva_esata_mvsdio_data = { | |||
58 | 58 | ||
59 | static struct gpio_led sheevaplug_led_pins[] = { | 59 | static struct gpio_led sheevaplug_led_pins[] = { |
60 | { | 60 | { |
61 | .name = "plug:red:misc", | ||
62 | .default_trigger = "none", | ||
63 | .gpio = 46, | ||
64 | .active_low = 1, | ||
65 | }, | ||
66 | { | ||
61 | .name = "plug:green:health", | 67 | .name = "plug:green:health", |
62 | .default_trigger = "default-on", | 68 | .default_trigger = "default-on", |
63 | .gpio = 49, | 69 | .gpio = 49, |
@@ -80,6 +86,7 @@ static struct platform_device sheevaplug_leds = { | |||
80 | 86 | ||
81 | static unsigned int sheevaplug_mpp_config[] __initdata = { | 87 | static unsigned int sheevaplug_mpp_config[] __initdata = { |
82 | MPP29_GPIO, /* USB Power Enable */ | 88 | MPP29_GPIO, /* USB Power Enable */ |
89 | MPP46_GPIO, /* LED Red */ | ||
83 | MPP49_GPIO, /* LED */ | 90 | MPP49_GPIO, /* LED */ |
84 | 0 | 91 | 0 |
85 | }; | 92 | }; |
diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c index 55fbf7111a5b..31e456508a6f 100644 --- a/arch/arm/mach-ks8695/gpio.c +++ b/arch/arm/mach-ks8695/gpio.c | |||
@@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) | |||
80 | local_irq_restore(flags); | 80 | local_irq_restore(flags); |
81 | 81 | ||
82 | /* Set IRQ triggering type */ | 82 | /* Set IRQ triggering type */ |
83 | set_irq_type(gpio_irq[pin], type); | 83 | irq_set_irq_type(gpio_irq[pin], type); |
84 | 84 | ||
85 | /* enable interrupt mode */ | 85 | /* enable interrupt mode */ |
86 | ks8695_gpio_mode(pin, 0); | 86 | ks8695_gpio_mode(pin, 0); |
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c index 7998ccaa6333..a78092dcd6fb 100644 --- a/arch/arm/mach-ks8695/irq.c +++ b/arch/arm/mach-ks8695/irq.c | |||
@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) | |||
115 | } | 115 | } |
116 | 116 | ||
117 | if (level_triggered) { | 117 | if (level_triggered) { |
118 | set_irq_chip(d->irq, &ks8695_irq_level_chip); | 118 | irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip, |
119 | set_irq_handler(d->irq, handle_level_irq); | 119 | handle_level_irq); |
120 | } | 120 | } |
121 | else { | 121 | else { |
122 | set_irq_chip(d->irq, &ks8695_irq_edge_chip); | 122 | irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip, |
123 | set_irq_handler(d->irq, handle_edge_irq); | 123 | handle_edge_irq); |
124 | } | 124 | } |
125 | 125 | ||
126 | __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); | 126 | __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); |
@@ -158,16 +158,18 @@ void __init ks8695_init_irq(void) | |||
158 | case KS8695_IRQ_UART_RX: | 158 | case KS8695_IRQ_UART_RX: |
159 | case KS8695_IRQ_COMM_TX: | 159 | case KS8695_IRQ_COMM_TX: |
160 | case KS8695_IRQ_COMM_RX: | 160 | case KS8695_IRQ_COMM_RX: |
161 | set_irq_chip(irq, &ks8695_irq_level_chip); | 161 | irq_set_chip_and_handler(irq, |
162 | set_irq_handler(irq, handle_level_irq); | 162 | &ks8695_irq_level_chip, |
163 | handle_level_irq); | ||
163 | break; | 164 | break; |
164 | 165 | ||
165 | /* Edge-triggered interrupts */ | 166 | /* Edge-triggered interrupts */ |
166 | default: | 167 | default: |
167 | /* clear pending bit */ | 168 | /* clear pending bit */ |
168 | ks8695_irq_ack(irq_get_irq_data(irq)); | 169 | ks8695_irq_ack(irq_get_irq_data(irq)); |
169 | set_irq_chip(irq, &ks8695_irq_edge_chip); | 170 | irq_set_chip_and_handler(irq, |
170 | set_irq_handler(irq, handle_edge_irq); | 171 | &ks8695_irq_edge_chip, |
172 | handle_edge_irq); | ||
171 | } | 173 | } |
172 | 174 | ||
173 | set_irq_flags(irq, IRQF_VALID); | 175 | set_irq_flags(irq, IRQF_VALID); |
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 316ecbf6c586..4eae566dfdc7 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c | |||
@@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) | |||
290 | } | 290 | } |
291 | 291 | ||
292 | /* Ok to use the level handler for all types */ | 292 | /* Ok to use the level handler for all types */ |
293 | set_irq_handler(d->irq, handle_level_irq); | 293 | irq_set_handler(d->irq, handle_level_irq); |
294 | 294 | ||
295 | return 0; | 295 | return 0; |
296 | } | 296 | } |
@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void) | |||
390 | 390 | ||
391 | /* Configure supported IRQ's */ | 391 | /* Configure supported IRQ's */ |
392 | for (i = 0; i < NR_IRQS; i++) { | 392 | for (i = 0; i < NR_IRQS; i++) { |
393 | set_irq_chip(i, &lpc32xx_irq_chip); | 393 | irq_set_chip_and_handler(i, &lpc32xx_irq_chip, |
394 | set_irq_handler(i, handle_level_irq); | 394 | handle_level_irq); |
395 | set_irq_flags(i, IRQF_VALID); | 395 | set_irq_flags(i, IRQF_VALID); |
396 | } | 396 | } |
397 | 397 | ||
@@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void) | |||
406 | __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); | 406 | __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); |
407 | 407 | ||
408 | /* MIC SUBIRQx interrupts will route handling to the chain handlers */ | 408 | /* MIC SUBIRQx interrupts will route handling to the chain handlers */ |
409 | set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); | 409 | irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); |
410 | set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); | 410 | irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); |
411 | 411 | ||
412 | /* Initially disable all wake events */ | 412 | /* Initially disable all wake events */ |
413 | __raw_writel(0, LPC32XX_CLKPWR_P01_ER); | 413 | __raw_writel(0, LPC32XX_CLKPWR_P01_ER); |
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index fa037038e7b8..d21c5441a3d0 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c | |||
@@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) | |||
110 | if (chip->irq_ack) | 110 | if (chip->irq_ack) |
111 | chip->irq_ack(d); | 111 | chip->irq_ack(d); |
112 | 112 | ||
113 | set_irq_chip(irq, chip); | 113 | irq_set_chip(irq, chip); |
114 | set_irq_flags(irq, IRQF_VALID); | 114 | set_irq_flags(irq, IRQF_VALID); |
115 | set_irq_handler(irq, handle_level_irq); | 115 | irq_set_handler(irq, handle_level_irq); |
116 | } | 116 | } |
117 | } | 117 | } |
118 | 118 | ||
@@ -122,7 +122,7 @@ void __init mmp2_init_icu(void) | |||
122 | 122 | ||
123 | for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { | 123 | for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { |
124 | icu_mask_irq(irq_get_irq_data(irq)); | 124 | icu_mask_irq(irq_get_irq_data(irq)); |
125 | set_irq_chip(irq, &icu_irq_chip); | 125 | irq_set_chip(irq, &icu_irq_chip); |
126 | set_irq_flags(irq, IRQF_VALID); | 126 | set_irq_flags(irq, IRQF_VALID); |
127 | 127 | ||
128 | switch (irq) { | 128 | switch (irq) { |
@@ -133,7 +133,7 @@ void __init mmp2_init_icu(void) | |||
133 | case IRQ_MMP2_SSP_MUX: | 133 | case IRQ_MMP2_SSP_MUX: |
134 | break; | 134 | break; |
135 | default: | 135 | default: |
136 | set_irq_handler(irq, handle_level_irq); | 136 | irq_set_handler(irq, handle_level_irq); |
137 | break; | 137 | break; |
138 | } | 138 | } |
139 | } | 139 | } |
@@ -149,9 +149,9 @@ void __init mmp2_init_icu(void) | |||
149 | init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); | 149 | init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); |
150 | init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); | 150 | init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); |
151 | 151 | ||
152 | set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); | 152 | irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); |
153 | set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); | 153 | irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); |
154 | set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); | 154 | irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); |
155 | set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); | 155 | irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); |
156 | set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); | 156 | irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); |
157 | } | 157 | } |
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c index f86b450cb93c..89706a0d08f1 100644 --- a/arch/arm/mach-mmp/irq-pxa168.c +++ b/arch/arm/mach-mmp/irq-pxa168.c | |||
@@ -48,8 +48,7 @@ void __init icu_init_irq(void) | |||
48 | 48 | ||
49 | for (irq = 0; irq < 64; irq++) { | 49 | for (irq = 0; irq < 64; irq++) { |
50 | icu_mask_irq(irq_get_irq_data(irq)); | 50 | icu_mask_irq(irq_get_irq_data(irq)); |
51 | set_irq_chip(irq, &icu_irq_chip); | 51 | irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); |
52 | set_irq_handler(irq, handle_level_irq); | ||
53 | set_irq_flags(irq, IRQF_VALID); | 52 | set_irq_flags(irq, IRQF_VALID); |
54 | } | 53 | } |
55 | } | 54 | } |
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 1993721d472e..35c7ceeb3f29 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c | |||
@@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void) | |||
53 | */ | 53 | */ |
54 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { | 54 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { |
55 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) | 55 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) |
56 | set_irq_handler(i, handle_percpu_irq); | 56 | irq_set_handler(i, handle_percpu_irq); |
57 | } | 57 | } |
58 | } | 58 | } |
59 | 59 | ||
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index b3c55f138fce..1163b6fd05d2 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c | |||
@@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void) | |||
56 | */ | 56 | */ |
57 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { | 57 | for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { |
58 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) | 58 | if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) |
59 | set_irq_handler(i, handle_percpu_irq); | 59 | irq_set_handler(i, handle_percpu_irq); |
60 | } | 60 | } |
61 | } | 61 | } |
62 | 62 | ||
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c index 31117a4499c4..87e1d01edecc 100644 --- a/arch/arm/mach-msm/board-trout-gpio.c +++ b/arch/arm/mach-msm/board-trout-gpio.c | |||
@@ -214,17 +214,17 @@ int __init trout_init_gpio(void) | |||
214 | { | 214 | { |
215 | int i; | 215 | int i; |
216 | for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { | 216 | for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { |
217 | set_irq_chip(i, &trout_gpio_irq_chip); | 217 | irq_set_chip_and_handler(i, &trout_gpio_irq_chip, |
218 | set_irq_handler(i, handle_edge_irq); | 218 | handle_edge_irq); |
219 | set_irq_flags(i, IRQF_VALID); | 219 | set_irq_flags(i, IRQF_VALID); |
220 | } | 220 | } |
221 | 221 | ||
222 | for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) | 222 | for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) |
223 | gpiochip_add(&msm_gpio_banks[i].chip); | 223 | gpiochip_add(&msm_gpio_banks[i].chip); |
224 | 224 | ||
225 | set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); | 225 | irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); |
226 | set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); | 226 | irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); |
227 | set_irq_wake(MSM_GPIO_TO_INT(17), 1); | 227 | irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1); |
228 | 228 | ||
229 | return 0; | 229 | return 0; |
230 | } | 230 | } |
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c index 44be8464657b..f7a9724788b0 100644 --- a/arch/arm/mach-msm/board-trout-mmc.c +++ b/arch/arm/mach-msm/board-trout-mmc.c | |||
@@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev) | |||
174 | if (IS_ERR(vreg_sdslot)) | 174 | if (IS_ERR(vreg_sdslot)) |
175 | return PTR_ERR(vreg_sdslot); | 175 | return PTR_ERR(vreg_sdslot); |
176 | 176 | ||
177 | set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); | 177 | irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); |
178 | 178 | ||
179 | if (!opt_disable_sdcard) | 179 | if (!opt_disable_sdcard) |
180 | msm_add_sdcc(2, &trout_sdslot_data, | 180 | msm_add_sdcc(2, &trout_sdslot_data, |
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c index 0de19ec74e34..56a964e52ad3 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/arch/arm/mach-msm/gpio-v2.c | |||
@@ -230,18 +230,18 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio) | |||
230 | val, val2); | 230 | val, val2); |
231 | } | 231 | } |
232 | 232 | ||
233 | static void msm_gpio_irq_ack(unsigned int irq) | 233 | static void msm_gpio_irq_ack(struct irq_data *d) |
234 | { | 234 | { |
235 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | 235 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); |
236 | 236 | ||
237 | writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); | 237 | writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); |
238 | if (test_bit(gpio, msm_gpio.dual_edge_irqs)) | 238 | if (test_bit(gpio, msm_gpio.dual_edge_irqs)) |
239 | msm_gpio_update_dual_edge_pos(gpio); | 239 | msm_gpio_update_dual_edge_pos(gpio); |
240 | } | 240 | } |
241 | 241 | ||
242 | static void msm_gpio_irq_mask(unsigned int irq) | 242 | static void msm_gpio_irq_mask(struct irq_data *d) |
243 | { | 243 | { |
244 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | 244 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); |
245 | unsigned long irq_flags; | 245 | unsigned long irq_flags; |
246 | 246 | ||
247 | spin_lock_irqsave(&tlmm_lock, irq_flags); | 247 | spin_lock_irqsave(&tlmm_lock, irq_flags); |
@@ -251,9 +251,9 @@ static void msm_gpio_irq_mask(unsigned int irq) | |||
251 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | 251 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
252 | } | 252 | } |
253 | 253 | ||
254 | static void msm_gpio_irq_unmask(unsigned int irq) | 254 | static void msm_gpio_irq_unmask(struct irq_data *d) |
255 | { | 255 | { |
256 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | 256 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); |
257 | unsigned long irq_flags; | 257 | unsigned long irq_flags; |
258 | 258 | ||
259 | spin_lock_irqsave(&tlmm_lock, irq_flags); | 259 | spin_lock_irqsave(&tlmm_lock, irq_flags); |
@@ -263,9 +263,9 @@ static void msm_gpio_irq_unmask(unsigned int irq) | |||
263 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); | 263 | spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
264 | } | 264 | } |
265 | 265 | ||
266 | static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) | 266 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) |
267 | { | 267 | { |
268 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | 268 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); |
269 | unsigned long irq_flags; | 269 | unsigned long irq_flags; |
270 | uint32_t bits; | 270 | uint32_t bits; |
271 | 271 | ||
@@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) | |||
275 | 275 | ||
276 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { | 276 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { |
277 | bits |= BIT(INTR_DECT_CTL); | 277 | bits |= BIT(INTR_DECT_CTL); |
278 | irq_desc[irq].handle_irq = handle_edge_irq; | 278 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
279 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) | 279 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) |
280 | __set_bit(gpio, msm_gpio.dual_edge_irqs); | 280 | __set_bit(gpio, msm_gpio.dual_edge_irqs); |
281 | else | 281 | else |
282 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); | 282 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); |
283 | } else { | 283 | } else { |
284 | bits &= ~BIT(INTR_DECT_CTL); | 284 | bits &= ~BIT(INTR_DECT_CTL); |
285 | irq_desc[irq].handle_irq = handle_level_irq; | 285 | __irq_set_handler_locked(d->irq, handle_level_irq); |
286 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); | 286 | __clear_bit(gpio, msm_gpio.dual_edge_irqs); |
287 | } | 287 | } |
288 | 288 | ||
@@ -309,6 +309,7 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) | |||
309 | */ | 309 | */ |
310 | static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) | 310 | static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) |
311 | { | 311 | { |
312 | struct irq_data *data = irq_desc_get_irq_data(desc); | ||
312 | unsigned long i; | 313 | unsigned long i; |
313 | 314 | ||
314 | for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); | 315 | for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); |
@@ -318,21 +319,21 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
318 | generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, | 319 | generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, |
319 | i)); | 320 | i)); |
320 | } | 321 | } |
321 | desc->chip->ack(irq); | 322 | data->chip->irq_ack(data); |
322 | } | 323 | } |
323 | 324 | ||
324 | static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) | 325 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
325 | { | 326 | { |
326 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); | 327 | int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq); |
327 | 328 | ||
328 | if (on) { | 329 | if (on) { |
329 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | 330 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) |
330 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); | 331 | irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); |
331 | set_bit(gpio, msm_gpio.wake_irqs); | 332 | set_bit(gpio, msm_gpio.wake_irqs); |
332 | } else { | 333 | } else { |
333 | clear_bit(gpio, msm_gpio.wake_irqs); | 334 | clear_bit(gpio, msm_gpio.wake_irqs); |
334 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) | 335 | if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) |
335 | set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); | 336 | irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); |
336 | } | 337 | } |
337 | 338 | ||
338 | return 0; | 339 | return 0; |
@@ -340,11 +341,11 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) | |||
340 | 341 | ||
341 | static struct irq_chip msm_gpio_irq_chip = { | 342 | static struct irq_chip msm_gpio_irq_chip = { |
342 | .name = "msmgpio", | 343 | .name = "msmgpio", |
343 | .mask = msm_gpio_irq_mask, | 344 | .irq_mask = msm_gpio_irq_mask, |
344 | .unmask = msm_gpio_irq_unmask, | 345 | .irq_unmask = msm_gpio_irq_unmask, |
345 | .ack = msm_gpio_irq_ack, | 346 | .irq_ack = msm_gpio_irq_ack, |
346 | .set_type = msm_gpio_irq_set_type, | 347 | .irq_set_type = msm_gpio_irq_set_type, |
347 | .set_wake = msm_gpio_irq_set_wake, | 348 | .irq_set_wake = msm_gpio_irq_set_wake, |
348 | }; | 349 | }; |
349 | 350 | ||
350 | static int __devinit msm_gpio_probe(struct platform_device *dev) | 351 | static int __devinit msm_gpio_probe(struct platform_device *dev) |
@@ -361,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev) | |||
361 | 362 | ||
362 | for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { | 363 | for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { |
363 | irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); | 364 | irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); |
364 | set_irq_chip(irq, &msm_gpio_irq_chip); | 365 | irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, |
365 | set_irq_handler(irq, handle_level_irq); | 366 | handle_level_irq); |
366 | set_irq_flags(irq, IRQF_VALID); | 367 | set_irq_flags(irq, IRQF_VALID); |
367 | } | 368 | } |
368 | 369 | ||
369 | set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, | 370 | irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ, |
370 | msm_summary_irq_handler); | 371 | msm_summary_irq_handler); |
371 | return 0; | 372 | return 0; |
372 | } | 373 | } |
@@ -378,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev) | |||
378 | if (ret < 0) | 379 | if (ret < 0) |
379 | return ret; | 380 | return ret; |
380 | 381 | ||
381 | set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); | 382 | irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); |
382 | 383 | ||
383 | return 0; | 384 | return 0; |
384 | } | 385 | } |
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 176af9dcb8ee..5ea273b00da8 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c | |||
@@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) | |||
293 | val = readl(msm_chip->regs.int_edge); | 293 | val = readl(msm_chip->regs.int_edge); |
294 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { | 294 | if (flow_type & IRQ_TYPE_EDGE_BOTH) { |
295 | writel(val | mask, msm_chip->regs.int_edge); | 295 | writel(val | mask, msm_chip->regs.int_edge); |
296 | irq_desc[d->irq].handle_irq = handle_edge_irq; | 296 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
297 | } else { | 297 | } else { |
298 | writel(val & ~mask, msm_chip->regs.int_edge); | 298 | writel(val & ~mask, msm_chip->regs.int_edge); |
299 | irq_desc[d->irq].handle_irq = handle_level_irq; | 299 | __irq_set_handler_locked(d->irq, handle_level_irq); |
300 | } | 300 | } |
301 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | 301 | if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { |
302 | msm_chip->both_edge_detect |= mask; | 302 | msm_chip->both_edge_detect |= mask; |
@@ -354,9 +354,9 @@ static int __init msm_init_gpio(void) | |||
354 | msm_gpio_chips[j].chip.base + | 354 | msm_gpio_chips[j].chip.base + |
355 | msm_gpio_chips[j].chip.ngpio) | 355 | msm_gpio_chips[j].chip.ngpio) |
356 | j++; | 356 | j++; |
357 | set_irq_chip_data(i, &msm_gpio_chips[j]); | 357 | irq_set_chip_data(i, &msm_gpio_chips[j]); |
358 | set_irq_chip(i, &msm_gpio_irq_chip); | 358 | irq_set_chip_and_handler(i, &msm_gpio_irq_chip, |
359 | set_irq_handler(i, handle_edge_irq); | 359 | handle_edge_irq); |
360 | set_irq_flags(i, IRQF_VALID); | 360 | set_irq_flags(i, IRQF_VALID); |
361 | } | 361 | } |
362 | 362 | ||
@@ -366,10 +366,10 @@ static int __init msm_init_gpio(void) | |||
366 | gpiochip_add(&msm_gpio_chips[i].chip); | 366 | gpiochip_add(&msm_gpio_chips[i].chip); |
367 | } | 367 | } |
368 | 368 | ||
369 | set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); | 369 | irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); |
370 | set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); | 370 | irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); |
371 | set_irq_wake(INT_GPIO_GROUP1, 1); | 371 | irq_set_irq_wake(INT_GPIO_GROUP1, 1); |
372 | set_irq_wake(INT_GPIO_GROUP2, 2); | 372 | irq_set_irq_wake(INT_GPIO_GROUP2, 2); |
373 | return 0; | 373 | return 0; |
374 | } | 374 | } |
375 | 375 | ||
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c index 68c28bbdc969..1b54f807c2d0 100644 --- a/arch/arm/mach-msm/irq-vic.c +++ b/arch/arm/mach-msm/irq-vic.c | |||
@@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) | |||
313 | type = msm_irq_shadow_reg[index].int_type; | 313 | type = msm_irq_shadow_reg[index].int_type; |
314 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { | 314 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { |
315 | type |= b; | 315 | type |= b; |
316 | irq_desc[d->irq].handle_irq = handle_edge_irq; | 316 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
317 | } | 317 | } |
318 | if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { | 318 | if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { |
319 | type &= ~b; | 319 | type &= ~b; |
320 | irq_desc[d->irq].handle_irq = handle_level_irq; | 320 | __irq_set_handler_locked(d->irq, handle_level_irq); |
321 | } | 321 | } |
322 | writel(type, treg); | 322 | writel(type, treg); |
323 | msm_irq_shadow_reg[index].int_type = type; | 323 | msm_irq_shadow_reg[index].int_type = type; |
@@ -357,8 +357,7 @@ void __init msm_init_irq(void) | |||
357 | writel(3, VIC_INT_MASTEREN); | 357 | writel(3, VIC_INT_MASTEREN); |
358 | 358 | ||
359 | for (n = 0; n < NR_MSM_IRQS; n++) { | 359 | for (n = 0; n < NR_MSM_IRQS; n++) { |
360 | set_irq_chip(n, &msm_irq_chip); | 360 | irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); |
361 | set_irq_handler(n, handle_level_irq); | ||
362 | set_irq_flags(n, IRQF_VALID); | 361 | set_irq_flags(n, IRQF_VALID); |
363 | } | 362 | } |
364 | } | 363 | } |
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c index 0b27d899f40e..ea514be390c6 100644 --- a/arch/arm/mach-msm/irq.c +++ b/arch/arm/mach-msm/irq.c | |||
@@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) | |||
100 | 100 | ||
101 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { | 101 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { |
102 | writel(readl(treg) | b, treg); | 102 | writel(readl(treg) | b, treg); |
103 | irq_desc[d->irq].handle_irq = handle_edge_irq; | 103 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
104 | } | 104 | } |
105 | if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { | 105 | if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { |
106 | writel(readl(treg) & (~b), treg); | 106 | writel(readl(treg) & (~b), treg); |
107 | irq_desc[d->irq].handle_irq = handle_level_irq; | 107 | __irq_set_handler_locked(d->irq, handle_level_irq); |
108 | } | 108 | } |
109 | return 0; | 109 | return 0; |
110 | } | 110 | } |
@@ -145,8 +145,7 @@ void __init msm_init_irq(void) | |||
145 | writel(1, VIC_INT_MASTEREN); | 145 | writel(1, VIC_INT_MASTEREN); |
146 | 146 | ||
147 | for (n = 0; n < NR_MSM_IRQS; n++) { | 147 | for (n = 0; n < NR_MSM_IRQS; n++) { |
148 | set_irq_chip(n, &msm_irq_chip); | 148 | irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq); |
149 | set_irq_handler(n, handle_level_irq); | ||
150 | set_irq_flags(n, IRQF_VALID); | 149 | set_irq_flags(n, IRQF_VALID); |
151 | } | 150 | } |
152 | } | 151 | } |
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c index 11b54c7aeb09..689e78c95f38 100644 --- a/arch/arm/mach-msm/sirc.c +++ b/arch/arm/mach-msm/sirc.c | |||
@@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) | |||
105 | val = readl(sirc_regs.int_type); | 105 | val = readl(sirc_regs.int_type); |
106 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { | 106 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { |
107 | val |= mask; | 107 | val |= mask; |
108 | irq_desc[d->irq].handle_irq = handle_edge_irq; | 108 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
109 | } else { | 109 | } else { |
110 | val &= ~mask; | 110 | val &= ~mask; |
111 | irq_desc[d->irq].handle_irq = handle_level_irq; | 111 | __irq_set_handler_locked(d->irq, handle_level_irq); |
112 | } | 112 | } |
113 | 113 | ||
114 | writel(val, sirc_regs.int_type); | 114 | writel(val, sirc_regs.int_type); |
@@ -158,15 +158,14 @@ void __init msm_init_sirc(void) | |||
158 | wake_enable = 0; | 158 | wake_enable = 0; |
159 | 159 | ||
160 | for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { | 160 | for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { |
161 | set_irq_chip(i, &sirc_irq_chip); | 161 | irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq); |
162 | set_irq_handler(i, handle_edge_irq); | ||
163 | set_irq_flags(i, IRQF_VALID); | 162 | set_irq_flags(i, IRQF_VALID); |
164 | } | 163 | } |
165 | 164 | ||
166 | for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { | 165 | for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { |
167 | set_irq_chained_handler(sirc_reg_table[i].cascade_irq, | 166 | irq_set_chained_handler(sirc_reg_table[i].cascade_irq, |
168 | sirc_irq_handler); | 167 | sirc_irq_handler); |
169 | set_irq_wake(sirc_reg_table[i].cascade_irq, 1); | 168 | irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1); |
170 | } | 169 | } |
171 | return; | 170 | return; |
172 | } | 171 | } |
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 08da497c39c2..3e24431bb5ea 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c | |||
@@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void) | |||
38 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, | 38 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, |
39 | mv78xx0_core_index() ? 0x18 : 0, | 39 | mv78xx0_core_index() ? 0x18 : 0, |
40 | IRQ_MV78XX0_GPIO_START); | 40 | IRQ_MV78XX0_GPIO_START); |
41 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); | 41 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); |
42 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); | 42 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); |
43 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); | 43 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); |
44 | set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); | 44 | irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); |
45 | } | 45 | } |
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c index 80761474c0f8..2e288b38b4ad 100644 --- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c | |||
@@ -43,6 +43,7 @@ | |||
43 | #include <mach/ipu.h> | 43 | #include <mach/ipu.h> |
44 | #include <mach/mx3fb.h> | 44 | #include <mach/mx3fb.h> |
45 | #include <mach/audmux.h> | 45 | #include <mach/audmux.h> |
46 | #include <mach/esdhc.h> | ||
46 | 47 | ||
47 | #include "devices-imx35.h" | 48 | #include "devices-imx35.h" |
48 | #include "devices.h" | 49 | #include "devices.h" |
@@ -163,11 +164,14 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { | |||
163 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, | 164 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, |
164 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, | 165 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, |
165 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, | 166 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, |
167 | /* SD1 CD */ | ||
168 | MX35_PAD_LD18__GPIO3_24, | ||
166 | }; | 169 | }; |
167 | 170 | ||
168 | #define GPIO_LED1 IMX_GPIO_NR(3, 29) | 171 | #define GPIO_LED1 IMX_GPIO_NR(3, 29) |
169 | #define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) | 172 | #define GPIO_SWITCH1 IMX_GPIO_NR(3, 25) |
170 | #define GPIO_LCDPWR (4) | 173 | #define GPIO_LCDPWR IMX_GPIO_NR(1, 4) |
174 | #define GPIO_SD1CD IMX_GPIO_NR(3, 24) | ||
171 | 175 | ||
172 | static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, | 176 | static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, |
173 | unsigned int power) | 177 | unsigned int power) |
@@ -254,6 +258,11 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = { | |||
254 | .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, | 258 | .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, |
255 | }; | 259 | }; |
256 | 260 | ||
261 | static struct esdhc_platform_data sd1_pdata = { | ||
262 | .cd_gpio = GPIO_SD1CD, | ||
263 | .wp_gpio = -EINVAL, | ||
264 | }; | ||
265 | |||
257 | /* | 266 | /* |
258 | * system init for baseboard usage. Will be called by cpuimx35 init. | 267 | * system init for baseboard usage. Will be called by cpuimx35 init. |
259 | * | 268 | * |
@@ -289,7 +298,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void) | |||
289 | imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); | 298 | imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); |
290 | 299 | ||
291 | imx35_add_flexcan1(NULL); | 300 | imx35_add_flexcan1(NULL); |
292 | imx35_add_sdhci_esdhc_imx(0, NULL); | 301 | imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); |
293 | 302 | ||
294 | gpio_request(GPIO_LED1, "LED1"); | 303 | gpio_request(GPIO_LED1, "LED1"); |
295 | gpio_direction_output(GPIO_LED1, 1); | 304 | gpio_direction_output(GPIO_LED1, 1); |
@@ -301,7 +310,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void) | |||
301 | 310 | ||
302 | gpio_request(GPIO_LCDPWR, "LCDPWR"); | 311 | gpio_request(GPIO_LCDPWR, "LCDPWR"); |
303 | gpio_direction_output(GPIO_LCDPWR, 1); | 312 | gpio_direction_output(GPIO_LCDPWR, 1); |
304 | gpio_free(GPIO_LCDPWR); | ||
305 | 313 | ||
306 | i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, | 314 | i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, |
307 | ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); | 315 | ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); |
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 4e4b780c481d..3d095d69bc68 100644 --- a/arch/arm/mach-mx3/mach-mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c | |||
@@ -199,12 +199,11 @@ static void __init mx31ads_init_expio(void) | |||
199 | __raw_writew(0xFFFF, PBC_INTSTATUS_REG); | 199 | __raw_writew(0xFFFF, PBC_INTSTATUS_REG); |
200 | for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); | 200 | for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); |
201 | i++) { | 201 | i++) { |
202 | set_irq_chip(i, &expio_irq_chip); | 202 | irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); |
203 | set_irq_handler(i, handle_level_irq); | ||
204 | set_irq_flags(i, IRQF_VALID); | 203 | set_irq_flags(i, IRQF_VALID); |
205 | } | 204 | } |
206 | set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); | 205 | irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); |
207 | set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); | 206 | irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); |
208 | } | 207 | } |
209 | 208 | ||
210 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | 209 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 |
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index b3ecfb22d241..036ba1a4704b 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <mach/mx3fb.h> | 40 | #include <mach/mx3fb.h> |
41 | #include <mach/ulpi.h> | 41 | #include <mach/ulpi.h> |
42 | #include <mach/audmux.h> | 42 | #include <mach/audmux.h> |
43 | #include <mach/esdhc.h> | ||
43 | 44 | ||
44 | #include "devices-imx35.h" | 45 | #include "devices-imx35.h" |
45 | #include "devices.h" | 46 | #include "devices.h" |
@@ -217,11 +218,15 @@ static iomux_v3_cfg_t pcm043_pads[] = { | |||
217 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, | 218 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, |
218 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, | 219 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, |
219 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, | 220 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, |
221 | MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */ | ||
222 | MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */ | ||
220 | }; | 223 | }; |
221 | 224 | ||
222 | #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) | 225 | #define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) |
223 | #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) | 226 | #define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) |
224 | #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) | 227 | #define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) |
228 | #define SD1_GPIO_WP IMX_GPIO_NR(2, 23) | ||
229 | #define SD1_GPIO_CD IMX_GPIO_NR(2, 24) | ||
225 | 230 | ||
226 | static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) | 231 | static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) |
227 | { | 232 | { |
@@ -346,6 +351,11 @@ static int __init pcm043_otg_mode(char *options) | |||
346 | } | 351 | } |
347 | __setup("otg_mode=", pcm043_otg_mode); | 352 | __setup("otg_mode=", pcm043_otg_mode); |
348 | 353 | ||
354 | static struct esdhc_platform_data sd1_pdata = { | ||
355 | .wp_gpio = SD1_GPIO_WP, | ||
356 | .cd_gpio = SD1_GPIO_CD, | ||
357 | }; | ||
358 | |||
349 | /* | 359 | /* |
350 | * Board specific initialization. | 360 | * Board specific initialization. |
351 | */ | 361 | */ |
@@ -395,7 +405,7 @@ static void __init pcm043_init(void) | |||
395 | imx35_add_fsl_usb2_udc(&otg_device_pdata); | 405 | imx35_add_fsl_usb2_udc(&otg_device_pdata); |
396 | 406 | ||
397 | imx35_add_flexcan1(NULL); | 407 | imx35_add_flexcan1(NULL); |
398 | imx35_add_sdhci_esdhc_imx(0, NULL); | 408 | imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); |
399 | } | 409 | } |
400 | 410 | ||
401 | static void __init pcm043_timer_init(void) | 411 | static void __init pcm043_timer_init(void) |
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 83ee08847d4d..159340da9191 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig | |||
@@ -165,6 +165,7 @@ config MACH_MX53_LOCO | |||
165 | select IMX_HAVE_PLATFORM_IMX_I2C | 165 | select IMX_HAVE_PLATFORM_IMX_I2C |
166 | select IMX_HAVE_PLATFORM_IMX_UART | 166 | select IMX_HAVE_PLATFORM_IMX_UART |
167 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 167 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
168 | select IMX_HAVE_PLATFORM_GPIO_KEYS | ||
168 | help | 169 | help |
169 | Include support for MX53 LOCO platform. This includes specific | 170 | Include support for MX53 LOCO platform. This includes specific |
170 | configurations for the board and its peripherals. | 171 | configurations for the board and its peripherals. |
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 4f63048be3ca..0b9338cec516 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile | |||
@@ -3,7 +3,7 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Object file lists. | 5 | # Object file lists. |
6 | obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o | 6 | obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o |
7 | obj-$(CONFIG_SOC_IMX50) += mm-mx50.o | 7 | obj-$(CONFIG_SOC_IMX50) += mm-mx50.o |
8 | 8 | ||
9 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o | 9 | obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o |
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index b2ecd194e76d..bea4e4135f9d 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c | |||
@@ -228,13 +228,12 @@ static inline void babbage_fec_reset(void) | |||
228 | int ret; | 228 | int ret; |
229 | 229 | ||
230 | /* reset FEC PHY */ | 230 | /* reset FEC PHY */ |
231 | ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); | 231 | ret = gpio_request_one(BABBAGE_FEC_PHY_RESET, |
232 | GPIOF_OUT_INIT_LOW, "fec-phy-reset"); | ||
232 | if (ret) { | 233 | if (ret) { |
233 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | 234 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); |
234 | return; | 235 | return; |
235 | } | 236 | } |
236 | gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); | ||
237 | gpio_set_value(BABBAGE_FEC_PHY_RESET, 0); | ||
238 | msleep(1); | 237 | msleep(1); |
239 | gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); | 238 | gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); |
240 | } | 239 | } |
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c index 7b5735c5ea59..2af3f43f74db 100644 --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c | |||
@@ -34,7 +34,7 @@ | |||
34 | #include <mach/imx-uart.h> | 34 | #include <mach/imx-uart.h> |
35 | #include <mach/iomux-mx53.h> | 35 | #include <mach/iomux-mx53.h> |
36 | 36 | ||
37 | #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) | 37 | #define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) |
38 | #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) | 38 | #define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) |
39 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) | 39 | #define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) |
40 | 40 | ||
@@ -82,15 +82,14 @@ static inline void mx53_evk_fec_reset(void) | |||
82 | int ret; | 82 | int ret; |
83 | 83 | ||
84 | /* reset FEC PHY */ | 84 | /* reset FEC PHY */ |
85 | ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset"); | 85 | ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW, |
86 | "fec-phy-reset"); | ||
86 | if (ret) { | 87 | if (ret) { |
87 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); | 88 | printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret); |
88 | return; | 89 | return; |
89 | } | 90 | } |
90 | gpio_direction_output(SMD_FEC_PHY_RST, 0); | ||
91 | gpio_set_value(SMD_FEC_PHY_RST, 0); | ||
92 | msleep(1); | 91 | msleep(1); |
93 | gpio_set_value(SMD_FEC_PHY_RST, 1); | 92 | gpio_set_value(MX53_EVK_FEC_PHY_RST, 1); |
94 | } | 93 | } |
95 | 94 | ||
96 | static struct fec_platform_data mx53_evk_fec_pdata = { | 95 | static struct fec_platform_data mx53_evk_fec_pdata = { |
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c index 0a18f8d23eb0..10a1bea10548 100644 --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c | |||
@@ -36,6 +36,9 @@ | |||
36 | #include "crm_regs.h" | 36 | #include "crm_regs.h" |
37 | #include "devices-imx53.h" | 37 | #include "devices-imx53.h" |
38 | 38 | ||
39 | #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) | ||
40 | #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) | ||
41 | #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) | ||
39 | #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) | 42 | #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) |
40 | 43 | ||
41 | static iomux_v3_cfg_t mx53_loco_pads[] = { | 44 | static iomux_v3_cfg_t mx53_loco_pads[] = { |
@@ -180,6 +183,27 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { | |||
180 | MX53_PAD_GPIO_8__GPIO1_8, | 183 | MX53_PAD_GPIO_8__GPIO1_8, |
181 | }; | 184 | }; |
182 | 185 | ||
186 | #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ | ||
187 | { \ | ||
188 | .gpio = gpio_num, \ | ||
189 | .type = EV_KEY, \ | ||
190 | .code = ev_code, \ | ||
191 | .active_low = act_low, \ | ||
192 | .desc = "btn " descr, \ | ||
193 | .wakeup = wake, \ | ||
194 | } | ||
195 | |||
196 | static const struct gpio_keys_button loco_buttons[] __initconst = { | ||
197 | GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), | ||
198 | GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), | ||
199 | GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), | ||
200 | }; | ||
201 | |||
202 | static const struct gpio_keys_platform_data loco_button_data __initconst = { | ||
203 | .buttons = loco_buttons, | ||
204 | .nbuttons = ARRAY_SIZE(loco_buttons), | ||
205 | }; | ||
206 | |||
183 | static inline void mx53_loco_fec_reset(void) | 207 | static inline void mx53_loco_fec_reset(void) |
184 | { | 208 | { |
185 | int ret; | 209 | int ret; |
@@ -215,6 +239,7 @@ static void __init mx53_loco_board_init(void) | |||
215 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); | 239 | imx53_add_imx_i2c(1, &mx53_loco_i2c_data); |
216 | imx53_add_sdhci_esdhc_imx(0, NULL); | 240 | imx53_add_sdhci_esdhc_imx(0, NULL); |
217 | imx53_add_sdhci_esdhc_imx(2, NULL); | 241 | imx53_add_sdhci_esdhc_imx(2, NULL); |
242 | imx_add_gpio_keys(&loco_button_data); | ||
218 | } | 243 | } |
219 | 244 | ||
220 | static void __init mx53_loco_timer_init(void) | 245 | static void __init mx53_loco_timer_init(void) |
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index 652ace413825..fdbc05ed5513 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
@@ -865,6 +865,13 @@ static struct clk aips_tz2_clk = { | |||
865 | .disable = _clk_ccgr_disable_inwait, | 865 | .disable = _clk_ccgr_disable_inwait, |
866 | }; | 866 | }; |
867 | 867 | ||
868 | static struct clk gpc_dvfs_clk = { | ||
869 | .enable_reg = MXC_CCM_CCGR5, | ||
870 | .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, | ||
871 | .enable = _clk_ccgr_enable, | ||
872 | .disable = _clk_ccgr_disable, | ||
873 | }; | ||
874 | |||
868 | static struct clk gpt_32k_clk = { | 875 | static struct clk gpt_32k_clk = { |
869 | .id = 0, | 876 | .id = 0, |
870 | .parent = &ckil_clk, | 877 | .parent = &ckil_clk, |
@@ -1448,6 +1455,7 @@ static struct clk_lookup mx51_lookups[] = { | |||
1448 | _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) | 1455 | _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk) |
1449 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) | 1456 | _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk) |
1450 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) | 1457 | _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk) |
1458 | _REGISTER_CLOCK(NULL, "gpc_dvfs", gpc_dvfs_clk) | ||
1451 | }; | 1459 | }; |
1452 | 1460 | ||
1453 | static struct clk_lookup mx53_lookups[] = { | 1461 | static struct clk_lookup mx53_lookups[] = { |
@@ -1511,6 +1519,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
1511 | clk_enable(&iim_clk); | 1519 | clk_enable(&iim_clk); |
1512 | mx51_revision(); | 1520 | mx51_revision(); |
1513 | clk_disable(&iim_clk); | 1521 | clk_disable(&iim_clk); |
1522 | mx51_display_revision(); | ||
1514 | 1523 | ||
1515 | /* move usb_phy_clk to 24MHz */ | 1524 | /* move usb_phy_clk to 24MHz */ |
1516 | clk_set_parent(&usb_phy1_clk, &osc_clk); | 1525 | clk_set_parent(&usb_phy1_clk, &osc_clk); |
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index df46b5e60857..472bdfab2e55 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c | |||
@@ -21,6 +21,7 @@ | |||
21 | static int cpu_silicon_rev = -1; | 21 | static int cpu_silicon_rev = -1; |
22 | 22 | ||
23 | #define IIM_SREV 0x24 | 23 | #define IIM_SREV 0x24 |
24 | #define MX50_HW_ADADIG_DIGPROG 0xB0 | ||
24 | 25 | ||
25 | static int get_mx51_srev(void) | 26 | static int get_mx51_srev(void) |
26 | { | 27 | { |
@@ -51,6 +52,26 @@ int mx51_revision(void) | |||
51 | } | 52 | } |
52 | EXPORT_SYMBOL(mx51_revision); | 53 | EXPORT_SYMBOL(mx51_revision); |
53 | 54 | ||
55 | void mx51_display_revision(void) | ||
56 | { | ||
57 | int rev; | ||
58 | char *srev; | ||
59 | rev = mx51_revision(); | ||
60 | |||
61 | switch (rev) { | ||
62 | case IMX_CHIP_REVISION_2_0: | ||
63 | srev = IMX_CHIP_REVISION_2_0_STRING; | ||
64 | break; | ||
65 | case IMX_CHIP_REVISION_3_0: | ||
66 | srev = IMX_CHIP_REVISION_3_0_STRING; | ||
67 | break; | ||
68 | default: | ||
69 | srev = IMX_CHIP_REVISION_UNKNOWN_STRING; | ||
70 | } | ||
71 | printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev); | ||
72 | } | ||
73 | EXPORT_SYMBOL(mx51_display_revision); | ||
74 | |||
54 | #ifdef CONFIG_NEON | 75 | #ifdef CONFIG_NEON |
55 | 76 | ||
56 | /* | 77 | /* |
@@ -107,6 +128,44 @@ int mx53_revision(void) | |||
107 | } | 128 | } |
108 | EXPORT_SYMBOL(mx53_revision); | 129 | EXPORT_SYMBOL(mx53_revision); |
109 | 130 | ||
131 | static int get_mx50_srev(void) | ||
132 | { | ||
133 | void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K); | ||
134 | u32 rev; | ||
135 | |||
136 | if (!anatop) { | ||
137 | cpu_silicon_rev = -EINVAL; | ||
138 | return 0; | ||
139 | } | ||
140 | |||
141 | rev = readl(anatop + MX50_HW_ADADIG_DIGPROG); | ||
142 | rev &= 0xff; | ||
143 | |||
144 | iounmap(anatop); | ||
145 | if (rev == 0x0) | ||
146 | return IMX_CHIP_REVISION_1_0; | ||
147 | else if (rev == 0x1) | ||
148 | return IMX_CHIP_REVISION_1_1; | ||
149 | return 0; | ||
150 | } | ||
151 | |||
152 | /* | ||
153 | * Returns: | ||
154 | * the silicon revision of the cpu | ||
155 | * -EINVAL - not a mx50 | ||
156 | */ | ||
157 | int mx50_revision(void) | ||
158 | { | ||
159 | if (!cpu_is_mx50()) | ||
160 | return -EINVAL; | ||
161 | |||
162 | if (cpu_silicon_rev == -1) | ||
163 | cpu_silicon_rev = get_mx50_srev(); | ||
164 | |||
165 | return cpu_silicon_rev; | ||
166 | } | ||
167 | EXPORT_SYMBOL(mx50_revision); | ||
168 | |||
110 | static int __init post_cpu_init(void) | 169 | static int __init post_cpu_init(void) |
111 | { | 170 | { |
112 | unsigned int reg; | 171 | unsigned int reg; |
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c index e83ffadb65f8..4a8550529b04 100644 --- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c | |||
@@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void) | |||
212 | 212 | ||
213 | gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); | 213 | gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); |
214 | gpio_direction_input(MBIMX51_TSC2007_GPIO); | 214 | gpio_direction_input(MBIMX51_TSC2007_GPIO); |
215 | set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); | 215 | irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); |
216 | i2c_register_board_info(1, mbimx51_i2c_devices, | 216 | i2c_register_board_info(1, mbimx51_i2c_devices, |
217 | ARRAY_SIZE(mbimx51_i2c_devices)); | 217 | ARRAY_SIZE(mbimx51_i2c_devices)); |
218 | 218 | ||
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c index c372a4373691..e6c1119c20ae 100644 --- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c +++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c | |||
@@ -67,6 +67,10 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = { | |||
67 | MX51_PAD_SD1_DATA1__SD1_DATA1, | 67 | MX51_PAD_SD1_DATA1__SD1_DATA1, |
68 | MX51_PAD_SD1_DATA2__SD1_DATA2, | 68 | MX51_PAD_SD1_DATA2__SD1_DATA2, |
69 | MX51_PAD_SD1_DATA3__SD1_DATA3, | 69 | MX51_PAD_SD1_DATA3__SD1_DATA3, |
70 | /* SD1 CD */ | ||
71 | _MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | | ||
72 | PAD_CTL_PKE | PAD_CTL_SRE_FAST | | ||
73 | PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), | ||
70 | }; | 74 | }; |
71 | 75 | ||
72 | #define GPIO_LED1 IMX_GPIO_NR(3, 30) | 76 | #define GPIO_LED1 IMX_GPIO_NR(3, 30) |
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c index 868af8f435fa..d0c7075937cf 100644 --- a/arch/arm/mach-mx5/mx51_efika.c +++ b/arch/arm/mach-mx5/mx51_efika.c | |||
@@ -42,7 +42,6 @@ | |||
42 | #include <asm/mach-types.h> | 42 | #include <asm/mach-types.h> |
43 | #include <asm/mach/arch.h> | 43 | #include <asm/mach/arch.h> |
44 | #include <asm/mach/time.h> | 44 | #include <asm/mach/time.h> |
45 | #include <asm/mach-types.h> | ||
46 | 45 | ||
47 | #include "devices-imx51.h" | 46 | #include "devices-imx51.h" |
48 | #include "devices.h" | 47 | #include "devices.h" |
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c new file mode 100644 index 000000000000..76ae8dc33e00 --- /dev/null +++ b/arch/arm/mach-mx5/system.c | |||
@@ -0,0 +1,84 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
3 | */ | ||
4 | |||
5 | /* | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | #include <linux/platform_device.h> | ||
14 | #include <linux/io.h> | ||
15 | #include <mach/hardware.h> | ||
16 | #include "crm_regs.h" | ||
17 | |||
18 | /* set cpu low power mode before WFI instruction. This function is called | ||
19 | * mx5 because it can be used for mx50, mx51, and mx53.*/ | ||
20 | void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) | ||
21 | { | ||
22 | u32 plat_lpc, arm_srpgcr, ccm_clpcr; | ||
23 | u32 empgc0, empgc1; | ||
24 | int stop_mode = 0; | ||
25 | |||
26 | /* always allow platform to issue a deep sleep mode request */ | ||
27 | plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & | ||
28 | ~(MXC_CORTEXA8_PLAT_LPC_DSM); | ||
29 | ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); | ||
30 | arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); | ||
31 | empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); | ||
32 | empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); | ||
33 | |||
34 | switch (mode) { | ||
35 | case WAIT_CLOCKED: | ||
36 | break; | ||
37 | case WAIT_UNCLOCKED: | ||
38 | ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; | ||
39 | break; | ||
40 | case WAIT_UNCLOCKED_POWER_OFF: | ||
41 | case STOP_POWER_OFF: | ||
42 | plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM | ||
43 | | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; | ||
44 | if (mode == WAIT_UNCLOCKED_POWER_OFF) { | ||
45 | ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; | ||
46 | ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; | ||
47 | ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; | ||
48 | stop_mode = 0; | ||
49 | } else { | ||
50 | ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; | ||
51 | ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; | ||
52 | ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; | ||
53 | ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; | ||
54 | stop_mode = 1; | ||
55 | } | ||
56 | arm_srpgcr |= MXC_SRPGCR_PCR; | ||
57 | |||
58 | if (tzic_enable_wake(1) != 0) | ||
59 | return; | ||
60 | break; | ||
61 | case STOP_POWER_ON: | ||
62 | ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; | ||
63 | break; | ||
64 | default: | ||
65 | printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); | ||
66 | return; | ||
67 | } | ||
68 | |||
69 | __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); | ||
70 | __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); | ||
71 | __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); | ||
72 | |||
73 | /* Enable NEON SRPG for all but MX50TO1.0. */ | ||
74 | if (mx50_revision() != IMX_CHIP_REVISION_1_0) | ||
75 | __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); | ||
76 | |||
77 | if (stop_mode) { | ||
78 | empgc0 |= MXC_SRPGCR_PCR; | ||
79 | empgc1 |= MXC_SRPGCR_PCR; | ||
80 | |||
81 | __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); | ||
82 | __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); | ||
83 | } | ||
84 | } | ||
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 4f6f174af6c8..4522fbb235d5 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
@@ -22,6 +22,7 @@ config MACH_MX23EVK | |||
22 | select SOC_IMX23 | 22 | select SOC_IMX23 |
23 | select MXS_HAVE_AMBA_DUART | 23 | select MXS_HAVE_AMBA_DUART |
24 | select MXS_HAVE_PLATFORM_AUART | 24 | select MXS_HAVE_PLATFORM_AUART |
25 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
25 | select MXS_HAVE_PLATFORM_MXSFB | 26 | select MXS_HAVE_PLATFORM_MXSFB |
26 | default y | 27 | default y |
27 | help | 28 | help |
@@ -35,6 +36,7 @@ config MACH_MX28EVK | |||
35 | select MXS_HAVE_PLATFORM_AUART | 36 | select MXS_HAVE_PLATFORM_AUART |
36 | select MXS_HAVE_PLATFORM_FEC | 37 | select MXS_HAVE_PLATFORM_FEC |
37 | select MXS_HAVE_PLATFORM_FLEXCAN | 38 | select MXS_HAVE_PLATFORM_FLEXCAN |
39 | select MXS_HAVE_PLATFORM_MXS_MMC | ||
38 | select MXS_HAVE_PLATFORM_MXSFB | 40 | select MXS_HAVE_PLATFORM_MXSFB |
39 | select MXS_OCOTP | 41 | select MXS_OCOTP |
40 | default y | 42 | default y |
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c index d133c7f30940..c3577ea789ac 100644 --- a/arch/arm/mach-mxs/clock-mx23.c +++ b/arch/arm/mach-mxs/clock-mx23.c | |||
@@ -521,6 +521,15 @@ static int clk_misc_init(void) | |||
521 | __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, | 521 | __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT, |
522 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); | 522 | CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET); |
523 | 523 | ||
524 | /* | ||
525 | * 480 MHz seems too high to be ssp clock source directly, | ||
526 | * so set frac to get a 288 MHz ref_io. | ||
527 | */ | ||
528 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); | ||
529 | reg &= ~BM_CLKCTRL_FRAC_IOFRAC; | ||
530 | reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC; | ||
531 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); | ||
532 | |||
524 | return 0; | 533 | return 0; |
525 | } | 534 | } |
526 | 535 | ||
@@ -528,6 +537,12 @@ int __init mx23_clocks_init(void) | |||
528 | { | 537 | { |
529 | clk_misc_init(); | 538 | clk_misc_init(); |
530 | 539 | ||
540 | /* | ||
541 | * source ssp clock from ref_io than ref_xtal, | ||
542 | * as ref_xtal only provides 24 MHz as maximum. | ||
543 | */ | ||
544 | clk_set_parent(&ssp_clk, &ref_io_clk); | ||
545 | |||
531 | clk_enable(&cpu_clk); | 546 | clk_enable(&cpu_clk); |
532 | clk_enable(&hbus_clk); | 547 | clk_enable(&hbus_clk); |
533 | clk_enable(&xbus_clk); | 548 | clk_enable(&xbus_clk); |
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5e489a2b2023..1ad97fed1e94 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c | |||
@@ -618,6 +618,8 @@ static struct clk_lookup lookups[] = { | |||
618 | _REGISTER_CLOCK("pll2", NULL, pll2_clk) | 618 | _REGISTER_CLOCK("pll2", NULL, pll2_clk) |
619 | _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) | 619 | _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk) |
620 | _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) | 620 | _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk) |
621 | _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk) | ||
622 | _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk) | ||
621 | _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) | 623 | _REGISTER_CLOCK("flexcan.0", NULL, can0_clk) |
622 | _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) | 624 | _REGISTER_CLOCK("flexcan.1", NULL, can1_clk) |
623 | _REGISTER_CLOCK(NULL, "usb0", usb0_clk) | 625 | _REGISTER_CLOCK(NULL, "usb0", usb0_clk) |
@@ -737,6 +739,15 @@ static int clk_misc_init(void) | |||
737 | reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; | 739 | reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; |
738 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); | 740 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); |
739 | 741 | ||
742 | /* | ||
743 | * 480 MHz seems too high to be ssp clock source directly, | ||
744 | * so set frac0 to get a 288 MHz ref_io0. | ||
745 | */ | ||
746 | reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); | ||
747 | reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC; | ||
748 | reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC; | ||
749 | __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); | ||
750 | |||
740 | return 0; | 751 | return 0; |
741 | } | 752 | } |
742 | 753 | ||
@@ -744,6 +755,13 @@ int __init mx28_clocks_init(void) | |||
744 | { | 755 | { |
745 | clk_misc_init(); | 756 | clk_misc_init(); |
746 | 757 | ||
758 | /* | ||
759 | * source ssp clock from ref_io0 than ref_xtal, | ||
760 | * as ref_xtal only provides 24 MHz as maximum. | ||
761 | */ | ||
762 | clk_set_parent(&ssp0_clk, &ref_io0_clk); | ||
763 | clk_set_parent(&ssp1_clk, &ref_io0_clk); | ||
764 | |||
747 | clk_enable(&cpu_clk); | 765 | clk_enable(&cpu_clk); |
748 | clk_enable(&hbus_clk); | 766 | clk_enable(&hbus_clk); |
749 | clk_enable(&xbus_clk); | 767 | clk_enable(&xbus_clk); |
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index c7e14f4e3669..c6f345febd39 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h | |||
@@ -21,6 +21,10 @@ extern const struct mxs_auart_data mx23_auart_data[] __initconst; | |||
21 | #define mx23_add_auart0() mx23_add_auart(0) | 21 | #define mx23_add_auart0() mx23_add_auart(0) |
22 | #define mx23_add_auart1() mx23_add_auart(1) | 22 | #define mx23_add_auart1() mx23_add_auart(1) |
23 | 23 | ||
24 | extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst; | ||
25 | #define mx23_add_mxs_mmc(id, pdata) \ | ||
26 | mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata) | ||
27 | |||
24 | #define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) | 28 | #define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id) |
25 | 29 | ||
26 | struct platform_device *__init mx23_add_mxsfb( | 30 | struct platform_device *__init mx23_add_mxsfb( |
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 9d08555c4cf0..c473eddce8cf 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h | |||
@@ -37,6 +37,10 @@ extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst; | |||
37 | extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; | 37 | extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst; |
38 | #define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) | 38 | #define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id]) |
39 | 39 | ||
40 | extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst; | ||
41 | #define mx28_add_mxs_mmc(id, pdata) \ | ||
42 | mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata) | ||
43 | |||
40 | #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) | 44 | #define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id) |
41 | 45 | ||
42 | struct platform_device *__init mx28_add_mxsfb( | 46 | struct platform_device *__init mx28_add_mxsfb( |
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig index 1451ad060d82..acf9eea124c0 100644 --- a/arch/arm/mach-mxs/devices/Kconfig +++ b/arch/arm/mach-mxs/devices/Kconfig | |||
@@ -15,6 +15,9 @@ config MXS_HAVE_PLATFORM_FLEXCAN | |||
15 | config MXS_HAVE_PLATFORM_MXS_I2C | 15 | config MXS_HAVE_PLATFORM_MXS_I2C |
16 | bool | 16 | bool |
17 | 17 | ||
18 | config MXS_HAVE_PLATFORM_MXS_MMC | ||
19 | bool | ||
20 | |||
18 | config MXS_HAVE_PLATFORM_MXS_PWM | 21 | config MXS_HAVE_PLATFORM_MXS_PWM |
19 | bool | 22 | bool |
20 | 23 | ||
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile index 0d9bea30b0a2..324f2824d38d 100644 --- a/arch/arm/mach-mxs/devices/Makefile +++ b/arch/arm/mach-mxs/devices/Makefile | |||
@@ -4,5 +4,6 @@ obj-y += platform-dma.o | |||
4 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o | 4 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o |
5 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o | 5 | obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o |
6 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o | 6 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o |
7 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o | ||
7 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o | 8 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o |
8 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o | 9 | obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o |
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c new file mode 100644 index 000000000000..382dacbeca21 --- /dev/null +++ b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Pengutronix | ||
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
4 | * | ||
5 | * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it under | ||
8 | * the terms of the GNU General Public License version 2 as published by the | ||
9 | * Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/compiler.h> | ||
13 | #include <linux/err.h> | ||
14 | #include <linux/init.h> | ||
15 | |||
16 | #include <mach/mx23.h> | ||
17 | #include <mach/mx28.h> | ||
18 | #include <mach/devices-common.h> | ||
19 | |||
20 | #define mxs_mxs_mmc_data_entry_single(soc, _id, hwid) \ | ||
21 | { \ | ||
22 | .id = _id, \ | ||
23 | .iobase = soc ## _SSP ## hwid ## _BASE_ADDR, \ | ||
24 | .dma = soc ## _DMA_SSP ## hwid, \ | ||
25 | .irq_err = soc ## _INT_SSP ## hwid ## _ERROR, \ | ||
26 | .irq_dma = soc ## _INT_SSP ## hwid ## _DMA, \ | ||
27 | } | ||
28 | |||
29 | #define mxs_mxs_mmc_data_entry(soc, _id, hwid) \ | ||
30 | [_id] = mxs_mxs_mmc_data_entry_single(soc, _id, hwid) | ||
31 | |||
32 | |||
33 | #ifdef CONFIG_SOC_IMX23 | ||
34 | const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = { | ||
35 | mxs_mxs_mmc_data_entry(MX23, 0, 1), | ||
36 | mxs_mxs_mmc_data_entry(MX23, 1, 2), | ||
37 | }; | ||
38 | #endif | ||
39 | |||
40 | #ifdef CONFIG_SOC_IMX28 | ||
41 | const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = { | ||
42 | mxs_mxs_mmc_data_entry(MX28, 0, 0), | ||
43 | mxs_mxs_mmc_data_entry(MX28, 1, 1), | ||
44 | }; | ||
45 | #endif | ||
46 | |||
47 | struct platform_device *__init mxs_add_mxs_mmc( | ||
48 | const struct mxs_mxs_mmc_data *data, | ||
49 | const struct mxs_mmc_platform_data *pdata) | ||
50 | { | ||
51 | struct resource res[] = { | ||
52 | { | ||
53 | .start = data->iobase, | ||
54 | .end = data->iobase + SZ_8K - 1, | ||
55 | .flags = IORESOURCE_MEM, | ||
56 | }, { | ||
57 | .start = data->dma, | ||
58 | .end = data->dma, | ||
59 | .flags = IORESOURCE_DMA, | ||
60 | }, { | ||
61 | .start = data->irq_err, | ||
62 | .end = data->irq_err, | ||
63 | .flags = IORESOURCE_IRQ, | ||
64 | }, { | ||
65 | .start = data->irq_dma, | ||
66 | .end = data->irq_dma, | ||
67 | .flags = IORESOURCE_IRQ, | ||
68 | }, | ||
69 | }; | ||
70 | |||
71 | return mxs_add_platform_device("mxs-mmc", data->id, | ||
72 | res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); | ||
73 | } | ||
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c index 56fa2ed15222..2c950fef71a8 100644 --- a/arch/arm/mach-mxs/gpio.c +++ b/arch/arm/mach-mxs/gpio.c | |||
@@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) | |||
136 | static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) | 136 | static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
137 | { | 137 | { |
138 | u32 irq_stat; | 138 | u32 irq_stat; |
139 | struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); | 139 | struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq); |
140 | u32 gpio_irq_no_base = port->virtual_irq_start; | 140 | u32 gpio_irq_no_base = port->virtual_irq_start; |
141 | 141 | ||
142 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 142 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
@@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) | |||
265 | 265 | ||
266 | for (j = port[i].virtual_irq_start; | 266 | for (j = port[i].virtual_irq_start; |
267 | j < port[i].virtual_irq_start + 32; j++) { | 267 | j < port[i].virtual_irq_start + 32; j++) { |
268 | set_irq_chip(j, &gpio_irq_chip); | 268 | irq_set_chip_and_handler(j, &gpio_irq_chip, |
269 | set_irq_handler(j, handle_level_irq); | 269 | handle_level_irq); |
270 | set_irq_flags(j, IRQF_VALID); | 270 | set_irq_flags(j, IRQF_VALID); |
271 | } | 271 | } |
272 | 272 | ||
273 | /* setup one handler for each entry */ | 273 | /* setup one handler for each entry */ |
274 | set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); | 274 | irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler); |
275 | set_irq_data(port[i].irq, &port[i]); | 275 | irq_set_handler_data(port[i].irq, &port[i]); |
276 | 276 | ||
277 | /* register gpio chip */ | 277 | /* register gpio chip */ |
278 | port[i].chip.direction_input = mxs_gpio_direction_input; | 278 | port[i].chip.direction_input = mxs_gpio_direction_input; |
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c index 0f4c120fc169..23ca9d083b2c 100644 --- a/arch/arm/mach-mxs/icoll.c +++ b/arch/arm/mach-mxs/icoll.c | |||
@@ -74,8 +74,7 @@ void __init icoll_init_irq(void) | |||
74 | mxs_reset_block(icoll_base + HW_ICOLL_CTRL); | 74 | mxs_reset_block(icoll_base + HW_ICOLL_CTRL); |
75 | 75 | ||
76 | for (i = 0; i < MXS_INTERNAL_IRQS; i++) { | 76 | for (i = 0; i < MXS_INTERNAL_IRQS; i++) { |
77 | set_irq_chip(i, &mxs_icoll_chip); | 77 | irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq); |
78 | set_irq_handler(i, handle_level_irq); | ||
79 | set_irq_flags(i, IRQF_VALID); | 78 | set_irq_flags(i, IRQF_VALID); |
80 | } | 79 | } |
81 | } | 80 | } |
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h index 71f24484b044..c5137f14c364 100644 --- a/arch/arm/mach-mxs/include/mach/devices-common.h +++ b/arch/arm/mach-mxs/include/mach/devices-common.h | |||
@@ -73,6 +73,19 @@ struct mxs_i2c_data { | |||
73 | }; | 73 | }; |
74 | struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data); | 74 | struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data); |
75 | 75 | ||
76 | /* mmc */ | ||
77 | #include <mach/mmc.h> | ||
78 | struct mxs_mxs_mmc_data { | ||
79 | int id; | ||
80 | resource_size_t iobase; | ||
81 | resource_size_t dma; | ||
82 | resource_size_t irq_err; | ||
83 | resource_size_t irq_dma; | ||
84 | }; | ||
85 | struct platform_device *__init mxs_add_mxs_mmc( | ||
86 | const struct mxs_mxs_mmc_data *data, | ||
87 | const struct mxs_mmc_platform_data *pdata); | ||
88 | |||
76 | /* pwm */ | 89 | /* pwm */ |
77 | struct platform_device *__init mxs_add_mxs_pwm( | 90 | struct platform_device *__init mxs_add_mxs_pwm( |
78 | resource_size_t iobase, int id); | 91 | resource_size_t iobase, int id); |
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c index a66994f0518f..214e5b641bbc 100644 --- a/arch/arm/mach-mxs/mach-mx23evk.c +++ b/arch/arm/mach-mxs/mach-mx23evk.c | |||
@@ -28,6 +28,8 @@ | |||
28 | 28 | ||
29 | #define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) | 29 | #define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18) |
30 | #define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) | 30 | #define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28) |
31 | #define MX23EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30) | ||
32 | #define MX23EVK_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29) | ||
31 | 33 | ||
32 | static const iomux_cfg_t mx23evk_pads[] __initconst = { | 34 | static const iomux_cfg_t mx23evk_pads[] __initconst = { |
33 | /* duart */ | 35 | /* duart */ |
@@ -73,6 +75,36 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = { | |||
73 | MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, | 75 | MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL, |
74 | /* backlight control */ | 76 | /* backlight control */ |
75 | MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, | 77 | MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL, |
78 | |||
79 | /* mmc */ | ||
80 | MX23_PAD_SSP1_DATA0__SSP1_DATA0 | | ||
81 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
82 | MX23_PAD_SSP1_DATA1__SSP1_DATA1 | | ||
83 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
84 | MX23_PAD_SSP1_DATA2__SSP1_DATA2 | | ||
85 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
86 | MX23_PAD_SSP1_DATA3__SSP1_DATA3 | | ||
87 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
88 | MX23_PAD_GPMI_D08__SSP1_DATA4 | | ||
89 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
90 | MX23_PAD_GPMI_D09__SSP1_DATA5 | | ||
91 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
92 | MX23_PAD_GPMI_D10__SSP1_DATA6 | | ||
93 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
94 | MX23_PAD_GPMI_D11__SSP1_DATA7 | | ||
95 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
96 | MX23_PAD_SSP1_CMD__SSP1_CMD | | ||
97 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
98 | MX23_PAD_SSP1_DETECT__SSP1_DETECT | | ||
99 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
100 | MX23_PAD_SSP1_SCK__SSP1_SCK | | ||
101 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
102 | /* write protect */ | ||
103 | MX23_PAD_PWM4__GPIO_1_30 | | ||
104 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
105 | /* slot power enable */ | ||
106 | MX23_PAD_PWM3__GPIO_1_29 | | ||
107 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
76 | }; | 108 | }; |
77 | 109 | ||
78 | /* mxsfb (lcdif) */ | 110 | /* mxsfb (lcdif) */ |
@@ -101,6 +133,11 @@ static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = { | |||
101 | .ld_intf_width = STMLCDIF_24BIT, | 133 | .ld_intf_width = STMLCDIF_24BIT, |
102 | }; | 134 | }; |
103 | 135 | ||
136 | static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = { | ||
137 | .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT, | ||
138 | .flags = SLOTF_8_BIT_CAPABLE, | ||
139 | }; | ||
140 | |||
104 | static void __init mx23evk_init(void) | 141 | static void __init mx23evk_init(void) |
105 | { | 142 | { |
106 | int ret; | 143 | int ret; |
@@ -110,6 +147,13 @@ static void __init mx23evk_init(void) | |||
110 | mx23_add_duart(); | 147 | mx23_add_duart(); |
111 | mx23_add_auart0(); | 148 | mx23_add_auart0(); |
112 | 149 | ||
150 | /* power on mmc slot by writing 0 to the gpio */ | ||
151 | ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT, | ||
152 | "mmc0-slot-power"); | ||
153 | if (ret) | ||
154 | pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); | ||
155 | mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata); | ||
156 | |||
113 | ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); | 157 | ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable"); |
114 | if (ret) | 158 | if (ret) |
115 | pr_warn("failed to request gpio lcd-enable: %d\n", ret); | 159 | pr_warn("failed to request gpio lcd-enable: %d\n", ret); |
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c index 08002d02267a..bb329b9a2608 100644 --- a/arch/arm/mach-mxs/mach-mx28evk.c +++ b/arch/arm/mach-mxs/mach-mx28evk.c | |||
@@ -34,6 +34,11 @@ | |||
34 | #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) | 34 | #define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30) |
35 | #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) | 35 | #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) |
36 | 36 | ||
37 | #define MX28EVK_MMC0_WRITE_PROTECT MXS_GPIO_NR(2, 12) | ||
38 | #define MX28EVK_MMC1_WRITE_PROTECT MXS_GPIO_NR(0, 28) | ||
39 | #define MX28EVK_MMC0_SLOT_POWER MXS_GPIO_NR(3, 28) | ||
40 | #define MX28EVK_MMC1_SLOT_POWER MXS_GPIO_NR(3, 29) | ||
41 | |||
37 | static const iomux_cfg_t mx28evk_pads[] __initconst = { | 42 | static const iomux_cfg_t mx28evk_pads[] __initconst = { |
38 | /* duart */ | 43 | /* duart */ |
39 | MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, | 44 | MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL, |
@@ -115,6 +120,65 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = { | |||
115 | MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, | 120 | MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, |
116 | /* backlight control */ | 121 | /* backlight control */ |
117 | MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, | 122 | MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL, |
123 | /* mmc0 */ | ||
124 | MX28_PAD_SSP0_DATA0__SSP0_D0 | | ||
125 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
126 | MX28_PAD_SSP0_DATA1__SSP0_D1 | | ||
127 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
128 | MX28_PAD_SSP0_DATA2__SSP0_D2 | | ||
129 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
130 | MX28_PAD_SSP0_DATA3__SSP0_D3 | | ||
131 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
132 | MX28_PAD_SSP0_DATA4__SSP0_D4 | | ||
133 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
134 | MX28_PAD_SSP0_DATA5__SSP0_D5 | | ||
135 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
136 | MX28_PAD_SSP0_DATA6__SSP0_D6 | | ||
137 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
138 | MX28_PAD_SSP0_DATA7__SSP0_D7 | | ||
139 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
140 | MX28_PAD_SSP0_CMD__SSP0_CMD | | ||
141 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
142 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | ||
143 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
144 | MX28_PAD_SSP0_SCK__SSP0_SCK | | ||
145 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
146 | /* write protect */ | ||
147 | MX28_PAD_SSP1_SCK__GPIO_2_12 | | ||
148 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
149 | /* slot power enable */ | ||
150 | MX28_PAD_PWM3__GPIO_3_28 | | ||
151 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
152 | |||
153 | /* mmc1 */ | ||
154 | MX28_PAD_GPMI_D00__SSP1_D0 | | ||
155 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
156 | MX28_PAD_GPMI_D01__SSP1_D1 | | ||
157 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
158 | MX28_PAD_GPMI_D02__SSP1_D2 | | ||
159 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
160 | MX28_PAD_GPMI_D03__SSP1_D3 | | ||
161 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
162 | MX28_PAD_GPMI_D04__SSP1_D4 | | ||
163 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
164 | MX28_PAD_GPMI_D05__SSP1_D5 | | ||
165 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
166 | MX28_PAD_GPMI_D06__SSP1_D6 | | ||
167 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
168 | MX28_PAD_GPMI_D07__SSP1_D7 | | ||
169 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
170 | MX28_PAD_GPMI_RDY1__SSP1_CMD | | ||
171 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), | ||
172 | MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT | | ||
173 | (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
174 | MX28_PAD_GPMI_WRN__SSP1_SCK | | ||
175 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
176 | /* write protect */ | ||
177 | MX28_PAD_GPMI_RESETN__GPIO_0_28 | | ||
178 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
179 | /* slot power enable */ | ||
180 | MX28_PAD_PWM4__GPIO_3_29 | | ||
181 | (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | ||
118 | }; | 182 | }; |
119 | 183 | ||
120 | /* fec */ | 184 | /* fec */ |
@@ -258,6 +322,18 @@ static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = { | |||
258 | .ld_intf_width = STMLCDIF_24BIT, | 322 | .ld_intf_width = STMLCDIF_24BIT, |
259 | }; | 323 | }; |
260 | 324 | ||
325 | static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = { | ||
326 | { | ||
327 | /* mmc0 */ | ||
328 | .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT, | ||
329 | .flags = SLOTF_8_BIT_CAPABLE, | ||
330 | }, { | ||
331 | /* mmc1 */ | ||
332 | .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT, | ||
333 | .flags = SLOTF_8_BIT_CAPABLE, | ||
334 | }, | ||
335 | }; | ||
336 | |||
261 | static void __init mx28evk_init(void) | 337 | static void __init mx28evk_init(void) |
262 | { | 338 | { |
263 | int ret; | 339 | int ret; |
@@ -297,6 +373,19 @@ static void __init mx28evk_init(void) | |||
297 | gpio_set_value(MX28EVK_BL_ENABLE, 1); | 373 | gpio_set_value(MX28EVK_BL_ENABLE, 1); |
298 | 374 | ||
299 | mx28_add_mxsfb(&mx28evk_mxsfb_pdata); | 375 | mx28_add_mxsfb(&mx28evk_mxsfb_pdata); |
376 | |||
377 | /* power on mmc slot by writing 0 to the gpio */ | ||
378 | ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT, | ||
379 | "mmc0-slot-power"); | ||
380 | if (ret) | ||
381 | pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret); | ||
382 | mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]); | ||
383 | |||
384 | ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_DIR_OUT, | ||
385 | "mmc1-slot-power"); | ||
386 | if (ret) | ||
387 | pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret); | ||
388 | mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]); | ||
300 | } | 389 | } |
301 | 390 | ||
302 | static void __init mx28evk_timer_init(void) | 391 | static void __init mx28evk_timer_init(void) |
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c index fa0b154da67b..0fcff47009cf 100644 --- a/arch/arm/mach-mxs/module-tx28.c +++ b/arch/arm/mach-mxs/module-tx28.c | |||
@@ -45,7 +45,7 @@ static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = { | |||
45 | }; | 45 | }; |
46 | 46 | ||
47 | #define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) | 47 | #define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3) |
48 | static const iomux_cfg_t tx28_fec_pads[] __initconst = { | 48 | static const iomux_cfg_t tx28_fec0_pads[] __initconst = { |
49 | MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, | 49 | MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE, |
50 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, | 50 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE, |
51 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, | 51 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE, |
@@ -57,7 +57,20 @@ static const iomux_cfg_t tx28_fec_pads[] __initconst = { | |||
57 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, | 57 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE, |
58 | }; | 58 | }; |
59 | 59 | ||
60 | static const struct fec_platform_data tx28_fec_data __initconst = { | 60 | static const iomux_cfg_t tx28_fec1_pads[] __initconst = { |
61 | MX28_PAD_ENET0_RXD2__ENET1_RXD0, | ||
62 | MX28_PAD_ENET0_RXD3__ENET1_RXD1, | ||
63 | MX28_PAD_ENET0_TXD2__ENET1_TXD0, | ||
64 | MX28_PAD_ENET0_TXD3__ENET1_TXD1, | ||
65 | MX28_PAD_ENET0_COL__ENET1_TX_EN, | ||
66 | MX28_PAD_ENET0_CRS__ENET1_RX_EN, | ||
67 | }; | ||
68 | |||
69 | static struct fec_platform_data tx28_fec0_data = { | ||
70 | .phy = PHY_INTERFACE_MODE_RMII, | ||
71 | }; | ||
72 | |||
73 | static struct fec_platform_data tx28_fec1_data = { | ||
61 | .phy = PHY_INTERFACE_MODE_RMII, | 74 | .phy = PHY_INTERFACE_MODE_RMII, |
62 | }; | 75 | }; |
63 | 76 | ||
@@ -108,15 +121,15 @@ int __init tx28_add_fec0(void) | |||
108 | pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); | 121 | pr_debug("%s: Deasserting FEC PHY RESET\n", __func__); |
109 | gpio_set_value(TX28_FEC_PHY_RESET, 1); | 122 | gpio_set_value(TX28_FEC_PHY_RESET, 1); |
110 | 123 | ||
111 | ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads, | 124 | ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads, |
112 | ARRAY_SIZE(tx28_fec_pads)); | 125 | ARRAY_SIZE(tx28_fec0_pads)); |
113 | if (ret) { | 126 | if (ret) { |
114 | pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", | 127 | pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", |
115 | __func__, ret); | 128 | __func__, ret); |
116 | goto free_gpios; | 129 | goto free_gpios; |
117 | } | 130 | } |
118 | pr_debug("%s: Registering FEC device\n", __func__); | 131 | pr_debug("%s: Registering FEC0 device\n", __func__); |
119 | mx28_add_fec(0, &tx28_fec_data); | 132 | mx28_add_fec(0, &tx28_fec0_data); |
120 | return 0; | 133 | return 0; |
121 | 134 | ||
122 | free_gpios: | 135 | free_gpios: |
@@ -129,3 +142,19 @@ free_gpios: | |||
129 | 142 | ||
130 | return ret; | 143 | return ret; |
131 | } | 144 | } |
145 | |||
146 | int __init tx28_add_fec1(void) | ||
147 | { | ||
148 | int ret; | ||
149 | |||
150 | ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads, | ||
151 | ARRAY_SIZE(tx28_fec1_pads)); | ||
152 | if (ret) { | ||
153 | pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n", | ||
154 | __func__, ret); | ||
155 | return ret; | ||
156 | } | ||
157 | pr_debug("%s: Registering FEC1 device\n", __func__); | ||
158 | mx28_add_fec(1, &tx28_fec1_data); | ||
159 | return 0; | ||
160 | } | ||
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h index df9e1b6e81bf..8ed425457d30 100644 --- a/arch/arm/mach-mxs/module-tx28.h +++ b/arch/arm/mach-mxs/module-tx28.h | |||
@@ -7,3 +7,4 @@ | |||
7 | * Free Software Foundation. | 7 | * Free Software Foundation. |
8 | */ | 8 | */ |
9 | int __init tx28_add_fec0(void); | 9 | int __init tx28_add_fec0(void); |
10 | int __init tx28_add_fec1(void); | ||
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 29ffa750fbe6..00023b5cf12b 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c | |||
@@ -171,13 +171,13 @@ void __init netx_init_irq(void) | |||
171 | vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); | 171 | vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); |
172 | 172 | ||
173 | for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { | 173 | for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { |
174 | set_irq_chip(irq, &netx_hif_chip); | 174 | irq_set_chip_and_handler(irq, &netx_hif_chip, |
175 | set_irq_handler(irq, handle_level_irq); | 175 | handle_level_irq); |
176 | set_irq_flags(irq, IRQF_VALID); | 176 | set_irq_flags(irq, IRQF_VALID); |
177 | } | 177 | } |
178 | 178 | ||
179 | writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); | 179 | writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); |
180 | set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); | 180 | irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); |
181 | } | 181 | } |
182 | 182 | ||
183 | static int __init netx_init(void) | 183 | static int __init netx_init(void) |
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c index 0c0d5248c368..e27687d53504 100644 --- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c +++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c | |||
@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void) | |||
107 | __func__); | 107 | __func__); |
108 | 108 | ||
109 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { | 109 | for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { |
110 | set_irq_chip(i, &a9m9750dev_fpga_chip); | 110 | irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip, |
111 | set_irq_handler(i, handle_level_irq); | 111 | handle_level_irq); |
112 | set_irq_flags(i, IRQF_VALID); | 112 | set_irq_flags(i, IRQF_VALID); |
113 | } | 113 | } |
114 | 114 | ||
@@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void) | |||
118 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); | 118 | REGSET(eic, SYS_EIC, LVEDG, LEVEL); |
119 | __raw_writel(eic, SYS_EIC(2)); | 119 | __raw_writel(eic, SYS_EIC(2)); |
120 | 120 | ||
121 | set_irq_chained_handler(IRQ_NS9XXX_EXT2, | 121 | irq_set_chained_handler(IRQ_NS9XXX_EXT2, |
122 | a9m9750dev_fpga_demux_handler); | 122 | a9m9750dev_fpga_demux_handler); |
123 | } | 123 | } |
124 | 124 | ||
125 | void __init board_a9m9750dev_init_machine(void) | 125 | void __init board_a9m9750dev_init_machine(void) |
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h index f7e9196eb9ab..19ca6de46a45 100644 --- a/arch/arm/mach-ns9xxx/include/mach/board.h +++ b/arch/arm/mach-ns9xxx/include/mach/board.h | |||
@@ -14,12 +14,10 @@ | |||
14 | #include <asm/mach-types.h> | 14 | #include <asm/mach-types.h> |
15 | 15 | ||
16 | #define board_is_a9m9750dev() (0 \ | 16 | #define board_is_a9m9750dev() (0 \ |
17 | || machine_is_cc9p9360dev() \ | ||
18 | || machine_is_cc9p9750dev() \ | 17 | || machine_is_cc9p9750dev() \ |
19 | ) | 18 | ) |
20 | 19 | ||
21 | #define board_is_a9mvali() (0 \ | 20 | #define board_is_a9mvali() (0 \ |
22 | || machine_is_cc9p9360val() \ | ||
23 | || machine_is_cc9p9750val() \ | 21 | || machine_is_cc9p9750val() \ |
24 | ) | 22 | ) |
25 | 23 | ||
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h index f851a6b7da6c..628e9752589b 100644 --- a/arch/arm/mach-ns9xxx/include/mach/module.h +++ b/arch/arm/mach-ns9xxx/include/mach/module.h | |||
@@ -18,7 +18,6 @@ | |||
18 | ) | 18 | ) |
19 | 19 | ||
20 | #define module_is_cc9c() (0 \ | 20 | #define module_is_cc9c() (0 \ |
21 | || machine_is_cc9c() \ | ||
22 | ) | 21 | ) |
23 | 22 | ||
24 | #define module_is_cc9p9210() (0 \ | 23 | #define module_is_cc9p9210() (0 \ |
@@ -32,21 +31,17 @@ | |||
32 | ) | 31 | ) |
33 | 32 | ||
34 | #define module_is_cc9p9360() (0 \ | 33 | #define module_is_cc9p9360() (0 \ |
35 | || machine_is_a9m9360() \ | ||
36 | || machine_is_cc9p9360dev() \ | 34 | || machine_is_cc9p9360dev() \ |
37 | || machine_is_cc9p9360js() \ | 35 | || machine_is_cc9p9360js() \ |
38 | || machine_is_cc9p9360val() \ | ||
39 | ) | 36 | ) |
40 | 37 | ||
41 | #define module_is_cc9p9750() (0 \ | 38 | #define module_is_cc9p9750() (0 \ |
42 | || machine_is_a9m9750() \ | 39 | || machine_is_a9m9750() \ |
43 | || machine_is_cc9p9750dev() \ | ||
44 | || machine_is_cc9p9750js() \ | 40 | || machine_is_cc9p9750js() \ |
45 | || machine_is_cc9p9750val() \ | 41 | || machine_is_cc9p9750val() \ |
46 | ) | 42 | ) |
47 | 43 | ||
48 | #define module_is_ccw9c() (0 \ | 44 | #define module_is_ccw9c() (0 \ |
49 | || machine_is_ccw9c() \ | ||
50 | ) | 45 | ) |
51 | 46 | ||
52 | #define module_is_inc20otter() (0 \ | 47 | #define module_is_inc20otter() (0 \ |
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c index bf0fd48cbd80..37ab0a2b83ad 100644 --- a/arch/arm/mach-ns9xxx/irq.c +++ b/arch/arm/mach-ns9xxx/irq.c | |||
@@ -67,8 +67,7 @@ void __init ns9xxx_init_irq(void) | |||
67 | __raw_writel(prio2irq(i), SYS_IVA(i)); | 67 | __raw_writel(prio2irq(i), SYS_IVA(i)); |
68 | 68 | ||
69 | for (i = 0; i <= 31; ++i) { | 69 | for (i = 0; i <= 31; ++i) { |
70 | set_irq_chip(i, &ns9xxx_chip); | 70 | irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq); |
71 | set_irq_handler(i, handle_fasteoi_irq); | ||
72 | set_irq_flags(i, IRQF_VALID); | 71 | set_irq_flags(i, IRQF_VALID); |
73 | irq_set_status_flags(i, IRQ_LEVEL); | 72 | irq_set_status_flags(i, IRQ_LEVEL); |
74 | } | 73 | } |
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c index 1f8a05a22834..aa279f23e342 100644 --- a/arch/arm/mach-nuc93x/irq.c +++ b/arch/arm/mach-nuc93x/irq.c | |||
@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void) | |||
59 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); | 59 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); |
60 | 60 | ||
61 | for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { | 61 | for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { |
62 | set_irq_chip(irqno, &nuc93x_irq_chip); | 62 | irq_set_chip_and_handler(irqno, &nuc93x_irq_chip, |
63 | set_irq_handler(irqno, handle_level_irq); | 63 | handle_level_irq); |
64 | set_irq_flags(irqno, IRQF_VALID); | 64 | set_irq_flags(irqno, IRQF_VALID); |
65 | } | 65 | } |
66 | } | 66 | } |
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 7c5e2112c776..e68dfde1918e 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
@@ -276,7 +276,7 @@ static void __init osk_init_cf(void) | |||
276 | return; | 276 | return; |
277 | } | 277 | } |
278 | /* the CF I/O IRQ is really active-low */ | 278 | /* the CF I/O IRQ is really active-low */ |
279 | set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); | 279 | irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); |
280 | } | 280 | } |
281 | 281 | ||
282 | static void __init osk_init_irq(void) | 282 | static void __init osk_init_irq(void) |
@@ -482,7 +482,7 @@ static void __init osk_mistral_init(void) | |||
482 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ | 482 | omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ |
483 | gpio_request(4, "ts_int"); | 483 | gpio_request(4, "ts_int"); |
484 | gpio_direction_input(4); | 484 | gpio_direction_input(4); |
485 | set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); | 485 | irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); |
486 | 486 | ||
487 | spi_register_board_info(mistral_boardinfo, | 487 | spi_register_board_info(mistral_boardinfo, |
488 | ARRAY_SIZE(mistral_boardinfo)); | 488 | ARRAY_SIZE(mistral_boardinfo)); |
@@ -500,7 +500,7 @@ static void __init osk_mistral_init(void) | |||
500 | int irq = gpio_to_irq(OMAP_MPUIO(2)); | 500 | int irq = gpio_to_irq(OMAP_MPUIO(2)); |
501 | 501 | ||
502 | gpio_direction_input(OMAP_MPUIO(2)); | 502 | gpio_direction_input(OMAP_MPUIO(2)); |
503 | set_irq_type(irq, IRQ_TYPE_EDGE_RISING); | 503 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
504 | #ifdef CONFIG_PM | 504 | #ifdef CONFIG_PM |
505 | /* share the IRQ in case someone wants to use the | 505 | /* share the IRQ in case someone wants to use the |
506 | * button for more than wakeup from system sleep. | 506 | * button for more than wakeup from system sleep. |
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index d7bbbe721a75..45f01d2c3a7a 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
@@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id) | |||
256 | { | 256 | { |
257 | if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { | 257 | if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { |
258 | printk(KERN_INFO "PM: Power cable connected\n"); | 258 | printk(KERN_INFO "PM: Power cable connected\n"); |
259 | set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), | 259 | irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), |
260 | IRQ_TYPE_EDGE_FALLING); | 260 | IRQ_TYPE_EDGE_FALLING); |
261 | } else { | 261 | } else { |
262 | printk(KERN_INFO "PM: Power cable disconnected\n"); | 262 | printk(KERN_INFO "PM: Power cable disconnected\n"); |
263 | set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), | 263 | irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), |
264 | IRQ_TYPE_EDGE_RISING); | 264 | IRQ_TYPE_EDGE_RISING); |
265 | } | 265 | } |
266 | return IRQ_HANDLED; | 266 | return IRQ_HANDLED; |
267 | } | 267 | } |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index bdc0ac8dc21f..65d24204937a 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
@@ -279,10 +279,10 @@ static void __init voiceblue_init(void) | |||
279 | gpio_request(13, "16C554 irq"); | 279 | gpio_request(13, "16C554 irq"); |
280 | gpio_request(14, "16C554 irq"); | 280 | gpio_request(14, "16C554 irq"); |
281 | gpio_request(15, "16C554 irq"); | 281 | gpio_request(15, "16C554 irq"); |
282 | set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); | 282 | irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); |
283 | set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); | 283 | irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); |
284 | set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); | 284 | irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); |
285 | set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); | 285 | irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); |
286 | 286 | ||
287 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); | 287 | platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); |
288 | omap_board_config = voiceblue_config; | 288 | omap_board_config = voiceblue_config; |
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c index 0ace7998aaa5..cddbf8b089ce 100644 --- a/arch/arm/mach-omap1/fpga.c +++ b/arch/arm/mach-omap1/fpga.c | |||
@@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void) | |||
156 | * The touchscreen interrupt is level-sensitive, so | 156 | * The touchscreen interrupt is level-sensitive, so |
157 | * we'll use the regular mask_ack routine for it. | 157 | * we'll use the regular mask_ack routine for it. |
158 | */ | 158 | */ |
159 | set_irq_chip(i, &omap_fpga_irq_ack); | 159 | irq_set_chip(i, &omap_fpga_irq_ack); |
160 | } | 160 | } |
161 | else { | 161 | else { |
162 | /* | 162 | /* |
163 | * All FPGA interrupts except the touchscreen are | 163 | * All FPGA interrupts except the touchscreen are |
164 | * edge-sensitive, so we won't mask them. | 164 | * edge-sensitive, so we won't mask them. |
165 | */ | 165 | */ |
166 | set_irq_chip(i, &omap_fpga_irq); | 166 | irq_set_chip(i, &omap_fpga_irq); |
167 | } | 167 | } |
168 | 168 | ||
169 | set_irq_handler(i, handle_edge_irq); | 169 | irq_set_handler(i, handle_edge_irq); |
170 | set_irq_flags(i, IRQF_VALID); | 170 | set_irq_flags(i, IRQF_VALID); |
171 | } | 171 | } |
172 | 172 | ||
@@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void) | |||
183 | return; | 183 | return; |
184 | } | 184 | } |
185 | gpio_direction_input(13); | 185 | gpio_direction_input(13); |
186 | set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); | 186 | irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); |
187 | set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); | 187 | irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); |
188 | } | 188 | } |
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 731dd33bff51..5d3da7a63af3 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
@@ -230,8 +230,8 @@ void __init omap_init_irq(void) | |||
230 | irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); | 230 | irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); |
231 | omap_irq_set_cfg(j, 0, 0, irq_trigger); | 231 | omap_irq_set_cfg(j, 0, 0, irq_trigger); |
232 | 232 | ||
233 | set_irq_chip(j, &omap_irq_chip); | 233 | irq_set_chip_and_handler(j, &omap_irq_chip, |
234 | set_irq_handler(j, handle_level_irq); | 234 | handle_level_irq); |
235 | set_irq_flags(j, IRQF_VALID); | 235 | set_irq_flags(j, IRQF_VALID); |
236 | } | 236 | } |
237 | } | 237 | } |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 493505c3b2f5..130034bf01d5 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -743,7 +743,7 @@ static int __init gpmc_init(void) | |||
743 | /* initalize the irq_chained */ | 743 | /* initalize the irq_chained */ |
744 | irq = OMAP_GPMC_IRQ_BASE; | 744 | irq = OMAP_GPMC_IRQ_BASE; |
745 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | 745 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { |
746 | set_irq_chip_and_handler(irq, &dummy_irq_chip, | 746 | irq_set_chip_and_handler(irq, &dummy_irq_chip, |
747 | handle_simple_irq); | 747 | handle_simple_irq); |
748 | set_irq_flags(irq, IRQF_VALID); | 748 | set_irq_flags(irq, IRQF_VALID); |
749 | irq++; | 749 | irq++; |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bc524b94fd59..237e4530abf2 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
@@ -223,8 +223,7 @@ void __init omap_init_irq(void) | |||
223 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); | 223 | nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); |
224 | 224 | ||
225 | for (i = 0; i < nr_of_irqs; i++) { | 225 | for (i = 0; i < nr_of_irqs; i++) { |
226 | set_irq_chip(i, &omap_irq_chip); | 226 | irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq); |
227 | set_irq_handler(i, handle_level_irq); | ||
228 | set_irq_flags(i, IRQF_VALID); | 227 | set_irq_flags(i, IRQF_VALID); |
229 | } | 228 | } |
230 | } | 229 | } |
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index c10a11715376..b7d4591214e0 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c | |||
@@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void) | |||
213 | pin = DB88F5281_PCI_SLOT0_IRQ_PIN; | 213 | pin = DB88F5281_PCI_SLOT0_IRQ_PIN; |
214 | if (gpio_request(pin, "PCI Int1") == 0) { | 214 | if (gpio_request(pin, "PCI Int1") == 0) { |
215 | if (gpio_direction_input(pin) == 0) { | 215 | if (gpio_direction_input(pin) == 0) { |
216 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 216 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
217 | } else { | 217 | } else { |
218 | printk(KERN_ERR "db88f5281_pci_preinit faield to " | 218 | printk(KERN_ERR "db88f5281_pci_preinit faield to " |
219 | "set_irq_type pin %d\n", pin); | 219 | "set_irq_type pin %d\n", pin); |
@@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void) | |||
226 | pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; | 226 | pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; |
227 | if (gpio_request(pin, "PCI Int2") == 0) { | 227 | if (gpio_request(pin, "PCI Int2") == 0) { |
228 | if (gpio_direction_input(pin) == 0) { | 228 | if (gpio_direction_input(pin) == 0) { |
229 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 229 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
230 | } else { | 230 | } else { |
231 | printk(KERN_ERR "db88f5281_pci_preinit faield " | 231 | printk(KERN_ERR "db88f5281_pci_preinit faield " |
232 | "to set_irq_type pin %d\n", pin); | 232 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index ed85891f8699..43cf8bc9767b 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c | |||
@@ -34,8 +34,8 @@ void __init orion5x_init_irq(void) | |||
34 | * Initialize gpiolib for GPIOs 0-31. | 34 | * Initialize gpiolib for GPIOs 0-31. |
35 | */ | 35 | */ |
36 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); | 36 | orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); |
37 | set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); | 37 | irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); |
38 | set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); | 38 | irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); |
39 | set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); | 39 | irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); |
40 | set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); | 40 | irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); |
41 | } | 41 | } |
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index 67ec6959b267..4fc46772a087 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c | |||
@@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void) | |||
148 | pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; | 148 | pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; |
149 | if (gpio_request(pin, "PCI IntA") == 0) { | 149 | if (gpio_request(pin, "PCI IntA") == 0) { |
150 | if (gpio_direction_input(pin) == 0) { | 150 | if (gpio_direction_input(pin) == 0) { |
151 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 151 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
152 | } else { | 152 | } else { |
153 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " | 153 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " |
154 | "set_irq_type pin %d\n", pin); | 154 | "set_irq_type pin %d\n", pin); |
@@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void) | |||
161 | pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; | 161 | pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; |
162 | if (gpio_request(pin, "PCI IntB") == 0) { | 162 | if (gpio_request(pin, "PCI IntB") == 0) { |
163 | if (gpio_direction_input(pin) == 0) { | 163 | if (gpio_direction_input(pin) == 0) { |
164 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 164 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
165 | } else { | 165 | } else { |
166 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " | 166 | printk(KERN_ERR "rd88f5182_pci_preinit faield to " |
167 | "set_irq_type pin %d\n", pin); | 167 | "set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 5653ee6c71d8..616004143912 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c | |||
@@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void) | |||
88 | pin = TSP2_PCI_SLOT0_IRQ_PIN; | 88 | pin = TSP2_PCI_SLOT0_IRQ_PIN; |
89 | if (gpio_request(pin, "PCI Int1") == 0) { | 89 | if (gpio_request(pin, "PCI Int1") == 0) { |
90 | if (gpio_direction_input(pin) == 0) { | 90 | if (gpio_direction_input(pin) == 0) { |
91 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 91 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
92 | } else { | 92 | } else { |
93 | printk(KERN_ERR "tsp2_pci_preinit failed " | 93 | printk(KERN_ERR "tsp2_pci_preinit failed " |
94 | "to set_irq_type pin %d\n", pin); | 94 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index 8bbd27ea6735..f0f43e13ac87 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c | |||
@@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void) | |||
117 | pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; | 117 | pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; |
118 | if (gpio_request(pin, "PCI Int1") == 0) { | 118 | if (gpio_request(pin, "PCI Int1") == 0) { |
119 | if (gpio_direction_input(pin) == 0) { | 119 | if (gpio_direction_input(pin) == 0) { |
120 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 120 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
121 | } else { | 121 | } else { |
122 | printk(KERN_ERR "qnap_ts209_pci_preinit failed to " | 122 | printk(KERN_ERR "qnap_ts209_pci_preinit failed to " |
123 | "set_irq_type pin %d\n", pin); | 123 | "set_irq_type pin %d\n", pin); |
@@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void) | |||
131 | pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; | 131 | pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; |
132 | if (gpio_request(pin, "PCI Int2") == 0) { | 132 | if (gpio_request(pin, "PCI Int2") == 0) { |
133 | if (gpio_direction_input(pin) == 0) { | 133 | if (gpio_direction_input(pin) == 0) { |
134 | set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); | 134 | irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
135 | } else { | 135 | } else { |
136 | printk(KERN_ERR "qnap_ts209_pci_preinit failed " | 136 | printk(KERN_ERR "qnap_ts209_pci_preinit failed " |
137 | "to set_irq_type pin %d\n", pin); | 137 | "to set_irq_type pin %d\n", pin); |
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 8554707d20a9..edb1dd2d1611 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c | |||
@@ -402,7 +402,7 @@ static void ts78xx_fpga_supports(void) | |||
402 | /* enable devices if magic matches */ | 402 | /* enable devices if magic matches */ |
403 | switch ((ts78xx_fpga.id >> 8) & 0xffffff) { | 403 | switch ((ts78xx_fpga.id >> 8) & 0xffffff) { |
404 | case TS7800_FPGA_MAGIC: | 404 | case TS7800_FPGA_MAGIC: |
405 | printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n", | 405 | pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n", |
406 | ts78xx_fpga.id & 0xff); | 406 | ts78xx_fpga.id & 0xff); |
407 | ts78xx_fpga.supports.ts_rtc.present = 1; | 407 | ts78xx_fpga.supports.ts_rtc.present = 1; |
408 | ts78xx_fpga.supports.ts_nand.present = 1; | 408 | ts78xx_fpga.supports.ts_nand.present = 1; |
@@ -423,7 +423,7 @@ static int ts78xx_fpga_load_devices(void) | |||
423 | if (ts78xx_fpga.supports.ts_rtc.present == 1) { | 423 | if (ts78xx_fpga.supports.ts_rtc.present == 1) { |
424 | tmp = ts78xx_ts_rtc_load(); | 424 | tmp = ts78xx_ts_rtc_load(); |
425 | if (tmp) { | 425 | if (tmp) { |
426 | printk(KERN_INFO "TS-78xx: RTC not registered\n"); | 426 | pr_info("TS-78xx: RTC not registered\n"); |
427 | ts78xx_fpga.supports.ts_rtc.present = 0; | 427 | ts78xx_fpga.supports.ts_rtc.present = 0; |
428 | } | 428 | } |
429 | ret |= tmp; | 429 | ret |= tmp; |
@@ -431,7 +431,7 @@ static int ts78xx_fpga_load_devices(void) | |||
431 | if (ts78xx_fpga.supports.ts_nand.present == 1) { | 431 | if (ts78xx_fpga.supports.ts_nand.present == 1) { |
432 | tmp = ts78xx_ts_nand_load(); | 432 | tmp = ts78xx_ts_nand_load(); |
433 | if (tmp) { | 433 | if (tmp) { |
434 | printk(KERN_INFO "TS-78xx: NAND not registered\n"); | 434 | pr_info("TS-78xx: NAND not registered\n"); |
435 | ts78xx_fpga.supports.ts_nand.present = 0; | 435 | ts78xx_fpga.supports.ts_nand.present = 0; |
436 | } | 436 | } |
437 | ret |= tmp; | 437 | ret |= tmp; |
@@ -439,7 +439,7 @@ static int ts78xx_fpga_load_devices(void) | |||
439 | if (ts78xx_fpga.supports.ts_rng.present == 1) { | 439 | if (ts78xx_fpga.supports.ts_rng.present == 1) { |
440 | tmp = ts78xx_ts_rng_load(); | 440 | tmp = ts78xx_ts_rng_load(); |
441 | if (tmp) { | 441 | if (tmp) { |
442 | printk(KERN_INFO "TS-78xx: RNG not registered\n"); | 442 | pr_info("TS-78xx: RNG not registered\n"); |
443 | ts78xx_fpga.supports.ts_rng.present = 0; | 443 | ts78xx_fpga.supports.ts_rng.present = 0; |
444 | } | 444 | } |
445 | ret |= tmp; | 445 | ret |= tmp; |
@@ -466,7 +466,7 @@ static int ts78xx_fpga_load(void) | |||
466 | { | 466 | { |
467 | ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); | 467 | ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); |
468 | 468 | ||
469 | printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", | 469 | pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", |
470 | (ts78xx_fpga.id >> 8) & 0xffffff, | 470 | (ts78xx_fpga.id >> 8) & 0xffffff, |
471 | ts78xx_fpga.id & 0xff); | 471 | ts78xx_fpga.id & 0xff); |
472 | 472 | ||
@@ -494,7 +494,7 @@ static int ts78xx_fpga_unload(void) | |||
494 | * UrJTAG SVN since r1381 can be used to reprogram the FPGA | 494 | * UrJTAG SVN since r1381 can be used to reprogram the FPGA |
495 | */ | 495 | */ |
496 | if (ts78xx_fpga.id != fpga_id) { | 496 | if (ts78xx_fpga.id != fpga_id) { |
497 | printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n" | 497 | pr_err("TS-78xx FPGA: magic/rev mismatch\n" |
498 | "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", | 498 | "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", |
499 | (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, | 499 | (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, |
500 | (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); | 500 | (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); |
@@ -525,7 +525,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, | |||
525 | int value, ret; | 525 | int value, ret; |
526 | 526 | ||
527 | if (ts78xx_fpga.state < 0) { | 527 | if (ts78xx_fpga.state < 0) { |
528 | printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n"); | 528 | pr_err("TS-78xx FPGA: borked, you must powercycle asap\n"); |
529 | return -EBUSY; | 529 | return -EBUSY; |
530 | } | 530 | } |
531 | 531 | ||
@@ -534,7 +534,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj, | |||
534 | else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) | 534 | else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) |
535 | value = 0; | 535 | value = 0; |
536 | else { | 536 | else { |
537 | printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n"); | 537 | pr_err("ts78xx_fpga_store: Invalid value\n"); |
538 | return -EINVAL; | 538 | return -EINVAL; |
539 | } | 539 | } |
540 | 540 | ||
@@ -616,7 +616,7 @@ static void __init ts78xx_init(void) | |||
616 | ret = ts78xx_fpga_load(); | 616 | ret = ts78xx_fpga_load(); |
617 | ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); | 617 | ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); |
618 | if (ret) | 618 | if (ret) |
619 | printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); | 619 | pr_err("sysfs_create_file failed: %d\n", ret); |
620 | } | 620 | } |
621 | 621 | ||
622 | MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") | 622 | MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") |
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c index c69c180aec76..7608c7a288cf 100644 --- a/arch/arm/mach-pnx4008/irq.c +++ b/arch/arm/mach-pnx4008/irq.c | |||
@@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) | |||
58 | case IRQ_TYPE_EDGE_RISING: | 58 | case IRQ_TYPE_EDGE_RISING: |
59 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ | 59 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
60 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ | 60 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ |
61 | set_irq_handler(d->irq, handle_edge_irq); | 61 | irq_set_handler(d->irq, handle_edge_irq); |
62 | break; | 62 | break; |
63 | case IRQ_TYPE_EDGE_FALLING: | 63 | case IRQ_TYPE_EDGE_FALLING: |
64 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ | 64 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ |
65 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ | 65 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ |
66 | set_irq_handler(d->irq, handle_edge_irq); | 66 | irq_set_handler(d->irq, handle_edge_irq); |
67 | break; | 67 | break; |
68 | case IRQ_TYPE_LEVEL_LOW: | 68 | case IRQ_TYPE_LEVEL_LOW: |
69 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ | 69 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
70 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ | 70 | __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ |
71 | set_irq_handler(d->irq, handle_level_irq); | 71 | irq_set_handler(d->irq, handle_level_irq); |
72 | break; | 72 | break; |
73 | case IRQ_TYPE_LEVEL_HIGH: | 73 | case IRQ_TYPE_LEVEL_HIGH: |
74 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ | 74 | __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ |
75 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ | 75 | __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ |
76 | set_irq_handler(d->irq, handle_level_irq); | 76 | irq_set_handler(d->irq, handle_level_irq); |
77 | break; | 77 | break; |
78 | 78 | ||
79 | /* IRQ_TYPE_EDGE_BOTH is not supported */ | 79 | /* IRQ_TYPE_EDGE_BOTH is not supported */ |
@@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void) | |||
98 | /* configure IRQ's */ | 98 | /* configure IRQ's */ |
99 | for (i = 0; i < NR_IRQS; i++) { | 99 | for (i = 0; i < NR_IRQS; i++) { |
100 | set_irq_flags(i, IRQF_VALID); | 100 | set_irq_flags(i, IRQF_VALID); |
101 | set_irq_chip(i, &pnx4008_irq_chip); | 101 | irq_set_chip(i, &pnx4008_irq_chip); |
102 | pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); | 102 | pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); |
103 | } | 103 | } |
104 | 104 | ||
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 3499fada73ae..4cb069fd9af2 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c | |||
@@ -128,8 +128,8 @@ static int am200_init_gpio_regs(struct metronomefb_par *par) | |||
128 | return 0; | 128 | return 0; |
129 | 129 | ||
130 | err_req_gpio: | 130 | err_req_gpio: |
131 | while (i > 0) | 131 | while (--i >= 0) |
132 | gpio_free(gpios[i--]); | 132 | gpio_free(gpios[i]); |
133 | 133 | ||
134 | return err; | 134 | return err; |
135 | } | 135 | } |
@@ -194,7 +194,7 @@ static struct notifier_block am200_fb_notif = { | |||
194 | }; | 194 | }; |
195 | 195 | ||
196 | /* this gets called as part of our init. these steps must be done now so | 196 | /* this gets called as part of our init. these steps must be done now so |
197 | * that we can use set_pxa_fb_info */ | 197 | * that we can use pxa_set_fb_info */ |
198 | static void __init am200_presetup_fb(void) | 198 | static void __init am200_presetup_fb(void) |
199 | { | 199 | { |
200 | int fw; | 200 | int fw; |
@@ -249,7 +249,7 @@ static void __init am200_presetup_fb(void) | |||
249 | /* we divide since we told the LCD controller we're 16bpp */ | 249 | /* we divide since we told the LCD controller we're 16bpp */ |
250 | am200_fb_info.modes->xres /= 2; | 250 | am200_fb_info.modes->xres /= 2; |
251 | 251 | ||
252 | set_pxa_fb_info(&am200_fb_info); | 252 | pxa_set_fb_info(NULL, &am200_fb_info); |
253 | 253 | ||
254 | } | 254 | } |
255 | 255 | ||
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 993d75e66390..fa8bad235d9f 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c | |||
@@ -125,10 +125,7 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par) | |||
125 | if (err) { | 125 | if (err) { |
126 | dev_err(&am300_device->dev, "failed requesting " | 126 | dev_err(&am300_device->dev, "failed requesting " |
127 | "gpio %d, err=%d\n", i, err); | 127 | "gpio %d, err=%d\n", i, err); |
128 | while (i >= DB0_GPIO_PIN) | 128 | goto err_req_gpio2; |
129 | gpio_free(i--); | ||
130 | i = ARRAY_SIZE(gpios) - 1; | ||
131 | goto err_req_gpio; | ||
132 | } | 129 | } |
133 | } | 130 | } |
134 | 131 | ||
@@ -159,9 +156,13 @@ static int am300_init_gpio_regs(struct broadsheetfb_par *par) | |||
159 | 156 | ||
160 | return 0; | 157 | return 0; |
161 | 158 | ||
159 | err_req_gpio2: | ||
160 | while (--i >= DB0_GPIO_PIN) | ||
161 | gpio_free(i); | ||
162 | i = ARRAY_SIZE(gpios); | ||
162 | err_req_gpio: | 163 | err_req_gpio: |
163 | while (i > 0) | 164 | while (--i >= 0) |
164 | gpio_free(gpios[i--]); | 165 | gpio_free(gpios[i]); |
165 | 166 | ||
166 | return err; | 167 | return err; |
167 | } | 168 | } |
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index d2af73321dae..bfbecec6d05f 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c | |||
@@ -263,7 +263,7 @@ static void __init balloon3_lcd_init(void) | |||
263 | } | 263 | } |
264 | 264 | ||
265 | balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power; | 265 | balloon3_lcd_screen.pxafb_backlight_power = balloon3_backlight_power; |
266 | set_pxa_fb_info(&balloon3_lcd_screen); | 266 | pxa_set_fb_info(NULL, &balloon3_lcd_screen); |
267 | return; | 267 | return; |
268 | 268 | ||
269 | err2: | 269 | err2: |
@@ -527,13 +527,13 @@ static void __init balloon3_init_irq(void) | |||
527 | pxa27x_init_irq(); | 527 | pxa27x_init_irq(); |
528 | /* setup extra Balloon3 irqs */ | 528 | /* setup extra Balloon3 irqs */ |
529 | for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { | 529 | for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { |
530 | set_irq_chip(irq, &balloon3_irq_chip); | 530 | irq_set_chip_and_handler(irq, &balloon3_irq_chip, |
531 | set_irq_handler(irq, handle_level_irq); | 531 | handle_level_irq); |
532 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 532 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
533 | } | 533 | } |
534 | 534 | ||
535 | set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); | 535 | irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); |
536 | set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); | 536 | irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); |
537 | 537 | ||
538 | pr_debug("%s: chained handler installed - irq %d automatically " | 538 | pr_debug("%s: chained handler installed - irq %d automatically " |
539 | "enabled\n", __func__, BALLOON3_AUX_NIRQ); | 539 | "enabled\n", __func__, BALLOON3_AUX_NIRQ); |
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index a2380cd76f80..8b1a30959fae 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c | |||
@@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio) | |||
70 | 70 | ||
71 | cmx2xx_it8152_irq_gpio = irq_gpio; | 71 | cmx2xx_it8152_irq_gpio = irq_gpio; |
72 | 72 | ||
73 | set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); | 73 | irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); |
74 | 74 | ||
75 | set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux); | 75 | irq_set_chained_handler(gpio_to_irq(irq_gpio), |
76 | cmx2xx_it8152_irq_demux); | ||
76 | } | 77 | } |
77 | 78 | ||
78 | #ifdef CONFIG_PM | 79 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index b734d8468168..8225e2e58c6e 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c | |||
@@ -379,7 +379,7 @@ __setup("monitor=", cmx2xx_set_display); | |||
379 | 379 | ||
380 | static void __init cmx2xx_init_display(void) | 380 | static void __init cmx2xx_init_display(void) |
381 | { | 381 | { |
382 | set_pxa_fb_info(cmx2xx_display); | 382 | pxa_set_fb_info(NULL, cmx2xx_display); |
383 | } | 383 | } |
384 | #else | 384 | #else |
385 | static inline void cmx2xx_init_display(void) {} | 385 | static inline void cmx2xx_init_display(void) {} |
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index bfca7ed2fea3..b2248e76ec8b 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
@@ -296,7 +296,7 @@ static struct pxafb_mach_info cm_x300_lcd = { | |||
296 | 296 | ||
297 | static void __init cm_x300_init_lcd(void) | 297 | static void __init cm_x300_init_lcd(void) |
298 | { | 298 | { |
299 | set_pxa_fb_info(&cm_x300_lcd); | 299 | pxa_set_fb_info(NULL, &cm_x300_lcd); |
300 | } | 300 | } |
301 | #else | 301 | #else |
302 | static inline void cm_x300_init_lcd(void) {} | 302 | static inline void cm_x300_init_lcd(void) {} |
@@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void) | |||
765 | { | 765 | { |
766 | pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); | 766 | pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); |
767 | i2c_register_board_info(1, &cm_x300_pmic_info, 1); | 767 | i2c_register_board_info(1, &cm_x300_pmic_info, 1); |
768 | set_irq_wake(IRQ_WAKEUP0, 1); | 768 | irq_set_irq_wake(IRQ_WAKEUP0, 1); |
769 | } | 769 | } |
770 | 770 | ||
771 | static void __init cm_x300_init_wi2wi(void) | 771 | static void __init cm_x300_init_wi2wi(void) |
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c index ee797397dc5b..44c1b77ece67 100644 --- a/arch/arm/mach-pxa/colibri-pxa270-income.c +++ b/arch/arm/mach-pxa/colibri-pxa270-income.c | |||
@@ -175,7 +175,7 @@ static struct pxafb_mach_info income_lcd_screen = { | |||
175 | 175 | ||
176 | static void __init income_lcd_init(void) | 176 | static void __init income_lcd_init(void) |
177 | { | 177 | { |
178 | set_pxa_fb_info(&income_lcd_screen); | 178 | pxa_set_fb_info(NULL, &income_lcd_screen); |
179 | } | 179 | } |
180 | #else | 180 | #else |
181 | static inline void income_lcd_init(void) {} | 181 | static inline void income_lcd_init(void) {} |
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index 96b2d9fbfef0..3f9be419959d 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c | |||
@@ -105,7 +105,7 @@ void __init colibri_pxa3xx_init_lcd(int bl_pin) | |||
105 | lcd_bl_pin = bl_pin; | 105 | lcd_bl_pin = bl_pin; |
106 | gpio_request(bl_pin, "lcd backlight"); | 106 | gpio_request(bl_pin, "lcd backlight"); |
107 | gpio_direction_output(bl_pin, 0); | 107 | gpio_direction_output(bl_pin, 0); |
108 | set_pxa_fb_info(&sharp_lq43_info); | 108 | pxa_set_fb_info(NULL, &sharp_lq43_info); |
109 | } | 109 | } |
110 | #endif | 110 | #endif |
111 | 111 | ||
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index d4e705caefea..3a5507e31919 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
@@ -462,7 +462,6 @@ static struct pxaficp_platform_data corgi_ficp_platform_data = { | |||
462 | * USB Device Controller | 462 | * USB Device Controller |
463 | */ | 463 | */ |
464 | static struct pxa2xx_udc_mach_info udc_info __initdata = { | 464 | static struct pxa2xx_udc_mach_info udc_info __initdata = { |
465 | .gpio_vbus = -1, | ||
466 | /* no connect GPIO; corgi can't tell connection status */ | 465 | /* no connect GPIO; corgi can't tell connection status */ |
467 | .gpio_pullup = CORGI_GPIO_USB_PULLUP, | 466 | .gpio_pullup = CORGI_GPIO_USB_PULLUP, |
468 | }; | 467 | }; |
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index c4bf08b3eb61..2e0425404de5 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
@@ -90,7 +90,6 @@ void __init pxa_set_mci_info(struct pxamci_platform_data *info) | |||
90 | 90 | ||
91 | static struct pxa2xx_udc_mach_info pxa_udc_info = { | 91 | static struct pxa2xx_udc_mach_info pxa_udc_info = { |
92 | .gpio_pullup = -1, | 92 | .gpio_pullup = -1, |
93 | .gpio_vbus = -1, | ||
94 | }; | 93 | }; |
95 | 94 | ||
96 | void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) | 95 | void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info) |
@@ -188,16 +187,12 @@ struct platform_device pxa_device_fb = { | |||
188 | .resource = pxafb_resources, | 187 | .resource = pxafb_resources, |
189 | }; | 188 | }; |
190 | 189 | ||
191 | void __init set_pxa_fb_info(struct pxafb_mach_info *info) | 190 | void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info) |
192 | { | 191 | { |
192 | pxa_device_fb.dev.parent = parent; | ||
193 | pxa_register_device(&pxa_device_fb, info); | 193 | pxa_register_device(&pxa_device_fb, info); |
194 | } | 194 | } |
195 | 195 | ||
196 | void __init set_pxa_fb_parent(struct device *parent_dev) | ||
197 | { | ||
198 | pxa_device_fb.dev.parent = parent_dev; | ||
199 | } | ||
200 | |||
201 | static struct resource pxa_resource_ffuart[] = { | 196 | static struct resource pxa_resource_ffuart[] = { |
202 | { | 197 | { |
203 | .start = 0x40100000, | 198 | .start = 0x40100000, |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index b411d7cbf5a1..f8a6e9d79a3a 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
@@ -689,7 +689,7 @@ static struct pxafb_mach_info em_x270_lcd = { | |||
689 | 689 | ||
690 | static void __init em_x270_init_lcd(void) | 690 | static void __init em_x270_init_lcd(void) |
691 | { | 691 | { |
692 | set_pxa_fb_info(&em_x270_lcd); | 692 | pxa_set_fb_info(NULL, &em_x270_lcd); |
693 | } | 693 | } |
694 | #else | 694 | #else |
695 | static inline void em_x270_init_lcd(void) {} | 695 | static inline void em_x270_init_lcd(void) {} |
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index edca0a043293..2e3970fdde0b 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/mfd/t7l66xb.h> | 20 | #include <linux/mfd/t7l66xb.h> |
21 | #include <linux/mtd/nand.h> | 21 | #include <linux/mtd/nand.h> |
22 | #include <linux/mtd/partitions.h> | 22 | #include <linux/mtd/partitions.h> |
23 | #include <linux/usb/gpio_vbus.h> | ||
23 | 24 | ||
24 | #include <video/w100fb.h> | 25 | #include <video/w100fb.h> |
25 | 26 | ||
@@ -51,12 +52,20 @@ void __init eseries_fixup(struct machine_desc *desc, | |||
51 | mi->bank[0].size = (64*1024*1024); | 52 | mi->bank[0].size = (64*1024*1024); |
52 | } | 53 | } |
53 | 54 | ||
54 | struct pxa2xx_udc_mach_info e7xx_udc_mach_info = { | 55 | struct gpio_vbus_mach_info e7xx_udc_info = { |
55 | .gpio_vbus = GPIO_E7XX_USB_DISC, | 56 | .gpio_vbus = GPIO_E7XX_USB_DISC, |
56 | .gpio_pullup = GPIO_E7XX_USB_PULLUP, | 57 | .gpio_pullup = GPIO_E7XX_USB_PULLUP, |
57 | .gpio_pullup_inverted = 1 | 58 | .gpio_pullup_inverted = 1 |
58 | }; | 59 | }; |
59 | 60 | ||
61 | static struct platform_device e7xx_gpio_vbus = { | ||
62 | .name = "gpio-vbus", | ||
63 | .id = -1, | ||
64 | .dev = { | ||
65 | .platform_data = &e7xx_udc_info, | ||
66 | }, | ||
67 | }; | ||
68 | |||
60 | struct pxaficp_platform_data e7xx_ficp_platform_data = { | 69 | struct pxaficp_platform_data e7xx_ficp_platform_data = { |
61 | .gpio_pwdown = GPIO_E7XX_IR_OFF, | 70 | .gpio_pwdown = GPIO_E7XX_IR_OFF, |
62 | .transceiver_cap = IR_SIRMODE | IR_OFF, | 71 | .transceiver_cap = IR_SIRMODE | IR_OFF, |
@@ -165,6 +174,7 @@ static struct platform_device e330_tc6387xb_device = { | |||
165 | 174 | ||
166 | static struct platform_device *e330_devices[] __initdata = { | 175 | static struct platform_device *e330_devices[] __initdata = { |
167 | &e330_tc6387xb_device, | 176 | &e330_tc6387xb_device, |
177 | &e7xx_gpio_vbus, | ||
168 | }; | 178 | }; |
169 | 179 | ||
170 | static void __init e330_init(void) | 180 | static void __init e330_init(void) |
@@ -175,7 +185,6 @@ static void __init e330_init(void) | |||
175 | eseries_register_clks(); | 185 | eseries_register_clks(); |
176 | eseries_get_tmio_gpios(); | 186 | eseries_get_tmio_gpios(); |
177 | platform_add_devices(ARRAY_AND_SIZE(e330_devices)); | 187 | platform_add_devices(ARRAY_AND_SIZE(e330_devices)); |
178 | pxa_set_udc_info(&e7xx_udc_mach_info); | ||
179 | } | 188 | } |
180 | 189 | ||
181 | MACHINE_START(E330, "Toshiba e330") | 190 | MACHINE_START(E330, "Toshiba e330") |
@@ -214,6 +223,7 @@ static struct platform_device e350_t7l66xb_device = { | |||
214 | 223 | ||
215 | static struct platform_device *e350_devices[] __initdata = { | 224 | static struct platform_device *e350_devices[] __initdata = { |
216 | &e350_t7l66xb_device, | 225 | &e350_t7l66xb_device, |
226 | &e7xx_gpio_vbus, | ||
217 | }; | 227 | }; |
218 | 228 | ||
219 | static void __init e350_init(void) | 229 | static void __init e350_init(void) |
@@ -224,7 +234,6 @@ static void __init e350_init(void) | |||
224 | eseries_register_clks(); | 234 | eseries_register_clks(); |
225 | eseries_get_tmio_gpios(); | 235 | eseries_get_tmio_gpios(); |
226 | platform_add_devices(ARRAY_AND_SIZE(e350_devices)); | 236 | platform_add_devices(ARRAY_AND_SIZE(e350_devices)); |
227 | pxa_set_udc_info(&e7xx_udc_mach_info); | ||
228 | } | 237 | } |
229 | 238 | ||
230 | MACHINE_START(E350, "Toshiba e350") | 239 | MACHINE_START(E350, "Toshiba e350") |
@@ -333,6 +342,7 @@ static struct platform_device e400_t7l66xb_device = { | |||
333 | 342 | ||
334 | static struct platform_device *e400_devices[] __initdata = { | 343 | static struct platform_device *e400_devices[] __initdata = { |
335 | &e400_t7l66xb_device, | 344 | &e400_t7l66xb_device, |
345 | &e7xx_gpio_vbus, | ||
336 | }; | 346 | }; |
337 | 347 | ||
338 | static void __init e400_init(void) | 348 | static void __init e400_init(void) |
@@ -344,9 +354,8 @@ static void __init e400_init(void) | |||
344 | /* Fixme - e400 may have a switched clock */ | 354 | /* Fixme - e400 may have a switched clock */ |
345 | eseries_register_clks(); | 355 | eseries_register_clks(); |
346 | eseries_get_tmio_gpios(); | 356 | eseries_get_tmio_gpios(); |
347 | set_pxa_fb_info(&e400_pxafb_mach_info); | 357 | pxa_set_fb_info(NULL, &e400_pxafb_mach_info); |
348 | platform_add_devices(ARRAY_AND_SIZE(e400_devices)); | 358 | platform_add_devices(ARRAY_AND_SIZE(e400_devices)); |
349 | pxa_set_udc_info(&e7xx_udc_mach_info); | ||
350 | } | 359 | } |
351 | 360 | ||
352 | MACHINE_START(E400, "Toshiba e400") | 361 | MACHINE_START(E400, "Toshiba e400") |
@@ -519,6 +528,7 @@ static struct platform_device e740_t7l66xb_device = { | |||
519 | static struct platform_device *e740_devices[] __initdata = { | 528 | static struct platform_device *e740_devices[] __initdata = { |
520 | &e740_fb_device, | 529 | &e740_fb_device, |
521 | &e740_t7l66xb_device, | 530 | &e740_t7l66xb_device, |
531 | &e7xx_gpio_vbus, | ||
522 | }; | 532 | }; |
523 | 533 | ||
524 | static void __init e740_init(void) | 534 | static void __init e740_init(void) |
@@ -532,7 +542,6 @@ static void __init e740_init(void) | |||
532 | "UDCCLK", &pxa25x_device_udc.dev), | 542 | "UDCCLK", &pxa25x_device_udc.dev), |
533 | eseries_get_tmio_gpios(); | 543 | eseries_get_tmio_gpios(); |
534 | platform_add_devices(ARRAY_AND_SIZE(e740_devices)); | 544 | platform_add_devices(ARRAY_AND_SIZE(e740_devices)); |
535 | pxa_set_udc_info(&e7xx_udc_mach_info); | ||
536 | pxa_set_ac97_info(NULL); | 545 | pxa_set_ac97_info(NULL); |
537 | pxa_set_ficp_info(&e7xx_ficp_platform_data); | 546 | pxa_set_ficp_info(&e7xx_ficp_platform_data); |
538 | } | 547 | } |
@@ -711,6 +720,7 @@ static struct platform_device e750_tc6393xb_device = { | |||
711 | static struct platform_device *e750_devices[] __initdata = { | 720 | static struct platform_device *e750_devices[] __initdata = { |
712 | &e750_fb_device, | 721 | &e750_fb_device, |
713 | &e750_tc6393xb_device, | 722 | &e750_tc6393xb_device, |
723 | &e7xx_gpio_vbus, | ||
714 | }; | 724 | }; |
715 | 725 | ||
716 | static void __init e750_init(void) | 726 | static void __init e750_init(void) |
@@ -723,7 +733,6 @@ static void __init e750_init(void) | |||
723 | "GPIO11_CLK", NULL), | 733 | "GPIO11_CLK", NULL), |
724 | eseries_get_tmio_gpios(); | 734 | eseries_get_tmio_gpios(); |
725 | platform_add_devices(ARRAY_AND_SIZE(e750_devices)); | 735 | platform_add_devices(ARRAY_AND_SIZE(e750_devices)); |
726 | pxa_set_udc_info(&e7xx_udc_mach_info); | ||
727 | pxa_set_ac97_info(NULL); | 736 | pxa_set_ac97_info(NULL); |
728 | pxa_set_ficp_info(&e7xx_ficp_platform_data); | 737 | pxa_set_ficp_info(&e7xx_ficp_platform_data); |
729 | } | 738 | } |
@@ -873,12 +882,21 @@ static struct platform_device e800_fb_device = { | |||
873 | 882 | ||
874 | /* --------------------------- UDC definitions --------------------------- */ | 883 | /* --------------------------- UDC definitions --------------------------- */ |
875 | 884 | ||
876 | static struct pxa2xx_udc_mach_info e800_udc_mach_info = { | 885 | static struct gpio_vbus_mach_info e800_udc_info = { |
877 | .gpio_vbus = GPIO_E800_USB_DISC, | 886 | .gpio_vbus = GPIO_E800_USB_DISC, |
878 | .gpio_pullup = GPIO_E800_USB_PULLUP, | 887 | .gpio_pullup = GPIO_E800_USB_PULLUP, |
879 | .gpio_pullup_inverted = 1 | 888 | .gpio_pullup_inverted = 1 |
880 | }; | 889 | }; |
881 | 890 | ||
891 | static struct platform_device e800_gpio_vbus = { | ||
892 | .name = "gpio-vbus", | ||
893 | .id = -1, | ||
894 | .dev = { | ||
895 | .platform_data = &e800_udc_info, | ||
896 | }, | ||
897 | }; | ||
898 | |||
899 | |||
882 | /* ----------------- e800 tc6393xb parameters ------------------ */ | 900 | /* ----------------- e800 tc6393xb parameters ------------------ */ |
883 | 901 | ||
884 | static struct tc6393xb_platform_data e800_tc6393xb_info = { | 902 | static struct tc6393xb_platform_data e800_tc6393xb_info = { |
@@ -907,6 +925,7 @@ static struct platform_device e800_tc6393xb_device = { | |||
907 | static struct platform_device *e800_devices[] __initdata = { | 925 | static struct platform_device *e800_devices[] __initdata = { |
908 | &e800_fb_device, | 926 | &e800_fb_device, |
909 | &e800_tc6393xb_device, | 927 | &e800_tc6393xb_device, |
928 | &e800_gpio_vbus, | ||
910 | }; | 929 | }; |
911 | 930 | ||
912 | static void __init e800_init(void) | 931 | static void __init e800_init(void) |
@@ -919,7 +938,6 @@ static void __init e800_init(void) | |||
919 | "GPIO11_CLK", NULL), | 938 | "GPIO11_CLK", NULL), |
920 | eseries_get_tmio_gpios(); | 939 | eseries_get_tmio_gpios(); |
921 | platform_add_devices(ARRAY_AND_SIZE(e800_devices)); | 940 | platform_add_devices(ARRAY_AND_SIZE(e800_devices)); |
922 | pxa_set_udc_info(&e800_udc_mach_info); | ||
923 | pxa_set_ac97_info(NULL); | 941 | pxa_set_ac97_info(NULL); |
924 | } | 942 | } |
925 | 943 | ||
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 93f05e024313..d88aed8fbe15 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c | |||
@@ -783,7 +783,7 @@ static void __init a780_init(void) | |||
783 | 783 | ||
784 | pxa_set_i2c_info(NULL); | 784 | pxa_set_i2c_info(NULL); |
785 | 785 | ||
786 | set_pxa_fb_info(&ezx_fb_info_1); | 786 | pxa_set_fb_info(NULL, &ezx_fb_info_1); |
787 | 787 | ||
788 | pxa_set_keypad_info(&a780_keypad_platform_data); | 788 | pxa_set_keypad_info(&a780_keypad_platform_data); |
789 | 789 | ||
@@ -853,7 +853,7 @@ static void __init e680_init(void) | |||
853 | pxa_set_i2c_info(NULL); | 853 | pxa_set_i2c_info(NULL); |
854 | i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); | 854 | i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); |
855 | 855 | ||
856 | set_pxa_fb_info(&ezx_fb_info_1); | 856 | pxa_set_fb_info(NULL, &ezx_fb_info_1); |
857 | 857 | ||
858 | pxa_set_keypad_info(&e680_keypad_platform_data); | 858 | pxa_set_keypad_info(&e680_keypad_platform_data); |
859 | 859 | ||
@@ -918,7 +918,7 @@ static void __init a1200_init(void) | |||
918 | pxa_set_i2c_info(NULL); | 918 | pxa_set_i2c_info(NULL); |
919 | i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); | 919 | i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); |
920 | 920 | ||
921 | set_pxa_fb_info(&ezx_fb_info_2); | 921 | pxa_set_fb_info(NULL, &ezx_fb_info_2); |
922 | 922 | ||
923 | pxa_set_keypad_info(&a1200_keypad_platform_data); | 923 | pxa_set_keypad_info(&a1200_keypad_platform_data); |
924 | 924 | ||
@@ -1103,7 +1103,7 @@ static void __init a910_init(void) | |||
1103 | pxa_set_i2c_info(NULL); | 1103 | pxa_set_i2c_info(NULL); |
1104 | i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info)); | 1104 | i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info)); |
1105 | 1105 | ||
1106 | set_pxa_fb_info(&ezx_fb_info_2); | 1106 | pxa_set_fb_info(NULL, &ezx_fb_info_2); |
1107 | 1107 | ||
1108 | pxa_set_keypad_info(&a910_keypad_platform_data); | 1108 | pxa_set_keypad_info(&a910_keypad_platform_data); |
1109 | 1109 | ||
@@ -1173,7 +1173,7 @@ static void __init e6_init(void) | |||
1173 | pxa_set_i2c_info(NULL); | 1173 | pxa_set_i2c_info(NULL); |
1174 | i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); | 1174 | i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); |
1175 | 1175 | ||
1176 | set_pxa_fb_info(&ezx_fb_info_2); | 1176 | pxa_set_fb_info(NULL, &ezx_fb_info_2); |
1177 | 1177 | ||
1178 | pxa_set_keypad_info(&e6_keypad_platform_data); | 1178 | pxa_set_keypad_info(&e6_keypad_platform_data); |
1179 | 1179 | ||
@@ -1212,7 +1212,7 @@ static void __init e2_init(void) | |||
1212 | pxa_set_i2c_info(NULL); | 1212 | pxa_set_i2c_info(NULL); |
1213 | i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); | 1213 | i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); |
1214 | 1214 | ||
1215 | set_pxa_fb_info(&ezx_fb_info_2); | 1215 | pxa_set_fb_info(NULL, &ezx_fb_info_2); |
1216 | 1216 | ||
1217 | pxa_set_keypad_info(&e2_keypad_platform_data); | 1217 | pxa_set_keypad_info(&e2_keypad_platform_data); |
1218 | 1218 | ||
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 6fd319ea5284..d65e4bde9b91 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/gpio.h> | 26 | #include <linux/gpio.h> |
27 | #include <linux/err.h> | 27 | #include <linux/err.h> |
28 | #include <linux/clk.h> | 28 | #include <linux/clk.h> |
29 | #include <linux/usb/gpio_vbus.h> | ||
29 | 30 | ||
30 | #include <asm/setup.h> | 31 | #include <asm/setup.h> |
31 | #include <asm/memory.h> | 32 | #include <asm/memory.h> |
@@ -106,14 +107,22 @@ static void __init gumstix_mmc_init(void) | |||
106 | #endif | 107 | #endif |
107 | 108 | ||
108 | #ifdef CONFIG_USB_GADGET_PXA25X | 109 | #ifdef CONFIG_USB_GADGET_PXA25X |
109 | static struct pxa2xx_udc_mach_info gumstix_udc_info __initdata = { | 110 | static struct gpio_vbus_mach_info gumstix_udc_info = { |
110 | .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, | 111 | .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, |
111 | .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, | 112 | .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, |
112 | }; | 113 | }; |
113 | 114 | ||
115 | static struct platform_device gumstix_gpio_vbus = { | ||
116 | .name = "gpio-vbus", | ||
117 | .id = -1, | ||
118 | .dev = { | ||
119 | .platform_data = &gumstix_udc_info, | ||
120 | }, | ||
121 | }; | ||
122 | |||
114 | static void __init gumstix_udc_init(void) | 123 | static void __init gumstix_udc_init(void) |
115 | { | 124 | { |
116 | pxa_set_udc_info(&gumstix_udc_info); | 125 | platform_device_register(&gumstix_gpio_vbus); |
117 | } | 126 | } |
118 | #else | 127 | #else |
119 | static void gumstix_udc_init(void) | 128 | static void gumstix_udc_init(void) |
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index dd40e4a9291c..f7fb64f11a7d 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c | |||
@@ -167,7 +167,7 @@ static void __init idp_init(void) | |||
167 | 167 | ||
168 | platform_device_register(&smc91x_device); | 168 | platform_device_register(&smc91x_device); |
169 | //platform_device_register(&mst_audio_device); | 169 | //platform_device_register(&mst_audio_device); |
170 | set_pxa_fb_info(&sharp_lm8v31); | 170 | pxa_set_fb_info(NULL, &sharp_lm8v31); |
171 | pxa_set_mci_info(&idp_mci_platform_data); | 171 | pxa_set_mci_info(&idp_mci_platform_data); |
172 | } | 172 | } |
173 | 173 | ||
diff --git a/arch/arm/mach-pxa/include/mach/palmz72.h b/arch/arm/mach-pxa/include/mach/palmz72.h index 2bbcf70dd935..0d4700a79612 100644 --- a/arch/arm/mach-pxa/include/mach/palmz72.h +++ b/arch/arm/mach-pxa/include/mach/palmz72.h | |||
@@ -44,6 +44,11 @@ | |||
44 | #define GPIO_NR_PALMZ72_BT_POWER 17 | 44 | #define GPIO_NR_PALMZ72_BT_POWER 17 |
45 | #define GPIO_NR_PALMZ72_BT_RESET 83 | 45 | #define GPIO_NR_PALMZ72_BT_RESET 83 |
46 | 46 | ||
47 | /* Camera */ | ||
48 | #define GPIO_NR_PALMZ72_CAM_PWDN 56 | ||
49 | #define GPIO_NR_PALMZ72_CAM_RESET 57 | ||
50 | #define GPIO_NR_PALMZ72_CAM_POWER 91 | ||
51 | |||
47 | /** Initial values **/ | 52 | /** Initial values **/ |
48 | 53 | ||
49 | /* Battery */ | 54 | /* Battery */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index 160ec83f51a6..01a45ac48114 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h | |||
@@ -154,8 +154,8 @@ struct pxafb_mach_info { | |||
154 | void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); | 154 | void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); |
155 | void (*smart_update)(struct fb_info *); | 155 | void (*smart_update)(struct fb_info *); |
156 | }; | 156 | }; |
157 | void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info); | 157 | |
158 | void set_pxa_fb_parent(struct device *parent_dev); | 158 | void pxa_set_fb_info(struct device *, struct pxafb_mach_info *); |
159 | unsigned long pxafb_get_hsync_time(struct device *dev); | 159 | unsigned long pxafb_get_hsync_time(struct device *dev); |
160 | 160 | ||
161 | extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); | 161 | extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int); |
diff --git a/arch/arm/mach-pxa/include/mach/z2.h b/arch/arm/mach-pxa/include/mach/z2.h index 8835c16bc82f..7b0f71ef3167 100644 --- a/arch/arm/mach-pxa/include/mach/z2.h +++ b/arch/arm/mach-pxa/include/mach/z2.h | |||
@@ -25,8 +25,7 @@ | |||
25 | #define GPIO98_ZIPITZ2_LID_BUTTON 98 | 25 | #define GPIO98_ZIPITZ2_LID_BUTTON 98 |
26 | 26 | ||
27 | /* Libertas GSPI8686 WiFi */ | 27 | /* Libertas GSPI8686 WiFi */ |
28 | #define GPIO14_ZIPITZ2_WIFI_RESET 14 | 28 | #define GPIO14_ZIPITZ2_WIFI_POWER 14 |
29 | #define GPIO15_ZIPITZ2_WIFI_POWER 15 | ||
30 | #define GPIO24_ZIPITZ2_WIFI_CS 24 | 29 | #define GPIO24_ZIPITZ2_WIFI_CS 24 |
31 | #define GPIO36_ZIPITZ2_WIFI_IRQ 36 | 30 | #define GPIO36_ZIPITZ2_WIFI_IRQ 36 |
32 | 31 | ||
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index 2693e3c3776f..6251e3f5c62c 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) | |||
137 | GEDR0 = 0x3; | 137 | GEDR0 = 0x3; |
138 | 138 | ||
139 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | 139 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { |
140 | set_irq_chip(irq, &pxa_low_gpio_chip); | 140 | irq_set_chip_and_handler(irq, &pxa_low_gpio_chip, |
141 | set_irq_chip_data(irq, irq_base(0)); | 141 | handle_edge_irq); |
142 | set_irq_handler(irq, handle_edge_irq); | 142 | irq_set_chip_data(irq, irq_base(0)); |
143 | set_irq_flags(irq, IRQF_VALID); | 143 | set_irq_flags(irq, IRQF_VALID); |
144 | } | 144 | } |
145 | 145 | ||
@@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) | |||
165 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); | 165 | __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); |
166 | 166 | ||
167 | irq = PXA_IRQ(i); | 167 | irq = PXA_IRQ(i); |
168 | set_irq_chip(irq, &pxa_internal_irq_chip); | 168 | irq_set_chip_and_handler(irq, &pxa_internal_irq_chip, |
169 | set_irq_chip_data(irq, base); | 169 | handle_level_irq); |
170 | set_irq_handler(irq, handle_level_irq); | 170 | irq_set_chip_data(irq, base); |
171 | set_irq_flags(irq, IRQF_VALID); | 171 | set_irq_flags(irq, IRQF_VALID); |
172 | } | 172 | } |
173 | } | 173 | } |
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 87c1ed9ccd2f..e5e326d2cdc9 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
@@ -185,7 +185,7 @@ static struct pxafb_mach_info littleton_lcd_info = { | |||
185 | 185 | ||
186 | static void littleton_init_lcd(void) | 186 | static void littleton_init_lcd(void) |
187 | { | 187 | { |
188 | set_pxa_fb_info(&littleton_lcd_info); | 188 | pxa_set_fb_info(NULL, &littleton_lcd_info); |
189 | } | 189 | } |
190 | #else | 190 | #else |
191 | static inline void littleton_init_lcd(void) {}; | 191 | static inline void littleton_init_lcd(void) {}; |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index c9a3e775c2de..f5de541725b1 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
@@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void) | |||
149 | 149 | ||
150 | /* setup extra LogicPD PXA270 irqs */ | 150 | /* setup extra LogicPD PXA270 irqs */ |
151 | for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { | 151 | for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { |
152 | set_irq_chip(irq, &lpd270_irq_chip); | 152 | irq_set_chip_and_handler(irq, &lpd270_irq_chip, |
153 | set_irq_handler(irq, handle_level_irq); | 153 | handle_level_irq); |
154 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 154 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
155 | } | 155 | } |
156 | set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); | 156 | irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); |
157 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); | 157 | irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
158 | } | 158 | } |
159 | 159 | ||
160 | 160 | ||
@@ -480,7 +480,7 @@ static void __init lpd270_init(void) | |||
480 | pxa_set_ac97_info(NULL); | 480 | pxa_set_ac97_info(NULL); |
481 | 481 | ||
482 | if (lpd270_lcd_to_use != NULL) | 482 | if (lpd270_lcd_to_use != NULL) |
483 | set_pxa_fb_info(lpd270_lcd_to_use); | 483 | pxa_set_fb_info(NULL, lpd270_lcd_to_use); |
484 | 484 | ||
485 | pxa_set_ohci_info(&lpd270_ohci_platform_data); | 485 | pxa_set_ohci_info(&lpd270_ohci_platform_data); |
486 | } | 486 | } |
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index dca20de306bb..3ede978c83d9 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
@@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void) | |||
165 | 165 | ||
166 | /* setup extra lubbock irqs */ | 166 | /* setup extra lubbock irqs */ |
167 | for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { | 167 | for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { |
168 | set_irq_chip(irq, &lubbock_irq_chip); | 168 | irq_set_chip_and_handler(irq, &lubbock_irq_chip, |
169 | set_irq_handler(irq, handle_level_irq); | 169 | handle_level_irq); |
170 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 170 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
171 | } | 171 | } |
172 | 172 | ||
173 | set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); | 173 | irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); |
174 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); | 174 | irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
175 | } | 175 | } |
176 | 176 | ||
177 | #ifdef CONFIG_PM | 177 | #ifdef CONFIG_PM |
@@ -521,7 +521,7 @@ static void __init lubbock_init(void) | |||
521 | 521 | ||
522 | clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); | 522 | clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); |
523 | pxa_set_udc_info(&udc_info); | 523 | pxa_set_udc_info(&udc_info); |
524 | set_pxa_fb_info(&sharp_lm8v31); | 524 | pxa_set_fb_info(NULL, &sharp_lm8v31); |
525 | pxa_set_mci_info(&lubbock_mci_platform_data); | 525 | pxa_set_mci_info(&lubbock_mci_platform_data); |
526 | pxa_set_ficp_info(&lubbock_ficp_platform_data); | 526 | pxa_set_ficp_info(&lubbock_ficp_platform_data); |
527 | pxa_set_ac97_info(NULL); | 527 | pxa_set_ac97_info(NULL); |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 5535991c4a3c..a72993dde2b3 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
@@ -757,7 +757,7 @@ static void __init magician_init(void) | |||
757 | gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0); | 757 | gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0); |
758 | gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0); | 758 | gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0); |
759 | gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0); | 759 | gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0); |
760 | set_pxa_fb_info(lcd_select ? &samsung_info : &toppoly_info); | 760 | pxa_set_fb_info(NULL, lcd_select ? &samsung_info : &toppoly_info); |
761 | } else | 761 | } else |
762 | pr_err("LCD detection: CPLD mapping failed\n"); | 762 | pr_err("LCD detection: CPLD mapping failed\n"); |
763 | } | 763 | } |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index f9542220595a..95163baca29e 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
@@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void) | |||
166 | 166 | ||
167 | /* setup extra Mainstone irqs */ | 167 | /* setup extra Mainstone irqs */ |
168 | for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { | 168 | for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { |
169 | set_irq_chip(irq, &mainstone_irq_chip); | 169 | irq_set_chip_and_handler(irq, &mainstone_irq_chip, |
170 | set_irq_handler(irq, handle_level_irq); | 170 | handle_level_irq); |
171 | if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) | 171 | if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) |
172 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); | 172 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); |
173 | else | 173 | else |
@@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void) | |||
179 | MST_INTMSKENA = 0; | 179 | MST_INTMSKENA = 0; |
180 | MST_INTSETCLR = 0; | 180 | MST_INTSETCLR = 0; |
181 | 181 | ||
182 | set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); | 182 | irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); |
183 | set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); | 183 | irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); |
184 | } | 184 | } |
185 | 185 | ||
186 | #ifdef CONFIG_PM | 186 | #ifdef CONFIG_PM |
@@ -592,7 +592,7 @@ static void __init mainstone_init(void) | |||
592 | else | 592 | else |
593 | mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; | 593 | mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode; |
594 | 594 | ||
595 | set_pxa_fb_info(&mainstone_pxafb_info); | 595 | pxa_set_fb_info(NULL, &mainstone_pxafb_info); |
596 | mainstone_backlight_register(); | 596 | mainstone_backlight_register(); |
597 | 597 | ||
598 | pxa_set_mci_info(&mainstone_mci_platform_data); | 598 | pxa_set_mci_info(&mainstone_mci_platform_data); |
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 78d98a8607ec..dd13bb63259b 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c | |||
@@ -795,7 +795,7 @@ static void __init mioa701_machine_init(void) | |||
795 | pxa_set_stuart_info(NULL); | 795 | pxa_set_stuart_info(NULL); |
796 | mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); | 796 | mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); |
797 | bootstrap_init(); | 797 | bootstrap_init(); |
798 | set_pxa_fb_info(&mioa701_pxafb_info); | 798 | pxa_set_fb_info(NULL, &mioa701_pxafb_info); |
799 | pxa_set_mci_info(&mioa701_mci_info); | 799 | pxa_set_mci_info(&mioa701_mci_info); |
800 | pxa_set_keypad_info(&mioa701_keypad_info); | 800 | pxa_set_keypad_info(&mioa701_keypad_info); |
801 | pxa_set_udc_info(&mioa701_udc_info); | 801 | pxa_set_udc_info(&mioa701_udc_info); |
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c index 72adb3ae2b43..325c245c0a0d 100644 --- a/arch/arm/mach-pxa/palm27x.c +++ b/arch/arm/mach-pxa/palm27x.c | |||
@@ -1,8 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Common code for Palm LD, T5, TX, Z72 | 2 | * Common code for Palm LD, T5, TX, Z72 |
3 | * | 3 | * |
4 | * Copyright (C) 2010 | 4 | * Copyright (C) 2010-2011 Marek Vasut <marek.vasut@gmail.com> |
5 | * Marek Vasut <marek.vasut@gmail.com> | ||
6 | * | 5 | * |
7 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
@@ -158,7 +157,7 @@ void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode) | |||
158 | palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl; | 157 | palm27x_lcd_screen.pxafb_lcd_power = palm27x_lcd_ctl; |
159 | } | 158 | } |
160 | 159 | ||
161 | set_pxa_fb_info(&palm27x_lcd_screen); | 160 | pxa_set_fb_info(NULL, &palm27x_lcd_screen); |
162 | } | 161 | } |
163 | #endif | 162 | #endif |
164 | 163 | ||
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index a09a2374697b..fb06bd047272 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c | |||
@@ -507,7 +507,7 @@ static struct pxafb_mach_info palmtc_lcd_screen = { | |||
507 | 507 | ||
508 | static void __init palmtc_lcd_init(void) | 508 | static void __init palmtc_lcd_init(void) |
509 | { | 509 | { |
510 | set_pxa_fb_info(&palmtc_lcd_screen); | 510 | pxa_set_fb_info(NULL, &palmtc_lcd_screen); |
511 | } | 511 | } |
512 | #else | 512 | #else |
513 | static inline void palmtc_lcd_init(void) {} | 513 | static inline void palmtc_lcd_init(void) {} |
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 3f25014a136c..726f5b98dcd3 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c | |||
@@ -136,30 +136,14 @@ static struct platform_device palmte2_pxa_keys = { | |||
136 | /****************************************************************************** | 136 | /****************************************************************************** |
137 | * Backlight | 137 | * Backlight |
138 | ******************************************************************************/ | 138 | ******************************************************************************/ |
139 | static struct gpio palmte_bl_gpios[] = { | ||
140 | { GPIO_NR_PALMTE2_BL_POWER, GPIOF_INIT_LOW, "Backlight power" }, | ||
141 | { GPIO_NR_PALMTE2_LCD_POWER, GPIOF_INIT_LOW, "LCD power" }, | ||
142 | }; | ||
143 | |||
139 | static int palmte2_backlight_init(struct device *dev) | 144 | static int palmte2_backlight_init(struct device *dev) |
140 | { | 145 | { |
141 | int ret; | 146 | return gpio_request_array(ARRAY_AND_SIZE(palmte_bl_gpios)); |
142 | |||
143 | ret = gpio_request(GPIO_NR_PALMTE2_BL_POWER, "BL POWER"); | ||
144 | if (ret) | ||
145 | goto err; | ||
146 | ret = gpio_direction_output(GPIO_NR_PALMTE2_BL_POWER, 0); | ||
147 | if (ret) | ||
148 | goto err2; | ||
149 | ret = gpio_request(GPIO_NR_PALMTE2_LCD_POWER, "LCD POWER"); | ||
150 | if (ret) | ||
151 | goto err2; | ||
152 | ret = gpio_direction_output(GPIO_NR_PALMTE2_LCD_POWER, 0); | ||
153 | if (ret) | ||
154 | goto err3; | ||
155 | |||
156 | return 0; | ||
157 | err3: | ||
158 | gpio_free(GPIO_NR_PALMTE2_LCD_POWER); | ||
159 | err2: | ||
160 | gpio_free(GPIO_NR_PALMTE2_BL_POWER); | ||
161 | err: | ||
162 | return ret; | ||
163 | } | 147 | } |
164 | 148 | ||
165 | static int palmte2_backlight_notify(struct device *dev, int brightness) | 149 | static int palmte2_backlight_notify(struct device *dev, int brightness) |
@@ -171,8 +155,7 @@ static int palmte2_backlight_notify(struct device *dev, int brightness) | |||
171 | 155 | ||
172 | static void palmte2_backlight_exit(struct device *dev) | 156 | static void palmte2_backlight_exit(struct device *dev) |
173 | { | 157 | { |
174 | gpio_free(GPIO_NR_PALMTE2_BL_POWER); | 158 | gpio_free_array(ARRAY_AND_SIZE(palmte_bl_gpios)); |
175 | gpio_free(GPIO_NR_PALMTE2_LCD_POWER); | ||
176 | } | 159 | } |
177 | 160 | ||
178 | static struct platform_pwm_backlight_data palmte2_backlight_data = { | 161 | static struct platform_pwm_backlight_data palmte2_backlight_data = { |
@@ -363,7 +346,7 @@ static void __init palmte2_init(void) | |||
363 | pxa_set_btuart_info(NULL); | 346 | pxa_set_btuart_info(NULL); |
364 | pxa_set_stuart_info(NULL); | 347 | pxa_set_stuart_info(NULL); |
365 | 348 | ||
366 | set_pxa_fb_info(&palmte2_lcd_screen); | 349 | pxa_set_fb_info(NULL, &palmte2_lcd_screen); |
367 | pxa_set_mci_info(&palmte2_mci_platform_data); | 350 | pxa_set_mci_info(&palmte2_mci_platform_data); |
368 | palmte2_udc_init(); | 351 | palmte2_udc_init(); |
369 | pxa_set_ac97_info(&palmte2_ac97_pdata); | 352 | pxa_set_ac97_info(&palmte2_ac97_pdata); |
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 3010193b081e..3b8a4f37dbbe 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <linux/wm97xx.h> | 30 | #include <linux/wm97xx.h> |
31 | #include <linux/power_supply.h> | 31 | #include <linux/power_supply.h> |
32 | #include <linux/usb/gpio_vbus.h> | 32 | #include <linux/usb/gpio_vbus.h> |
33 | #include <linux/i2c-gpio.h> | ||
33 | 34 | ||
34 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
35 | #include <asm/mach/arch.h> | 36 | #include <asm/mach/arch.h> |
@@ -47,6 +48,9 @@ | |||
47 | #include <mach/palm27x.h> | 48 | #include <mach/palm27x.h> |
48 | 49 | ||
49 | #include <mach/pm.h> | 50 | #include <mach/pm.h> |
51 | #include <mach/camera.h> | ||
52 | |||
53 | #include <media/soc_camera.h> | ||
50 | 54 | ||
51 | #include "generic.h" | 55 | #include "generic.h" |
52 | #include "devices.h" | 56 | #include "devices.h" |
@@ -103,6 +107,28 @@ static unsigned long palmz72_pin_config[] __initdata = { | |||
103 | GPIO22_GPIO, /* LCD border color */ | 107 | GPIO22_GPIO, /* LCD border color */ |
104 | GPIO96_GPIO, /* lcd power */ | 108 | GPIO96_GPIO, /* lcd power */ |
105 | 109 | ||
110 | /* PXA Camera */ | ||
111 | GPIO81_CIF_DD_0, | ||
112 | GPIO48_CIF_DD_5, | ||
113 | GPIO50_CIF_DD_3, | ||
114 | GPIO51_CIF_DD_2, | ||
115 | GPIO52_CIF_DD_4, | ||
116 | GPIO53_CIF_MCLK, | ||
117 | GPIO54_CIF_PCLK, | ||
118 | GPIO55_CIF_DD_1, | ||
119 | GPIO84_CIF_FV, | ||
120 | GPIO85_CIF_LV, | ||
121 | GPIO93_CIF_DD_6, | ||
122 | GPIO108_CIF_DD_7, | ||
123 | |||
124 | GPIO56_GPIO, /* OV9640 Powerdown */ | ||
125 | GPIO57_GPIO, /* OV9640 Reset */ | ||
126 | GPIO91_GPIO, /* OV9640 Power */ | ||
127 | |||
128 | /* I2C */ | ||
129 | GPIO117_GPIO, /* I2C_SCL */ | ||
130 | GPIO118_GPIO, /* I2C_SDA */ | ||
131 | |||
106 | /* Misc. */ | 132 | /* Misc. */ |
107 | GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */ | 133 | GPIO0_GPIO | WAKEUP_ON_LEVEL_HIGH, /* power detect */ |
108 | GPIO88_GPIO, /* green led */ | 134 | GPIO88_GPIO, /* green led */ |
@@ -254,6 +280,106 @@ device_initcall(palmz72_pm_init); | |||
254 | #endif | 280 | #endif |
255 | 281 | ||
256 | /****************************************************************************** | 282 | /****************************************************************************** |
283 | * SoC Camera | ||
284 | ******************************************************************************/ | ||
285 | #if defined(CONFIG_SOC_CAMERA_OV9640) || \ | ||
286 | defined(CONFIG_SOC_CAMERA_OV9640_MODULE) | ||
287 | static struct pxacamera_platform_data palmz72_pxacamera_platform_data = { | ||
288 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | | ||
289 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, | ||
290 | .mclk_10khz = 2600, | ||
291 | }; | ||
292 | |||
293 | /* Board I2C devices. */ | ||
294 | static struct i2c_board_info palmz72_i2c_device[] = { | ||
295 | { | ||
296 | I2C_BOARD_INFO("ov9640", 0x30), | ||
297 | } | ||
298 | }; | ||
299 | |||
300 | static int palmz72_camera_power(struct device *dev, int power) | ||
301 | { | ||
302 | gpio_set_value(GPIO_NR_PALMZ72_CAM_PWDN, !power); | ||
303 | mdelay(50); | ||
304 | return 0; | ||
305 | } | ||
306 | |||
307 | static int palmz72_camera_reset(struct device *dev) | ||
308 | { | ||
309 | gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 1); | ||
310 | mdelay(50); | ||
311 | gpio_set_value(GPIO_NR_PALMZ72_CAM_RESET, 0); | ||
312 | mdelay(50); | ||
313 | return 0; | ||
314 | } | ||
315 | |||
316 | static struct soc_camera_link palmz72_iclink = { | ||
317 | .bus_id = 0, /* Match id in pxa27x_device_camera in device.c */ | ||
318 | .board_info = &palmz72_i2c_device[0], | ||
319 | .i2c_adapter_id = 0, | ||
320 | .module_name = "ov96xx", | ||
321 | .power = &palmz72_camera_power, | ||
322 | .reset = &palmz72_camera_reset, | ||
323 | .flags = SOCAM_DATAWIDTH_8, | ||
324 | }; | ||
325 | |||
326 | static struct i2c_gpio_platform_data palmz72_i2c_bus_data = { | ||
327 | .sda_pin = 118, | ||
328 | .scl_pin = 117, | ||
329 | .udelay = 10, | ||
330 | .timeout = 100, | ||
331 | }; | ||
332 | |||
333 | static struct platform_device palmz72_i2c_bus_device = { | ||
334 | .name = "i2c-gpio", | ||
335 | .id = 0, /* we use this as a replacement for i2c-pxa */ | ||
336 | .dev = { | ||
337 | .platform_data = &palmz72_i2c_bus_data, | ||
338 | } | ||
339 | }; | ||
340 | |||
341 | static struct platform_device palmz72_camera = { | ||
342 | .name = "soc-camera-pdrv", | ||
343 | .id = -1, | ||
344 | .dev = { | ||
345 | .platform_data = &palmz72_iclink, | ||
346 | }, | ||
347 | }; | ||
348 | |||
349 | /* Here we request the camera GPIOs and configure them. We power up the camera | ||
350 | * module, deassert the reset pin, but put it into powerdown (low to no power | ||
351 | * consumption) mode. This allows us to later bring the module up fast. */ | ||
352 | static struct gpio palmz72_camera_gpios[] = { | ||
353 | { GPIO_NR_PALMZ72_CAM_POWER, GPIOF_INIT_HIGH,"Camera DVDD" }, | ||
354 | { GPIO_NR_PALMZ72_CAM_RESET, GPIOF_INIT_LOW, "Camera RESET" }, | ||
355 | { GPIO_NR_PALMZ72_CAM_PWDN, GPIOF_INIT_LOW, "Camera PWDN" }, | ||
356 | }; | ||
357 | |||
358 | static inline void __init palmz72_cam_gpio_init(void) | ||
359 | { | ||
360 | int ret; | ||
361 | |||
362 | ret = gpio_request_array(ARRAY_AND_SIZE(palmz72_camera_gpios)); | ||
363 | if (!ret) | ||
364 | gpio_free_array(ARRAY_AND_SIZE(palmz72_camera_gpios)); | ||
365 | else | ||
366 | printk(KERN_ERR "Camera GPIO init failed!\n"); | ||
367 | |||
368 | return; | ||
369 | } | ||
370 | |||
371 | static void __init palmz72_camera_init(void) | ||
372 | { | ||
373 | palmz72_cam_gpio_init(); | ||
374 | pxa_set_camera_info(&palmz72_pxacamera_platform_data); | ||
375 | platform_device_register(&palmz72_i2c_bus_device); | ||
376 | platform_device_register(&palmz72_camera); | ||
377 | } | ||
378 | #else | ||
379 | static inline void palmz72_camera_init(void) {} | ||
380 | #endif | ||
381 | |||
382 | /****************************************************************************** | ||
257 | * Machine init | 383 | * Machine init |
258 | ******************************************************************************/ | 384 | ******************************************************************************/ |
259 | static void __init palmz72_init(void) | 385 | static void __init palmz72_init(void) |
@@ -276,6 +402,7 @@ static void __init palmz72_init(void) | |||
276 | palm27x_pmic_init(); | 402 | palm27x_pmic_init(); |
277 | palmz72_kpc_init(); | 403 | palmz72_kpc_init(); |
278 | palmz72_leds_init(); | 404 | palmz72_leds_init(); |
405 | palmz72_camera_init(); | ||
279 | } | 406 | } |
280 | 407 | ||
281 | MACHINE_START(PALMZ72, "Palm Zire72") | 408 | MACHINE_START(PALMZ72, "Palm Zire72") |
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9dbf3ccd4150..6d5b7e062124 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c | |||
@@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void) | |||
281 | 281 | ||
282 | /* setup extra PCM990 irqs */ | 282 | /* setup extra PCM990 irqs */ |
283 | for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { | 283 | for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { |
284 | set_irq_chip(irq, &pcm990_irq_chip); | 284 | irq_set_chip_and_handler(irq, &pcm990_irq_chip, |
285 | set_irq_handler(irq, handle_level_irq); | 285 | handle_level_irq); |
286 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 286 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
287 | } | 287 | } |
288 | 288 | ||
289 | PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ | 289 | PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ |
290 | PCM990_INTSETCLR = 0xFF; | 290 | PCM990_INTSETCLR = 0xFF; |
291 | 291 | ||
292 | set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); | 292 | irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); |
293 | set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); | 293 | irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); |
294 | } | 294 | } |
295 | 295 | ||
296 | static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, | 296 | static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, |
@@ -515,7 +515,7 @@ void __init pcm990_baseboard_init(void) | |||
515 | pcm990_init_irq(); | 515 | pcm990_init_irq(); |
516 | 516 | ||
517 | #ifndef CONFIG_PCM990_DISPLAY_NONE | 517 | #ifndef CONFIG_PCM990_DISPLAY_NONE |
518 | set_pxa_fb_info(&pcm990_fbinfo); | 518 | pxa_set_fb_info(NULL, &pcm990_fbinfo); |
519 | #endif | 519 | #endif |
520 | platform_device_register(&pcm990_backlight_device); | 520 | platform_device_register(&pcm990_backlight_device); |
521 | 521 | ||
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 35353af345d5..16d14fd79b4b 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
@@ -445,8 +445,7 @@ static void __init poodle_init(void) | |||
445 | if (ret) | 445 | if (ret) |
446 | pr_warning("poodle: Unable to register LoCoMo device\n"); | 446 | pr_warning("poodle: Unable to register LoCoMo device\n"); |
447 | 447 | ||
448 | set_pxa_fb_parent(&poodle_locomo_device.dev); | 448 | pxa_set_fb_info(&poodle_locomo_device.dev, &poodle_fb_info); |
449 | set_pxa_fb_info(&poodle_fb_info); | ||
450 | pxa_set_udc_info(&udc_info); | 449 | pxa_set_udc_info(&udc_info); |
451 | pxa_set_mci_info(&poodle_mci_platform_data); | 450 | pxa_set_mci_info(&poodle_mci_platform_data); |
452 | pxa_set_ficp_info(&poodle_ficp_platform_data); | 451 | pxa_set_ficp_info(&poodle_ficp_platform_data); |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index f374247b8466..8dd107391157 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) | |||
362 | int irq; | 362 | int irq; |
363 | 363 | ||
364 | for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { | 364 | for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { |
365 | set_irq_chip(irq, &pxa_ext_wakeup_chip); | 365 | irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, |
366 | set_irq_handler(irq, handle_edge_irq); | 366 | handle_edge_irq); |
367 | set_irq_flags(irq, IRQF_VALID); | 367 | set_irq_flags(irq, IRQF_VALID); |
368 | } | 368 | } |
369 | 369 | ||
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c index 47094188e029..cd1861351f75 100644 --- a/arch/arm/mach-pxa/raumfeld.c +++ b/arch/arm/mach-pxa/raumfeld.c | |||
@@ -597,7 +597,7 @@ static void __init raumfeld_lcd_init(void) | |||
597 | { | 597 | { |
598 | int ret; | 598 | int ret; |
599 | 599 | ||
600 | set_pxa_fb_info(&raumfeld_sharp_lcd_info); | 600 | pxa_set_fb_info(NULL, &raumfeld_sharp_lcd_info); |
601 | 601 | ||
602 | /* Earlier devices had the backlight regulator controlled | 602 | /* Earlier devices had the backlight regulator controlled |
603 | * via PWM, later versions use another controller for that */ | 603 | * via PWM, later versions use another controller for that */ |
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index eb83c89428ef..fee97a935122 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c | |||
@@ -473,7 +473,7 @@ static struct pxafb_mach_info saar_lcd_info = { | |||
473 | 473 | ||
474 | static void __init saar_init_lcd(void) | 474 | static void __init saar_init_lcd(void) |
475 | { | 475 | { |
476 | set_pxa_fb_info(&saar_lcd_info); | 476 | pxa_set_fb_info(NULL, &saar_lcd_info); |
477 | } | 477 | } |
478 | #else | 478 | #else |
479 | static inline void saar_init_lcd(void) {} | 479 | static inline void saar_init_lcd(void) {} |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 38e2c0912b9a..01c576963e94 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
@@ -724,7 +724,7 @@ static struct pxafb_mach_info spitz_pxafb_info = { | |||
724 | 724 | ||
725 | static void __init spitz_lcd_init(void) | 725 | static void __init spitz_lcd_init(void) |
726 | { | 726 | { |
727 | set_pxa_fb_info(&spitz_pxafb_info); | 727 | pxa_set_fb_info(NULL, &spitz_pxafb_info); |
728 | } | 728 | } |
729 | #else | 729 | #else |
730 | static inline void spitz_lcd_init(void) {} | 730 | static inline void spitz_lcd_init(void) {} |
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 9cecf8366db8..53d4a472b699 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c | |||
@@ -466,7 +466,7 @@ static void __init tavorevb_init_lcd(void) | |||
466 | { | 466 | { |
467 | platform_device_register(&tavorevb_backlight_devices[0]); | 467 | platform_device_register(&tavorevb_backlight_devices[0]); |
468 | platform_device_register(&tavorevb_backlight_devices[1]); | 468 | platform_device_register(&tavorevb_backlight_devices[1]); |
469 | set_pxa_fb_info(&tavorevb_lcd_info); | 469 | pxa_set_fb_info(NULL, &tavorevb_lcd_info); |
470 | } | 470 | } |
471 | #else | 471 | #else |
472 | static inline void tavorevb_init_lcd(void) {} | 472 | static inline void tavorevb_init_lcd(void) {} |
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index e7f64d9b4f2d..428da3ff33a5 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c | |||
@@ -100,7 +100,6 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |||
100 | static struct clock_event_device ckevt_pxa_osmr0 = { | 100 | static struct clock_event_device ckevt_pxa_osmr0 = { |
101 | .name = "osmr0", | 101 | .name = "osmr0", |
102 | .features = CLOCK_EVT_FEAT_ONESHOT, | 102 | .features = CLOCK_EVT_FEAT_ONESHOT, |
103 | .shift = 32, | ||
104 | .rating = 200, | 103 | .rating = 200, |
105 | .set_next_event = pxa_osmr0_set_next_event, | 104 | .set_next_event = pxa_osmr0_set_next_event, |
106 | .set_mode = pxa_osmr0_set_mode, | 105 | .set_mode = pxa_osmr0_set_mode, |
@@ -135,8 +134,8 @@ static void __init pxa_timer_init(void) | |||
135 | 134 | ||
136 | init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); | 135 | init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); |
137 | 136 | ||
138 | ckevt_pxa_osmr0.mult = | 137 | clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4); |
139 | div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); | 138 | clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); |
140 | ckevt_pxa_osmr0.max_delta_ns = | 139 | ckevt_pxa_osmr0.max_delta_ns = |
141 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); | 140 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); |
142 | ckevt_pxa_osmr0.min_delta_ns = | 141 | ckevt_pxa_osmr0.min_delta_ns = |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 5ad3807af334..5fa145778e7d 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <linux/spi/pxa2xx_spi.h> | 35 | #include <linux/spi/pxa2xx_spi.h> |
36 | #include <linux/input/matrix_keypad.h> | 36 | #include <linux/input/matrix_keypad.h> |
37 | #include <linux/i2c/pxa-i2c.h> | 37 | #include <linux/i2c/pxa-i2c.h> |
38 | #include <linux/usb/gpio_vbus.h> | ||
38 | 39 | ||
39 | #include <asm/setup.h> | 40 | #include <asm/setup.h> |
40 | #include <asm/mach-types.h> | 41 | #include <asm/mach-types.h> |
@@ -240,12 +241,20 @@ static struct scoop_pcmcia_config tosa_pcmcia_config = { | |||
240 | /* | 241 | /* |
241 | * USB Device Controller | 242 | * USB Device Controller |
242 | */ | 243 | */ |
243 | static struct pxa2xx_udc_mach_info udc_info __initdata = { | 244 | static struct gpio_vbus_mach_info tosa_udc_info = { |
244 | .gpio_pullup = TOSA_GPIO_USB_PULLUP, | 245 | .gpio_pullup = TOSA_GPIO_USB_PULLUP, |
245 | .gpio_vbus = TOSA_GPIO_USB_IN, | 246 | .gpio_vbus = TOSA_GPIO_USB_IN, |
246 | .gpio_vbus_inverted = 1, | 247 | .gpio_vbus_inverted = 1, |
247 | }; | 248 | }; |
248 | 249 | ||
250 | static struct platform_device tosa_gpio_vbus = { | ||
251 | .name = "gpio-vbus", | ||
252 | .id = -1, | ||
253 | .dev = { | ||
254 | .platform_data = &tosa_udc_info, | ||
255 | }, | ||
256 | }; | ||
257 | |||
249 | /* | 258 | /* |
250 | * MMC/SD Device | 259 | * MMC/SD Device |
251 | */ | 260 | */ |
@@ -891,6 +900,7 @@ static struct platform_device *devices[] __initdata = { | |||
891 | &tosa_bt_device, | 900 | &tosa_bt_device, |
892 | &sharpsl_rom_device, | 901 | &sharpsl_rom_device, |
893 | &wm9712_device, | 902 | &wm9712_device, |
903 | &tosa_gpio_vbus, | ||
894 | }; | 904 | }; |
895 | 905 | ||
896 | static void tosa_poweroff(void) | 906 | static void tosa_poweroff(void) |
@@ -937,7 +947,6 @@ static void __init tosa_init(void) | |||
937 | dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16); | 947 | dummy = gpiochip_reserve(TOSA_TC6393XB_GPIO_BASE, 16); |
938 | 948 | ||
939 | pxa_set_mci_info(&tosa_mci_platform_data); | 949 | pxa_set_mci_info(&tosa_mci_platform_data); |
940 | pxa_set_udc_info(&udc_info); | ||
941 | pxa_set_ficp_info(&tosa_ficp_platform_data); | 950 | pxa_set_ficp_info(&tosa_ficp_platform_data); |
942 | pxa_set_i2c_info(NULL); | 951 | pxa_set_i2c_info(NULL); |
943 | pxa_set_ac97_info(NULL); | 952 | pxa_set_ac97_info(NULL); |
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 857bb2e63486..b9cfbebdfe9c 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
@@ -516,9 +516,9 @@ static void __init trizeps4_init(void) | |||
516 | pxa_set_stuart_info(NULL); | 516 | pxa_set_stuart_info(NULL); |
517 | 517 | ||
518 | if (0) /* dont know how to determine LCD */ | 518 | if (0) /* dont know how to determine LCD */ |
519 | set_pxa_fb_info(&sharp_lcd); | 519 | pxa_set_fb_info(NULL, &sharp_lcd); |
520 | else | 520 | else |
521 | set_pxa_fb_info(&toshiba_lcd); | 521 | pxa_set_fb_info(NULL, &toshiba_lcd); |
522 | 522 | ||
523 | pxa_set_mci_info(&trizeps4_mci_platform_data); | 523 | pxa_set_mci_info(&trizeps4_mci_platform_data); |
524 | #ifndef STATUS_LEDS_ON_STUART_PINS | 524 | #ifndef STATUS_LEDS_ON_STUART_PINS |
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 12279214c875..b523f119e0f0 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
@@ -310,14 +310,14 @@ static void __init viper_init_irq(void) | |||
310 | /* setup ISA IRQs */ | 310 | /* setup ISA IRQs */ |
311 | for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { | 311 | for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { |
312 | isa_irq = viper_bit_to_irq(level); | 312 | isa_irq = viper_bit_to_irq(level); |
313 | set_irq_chip(isa_irq, &viper_irq_chip); | 313 | irq_set_chip_and_handler(isa_irq, &viper_irq_chip, |
314 | set_irq_handler(isa_irq, handle_edge_irq); | 314 | handle_edge_irq); |
315 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); | 315 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); |
316 | } | 316 | } |
317 | 317 | ||
318 | set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), | 318 | irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), |
319 | viper_irq_handler); | 319 | viper_irq_handler); |
320 | set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); | 320 | irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); |
321 | } | 321 | } |
322 | 322 | ||
323 | /* Flat Panel */ | 323 | /* Flat Panel */ |
@@ -932,7 +932,7 @@ static void __init viper_init(void) | |||
932 | /* Wake-up serial console */ | 932 | /* Wake-up serial console */ |
933 | viper_init_serial_gpio(); | 933 | viper_init_serial_gpio(); |
934 | 934 | ||
935 | set_pxa_fb_info(&fb_info); | 935 | pxa_set_fb_info(NULL, &fb_info); |
936 | 936 | ||
937 | /* v1 hardware cannot use the datacs line */ | 937 | /* v1 hardware cannot use the datacs line */ |
938 | version = viper_hw_version(); | 938 | version = viper_hw_version(); |
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c index e709fd459268..f71d377c8640 100644 --- a/arch/arm/mach-pxa/vpac270.c +++ b/arch/arm/mach-pxa/vpac270.c | |||
@@ -572,7 +572,7 @@ static void __init vpac270_lcd_init(void) | |||
572 | } | 572 | } |
573 | 573 | ||
574 | vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power; | 574 | vpac270_lcd_screen.pxafb_lcd_power = vpac270_lcd_power; |
575 | set_pxa_fb_info(&vpac270_lcd_screen); | 575 | pxa_set_fb_info(NULL, &vpac270_lcd_screen); |
576 | return; | 576 | return; |
577 | 577 | ||
578 | err2: | 578 | err2: |
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c index aaf883754ef4..fbe9e02e2f9f 100644 --- a/arch/arm/mach-pxa/z2.c +++ b/arch/arm/mach-pxa/z2.c | |||
@@ -91,13 +91,13 @@ static unsigned long z2_pin_config[] = { | |||
91 | GPIO47_STUART_TXD, | 91 | GPIO47_STUART_TXD, |
92 | 92 | ||
93 | /* Keypad */ | 93 | /* Keypad */ |
94 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | 94 | GPIO100_KP_MKIN_0, |
95 | GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH, | 95 | GPIO101_KP_MKIN_1, |
96 | GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH, | 96 | GPIO102_KP_MKIN_2, |
97 | GPIO34_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH, | 97 | GPIO34_KP_MKIN_3, |
98 | GPIO38_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH, | 98 | GPIO38_KP_MKIN_4, |
99 | GPIO16_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, | 99 | GPIO16_KP_MKIN_5, |
100 | GPIO17_KP_MKIN_6 | WAKEUP_ON_LEVEL_HIGH, | 100 | GPIO17_KP_MKIN_6, |
101 | GPIO103_KP_MKOUT_0, | 101 | GPIO103_KP_MKOUT_0, |
102 | GPIO104_KP_MKOUT_1, | 102 | GPIO104_KP_MKOUT_1, |
103 | GPIO105_KP_MKOUT_2, | 103 | GPIO105_KP_MKOUT_2, |
@@ -138,8 +138,7 @@ static unsigned long z2_pin_config[] = { | |||
138 | GPIO1_GPIO, /* Power button */ | 138 | GPIO1_GPIO, /* Power button */ |
139 | GPIO37_GPIO, /* Headphone detect */ | 139 | GPIO37_GPIO, /* Headphone detect */ |
140 | GPIO98_GPIO, /* Lid switch */ | 140 | GPIO98_GPIO, /* Lid switch */ |
141 | GPIO14_GPIO, /* WiFi Reset */ | 141 | GPIO14_GPIO, /* WiFi Power */ |
142 | GPIO15_GPIO, /* WiFi Power */ | ||
143 | GPIO24_GPIO, /* WiFi CS */ | 142 | GPIO24_GPIO, /* WiFi CS */ |
144 | GPIO36_GPIO, /* WiFi IRQ */ | 143 | GPIO36_GPIO, /* WiFi IRQ */ |
145 | GPIO88_GPIO, /* LCD CS */ | 144 | GPIO88_GPIO, /* LCD CS */ |
@@ -204,7 +203,7 @@ static struct platform_pwm_backlight_data z2_backlight_data[] = { | |||
204 | /* Keypad Backlight */ | 203 | /* Keypad Backlight */ |
205 | .pwm_id = 1, | 204 | .pwm_id = 1, |
206 | .max_brightness = 1023, | 205 | .max_brightness = 1023, |
207 | .dft_brightness = 512, | 206 | .dft_brightness = 0, |
208 | .pwm_period_ns = 1260320, | 207 | .pwm_period_ns = 1260320, |
209 | }, | 208 | }, |
210 | [1] = { | 209 | [1] = { |
@@ -271,7 +270,7 @@ static struct pxafb_mach_info z2_lcd_screen = { | |||
271 | 270 | ||
272 | static void __init z2_lcd_init(void) | 271 | static void __init z2_lcd_init(void) |
273 | { | 272 | { |
274 | set_pxa_fb_info(&z2_lcd_screen); | 273 | pxa_set_fb_info(NULL, &z2_lcd_screen); |
275 | } | 274 | } |
276 | #else | 275 | #else |
277 | static inline void z2_lcd_init(void) {} | 276 | static inline void z2_lcd_init(void) {} |
@@ -309,12 +308,12 @@ struct gpio_led z2_gpio_leds[] = { | |||
309 | .active_low = 1, | 308 | .active_low = 1, |
310 | }, { | 309 | }, { |
311 | .name = "z2:green:charged", | 310 | .name = "z2:green:charged", |
312 | .default_trigger = "none", | 311 | .default_trigger = "mmc0", |
313 | .gpio = GPIO85_ZIPITZ2_LED_CHARGED, | 312 | .gpio = GPIO85_ZIPITZ2_LED_CHARGED, |
314 | .active_low = 1, | 313 | .active_low = 1, |
315 | }, { | 314 | }, { |
316 | .name = "z2:amber:charging", | 315 | .name = "z2:amber:charging", |
317 | .default_trigger = "none", | 316 | .default_trigger = "Z2-charging-or-full", |
318 | .gpio = GPIO83_ZIPITZ2_LED_CHARGING, | 317 | .gpio = GPIO83_ZIPITZ2_LED_CHARGING, |
319 | .active_low = 1, | 318 | .active_low = 1, |
320 | }, | 319 | }, |
@@ -427,8 +426,22 @@ static inline void z2_mkp_init(void) {} | |||
427 | ******************************************************************************/ | 426 | ******************************************************************************/ |
428 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | 427 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) |
429 | static struct gpio_keys_button z2_pxa_buttons[] = { | 428 | static struct gpio_keys_button z2_pxa_buttons[] = { |
430 | {KEY_POWER, GPIO1_ZIPITZ2_POWER_BUTTON, 0, "Power Button" }, | 429 | { |
431 | {KEY_CLOSE, GPIO98_ZIPITZ2_LID_BUTTON, 0, "Lid Button" }, | 430 | .code = KEY_POWER, |
431 | .gpio = GPIO1_ZIPITZ2_POWER_BUTTON, | ||
432 | .active_low = 0, | ||
433 | .desc = "Power Button", | ||
434 | .wakeup = 1, | ||
435 | .type = EV_KEY, | ||
436 | }, | ||
437 | { | ||
438 | .code = SW_LID, | ||
439 | .gpio = GPIO98_ZIPITZ2_LID_BUTTON, | ||
440 | .active_low = 1, | ||
441 | .desc = "Lid Switch", | ||
442 | .wakeup = 0, | ||
443 | .type = EV_SW, | ||
444 | }, | ||
432 | }; | 445 | }; |
433 | 446 | ||
434 | static struct gpio_keys_platform_data z2_pxa_keys_data = { | 447 | static struct gpio_keys_platform_data z2_pxa_keys_data = { |
@@ -461,9 +474,9 @@ static struct z2_battery_info batt_chip_info = { | |||
461 | .batt_I2C_addr = 0x55, | 474 | .batt_I2C_addr = 0x55, |
462 | .batt_I2C_reg = 2, | 475 | .batt_I2C_reg = 2, |
463 | .charge_gpio = GPIO0_ZIPITZ2_AC_DETECT, | 476 | .charge_gpio = GPIO0_ZIPITZ2_AC_DETECT, |
464 | .min_voltage = 2400000, | 477 | .min_voltage = 3475000, |
465 | .max_voltage = 3700000, | 478 | .max_voltage = 4190000, |
466 | .batt_div = 69, | 479 | .batt_div = 59, |
467 | .batt_mult = 1000000, | 480 | .batt_mult = 1000000, |
468 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, | 481 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LION, |
469 | .batt_name = "Z2", | 482 | .batt_name = "Z2", |
@@ -497,26 +510,16 @@ static int z2_lbs_spi_setup(struct spi_device *spi) | |||
497 | { | 510 | { |
498 | int ret = 0; | 511 | int ret = 0; |
499 | 512 | ||
500 | ret = gpio_request(GPIO15_ZIPITZ2_WIFI_POWER, "WiFi Power"); | 513 | ret = gpio_request(GPIO14_ZIPITZ2_WIFI_POWER, "WiFi Power"); |
501 | if (ret) | 514 | if (ret) |
502 | goto err; | 515 | goto err; |
503 | 516 | ||
504 | ret = gpio_direction_output(GPIO15_ZIPITZ2_WIFI_POWER, 1); | 517 | ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_POWER, 1); |
505 | if (ret) | 518 | if (ret) |
506 | goto err2; | 519 | goto err2; |
507 | 520 | ||
508 | ret = gpio_request(GPIO14_ZIPITZ2_WIFI_RESET, "WiFi Reset"); | 521 | /* Wait until card is powered on */ |
509 | if (ret) | ||
510 | goto err2; | ||
511 | |||
512 | ret = gpio_direction_output(GPIO14_ZIPITZ2_WIFI_RESET, 0); | ||
513 | if (ret) | ||
514 | goto err3; | ||
515 | |||
516 | /* Reset the card */ | ||
517 | mdelay(180); | 522 | mdelay(180); |
518 | gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 1); | ||
519 | mdelay(20); | ||
520 | 523 | ||
521 | spi->bits_per_word = 16; | 524 | spi->bits_per_word = 16; |
522 | spi->mode = SPI_MODE_2, | 525 | spi->mode = SPI_MODE_2, |
@@ -525,22 +528,18 @@ static int z2_lbs_spi_setup(struct spi_device *spi) | |||
525 | 528 | ||
526 | return 0; | 529 | return 0; |
527 | 530 | ||
528 | err3: | ||
529 | gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); | ||
530 | err2: | 531 | err2: |
531 | gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); | 532 | gpio_free(GPIO14_ZIPITZ2_WIFI_POWER); |
532 | err: | 533 | err: |
533 | return ret; | 534 | return ret; |
534 | }; | 535 | }; |
535 | 536 | ||
536 | static int z2_lbs_spi_teardown(struct spi_device *spi) | 537 | static int z2_lbs_spi_teardown(struct spi_device *spi) |
537 | { | 538 | { |
538 | gpio_set_value(GPIO14_ZIPITZ2_WIFI_RESET, 0); | 539 | gpio_set_value(GPIO14_ZIPITZ2_WIFI_POWER, 0); |
539 | gpio_set_value(GPIO15_ZIPITZ2_WIFI_POWER, 0); | 540 | gpio_free(GPIO14_ZIPITZ2_WIFI_POWER); |
540 | gpio_free(GPIO14_ZIPITZ2_WIFI_RESET); | ||
541 | gpio_free(GPIO15_ZIPITZ2_WIFI_POWER); | ||
542 | return 0; | ||
543 | 541 | ||
542 | return 0; | ||
544 | }; | 543 | }; |
545 | 544 | ||
546 | static struct pxa2xx_spi_chip z2_lbs_chip_info = { | 545 | static struct pxa2xx_spi_chip z2_lbs_chip_info = { |
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 730f51e57c17..00363c7ac182 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c | |||
@@ -136,22 +136,23 @@ static void __init zeus_init_irq(void) | |||
136 | 136 | ||
137 | /* Peripheral IRQs. It would be nice to move those inside driver | 137 | /* Peripheral IRQs. It would be nice to move those inside driver |
138 | configuration, but it is not supported at the moment. */ | 138 | configuration, but it is not supported at the moment. */ |
139 | set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); | 139 | irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); |
140 | set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); | 140 | irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); |
141 | set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); | 141 | irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); |
142 | set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); | 142 | irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), |
143 | set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); | 143 | IRQ_TYPE_EDGE_FALLING); |
144 | irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
144 | 145 | ||
145 | /* Setup ISA IRQs */ | 146 | /* Setup ISA IRQs */ |
146 | for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { | 147 | for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { |
147 | isa_irq = zeus_bit_to_irq(level); | 148 | isa_irq = zeus_bit_to_irq(level); |
148 | set_irq_chip(isa_irq, &zeus_irq_chip); | 149 | irq_set_chip_and_handler(isa_irq, &zeus_irq_chip, |
149 | set_irq_handler(isa_irq, handle_edge_irq); | 150 | handle_edge_irq); |
150 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); | 151 | set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); |
151 | } | 152 | } |
152 | 153 | ||
153 | set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); | 154 | irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); |
154 | set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); | 155 | irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); |
155 | } | 156 | } |
156 | 157 | ||
157 | 158 | ||
@@ -846,7 +847,7 @@ static void __init zeus_init(void) | |||
846 | if (zeus_setup_fb_gpios()) | 847 | if (zeus_setup_fb_gpios()) |
847 | pr_err("Failed to setup fb gpios\n"); | 848 | pr_err("Failed to setup fb gpios\n"); |
848 | else | 849 | else |
849 | set_pxa_fb_info(&zeus_fb_info); | 850 | pxa_set_fb_info(NULL, &zeus_fb_info); |
850 | 851 | ||
851 | pxa_set_mci_info(&zeus_mci_platform_data); | 852 | pxa_set_mci_info(&zeus_mci_platform_data); |
852 | pxa_set_udc_info(&zeus_udc_info); | 853 | pxa_set_udc_info(&zeus_udc_info); |
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index a4c784aab764..5821185f77ab 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c | |||
@@ -208,7 +208,7 @@ static void __init zylonite_init_lcd(void) | |||
208 | platform_device_register(&zylonite_backlight_device); | 208 | platform_device_register(&zylonite_backlight_device); |
209 | 209 | ||
210 | if (lcd_id & 0x20) { | 210 | if (lcd_id & 0x20) { |
211 | set_pxa_fb_info(&zylonite_sharp_lcd_info); | 211 | pxa_set_fb_info(NULL, &zylonite_sharp_lcd_info); |
212 | return; | 212 | return; |
213 | } | 213 | } |
214 | 214 | ||
@@ -220,7 +220,7 @@ static void __init zylonite_init_lcd(void) | |||
220 | else | 220 | else |
221 | zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; | 221 | zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode; |
222 | 222 | ||
223 | set_pxa_fb_info(&zylonite_toshiba_lcd_info); | 223 | pxa_set_fb_info(NULL, &zylonite_toshiba_lcd_info); |
224 | } | 224 | } |
225 | #else | 225 | #else |
226 | static inline void zylonite_init_lcd(void) {} | 226 | static inline void zylonite_init_lcd(void) {} |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 2ecc1d94284e..10e75faba4c9 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
@@ -348,7 +348,7 @@ static void __init gic_init_irq(void) | |||
348 | 348 | ||
349 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB | 349 | #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB |
350 | /* board GIC, secondary */ | 350 | /* board GIC, secondary */ |
351 | gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE), | 351 | gic_init(1, 96, __io_address(REALVIEW_EB_GIC_DIST_BASE), |
352 | __io_address(REALVIEW_EB_GIC_CPU_BASE)); | 352 | __io_address(REALVIEW_EB_GIC_CPU_BASE)); |
353 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); | 353 | gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1); |
354 | #endif | 354 | #endif |
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index d29cd9b737fc..2e1b5309fbab 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c | |||
@@ -133,25 +133,25 @@ void __init rpc_init_irq(void) | |||
133 | 133 | ||
134 | switch (irq) { | 134 | switch (irq) { |
135 | case 0 ... 7: | 135 | case 0 ... 7: |
136 | set_irq_chip(irq, &iomd_a_chip); | 136 | irq_set_chip_and_handler(irq, &iomd_a_chip, |
137 | set_irq_handler(irq, handle_level_irq); | 137 | handle_level_irq); |
138 | set_irq_flags(irq, flags); | 138 | set_irq_flags(irq, flags); |
139 | break; | 139 | break; |
140 | 140 | ||
141 | case 8 ... 15: | 141 | case 8 ... 15: |
142 | set_irq_chip(irq, &iomd_b_chip); | 142 | irq_set_chip_and_handler(irq, &iomd_b_chip, |
143 | set_irq_handler(irq, handle_level_irq); | 143 | handle_level_irq); |
144 | set_irq_flags(irq, flags); | 144 | set_irq_flags(irq, flags); |
145 | break; | 145 | break; |
146 | 146 | ||
147 | case 16 ... 21: | 147 | case 16 ... 21: |
148 | set_irq_chip(irq, &iomd_dma_chip); | 148 | irq_set_chip_and_handler(irq, &iomd_dma_chip, |
149 | set_irq_handler(irq, handle_level_irq); | 149 | handle_level_irq); |
150 | set_irq_flags(irq, flags); | 150 | set_irq_flags(irq, flags); |
151 | break; | 151 | break; |
152 | 152 | ||
153 | case 64 ... 71: | 153 | case 64 ... 71: |
154 | set_irq_chip(irq, &iomd_fiq_chip); | 154 | irq_set_chip(irq, &iomd_fiq_chip); |
155 | set_irq_flags(irq, IRQF_VALID); | 155 | set_irq_flags(irq, IRQF_VALID); |
156 | break; | 156 | break; |
157 | } | 157 | } |
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 606cb6b1cc47..bc53d2d16d1a 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c | |||
@@ -147,15 +147,15 @@ static __init int bast_irq_init(void) | |||
147 | 147 | ||
148 | __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); | 148 | __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); |
149 | 149 | ||
150 | set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); | 150 | irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux); |
151 | 151 | ||
152 | /* register our IRQs */ | 152 | /* register our IRQs */ |
153 | 153 | ||
154 | for (i = 0; i < 4; i++) { | 154 | for (i = 0; i < 4; i++) { |
155 | unsigned int irqno = bast_pc104_irqs[i]; | 155 | unsigned int irqno = bast_pc104_irqs[i]; |
156 | 156 | ||
157 | set_irq_chip(irqno, &bast_pc104_chip); | 157 | irq_set_chip_and_handler(irqno, &bast_pc104_chip, |
158 | set_irq_handler(irqno, handle_level_irq); | 158 | handle_level_irq); |
159 | set_irq_flags(irqno, IRQF_VALID); | 159 | set_irq_flags(irqno, IRQF_VALID); |
160 | } | 160 | } |
161 | } | 161 | } |
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c index eddb52ba5b65..f3355d2ec634 100644 --- a/arch/arm/mach-s3c2412/irq.c +++ b/arch/arm/mach-s3c2412/irq.c | |||
@@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev) | |||
175 | unsigned int irqno; | 175 | unsigned int irqno; |
176 | 176 | ||
177 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 177 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
178 | set_irq_chip(irqno, &s3c2412_irq_eint0t4); | 178 | irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4, |
179 | set_irq_handler(irqno, handle_edge_irq); | 179 | handle_edge_irq); |
180 | set_irq_flags(irqno, IRQF_VALID); | 180 | set_irq_flags(irqno, IRQF_VALID); |
181 | } | 181 | } |
182 | 182 | ||
183 | /* add demux support for CF/SDI */ | 183 | /* add demux support for CF/SDI */ |
184 | 184 | ||
185 | set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); | 185 | irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); |
186 | 186 | ||
187 | for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { | 187 | for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { |
188 | set_irq_chip(irqno, &s3c2412_irq_cfsdi); | 188 | irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi, |
189 | set_irq_handler(irqno, handle_level_irq); | 189 | handle_level_irq); |
190 | set_irq_flags(irqno, IRQF_VALID); | 190 | set_irq_flags(irqno, IRQF_VALID); |
191 | } | 191 | } |
192 | 192 | ||
@@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev) | |||
195 | s3c2412_irq_rtc_chip = s3c_irq_chip; | 195 | s3c2412_irq_rtc_chip = s3c_irq_chip; |
196 | s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; | 196 | s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; |
197 | 197 | ||
198 | set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); | 198 | irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); |
199 | 199 | ||
200 | return 0; | 200 | return 0; |
201 | } | 201 | } |
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c index 680fe386aca5..77b38f2381c1 100644 --- a/arch/arm/mach-s3c2416/irq.c +++ b/arch/arm/mach-s3c2416/irq.c | |||
@@ -202,13 +202,11 @@ static int __init s3c2416_add_sub(unsigned int base, | |||
202 | { | 202 | { |
203 | unsigned int irqno; | 203 | unsigned int irqno; |
204 | 204 | ||
205 | set_irq_chip(base, &s3c_irq_level_chip); | 205 | irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); |
206 | set_irq_handler(base, handle_level_irq); | 206 | irq_set_chained_handler(base, demux); |
207 | set_irq_chained_handler(base, demux); | ||
208 | 207 | ||
209 | for (irqno = start; irqno <= end; irqno++) { | 208 | for (irqno = start; irqno <= end; irqno++) { |
210 | set_irq_chip(irqno, chip); | 209 | irq_set_chip_and_handler(irqno, chip, handle_level_irq); |
211 | set_irq_handler(irqno, handle_level_irq); | ||
212 | set_irq_flags(irqno, IRQF_VALID); | 210 | set_irq_flags(irqno, IRQF_VALID); |
213 | } | 211 | } |
214 | 212 | ||
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index acad4428bef0..eb1cc0f0705e 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c | |||
@@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev) | |||
100 | 100 | ||
101 | /* add new chained handler for wdt, ac7 */ | 101 | /* add new chained handler for wdt, ac7 */ |
102 | 102 | ||
103 | set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); | 103 | irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip, |
104 | set_irq_handler(IRQ_WDT, handle_level_irq); | 104 | handle_level_irq); |
105 | set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); | 105 | irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); |
106 | 106 | ||
107 | for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { | 107 | for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { |
108 | set_irq_chip(irqno, &s3c_irq_wdtac97); | 108 | irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97, |
109 | set_irq_handler(irqno, handle_level_irq); | 109 | handle_level_irq); |
110 | set_irq_flags(irqno, IRQF_VALID); | 110 | set_irq_flags(irqno, IRQF_VALID); |
111 | } | 111 | } |
112 | 112 | ||
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c index 83daf4ece764..de07c2feaa32 100644 --- a/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/arch/arm/mach-s3c2440/s3c244x-irq.c | |||
@@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev) | |||
95 | { | 95 | { |
96 | unsigned int irqno; | 96 | unsigned int irqno; |
97 | 97 | ||
98 | set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip); | 98 | irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip, |
99 | set_irq_handler(IRQ_NFCON, handle_level_irq); | 99 | handle_level_irq); |
100 | set_irq_flags(IRQ_NFCON, IRQF_VALID); | 100 | set_irq_flags(IRQ_NFCON, IRQF_VALID); |
101 | 101 | ||
102 | /* add chained handler for camera */ | 102 | /* add chained handler for camera */ |
103 | 103 | ||
104 | set_irq_chip(IRQ_CAM, &s3c_irq_level_chip); | 104 | irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip, |
105 | set_irq_handler(IRQ_CAM, handle_level_irq); | 105 | handle_level_irq); |
106 | set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam); | 106 | irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam); |
107 | 107 | ||
108 | for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { | 108 | for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) { |
109 | set_irq_chip(irqno, &s3c_irq_cam); | 109 | irq_set_chip_and_handler(irqno, &s3c_irq_cam, |
110 | set_irq_handler(irqno, handle_level_irq); | 110 | handle_level_irq); |
111 | set_irq_flags(irqno, IRQF_VALID); | 111 | set_irq_flags(irqno, IRQF_VALID); |
112 | } | 112 | } |
113 | 113 | ||
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c index c7820f9c1352..83ecb1173fb1 100644 --- a/arch/arm/mach-s3c2443/irq.c +++ b/arch/arm/mach-s3c2443/irq.c | |||
@@ -230,13 +230,11 @@ static int __init s3c2443_add_sub(unsigned int base, | |||
230 | { | 230 | { |
231 | unsigned int irqno; | 231 | unsigned int irqno; |
232 | 232 | ||
233 | set_irq_chip(base, &s3c_irq_level_chip); | 233 | irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq); |
234 | set_irq_handler(base, handle_level_irq); | 234 | irq_set_chained_handler(base, demux); |
235 | set_irq_chained_handler(base, demux); | ||
236 | 235 | ||
237 | for (irqno = start; irqno <= end; irqno++) { | 236 | for (irqno = start; irqno <= end; irqno++) { |
238 | set_irq_chip(irqno, chip); | 237 | irq_set_chip_and_handler(irqno, chip, handle_level_irq); |
239 | set_irq_handler(irqno, handle_level_irq); | ||
240 | set_irq_flags(irqno, IRQF_VALID); | 238 | set_irq_flags(irqno, IRQF_VALID); |
241 | } | 239 | } |
242 | 240 | ||
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c index 2ead8189da74..4d203be1f4c3 100644 --- a/arch/arm/mach-s3c64xx/irq-eint.c +++ b/arch/arm/mach-s3c64xx/irq-eint.c | |||
@@ -197,16 +197,15 @@ static int __init s3c64xx_init_irq_eint(void) | |||
197 | int irq; | 197 | int irq; |
198 | 198 | ||
199 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { | 199 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { |
200 | set_irq_chip(irq, &s3c_irq_eint); | 200 | irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); |
201 | set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); | 201 | irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq)); |
202 | set_irq_handler(irq, handle_level_irq); | ||
203 | set_irq_flags(irq, IRQF_VALID); | 202 | set_irq_flags(irq, IRQF_VALID); |
204 | } | 203 | } |
205 | 204 | ||
206 | set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); | 205 | irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); |
207 | set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); | 206 | irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); |
208 | set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); | 207 | irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); |
209 | set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); | 208 | irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); |
210 | 209 | ||
211 | return 0; | 210 | return 0; |
212 | } | 211 | } |
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 98d780608c7e..7f3da4b11ec9 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c | |||
@@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = { | |||
96 | static void __init cerf_init_irq(void) | 96 | static void __init cerf_init_irq(void) |
97 | { | 97 | { |
98 | sa1100_init_irq(); | 98 | sa1100_init_irq(); |
99 | set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); | 99 | irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING); |
100 | } | 100 | } |
101 | 101 | ||
102 | static struct map_desc cerf_io_desc[] __initdata = { | 102 | static struct map_desc cerf_io_desc[] __initdata = { |
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 3d85dfad9c1f..423ddb3d65e9 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c | |||
@@ -323,28 +323,28 @@ void __init sa1100_init_irq(void) | |||
323 | ICCR = 1; | 323 | ICCR = 1; |
324 | 324 | ||
325 | for (irq = 0; irq <= 10; irq++) { | 325 | for (irq = 0; irq <= 10; irq++) { |
326 | set_irq_chip(irq, &sa1100_low_gpio_chip); | 326 | irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip, |
327 | set_irq_handler(irq, handle_edge_irq); | 327 | handle_edge_irq); |
328 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 328 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
329 | } | 329 | } |
330 | 330 | ||
331 | for (irq = 12; irq <= 31; irq++) { | 331 | for (irq = 12; irq <= 31; irq++) { |
332 | set_irq_chip(irq, &sa1100_normal_chip); | 332 | irq_set_chip_and_handler(irq, &sa1100_normal_chip, |
333 | set_irq_handler(irq, handle_level_irq); | 333 | handle_level_irq); |
334 | set_irq_flags(irq, IRQF_VALID); | 334 | set_irq_flags(irq, IRQF_VALID); |
335 | } | 335 | } |
336 | 336 | ||
337 | for (irq = 32; irq <= 48; irq++) { | 337 | for (irq = 32; irq <= 48; irq++) { |
338 | set_irq_chip(irq, &sa1100_high_gpio_chip); | 338 | irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip, |
339 | set_irq_handler(irq, handle_edge_irq); | 339 | handle_edge_irq); |
340 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 340 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
341 | } | 341 | } |
342 | 342 | ||
343 | /* | 343 | /* |
344 | * Install handler for GPIO 11-27 edge detect interrupts | 344 | * Install handler for GPIO 11-27 edge detect interrupts |
345 | */ | 345 | */ |
346 | set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip); | 346 | irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip); |
347 | set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); | 347 | irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); |
348 | 348 | ||
349 | sa1100_init_gpio(); | 349 | sa1100_init_gpio(); |
350 | } | 350 | } |
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 4aad01f73660..b4fa53a1427e 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c | |||
@@ -145,8 +145,8 @@ static int __devinit neponset_probe(struct platform_device *dev) | |||
145 | /* | 145 | /* |
146 | * Install handler for GPIO25. | 146 | * Install handler for GPIO25. |
147 | */ | 147 | */ |
148 | set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); | 148 | irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING); |
149 | set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler); | 149 | irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler); |
150 | 150 | ||
151 | /* | 151 | /* |
152 | * We would set IRQ_GPIO25 to be a wake-up IRQ, but | 152 | * We would set IRQ_GPIO25 to be a wake-up IRQ, but |
@@ -161,9 +161,9 @@ static int __devinit neponset_probe(struct platform_device *dev) | |||
161 | * Setup other Neponset IRQs. SA1111 will be done by the | 161 | * Setup other Neponset IRQs. SA1111 will be done by the |
162 | * generic SA1111 code. | 162 | * generic SA1111 code. |
163 | */ | 163 | */ |
164 | set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); | 164 | irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq); |
165 | set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); | 165 | set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE); |
166 | set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq); | 166 | irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq); |
167 | set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); | 167 | set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE); |
168 | 168 | ||
169 | /* | 169 | /* |
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index 42b80400c100..65161f2bea29 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c | |||
@@ -142,7 +142,7 @@ static void __init pleb_map_io(void) | |||
142 | 142 | ||
143 | GPDR &= ~GPIO_ETH0_IRQ; | 143 | GPDR &= ~GPIO_ETH0_IRQ; |
144 | 144 | ||
145 | set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); | 145 | irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING); |
146 | } | 146 | } |
147 | 147 | ||
148 | MACHINE_START(PLEB, "PLEB") | 148 | MACHINE_START(PLEB, "PLEB") |
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c index 831fc66dfa4d..5dce13e429f3 100644 --- a/arch/arm/mach-shark/irq.c +++ b/arch/arm/mach-shark/irq.c | |||
@@ -80,8 +80,7 @@ void __init shark_init_irq(void) | |||
80 | int irq; | 80 | int irq; |
81 | 81 | ||
82 | for (irq = 0; irq < NR_IRQS; irq++) { | 82 | for (irq = 0; irq < NR_IRQS; irq++) { |
83 | set_irq_chip(irq, &fb_chip); | 83 | irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq); |
84 | set_irq_handler(irq, handle_edge_irq); | ||
85 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 84 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
86 | } | 85 | } |
87 | 86 | ||
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c index a94f29da5d30..783b66fa95fb 100644 --- a/arch/arm/mach-shmobile/board-ap4evb.c +++ b/arch/arm/mach-shmobile/board-ap4evb.c | |||
@@ -24,9 +24,9 @@ | |||
24 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
25 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
26 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
27 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
28 | #include <linux/mfd/tmio.h> | 27 | #include <linux/mfd/tmio.h> |
29 | #include <linux/mmc/host.h> | 28 | #include <linux/mmc/host.h> |
29 | #include <linux/mmc/sh_mobile_sdhi.h> | ||
30 | #include <linux/mtd/mtd.h> | 30 | #include <linux/mtd/mtd.h> |
31 | #include <linux/mtd/partitions.h> | 31 | #include <linux/mtd/partitions.h> |
32 | #include <linux/mtd/physmap.h> | 32 | #include <linux/mtd/physmap.h> |
@@ -312,7 +312,7 @@ static struct resource sdhi0_resources[] = { | |||
312 | [0] = { | 312 | [0] = { |
313 | .name = "SDHI0", | 313 | .name = "SDHI0", |
314 | .start = 0xe6850000, | 314 | .start = 0xe6850000, |
315 | .end = 0xe68501ff, | 315 | .end = 0xe68500ff, |
316 | .flags = IORESOURCE_MEM, | 316 | .flags = IORESOURCE_MEM, |
317 | }, | 317 | }, |
318 | [1] = { | 318 | [1] = { |
@@ -345,7 +345,7 @@ static struct resource sdhi1_resources[] = { | |||
345 | [0] = { | 345 | [0] = { |
346 | .name = "SDHI1", | 346 | .name = "SDHI1", |
347 | .start = 0xe6860000, | 347 | .start = 0xe6860000, |
348 | .end = 0xe68601ff, | 348 | .end = 0xe68600ff, |
349 | .flags = IORESOURCE_MEM, | 349 | .flags = IORESOURCE_MEM, |
350 | }, | 350 | }, |
351 | [1] = { | 351 | [1] = { |
@@ -1255,7 +1255,7 @@ static void __init ap4evb_init(void) | |||
1255 | gpio_request(GPIO_FN_KEYIN4, NULL); | 1255 | gpio_request(GPIO_FN_KEYIN4, NULL); |
1256 | 1256 | ||
1257 | /* enable TouchScreen */ | 1257 | /* enable TouchScreen */ |
1258 | set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); | 1258 | irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW); |
1259 | 1259 | ||
1260 | tsc_device.irq = IRQ28; | 1260 | tsc_device.irq = IRQ28; |
1261 | i2c_register_board_info(1, &tsc_device, 1); | 1261 | i2c_register_board_info(1, &tsc_device, 1); |
@@ -1311,7 +1311,7 @@ static void __init ap4evb_init(void) | |||
1311 | lcdc_info.ch[0].lcd_size_cfg.height = 91; | 1311 | lcdc_info.ch[0].lcd_size_cfg.height = 91; |
1312 | 1312 | ||
1313 | /* enable TouchScreen */ | 1313 | /* enable TouchScreen */ |
1314 | set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); | 1314 | irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); |
1315 | 1315 | ||
1316 | tsc_device.irq = IRQ7; | 1316 | tsc_device.irq = IRQ7; |
1317 | i2c_register_board_info(0, &tsc_device, 1); | 1317 | i2c_register_board_info(0, &tsc_device, 1); |
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c index dee3e9231fb9..c87a7b7c5832 100644 --- a/arch/arm/mach-shmobile/board-g4evm.c +++ b/arch/arm/mach-shmobile/board-g4evm.c | |||
@@ -31,7 +31,7 @@ | |||
31 | #include <linux/input.h> | 31 | #include <linux/input.h> |
32 | #include <linux/input/sh_keysc.h> | 32 | #include <linux/input/sh_keysc.h> |
33 | #include <linux/mmc/host.h> | 33 | #include <linux/mmc/host.h> |
34 | #include <linux/mfd/sh_mobile_sdhi.h> | 34 | #include <linux/mmc/sh_mobile_sdhi.h> |
35 | #include <linux/gpio.h> | 35 | #include <linux/gpio.h> |
36 | #include <mach/sh7377.h> | 36 | #include <mach/sh7377.h> |
37 | #include <mach/common.h> | 37 | #include <mach/common.h> |
@@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = { | |||
205 | [0] = { | 205 | [0] = { |
206 | .name = "SDHI0", | 206 | .name = "SDHI0", |
207 | .start = 0xe6d50000, | 207 | .start = 0xe6d50000, |
208 | .end = 0xe6d501ff, | 208 | .end = 0xe6d50nff, |
209 | .flags = IORESOURCE_MEM, | 209 | .flags = IORESOURCE_MEM, |
210 | }, | 210 | }, |
211 | [1] = { | 211 | [1] = { |
@@ -232,7 +232,7 @@ static struct resource sdhi1_resources[] = { | |||
232 | [0] = { | 232 | [0] = { |
233 | .name = "SDHI1", | 233 | .name = "SDHI1", |
234 | .start = 0xe6d60000, | 234 | .start = 0xe6d60000, |
235 | .end = 0xe6d601ff, | 235 | .end = 0xe6d600ff, |
236 | .flags = IORESOURCE_MEM, | 236 | .flags = IORESOURCE_MEM, |
237 | }, | 237 | }, |
238 | [1] = { | 238 | [1] = { |
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 49bc07482179..8184d4d4f234 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c | |||
@@ -32,10 +32,10 @@ | |||
32 | #include <linux/io.h> | 32 | #include <linux/io.h> |
33 | #include <linux/i2c.h> | 33 | #include <linux/i2c.h> |
34 | #include <linux/leds.h> | 34 | #include <linux/leds.h> |
35 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
36 | #include <linux/mfd/tmio.h> | 35 | #include <linux/mfd/tmio.h> |
37 | #include <linux/mmc/host.h> | 36 | #include <linux/mmc/host.h> |
38 | #include <linux/mmc/sh_mmcif.h> | 37 | #include <linux/mmc/sh_mmcif.h> |
38 | #include <linux/mmc/sh_mobile_sdhi.h> | ||
39 | #include <linux/mtd/mtd.h> | 39 | #include <linux/mtd/mtd.h> |
40 | #include <linux/mtd/partitions.h> | 40 | #include <linux/mtd/partitions.h> |
41 | #include <linux/mtd/physmap.h> | 41 | #include <linux/mtd/physmap.h> |
@@ -690,7 +690,7 @@ static struct resource sdhi0_resources[] = { | |||
690 | [0] = { | 690 | [0] = { |
691 | .name = "SDHI0", | 691 | .name = "SDHI0", |
692 | .start = 0xe6850000, | 692 | .start = 0xe6850000, |
693 | .end = 0xe68501ff, | 693 | .end = 0xe68500ff, |
694 | .flags = IORESOURCE_MEM, | 694 | .flags = IORESOURCE_MEM, |
695 | }, | 695 | }, |
696 | [1] = { | 696 | [1] = { |
@@ -725,7 +725,7 @@ static struct resource sdhi1_resources[] = { | |||
725 | [0] = { | 725 | [0] = { |
726 | .name = "SDHI1", | 726 | .name = "SDHI1", |
727 | .start = 0xe6860000, | 727 | .start = 0xe6860000, |
728 | .end = 0xe68601ff, | 728 | .end = 0xe68600ff, |
729 | .flags = IORESOURCE_MEM, | 729 | .flags = IORESOURCE_MEM, |
730 | }, | 730 | }, |
731 | [1] = { | 731 | [1] = { |
@@ -768,7 +768,7 @@ static struct resource sdhi2_resources[] = { | |||
768 | [0] = { | 768 | [0] = { |
769 | .name = "SDHI2", | 769 | .name = "SDHI2", |
770 | .start = 0xe6870000, | 770 | .start = 0xe6870000, |
771 | .end = 0xe68701ff, | 771 | .end = 0xe68700ff, |
772 | .flags = IORESOURCE_MEM, | 772 | .flags = IORESOURCE_MEM, |
773 | }, | 773 | }, |
774 | [1] = { | 774 | [1] = { |
@@ -1124,15 +1124,15 @@ static void __init mackerel_init(void) | |||
1124 | 1124 | ||
1125 | /* enable Keypad */ | 1125 | /* enable Keypad */ |
1126 | gpio_request(GPIO_FN_IRQ9_42, NULL); | 1126 | gpio_request(GPIO_FN_IRQ9_42, NULL); |
1127 | set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); | 1127 | irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH); |
1128 | 1128 | ||
1129 | /* enable Touchscreen */ | 1129 | /* enable Touchscreen */ |
1130 | gpio_request(GPIO_FN_IRQ7_40, NULL); | 1130 | gpio_request(GPIO_FN_IRQ7_40, NULL); |
1131 | set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); | 1131 | irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW); |
1132 | 1132 | ||
1133 | /* enable Accelerometer */ | 1133 | /* enable Accelerometer */ |
1134 | gpio_request(GPIO_FN_IRQ21, NULL); | 1134 | gpio_request(GPIO_FN_IRQ21, NULL); |
1135 | set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); | 1135 | irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); |
1136 | 1136 | ||
1137 | /* enable SDHI0 */ | 1137 | /* enable SDHI0 */ |
1138 | gpio_request(GPIO_FN_SDHICD0, NULL); | 1138 | gpio_request(GPIO_FN_SDHICD0, NULL); |
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c index 2fe9704d5ea1..cc442d198cdc 100644 --- a/arch/arm/mach-shmobile/intc-sh7367.c +++ b/arch/arm/mach-shmobile/intc-sh7367.c | |||
@@ -421,7 +421,7 @@ static struct intc_desc intcs_desc __initdata = { | |||
421 | 421 | ||
422 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | 422 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) |
423 | { | 423 | { |
424 | void __iomem *reg = (void *)get_irq_data(irq); | 424 | void __iomem *reg = (void *)irq_get_handler_data(irq); |
425 | unsigned int evtcodeas = ioread32(reg); | 425 | unsigned int evtcodeas = ioread32(reg); |
426 | 426 | ||
427 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | 427 | generic_handle_irq(intcs_evt2irq(evtcodeas)); |
@@ -435,6 +435,6 @@ void __init sh7367_init_irq(void) | |||
435 | register_intc_controller(&intcs_desc); | 435 | register_intc_controller(&intcs_desc); |
436 | 436 | ||
437 | /* demux using INTEVTSA */ | 437 | /* demux using INTEVTSA */ |
438 | set_irq_data(evt2irq(0xf80), (void *)intevtsa); | 438 | irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); |
439 | set_irq_chained_handler(evt2irq(0xf80), intcs_demux); | 439 | irq_set_chained_handler(evt2irq(0xf80), intcs_demux); |
440 | } | 440 | } |
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index ca5f9d17b39a..7a4960f9c1e3 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c | |||
@@ -601,7 +601,7 @@ static struct intc_desc intcs_desc __initdata = { | |||
601 | 601 | ||
602 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | 602 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) |
603 | { | 603 | { |
604 | void __iomem *reg = (void *)get_irq_data(irq); | 604 | void __iomem *reg = (void *)irq_get_handler_data(irq); |
605 | unsigned int evtcodeas = ioread32(reg); | 605 | unsigned int evtcodeas = ioread32(reg); |
606 | 606 | ||
607 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | 607 | generic_handle_irq(intcs_evt2irq(evtcodeas)); |
@@ -615,6 +615,6 @@ void __init sh7372_init_irq(void) | |||
615 | register_intc_controller(&intcs_desc); | 615 | register_intc_controller(&intcs_desc); |
616 | 616 | ||
617 | /* demux using INTEVTSA */ | 617 | /* demux using INTEVTSA */ |
618 | set_irq_data(evt2irq(0xf80), (void *)intevtsa); | 618 | irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); |
619 | set_irq_chained_handler(evt2irq(0xf80), intcs_demux); | 619 | irq_set_chained_handler(evt2irq(0xf80), intcs_demux); |
620 | } | 620 | } |
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c index dd568382cc9f..fe45154ce660 100644 --- a/arch/arm/mach-shmobile/intc-sh7377.c +++ b/arch/arm/mach-shmobile/intc-sh7377.c | |||
@@ -626,7 +626,7 @@ static struct intc_desc intcs_desc __initdata = { | |||
626 | 626 | ||
627 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) | 627 | static void intcs_demux(unsigned int irq, struct irq_desc *desc) |
628 | { | 628 | { |
629 | void __iomem *reg = (void *)get_irq_data(irq); | 629 | void __iomem *reg = (void *)irq_get_handler_data(irq); |
630 | unsigned int evtcodeas = ioread32(reg); | 630 | unsigned int evtcodeas = ioread32(reg); |
631 | 631 | ||
632 | generic_handle_irq(intcs_evt2irq(evtcodeas)); | 632 | generic_handle_irq(intcs_evt2irq(evtcodeas)); |
@@ -641,6 +641,6 @@ void __init sh7377_init_irq(void) | |||
641 | register_intc_controller(&intcs_desc); | 641 | register_intc_controller(&intcs_desc); |
642 | 642 | ||
643 | /* demux using INTEVTSA */ | 643 | /* demux using INTEVTSA */ |
644 | set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); | 644 | irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa); |
645 | set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); | 645 | irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux); |
646 | } | 646 | } |
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c index aa9231f4fc6e..209fa5c65d4c 100644 --- a/arch/arm/mach-tcc8k/irq.c +++ b/arch/arm/mach-tcc8k/irq.c | |||
@@ -102,10 +102,10 @@ void __init tcc8k_init_irq(void) | |||
102 | 102 | ||
103 | for (irqno = 0; irqno < NR_IRQS; irqno++) { | 103 | for (irqno = 0; irqno < NR_IRQS; irqno++) { |
104 | if (irqno < 32) | 104 | if (irqno < 32) |
105 | set_irq_chip(irqno, &tcc8000_irq_chip0); | 105 | irq_set_chip(irqno, &tcc8000_irq_chip0); |
106 | else | 106 | else |
107 | set_irq_chip(irqno, &tcc8000_irq_chip1); | 107 | irq_set_chip(irqno, &tcc8000_irq_chip1); |
108 | set_irq_handler(irqno, handle_level_irq); | 108 | irq_set_handler(irqno, handle_level_irq); |
109 | set_irq_flags(irqno, IRQF_VALID); | 109 | set_irq_flags(irqno, IRQF_VALID); |
110 | } | 110 | } |
111 | } | 111 | } |
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c index 12090a2cf3e0..76a3f654220f 100644 --- a/arch/arm/mach-tegra/gpio.c +++ b/arch/arm/mach-tegra/gpio.c | |||
@@ -208,9 +208,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
208 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | 208 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
209 | 209 | ||
210 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | 210 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
211 | __set_irq_handler_unlocked(d->irq, handle_level_irq); | 211 | __irq_set_handler_locked(d->irq, handle_level_irq); |
212 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 212 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
213 | __set_irq_handler_unlocked(d->irq, handle_edge_irq); | 213 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
214 | 214 | ||
215 | return 0; | 215 | return 0; |
216 | } | 216 | } |
@@ -224,7 +224,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
224 | 224 | ||
225 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 225 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
226 | 226 | ||
227 | bank = get_irq_data(irq); | 227 | bank = irq_get_handler_data(irq); |
228 | 228 | ||
229 | for (port = 0; port < 4; port++) { | 229 | for (port = 0; port < 4; port++) { |
230 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | 230 | int gpio = tegra_gpio_compose(bank->bank, port, 0); |
@@ -275,13 +275,6 @@ void tegra_gpio_resume(void) | |||
275 | } | 275 | } |
276 | 276 | ||
277 | local_irq_restore(flags); | 277 | local_irq_restore(flags); |
278 | |||
279 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { | ||
280 | struct irq_desc *desc = irq_to_desc(i); | ||
281 | if (!desc || (desc->status & IRQ_WAKEUP)) | ||
282 | continue; | ||
283 | enable_irq(i); | ||
284 | } | ||
285 | } | 278 | } |
286 | 279 | ||
287 | void tegra_gpio_suspend(void) | 280 | void tegra_gpio_suspend(void) |
@@ -289,18 +282,6 @@ void tegra_gpio_suspend(void) | |||
289 | unsigned long flags; | 282 | unsigned long flags; |
290 | int b, p, i; | 283 | int b, p, i; |
291 | 284 | ||
292 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { | ||
293 | struct irq_desc *desc = irq_to_desc(i); | ||
294 | if (!desc) | ||
295 | continue; | ||
296 | if (desc->status & IRQ_WAKEUP) { | ||
297 | int gpio = i - INT_GPIO_BASE; | ||
298 | pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7); | ||
299 | continue; | ||
300 | } | ||
301 | disable_irq(i); | ||
302 | } | ||
303 | |||
304 | local_irq_save(flags); | 285 | local_irq_save(flags); |
305 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { | 286 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { |
306 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; | 287 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
@@ -320,7 +301,7 @@ void tegra_gpio_suspend(void) | |||
320 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) | 301 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
321 | { | 302 | { |
322 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); | 303 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
323 | return set_irq_wake(bank->irq, enable); | 304 | return irq_set_irq_wake(bank->irq, enable); |
324 | } | 305 | } |
325 | #endif | 306 | #endif |
326 | 307 | ||
@@ -359,18 +340,18 @@ static int __init tegra_gpio_init(void) | |||
359 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { | 340 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { |
360 | bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; | 341 | bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; |
361 | 342 | ||
362 | lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); | 343 | irq_set_lockdep_class(i, &gpio_lock_class); |
363 | set_irq_chip_data(i, bank); | 344 | irq_set_chip_data(i, bank); |
364 | set_irq_chip(i, &tegra_gpio_irq_chip); | 345 | irq_set_chip_and_handler(i, &tegra_gpio_irq_chip, |
365 | set_irq_handler(i, handle_simple_irq); | 346 | handle_simple_irq); |
366 | set_irq_flags(i, IRQF_VALID); | 347 | set_irq_flags(i, IRQF_VALID); |
367 | } | 348 | } |
368 | 349 | ||
369 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { | 350 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { |
370 | bank = &tegra_gpio_banks[i]; | 351 | bank = &tegra_gpio_banks[i]; |
371 | 352 | ||
372 | set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); | 353 | irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); |
373 | set_irq_data(bank->irq, bank); | 354 | irq_set_handler_data(bank->irq, bank); |
374 | 355 | ||
375 | for (j = 0; j < 4; j++) | 356 | for (j = 0; j < 4; j++) |
376 | spin_lock_init(&bank->lvl_lock[j]); | 357 | spin_lock_init(&bank->lvl_lock[j]); |
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index dfbc219ea492..4330d8995b27 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
@@ -144,7 +144,7 @@ void __init tegra_init_irq(void) | |||
144 | gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), | 144 | gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), |
145 | IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); | 145 | IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); |
146 | 146 | ||
147 | gic = get_irq_chip(29); | 147 | gic = irq_get_chip(29); |
148 | tegra_gic_unmask_irq = gic->irq_unmask; | 148 | tegra_gic_unmask_irq = gic->irq_unmask; |
149 | tegra_gic_mask_irq = gic->irq_mask; | 149 | tegra_gic_mask_irq = gic->irq_mask; |
150 | tegra_gic_ack_irq = gic->irq_ack; | 150 | tegra_gic_ack_irq = gic->irq_ack; |
@@ -154,8 +154,7 @@ void __init tegra_init_irq(void) | |||
154 | 154 | ||
155 | for (i = 0; i < INT_MAIN_NR; i++) { | 155 | for (i = 0; i < INT_MAIN_NR; i++) { |
156 | irq = INT_PRI_BASE + i; | 156 | irq = INT_PRI_BASE + i; |
157 | set_irq_chip(irq, &tegra_irq); | 157 | irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq); |
158 | set_irq_handler(irq, handle_level_irq); | ||
159 | set_irq_flags(irq, IRQF_VALID); | 158 | set_irq_flags(irq, IRQF_VALID); |
160 | } | 159 | } |
161 | } | 160 | } |
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c index e1296a7447c8..6b86416c94c9 100644 --- a/arch/arm/mach-ux500/modem-irq-db5500.c +++ b/arch/arm/mach-ux500/modem-irq-db5500.c | |||
@@ -90,8 +90,7 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data) | |||
90 | 90 | ||
91 | static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) | 91 | static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip) |
92 | { | 92 | { |
93 | set_irq_chip(irq, modem_irq_chip); | 93 | irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq); |
94 | set_irq_handler(irq, handle_simple_irq); | ||
95 | set_irq_flags(irq, IRQF_VALID); | 94 | set_irq_flags(irq, IRQF_VALID); |
96 | 95 | ||
97 | pr_debug("modem_irq: Created virtual IRQ %d\n", irq); | 96 | pr_debug("modem_irq: Created virtual IRQ %d\n", irq); |
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c index 5f4ddde4f02a..245140c0df10 100644 --- a/arch/arm/mach-vt8500/irq.c +++ b/arch/arm/mach-vt8500/irq.c | |||
@@ -97,15 +97,15 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) | |||
97 | return -EINVAL; | 97 | return -EINVAL; |
98 | case IRQF_TRIGGER_HIGH: | 98 | case IRQF_TRIGGER_HIGH: |
99 | dctr |= VT8500_TRIGGER_HIGH; | 99 | dctr |= VT8500_TRIGGER_HIGH; |
100 | irq_desc[orig_irq].handle_irq = handle_level_irq; | 100 | __irq_set_handler_locked(orig_irq, handle_level_irq); |
101 | break; | 101 | break; |
102 | case IRQF_TRIGGER_FALLING: | 102 | case IRQF_TRIGGER_FALLING: |
103 | dctr |= VT8500_TRIGGER_FALLING; | 103 | dctr |= VT8500_TRIGGER_FALLING; |
104 | irq_desc[orig_irq].handle_irq = handle_edge_irq; | 104 | __irq_set_handler_locked(orig_irq, handle_edge_irq); |
105 | break; | 105 | break; |
106 | case IRQF_TRIGGER_RISING: | 106 | case IRQF_TRIGGER_RISING: |
107 | dctr |= VT8500_TRIGGER_RISING; | 107 | dctr |= VT8500_TRIGGER_RISING; |
108 | irq_desc[orig_irq].handle_irq = handle_edge_irq; | 108 | __irq_set_handler_locked(orig_irq, handle_edge_irq); |
109 | break; | 109 | break; |
110 | } | 110 | } |
111 | writeb(dctr, base + VT8500_IC_DCTR + irq); | 111 | writeb(dctr, base + VT8500_IC_DCTR + irq); |
@@ -136,8 +136,8 @@ void __init vt8500_init_irq(void) | |||
136 | /* Disable all interrupts and route them to IRQ */ | 136 | /* Disable all interrupts and route them to IRQ */ |
137 | writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); | 137 | writeb(0x00, ic_regbase + VT8500_IC_DCTR + i); |
138 | 138 | ||
139 | set_irq_chip(i, &vt8500_irq_chip); | 139 | irq_set_chip_and_handler(i, &vt8500_irq_chip, |
140 | set_irq_handler(i, handle_level_irq); | 140 | handle_level_irq); |
141 | set_irq_flags(i, IRQF_VALID); | 141 | set_irq_flags(i, IRQF_VALID); |
142 | } | 142 | } |
143 | } else { | 143 | } else { |
@@ -167,8 +167,8 @@ void __init wm8505_init_irq(void) | |||
167 | writeb(0x00, sic_regbase + VT8500_IC_DCTR | 167 | writeb(0x00, sic_regbase + VT8500_IC_DCTR |
168 | + i - 64); | 168 | + i - 64); |
169 | 169 | ||
170 | set_irq_chip(i, &vt8500_irq_chip); | 170 | irq_set_chip_and_handler(i, &vt8500_irq_chip, |
171 | set_irq_handler(i, handle_level_irq); | 171 | handle_level_irq); |
172 | set_irq_flags(i, IRQF_VALID); | 172 | set_irq_flags(i, IRQF_VALID); |
173 | } | 173 | } |
174 | } else { | 174 | } else { |
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index 9c350103dcda..7bf143c443f1 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c | |||
@@ -207,8 +207,8 @@ void __init nuc900_init_irq(void) | |||
207 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); | 207 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); |
208 | 208 | ||
209 | for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { | 209 | for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { |
210 | set_irq_chip(irqno, &nuc900_irq_chip); | 210 | irq_set_chip_and_handler(irqno, &nuc900_irq_chip, |
211 | set_irq_handler(irqno, handle_level_irq); | 211 | handle_level_irq); |
212 | set_irq_flags(irqno, IRQF_VALID); | 212 | set_irq_flags(irqno, IRQF_VALID); |
213 | } | 213 | } |
214 | } | 214 | } |
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c index c856fa397606..f0ba0726306c 100644 --- a/arch/arm/plat-mxc/3ds_debugboard.c +++ b/arch/arm/plat-mxc/3ds_debugboard.c | |||
@@ -100,14 +100,9 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc) | |||
100 | 100 | ||
101 | expio_irq = MXC_BOARD_IRQ_START; | 101 | expio_irq = MXC_BOARD_IRQ_START; |
102 | for (; int_valid != 0; int_valid >>= 1, expio_irq++) { | 102 | for (; int_valid != 0; int_valid >>= 1, expio_irq++) { |
103 | struct irq_desc *d; | ||
104 | if ((int_valid & 1) == 0) | 103 | if ((int_valid & 1) == 0) |
105 | continue; | 104 | continue; |
106 | d = irq_desc + expio_irq; | 105 | generic_handle_irq(expio_irq); |
107 | if (unlikely(!(d->handle_irq))) | ||
108 | pr_err("\nEXPIO irq: %d unhandled\n", expio_irq); | ||
109 | else | ||
110 | d->handle_irq(expio_irq, d); | ||
111 | } | 106 | } |
112 | 107 | ||
113 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 108 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
@@ -186,12 +181,11 @@ int __init mxc_expio_init(u32 base, u32 p_irq) | |||
186 | __raw_writew(0x1F, brd_io + INTR_MASK_REG); | 181 | __raw_writew(0x1F, brd_io + INTR_MASK_REG); |
187 | for (i = MXC_EXP_IO_BASE; | 182 | for (i = MXC_EXP_IO_BASE; |
188 | i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { | 183 | i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { |
189 | set_irq_chip(i, &expio_irq_chip); | 184 | irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); |
190 | set_irq_handler(i, handle_level_irq); | ||
191 | set_irq_flags(i, IRQF_VALID); | 185 | set_irq_flags(i, IRQF_VALID); |
192 | } | 186 | } |
193 | set_irq_type(p_irq, IRQF_TRIGGER_LOW); | 187 | irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); |
194 | set_irq_chained_handler(p_irq, mxc_expio_irq_handler); | 188 | irq_set_chained_handler(p_irq, mxc_expio_irq_handler); |
195 | 189 | ||
196 | /* Register Lan device on the debugboard */ | 190 | /* Register Lan device on the debugboard */ |
197 | smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); | 191 | smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); |
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c index deb284bc7c4b..09e2bd0fcdca 100644 --- a/arch/arm/plat-mxc/avic.c +++ b/arch/arm/plat-mxc/avic.c | |||
@@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase) | |||
139 | __raw_writel(0, avic_base + AVIC_INTTYPEH); | 139 | __raw_writel(0, avic_base + AVIC_INTTYPEH); |
140 | __raw_writel(0, avic_base + AVIC_INTTYPEL); | 140 | __raw_writel(0, avic_base + AVIC_INTTYPEL); |
141 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 141 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { |
142 | set_irq_chip(i, &mxc_avic_chip.base); | 142 | irq_set_chip_and_handler(i, &mxc_avic_chip.base, |
143 | set_irq_handler(i, handle_level_irq); | 143 | handle_level_irq); |
144 | set_irq_flags(i, IRQF_VALID); | 144 | set_irq_flags(i, IRQF_VALID); |
145 | } | 145 | } |
146 | 146 | ||
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index 6561c9df5f0d..ccc789e21daa 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c | |||
@@ -53,7 +53,7 @@ struct platform_device *__init imx_add_fec( | |||
53 | struct resource res[] = { | 53 | struct resource res[] = { |
54 | { | 54 | { |
55 | .start = data->iobase, | 55 | .start = data->iobase, |
56 | .end = data->iobase + SZ_4K, | 56 | .end = data->iobase + SZ_4K - 1, |
57 | .flags = IORESOURCE_MEM, | 57 | .flags = IORESOURCE_MEM, |
58 | }, { | 58 | }, { |
59 | .start = data->irq, | 59 | .start = data->irq, |
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c index 10653cc8d1fa..805336fdc252 100644 --- a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c +++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c | |||
@@ -27,7 +27,7 @@ struct platform_device *__init imx_add_imxdi_rtc( | |||
27 | struct resource res[] = { | 27 | struct resource res[] = { |
28 | { | 28 | { |
29 | .start = data->iobase, | 29 | .start = data->iobase, |
30 | .end = data->iobase + SZ_16K, | 30 | .end = data->iobase + SZ_16K - 1, |
31 | .flags = IORESOURCE_MEM, | 31 | .flags = IORESOURCE_MEM, |
32 | }, { | 32 | }, { |
33 | .start = data->irq, | 33 | .start = data->irq, |
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 57d59855f9ec..7a107246fd98 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) | |||
175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) | 175 | static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) |
176 | { | 176 | { |
177 | u32 irq_stat; | 177 | u32 irq_stat; |
178 | struct mxc_gpio_port *port = get_irq_data(irq); | 178 | struct mxc_gpio_port *port = irq_get_handler_data(irq); |
179 | 179 | ||
180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & | 180 | irq_stat = __raw_readl(port->base + GPIO_ISR) & |
181 | __raw_readl(port->base + GPIO_IMR); | 181 | __raw_readl(port->base + GPIO_IMR); |
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |||
188 | { | 188 | { |
189 | int i; | 189 | int i; |
190 | u32 irq_msk, irq_stat; | 190 | u32 irq_msk, irq_stat; |
191 | struct mxc_gpio_port *port = get_irq_data(irq); | 191 | struct mxc_gpio_port *port = irq_get_handler_data(irq); |
192 | 192 | ||
193 | /* walk through all interrupt status registers */ | 193 | /* walk through all interrupt status registers */ |
194 | for (i = 0; i < gpio_table_size; i++) { | 194 | for (i = 0; i < gpio_table_size; i++) { |
@@ -311,8 +311,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
311 | __raw_writel(~0, port[i].base + GPIO_ISR); | 311 | __raw_writel(~0, port[i].base + GPIO_ISR); |
312 | for (j = port[i].virtual_irq_start; | 312 | for (j = port[i].virtual_irq_start; |
313 | j < port[i].virtual_irq_start + 32; j++) { | 313 | j < port[i].virtual_irq_start + 32; j++) { |
314 | set_irq_chip(j, &gpio_irq_chip); | 314 | irq_set_chip_and_handler(j, &gpio_irq_chip, |
315 | set_irq_handler(j, handle_level_irq); | 315 | handle_level_irq); |
316 | set_irq_flags(j, IRQF_VALID); | 316 | set_irq_flags(j, IRQF_VALID); |
317 | } | 317 | } |
318 | 318 | ||
@@ -331,21 +331,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
331 | 331 | ||
332 | if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { | 332 | if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { |
333 | /* setup one handler for each entry */ | 333 | /* setup one handler for each entry */ |
334 | set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); | 334 | irq_set_chained_handler(port[i].irq, |
335 | set_irq_data(port[i].irq, &port[i]); | 335 | mx3_gpio_irq_handler); |
336 | irq_set_handler_data(port[i].irq, &port[i]); | ||
336 | if (port[i].irq_high) { | 337 | if (port[i].irq_high) { |
337 | /* setup handler for GPIO 16 to 31 */ | 338 | /* setup handler for GPIO 16 to 31 */ |
338 | set_irq_chained_handler(port[i].irq_high, | 339 | irq_set_chained_handler(port[i].irq_high, |
339 | mx3_gpio_irq_handler); | 340 | mx3_gpio_irq_handler); |
340 | set_irq_data(port[i].irq_high, &port[i]); | 341 | irq_set_handler_data(port[i].irq_high, |
342 | &port[i]); | ||
341 | } | 343 | } |
342 | } | 344 | } |
343 | } | 345 | } |
344 | 346 | ||
345 | if (cpu_is_mx2()) { | 347 | if (cpu_is_mx2()) { |
346 | /* setup one handler for all GPIO interrupts */ | 348 | /* setup one handler for all GPIO interrupts */ |
347 | set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler); | 349 | irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler); |
348 | set_irq_data(port[0].irq, port); | 350 | irq_set_handler_data(port[0].irq, port); |
349 | } | 351 | } |
350 | 352 | ||
351 | return 0; | 353 | return 0; |
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h index 5cd6466964af..6fda788ed0e9 100644 --- a/arch/arm/plat-mxc/include/mach/audmux.h +++ b/arch/arm/plat-mxc/include/mach/audmux.h | |||
@@ -15,6 +15,14 @@ | |||
15 | #define MX31_AUDMUX_PORT5_SSI_PINS_5 4 | 15 | #define MX31_AUDMUX_PORT5_SSI_PINS_5 4 |
16 | #define MX31_AUDMUX_PORT6_SSI_PINS_6 5 | 16 | #define MX31_AUDMUX_PORT6_SSI_PINS_6 5 |
17 | 17 | ||
18 | #define MX51_AUDMUX_PORT1_SSI0 0 | ||
19 | #define MX51_AUDMUX_PORT2_SSI1 1 | ||
20 | #define MX51_AUDMUX_PORT3 2 | ||
21 | #define MX51_AUDMUX_PORT4 3 | ||
22 | #define MX51_AUDMUX_PORT5 4 | ||
23 | #define MX51_AUDMUX_PORT6 5 | ||
24 | #define MX51_AUDMUX_PORT7 6 | ||
25 | |||
18 | /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ | 26 | /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ |
19 | #define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) | 27 | #define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) |
20 | #define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) | 28 | #define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) |
@@ -28,7 +36,7 @@ | |||
28 | #define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) | 36 | #define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) |
29 | #define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) | 37 | #define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) |
30 | 38 | ||
31 | /* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */ | 39 | /* Register definitions for the i.MX25/31/35/51 Digital Audio Multiplexer */ |
32 | #define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) | 40 | #define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) |
33 | #define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) | 41 | #define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) |
34 | #define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) | 42 | #define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h index c4f116d214f2..7a9b20abda09 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h | |||
@@ -90,12 +90,12 @@ | |||
90 | #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) | 90 | #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) |
91 | #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) | 91 | #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) |
92 | #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) | 92 | #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) |
93 | #define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) | 93 | #define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) |
94 | #define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) | 94 | #define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) |
95 | #define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) | 95 | #define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) |
96 | #define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) | 96 | #define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) |
97 | #define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) | 97 | #define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) |
98 | #define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) | 98 | #define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) |
99 | #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) | 99 | #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) |
100 | #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) | 100 | #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) |
101 | #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) | 101 | #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) |
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h index aaec2a6e7b3a..5f2da75a47f4 100644 --- a/arch/arm/plat-mxc/include/mach/mx50.h +++ b/arch/arm/plat-mxc/include/mach/mx50.h | |||
@@ -282,4 +282,8 @@ | |||
282 | #define MX50_INT_APBHDMA_CHAN6 116 | 282 | #define MX50_INT_APBHDMA_CHAN6 116 |
283 | #define MX50_INT_APBHDMA_CHAN7 117 | 283 | #define MX50_INT_APBHDMA_CHAN7 117 |
284 | 284 | ||
285 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | ||
286 | extern int mx50_revision(void); | ||
287 | #endif | ||
288 | |||
285 | #endif /* ifndef __MACH_MX50_H__ */ | 289 | #endif /* ifndef __MACH_MX50_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 1eb339e6c857..dede19a766ff 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
@@ -347,6 +347,7 @@ | |||
347 | 347 | ||
348 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 348 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
349 | extern int mx51_revision(void); | 349 | extern int mx51_revision(void); |
350 | extern void mx51_display_revision(void); | ||
350 | #endif | 351 | #endif |
351 | 352 | ||
352 | /* tape-out 1 defines */ | 353 | /* tape-out 1 defines */ |
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 7e072637eefa..1aea818d9d31 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h | |||
@@ -51,6 +51,20 @@ | |||
51 | #define IMX_CHIP_REVISION_3_3 0x33 | 51 | #define IMX_CHIP_REVISION_3_3 0x33 |
52 | #define IMX_CHIP_REVISION_UNKNOWN 0xff | 52 | #define IMX_CHIP_REVISION_UNKNOWN 0xff |
53 | 53 | ||
54 | #define IMX_CHIP_REVISION_1_0_STRING "1.0" | ||
55 | #define IMX_CHIP_REVISION_1_1_STRING "1.1" | ||
56 | #define IMX_CHIP_REVISION_1_2_STRING "1.2" | ||
57 | #define IMX_CHIP_REVISION_1_3_STRING "1.3" | ||
58 | #define IMX_CHIP_REVISION_2_0_STRING "2.0" | ||
59 | #define IMX_CHIP_REVISION_2_1_STRING "2.1" | ||
60 | #define IMX_CHIP_REVISION_2_2_STRING "2.2" | ||
61 | #define IMX_CHIP_REVISION_2_3_STRING "2.3" | ||
62 | #define IMX_CHIP_REVISION_3_0_STRING "3.0" | ||
63 | #define IMX_CHIP_REVISION_3_1_STRING "3.1" | ||
64 | #define IMX_CHIP_REVISION_3_2_STRING "3.2" | ||
65 | #define IMX_CHIP_REVISION_3_3_STRING "3.3" | ||
66 | #define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown" | ||
67 | |||
54 | #ifndef __ASSEMBLY__ | 68 | #ifndef __ASSEMBLY__ |
55 | extern unsigned int __mxc_cpu_type; | 69 | extern unsigned int __mxc_cpu_type; |
56 | #endif | 70 | #endif |
@@ -181,6 +195,15 @@ struct cpu_op { | |||
181 | u32 cpu_rate; | 195 | u32 cpu_rate; |
182 | }; | 196 | }; |
183 | 197 | ||
198 | int tzic_enable_wake(int is_idle); | ||
199 | enum mxc_cpu_pwr_mode { | ||
200 | WAIT_CLOCKED, /* wfi only */ | ||
201 | WAIT_UNCLOCKED, /* WAIT */ | ||
202 | WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */ | ||
203 | STOP_POWER_ON, /* just STOP */ | ||
204 | STOP_POWER_OFF, /* STOP + SRPG */ | ||
205 | }; | ||
206 | |||
184 | extern struct cpu_op *(*get_cpu_op)(int *op); | 207 | extern struct cpu_op *(*get_cpu_op)(int *op); |
185 | #endif | 208 | #endif |
186 | 209 | ||
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 95be51bfe9a9..0417da9f710d 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h | |||
@@ -20,6 +20,8 @@ | |||
20 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
21 | #include <mach/common.h> | 21 | #include <mach/common.h> |
22 | 22 | ||
23 | extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); | ||
24 | |||
23 | static inline void arch_idle(void) | 25 | static inline void arch_idle(void) |
24 | { | 26 | { |
25 | #ifdef CONFIG_ARCH_MXC91231 | 27 | #ifdef CONFIG_ARCH_MXC91231 |
@@ -54,7 +56,9 @@ static inline void arch_idle(void) | |||
54 | "orr %0, %0, #0x00000004\n" | 56 | "orr %0, %0, #0x00000004\n" |
55 | "mcr p15, 0, %0, c1, c0, 0\n" | 57 | "mcr p15, 0, %0, c1, c0, 0\n" |
56 | : "=r" (reg)); | 58 | : "=r" (reg)); |
57 | } else | 59 | } else if (cpu_is_mx51()) |
60 | mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); | ||
61 | else | ||
58 | cpu_do_idle(); | 62 | cpu_do_idle(); |
59 | } | 63 | } |
60 | 64 | ||
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c index 0c799ac27730..e1c6eff7258a 100644 --- a/arch/arm/plat-mxc/irq-common.c +++ b/arch/arm/plat-mxc/irq-common.c | |||
@@ -29,7 +29,7 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio) | |||
29 | 29 | ||
30 | ret = -ENOSYS; | 30 | ret = -ENOSYS; |
31 | 31 | ||
32 | base = get_irq_chip(irq); | 32 | base = irq_get_chip(irq); |
33 | if (base) { | 33 | if (base) { |
34 | chip = container_of(base, struct mxc_irq_chip, base); | 34 | chip = container_of(base, struct mxc_irq_chip, base); |
35 | if (chip->set_priority) | 35 | if (chip->set_priority) |
@@ -48,7 +48,7 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type) | |||
48 | 48 | ||
49 | ret = -ENOSYS; | 49 | ret = -ENOSYS; |
50 | 50 | ||
51 | base = get_irq_chip(irq); | 51 | base = irq_get_chip(irq); |
52 | if (base) { | 52 | if (base) { |
53 | chip = container_of(base, struct mxc_irq_chip, base); | 53 | chip = container_of(base, struct mxc_irq_chip, base); |
54 | if (chip->set_irq_fiq) | 54 | if (chip->set_irq_fiq) |
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 9f0c2610595e..2237ff8b434f 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <linux/clk.h> | 27 | #include <linux/clk.h> |
28 | 28 | ||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <asm/sched_clock.h> | ||
30 | #include <asm/mach/time.h> | 31 | #include <asm/mach/time.h> |
31 | #include <mach/common.h> | 32 | #include <mach/common.h> |
32 | 33 | ||
@@ -105,6 +106,11 @@ static void gpt_irq_acknowledge(void) | |||
105 | __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); | 106 | __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); |
106 | } | 107 | } |
107 | 108 | ||
109 | static cycle_t dummy_get_cycles(struct clocksource *cs) | ||
110 | { | ||
111 | return 0; | ||
112 | } | ||
113 | |||
108 | static cycle_t mx1_2_get_cycles(struct clocksource *cs) | 114 | static cycle_t mx1_2_get_cycles(struct clocksource *cs) |
109 | { | 115 | { |
110 | return __raw_readl(timer_base + MX1_2_TCN); | 116 | return __raw_readl(timer_base + MX1_2_TCN); |
@@ -118,18 +124,35 @@ static cycle_t v2_get_cycles(struct clocksource *cs) | |||
118 | static struct clocksource clocksource_mxc = { | 124 | static struct clocksource clocksource_mxc = { |
119 | .name = "mxc_timer1", | 125 | .name = "mxc_timer1", |
120 | .rating = 200, | 126 | .rating = 200, |
121 | .read = mx1_2_get_cycles, | 127 | .read = dummy_get_cycles, |
122 | .mask = CLOCKSOURCE_MASK(32), | 128 | .mask = CLOCKSOURCE_MASK(32), |
123 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 129 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
124 | }; | 130 | }; |
125 | 131 | ||
132 | static DEFINE_CLOCK_DATA(cd); | ||
133 | unsigned long long notrace sched_clock(void) | ||
134 | { | ||
135 | cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); | ||
136 | |||
137 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); | ||
138 | } | ||
139 | |||
140 | static void notrace mxc_update_sched_clock(void) | ||
141 | { | ||
142 | cycle_t cyc = clocksource_mxc.read(&clocksource_mxc); | ||
143 | update_sched_clock(&cd, cyc, (u32)~0); | ||
144 | } | ||
145 | |||
126 | static int __init mxc_clocksource_init(struct clk *timer_clk) | 146 | static int __init mxc_clocksource_init(struct clk *timer_clk) |
127 | { | 147 | { |
128 | unsigned int c = clk_get_rate(timer_clk); | 148 | unsigned int c = clk_get_rate(timer_clk); |
129 | 149 | ||
130 | if (timer_is_v2()) | 150 | if (timer_is_v2()) |
131 | clocksource_mxc.read = v2_get_cycles; | 151 | clocksource_mxc.read = v2_get_cycles; |
152 | else | ||
153 | clocksource_mxc.read = mx1_2_get_cycles; | ||
132 | 154 | ||
155 | init_sched_clock(&cd, mxc_update_sched_clock, 32, c); | ||
133 | clocksource_register_hz(&clocksource_mxc, c); | 156 | clocksource_register_hz(&clocksource_mxc, c); |
134 | 157 | ||
135 | return 0; | 158 | return 0; |
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index bc3a6be8a27f..57f9395f87ce 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
@@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
167 | /* all IRQ no FIQ Warning :: No selection */ | 167 | /* all IRQ no FIQ Warning :: No selection */ |
168 | 168 | ||
169 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | 169 | for (i = 0; i < MXC_INTERNAL_IRQS; i++) { |
170 | set_irq_chip(i, &mxc_tzic_chip.base); | 170 | irq_set_chip_and_handler(i, &mxc_tzic_chip.base, |
171 | set_irq_handler(i, handle_level_irq); | 171 | handle_level_irq); |
172 | set_irq_flags(i, IRQF_VALID); | 172 | set_irq_flags(i, IRQF_VALID); |
173 | } | 173 | } |
174 | 174 | ||
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c index 80643bc38e10..f49748eca1a3 100644 --- a/arch/arm/plat-nomadik/gpio.c +++ b/arch/arm/plat-nomadik/gpio.c | |||
@@ -54,6 +54,7 @@ struct nmk_gpio_chip { | |||
54 | u32 rwimsc; | 54 | u32 rwimsc; |
55 | u32 fwimsc; | 55 | u32 fwimsc; |
56 | u32 slpm; | 56 | u32 slpm; |
57 | u32 enabled; | ||
57 | }; | 58 | }; |
58 | 59 | ||
59 | static struct nmk_gpio_chip * | 60 | static struct nmk_gpio_chip * |
@@ -318,7 +319,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |||
318 | struct nmk_gpio_chip *nmk_chip; | 319 | struct nmk_gpio_chip *nmk_chip; |
319 | int pin = PIN_NUM(cfgs[i]); | 320 | int pin = PIN_NUM(cfgs[i]); |
320 | 321 | ||
321 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); | 322 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); |
322 | if (!nmk_chip) { | 323 | if (!nmk_chip) { |
323 | ret = -EINVAL; | 324 | ret = -EINVAL; |
324 | break; | 325 | break; |
@@ -397,7 +398,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |||
397 | struct nmk_gpio_chip *nmk_chip; | 398 | struct nmk_gpio_chip *nmk_chip; |
398 | unsigned long flags; | 399 | unsigned long flags; |
399 | 400 | ||
400 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 401 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
401 | if (!nmk_chip) | 402 | if (!nmk_chip) |
402 | return -EINVAL; | 403 | return -EINVAL; |
403 | 404 | ||
@@ -430,7 +431,7 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |||
430 | struct nmk_gpio_chip *nmk_chip; | 431 | struct nmk_gpio_chip *nmk_chip; |
431 | unsigned long flags; | 432 | unsigned long flags; |
432 | 433 | ||
433 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 434 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
434 | if (!nmk_chip) | 435 | if (!nmk_chip) |
435 | return -EINVAL; | 436 | return -EINVAL; |
436 | 437 | ||
@@ -456,7 +457,7 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode) | |||
456 | struct nmk_gpio_chip *nmk_chip; | 457 | struct nmk_gpio_chip *nmk_chip; |
457 | unsigned long flags; | 458 | unsigned long flags; |
458 | 459 | ||
459 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 460 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
460 | if (!nmk_chip) | 461 | if (!nmk_chip) |
461 | return -EINVAL; | 462 | return -EINVAL; |
462 | 463 | ||
@@ -473,7 +474,7 @@ int nmk_gpio_get_mode(int gpio) | |||
473 | struct nmk_gpio_chip *nmk_chip; | 474 | struct nmk_gpio_chip *nmk_chip; |
474 | u32 afunc, bfunc, bit; | 475 | u32 afunc, bfunc, bit; |
475 | 476 | ||
476 | nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 477 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
477 | if (!nmk_chip) | 478 | if (!nmk_chip) |
478 | return -EINVAL; | 479 | return -EINVAL; |
479 | 480 | ||
@@ -541,13 +542,6 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, | |||
541 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, | 542 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
542 | int gpio, bool on) | 543 | int gpio, bool on) |
543 | { | 544 | { |
544 | #ifdef CONFIG_ARCH_U8500 | ||
545 | if (cpu_is_u8500v2()) { | ||
546 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, | ||
547 | on ? NMK_GPIO_SLPM_WAKEUP_ENABLE | ||
548 | : NMK_GPIO_SLPM_WAKEUP_DISABLE); | ||
549 | } | ||
550 | #endif | ||
551 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); | 545 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
552 | } | 546 | } |
553 | 547 | ||
@@ -564,6 +558,11 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |||
564 | if (!nmk_chip) | 558 | if (!nmk_chip) |
565 | return -EINVAL; | 559 | return -EINVAL; |
566 | 560 | ||
561 | if (enable) | ||
562 | nmk_chip->enabled |= bitmask; | ||
563 | else | ||
564 | nmk_chip->enabled &= ~bitmask; | ||
565 | |||
567 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | 566 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
568 | spin_lock(&nmk_chip->lock); | 567 | spin_lock(&nmk_chip->lock); |
569 | 568 | ||
@@ -590,8 +589,6 @@ static void nmk_gpio_irq_unmask(struct irq_data *d) | |||
590 | 589 | ||
591 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | 590 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
592 | { | 591 | { |
593 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
594 | bool enabled = !(desc->status & IRQ_DISABLED); | ||
595 | struct nmk_gpio_chip *nmk_chip; | 592 | struct nmk_gpio_chip *nmk_chip; |
596 | unsigned long flags; | 593 | unsigned long flags; |
597 | u32 bitmask; | 594 | u32 bitmask; |
@@ -606,7 +603,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |||
606 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | 603 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
607 | spin_lock(&nmk_chip->lock); | 604 | spin_lock(&nmk_chip->lock); |
608 | 605 | ||
609 | if (!enabled) | 606 | if (!(nmk_chip->enabled & bitmask)) |
610 | __nmk_gpio_set_wake(nmk_chip, gpio, on); | 607 | __nmk_gpio_set_wake(nmk_chip, gpio, on); |
611 | 608 | ||
612 | if (on) | 609 | if (on) |
@@ -622,9 +619,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |||
622 | 619 | ||
623 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) | 620 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
624 | { | 621 | { |
625 | struct irq_desc *desc = irq_to_desc(d->irq); | 622 | bool enabled, wake = irqd_is_wakeup_set(d); |
626 | bool enabled = !(desc->status & IRQ_DISABLED); | ||
627 | bool wake = desc->wake_depth; | ||
628 | int gpio; | 623 | int gpio; |
629 | struct nmk_gpio_chip *nmk_chip; | 624 | struct nmk_gpio_chip *nmk_chip; |
630 | unsigned long flags; | 625 | unsigned long flags; |
@@ -641,6 +636,8 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
641 | if (type & IRQ_TYPE_LEVEL_LOW) | 636 | if (type & IRQ_TYPE_LEVEL_LOW) |
642 | return -EINVAL; | 637 | return -EINVAL; |
643 | 638 | ||
639 | enabled = nmk_chip->enabled & bitmask; | ||
640 | |||
644 | spin_lock_irqsave(&nmk_chip->lock, flags); | 641 | spin_lock_irqsave(&nmk_chip->lock, flags); |
645 | 642 | ||
646 | if (enabled) | 643 | if (enabled) |
@@ -681,7 +678,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
681 | u32 status) | 678 | u32 status) |
682 | { | 679 | { |
683 | struct nmk_gpio_chip *nmk_chip; | 680 | struct nmk_gpio_chip *nmk_chip; |
684 | struct irq_chip *host_chip = get_irq_chip(irq); | 681 | struct irq_chip *host_chip = irq_get_chip(irq); |
685 | unsigned int first_irq; | 682 | unsigned int first_irq; |
686 | 683 | ||
687 | if (host_chip->irq_mask_ack) | 684 | if (host_chip->irq_mask_ack) |
@@ -692,7 +689,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
692 | host_chip->irq_ack(&desc->irq_data); | 689 | host_chip->irq_ack(&desc->irq_data); |
693 | } | 690 | } |
694 | 691 | ||
695 | nmk_chip = get_irq_data(irq); | 692 | nmk_chip = irq_get_handler_data(irq); |
696 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | 693 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
697 | while (status) { | 694 | while (status) { |
698 | int bit = __ffs(status); | 695 | int bit = __ffs(status); |
@@ -706,7 +703,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
706 | 703 | ||
707 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | 704 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
708 | { | 705 | { |
709 | struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); | 706 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
710 | u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); | 707 | u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); |
711 | 708 | ||
712 | __nmk_gpio_irq_handler(irq, desc, status); | 709 | __nmk_gpio_irq_handler(irq, desc, status); |
@@ -715,7 +712,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
715 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | 712 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, |
716 | struct irq_desc *desc) | 713 | struct irq_desc *desc) |
717 | { | 714 | { |
718 | struct nmk_gpio_chip *nmk_chip = get_irq_data(irq); | 715 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
719 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); | 716 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
720 | 717 | ||
721 | __nmk_gpio_irq_handler(irq, desc, status); | 718 | __nmk_gpio_irq_handler(irq, desc, status); |
@@ -728,20 +725,20 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) | |||
728 | 725 | ||
729 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | 726 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
730 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { | 727 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
731 | set_irq_chip(i, &nmk_gpio_irq_chip); | 728 | irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, |
732 | set_irq_handler(i, handle_edge_irq); | 729 | handle_edge_irq); |
733 | set_irq_flags(i, IRQF_VALID); | 730 | set_irq_flags(i, IRQF_VALID); |
734 | set_irq_chip_data(i, nmk_chip); | 731 | irq_set_chip_data(i, nmk_chip); |
735 | set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | 732 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); |
736 | } | 733 | } |
737 | 734 | ||
738 | set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); | 735 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
739 | set_irq_data(nmk_chip->parent_irq, nmk_chip); | 736 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); |
740 | 737 | ||
741 | if (nmk_chip->secondary_parent_irq >= 0) { | 738 | if (nmk_chip->secondary_parent_irq >= 0) { |
742 | set_irq_chained_handler(nmk_chip->secondary_parent_irq, | 739 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
743 | nmk_gpio_secondary_irq_handler); | 740 | nmk_gpio_secondary_irq_handler); |
744 | set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip); | 741 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
745 | } | 742 | } |
746 | 743 | ||
747 | return 0; | 744 | return 0; |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 971d18636942..d2adcdda23cf 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
@@ -755,18 +755,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type) | |||
755 | bank = irq_data_get_irq_chip_data(d); | 755 | bank = irq_data_get_irq_chip_data(d); |
756 | spin_lock_irqsave(&bank->lock, flags); | 756 | spin_lock_irqsave(&bank->lock, flags); |
757 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); | 757 | retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type); |
758 | if (retval == 0) { | ||
759 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
760 | |||
761 | desc->status &= ~IRQ_TYPE_SENSE_MASK; | ||
762 | desc->status |= type; | ||
763 | } | ||
764 | spin_unlock_irqrestore(&bank->lock, flags); | 758 | spin_unlock_irqrestore(&bank->lock, flags); |
765 | 759 | ||
766 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | 760 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
767 | __set_irq_handler_unlocked(d->irq, handle_level_irq); | 761 | __irq_set_handler_locked(d->irq, handle_level_irq); |
768 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 762 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
769 | __set_irq_handler_unlocked(d->irq, handle_edge_irq); | 763 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
770 | 764 | ||
771 | return retval; | 765 | return retval; |
772 | } | 766 | } |
@@ -1146,7 +1140,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
1146 | 1140 | ||
1147 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 1141 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
1148 | 1142 | ||
1149 | bank = get_irq_data(irq); | 1143 | bank = irq_get_handler_data(irq); |
1150 | #ifdef CONFIG_ARCH_OMAP1 | 1144 | #ifdef CONFIG_ARCH_OMAP1 |
1151 | if (bank->method == METHOD_MPUIO) | 1145 | if (bank->method == METHOD_MPUIO) |
1152 | isr_reg = bank->base + | 1146 | isr_reg = bank->base + |
@@ -1270,8 +1264,7 @@ static void gpio_unmask_irq(struct irq_data *d) | |||
1270 | unsigned int gpio = d->irq - IH_GPIO_BASE; | 1264 | unsigned int gpio = d->irq - IH_GPIO_BASE; |
1271 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | 1265 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); |
1272 | unsigned int irq_mask = 1 << get_gpio_index(gpio); | 1266 | unsigned int irq_mask = 1 << get_gpio_index(gpio); |
1273 | struct irq_desc *desc = irq_to_desc(d->irq); | 1267 | u32 trigger = irqd_get_trigger_type(d); |
1274 | u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK; | ||
1275 | 1268 | ||
1276 | if (trigger) | 1269 | if (trigger) |
1277 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); | 1270 | _set_gpio_triggering(bank, get_gpio_index(gpio), trigger); |
@@ -1672,19 +1665,17 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank) | |||
1672 | 1665 | ||
1673 | for (j = bank->virtual_irq_start; | 1666 | for (j = bank->virtual_irq_start; |
1674 | j < bank->virtual_irq_start + bank_width; j++) { | 1667 | j < bank->virtual_irq_start + bank_width; j++) { |
1675 | struct irq_desc *d = irq_to_desc(j); | 1668 | irq_set_lockdep_class(j, &gpio_lock_class); |
1676 | 1669 | irq_set_chip_data(j, bank); | |
1677 | lockdep_set_class(&d->lock, &gpio_lock_class); | ||
1678 | set_irq_chip_data(j, bank); | ||
1679 | if (bank_is_mpuio(bank)) | 1670 | if (bank_is_mpuio(bank)) |
1680 | set_irq_chip(j, &mpuio_irq_chip); | 1671 | irq_set_chip(j, &mpuio_irq_chip); |
1681 | else | 1672 | else |
1682 | set_irq_chip(j, &gpio_irq_chip); | 1673 | irq_set_chip(j, &gpio_irq_chip); |
1683 | set_irq_handler(j, handle_simple_irq); | 1674 | irq_set_handler(j, handle_simple_irq); |
1684 | set_irq_flags(j, IRQF_VALID); | 1675 | set_irq_flags(j, IRQF_VALID); |
1685 | } | 1676 | } |
1686 | set_irq_chained_handler(bank->irq, gpio_irq_handler); | 1677 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1687 | set_irq_data(bank->irq, bank); | 1678 | irq_set_handler_data(bank->irq, bank); |
1688 | } | 1679 | } |
1689 | 1680 | ||
1690 | static int __devinit omap_gpio_probe(struct platform_device *pdev) | 1681 | static int __devinit omap_gpio_probe(struct platform_device *pdev) |
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 078894bc3b9a..a431a138f402 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c | |||
@@ -324,9 +324,8 @@ EXPORT_SYMBOL(orion_gpio_set_blink); | |||
324 | static void gpio_irq_ack(struct irq_data *d) | 324 | static void gpio_irq_ack(struct irq_data *d) |
325 | { | 325 | { |
326 | struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); | 326 | struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); |
327 | int type; | 327 | int type = irqd_get_trigger_type(d); |
328 | 328 | ||
329 | type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; | ||
330 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | 329 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
331 | int pin = d->irq - ochip->secondary_irq_base; | 330 | int pin = d->irq - ochip->secondary_irq_base; |
332 | 331 | ||
@@ -337,11 +336,10 @@ static void gpio_irq_ack(struct irq_data *d) | |||
337 | static void gpio_irq_mask(struct irq_data *d) | 336 | static void gpio_irq_mask(struct irq_data *d) |
338 | { | 337 | { |
339 | struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); | 338 | struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); |
340 | int type; | 339 | int type = irqd_get_trigger_type(d); |
341 | void __iomem *reg; | 340 | void __iomem *reg; |
342 | int pin; | 341 | int pin; |
343 | 342 | ||
344 | type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; | ||
345 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | 343 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
346 | reg = GPIO_EDGE_MASK(ochip); | 344 | reg = GPIO_EDGE_MASK(ochip); |
347 | else | 345 | else |
@@ -355,11 +353,10 @@ static void gpio_irq_mask(struct irq_data *d) | |||
355 | static void gpio_irq_unmask(struct irq_data *d) | 353 | static void gpio_irq_unmask(struct irq_data *d) |
356 | { | 354 | { |
357 | struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); | 355 | struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); |
358 | int type; | 356 | int type = irqd_get_trigger_type(d); |
359 | void __iomem *reg; | 357 | void __iomem *reg; |
360 | int pin; | 358 | int pin; |
361 | 359 | ||
362 | type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK; | ||
363 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) | 360 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
364 | reg = GPIO_EDGE_MASK(ochip); | 361 | reg = GPIO_EDGE_MASK(ochip); |
365 | else | 362 | else |
@@ -389,9 +386,9 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type) | |||
389 | * Set edge/level type. | 386 | * Set edge/level type. |
390 | */ | 387 | */ |
391 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { | 388 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
392 | set_irq_handler(d->irq, handle_edge_irq); | 389 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
393 | } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | 390 | } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
394 | set_irq_handler(d->irq, handle_level_irq); | 391 | __irq_set_handler_locked(d->irq, handle_level_irq); |
395 | } else { | 392 | } else { |
396 | printk(KERN_ERR "failed to set irq=%d (type=%d)\n", | 393 | printk(KERN_ERR "failed to set irq=%d (type=%d)\n", |
397 | d->irq, type); | 394 | d->irq, type); |
@@ -477,10 +474,10 @@ void __init orion_gpio_init(int gpio_base, int ngpio, | |||
477 | for (i = 0; i < ngpio; i++) { | 474 | for (i = 0; i < ngpio; i++) { |
478 | unsigned int irq = secondary_irq_base + i; | 475 | unsigned int irq = secondary_irq_base + i; |
479 | 476 | ||
480 | set_irq_chip(irq, &orion_gpio_irq_chip); | 477 | irq_set_chip_and_handler(irq, &orion_gpio_irq_chip, |
481 | set_irq_handler(irq, handle_level_irq); | 478 | handle_level_irq); |
482 | set_irq_chip_data(irq, ochip); | 479 | irq_set_chip_data(irq, ochip); |
483 | irq_desc[irq].status |= IRQ_LEVEL; | 480 | irq_set_status_flags(irq, IRQ_LEVEL); |
484 | set_irq_flags(irq, IRQF_VALID); | 481 | set_irq_flags(irq, IRQF_VALID); |
485 | } | 482 | } |
486 | } | 483 | } |
@@ -488,7 +485,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio, | |||
488 | void orion_gpio_irq_handler(int pinoff) | 485 | void orion_gpio_irq_handler(int pinoff) |
489 | { | 486 | { |
490 | struct orion_gpio_chip *ochip; | 487 | struct orion_gpio_chip *ochip; |
491 | u32 cause; | 488 | u32 cause, type; |
492 | int i; | 489 | int i; |
493 | 490 | ||
494 | ochip = orion_gpio_chip_find(pinoff); | 491 | ochip = orion_gpio_chip_find(pinoff); |
@@ -500,15 +497,14 @@ void orion_gpio_irq_handler(int pinoff) | |||
500 | 497 | ||
501 | for (i = 0; i < ochip->chip.ngpio; i++) { | 498 | for (i = 0; i < ochip->chip.ngpio; i++) { |
502 | int irq; | 499 | int irq; |
503 | struct irq_desc *desc; | ||
504 | 500 | ||
505 | irq = ochip->secondary_irq_base + i; | 501 | irq = ochip->secondary_irq_base + i; |
506 | 502 | ||
507 | if (!(cause & (1 << i))) | 503 | if (!(cause & (1 << i))) |
508 | continue; | 504 | continue; |
509 | 505 | ||
510 | desc = irq_desc + irq; | 506 | type = irqd_get_trigger_type(irq_get_irq_data(irq)); |
511 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | 507 | if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
512 | /* Swap polarity (race with GPIO line) */ | 508 | /* Swap polarity (race with GPIO line) */ |
513 | u32 polarity; | 509 | u32 polarity; |
514 | 510 | ||
@@ -516,7 +512,6 @@ void orion_gpio_irq_handler(int pinoff) | |||
516 | polarity ^= 1 << i; | 512 | polarity ^= 1 << i; |
517 | writel(polarity, GPIO_IN_POL(ochip)); | 513 | writel(polarity, GPIO_IN_POL(ochip)); |
518 | } | 514 | } |
519 | 515 | generic_handle_irq(irq); | |
520 | desc_handle_irq(irq, desc); | ||
521 | } | 516 | } |
522 | } | 517 | } |
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index 7d0c7eb59f09..d8d638e09f8f 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c | |||
@@ -56,10 +56,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) | |||
56 | for (i = 0; i < 32; i++) { | 56 | for (i = 0; i < 32; i++) { |
57 | unsigned int irq = irq_start + i; | 57 | unsigned int irq = irq_start + i; |
58 | 58 | ||
59 | set_irq_chip(irq, &orion_irq_chip); | 59 | irq_set_chip_and_handler(irq, &orion_irq_chip, |
60 | set_irq_chip_data(irq, maskaddr); | 60 | handle_level_irq); |
61 | set_irq_handler(irq, handle_level_irq); | 61 | irq_set_chip_data(irq, maskaddr); |
62 | irq_desc[irq].status |= IRQ_LEVEL; | 62 | irq_set_status_flags(irq, IRQ_LEVEL); |
63 | set_irq_flags(irq, IRQF_VALID); | 63 | set_irq_flags(irq, IRQF_VALID); |
64 | } | 64 | } |
65 | } | 65 | } |
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c index e7de6ae2a1e8..dce088f45678 100644 --- a/arch/arm/plat-pxa/gpio.c +++ b/arch/arm/plat-pxa/gpio.c | |||
@@ -284,13 +284,13 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) | |||
284 | } | 284 | } |
285 | 285 | ||
286 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { | 286 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { |
287 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | 287 | irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, |
288 | set_irq_handler(irq, handle_edge_irq); | 288 | handle_edge_irq); |
289 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 289 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
290 | } | 290 | } |
291 | 291 | ||
292 | /* Install handler for GPIO>=2 edge detect interrupts */ | 292 | /* Install handler for GPIO>=2 edge detect interrupts */ |
293 | set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); | 293 | irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler); |
294 | pxa_muxed_gpio_chip.irq_set_wake = fn; | 294 | pxa_muxed_gpio_chip.irq_set_wake = fn; |
295 | } | 295 | } |
296 | 296 | ||
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 4434cb56bd9a..9aee7e1668b1 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
@@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void) | |||
592 | case IRQ_UART1: | 592 | case IRQ_UART1: |
593 | case IRQ_UART2: | 593 | case IRQ_UART2: |
594 | case IRQ_ADCPARENT: | 594 | case IRQ_ADCPARENT: |
595 | set_irq_chip(irqno, &s3c_irq_level_chip); | 595 | irq_set_chip_and_handler(irqno, &s3c_irq_level_chip, |
596 | set_irq_handler(irqno, handle_level_irq); | 596 | handle_level_irq); |
597 | break; | 597 | break; |
598 | 598 | ||
599 | case IRQ_RESERVED6: | 599 | case IRQ_RESERVED6: |
@@ -603,35 +603,35 @@ void __init s3c24xx_init_irq(void) | |||
603 | 603 | ||
604 | default: | 604 | default: |
605 | //irqdbf("registering irq %d (s3c irq)\n", irqno); | 605 | //irqdbf("registering irq %d (s3c irq)\n", irqno); |
606 | set_irq_chip(irqno, &s3c_irq_chip); | 606 | irq_set_chip_and_handler(irqno, &s3c_irq_chip, |
607 | set_irq_handler(irqno, handle_edge_irq); | 607 | handle_edge_irq); |
608 | set_irq_flags(irqno, IRQF_VALID); | 608 | set_irq_flags(irqno, IRQF_VALID); |
609 | } | 609 | } |
610 | } | 610 | } |
611 | 611 | ||
612 | /* setup the cascade irq handlers */ | 612 | /* setup the cascade irq handlers */ |
613 | 613 | ||
614 | set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); | 614 | irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); |
615 | set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); | 615 | irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); |
616 | 616 | ||
617 | set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); | 617 | irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); |
618 | set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); | 618 | irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); |
619 | set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); | 619 | irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); |
620 | set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); | 620 | irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); |
621 | 621 | ||
622 | /* external interrupts */ | 622 | /* external interrupts */ |
623 | 623 | ||
624 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | 624 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { |
625 | irqdbf("registering irq %d (ext int)\n", irqno); | 625 | irqdbf("registering irq %d (ext int)\n", irqno); |
626 | set_irq_chip(irqno, &s3c_irq_eint0t4); | 626 | irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4, |
627 | set_irq_handler(irqno, handle_edge_irq); | 627 | handle_edge_irq); |
628 | set_irq_flags(irqno, IRQF_VALID); | 628 | set_irq_flags(irqno, IRQF_VALID); |
629 | } | 629 | } |
630 | 630 | ||
631 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { | 631 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { |
632 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); | 632 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); |
633 | set_irq_chip(irqno, &s3c_irqext_chip); | 633 | irq_set_chip_and_handler(irqno, &s3c_irqext_chip, |
634 | set_irq_handler(irqno, handle_edge_irq); | 634 | handle_edge_irq); |
635 | set_irq_flags(irqno, IRQF_VALID); | 635 | set_irq_flags(irqno, IRQF_VALID); |
636 | } | 636 | } |
637 | 637 | ||
@@ -641,29 +641,28 @@ void __init s3c24xx_init_irq(void) | |||
641 | 641 | ||
642 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { | 642 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { |
643 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); | 643 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); |
644 | set_irq_chip(irqno, &s3c_irq_uart0); | 644 | irq_set_chip_and_handler(irqno, &s3c_irq_uart0, |
645 | set_irq_handler(irqno, handle_level_irq); | 645 | handle_level_irq); |
646 | set_irq_flags(irqno, IRQF_VALID); | 646 | set_irq_flags(irqno, IRQF_VALID); |
647 | } | 647 | } |
648 | 648 | ||
649 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { | 649 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { |
650 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); | 650 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); |
651 | set_irq_chip(irqno, &s3c_irq_uart1); | 651 | irq_set_chip_and_handler(irqno, &s3c_irq_uart1, |
652 | set_irq_handler(irqno, handle_level_irq); | 652 | handle_level_irq); |
653 | set_irq_flags(irqno, IRQF_VALID); | 653 | set_irq_flags(irqno, IRQF_VALID); |
654 | } | 654 | } |
655 | 655 | ||
656 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { | 656 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { |
657 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); | 657 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); |
658 | set_irq_chip(irqno, &s3c_irq_uart2); | 658 | irq_set_chip_and_handler(irqno, &s3c_irq_uart2, |
659 | set_irq_handler(irqno, handle_level_irq); | 659 | handle_level_irq); |
660 | set_irq_flags(irqno, IRQF_VALID); | 660 | set_irq_flags(irqno, IRQF_VALID); |
661 | } | 661 | } |
662 | 662 | ||
663 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { | 663 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { |
664 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); | 664 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); |
665 | set_irq_chip(irqno, &s3c_irq_adc); | 665 | irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq); |
666 | set_irq_handler(irqno, handle_edge_irq); | ||
667 | set_irq_flags(irqno, IRQF_VALID); | 666 | set_irq_flags(irqno, IRQF_VALID); |
668 | } | 667 | } |
669 | 668 | ||
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c index 225aa25405db..b5bb774985b0 100644 --- a/arch/arm/plat-s5p/irq-eint.c +++ b/arch/arm/plat-s5p/irq-eint.c | |||
@@ -205,15 +205,14 @@ int __init s5p_init_irq_eint(void) | |||
205 | int irq; | 205 | int irq; |
206 | 206 | ||
207 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) | 207 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) |
208 | set_irq_chip(irq, &s5p_irq_vic_eint); | 208 | irq_set_chip(irq, &s5p_irq_vic_eint); |
209 | 209 | ||
210 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { | 210 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { |
211 | set_irq_chip(irq, &s5p_irq_eint); | 211 | irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq); |
212 | set_irq_handler(irq, handle_level_irq); | ||
213 | set_irq_flags(irq, IRQF_VALID); | 212 | set_irq_flags(irq, IRQF_VALID); |
214 | } | 213 | } |
215 | 214 | ||
216 | set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); | 215 | irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); |
217 | return 0; | 216 | return 0; |
218 | } | 217 | } |
219 | 218 | ||
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index cd87d3256e03..46dd078147d8 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c | |||
@@ -43,13 +43,13 @@ LIST_HEAD(banks); | |||
43 | 43 | ||
44 | static int s5p_gpioint_get_offset(struct irq_data *data) | 44 | static int s5p_gpioint_get_offset(struct irq_data *data) |
45 | { | 45 | { |
46 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 46 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
47 | return data->irq - chip->irq_base; | 47 | return data->irq - chip->irq_base; |
48 | } | 48 | } |
49 | 49 | ||
50 | static void s5p_gpioint_ack(struct irq_data *data) | 50 | static void s5p_gpioint_ack(struct irq_data *data) |
51 | { | 51 | { |
52 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 52 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
53 | int group, offset, pend_offset; | 53 | int group, offset, pend_offset; |
54 | unsigned int value; | 54 | unsigned int value; |
55 | 55 | ||
@@ -64,7 +64,7 @@ static void s5p_gpioint_ack(struct irq_data *data) | |||
64 | 64 | ||
65 | static void s5p_gpioint_mask(struct irq_data *data) | 65 | static void s5p_gpioint_mask(struct irq_data *data) |
66 | { | 66 | { |
67 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 67 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
68 | int group, offset, mask_offset; | 68 | int group, offset, mask_offset; |
69 | unsigned int value; | 69 | unsigned int value; |
70 | 70 | ||
@@ -79,7 +79,7 @@ static void s5p_gpioint_mask(struct irq_data *data) | |||
79 | 79 | ||
80 | static void s5p_gpioint_unmask(struct irq_data *data) | 80 | static void s5p_gpioint_unmask(struct irq_data *data) |
81 | { | 81 | { |
82 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 82 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
83 | int group, offset, mask_offset; | 83 | int group, offset, mask_offset; |
84 | unsigned int value; | 84 | unsigned int value; |
85 | 85 | ||
@@ -100,7 +100,7 @@ static void s5p_gpioint_mask_ack(struct irq_data *data) | |||
100 | 100 | ||
101 | static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) | 101 | static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type) |
102 | { | 102 | { |
103 | struct s3c_gpio_chip *chip = irq_data_get_irq_data(data); | 103 | struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data); |
104 | int group, offset, con_offset; | 104 | int group, offset, con_offset; |
105 | unsigned int value; | 105 | unsigned int value; |
106 | 106 | ||
@@ -149,7 +149,7 @@ static struct irq_chip s5p_gpioint = { | |||
149 | 149 | ||
150 | static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) | 150 | static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) |
151 | { | 151 | { |
152 | struct s5p_gpioint_bank *bank = get_irq_data(irq); | 152 | struct s5p_gpioint_bank *bank = irq_get_handler_data(irq); |
153 | int group, pend_offset, mask_offset; | 153 | int group, pend_offset, mask_offset; |
154 | unsigned int pend, mask; | 154 | unsigned int pend, mask; |
155 | 155 | ||
@@ -200,8 +200,8 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) | |||
200 | if (!bank->chips) | 200 | if (!bank->chips) |
201 | return -ENOMEM; | 201 | return -ENOMEM; |
202 | 202 | ||
203 | set_irq_chained_handler(bank->irq, s5p_gpioint_handler); | 203 | irq_set_chained_handler(bank->irq, s5p_gpioint_handler); |
204 | set_irq_data(bank->irq, bank); | 204 | irq_set_handler_data(bank->irq, bank); |
205 | bank->handler = s5p_gpioint_handler; | 205 | bank->handler = s5p_gpioint_handler; |
206 | printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", | 206 | printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n", |
207 | bank->irq); | 207 | bank->irq); |
@@ -219,9 +219,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) | |||
219 | bank->chips[group - bank->start] = chip; | 219 | bank->chips[group - bank->start] = chip; |
220 | for (i = 0; i < chip->chip.ngpio; i++) { | 220 | for (i = 0; i < chip->chip.ngpio; i++) { |
221 | irq = chip->irq_base + i; | 221 | irq = chip->irq_base + i; |
222 | set_irq_chip(irq, &s5p_gpioint); | 222 | irq_set_chip(irq, &s5p_gpioint); |
223 | set_irq_data(irq, chip); | 223 | irq_set_handler_data(irq, chip); |
224 | set_irq_handler(irq, handle_level_irq); | 224 | irq_set_handler(irq, handle_level_irq); |
225 | set_irq_flags(irq, IRQF_VALID); | 225 | set_irq_flags(irq, IRQF_VALID); |
226 | } | 226 | } |
227 | return 0; | 227 | return 0; |
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c index 4e770355ccbc..4d4e571af553 100644 --- a/arch/arm/plat-samsung/irq-uart.c +++ b/arch/arm/plat-samsung/irq-uart.c | |||
@@ -107,7 +107,6 @@ static struct irq_chip s3c_irq_uart = { | |||
107 | 107 | ||
108 | static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) | 108 | static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) |
109 | { | 109 | { |
110 | struct irq_desc *desc = irq_to_desc(uirq->parent_irq); | ||
111 | void __iomem *reg_base = uirq->regs; | 110 | void __iomem *reg_base = uirq->regs; |
112 | unsigned int irq; | 111 | unsigned int irq; |
113 | int offs; | 112 | int offs; |
@@ -118,14 +117,13 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) | |||
118 | for (offs = 0; offs < 3; offs++) { | 117 | for (offs = 0; offs < 3; offs++) { |
119 | irq = uirq->base_irq + offs; | 118 | irq = uirq->base_irq + offs; |
120 | 119 | ||
121 | set_irq_chip(irq, &s3c_irq_uart); | 120 | irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq); |
122 | set_irq_chip_data(irq, uirq); | 121 | irq_set_chip_data(irq, uirq); |
123 | set_irq_handler(irq, handle_level_irq); | ||
124 | set_irq_flags(irq, IRQF_VALID); | 122 | set_irq_flags(irq, IRQF_VALID); |
125 | } | 123 | } |
126 | 124 | ||
127 | desc->irq_data.handler_data = uirq; | 125 | irq_set_handler_data(uirq->parent_irq, uirq); |
128 | set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); | 126 | irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); |
129 | } | 127 | } |
130 | 128 | ||
131 | /** | 129 | /** |
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c index dd8692ae5c4c..d6ad66ab9290 100644 --- a/arch/arm/plat-samsung/irq-vic-timer.c +++ b/arch/arm/plat-samsung/irq-vic-timer.c | |||
@@ -77,14 +77,11 @@ static struct irq_chip s3c_irq_timer = { | |||
77 | void __init s3c_init_vic_timer_irq(unsigned int parent_irq, | 77 | void __init s3c_init_vic_timer_irq(unsigned int parent_irq, |
78 | unsigned int timer_irq) | 78 | unsigned int timer_irq) |
79 | { | 79 | { |
80 | struct irq_desc *desc = irq_to_desc(parent_irq); | ||
81 | 80 | ||
82 | set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); | 81 | irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer); |
82 | irq_set_handler_data(parent_irq, (void *)timer_irq); | ||
83 | 83 | ||
84 | set_irq_chip(timer_irq, &s3c_irq_timer); | 84 | irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq); |
85 | set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); | 85 | irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0))); |
86 | set_irq_handler(timer_irq, handle_level_irq); | ||
87 | set_irq_flags(timer_irq, IRQF_VALID); | 86 | set_irq_flags(timer_irq, IRQF_VALID); |
88 | |||
89 | desc->irq_data.handler_data = (void *)timer_irq; | ||
90 | } | 87 | } |
diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c index 2e09b6ad84ca..dc814037297b 100644 --- a/arch/arm/plat-samsung/wakeup-mask.c +++ b/arch/arm/plat-samsung/wakeup-mask.c | |||
@@ -22,7 +22,7 @@ | |||
22 | void samsung_sync_wakemask(void __iomem *reg, | 22 | void samsung_sync_wakemask(void __iomem *reg, |
23 | struct samsung_wakeup_mask *mask, int nr_mask) | 23 | struct samsung_wakeup_mask *mask, int nr_mask) |
24 | { | 24 | { |
25 | struct irq_desc *desc; | 25 | struct irq_data *data; |
26 | u32 val; | 26 | u32 val; |
27 | 27 | ||
28 | val = __raw_readl(reg); | 28 | val = __raw_readl(reg); |
@@ -33,10 +33,10 @@ void samsung_sync_wakemask(void __iomem *reg, | |||
33 | continue; | 33 | continue; |
34 | } | 34 | } |
35 | 35 | ||
36 | desc = irq_to_desc(mask->irq); | 36 | data = irq_get_irq_data(mask->irq); |
37 | 37 | ||
38 | /* bit of a liberty to read this directly from irq_desc. */ | 38 | /* bit of a liberty to read this directly from irq_data. */ |
39 | if (desc->wake_depth > 0) | 39 | if (irqd_is_wakeup_set(data)) |
40 | val &= ~mask->bit; | 40 | val &= ~mask->bit; |
41 | else | 41 | else |
42 | val |= mask->bit; | 42 | val |= mask->bit; |
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c index 78189035e7f1..961fb7261243 100644 --- a/arch/arm/plat-spear/shirq.c +++ b/arch/arm/plat-spear/shirq.c | |||
@@ -68,7 +68,7 @@ static struct irq_chip shirq_chip = { | |||
68 | static void shirq_handler(unsigned irq, struct irq_desc *desc) | 68 | static void shirq_handler(unsigned irq, struct irq_desc *desc) |
69 | { | 69 | { |
70 | u32 i, val, mask; | 70 | u32 i, val, mask; |
71 | struct spear_shirq *shirq = get_irq_data(irq); | 71 | struct spear_shirq *shirq = irq_get_handler_data(irq); |
72 | 72 | ||
73 | desc->irq_data.chip->irq_ack(&desc->irq_data); | 73 | desc->irq_data.chip->irq_ack(&desc->irq_data); |
74 | while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & | 74 | while ((val = readl(shirq->regs.base + shirq->regs.status_reg) & |
@@ -105,14 +105,14 @@ int spear_shirq_register(struct spear_shirq *shirq) | |||
105 | if (!shirq->dev_count) | 105 | if (!shirq->dev_count) |
106 | return -EINVAL; | 106 | return -EINVAL; |
107 | 107 | ||
108 | set_irq_chained_handler(shirq->irq, shirq_handler); | 108 | irq_set_chained_handler(shirq->irq, shirq_handler); |
109 | for (i = 0; i < shirq->dev_count; i++) { | 109 | for (i = 0; i < shirq->dev_count; i++) { |
110 | set_irq_chip(shirq->dev_config[i].virq, &shirq_chip); | 110 | irq_set_chip_and_handler(shirq->dev_config[i].virq, |
111 | set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq); | 111 | &shirq_chip, handle_simple_irq); |
112 | set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); | 112 | set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID); |
113 | set_irq_chip_data(shirq->dev_config[i].virq, shirq); | 113 | irq_set_chip_data(shirq->dev_config[i].virq, shirq); |
114 | } | 114 | } |
115 | 115 | ||
116 | set_irq_data(shirq->irq, shirq); | 116 | irq_set_handler_data(shirq->irq, shirq); |
117 | return 0; | 117 | return 0; |
118 | } | 118 | } |
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c index aaa168683d4e..6fdf9acf82ed 100644 --- a/arch/arm/plat-stmp3xxx/irq.c +++ b/arch/arm/plat-stmp3xxx/irq.c | |||
@@ -35,8 +35,7 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip) | |||
35 | /* Disable all interrupts initially */ | 35 | /* Disable all interrupts initially */ |
36 | for (i = 0; i < NR_REAL_IRQS; i++) { | 36 | for (i = 0; i < NR_REAL_IRQS; i++) { |
37 | chip->irq_mask(irq_get_irq_data(i)); | 37 | chip->irq_mask(irq_get_irq_data(i)); |
38 | set_irq_chip(i, chip); | 38 | irq_set_chip_and_handler(i, chip, handle_level_irq); |
39 | set_irq_handler(i, handle_level_irq); | ||
40 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 39 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
41 | } | 40 | } |
42 | 41 | ||
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c index 66d5bac3ace2..3def03b3217d 100644 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ b/arch/arm/plat-stmp3xxx/pinmux.c | |||
@@ -489,14 +489,13 @@ static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset) | |||
489 | 489 | ||
490 | static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) | 490 | static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc) |
491 | { | 491 | { |
492 | struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq); | 492 | struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq); |
493 | int gpio_irq = pm->virq; | 493 | int gpio_irq = pm->virq; |
494 | u32 stat = __raw_readl(pm->irqstat); | 494 | u32 stat = __raw_readl(pm->irqstat); |
495 | 495 | ||
496 | while (stat) { | 496 | while (stat) { |
497 | if (stat & 1) | 497 | if (stat & 1) |
498 | irq_desc[gpio_irq].handle_irq(gpio_irq, | 498 | generic_handle_irq(gpio_irq); |
499 | &irq_desc[gpio_irq]); | ||
500 | gpio_irq++; | 499 | gpio_irq++; |
501 | stat >>= 1; | 500 | stat >>= 1; |
502 | } | 501 | } |
@@ -534,15 +533,15 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start) | |||
534 | 533 | ||
535 | for (virq = pm->virq; virq < pm->virq; virq++) { | 534 | for (virq = pm->virq; virq < pm->virq; virq++) { |
536 | gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); | 535 | gpio_irq_chip.irq_mask(irq_get_irq_data(virq)); |
537 | set_irq_chip(virq, &gpio_irq_chip); | 536 | irq_set_chip_and_handler(virq, &gpio_irq_chip, |
538 | set_irq_handler(virq, handle_level_irq); | 537 | handle_level_irq); |
539 | set_irq_flags(virq, IRQF_VALID); | 538 | set_irq_flags(virq, IRQF_VALID); |
540 | } | 539 | } |
541 | r = gpiochip_add(&pm->chip); | 540 | r = gpiochip_add(&pm->chip); |
542 | if (r < 0) | 541 | if (r < 0) |
543 | break; | 542 | break; |
544 | set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq); | 543 | irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq); |
545 | set_irq_data(pm->irq, pm); | 544 | irq_set_handler_data(pm->irq, pm); |
546 | } | 545 | } |
547 | return r; | 546 | return r; |
548 | } | 547 | } |
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c index 31d945d37e4f..f0cc8e19b094 100644 --- a/arch/arm/plat-versatile/fpga-irq.c +++ b/arch/arm/plat-versatile/fpga-irq.c | |||
@@ -30,7 +30,7 @@ static void fpga_irq_unmask(struct irq_data *d) | |||
30 | 30 | ||
31 | static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) | 31 | static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc) |
32 | { | 32 | { |
33 | struct fpga_irq_data *f = get_irq_desc_data(desc); | 33 | struct fpga_irq_data *f = irq_desc_get_handler_data(desc); |
34 | u32 status = readl(f->base + IRQ_STATUS); | 34 | u32 status = readl(f->base + IRQ_STATUS); |
35 | 35 | ||
36 | if (status == 0) { | 36 | if (status == 0) { |
@@ -55,17 +55,17 @@ void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f) | |||
55 | f->chip.irq_unmask = fpga_irq_unmask; | 55 | f->chip.irq_unmask = fpga_irq_unmask; |
56 | 56 | ||
57 | if (parent_irq != -1) { | 57 | if (parent_irq != -1) { |
58 | set_irq_data(parent_irq, f); | 58 | irq_set_handler_data(parent_irq, f); |
59 | set_irq_chained_handler(parent_irq, fpga_irq_handle); | 59 | irq_set_chained_handler(parent_irq, fpga_irq_handle); |
60 | } | 60 | } |
61 | 61 | ||
62 | for (i = 0; i < 32; i++) { | 62 | for (i = 0; i < 32; i++) { |
63 | if (valid & (1 << i)) { | 63 | if (valid & (1 << i)) { |
64 | unsigned int irq = f->irq_start + i; | 64 | unsigned int irq = f->irq_start + i; |
65 | 65 | ||
66 | set_irq_chip_data(irq, f); | 66 | irq_set_chip_data(irq, f); |
67 | set_irq_chip(irq, &f->chip); | 67 | irq_set_chip_and_handler(irq, &f->chip, |
68 | set_irq_handler(irq, handle_level_irq); | 68 | handle_level_irq); |
69 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | 69 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
70 | } | 70 | } |
71 | } | 71 | } |
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 49642b59f73d..e9d689b7c833 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig | |||
@@ -10,7 +10,6 @@ config AVR32 | |||
10 | select GENERIC_IRQ_PROBE | 10 | select GENERIC_IRQ_PROBE |
11 | select HARDIRQS_SW_RESEND | 11 | select HARDIRQS_SW_RESEND |
12 | select GENERIC_IRQ_SHOW | 12 | select GENERIC_IRQ_SHOW |
13 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
14 | help | 13 | help |
15 | AVR32 is a high-performance 32-bit RISC microprocessor core, | 14 | AVR32 is a high-performance 32-bit RISC microprocessor core, |
16 | designed for cost-sensitive embedded applications, with particular | 15 | designed for cost-sensitive embedded applications, with particular |
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c index 37534103574e..f308e1ddc629 100644 --- a/arch/avr32/mach-at32ap/pio.c +++ b/arch/avr32/mach-at32ap/pio.c | |||
@@ -282,7 +282,7 @@ static struct irq_chip gpio_irqchip = { | |||
282 | 282 | ||
283 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 283 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
284 | { | 284 | { |
285 | struct pio_device *pio = get_irq_desc_chip_data(desc); | 285 | struct pio_device *pio = irq_desc_get_chip_data(desc); |
286 | unsigned gpio_irq; | 286 | unsigned gpio_irq; |
287 | 287 | ||
288 | gpio_irq = (unsigned) irq_get_handler_data(irq); | 288 | gpio_irq = (unsigned) irq_get_handler_data(irq); |
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 672c21632f2f..8addb1220b4f 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -34,7 +34,6 @@ config BLACKFIN | |||
34 | select GENERIC_ATOMIC64 | 34 | select GENERIC_ATOMIC64 |
35 | select GENERIC_IRQ_PROBE | 35 | select GENERIC_IRQ_PROBE |
36 | select IRQ_PER_CPU if SMP | 36 | select IRQ_PER_CPU if SMP |
37 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
38 | 37 | ||
39 | config GENERIC_CSUM | 38 | config GENERIC_CSUM |
40 | def_bool y | 39 | def_bool y |
diff --git a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig index 362f59dd5228..ad0881ba30af 100644 --- a/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig +++ b/arch/blackfin/configs/BF527-AD7160-EVAL_defconfig | |||
@@ -46,7 +46,6 @@ CONFIG_UNIX=y | |||
46 | # CONFIG_WIRELESS is not set | 46 | # CONFIG_WIRELESS is not set |
47 | CONFIG_BLK_DEV_LOOP=y | 47 | CONFIG_BLK_DEV_LOOP=y |
48 | CONFIG_BLK_DEV_RAM=y | 48 | CONFIG_BLK_DEV_RAM=y |
49 | # CONFIG_MISC_DEVICES is not set | ||
50 | # CONFIG_INPUT_MOUSEDEV is not set | 49 | # CONFIG_INPUT_MOUSEDEV is not set |
51 | CONFIG_INPUT_EVDEV=y | 50 | CONFIG_INPUT_EVDEV=y |
52 | # CONFIG_INPUT_KEYBOARD is not set | 51 | # CONFIG_INPUT_KEYBOARD is not set |
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig index 6883803e6ca8..580bf4296a14 100644 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig | |||
@@ -70,7 +70,6 @@ CONFIG_MTD_ROM=m | |||
70 | CONFIG_MTD_PHYSMAP=m | 70 | CONFIG_MTD_PHYSMAP=m |
71 | CONFIG_MTD_NAND=m | 71 | CONFIG_MTD_NAND=m |
72 | CONFIG_BLK_DEV_RAM=y | 72 | CONFIG_BLK_DEV_RAM=y |
73 | # CONFIG_MISC_DEVICES is not set | ||
74 | CONFIG_NETDEVICES=y | 73 | CONFIG_NETDEVICES=y |
75 | CONFIG_PHYLIB=y | 74 | CONFIG_PHYLIB=y |
76 | CONFIG_SMSC_PHY=y | 75 | CONFIG_SMSC_PHY=y |
diff --git a/arch/blackfin/configs/BF561-ACVILON_defconfig b/arch/blackfin/configs/BF561-ACVILON_defconfig index b7c8451f26ac..77a27e31d6d1 100644 --- a/arch/blackfin/configs/BF561-ACVILON_defconfig +++ b/arch/blackfin/configs/BF561-ACVILON_defconfig | |||
@@ -63,7 +63,6 @@ CONFIG_BLK_DEV_LOOP=y | |||
63 | CONFIG_BLK_DEV_RAM=y | 63 | CONFIG_BLK_DEV_RAM=y |
64 | CONFIG_BLK_DEV_RAM_COUNT=2 | 64 | CONFIG_BLK_DEV_RAM_COUNT=2 |
65 | CONFIG_BLK_DEV_RAM_SIZE=16384 | 65 | CONFIG_BLK_DEV_RAM_SIZE=16384 |
66 | # CONFIG_MISC_DEVICES is not set | ||
67 | CONFIG_SCSI=y | 66 | CONFIG_SCSI=y |
68 | # CONFIG_SCSI_PROC_FS is not set | 67 | # CONFIG_SCSI_PROC_FS is not set |
69 | CONFIG_BLK_DEV_SD=y | 68 | CONFIG_BLK_DEV_SD=y |
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index 97ebe09a7370..85014319672c 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig | |||
@@ -58,6 +58,7 @@ CONFIG_MTD_M25P80=y | |||
58 | CONFIG_BLK_DEV_LOOP=y | 58 | CONFIG_BLK_DEV_LOOP=y |
59 | CONFIG_BLK_DEV_NBD=y | 59 | CONFIG_BLK_DEV_NBD=y |
60 | CONFIG_BLK_DEV_RAM=y | 60 | CONFIG_BLK_DEV_RAM=y |
61 | CONFIG_MISC_DEVICES=y | ||
61 | CONFIG_EEPROM_AT25=y | 62 | CONFIG_EEPROM_AT25=y |
62 | CONFIG_NETDEVICES=y | 63 | CONFIG_NETDEVICES=y |
63 | CONFIG_NET_ETHERNET=y | 64 | CONFIG_NET_ETHERNET=y |
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index c2457543e58c..dbf750cd2db8 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig | |||
@@ -64,7 +64,6 @@ CONFIG_MTD_ROM=m | |||
64 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 64 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
65 | CONFIG_MTD_GPIO_ADDR=y | 65 | CONFIG_MTD_GPIO_ADDR=y |
66 | CONFIG_BLK_DEV_RAM=y | 66 | CONFIG_BLK_DEV_RAM=y |
67 | # CONFIG_MISC_DEVICES is not set | ||
68 | CONFIG_SCSI=y | 67 | CONFIG_SCSI=y |
69 | CONFIG_BLK_DEV_SD=y | 68 | CONFIG_BLK_DEV_SD=y |
70 | # CONFIG_SCSI_LOWLEVEL is not set | 69 | # CONFIG_SCSI_LOWLEVEL is not set |
diff --git a/arch/blackfin/configs/CM-BF533_defconfig b/arch/blackfin/configs/CM-BF533_defconfig index baf1c1573e5e..07ffbdae34ee 100644 --- a/arch/blackfin/configs/CM-BF533_defconfig +++ b/arch/blackfin/configs/CM-BF533_defconfig | |||
@@ -44,7 +44,6 @@ CONFIG_MTD_CFI=y | |||
44 | CONFIG_MTD_CFI_INTELEXT=y | 44 | CONFIG_MTD_CFI_INTELEXT=y |
45 | CONFIG_MTD_RAM=y | 45 | CONFIG_MTD_RAM=y |
46 | CONFIG_MTD_PHYSMAP=y | 46 | CONFIG_MTD_PHYSMAP=y |
47 | # CONFIG_MISC_DEVICES is not set | ||
48 | CONFIG_NETDEVICES=y | 47 | CONFIG_NETDEVICES=y |
49 | # CONFIG_NETDEV_1000 is not set | 48 | # CONFIG_NETDEV_1000 is not set |
50 | # CONFIG_NETDEV_10000 is not set | 49 | # CONFIG_NETDEV_10000 is not set |
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index df267588efec..31d954216c05 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig | |||
@@ -63,7 +63,6 @@ CONFIG_MTD_RAM=y | |||
63 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 63 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
64 | CONFIG_MTD_PHYSMAP=y | 64 | CONFIG_MTD_PHYSMAP=y |
65 | CONFIG_BLK_DEV_RAM=y | 65 | CONFIG_BLK_DEV_RAM=y |
66 | # CONFIG_MISC_DEVICES is not set | ||
67 | CONFIG_SCSI=m | 66 | CONFIG_SCSI=m |
68 | CONFIG_BLK_DEV_SD=m | 67 | CONFIG_BLK_DEV_SD=m |
69 | # CONFIG_SCSI_LOWLEVEL is not set | 68 | # CONFIG_SCSI_LOWLEVEL is not set |
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig index f50313657f3e..b192acfae386 100644 --- a/arch/blackfin/configs/DNP5370_defconfig +++ b/arch/blackfin/configs/DNP5370_defconfig | |||
@@ -55,7 +55,6 @@ CONFIG_MTD_NAND=y | |||
55 | CONFIG_MTD_NAND_PLATFORM=y | 55 | CONFIG_MTD_NAND_PLATFORM=y |
56 | CONFIG_BLK_DEV_LOOP=y | 56 | CONFIG_BLK_DEV_LOOP=y |
57 | CONFIG_BLK_DEV_RAM=y | 57 | CONFIG_BLK_DEV_RAM=y |
58 | # CONFIG_MISC_DEVICES is not set | ||
59 | CONFIG_NETDEVICES=y | 58 | CONFIG_NETDEVICES=y |
60 | CONFIG_DAVICOM_PHY=y | 59 | CONFIG_DAVICOM_PHY=y |
61 | CONFIG_NET_ETHERNET=y | 60 | CONFIG_NET_ETHERNET=y |
diff --git a/arch/blackfin/configs/H8606_defconfig b/arch/blackfin/configs/H8606_defconfig index 7450127b6455..06e9f497faed 100644 --- a/arch/blackfin/configs/H8606_defconfig +++ b/arch/blackfin/configs/H8606_defconfig | |||
@@ -45,6 +45,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y | |||
45 | CONFIG_MTD_M25P80=y | 45 | CONFIG_MTD_M25P80=y |
46 | # CONFIG_M25PXX_USE_FAST_READ is not set | 46 | # CONFIG_M25PXX_USE_FAST_READ is not set |
47 | CONFIG_BLK_DEV_RAM=y | 47 | CONFIG_BLK_DEV_RAM=y |
48 | CONFIG_MISC_DEVICES=y | ||
48 | CONFIG_EEPROM_AT25=y | 49 | CONFIG_EEPROM_AT25=y |
49 | CONFIG_NETDEVICES=y | 50 | CONFIG_NETDEVICES=y |
50 | CONFIG_NET_ETHERNET=y | 51 | CONFIG_NET_ETHERNET=y |
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index 853809510ee9..12e66cd7cdaa 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig | |||
@@ -48,6 +48,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y | |||
48 | CONFIG_MTD_UCLINUX=y | 48 | CONFIG_MTD_UCLINUX=y |
49 | CONFIG_MTD_NAND=m | 49 | CONFIG_MTD_NAND=m |
50 | CONFIG_BLK_DEV_RAM=y | 50 | CONFIG_BLK_DEV_RAM=y |
51 | CONFIG_MISC_DEVICES=y | ||
51 | CONFIG_EEPROM_AT25=m | 52 | CONFIG_EEPROM_AT25=m |
52 | CONFIG_NETDEVICES=y | 53 | CONFIG_NETDEVICES=y |
53 | # CONFIG_NETDEV_1000 is not set | 54 | # CONFIG_NETDEV_1000 is not set |
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 49762c6bb0d5..8a0fed16058f 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h | |||
@@ -25,7 +25,6 @@ | |||
25 | #include <asm-generic/bitops/const_hweight.h> | 25 | #include <asm-generic/bitops/const_hweight.h> |
26 | #include <asm-generic/bitops/lock.h> | 26 | #include <asm-generic/bitops/lock.h> |
27 | 27 | ||
28 | #include <asm-generic/bitops/le.h> | ||
29 | #include <asm-generic/bitops/ext2-atomic.h> | 28 | #include <asm-generic/bitops/ext2-atomic.h> |
30 | 29 | ||
31 | #ifndef CONFIG_SMP | 30 | #ifndef CONFIG_SMP |
@@ -113,6 +112,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) | |||
113 | 112 | ||
114 | #endif /* CONFIG_SMP */ | 113 | #endif /* CONFIG_SMP */ |
115 | 114 | ||
115 | /* Needs to be after test_bit and friends */ | ||
116 | #include <asm-generic/bitops/le.h> | ||
117 | |||
116 | /* | 118 | /* |
117 | * hweightN: returns the hamming weight (i.e. the number | 119 | * hweightN: returns the hamming weight (i.e. the number |
118 | * of bits set) of a N-bit word | 120 | * of bits set) of a N-bit word |
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 8f079392aff0..1696d34f51c2 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c | |||
@@ -48,7 +48,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
48 | seq_printf(p, "%3d: ", i); | 48 | seq_printf(p, "%3d: ", i); |
49 | for_each_online_cpu(j) | 49 | for_each_online_cpu(j) |
50 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | 50 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); |
51 | seq_printf(p, " %8s", get_irq_desc_chip(desc)->name); | 51 | seq_printf(p, " %8s", irq_desc_get_chip(desc)->name); |
52 | seq_printf(p, " %s", action->name); | 52 | seq_printf(p, " %s", action->name); |
53 | for (action = action->next; action; action = action->next) | 53 | for (action = action->next; action; action = action->next) |
54 | seq_printf(p, " %s", action->name); | 54 | seq_printf(p, " %s", action->name); |
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c index a6dfa6b71e63..35e350cad9d9 100644 --- a/arch/blackfin/kernel/module.c +++ b/arch/blackfin/kernel/module.c | |||
@@ -4,7 +4,7 @@ | |||
4 | * Licensed under the GPL-2 or later | 4 | * Licensed under the GPL-2 or later |
5 | */ | 5 | */ |
6 | 6 | ||
7 | #define pr_fmt(fmt) "module %s: " fmt | 7 | #define pr_fmt(fmt) "module %s: " fmt, mod->name |
8 | 8 | ||
9 | #include <linux/moduleloader.h> | 9 | #include <linux/moduleloader.h> |
10 | #include <linux/elf.h> | 10 | #include <linux/elf.h> |
@@ -57,8 +57,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
57 | dest = l1_inst_sram_alloc(s->sh_size); | 57 | dest = l1_inst_sram_alloc(s->sh_size); |
58 | mod->arch.text_l1 = dest; | 58 | mod->arch.text_l1 = dest; |
59 | if (dest == NULL) { | 59 | if (dest == NULL) { |
60 | pr_err("L1 inst memory allocation failed\n", | 60 | pr_err("L1 inst memory allocation failed\n"); |
61 | mod->name); | ||
62 | return -1; | 61 | return -1; |
63 | } | 62 | } |
64 | dma_memcpy(dest, (void *)s->sh_addr, s->sh_size); | 63 | dma_memcpy(dest, (void *)s->sh_addr, s->sh_size); |
@@ -70,8 +69,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
70 | dest = l1_data_sram_alloc(s->sh_size); | 69 | dest = l1_data_sram_alloc(s->sh_size); |
71 | mod->arch.data_a_l1 = dest; | 70 | mod->arch.data_a_l1 = dest; |
72 | if (dest == NULL) { | 71 | if (dest == NULL) { |
73 | pr_err("L1 data memory allocation failed\n", | 72 | pr_err("L1 data memory allocation failed\n"); |
74 | mod->name); | ||
75 | return -1; | 73 | return -1; |
76 | } | 74 | } |
77 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 75 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
@@ -83,8 +81,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
83 | dest = l1_data_sram_zalloc(s->sh_size); | 81 | dest = l1_data_sram_zalloc(s->sh_size); |
84 | mod->arch.bss_a_l1 = dest; | 82 | mod->arch.bss_a_l1 = dest; |
85 | if (dest == NULL) { | 83 | if (dest == NULL) { |
86 | pr_err("L1 data memory allocation failed\n", | 84 | pr_err("L1 data memory allocation failed\n"); |
87 | mod->name); | ||
88 | return -1; | 85 | return -1; |
89 | } | 86 | } |
90 | 87 | ||
@@ -93,8 +90,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
93 | dest = l1_data_B_sram_alloc(s->sh_size); | 90 | dest = l1_data_B_sram_alloc(s->sh_size); |
94 | mod->arch.data_b_l1 = dest; | 91 | mod->arch.data_b_l1 = dest; |
95 | if (dest == NULL) { | 92 | if (dest == NULL) { |
96 | pr_err("L1 data memory allocation failed\n", | 93 | pr_err("L1 data memory allocation failed\n"); |
97 | mod->name); | ||
98 | return -1; | 94 | return -1; |
99 | } | 95 | } |
100 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 96 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
@@ -104,8 +100,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
104 | dest = l1_data_B_sram_alloc(s->sh_size); | 100 | dest = l1_data_B_sram_alloc(s->sh_size); |
105 | mod->arch.bss_b_l1 = dest; | 101 | mod->arch.bss_b_l1 = dest; |
106 | if (dest == NULL) { | 102 | if (dest == NULL) { |
107 | pr_err("L1 data memory allocation failed\n", | 103 | pr_err("L1 data memory allocation failed\n"); |
108 | mod->name); | ||
109 | return -1; | 104 | return -1; |
110 | } | 105 | } |
111 | memset(dest, 0, s->sh_size); | 106 | memset(dest, 0, s->sh_size); |
@@ -117,8 +112,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
117 | dest = l2_sram_alloc(s->sh_size); | 112 | dest = l2_sram_alloc(s->sh_size); |
118 | mod->arch.text_l2 = dest; | 113 | mod->arch.text_l2 = dest; |
119 | if (dest == NULL) { | 114 | if (dest == NULL) { |
120 | pr_err("L2 SRAM allocation failed\n", | 115 | pr_err("L2 SRAM allocation failed\n"); |
121 | mod->name); | ||
122 | return -1; | 116 | return -1; |
123 | } | 117 | } |
124 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 118 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
@@ -130,8 +124,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
130 | dest = l2_sram_alloc(s->sh_size); | 124 | dest = l2_sram_alloc(s->sh_size); |
131 | mod->arch.data_l2 = dest; | 125 | mod->arch.data_l2 = dest; |
132 | if (dest == NULL) { | 126 | if (dest == NULL) { |
133 | pr_err("L2 SRAM allocation failed\n", | 127 | pr_err("L2 SRAM allocation failed\n"); |
134 | mod->name); | ||
135 | return -1; | 128 | return -1; |
136 | } | 129 | } |
137 | memcpy(dest, (void *)s->sh_addr, s->sh_size); | 130 | memcpy(dest, (void *)s->sh_addr, s->sh_size); |
@@ -143,8 +136,7 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
143 | dest = l2_sram_zalloc(s->sh_size); | 136 | dest = l2_sram_zalloc(s->sh_size); |
144 | mod->arch.bss_l2 = dest; | 137 | mod->arch.bss_l2 = dest; |
145 | if (dest == NULL) { | 138 | if (dest == NULL) { |
146 | pr_err("L2 SRAM allocation failed\n", | 139 | pr_err("L2 SRAM allocation failed\n"); |
147 | mod->name); | ||
148 | return -1; | 140 | return -1; |
149 | } | 141 | } |
150 | 142 | ||
@@ -160,9 +152,9 @@ module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs, | |||
160 | 152 | ||
161 | int | 153 | int |
162 | apply_relocate(Elf_Shdr * sechdrs, const char *strtab, | 154 | apply_relocate(Elf_Shdr * sechdrs, const char *strtab, |
163 | unsigned int symindex, unsigned int relsec, struct module *me) | 155 | unsigned int symindex, unsigned int relsec, struct module *mod) |
164 | { | 156 | { |
165 | pr_err(".rel unsupported\n", me->name); | 157 | pr_err(".rel unsupported\n"); |
166 | return -ENOEXEC; | 158 | return -ENOEXEC; |
167 | } | 159 | } |
168 | 160 | ||
@@ -186,7 +178,7 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, | |||
186 | Elf32_Sym *sym; | 178 | Elf32_Sym *sym; |
187 | unsigned long location, value, size; | 179 | unsigned long location, value, size; |
188 | 180 | ||
189 | pr_debug("applying relocate section %u to %u\n", mod->name, | 181 | pr_debug("applying relocate section %u to %u\n", |
190 | relsec, sechdrs[relsec].sh_info); | 182 | relsec, sechdrs[relsec].sh_info); |
191 | 183 | ||
192 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { | 184 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { |
@@ -203,14 +195,14 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, | |||
203 | 195 | ||
204 | #ifdef CONFIG_SMP | 196 | #ifdef CONFIG_SMP |
205 | if (location >= COREB_L1_DATA_A_START) { | 197 | if (location >= COREB_L1_DATA_A_START) { |
206 | pr_err("cannot relocate in L1: %u (SMP kernel)", | 198 | pr_err("cannot relocate in L1: %u (SMP kernel)\n", |
207 | mod->name, ELF32_R_TYPE(rel[i].r_info)); | 199 | ELF32_R_TYPE(rel[i].r_info)); |
208 | return -ENOEXEC; | 200 | return -ENOEXEC; |
209 | } | 201 | } |
210 | #endif | 202 | #endif |
211 | 203 | ||
212 | pr_debug("location is %lx, value is %lx type is %d\n", | 204 | pr_debug("location is %lx, value is %lx type is %d\n", |
213 | mod->name, location, value, ELF32_R_TYPE(rel[i].r_info)); | 205 | location, value, ELF32_R_TYPE(rel[i].r_info)); |
214 | 206 | ||
215 | switch (ELF32_R_TYPE(rel[i].r_info)) { | 207 | switch (ELF32_R_TYPE(rel[i].r_info)) { |
216 | 208 | ||
@@ -230,11 +222,11 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, | |||
230 | case R_BFIN_PCREL12_JUMP_S: | 222 | case R_BFIN_PCREL12_JUMP_S: |
231 | case R_BFIN_PCREL10: | 223 | case R_BFIN_PCREL10: |
232 | pr_err("unsupported relocation: %u (no -mlong-calls?)\n", | 224 | pr_err("unsupported relocation: %u (no -mlong-calls?)\n", |
233 | mod->name, ELF32_R_TYPE(rel[i].r_info)); | 225 | ELF32_R_TYPE(rel[i].r_info)); |
234 | return -ENOEXEC; | 226 | return -ENOEXEC; |
235 | 227 | ||
236 | default: | 228 | default: |
237 | pr_err("unknown relocation: %u\n", mod->name, | 229 | pr_err("unknown relocation: %u\n", |
238 | ELF32_R_TYPE(rel[i].r_info)); | 230 | ELF32_R_TYPE(rel[i].r_info)); |
239 | return -ENOEXEC; | 231 | return -ENOEXEC; |
240 | } | 232 | } |
@@ -251,8 +243,7 @@ apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, | |||
251 | isram_memcpy((void *)location, &value, size); | 243 | isram_memcpy((void *)location, &value, size); |
252 | break; | 244 | break; |
253 | default: | 245 | default: |
254 | pr_err("invalid relocation for %#lx\n", | 246 | pr_err("invalid relocation for %#lx\n", location); |
255 | mod->name, location); | ||
256 | return -ENOEXEC; | 247 | return -ENOEXEC; |
257 | } | 248 | } |
258 | } | 249 | } |
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c index 05b550891ce5..050db44fe919 100644 --- a/arch/blackfin/kernel/trace.c +++ b/arch/blackfin/kernel/trace.c | |||
@@ -912,10 +912,11 @@ void show_regs(struct pt_regs *fp) | |||
912 | /* if no interrupts are going off, don't print this out */ | 912 | /* if no interrupts are going off, don't print this out */ |
913 | if (fp->ipend & ~0x3F) { | 913 | if (fp->ipend & ~0x3F) { |
914 | for (i = 0; i < (NR_IRQS - 1); i++) { | 914 | for (i = 0; i < (NR_IRQS - 1); i++) { |
915 | struct irq_desc *desc = irq_to_desc(i); | ||
915 | if (!in_atomic) | 916 | if (!in_atomic) |
916 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | 917 | raw_spin_lock_irqsave(&desc->lock, flags); |
917 | 918 | ||
918 | action = irq_desc[i].action; | 919 | action = desc->action; |
919 | if (!action) | 920 | if (!action) |
920 | goto unlock; | 921 | goto unlock; |
921 | 922 | ||
@@ -928,7 +929,7 @@ void show_regs(struct pt_regs *fp) | |||
928 | pr_cont("\n"); | 929 | pr_cont("\n"); |
929 | unlock: | 930 | unlock: |
930 | if (!in_atomic) | 931 | if (!in_atomic) |
931 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | 932 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
932 | } | 933 | } |
933 | } | 934 | } |
934 | 935 | ||
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index 5d68bf613b0b..7b07740cf68c 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c | |||
@@ -154,13 +154,13 @@ void platform_clear_ipi(unsigned int cpu, int irq) | |||
154 | void __cpuinit bfin_local_timer_setup(void) | 154 | void __cpuinit bfin_local_timer_setup(void) |
155 | { | 155 | { |
156 | #if defined(CONFIG_TICKSOURCE_CORETMR) | 156 | #if defined(CONFIG_TICKSOURCE_CORETMR) |
157 | struct irq_chip *chip = get_irq_chip(IRQ_CORETMR); | 157 | struct irq_data *data = irq_get_irq_data(IRQ_CORETMR); |
158 | struct irq_desc *desc = irq_to_desc(IRQ_CORETMR); | 158 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
159 | 159 | ||
160 | bfin_coretmr_init(); | 160 | bfin_coretmr_init(); |
161 | bfin_coretmr_clockevent_init(); | 161 | bfin_coretmr_clockevent_init(); |
162 | 162 | ||
163 | chip->irq_unmask(&desc->irq_data); | 163 | chip->irq_unmask(data); |
164 | #else | 164 | #else |
165 | /* Power down the core timer, just to play safe. */ | 165 | /* Power down the core timer, just to play safe. */ |
166 | bfin_write_TCNTL(0); | 166 | bfin_write_TCNTL(0); |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 6cd52395a999..43d9fb195c1e 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
@@ -559,7 +559,7 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) | |||
559 | #ifdef CONFIG_IPIPE | 559 | #ifdef CONFIG_IPIPE |
560 | handle = handle_level_irq; | 560 | handle = handle_level_irq; |
561 | #endif | 561 | #endif |
562 | __set_irq_handler_unlocked(irq, handle); | 562 | __irq_set_handler_locked(irq, handle); |
563 | } | 563 | } |
564 | 564 | ||
565 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); | 565 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); |
@@ -578,10 +578,9 @@ static void bfin_gpio_ack_irq(struct irq_data *d) | |||
578 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) | 578 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
579 | { | 579 | { |
580 | unsigned int irq = d->irq; | 580 | unsigned int irq = d->irq; |
581 | struct irq_desc *desc = irq_to_desc(irq); | ||
582 | u32 gpionr = irq_to_gpio(irq); | 581 | u32 gpionr = irq_to_gpio(irq); |
583 | 582 | ||
584 | if (desc->handle_irq == handle_edge_irq) | 583 | if (!irqd_is_level_type(d)) |
585 | set_gpio_data(gpionr, 0); | 584 | set_gpio_data(gpionr, 0); |
586 | 585 | ||
587 | set_gpio_maska(gpionr, 0); | 586 | set_gpio_maska(gpionr, 0); |
@@ -837,12 +836,11 @@ void init_pint_lut(void) | |||
837 | 836 | ||
838 | static void bfin_gpio_ack_irq(struct irq_data *d) | 837 | static void bfin_gpio_ack_irq(struct irq_data *d) |
839 | { | 838 | { |
840 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
841 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; | 839 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
842 | u32 pintbit = PINT_BIT(pint_val); | 840 | u32 pintbit = PINT_BIT(pint_val); |
843 | u32 bank = PINT_2_BANK(pint_val); | 841 | u32 bank = PINT_2_BANK(pint_val); |
844 | 842 | ||
845 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | 843 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
846 | if (pint[bank]->invert_set & pintbit) | 844 | if (pint[bank]->invert_set & pintbit) |
847 | pint[bank]->invert_clear = pintbit; | 845 | pint[bank]->invert_clear = pintbit; |
848 | else | 846 | else |
@@ -854,12 +852,11 @@ static void bfin_gpio_ack_irq(struct irq_data *d) | |||
854 | 852 | ||
855 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) | 853 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
856 | { | 854 | { |
857 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
858 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; | 855 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
859 | u32 pintbit = PINT_BIT(pint_val); | 856 | u32 pintbit = PINT_BIT(pint_val); |
860 | u32 bank = PINT_2_BANK(pint_val); | 857 | u32 bank = PINT_2_BANK(pint_val); |
861 | 858 | ||
862 | if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { | 859 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
863 | if (pint[bank]->invert_set & pintbit) | 860 | if (pint[bank]->invert_set & pintbit) |
864 | pint[bank]->invert_clear = pintbit; | 861 | pint[bank]->invert_clear = pintbit; |
865 | else | 862 | else |
@@ -1166,9 +1163,9 @@ int __init init_arch_irq(void) | |||
1166 | 1163 | ||
1167 | for (irq = 0; irq <= SYS_IRQS; irq++) { | 1164 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
1168 | if (irq <= IRQ_CORETMR) | 1165 | if (irq <= IRQ_CORETMR) |
1169 | set_irq_chip(irq, &bfin_core_irqchip); | 1166 | irq_set_chip(irq, &bfin_core_irqchip); |
1170 | else | 1167 | else |
1171 | set_irq_chip(irq, &bfin_internal_irqchip); | 1168 | irq_set_chip(irq, &bfin_internal_irqchip); |
1172 | 1169 | ||
1173 | switch (irq) { | 1170 | switch (irq) { |
1174 | #if defined(CONFIG_BF53x) | 1171 | #if defined(CONFIG_BF53x) |
@@ -1192,50 +1189,50 @@ int __init init_arch_irq(void) | |||
1192 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) | 1189 | #elif defined(CONFIG_BF538) || defined(CONFIG_BF539) |
1193 | case IRQ_PORTF_INTA: | 1190 | case IRQ_PORTF_INTA: |
1194 | #endif | 1191 | #endif |
1195 | set_irq_chained_handler(irq, | 1192 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); |
1196 | bfin_demux_gpio_irq); | ||
1197 | break; | 1193 | break; |
1198 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | 1194 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
1199 | case IRQ_GENERIC_ERROR: | 1195 | case IRQ_GENERIC_ERROR: |
1200 | set_irq_chained_handler(irq, bfin_demux_error_irq); | 1196 | irq_set_chained_handler(irq, bfin_demux_error_irq); |
1201 | break; | 1197 | break; |
1202 | #endif | 1198 | #endif |
1203 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | 1199 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
1204 | case IRQ_MAC_ERROR: | 1200 | case IRQ_MAC_ERROR: |
1205 | set_irq_chained_handler(irq, bfin_demux_mac_status_irq); | 1201 | irq_set_chained_handler(irq, |
1202 | bfin_demux_mac_status_irq); | ||
1206 | break; | 1203 | break; |
1207 | #endif | 1204 | #endif |
1208 | #ifdef CONFIG_SMP | 1205 | #ifdef CONFIG_SMP |
1209 | case IRQ_SUPPLE_0: | 1206 | case IRQ_SUPPLE_0: |
1210 | case IRQ_SUPPLE_1: | 1207 | case IRQ_SUPPLE_1: |
1211 | set_irq_handler(irq, handle_percpu_irq); | 1208 | irq_set_handler(irq, handle_percpu_irq); |
1212 | break; | 1209 | break; |
1213 | #endif | 1210 | #endif |
1214 | 1211 | ||
1215 | #ifdef CONFIG_TICKSOURCE_CORETMR | 1212 | #ifdef CONFIG_TICKSOURCE_CORETMR |
1216 | case IRQ_CORETMR: | 1213 | case IRQ_CORETMR: |
1217 | # ifdef CONFIG_SMP | 1214 | # ifdef CONFIG_SMP |
1218 | set_irq_handler(irq, handle_percpu_irq); | 1215 | irq_set_handler(irq, handle_percpu_irq); |
1219 | break; | 1216 | break; |
1220 | # else | 1217 | # else |
1221 | set_irq_handler(irq, handle_simple_irq); | 1218 | irq_set_handler(irq, handle_simple_irq); |
1222 | break; | 1219 | break; |
1223 | # endif | 1220 | # endif |
1224 | #endif | 1221 | #endif |
1225 | 1222 | ||
1226 | #ifdef CONFIG_TICKSOURCE_GPTMR0 | 1223 | #ifdef CONFIG_TICKSOURCE_GPTMR0 |
1227 | case IRQ_TIMER0: | 1224 | case IRQ_TIMER0: |
1228 | set_irq_handler(irq, handle_simple_irq); | 1225 | irq_set_handler(irq, handle_simple_irq); |
1229 | break; | 1226 | break; |
1230 | #endif | 1227 | #endif |
1231 | 1228 | ||
1232 | #ifdef CONFIG_IPIPE | 1229 | #ifdef CONFIG_IPIPE |
1233 | default: | 1230 | default: |
1234 | set_irq_handler(irq, handle_level_irq); | 1231 | irq_set_handler(irq, handle_level_irq); |
1235 | break; | 1232 | break; |
1236 | #else /* !CONFIG_IPIPE */ | 1233 | #else /* !CONFIG_IPIPE */ |
1237 | default: | 1234 | default: |
1238 | set_irq_handler(irq, handle_simple_irq); | 1235 | irq_set_handler(irq, handle_simple_irq); |
1239 | break; | 1236 | break; |
1240 | #endif /* !CONFIG_IPIPE */ | 1237 | #endif /* !CONFIG_IPIPE */ |
1241 | } | 1238 | } |
@@ -1243,22 +1240,22 @@ int __init init_arch_irq(void) | |||
1243 | 1240 | ||
1244 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX | 1241 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
1245 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) | 1242 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) |
1246 | set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip, | 1243 | irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip, |
1247 | handle_level_irq); | 1244 | handle_level_irq); |
1248 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | 1245 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
1249 | set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); | 1246 | irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq); |
1250 | #endif | 1247 | #endif |
1251 | #endif | 1248 | #endif |
1252 | 1249 | ||
1253 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | 1250 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
1254 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) | 1251 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) |
1255 | set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip, | 1252 | irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, |
1256 | handle_level_irq); | 1253 | handle_level_irq); |
1257 | #endif | 1254 | #endif |
1258 | /* if configured as edge, then will be changed to do_edge_IRQ */ | 1255 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
1259 | for (irq = GPIO_IRQ_BASE; | 1256 | for (irq = GPIO_IRQ_BASE; |
1260 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) | 1257 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
1261 | set_irq_chip_and_handler(irq, &bfin_gpio_irqchip, | 1258 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, |
1262 | handle_level_irq); | 1259 | handle_level_irq); |
1263 | 1260 | ||
1264 | bfin_write_IMASK(0); | 1261 | bfin_write_IMASK(0); |
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig index 617925ddd142..a6d03069d0ff 100644 --- a/arch/cris/Kconfig +++ b/arch/cris/Kconfig | |||
@@ -55,7 +55,6 @@ config CRIS | |||
55 | default y | 55 | default y |
56 | select HAVE_IDE | 56 | select HAVE_IDE |
57 | select HAVE_GENERIC_HARDIRQS | 57 | select HAVE_GENERIC_HARDIRQS |
58 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
59 | select GENERIC_IRQ_SHOW | 58 | select GENERIC_IRQ_SHOW |
60 | 59 | ||
61 | config HZ | 60 | config HZ |
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig index f6037b2da25e..064f62196745 100644 --- a/arch/frv/Kconfig +++ b/arch/frv/Kconfig | |||
@@ -6,6 +6,7 @@ config FRV | |||
6 | select HAVE_IRQ_WORK | 6 | select HAVE_IRQ_WORK |
7 | select HAVE_PERF_EVENTS | 7 | select HAVE_PERF_EVENTS |
8 | select HAVE_GENERIC_HARDIRQS | 8 | select HAVE_GENERIC_HARDIRQS |
9 | select GENERIC_IRQ_SHOW | ||
9 | 10 | ||
10 | config ZONE_DMA | 11 | config ZONE_DMA |
11 | bool | 12 | bool |
@@ -361,7 +362,6 @@ menu "Power management options" | |||
361 | 362 | ||
362 | config ARCH_SUSPEND_POSSIBLE | 363 | config ARCH_SUSPEND_POSSIBLE |
363 | def_bool y | 364 | def_bool y |
364 | depends on !SMP | ||
365 | 365 | ||
366 | source kernel/power/Kconfig | 366 | source kernel/power/Kconfig |
367 | endmenu | 367 | endmenu |
diff --git a/arch/frv/include/asm/system.h b/arch/frv/include/asm/system.h index 0a6d8d9ca45b..6c10fd2c626d 100644 --- a/arch/frv/include/asm/system.h +++ b/arch/frv/include/asm/system.h | |||
@@ -45,21 +45,12 @@ do { \ | |||
45 | #define wmb() asm volatile ("membar" : : :"memory") | 45 | #define wmb() asm volatile ("membar" : : :"memory") |
46 | #define read_barrier_depends() do { } while (0) | 46 | #define read_barrier_depends() do { } while (0) |
47 | 47 | ||
48 | #ifdef CONFIG_SMP | ||
49 | #define smp_mb() mb() | ||
50 | #define smp_rmb() rmb() | ||
51 | #define smp_wmb() wmb() | ||
52 | #define smp_read_barrier_depends() read_barrier_depends() | ||
53 | #define set_mb(var, value) \ | ||
54 | do { xchg(&var, (value)); } while (0) | ||
55 | #else | ||
56 | #define smp_mb() barrier() | 48 | #define smp_mb() barrier() |
57 | #define smp_rmb() barrier() | 49 | #define smp_rmb() barrier() |
58 | #define smp_wmb() barrier() | 50 | #define smp_wmb() barrier() |
59 | #define smp_read_barrier_depends() do {} while(0) | 51 | #define smp_read_barrier_depends() do {} while(0) |
60 | #define set_mb(var, value) \ | 52 | #define set_mb(var, value) \ |
61 | do { var = (value); barrier(); } while (0) | 53 | do { var = (value); barrier(); } while (0) |
62 | #endif | ||
63 | 54 | ||
64 | extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2))); | 55 | extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2))); |
65 | extern void free_initmem(void); | 56 | extern void free_initmem(void); |
diff --git a/arch/frv/include/asm/thread_info.h b/arch/frv/include/asm/thread_info.h index 8582e9c7531c..cefbe73dc119 100644 --- a/arch/frv/include/asm/thread_info.h +++ b/arch/frv/include/asm/thread_info.h | |||
@@ -21,6 +21,8 @@ | |||
21 | 21 | ||
22 | #define THREAD_SIZE 8192 | 22 | #define THREAD_SIZE 8192 |
23 | 23 | ||
24 | #define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR | ||
25 | |||
24 | /* | 26 | /* |
25 | * low level task data that entry.S needs immediate access to | 27 | * low level task data that entry.S needs immediate access to |
26 | * - this struct should fit entirely inside of one cache line | 28 | * - this struct should fit entirely inside of one cache line |
@@ -87,7 +89,7 @@ register struct thread_info *__current_thread_info asm("gr15"); | |||
87 | #define alloc_thread_info_node(tsk, node) \ | 89 | #define alloc_thread_info_node(tsk, node) \ |
88 | kzalloc_node(THREAD_SIZE, GFP_KERNEL, node) | 90 | kzalloc_node(THREAD_SIZE, GFP_KERNEL, node) |
89 | #else | 91 | #else |
90 | #define alloc_thread_info_node(tsk) \ | 92 | #define alloc_thread_info_node(tsk, node) \ |
91 | kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) | 93 | kmalloc_node(THREAD_SIZE, GFP_KERNEL, node) |
92 | #endif | 94 | #endif |
93 | 95 | ||
diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c index 4dd9adaf115a..9afc2ea400dc 100644 --- a/arch/frv/kernel/irq-mb93091.c +++ b/arch/frv/kernel/irq-mb93091.c | |||
@@ -36,45 +36,45 @@ | |||
36 | /* | 36 | /* |
37 | * on-motherboard FPGA PIC operations | 37 | * on-motherboard FPGA PIC operations |
38 | */ | 38 | */ |
39 | static void frv_fpga_mask(unsigned int irq) | 39 | static void frv_fpga_mask(struct irq_data *d) |
40 | { | 40 | { |
41 | uint16_t imr = __get_IMR(); | 41 | uint16_t imr = __get_IMR(); |
42 | 42 | ||
43 | imr |= 1 << (irq - IRQ_BASE_FPGA); | 43 | imr |= 1 << (d->irq - IRQ_BASE_FPGA); |
44 | 44 | ||
45 | __set_IMR(imr); | 45 | __set_IMR(imr); |
46 | } | 46 | } |
47 | 47 | ||
48 | static void frv_fpga_ack(unsigned int irq) | 48 | static void frv_fpga_ack(struct irq_data *d) |
49 | { | 49 | { |
50 | __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); | 50 | __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); |
51 | } | 51 | } |
52 | 52 | ||
53 | static void frv_fpga_mask_ack(unsigned int irq) | 53 | static void frv_fpga_mask_ack(struct irq_data *d) |
54 | { | 54 | { |
55 | uint16_t imr = __get_IMR(); | 55 | uint16_t imr = __get_IMR(); |
56 | 56 | ||
57 | imr |= 1 << (irq - IRQ_BASE_FPGA); | 57 | imr |= 1 << (d->irq - IRQ_BASE_FPGA); |
58 | __set_IMR(imr); | 58 | __set_IMR(imr); |
59 | 59 | ||
60 | __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); | 60 | __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); |
61 | } | 61 | } |
62 | 62 | ||
63 | static void frv_fpga_unmask(unsigned int irq) | 63 | static void frv_fpga_unmask(struct irq_data *d) |
64 | { | 64 | { |
65 | uint16_t imr = __get_IMR(); | 65 | uint16_t imr = __get_IMR(); |
66 | 66 | ||
67 | imr &= ~(1 << (irq - IRQ_BASE_FPGA)); | 67 | imr &= ~(1 << (d->irq - IRQ_BASE_FPGA)); |
68 | 68 | ||
69 | __set_IMR(imr); | 69 | __set_IMR(imr); |
70 | } | 70 | } |
71 | 71 | ||
72 | static struct irq_chip frv_fpga_pic = { | 72 | static struct irq_chip frv_fpga_pic = { |
73 | .name = "mb93091", | 73 | .name = "mb93091", |
74 | .ack = frv_fpga_ack, | 74 | .irq_ack = frv_fpga_ack, |
75 | .mask = frv_fpga_mask, | 75 | .irq_mask = frv_fpga_mask, |
76 | .mask_ack = frv_fpga_mask_ack, | 76 | .irq_mask_ack = frv_fpga_mask_ack, |
77 | .unmask = frv_fpga_unmask, | 77 | .irq_unmask = frv_fpga_unmask, |
78 | }; | 78 | }; |
79 | 79 | ||
80 | /* | 80 | /* |
@@ -146,9 +146,9 @@ void __init fpga_init(void) | |||
146 | __clr_IFR(0x0000); | 146 | __clr_IFR(0x0000); |
147 | 147 | ||
148 | for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++) | 148 | for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++) |
149 | set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq); | 149 | irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq); |
150 | 150 | ||
151 | set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq); | 151 | irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq); |
152 | 152 | ||
153 | /* the FPGA drives the first four external IRQ inputs on the CPU PIC */ | 153 | /* the FPGA drives the first four external IRQ inputs on the CPU PIC */ |
154 | setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]); | 154 | setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]); |
diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c index e45209031873..4d4ad09d3c91 100644 --- a/arch/frv/kernel/irq-mb93093.c +++ b/arch/frv/kernel/irq-mb93093.c | |||
@@ -35,45 +35,44 @@ | |||
35 | /* | 35 | /* |
36 | * off-CPU FPGA PIC operations | 36 | * off-CPU FPGA PIC operations |
37 | */ | 37 | */ |
38 | static void frv_fpga_mask(unsigned int irq) | 38 | static void frv_fpga_mask(struct irq_data *d) |
39 | { | 39 | { |
40 | uint16_t imr = __get_IMR(); | 40 | uint16_t imr = __get_IMR(); |
41 | 41 | ||
42 | imr |= 1 << (irq - IRQ_BASE_FPGA); | 42 | imr |= 1 << (d->irq - IRQ_BASE_FPGA); |
43 | __set_IMR(imr); | 43 | __set_IMR(imr); |
44 | } | 44 | } |
45 | 45 | ||
46 | static void frv_fpga_ack(unsigned int irq) | 46 | static void frv_fpga_ack(struct irq_data *d) |
47 | { | 47 | { |
48 | __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); | 48 | __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); |
49 | } | 49 | } |
50 | 50 | ||
51 | static void frv_fpga_mask_ack(unsigned int irq) | 51 | static void frv_fpga_mask_ack(struct irq_data *d) |
52 | { | 52 | { |
53 | uint16_t imr = __get_IMR(); | 53 | uint16_t imr = __get_IMR(); |
54 | 54 | ||
55 | imr |= 1 << (irq - IRQ_BASE_FPGA); | 55 | imr |= 1 << (d->irq - IRQ_BASE_FPGA); |
56 | __set_IMR(imr); | 56 | __set_IMR(imr); |
57 | 57 | ||
58 | __clr_IFR(1 << (irq - IRQ_BASE_FPGA)); | 58 | __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA)); |
59 | } | 59 | } |
60 | 60 | ||
61 | static void frv_fpga_unmask(unsigned int irq) | 61 | static void frv_fpga_unmask(struct irq_data *d) |
62 | { | 62 | { |
63 | uint16_t imr = __get_IMR(); | 63 | uint16_t imr = __get_IMR(); |
64 | 64 | ||
65 | imr &= ~(1 << (irq - IRQ_BASE_FPGA)); | 65 | imr &= ~(1 << (d->irq - IRQ_BASE_FPGA)); |
66 | 66 | ||
67 | __set_IMR(imr); | 67 | __set_IMR(imr); |
68 | } | 68 | } |
69 | 69 | ||
70 | static struct irq_chip frv_fpga_pic = { | 70 | static struct irq_chip frv_fpga_pic = { |
71 | .name = "mb93093", | 71 | .name = "mb93093", |
72 | .ack = frv_fpga_ack, | 72 | .irq_ack = frv_fpga_ack, |
73 | .mask = frv_fpga_mask, | 73 | .irq_mask = frv_fpga_mask, |
74 | .mask_ack = frv_fpga_mask_ack, | 74 | .irq_mask_ack = frv_fpga_mask_ack, |
75 | .unmask = frv_fpga_unmask, | 75 | .irq_unmask = frv_fpga_unmask, |
76 | .end = frv_fpga_end, | ||
77 | }; | 76 | }; |
78 | 77 | ||
79 | /* | 78 | /* |
@@ -94,7 +93,7 @@ static irqreturn_t fpga_interrupt(int irq, void *_mask) | |||
94 | irq = 31 - irq; | 93 | irq = 31 - irq; |
95 | mask &= ~(1 << irq); | 94 | mask &= ~(1 << irq); |
96 | 95 | ||
97 | generic_irq_handle(IRQ_BASE_FPGA + irq); | 96 | generic_handle_irq(IRQ_BASE_FPGA + irq); |
98 | } | 97 | } |
99 | 98 | ||
100 | return IRQ_HANDLED; | 99 | return IRQ_HANDLED; |
@@ -125,7 +124,7 @@ void __init fpga_init(void) | |||
125 | __clr_IFR(0x0000); | 124 | __clr_IFR(0x0000); |
126 | 125 | ||
127 | for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++) | 126 | for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++) |
128 | set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq); | 127 | irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq); |
129 | 128 | ||
130 | /* the FPGA drives external IRQ input #2 on the CPU PIC */ | 129 | /* the FPGA drives external IRQ input #2 on the CPU PIC */ |
131 | setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]); | 130 | setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]); |
diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c index ba55ecdfb245..4d034c7840c9 100644 --- a/arch/frv/kernel/irq-mb93493.c +++ b/arch/frv/kernel/irq-mb93493.c | |||
@@ -45,46 +45,46 @@ | |||
45 | * daughter board PIC operations | 45 | * daughter board PIC operations |
46 | * - there is no way to ACK interrupts in the MB93493 chip | 46 | * - there is no way to ACK interrupts in the MB93493 chip |
47 | */ | 47 | */ |
48 | static void frv_mb93493_mask(unsigned int irq) | 48 | static void frv_mb93493_mask(struct irq_data *d) |
49 | { | 49 | { |
50 | uint32_t iqsr; | 50 | uint32_t iqsr; |
51 | volatile void *piqsr; | 51 | volatile void *piqsr; |
52 | 52 | ||
53 | if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493))) | 53 | if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493))) |
54 | piqsr = __addr_MB93493_IQSR(1); | 54 | piqsr = __addr_MB93493_IQSR(1); |
55 | else | 55 | else |
56 | piqsr = __addr_MB93493_IQSR(0); | 56 | piqsr = __addr_MB93493_IQSR(0); |
57 | 57 | ||
58 | iqsr = readl(piqsr); | 58 | iqsr = readl(piqsr); |
59 | iqsr &= ~(1 << (irq - IRQ_BASE_MB93493 + 16)); | 59 | iqsr &= ~(1 << (d->irq - IRQ_BASE_MB93493 + 16)); |
60 | writel(iqsr, piqsr); | 60 | writel(iqsr, piqsr); |
61 | } | 61 | } |
62 | 62 | ||
63 | static void frv_mb93493_ack(unsigned int irq) | 63 | static void frv_mb93493_ack(struct irq_data *d) |
64 | { | 64 | { |
65 | } | 65 | } |
66 | 66 | ||
67 | static void frv_mb93493_unmask(unsigned int irq) | 67 | static void frv_mb93493_unmask(struct irq_data *d) |
68 | { | 68 | { |
69 | uint32_t iqsr; | 69 | uint32_t iqsr; |
70 | volatile void *piqsr; | 70 | volatile void *piqsr; |
71 | 71 | ||
72 | if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493))) | 72 | if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493))) |
73 | piqsr = __addr_MB93493_IQSR(1); | 73 | piqsr = __addr_MB93493_IQSR(1); |
74 | else | 74 | else |
75 | piqsr = __addr_MB93493_IQSR(0); | 75 | piqsr = __addr_MB93493_IQSR(0); |
76 | 76 | ||
77 | iqsr = readl(piqsr); | 77 | iqsr = readl(piqsr); |
78 | iqsr |= 1 << (irq - IRQ_BASE_MB93493 + 16); | 78 | iqsr |= 1 << (d->irq - IRQ_BASE_MB93493 + 16); |
79 | writel(iqsr, piqsr); | 79 | writel(iqsr, piqsr); |
80 | } | 80 | } |
81 | 81 | ||
82 | static struct irq_chip frv_mb93493_pic = { | 82 | static struct irq_chip frv_mb93493_pic = { |
83 | .name = "mb93093", | 83 | .name = "mb93093", |
84 | .ack = frv_mb93493_ack, | 84 | .irq_ack = frv_mb93493_ack, |
85 | .mask = frv_mb93493_mask, | 85 | .irq_mask = frv_mb93493_mask, |
86 | .mask_ack = frv_mb93493_mask, | 86 | .irq_mask_ack = frv_mb93493_mask, |
87 | .unmask = frv_mb93493_unmask, | 87 | .irq_unmask = frv_mb93493_unmask, |
88 | }; | 88 | }; |
89 | 89 | ||
90 | /* | 90 | /* |
@@ -139,7 +139,8 @@ void __init mb93493_init(void) | |||
139 | int irq; | 139 | int irq; |
140 | 140 | ||
141 | for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++) | 141 | for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++) |
142 | set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq); | 142 | irq_set_chip_and_handler(irq, &frv_mb93493_pic, |
143 | handle_edge_irq); | ||
143 | 144 | ||
144 | /* the MB93493 drives external IRQ inputs on the CPU PIC */ | 145 | /* the MB93493 drives external IRQ inputs on the CPU PIC */ |
145 | setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]); | 146 | setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]); |
diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c index 625136625a7f..a5f624a9f559 100644 --- a/arch/frv/kernel/irq.c +++ b/arch/frv/kernel/irq.c | |||
@@ -47,89 +47,45 @@ extern void __init mb93493_init(void); | |||
47 | 47 | ||
48 | atomic_t irq_err_count; | 48 | atomic_t irq_err_count; |
49 | 49 | ||
50 | /* | 50 | int arch_show_interrupts(struct seq_file *p, int prec) |
51 | * Generic, controller-independent functions: | ||
52 | */ | ||
53 | int show_interrupts(struct seq_file *p, void *v) | ||
54 | { | 51 | { |
55 | int i = *(loff_t *) v, cpu; | 52 | seq_printf(p, "%*s: ", prec, "ERR"); |
56 | struct irqaction * action; | 53 | seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); |
57 | unsigned long flags; | ||
58 | |||
59 | if (i == 0) { | ||
60 | char cpuname[12]; | ||
61 | |||
62 | seq_printf(p, " "); | ||
63 | for_each_present_cpu(cpu) { | ||
64 | sprintf(cpuname, "CPU%d", cpu); | ||
65 | seq_printf(p, " %10s", cpuname); | ||
66 | } | ||
67 | seq_putc(p, '\n'); | ||
68 | } | ||
69 | |||
70 | if (i < NR_IRQS) { | ||
71 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
72 | action = irq_desc[i].action; | ||
73 | if (action) { | ||
74 | seq_printf(p, "%3d: ", i); | ||
75 | for_each_present_cpu(cpu) | ||
76 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); | ||
77 | seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-"); | ||
78 | seq_printf(p, " %s", action->name); | ||
79 | for (action = action->next; | ||
80 | action; | ||
81 | action = action->next) | ||
82 | seq_printf(p, ", %s", action->name); | ||
83 | |||
84 | seq_putc(p, '\n'); | ||
85 | } | ||
86 | |||
87 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
88 | } else if (i == NR_IRQS) { | ||
89 | seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count)); | ||
90 | } | ||
91 | |||
92 | return 0; | 54 | return 0; |
93 | } | 55 | } |
94 | 56 | ||
95 | /* | 57 | /* |
96 | * on-CPU PIC operations | 58 | * on-CPU PIC operations |
97 | */ | 59 | */ |
98 | static void frv_cpupic_ack(unsigned int irqlevel) | 60 | static void frv_cpupic_ack(struct irq_data *d) |
99 | { | 61 | { |
100 | __clr_RC(irqlevel); | 62 | __clr_RC(d->irq); |
101 | __clr_IRL(); | 63 | __clr_IRL(); |
102 | } | 64 | } |
103 | 65 | ||
104 | static void frv_cpupic_mask(unsigned int irqlevel) | 66 | static void frv_cpupic_mask(struct irq_data *d) |
105 | { | 67 | { |
106 | __set_MASK(irqlevel); | 68 | __set_MASK(d->irq); |
107 | } | 69 | } |
108 | 70 | ||
109 | static void frv_cpupic_mask_ack(unsigned int irqlevel) | 71 | static void frv_cpupic_mask_ack(struct irq_data *d) |
110 | { | 72 | { |
111 | __set_MASK(irqlevel); | 73 | __set_MASK(d->irq); |
112 | __clr_RC(irqlevel); | 74 | __clr_RC(d->irq); |
113 | __clr_IRL(); | 75 | __clr_IRL(); |
114 | } | 76 | } |
115 | 77 | ||
116 | static void frv_cpupic_unmask(unsigned int irqlevel) | 78 | static void frv_cpupic_unmask(struct irq_data *d) |
117 | { | ||
118 | __clr_MASK(irqlevel); | ||
119 | } | ||
120 | |||
121 | static void frv_cpupic_end(unsigned int irqlevel) | ||
122 | { | 79 | { |
123 | __clr_MASK(irqlevel); | 80 | __clr_MASK(d->irq); |
124 | } | 81 | } |
125 | 82 | ||
126 | static struct irq_chip frv_cpu_pic = { | 83 | static struct irq_chip frv_cpu_pic = { |
127 | .name = "cpu", | 84 | .name = "cpu", |
128 | .ack = frv_cpupic_ack, | 85 | .irq_ack = frv_cpupic_ack, |
129 | .mask = frv_cpupic_mask, | 86 | .irq_mask = frv_cpupic_mask, |
130 | .mask_ack = frv_cpupic_mask_ack, | 87 | .irq_mask_ack = frv_cpupic_mask_ack, |
131 | .unmask = frv_cpupic_unmask, | 88 | .irq_unmask = frv_cpupic_unmask, |
132 | .end = frv_cpupic_end, | ||
133 | }; | 89 | }; |
134 | 90 | ||
135 | /* | 91 | /* |
@@ -161,10 +117,10 @@ void __init init_IRQ(void) | |||
161 | int level; | 117 | int level; |
162 | 118 | ||
163 | for (level = 1; level <= 14; level++) | 119 | for (level = 1; level <= 14; level++) |
164 | set_irq_chip_and_handler(level, &frv_cpu_pic, | 120 | irq_set_chip_and_handler(level, &frv_cpu_pic, |
165 | handle_level_irq); | 121 | handle_level_irq); |
166 | 122 | ||
167 | set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq); | 123 | irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq); |
168 | 124 | ||
169 | /* set the trigger levels for internal interrupt sources | 125 | /* set the trigger levels for internal interrupt sources |
170 | * - timers all falling-edge | 126 | * - timers all falling-edge |
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig index 931a1ac99ff1..e20322ffcaf8 100644 --- a/arch/h8300/Kconfig +++ b/arch/h8300/Kconfig | |||
@@ -3,7 +3,6 @@ config H8300 | |||
3 | default y | 3 | default y |
4 | select HAVE_IDE | 4 | select HAVE_IDE |
5 | select HAVE_GENERIC_HARDIRQS | 5 | select HAVE_GENERIC_HARDIRQS |
6 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
7 | select GENERIC_IRQ_SHOW | 6 | select GENERIC_IRQ_SHOW |
8 | 7 | ||
9 | config SYMBOL_PREFIX | 8 | config SYMBOL_PREFIX |
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index fcf3b437a2d9..c4ea0925cdbd 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig | |||
@@ -26,6 +26,7 @@ config IA64 | |||
26 | select GENERIC_IRQ_PROBE | 26 | select GENERIC_IRQ_PROBE |
27 | select GENERIC_PENDING_IRQ if SMP | 27 | select GENERIC_PENDING_IRQ if SMP |
28 | select IRQ_PER_CPU | 28 | select IRQ_PER_CPU |
29 | select GENERIC_IRQ_SHOW | ||
29 | default y | 30 | default y |
30 | help | 31 | help |
31 | The Itanium Processor Family is Intel's 64-bit successor to | 32 | The Itanium Processor Family is Intel's 64-bit successor to |
diff --git a/arch/ia64/hp/sim/hpsim_irq.c b/arch/ia64/hp/sim/hpsim_irq.c index b272261d77cc..4bd9a63260ee 100644 --- a/arch/ia64/hp/sim/hpsim_irq.c +++ b/arch/ia64/hp/sim/hpsim_irq.c | |||
@@ -11,42 +11,41 @@ | |||
11 | #include <linux/irq.h> | 11 | #include <linux/irq.h> |
12 | 12 | ||
13 | static unsigned int | 13 | static unsigned int |
14 | hpsim_irq_startup (unsigned int irq) | 14 | hpsim_irq_startup(struct irq_data *data) |
15 | { | 15 | { |
16 | return 0; | 16 | return 0; |
17 | } | 17 | } |
18 | 18 | ||
19 | static void | 19 | static void |
20 | hpsim_irq_noop (unsigned int irq) | 20 | hpsim_irq_noop(struct irq_data *data) |
21 | { | 21 | { |
22 | } | 22 | } |
23 | 23 | ||
24 | static int | 24 | static int |
25 | hpsim_set_affinity_noop(unsigned int a, const struct cpumask *b) | 25 | hpsim_set_affinity_noop(struct irq_data *d, const struct cpumask *b, bool f) |
26 | { | 26 | { |
27 | return 0; | 27 | return 0; |
28 | } | 28 | } |
29 | 29 | ||
30 | static struct irq_chip irq_type_hp_sim = { | 30 | static struct irq_chip irq_type_hp_sim = { |
31 | .name = "hpsim", | 31 | .name = "hpsim", |
32 | .startup = hpsim_irq_startup, | 32 | .irq_startup = hpsim_irq_startup, |
33 | .shutdown = hpsim_irq_noop, | 33 | .irq_shutdown = hpsim_irq_noop, |
34 | .enable = hpsim_irq_noop, | 34 | .irq_enable = hpsim_irq_noop, |
35 | .disable = hpsim_irq_noop, | 35 | .irq_disable = hpsim_irq_noop, |
36 | .ack = hpsim_irq_noop, | 36 | .irq_ack = hpsim_irq_noop, |
37 | .end = hpsim_irq_noop, | 37 | .irq_set_affinity = hpsim_set_affinity_noop, |
38 | .set_affinity = hpsim_set_affinity_noop, | ||
39 | }; | 38 | }; |
40 | 39 | ||
41 | void __init | 40 | void __init |
42 | hpsim_irq_init (void) | 41 | hpsim_irq_init (void) |
43 | { | 42 | { |
44 | struct irq_desc *idesc; | ||
45 | int i; | 43 | int i; |
46 | 44 | ||
47 | for (i = 0; i < NR_IRQS; ++i) { | 45 | for_each_active_irq(i) { |
48 | idesc = irq_desc + i; | 46 | struct irq_chip *chip = irq_get_chip(i); |
49 | if (idesc->chip == &no_irq_chip) | 47 | |
50 | idesc->chip = &irq_type_hp_sim; | 48 | if (chip == &no_irq_chip) |
49 | irq_set_chip(i, &irq_type_hp_sim); | ||
51 | } | 50 | } |
52 | } | 51 | } |
diff --git a/arch/ia64/include/asm/hw_irq.h b/arch/ia64/include/asm/hw_irq.h index bf2e37493e04..a681d02cb324 100644 --- a/arch/ia64/include/asm/hw_irq.h +++ b/arch/ia64/include/asm/hw_irq.h | |||
@@ -151,9 +151,6 @@ static inline void ia64_native_resend_irq(unsigned int vector) | |||
151 | /* | 151 | /* |
152 | * Default implementations for the irq-descriptor API: | 152 | * Default implementations for the irq-descriptor API: |
153 | */ | 153 | */ |
154 | |||
155 | extern struct irq_desc irq_desc[NR_IRQS]; | ||
156 | |||
157 | #ifndef CONFIG_IA64_GENERIC | 154 | #ifndef CONFIG_IA64_GENERIC |
158 | static inline ia64_vector __ia64_irq_to_vector(int irq) | 155 | static inline ia64_vector __ia64_irq_to_vector(int irq) |
159 | { | 156 | { |
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c index 22c38404f539..b0f9afebb146 100644 --- a/arch/ia64/kernel/iosapic.c +++ b/arch/ia64/kernel/iosapic.c | |||
@@ -257,7 +257,7 @@ set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask) | |||
257 | } | 257 | } |
258 | 258 | ||
259 | static void | 259 | static void |
260 | nop (unsigned int irq) | 260 | nop (struct irq_data *data) |
261 | { | 261 | { |
262 | /* do nothing... */ | 262 | /* do nothing... */ |
263 | } | 263 | } |
@@ -287,8 +287,9 @@ kexec_disable_iosapic(void) | |||
287 | #endif | 287 | #endif |
288 | 288 | ||
289 | static void | 289 | static void |
290 | mask_irq (unsigned int irq) | 290 | mask_irq (struct irq_data *data) |
291 | { | 291 | { |
292 | unsigned int irq = data->irq; | ||
292 | u32 low32; | 293 | u32 low32; |
293 | int rte_index; | 294 | int rte_index; |
294 | struct iosapic_rte_info *rte; | 295 | struct iosapic_rte_info *rte; |
@@ -305,8 +306,9 @@ mask_irq (unsigned int irq) | |||
305 | } | 306 | } |
306 | 307 | ||
307 | static void | 308 | static void |
308 | unmask_irq (unsigned int irq) | 309 | unmask_irq (struct irq_data *data) |
309 | { | 310 | { |
311 | unsigned int irq = data->irq; | ||
310 | u32 low32; | 312 | u32 low32; |
311 | int rte_index; | 313 | int rte_index; |
312 | struct iosapic_rte_info *rte; | 314 | struct iosapic_rte_info *rte; |
@@ -323,9 +325,11 @@ unmask_irq (unsigned int irq) | |||
323 | 325 | ||
324 | 326 | ||
325 | static int | 327 | static int |
326 | iosapic_set_affinity(unsigned int irq, const struct cpumask *mask) | 328 | iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
329 | bool force) | ||
327 | { | 330 | { |
328 | #ifdef CONFIG_SMP | 331 | #ifdef CONFIG_SMP |
332 | unsigned int irq = data->irq; | ||
329 | u32 high32, low32; | 333 | u32 high32, low32; |
330 | int cpu, dest, rte_index; | 334 | int cpu, dest, rte_index; |
331 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; | 335 | int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0; |
@@ -379,32 +383,33 @@ iosapic_set_affinity(unsigned int irq, const struct cpumask *mask) | |||
379 | */ | 383 | */ |
380 | 384 | ||
381 | static unsigned int | 385 | static unsigned int |
382 | iosapic_startup_level_irq (unsigned int irq) | 386 | iosapic_startup_level_irq (struct irq_data *data) |
383 | { | 387 | { |
384 | unmask_irq(irq); | 388 | unmask_irq(data); |
385 | return 0; | 389 | return 0; |
386 | } | 390 | } |
387 | 391 | ||
388 | static void | 392 | static void |
389 | iosapic_unmask_level_irq (unsigned int irq) | 393 | iosapic_unmask_level_irq (struct irq_data *data) |
390 | { | 394 | { |
395 | unsigned int irq = data->irq; | ||
391 | ia64_vector vec = irq_to_vector(irq); | 396 | ia64_vector vec = irq_to_vector(irq); |
392 | struct iosapic_rte_info *rte; | 397 | struct iosapic_rte_info *rte; |
393 | int do_unmask_irq = 0; | 398 | int do_unmask_irq = 0; |
394 | 399 | ||
395 | irq_complete_move(irq); | 400 | irq_complete_move(irq); |
396 | if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { | 401 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
397 | do_unmask_irq = 1; | 402 | do_unmask_irq = 1; |
398 | mask_irq(irq); | 403 | mask_irq(data); |
399 | } else | 404 | } else |
400 | unmask_irq(irq); | 405 | unmask_irq(data); |
401 | 406 | ||
402 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) | 407 | list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) |
403 | iosapic_eoi(rte->iosapic->addr, vec); | 408 | iosapic_eoi(rte->iosapic->addr, vec); |
404 | 409 | ||
405 | if (unlikely(do_unmask_irq)) { | 410 | if (unlikely(do_unmask_irq)) { |
406 | move_masked_irq(irq); | 411 | irq_move_masked_irq(data); |
407 | unmask_irq(irq); | 412 | unmask_irq(data); |
408 | } | 413 | } |
409 | } | 414 | } |
410 | 415 | ||
@@ -414,15 +419,15 @@ iosapic_unmask_level_irq (unsigned int irq) | |||
414 | #define iosapic_ack_level_irq nop | 419 | #define iosapic_ack_level_irq nop |
415 | 420 | ||
416 | static struct irq_chip irq_type_iosapic_level = { | 421 | static struct irq_chip irq_type_iosapic_level = { |
417 | .name = "IO-SAPIC-level", | 422 | .name = "IO-SAPIC-level", |
418 | .startup = iosapic_startup_level_irq, | 423 | .irq_startup = iosapic_startup_level_irq, |
419 | .shutdown = iosapic_shutdown_level_irq, | 424 | .irq_shutdown = iosapic_shutdown_level_irq, |
420 | .enable = iosapic_enable_level_irq, | 425 | .irq_enable = iosapic_enable_level_irq, |
421 | .disable = iosapic_disable_level_irq, | 426 | .irq_disable = iosapic_disable_level_irq, |
422 | .ack = iosapic_ack_level_irq, | 427 | .irq_ack = iosapic_ack_level_irq, |
423 | .mask = mask_irq, | 428 | .irq_mask = mask_irq, |
424 | .unmask = iosapic_unmask_level_irq, | 429 | .irq_unmask = iosapic_unmask_level_irq, |
425 | .set_affinity = iosapic_set_affinity | 430 | .irq_set_affinity = iosapic_set_affinity |
426 | }; | 431 | }; |
427 | 432 | ||
428 | /* | 433 | /* |
@@ -430,9 +435,9 @@ static struct irq_chip irq_type_iosapic_level = { | |||
430 | */ | 435 | */ |
431 | 436 | ||
432 | static unsigned int | 437 | static unsigned int |
433 | iosapic_startup_edge_irq (unsigned int irq) | 438 | iosapic_startup_edge_irq (struct irq_data *data) |
434 | { | 439 | { |
435 | unmask_irq(irq); | 440 | unmask_irq(data); |
436 | /* | 441 | /* |
437 | * IOSAPIC simply drops interrupts pended while the | 442 | * IOSAPIC simply drops interrupts pended while the |
438 | * corresponding pin was masked, so we can't know if an | 443 | * corresponding pin was masked, so we can't know if an |
@@ -442,37 +447,25 @@ iosapic_startup_edge_irq (unsigned int irq) | |||
442 | } | 447 | } |
443 | 448 | ||
444 | static void | 449 | static void |
445 | iosapic_ack_edge_irq (unsigned int irq) | 450 | iosapic_ack_edge_irq (struct irq_data *data) |
446 | { | 451 | { |
447 | struct irq_desc *idesc = irq_desc + irq; | 452 | irq_complete_move(data->irq); |
448 | 453 | irq_move_irq(data); | |
449 | irq_complete_move(irq); | ||
450 | move_native_irq(irq); | ||
451 | /* | ||
452 | * Once we have recorded IRQ_PENDING already, we can mask the | ||
453 | * interrupt for real. This prevents IRQ storms from unhandled | ||
454 | * devices. | ||
455 | */ | ||
456 | if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) == | ||
457 | (IRQ_PENDING|IRQ_DISABLED)) | ||
458 | mask_irq(irq); | ||
459 | } | 454 | } |
460 | 455 | ||
461 | #define iosapic_enable_edge_irq unmask_irq | 456 | #define iosapic_enable_edge_irq unmask_irq |
462 | #define iosapic_disable_edge_irq nop | 457 | #define iosapic_disable_edge_irq nop |
463 | #define iosapic_end_edge_irq nop | ||
464 | 458 | ||
465 | static struct irq_chip irq_type_iosapic_edge = { | 459 | static struct irq_chip irq_type_iosapic_edge = { |
466 | .name = "IO-SAPIC-edge", | 460 | .name = "IO-SAPIC-edge", |
467 | .startup = iosapic_startup_edge_irq, | 461 | .irq_startup = iosapic_startup_edge_irq, |
468 | .shutdown = iosapic_disable_edge_irq, | 462 | .irq_shutdown = iosapic_disable_edge_irq, |
469 | .enable = iosapic_enable_edge_irq, | 463 | .irq_enable = iosapic_enable_edge_irq, |
470 | .disable = iosapic_disable_edge_irq, | 464 | .irq_disable = iosapic_disable_edge_irq, |
471 | .ack = iosapic_ack_edge_irq, | 465 | .irq_ack = iosapic_ack_edge_irq, |
472 | .end = iosapic_end_edge_irq, | 466 | .irq_mask = mask_irq, |
473 | .mask = mask_irq, | 467 | .irq_unmask = unmask_irq, |
474 | .unmask = unmask_irq, | 468 | .irq_set_affinity = iosapic_set_affinity |
475 | .set_affinity = iosapic_set_affinity | ||
476 | }; | 469 | }; |
477 | 470 | ||
478 | static unsigned int | 471 | static unsigned int |
@@ -562,8 +555,7 @@ static int | |||
562 | register_intr (unsigned int gsi, int irq, unsigned char delivery, | 555 | register_intr (unsigned int gsi, int irq, unsigned char delivery, |
563 | unsigned long polarity, unsigned long trigger) | 556 | unsigned long polarity, unsigned long trigger) |
564 | { | 557 | { |
565 | struct irq_desc *idesc; | 558 | struct irq_chip *chip, *irq_type; |
566 | struct irq_chip *irq_type; | ||
567 | int index; | 559 | int index; |
568 | struct iosapic_rte_info *rte; | 560 | struct iosapic_rte_info *rte; |
569 | 561 | ||
@@ -610,19 +602,18 @@ register_intr (unsigned int gsi, int irq, unsigned char delivery, | |||
610 | 602 | ||
611 | irq_type = iosapic_get_irq_chip(trigger); | 603 | irq_type = iosapic_get_irq_chip(trigger); |
612 | 604 | ||
613 | idesc = irq_desc + irq; | 605 | chip = irq_get_chip(irq); |
614 | if (irq_type != NULL && idesc->chip != irq_type) { | 606 | if (irq_type != NULL && chip != irq_type) { |
615 | if (idesc->chip != &no_irq_chip) | 607 | if (chip != &no_irq_chip) |
616 | printk(KERN_WARNING | 608 | printk(KERN_WARNING |
617 | "%s: changing vector %d from %s to %s\n", | 609 | "%s: changing vector %d from %s to %s\n", |
618 | __func__, irq_to_vector(irq), | 610 | __func__, irq_to_vector(irq), |
619 | idesc->chip->name, irq_type->name); | 611 | chip->name, irq_type->name); |
620 | idesc->chip = irq_type; | 612 | chip = irq_type; |
621 | } | 613 | } |
622 | if (trigger == IOSAPIC_EDGE) | 614 | __irq_set_chip_handler_name_locked(irq, chip, trigger == IOSAPIC_EDGE ? |
623 | __set_irq_handler_unlocked(irq, handle_edge_irq); | 615 | handle_edge_irq : handle_level_irq, |
624 | else | 616 | NULL); |
625 | __set_irq_handler_unlocked(irq, handle_level_irq); | ||
626 | return 0; | 617 | return 0; |
627 | } | 618 | } |
628 | 619 | ||
@@ -732,6 +723,7 @@ iosapic_register_intr (unsigned int gsi, | |||
732 | struct iosapic_rte_info *rte; | 723 | struct iosapic_rte_info *rte; |
733 | u32 low32; | 724 | u32 low32; |
734 | unsigned char dmode; | 725 | unsigned char dmode; |
726 | struct irq_desc *desc; | ||
735 | 727 | ||
736 | /* | 728 | /* |
737 | * If this GSI has already been registered (i.e., it's a | 729 | * If this GSI has already been registered (i.e., it's a |
@@ -759,12 +751,13 @@ iosapic_register_intr (unsigned int gsi, | |||
759 | goto unlock_iosapic_lock; | 751 | goto unlock_iosapic_lock; |
760 | } | 752 | } |
761 | 753 | ||
762 | raw_spin_lock(&irq_desc[irq].lock); | 754 | desc = irq_to_desc(irq); |
755 | raw_spin_lock(&desc->lock); | ||
763 | dest = get_target_cpu(gsi, irq); | 756 | dest = get_target_cpu(gsi, irq); |
764 | dmode = choose_dmode(); | 757 | dmode = choose_dmode(); |
765 | err = register_intr(gsi, irq, dmode, polarity, trigger); | 758 | err = register_intr(gsi, irq, dmode, polarity, trigger); |
766 | if (err < 0) { | 759 | if (err < 0) { |
767 | raw_spin_unlock(&irq_desc[irq].lock); | 760 | raw_spin_unlock(&desc->lock); |
768 | irq = err; | 761 | irq = err; |
769 | goto unlock_iosapic_lock; | 762 | goto unlock_iosapic_lock; |
770 | } | 763 | } |
@@ -783,7 +776,7 @@ iosapic_register_intr (unsigned int gsi, | |||
783 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), | 776 | (polarity == IOSAPIC_POL_HIGH ? "high" : "low"), |
784 | cpu_logical_id(dest), dest, irq_to_vector(irq)); | 777 | cpu_logical_id(dest), dest, irq_to_vector(irq)); |
785 | 778 | ||
786 | raw_spin_unlock(&irq_desc[irq].lock); | 779 | raw_spin_unlock(&desc->lock); |
787 | unlock_iosapic_lock: | 780 | unlock_iosapic_lock: |
788 | spin_unlock_irqrestore(&iosapic_lock, flags); | 781 | spin_unlock_irqrestore(&iosapic_lock, flags); |
789 | return irq; | 782 | return irq; |
@@ -794,7 +787,6 @@ iosapic_unregister_intr (unsigned int gsi) | |||
794 | { | 787 | { |
795 | unsigned long flags; | 788 | unsigned long flags; |
796 | int irq, index; | 789 | int irq, index; |
797 | struct irq_desc *idesc; | ||
798 | u32 low32; | 790 | u32 low32; |
799 | unsigned long trigger, polarity; | 791 | unsigned long trigger, polarity; |
800 | unsigned int dest; | 792 | unsigned int dest; |
@@ -824,7 +816,6 @@ iosapic_unregister_intr (unsigned int gsi) | |||
824 | if (--rte->refcnt > 0) | 816 | if (--rte->refcnt > 0) |
825 | goto out; | 817 | goto out; |
826 | 818 | ||
827 | idesc = irq_desc + irq; | ||
828 | rte->refcnt = NO_REF_RTE; | 819 | rte->refcnt = NO_REF_RTE; |
829 | 820 | ||
830 | /* Mask the interrupt */ | 821 | /* Mask the interrupt */ |
@@ -848,7 +839,7 @@ iosapic_unregister_intr (unsigned int gsi) | |||
848 | if (iosapic_intr_info[irq].count == 0) { | 839 | if (iosapic_intr_info[irq].count == 0) { |
849 | #ifdef CONFIG_SMP | 840 | #ifdef CONFIG_SMP |
850 | /* Clear affinity */ | 841 | /* Clear affinity */ |
851 | cpumask_setall(idesc->affinity); | 842 | cpumask_setall(irq_get_irq_data(irq)->affinity); |
852 | #endif | 843 | #endif |
853 | /* Clear the interrupt information */ | 844 | /* Clear the interrupt information */ |
854 | iosapic_intr_info[irq].dest = 0; | 845 | iosapic_intr_info[irq].dest = 0; |
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c index 94ee9d067cbd..ad69606613eb 100644 --- a/arch/ia64/kernel/irq.c +++ b/arch/ia64/kernel/irq.c | |||
@@ -53,47 +53,9 @@ atomic_t irq_err_count; | |||
53 | /* | 53 | /* |
54 | * /proc/interrupts printing: | 54 | * /proc/interrupts printing: |
55 | */ | 55 | */ |
56 | 56 | int arch_show_interrupts(struct seq_file *p, int prec) | |
57 | int show_interrupts(struct seq_file *p, void *v) | ||
58 | { | 57 | { |
59 | int i = *(loff_t *) v, j; | 58 | seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); |
60 | struct irqaction * action; | ||
61 | unsigned long flags; | ||
62 | |||
63 | if (i == 0) { | ||
64 | char cpuname[16]; | ||
65 | seq_printf(p, " "); | ||
66 | for_each_online_cpu(j) { | ||
67 | snprintf(cpuname, 10, "CPU%d", j); | ||
68 | seq_printf(p, "%10s ", cpuname); | ||
69 | } | ||
70 | seq_putc(p, '\n'); | ||
71 | } | ||
72 | |||
73 | if (i < NR_IRQS) { | ||
74 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
75 | action = irq_desc[i].action; | ||
76 | if (!action) | ||
77 | goto skip; | ||
78 | seq_printf(p, "%3d: ",i); | ||
79 | #ifndef CONFIG_SMP | ||
80 | seq_printf(p, "%10u ", kstat_irqs(i)); | ||
81 | #else | ||
82 | for_each_online_cpu(j) { | ||
83 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | ||
84 | } | ||
85 | #endif | ||
86 | seq_printf(p, " %14s", irq_desc[i].chip->name); | ||
87 | seq_printf(p, " %s", action->name); | ||
88 | |||
89 | for (action=action->next; action; action = action->next) | ||
90 | seq_printf(p, ", %s", action->name); | ||
91 | |||
92 | seq_putc(p, '\n'); | ||
93 | skip: | ||
94 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
95 | } else if (i == NR_IRQS) | ||
96 | seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); | ||
97 | return 0; | 59 | return 0; |
98 | } | 60 | } |
99 | 61 | ||
@@ -103,7 +65,7 @@ static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 }; | |||
103 | void set_irq_affinity_info (unsigned int irq, int hwid, int redir) | 65 | void set_irq_affinity_info (unsigned int irq, int hwid, int redir) |
104 | { | 66 | { |
105 | if (irq < NR_IRQS) { | 67 | if (irq < NR_IRQS) { |
106 | cpumask_copy(irq_desc[irq].affinity, | 68 | cpumask_copy(irq_get_irq_data(irq)->affinity, |
107 | cpumask_of(cpu_logical_id(hwid))); | 69 | cpumask_of(cpu_logical_id(hwid))); |
108 | irq_redir[irq] = (char) (redir & 0xff); | 70 | irq_redir[irq] = (char) (redir & 0xff); |
109 | } | 71 | } |
@@ -130,13 +92,14 @@ unsigned int vectors_in_migration[NR_IRQS]; | |||
130 | */ | 92 | */ |
131 | static void migrate_irqs(void) | 93 | static void migrate_irqs(void) |
132 | { | 94 | { |
133 | struct irq_desc *desc; | ||
134 | int irq, new_cpu; | 95 | int irq, new_cpu; |
135 | 96 | ||
136 | for (irq=0; irq < NR_IRQS; irq++) { | 97 | for (irq=0; irq < NR_IRQS; irq++) { |
137 | desc = irq_desc + irq; | 98 | struct irq_desc *desc = irq_to_desc(irq); |
99 | struct irq_data *data = irq_desc_get_irq_data(desc); | ||
100 | struct irq_chip *chip = irq_data_get_irq_chip(data); | ||
138 | 101 | ||
139 | if (desc->status == IRQ_DISABLED) | 102 | if (irqd_irq_disabled(data)) |
140 | continue; | 103 | continue; |
141 | 104 | ||
142 | /* | 105 | /* |
@@ -145,10 +108,10 @@ static void migrate_irqs(void) | |||
145 | * tell CPU not to respond to these local intr sources. | 108 | * tell CPU not to respond to these local intr sources. |
146 | * such as ITV,CPEI,MCA etc. | 109 | * such as ITV,CPEI,MCA etc. |
147 | */ | 110 | */ |
148 | if (desc->status == IRQ_PER_CPU) | 111 | if (irqd_is_per_cpu(data)) |
149 | continue; | 112 | continue; |
150 | 113 | ||
151 | if (cpumask_any_and(irq_desc[irq].affinity, cpu_online_mask) | 114 | if (cpumask_any_and(data->affinity, cpu_online_mask) |
152 | >= nr_cpu_ids) { | 115 | >= nr_cpu_ids) { |
153 | /* | 116 | /* |
154 | * Save it for phase 2 processing | 117 | * Save it for phase 2 processing |
@@ -160,16 +123,16 @@ static void migrate_irqs(void) | |||
160 | /* | 123 | /* |
161 | * Al three are essential, currently WARN_ON.. maybe panic? | 124 | * Al three are essential, currently WARN_ON.. maybe panic? |
162 | */ | 125 | */ |
163 | if (desc->chip && desc->chip->disable && | 126 | if (chip && chip->irq_disable && |
164 | desc->chip->enable && desc->chip->set_affinity) { | 127 | chip->irq_enable && chip->irq_set_affinity) { |
165 | desc->chip->disable(irq); | 128 | chip->irq_disable(data); |
166 | desc->chip->set_affinity(irq, | 129 | chip->irq_set_affinity(data, |
167 | cpumask_of(new_cpu)); | 130 | cpumask_of(new_cpu), false); |
168 | desc->chip->enable(irq); | 131 | chip->irq_enable(data); |
169 | } else { | 132 | } else { |
170 | WARN_ON((!(desc->chip) || !(desc->chip->disable) || | 133 | WARN_ON((!chip || !chip->irq_disable || |
171 | !(desc->chip->enable) || | 134 | !chip->irq_enable || |
172 | !(desc->chip->set_affinity))); | 135 | !chip->irq_set_affinity)); |
173 | } | 136 | } |
174 | } | 137 | } |
175 | } | 138 | } |
diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c index 38c07b866901..5b704740f160 100644 --- a/arch/ia64/kernel/irq_ia64.c +++ b/arch/ia64/kernel/irq_ia64.c | |||
@@ -343,7 +343,7 @@ static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id) | |||
343 | if (irq < 0) | 343 | if (irq < 0) |
344 | continue; | 344 | continue; |
345 | 345 | ||
346 | desc = irq_desc + irq; | 346 | desc = irq_to_desc(irq); |
347 | cfg = irq_cfg + irq; | 347 | cfg = irq_cfg + irq; |
348 | raw_spin_lock(&desc->lock); | 348 | raw_spin_lock(&desc->lock); |
349 | if (!cfg->move_cleanup_count) | 349 | if (!cfg->move_cleanup_count) |
@@ -626,17 +626,15 @@ static struct irqaction tlb_irqaction = { | |||
626 | void | 626 | void |
627 | ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action) | 627 | ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action) |
628 | { | 628 | { |
629 | struct irq_desc *desc; | ||
630 | unsigned int irq; | 629 | unsigned int irq; |
631 | 630 | ||
632 | irq = vec; | 631 | irq = vec; |
633 | BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL)); | 632 | BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL)); |
634 | desc = irq_desc + irq; | 633 | irq_set_status_flags(irq, IRQ_PER_CPU); |
635 | desc->status |= IRQ_PER_CPU; | 634 | irq_set_chip(irq, &irq_type_ia64_lsapic); |
636 | set_irq_chip(irq, &irq_type_ia64_lsapic); | ||
637 | if (action) | 635 | if (action) |
638 | setup_irq(irq, action); | 636 | setup_irq(irq, action); |
639 | set_irq_handler(irq, handle_percpu_irq); | 637 | irq_set_handler(irq, handle_percpu_irq); |
640 | } | 638 | } |
641 | 639 | ||
642 | void __init | 640 | void __init |
diff --git a/arch/ia64/kernel/irq_lsapic.c b/arch/ia64/kernel/irq_lsapic.c index fc1549d4564d..1b3a776e5161 100644 --- a/arch/ia64/kernel/irq_lsapic.c +++ b/arch/ia64/kernel/irq_lsapic.c | |||
@@ -15,31 +15,30 @@ | |||
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | 16 | ||
17 | static unsigned int | 17 | static unsigned int |
18 | lsapic_noop_startup (unsigned int irq) | 18 | lsapic_noop_startup (struct irq_data *data) |
19 | { | 19 | { |
20 | return 0; | 20 | return 0; |
21 | } | 21 | } |
22 | 22 | ||
23 | static void | 23 | static void |
24 | lsapic_noop (unsigned int irq) | 24 | lsapic_noop (struct irq_data *data) |
25 | { | 25 | { |
26 | /* nothing to do... */ | 26 | /* nothing to do... */ |
27 | } | 27 | } |
28 | 28 | ||
29 | static int lsapic_retrigger(unsigned int irq) | 29 | static int lsapic_retrigger(struct irq_data *data) |
30 | { | 30 | { |
31 | ia64_resend_irq(irq); | 31 | ia64_resend_irq(data->irq); |
32 | 32 | ||
33 | return 1; | 33 | return 1; |
34 | } | 34 | } |
35 | 35 | ||
36 | struct irq_chip irq_type_ia64_lsapic = { | 36 | struct irq_chip irq_type_ia64_lsapic = { |
37 | .name = "LSAPIC", | 37 | .name = "LSAPIC", |
38 | .startup = lsapic_noop_startup, | 38 | .irq_startup = lsapic_noop_startup, |
39 | .shutdown = lsapic_noop, | 39 | .irq_shutdown = lsapic_noop, |
40 | .enable = lsapic_noop, | 40 | .irq_enable = lsapic_noop, |
41 | .disable = lsapic_noop, | 41 | .irq_disable = lsapic_noop, |
42 | .ack = lsapic_noop, | 42 | .irq_ack = lsapic_noop, |
43 | .end = lsapic_noop, | 43 | .irq_retrigger = lsapic_retrigger, |
44 | .retrigger = lsapic_retrigger, | ||
45 | }; | 44 | }; |
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c index 80d50b83d419..84fb405eee87 100644 --- a/arch/ia64/kernel/mca.c +++ b/arch/ia64/kernel/mca.c | |||
@@ -2125,7 +2125,6 @@ ia64_mca_late_init(void) | |||
2125 | cpe_poll_timer.function = ia64_mca_cpe_poll; | 2125 | cpe_poll_timer.function = ia64_mca_cpe_poll; |
2126 | 2126 | ||
2127 | { | 2127 | { |
2128 | struct irq_desc *desc; | ||
2129 | unsigned int irq; | 2128 | unsigned int irq; |
2130 | 2129 | ||
2131 | if (cpe_vector >= 0) { | 2130 | if (cpe_vector >= 0) { |
@@ -2133,8 +2132,7 @@ ia64_mca_late_init(void) | |||
2133 | irq = local_vector_to_irq(cpe_vector); | 2132 | irq = local_vector_to_irq(cpe_vector); |
2134 | if (irq > 0) { | 2133 | if (irq > 0) { |
2135 | cpe_poll_enabled = 0; | 2134 | cpe_poll_enabled = 0; |
2136 | desc = irq_desc + irq; | 2135 | irq_set_status_flags(irq, IRQ_PER_CPU); |
2137 | desc->status |= IRQ_PER_CPU; | ||
2138 | setup_irq(irq, &mca_cpe_irqaction); | 2136 | setup_irq(irq, &mca_cpe_irqaction); |
2139 | ia64_cpe_irq = irq; | 2137 | ia64_cpe_irq = irq; |
2140 | ia64_mca_register_cpev(cpe_vector); | 2138 | ia64_mca_register_cpev(cpe_vector); |
diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c index 00b19a416eab..009df5434a7a 100644 --- a/arch/ia64/kernel/msi_ia64.c +++ b/arch/ia64/kernel/msi_ia64.c | |||
@@ -12,12 +12,13 @@ | |||
12 | static struct irq_chip ia64_msi_chip; | 12 | static struct irq_chip ia64_msi_chip; |
13 | 13 | ||
14 | #ifdef CONFIG_SMP | 14 | #ifdef CONFIG_SMP |
15 | static int ia64_set_msi_irq_affinity(unsigned int irq, | 15 | static int ia64_set_msi_irq_affinity(struct irq_data *idata, |
16 | const cpumask_t *cpu_mask) | 16 | const cpumask_t *cpu_mask, bool force) |
17 | { | 17 | { |
18 | struct msi_msg msg; | 18 | struct msi_msg msg; |
19 | u32 addr, data; | 19 | u32 addr, data; |
20 | int cpu = first_cpu(*cpu_mask); | 20 | int cpu = first_cpu(*cpu_mask); |
21 | unsigned int irq = idata->irq; | ||
21 | 22 | ||
22 | if (!cpu_online(cpu)) | 23 | if (!cpu_online(cpu)) |
23 | return -1; | 24 | return -1; |
@@ -38,7 +39,7 @@ static int ia64_set_msi_irq_affinity(unsigned int irq, | |||
38 | msg.data = data; | 39 | msg.data = data; |
39 | 40 | ||
40 | write_msi_msg(irq, &msg); | 41 | write_msi_msg(irq, &msg); |
41 | cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); | 42 | cpumask_copy(idata->affinity, cpumask_of(cpu)); |
42 | 43 | ||
43 | return 0; | 44 | return 0; |
44 | } | 45 | } |
@@ -55,7 +56,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |||
55 | if (irq < 0) | 56 | if (irq < 0) |
56 | return irq; | 57 | return irq; |
57 | 58 | ||
58 | set_irq_msi(irq, desc); | 59 | irq_set_msi_desc(irq, desc); |
59 | cpus_and(mask, irq_to_domain(irq), cpu_online_map); | 60 | cpus_and(mask, irq_to_domain(irq), cpu_online_map); |
60 | dest_phys_id = cpu_physical_id(first_cpu(mask)); | 61 | dest_phys_id = cpu_physical_id(first_cpu(mask)); |
61 | vector = irq_to_vector(irq); | 62 | vector = irq_to_vector(irq); |
@@ -74,7 +75,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |||
74 | MSI_DATA_VECTOR(vector); | 75 | MSI_DATA_VECTOR(vector); |
75 | 76 | ||
76 | write_msi_msg(irq, &msg); | 77 | write_msi_msg(irq, &msg); |
77 | set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq); | 78 | irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq); |
78 | 79 | ||
79 | return 0; | 80 | return 0; |
80 | } | 81 | } |
@@ -84,16 +85,16 @@ void ia64_teardown_msi_irq(unsigned int irq) | |||
84 | destroy_irq(irq); | 85 | destroy_irq(irq); |
85 | } | 86 | } |
86 | 87 | ||
87 | static void ia64_ack_msi_irq(unsigned int irq) | 88 | static void ia64_ack_msi_irq(struct irq_data *data) |
88 | { | 89 | { |
89 | irq_complete_move(irq); | 90 | irq_complete_move(data->irq); |
90 | move_native_irq(irq); | 91 | irq_move_irq(data); |
91 | ia64_eoi(); | 92 | ia64_eoi(); |
92 | } | 93 | } |
93 | 94 | ||
94 | static int ia64_msi_retrigger_irq(unsigned int irq) | 95 | static int ia64_msi_retrigger_irq(struct irq_data *data) |
95 | { | 96 | { |
96 | unsigned int vector = irq_to_vector(irq); | 97 | unsigned int vector = irq_to_vector(data->irq); |
97 | ia64_resend_irq(vector); | 98 | ia64_resend_irq(vector); |
98 | 99 | ||
99 | return 1; | 100 | return 1; |
@@ -103,14 +104,14 @@ static int ia64_msi_retrigger_irq(unsigned int irq) | |||
103 | * Generic ops used on most IA64 platforms. | 104 | * Generic ops used on most IA64 platforms. |
104 | */ | 105 | */ |
105 | static struct irq_chip ia64_msi_chip = { | 106 | static struct irq_chip ia64_msi_chip = { |
106 | .name = "PCI-MSI", | 107 | .name = "PCI-MSI", |
107 | .irq_mask = mask_msi_irq, | 108 | .irq_mask = mask_msi_irq, |
108 | .irq_unmask = unmask_msi_irq, | 109 | .irq_unmask = unmask_msi_irq, |
109 | .ack = ia64_ack_msi_irq, | 110 | .irq_ack = ia64_ack_msi_irq, |
110 | #ifdef CONFIG_SMP | 111 | #ifdef CONFIG_SMP |
111 | .set_affinity = ia64_set_msi_irq_affinity, | 112 | .irq_set_affinity = ia64_set_msi_irq_affinity, |
112 | #endif | 113 | #endif |
113 | .retrigger = ia64_msi_retrigger_irq, | 114 | .irq_retrigger = ia64_msi_retrigger_irq, |
114 | }; | 115 | }; |
115 | 116 | ||
116 | 117 | ||
@@ -132,8 +133,10 @@ void arch_teardown_msi_irq(unsigned int irq) | |||
132 | 133 | ||
133 | #ifdef CONFIG_DMAR | 134 | #ifdef CONFIG_DMAR |
134 | #ifdef CONFIG_SMP | 135 | #ifdef CONFIG_SMP |
135 | static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) | 136 | static int dmar_msi_set_affinity(struct irq_data *data, |
137 | const struct cpumask *mask, bool force) | ||
136 | { | 138 | { |
139 | unsigned int irq = data->irq; | ||
137 | struct irq_cfg *cfg = irq_cfg + irq; | 140 | struct irq_cfg *cfg = irq_cfg + irq; |
138 | struct msi_msg msg; | 141 | struct msi_msg msg; |
139 | int cpu = cpumask_first(mask); | 142 | int cpu = cpumask_first(mask); |
@@ -152,7 +155,7 @@ static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) | |||
152 | msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu)); | 155 | msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu)); |
153 | 156 | ||
154 | dmar_msi_write(irq, &msg); | 157 | dmar_msi_write(irq, &msg); |
155 | cpumask_copy(irq_desc[irq].affinity, mask); | 158 | cpumask_copy(data->affinity, mask); |
156 | 159 | ||
157 | return 0; | 160 | return 0; |
158 | } | 161 | } |
@@ -162,11 +165,11 @@ static struct irq_chip dmar_msi_type = { | |||
162 | .name = "DMAR_MSI", | 165 | .name = "DMAR_MSI", |
163 | .irq_unmask = dmar_msi_unmask, | 166 | .irq_unmask = dmar_msi_unmask, |
164 | .irq_mask = dmar_msi_mask, | 167 | .irq_mask = dmar_msi_mask, |
165 | .ack = ia64_ack_msi_irq, | 168 | .irq_ack = ia64_ack_msi_irq, |
166 | #ifdef CONFIG_SMP | 169 | #ifdef CONFIG_SMP |
167 | .set_affinity = dmar_msi_set_affinity, | 170 | .irq_set_affinity = dmar_msi_set_affinity, |
168 | #endif | 171 | #endif |
169 | .retrigger = ia64_msi_retrigger_irq, | 172 | .irq_retrigger = ia64_msi_retrigger_irq, |
170 | }; | 173 | }; |
171 | 174 | ||
172 | static int | 175 | static int |
@@ -203,8 +206,8 @@ int arch_setup_dmar_msi(unsigned int irq) | |||
203 | if (ret < 0) | 206 | if (ret < 0) |
204 | return ret; | 207 | return ret; |
205 | dmar_msi_write(irq, &msg); | 208 | dmar_msi_write(irq, &msg); |
206 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | 209 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
207 | "edge"); | 210 | "edge"); |
208 | return 0; | 211 | return 0; |
209 | } | 212 | } |
210 | #endif /* CONFIG_DMAR */ | 213 | #endif /* CONFIG_DMAR */ |
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c index d003b502a432..44f11ee411c0 100644 --- a/arch/ia64/kernel/smpboot.c +++ b/arch/ia64/kernel/smpboot.c | |||
@@ -677,7 +677,7 @@ extern void fixup_irqs(void); | |||
677 | int migrate_platform_irqs(unsigned int cpu) | 677 | int migrate_platform_irqs(unsigned int cpu) |
678 | { | 678 | { |
679 | int new_cpei_cpu; | 679 | int new_cpei_cpu; |
680 | struct irq_desc *desc = NULL; | 680 | struct irq_data *data = NULL; |
681 | const struct cpumask *mask; | 681 | const struct cpumask *mask; |
682 | int retval = 0; | 682 | int retval = 0; |
683 | 683 | ||
@@ -693,20 +693,20 @@ int migrate_platform_irqs(unsigned int cpu) | |||
693 | new_cpei_cpu = any_online_cpu(cpu_online_map); | 693 | new_cpei_cpu = any_online_cpu(cpu_online_map); |
694 | mask = cpumask_of(new_cpei_cpu); | 694 | mask = cpumask_of(new_cpei_cpu); |
695 | set_cpei_target_cpu(new_cpei_cpu); | 695 | set_cpei_target_cpu(new_cpei_cpu); |
696 | desc = irq_desc + ia64_cpe_irq; | 696 | data = irq_get_irq_data(ia64_cpe_irq); |
697 | /* | 697 | /* |
698 | * Switch for now, immediately, we need to do fake intr | 698 | * Switch for now, immediately, we need to do fake intr |
699 | * as other interrupts, but need to study CPEI behaviour with | 699 | * as other interrupts, but need to study CPEI behaviour with |
700 | * polling before making changes. | 700 | * polling before making changes. |
701 | */ | 701 | */ |
702 | if (desc) { | 702 | if (data && data->chip) { |
703 | desc->chip->disable(ia64_cpe_irq); | 703 | data->chip->irq_disable(data); |
704 | desc->chip->set_affinity(ia64_cpe_irq, mask); | 704 | data->chip->irq_set_affinity(data, mask, false); |
705 | desc->chip->enable(ia64_cpe_irq); | 705 | data->chip->irq_enable(data); |
706 | printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu); | 706 | printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu); |
707 | } | 707 | } |
708 | } | 708 | } |
709 | if (!desc) { | 709 | if (!data) { |
710 | printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu); | 710 | printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu); |
711 | retval = -EBUSY; | 711 | retval = -EBUSY; |
712 | } | 712 | } |
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c index 13c15d968098..139c018dbbf9 100644 --- a/arch/ia64/sn/kernel/irq.c +++ b/arch/ia64/sn/kernel/irq.c | |||
@@ -23,11 +23,9 @@ | |||
23 | #include <asm/sn/sn_sal.h> | 23 | #include <asm/sn/sn_sal.h> |
24 | #include <asm/sn/sn_feature_sets.h> | 24 | #include <asm/sn/sn_feature_sets.h> |
25 | 25 | ||
26 | static void force_interrupt(int irq); | ||
27 | static void register_intr_pda(struct sn_irq_info *sn_irq_info); | 26 | static void register_intr_pda(struct sn_irq_info *sn_irq_info); |
28 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info); | 27 | static void unregister_intr_pda(struct sn_irq_info *sn_irq_info); |
29 | 28 | ||
30 | int sn_force_interrupt_flag = 1; | ||
31 | extern int sn_ioif_inited; | 29 | extern int sn_ioif_inited; |
32 | struct list_head **sn_irq_lh; | 30 | struct list_head **sn_irq_lh; |
33 | static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */ | 31 | static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */ |
@@ -78,62 +76,40 @@ u64 sn_intr_redirect(nasid_t local_nasid, int local_widget, | |||
78 | return ret_stuff.status; | 76 | return ret_stuff.status; |
79 | } | 77 | } |
80 | 78 | ||
81 | static unsigned int sn_startup_irq(unsigned int irq) | 79 | static unsigned int sn_startup_irq(struct irq_data *data) |
82 | { | 80 | { |
83 | return 0; | 81 | return 0; |
84 | } | 82 | } |
85 | 83 | ||
86 | static void sn_shutdown_irq(unsigned int irq) | 84 | static void sn_shutdown_irq(struct irq_data *data) |
87 | { | 85 | { |
88 | } | 86 | } |
89 | 87 | ||
90 | extern void ia64_mca_register_cpev(int); | 88 | extern void ia64_mca_register_cpev(int); |
91 | 89 | ||
92 | static void sn_disable_irq(unsigned int irq) | 90 | static void sn_disable_irq(struct irq_data *data) |
93 | { | 91 | { |
94 | if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) | 92 | if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR)) |
95 | ia64_mca_register_cpev(0); | 93 | ia64_mca_register_cpev(0); |
96 | } | 94 | } |
97 | 95 | ||
98 | static void sn_enable_irq(unsigned int irq) | 96 | static void sn_enable_irq(struct irq_data *data) |
99 | { | 97 | { |
100 | if (irq == local_vector_to_irq(IA64_CPE_VECTOR)) | 98 | if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR)) |
101 | ia64_mca_register_cpev(irq); | 99 | ia64_mca_register_cpev(data->irq); |
102 | } | 100 | } |
103 | 101 | ||
104 | static void sn_ack_irq(unsigned int irq) | 102 | static void sn_ack_irq(struct irq_data *data) |
105 | { | 103 | { |
106 | u64 event_occurred, mask; | 104 | u64 event_occurred, mask; |
105 | unsigned int irq = data->irq & 0xff; | ||
107 | 106 | ||
108 | irq = irq & 0xff; | ||
109 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)); | 107 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED)); |
110 | mask = event_occurred & SH_ALL_INT_MASK; | 108 | mask = event_occurred & SH_ALL_INT_MASK; |
111 | HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask); | 109 | HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask); |
112 | __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs); | 110 | __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs); |
113 | 111 | ||
114 | move_native_irq(irq); | 112 | irq_move_irq(data); |
115 | } | ||
116 | |||
117 | static void sn_end_irq(unsigned int irq) | ||
118 | { | ||
119 | int ivec; | ||
120 | u64 event_occurred; | ||
121 | |||
122 | ivec = irq & 0xff; | ||
123 | if (ivec == SGI_UART_VECTOR) { | ||
124 | event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED)); | ||
125 | /* If the UART bit is set here, we may have received an | ||
126 | * interrupt from the UART that the driver missed. To | ||
127 | * make sure, we IPI ourselves to force us to look again. | ||
128 | */ | ||
129 | if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) { | ||
130 | platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, | ||
131 | IA64_IPI_DM_INT, 0); | ||
132 | } | ||
133 | } | ||
134 | __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs); | ||
135 | if (sn_force_interrupt_flag) | ||
136 | force_interrupt(irq); | ||
137 | } | 113 | } |
138 | 114 | ||
139 | static void sn_irq_info_free(struct rcu_head *head); | 115 | static void sn_irq_info_free(struct rcu_head *head); |
@@ -228,9 +204,11 @@ finish_up: | |||
228 | return new_irq_info; | 204 | return new_irq_info; |
229 | } | 205 | } |
230 | 206 | ||
231 | static int sn_set_affinity_irq(unsigned int irq, const struct cpumask *mask) | 207 | static int sn_set_affinity_irq(struct irq_data *data, |
208 | const struct cpumask *mask, bool force) | ||
232 | { | 209 | { |
233 | struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; | 210 | struct sn_irq_info *sn_irq_info, *sn_irq_info_safe; |
211 | unsigned int irq = data->irq; | ||
234 | nasid_t nasid; | 212 | nasid_t nasid; |
235 | int slice; | 213 | int slice; |
236 | 214 | ||
@@ -259,26 +237,25 @@ void sn_set_err_irq_affinity(unsigned int irq) { } | |||
259 | #endif | 237 | #endif |
260 | 238 | ||
261 | static void | 239 | static void |
262 | sn_mask_irq(unsigned int irq) | 240 | sn_mask_irq(struct irq_data *data) |
263 | { | 241 | { |
264 | } | 242 | } |
265 | 243 | ||
266 | static void | 244 | static void |
267 | sn_unmask_irq(unsigned int irq) | 245 | sn_unmask_irq(struct irq_data *data) |
268 | { | 246 | { |
269 | } | 247 | } |
270 | 248 | ||
271 | struct irq_chip irq_type_sn = { | 249 | struct irq_chip irq_type_sn = { |
272 | .name = "SN hub", | 250 | .name = "SN hub", |
273 | .startup = sn_startup_irq, | 251 | .irq_startup = sn_startup_irq, |
274 | .shutdown = sn_shutdown_irq, | 252 | .irq_shutdown = sn_shutdown_irq, |
275 | .enable = sn_enable_irq, | 253 | .irq_enable = sn_enable_irq, |
276 | .disable = sn_disable_irq, | 254 | .irq_disable = sn_disable_irq, |
277 | .ack = sn_ack_irq, | 255 | .irq_ack = sn_ack_irq, |
278 | .end = sn_end_irq, | 256 | .irq_mask = sn_mask_irq, |
279 | .mask = sn_mask_irq, | 257 | .irq_unmask = sn_unmask_irq, |
280 | .unmask = sn_unmask_irq, | 258 | .irq_set_affinity = sn_set_affinity_irq |
281 | .set_affinity = sn_set_affinity_irq | ||
282 | }; | 259 | }; |
283 | 260 | ||
284 | ia64_vector sn_irq_to_vector(int irq) | 261 | ia64_vector sn_irq_to_vector(int irq) |
@@ -296,15 +273,13 @@ unsigned int sn_local_vector_to_irq(u8 vector) | |||
296 | void sn_irq_init(void) | 273 | void sn_irq_init(void) |
297 | { | 274 | { |
298 | int i; | 275 | int i; |
299 | struct irq_desc *base_desc = irq_desc; | ||
300 | 276 | ||
301 | ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR; | 277 | ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR; |
302 | ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; | 278 | ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR; |
303 | 279 | ||
304 | for (i = 0; i < NR_IRQS; i++) { | 280 | for (i = 0; i < NR_IRQS; i++) { |
305 | if (base_desc[i].chip == &no_irq_chip) { | 281 | if (irq_get_chip(i) == &no_irq_chip) |
306 | base_desc[i].chip = &irq_type_sn; | 282 | irq_set_chip(i, &irq_type_sn); |
307 | } | ||
308 | } | 283 | } |
309 | } | 284 | } |
310 | 285 | ||
@@ -378,7 +353,6 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) | |||
378 | int cpu = nasid_slice_to_cpuid(nasid, slice); | 353 | int cpu = nasid_slice_to_cpuid(nasid, slice); |
379 | #ifdef CONFIG_SMP | 354 | #ifdef CONFIG_SMP |
380 | int cpuphys; | 355 | int cpuphys; |
381 | struct irq_desc *desc; | ||
382 | #endif | 356 | #endif |
383 | 357 | ||
384 | pci_dev_get(pci_dev); | 358 | pci_dev_get(pci_dev); |
@@ -395,12 +369,11 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info) | |||
395 | #ifdef CONFIG_SMP | 369 | #ifdef CONFIG_SMP |
396 | cpuphys = cpu_physical_id(cpu); | 370 | cpuphys = cpu_physical_id(cpu); |
397 | set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0); | 371 | set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0); |
398 | desc = irq_to_desc(sn_irq_info->irq_irq); | ||
399 | /* | 372 | /* |
400 | * Affinity was set by the PROM, prevent it from | 373 | * Affinity was set by the PROM, prevent it from |
401 | * being reset by the request_irq() path. | 374 | * being reset by the request_irq() path. |
402 | */ | 375 | */ |
403 | desc->status |= IRQ_AFFINITY_SET; | 376 | irqd_mark_affinity_was_set(irq_get_irq_data(sn_irq_info->irq_irq)); |
404 | #endif | 377 | #endif |
405 | } | 378 | } |
406 | 379 | ||
@@ -439,25 +412,11 @@ sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info) | |||
439 | pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type]; | 412 | pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type]; |
440 | 413 | ||
441 | /* Don't force an interrupt if the irq has been disabled */ | 414 | /* Don't force an interrupt if the irq has been disabled */ |
442 | if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) && | 415 | if (!irqd_irq_disabled(irq_get_irq_data(sn_irq_info->irq_irq)) && |
443 | pci_provider && pci_provider->force_interrupt) | 416 | pci_provider && pci_provider->force_interrupt) |
444 | (*pci_provider->force_interrupt)(sn_irq_info); | 417 | (*pci_provider->force_interrupt)(sn_irq_info); |
445 | } | 418 | } |
446 | 419 | ||
447 | static void force_interrupt(int irq) | ||
448 | { | ||
449 | struct sn_irq_info *sn_irq_info; | ||
450 | |||
451 | if (!sn_ioif_inited) | ||
452 | return; | ||
453 | |||
454 | rcu_read_lock(); | ||
455 | list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list) | ||
456 | sn_call_force_intr_provider(sn_irq_info); | ||
457 | |||
458 | rcu_read_unlock(); | ||
459 | } | ||
460 | |||
461 | /* | 420 | /* |
462 | * Check for lost interrupts. If the PIC int_status reg. says that | 421 | * Check for lost interrupts. If the PIC int_status reg. says that |
463 | * an interrupt has been sent, but not handled, and the interrupt | 422 | * an interrupt has been sent, but not handled, and the interrupt |
diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c index a5e500f02853..2b98b9e088de 100644 --- a/arch/ia64/sn/kernel/msi_sn.c +++ b/arch/ia64/sn/kernel/msi_sn.c | |||
@@ -144,16 +144,16 @@ int sn_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *entry) | |||
144 | */ | 144 | */ |
145 | msg.data = 0x100 + irq; | 145 | msg.data = 0x100 + irq; |
146 | 146 | ||
147 | set_irq_msi(irq, entry); | 147 | irq_set_msi_desc(irq, entry); |
148 | write_msi_msg(irq, &msg); | 148 | write_msi_msg(irq, &msg); |
149 | set_irq_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq); | 149 | irq_set_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq); |
150 | 150 | ||
151 | return 0; | 151 | return 0; |
152 | } | 152 | } |
153 | 153 | ||
154 | #ifdef CONFIG_SMP | 154 | #ifdef CONFIG_SMP |
155 | static int sn_set_msi_irq_affinity(unsigned int irq, | 155 | static int sn_set_msi_irq_affinity(struct irq_data *data, |
156 | const struct cpumask *cpu_mask) | 156 | const struct cpumask *cpu_mask, bool force) |
157 | { | 157 | { |
158 | struct msi_msg msg; | 158 | struct msi_msg msg; |
159 | int slice; | 159 | int slice; |
@@ -164,7 +164,7 @@ static int sn_set_msi_irq_affinity(unsigned int irq, | |||
164 | struct sn_irq_info *sn_irq_info; | 164 | struct sn_irq_info *sn_irq_info; |
165 | struct sn_irq_info *new_irq_info; | 165 | struct sn_irq_info *new_irq_info; |
166 | struct sn_pcibus_provider *provider; | 166 | struct sn_pcibus_provider *provider; |
167 | unsigned int cpu; | 167 | unsigned int cpu, irq = data->irq; |
168 | 168 | ||
169 | cpu = cpumask_first(cpu_mask); | 169 | cpu = cpumask_first(cpu_mask); |
170 | sn_irq_info = sn_msi_info[irq].sn_irq_info; | 170 | sn_irq_info = sn_msi_info[irq].sn_irq_info; |
@@ -206,33 +206,33 @@ static int sn_set_msi_irq_affinity(unsigned int irq, | |||
206 | msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff); | 206 | msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff); |
207 | 207 | ||
208 | write_msi_msg(irq, &msg); | 208 | write_msi_msg(irq, &msg); |
209 | cpumask_copy(irq_desc[irq].affinity, cpu_mask); | 209 | cpumask_copy(data->affinity, cpu_mask); |
210 | 210 | ||
211 | return 0; | 211 | return 0; |
212 | } | 212 | } |
213 | #endif /* CONFIG_SMP */ | 213 | #endif /* CONFIG_SMP */ |
214 | 214 | ||
215 | static void sn_ack_msi_irq(unsigned int irq) | 215 | static void sn_ack_msi_irq(struct irq_data *data) |
216 | { | 216 | { |
217 | move_native_irq(irq); | 217 | irq_move_irq(data); |
218 | ia64_eoi(); | 218 | ia64_eoi(); |
219 | } | 219 | } |
220 | 220 | ||
221 | static int sn_msi_retrigger_irq(unsigned int irq) | 221 | static int sn_msi_retrigger_irq(struct irq_data *data) |
222 | { | 222 | { |
223 | unsigned int vector = irq; | 223 | unsigned int vector = data->irq; |
224 | ia64_resend_irq(vector); | 224 | ia64_resend_irq(vector); |
225 | 225 | ||
226 | return 1; | 226 | return 1; |
227 | } | 227 | } |
228 | 228 | ||
229 | static struct irq_chip sn_msi_chip = { | 229 | static struct irq_chip sn_msi_chip = { |
230 | .name = "PCI-MSI", | 230 | .name = "PCI-MSI", |
231 | .irq_mask = mask_msi_irq, | 231 | .irq_mask = mask_msi_irq, |
232 | .irq_unmask = unmask_msi_irq, | 232 | .irq_unmask = unmask_msi_irq, |
233 | .ack = sn_ack_msi_irq, | 233 | .irq_ack = sn_ack_msi_irq, |
234 | #ifdef CONFIG_SMP | 234 | #ifdef CONFIG_SMP |
235 | .set_affinity = sn_set_msi_irq_affinity, | 235 | .irq_set_affinity = sn_set_msi_irq_affinity, |
236 | #endif | 236 | #endif |
237 | .retrigger = sn_msi_retrigger_irq, | 237 | .irq_retrigger = sn_msi_retrigger_irq, |
238 | }; | 238 | }; |
diff --git a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c index c76d8dc3aea3..7aab87f48060 100644 --- a/arch/ia64/sn/kernel/sn2/sn_proc_fs.c +++ b/arch/ia64/sn/kernel/sn2/sn_proc_fs.c | |||
@@ -45,38 +45,6 @@ static int licenseID_open(struct inode *inode, struct file *file) | |||
45 | return single_open(file, licenseID_show, NULL); | 45 | return single_open(file, licenseID_show, NULL); |
46 | } | 46 | } |
47 | 47 | ||
48 | /* | ||
49 | * Enable forced interrupt by default. | ||
50 | * When set, the sn interrupt handler writes the force interrupt register on | ||
51 | * the bridge chip. The hardware will then send an interrupt message if the | ||
52 | * interrupt line is active. This mimics a level sensitive interrupt. | ||
53 | */ | ||
54 | extern int sn_force_interrupt_flag; | ||
55 | |||
56 | static int sn_force_interrupt_show(struct seq_file *s, void *p) | ||
57 | { | ||
58 | seq_printf(s, "Force interrupt is %s\n", | ||
59 | sn_force_interrupt_flag ? "enabled" : "disabled"); | ||
60 | return 0; | ||
61 | } | ||
62 | |||
63 | static ssize_t sn_force_interrupt_write_proc(struct file *file, | ||
64 | const char __user *buffer, size_t count, loff_t *data) | ||
65 | { | ||
66 | char val; | ||
67 | |||
68 | if (copy_from_user(&val, buffer, 1)) | ||
69 | return -EFAULT; | ||
70 | |||
71 | sn_force_interrupt_flag = (val == '0') ? 0 : 1; | ||
72 | return count; | ||
73 | } | ||
74 | |||
75 | static int sn_force_interrupt_open(struct inode *inode, struct file *file) | ||
76 | { | ||
77 | return single_open(file, sn_force_interrupt_show, NULL); | ||
78 | } | ||
79 | |||
80 | static int coherence_id_show(struct seq_file *s, void *p) | 48 | static int coherence_id_show(struct seq_file *s, void *p) |
81 | { | 49 | { |
82 | seq_printf(s, "%d\n", partition_coherence_id()); | 50 | seq_printf(s, "%d\n", partition_coherence_id()); |
@@ -114,14 +82,6 @@ static const struct file_operations proc_license_id_fops = { | |||
114 | .release = single_release, | 82 | .release = single_release, |
115 | }; | 83 | }; |
116 | 84 | ||
117 | static const struct file_operations proc_sn_force_intr_fops = { | ||
118 | .open = sn_force_interrupt_open, | ||
119 | .read = seq_read, | ||
120 | .write = sn_force_interrupt_write_proc, | ||
121 | .llseek = seq_lseek, | ||
122 | .release = single_release, | ||
123 | }; | ||
124 | |||
125 | static const struct file_operations proc_coherence_id_fops = { | 85 | static const struct file_operations proc_coherence_id_fops = { |
126 | .open = coherence_id_open, | 86 | .open = coherence_id_open, |
127 | .read = seq_read, | 87 | .read = seq_read, |
@@ -149,8 +109,6 @@ void register_sn_procfs(void) | |||
149 | proc_create("system_serial_number", 0444, sgi_proc_dir, | 109 | proc_create("system_serial_number", 0444, sgi_proc_dir, |
150 | &proc_system_sn_fops); | 110 | &proc_system_sn_fops); |
151 | proc_create("licenseID", 0444, sgi_proc_dir, &proc_license_id_fops); | 111 | proc_create("licenseID", 0444, sgi_proc_dir, &proc_license_id_fops); |
152 | proc_create("sn_force_interrupt", 0644, sgi_proc_dir, | ||
153 | &proc_sn_force_intr_fops); | ||
154 | proc_create("coherence_id", 0444, sgi_proc_dir, | 112 | proc_create("coherence_id", 0444, sgi_proc_dir, |
155 | &proc_coherence_id_fops); | 113 | &proc_coherence_id_fops); |
156 | proc_create("sn_topology", 0444, sgi_proc_dir, &proc_sn_topo_fops); | 114 | proc_create("sn_topology", 0444, sgi_proc_dir, &proc_sn_topo_fops); |
diff --git a/arch/ia64/xen/irq_xen.c b/arch/ia64/xen/irq_xen.c index a3fb7cf9ae1d..108bb858acf2 100644 --- a/arch/ia64/xen/irq_xen.c +++ b/arch/ia64/xen/irq_xen.c | |||
@@ -138,7 +138,6 @@ static void | |||
138 | __xen_register_percpu_irq(unsigned int cpu, unsigned int vec, | 138 | __xen_register_percpu_irq(unsigned int cpu, unsigned int vec, |
139 | struct irqaction *action, int save) | 139 | struct irqaction *action, int save) |
140 | { | 140 | { |
141 | struct irq_desc *desc; | ||
142 | int irq = 0; | 141 | int irq = 0; |
143 | 142 | ||
144 | if (xen_slab_ready) { | 143 | if (xen_slab_ready) { |
@@ -223,8 +222,7 @@ __xen_register_percpu_irq(unsigned int cpu, unsigned int vec, | |||
223 | * mark the interrupt for migrations and trigger it | 222 | * mark the interrupt for migrations and trigger it |
224 | * on cpu hotplug. | 223 | * on cpu hotplug. |
225 | */ | 224 | */ |
226 | desc = irq_desc + irq; | 225 | irq_set_status_flags(irq, IRQ_PER_CPU); |
227 | desc->status |= IRQ_PER_CPU; | ||
228 | } | 226 | } |
229 | } | 227 | } |
230 | 228 | ||
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig index b28d0908a402..736b808d2291 100644 --- a/arch/m32r/Kconfig +++ b/arch/m32r/Kconfig | |||
@@ -8,7 +8,6 @@ config M32R | |||
8 | select HAVE_KERNEL_BZIP2 | 8 | select HAVE_KERNEL_BZIP2 |
9 | select HAVE_KERNEL_LZMA | 9 | select HAVE_KERNEL_LZMA |
10 | select HAVE_GENERIC_HARDIRQS | 10 | select HAVE_GENERIC_HARDIRQS |
11 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
12 | select GENERIC_IRQ_PROBE | 11 | select GENERIC_IRQ_PROBE |
13 | select GENERIC_IRQ_SHOW | 12 | select GENERIC_IRQ_SHOW |
14 | 13 | ||
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 6e056d3c5d01..75531da02a40 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig | |||
@@ -5,7 +5,6 @@ config M68K | |||
5 | select HAVE_AOUT if MMU | 5 | select HAVE_AOUT if MMU |
6 | select GENERIC_ATOMIC64 if MMU | 6 | select GENERIC_ATOMIC64 if MMU |
7 | select HAVE_GENERIC_HARDIRQS if !MMU | 7 | select HAVE_GENERIC_HARDIRQS if !MMU |
8 | select GENERIC_HARDIRQS_NO_DEPRECATED if !MMU | ||
9 | 8 | ||
10 | config RWSEM_GENERIC_SPINLOCK | 9 | config RWSEM_GENERIC_SPINLOCK |
11 | bool | 10 | bool |
diff --git a/arch/m68k/kernel/irq.c b/arch/m68k/kernel/irq.c index c7dd48f37bee..15dbc3e9d20c 100644 --- a/arch/m68k/kernel/irq.c +++ b/arch/m68k/kernel/irq.c | |||
@@ -44,7 +44,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
44 | if (ap) { | 44 | if (ap) { |
45 | seq_printf(p, "%3d: ", irq); | 45 | seq_printf(p, "%3d: ", irq); |
46 | seq_printf(p, "%10u ", kstat_irqs(irq)); | 46 | seq_printf(p, "%10u ", kstat_irqs(irq)); |
47 | seq_printf(p, "%14s ", get_irq_desc_chip(desc)->name); | 47 | seq_printf(p, "%14s ", irq_desc_get_chip(desc)->name); |
48 | 48 | ||
49 | seq_printf(p, "%s", ap->name); | 49 | seq_printf(p, "%s", ap->name); |
50 | for (ap = ap->next; ap; ap = ap->next) | 50 | for (ap = ap->next; ap; ap = ap->next) |
diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/5249/intc2.c index 8f4b63e17366..f343bf7bf5b0 100644 --- a/arch/m68k/platform/5249/intc2.c +++ b/arch/m68k/platform/5249/intc2.c | |||
@@ -51,8 +51,8 @@ static int __init mcf_intc2_init(void) | |||
51 | 51 | ||
52 | /* GPIO interrupt sources */ | 52 | /* GPIO interrupt sources */ |
53 | for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { | 53 | for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) { |
54 | set_irq_chip(irq, &intc2_irq_gpio_chip); | 54 | irq_set_chip(irq, &intc2_irq_gpio_chip); |
55 | set_irq_handler(irq, handle_edge_irq); | 55 | irq_set_handler(irq, handle_edge_irq); |
56 | } | 56 | } |
57 | 57 | ||
58 | return 0; | 58 | return 0; |
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/5272/intc.c index 969ff0a467c6..43e6e96f087f 100644 --- a/arch/m68k/platform/5272/intc.c +++ b/arch/m68k/platform/5272/intc.c | |||
@@ -145,7 +145,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type) | |||
145 | */ | 145 | */ |
146 | static void intc_external_irq(unsigned int irq, struct irq_desc *desc) | 146 | static void intc_external_irq(unsigned int irq, struct irq_desc *desc) |
147 | { | 147 | { |
148 | get_irq_desc_chip(desc)->irq_ack(&desc->irq_data); | 148 | irq_desc_get_chip(desc)->irq_ack(&desc->irq_data); |
149 | handle_simple_irq(irq, desc); | 149 | handle_simple_irq(irq, desc); |
150 | } | 150 | } |
151 | 151 | ||
@@ -171,16 +171,16 @@ void __init init_IRQ(void) | |||
171 | writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); | 171 | writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); |
172 | 172 | ||
173 | for (irq = 0; (irq < NR_IRQS); irq++) { | 173 | for (irq = 0; (irq < NR_IRQS); irq++) { |
174 | set_irq_chip(irq, &intc_irq_chip); | 174 | irq_set_chip(irq, &intc_irq_chip); |
175 | edge = 0; | 175 | edge = 0; |
176 | if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) | 176 | if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) |
177 | edge = intc_irqmap[irq - MCFINT_VECBASE].ack; | 177 | edge = intc_irqmap[irq - MCFINT_VECBASE].ack; |
178 | if (edge) { | 178 | if (edge) { |
179 | set_irq_type(irq, IRQ_TYPE_EDGE_RISING); | 179 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
180 | set_irq_handler(irq, intc_external_irq); | 180 | irq_set_handler(irq, intc_external_irq); |
181 | } else { | 181 | } else { |
182 | set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); | 182 | irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); |
183 | set_irq_handler(irq, handle_level_irq); | 183 | irq_set_handler(irq, handle_level_irq); |
184 | } | 184 | } |
185 | } | 185 | } |
186 | } | 186 | } |
diff --git a/arch/m68k/platform/68328/ints.c b/arch/m68k/platform/68328/ints.c index e5631831a200..a90288cf7446 100644 --- a/arch/m68k/platform/68328/ints.c +++ b/arch/m68k/platform/68328/ints.c | |||
@@ -179,8 +179,8 @@ void __init init_IRQ(void) | |||
179 | IMR = ~0; | 179 | IMR = ~0; |
180 | 180 | ||
181 | for (i = 0; (i < NR_IRQS); i++) { | 181 | for (i = 0; (i < NR_IRQS); i++) { |
182 | set_irq_chip(i, &intc_irq_chip); | 182 | irq_set_chip(i, &intc_irq_chip); |
183 | set_irq_handler(i, handle_level_irq); | 183 | irq_set_handler(i, handle_level_irq); |
184 | } | 184 | } |
185 | } | 185 | } |
186 | 186 | ||
diff --git a/arch/m68k/platform/68360/ints.c b/arch/m68k/platform/68360/ints.c index 8de3feb568c6..4af0f4e30f74 100644 --- a/arch/m68k/platform/68360/ints.c +++ b/arch/m68k/platform/68360/ints.c | |||
@@ -132,8 +132,8 @@ void init_IRQ(void) | |||
132 | pquicc->intr_cimr = 0x00000000; | 132 | pquicc->intr_cimr = 0x00000000; |
133 | 133 | ||
134 | for (i = 0; (i < NR_IRQS); i++) { | 134 | for (i = 0; (i < NR_IRQS); i++) { |
135 | set_irq_chip(i, &intc_irq_chip); | 135 | irq_set_chip(i, &intc_irq_chip); |
136 | set_irq_handler(i, handle_level_irq); | 136 | irq_set_handler(i, handle_level_irq); |
137 | } | 137 | } |
138 | } | 138 | } |
139 | 139 | ||
diff --git a/arch/m68k/platform/coldfire/intc-2.c b/arch/m68k/platform/coldfire/intc-2.c index 2cbfbf035db9..74b55cfbc3cb 100644 --- a/arch/m68k/platform/coldfire/intc-2.c +++ b/arch/m68k/platform/coldfire/intc-2.c | |||
@@ -164,7 +164,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type) | |||
164 | } | 164 | } |
165 | 165 | ||
166 | if (tb) | 166 | if (tb) |
167 | set_irq_handler(irq, handle_edge_irq); | 167 | irq_set_handler(irq, handle_edge_irq); |
168 | 168 | ||
169 | irq -= EINT0; | 169 | irq -= EINT0; |
170 | pa = __raw_readw(MCFEPORT_EPPAR); | 170 | pa = __raw_readw(MCFEPORT_EPPAR); |
@@ -204,11 +204,11 @@ void __init init_IRQ(void) | |||
204 | 204 | ||
205 | for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { | 205 | for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) { |
206 | if ((irq >= EINT1) && (irq <=EINT7)) | 206 | if ((irq >= EINT1) && (irq <=EINT7)) |
207 | set_irq_chip(irq, &intc_irq_chip_edge_port); | 207 | irq_set_chip(irq, &intc_irq_chip_edge_port); |
208 | else | 208 | else |
209 | set_irq_chip(irq, &intc_irq_chip); | 209 | irq_set_chip(irq, &intc_irq_chip); |
210 | set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); | 210 | irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); |
211 | set_irq_handler(irq, handle_level_irq); | 211 | irq_set_handler(irq, handle_level_irq); |
212 | } | 212 | } |
213 | } | 213 | } |
214 | 214 | ||
diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c index e642b24ab729..d6a4d9d53e42 100644 --- a/arch/m68k/platform/coldfire/intc-simr.c +++ b/arch/m68k/platform/coldfire/intc-simr.c | |||
@@ -141,7 +141,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type) | |||
141 | } | 141 | } |
142 | 142 | ||
143 | if (tb) | 143 | if (tb) |
144 | set_irq_handler(irq, handle_edge_irq); | 144 | irq_set_handler(irq, handle_edge_irq); |
145 | 145 | ||
146 | ebit = irq2ebit(irq) * 2; | 146 | ebit = irq2ebit(irq) * 2; |
147 | pa = __raw_readw(MCFEPORT_EPPAR); | 147 | pa = __raw_readw(MCFEPORT_EPPAR); |
@@ -181,11 +181,11 @@ void __init init_IRQ(void) | |||
181 | eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); | 181 | eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0); |
182 | for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { | 182 | for (irq = MCFINT_VECBASE; (irq < eirq); irq++) { |
183 | if ((irq >= EINT1) && (irq <= EINT7)) | 183 | if ((irq >= EINT1) && (irq <= EINT7)) |
184 | set_irq_chip(irq, &intc_irq_chip_edge_port); | 184 | irq_set_chip(irq, &intc_irq_chip_edge_port); |
185 | else | 185 | else |
186 | set_irq_chip(irq, &intc_irq_chip); | 186 | irq_set_chip(irq, &intc_irq_chip); |
187 | set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); | 187 | irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); |
188 | set_irq_handler(irq, handle_level_irq); | 188 | irq_set_handler(irq, handle_level_irq); |
189 | } | 189 | } |
190 | } | 190 | } |
191 | 191 | ||
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c index d648081a63f6..c28a6ed6cb23 100644 --- a/arch/m68k/platform/coldfire/intc.c +++ b/arch/m68k/platform/coldfire/intc.c | |||
@@ -143,9 +143,9 @@ void __init init_IRQ(void) | |||
143 | mcf_maskimr(0xffffffff); | 143 | mcf_maskimr(0xffffffff); |
144 | 144 | ||
145 | for (irq = 0; (irq < NR_IRQS); irq++) { | 145 | for (irq = 0; (irq < NR_IRQS); irq++) { |
146 | set_irq_chip(irq, &intc_irq_chip); | 146 | irq_set_chip(irq, &intc_irq_chip); |
147 | set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); | 147 | irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); |
148 | set_irq_handler(irq, handle_level_irq); | 148 | irq_set_handler(irq, handle_level_irq); |
149 | } | 149 | } |
150 | } | 150 | } |
151 | 151 | ||
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 5f0cf0e32653..851b3bf6e962 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig | |||
@@ -17,7 +17,7 @@ config MICROBLAZE | |||
17 | select OF_EARLY_FLATTREE | 17 | select OF_EARLY_FLATTREE |
18 | select HAVE_GENERIC_HARDIRQS | 18 | select HAVE_GENERIC_HARDIRQS |
19 | select GENERIC_IRQ_PROBE | 19 | select GENERIC_IRQ_PROBE |
20 | select GENERIC_HARDIRQS_NO_DEPRECATED | 20 | select GENERIC_IRQ_SHOW |
21 | 21 | ||
22 | config SWAP | 22 | config SWAP |
23 | def_bool n | 23 | def_bool n |
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c index e4661285118e..5ba7e162833b 100644 --- a/arch/microblaze/kernel/intc.c +++ b/arch/microblaze/kernel/intc.c | |||
@@ -50,7 +50,7 @@ static void intc_enable_or_unmask(struct irq_data *d) | |||
50 | * ack function since the handle_level_irq function | 50 | * ack function since the handle_level_irq function |
51 | * acks the irq before calling the interrupt handler | 51 | * acks the irq before calling the interrupt handler |
52 | */ | 52 | */ |
53 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) | 53 | if (irqd_is_level_type(d)) |
54 | out_be32(INTC_BASE + IAR, mask); | 54 | out_be32(INTC_BASE + IAR, mask); |
55 | } | 55 | } |
56 | 56 | ||
@@ -157,11 +157,11 @@ void __init init_IRQ(void) | |||
157 | 157 | ||
158 | for (i = 0; i < nr_irq; ++i) { | 158 | for (i = 0; i < nr_irq; ++i) { |
159 | if (intr_type & (0x00000001 << i)) { | 159 | if (intr_type & (0x00000001 << i)) { |
160 | set_irq_chip_and_handler_name(i, &intc_dev, | 160 | irq_set_chip_and_handler_name(i, &intc_dev, |
161 | handle_edge_irq, intc_dev.name); | 161 | handle_edge_irq, intc_dev.name); |
162 | irq_clear_status_flags(i, IRQ_LEVEL); | 162 | irq_clear_status_flags(i, IRQ_LEVEL); |
163 | } else { | 163 | } else { |
164 | set_irq_chip_and_handler_name(i, &intc_dev, | 164 | irq_set_chip_and_handler_name(i, &intc_dev, |
165 | handle_level_irq, intc_dev.name); | 165 | handle_level_irq, intc_dev.name); |
166 | irq_set_status_flags(i, IRQ_LEVEL); | 166 | irq_set_status_flags(i, IRQ_LEVEL); |
167 | } | 167 | } |
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c index 098822413729..ce7ac8435d5c 100644 --- a/arch/microblaze/kernel/irq.c +++ b/arch/microblaze/kernel/irq.c | |||
@@ -47,48 +47,6 @@ next_irq: | |||
47 | trace_hardirqs_on(); | 47 | trace_hardirqs_on(); |
48 | } | 48 | } |
49 | 49 | ||
50 | int show_interrupts(struct seq_file *p, void *v) | ||
51 | { | ||
52 | int i = *(loff_t *) v, j; | ||
53 | struct irq_desc *desc; | ||
54 | struct irqaction *action; | ||
55 | unsigned long flags; | ||
56 | |||
57 | if (i == 0) { | ||
58 | seq_printf(p, " "); | ||
59 | for_each_online_cpu(j) | ||
60 | seq_printf(p, "CPU%-8d", j); | ||
61 | seq_putc(p, '\n'); | ||
62 | } | ||
63 | |||
64 | if (i < nr_irq) { | ||
65 | desc = irq_to_desc(i); | ||
66 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
67 | action = desc->action; | ||
68 | if (!action) | ||
69 | goto skip; | ||
70 | seq_printf(p, "%3d: ", i); | ||
71 | #ifndef CONFIG_SMP | ||
72 | seq_printf(p, "%10u ", kstat_irqs(i)); | ||
73 | #else | ||
74 | for_each_online_cpu(j) | ||
75 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | ||
76 | #endif | ||
77 | seq_printf(p, " %8s", desc->status & | ||
78 | IRQ_LEVEL ? "level" : "edge"); | ||
79 | seq_printf(p, " %8s", desc->irq_data.chip->name); | ||
80 | seq_printf(p, " %s", action->name); | ||
81 | |||
82 | for (action = action->next; action; action = action->next) | ||
83 | seq_printf(p, ", %s", action->name); | ||
84 | |||
85 | seq_putc(p, '\n'); | ||
86 | skip: | ||
87 | raw_spin_unlock_irqrestore(&desc->lock, flags); | ||
88 | } | ||
89 | return 0; | ||
90 | } | ||
91 | |||
92 | /* MS: There is no any advance mapping mechanism. We are using simple 32bit | 50 | /* MS: There is no any advance mapping mechanism. We are using simple 32bit |
93 | intc without any cascades or any connection that's why mapping is 1:1 */ | 51 | intc without any cascades or any connection that's why mapping is 1:1 */ |
94 | unsigned int irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq) | 52 | unsigned int irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq) |
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index 1e01a1253631..53599067d2f9 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c | |||
@@ -237,7 +237,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev) | |||
237 | 237 | ||
238 | virq = irq_create_mapping(NULL, line); | 238 | virq = irq_create_mapping(NULL, line); |
239 | if (virq != NO_IRQ) | 239 | if (virq != NO_IRQ) |
240 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | 240 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
241 | } else { | 241 | } else { |
242 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", | 242 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
243 | oirq.size, oirq.specifier[0], oirq.specifier[1], | 243 | oirq.size, oirq.specifier[0], oirq.specifier[1], |
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c index f91c43a7d5dc..596ad00e7f05 100644 --- a/arch/mips/alchemy/devboards/bcsr.c +++ b/arch/mips/alchemy/devboards/bcsr.c | |||
@@ -142,8 +142,8 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq) | |||
142 | bcsr_csc_base = csc_start; | 142 | bcsr_csc_base = csc_start; |
143 | 143 | ||
144 | for (irq = csc_start; irq <= csc_end; irq++) | 144 | for (irq = csc_start; irq <= csc_end; irq++) |
145 | set_irq_chip_and_handler_name(irq, &bcsr_irq_type, | 145 | irq_set_chip_and_handler_name(irq, &bcsr_irq_type, |
146 | handle_level_irq, "level"); | 146 | handle_level_irq, "level"); |
147 | 147 | ||
148 | set_irq_chained_handler(hook_irq, bcsr_csc_handler); | 148 | irq_set_chained_handler(hook_irq, bcsr_csc_handler); |
149 | } | 149 | } |
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c index 887619547553..4a8980027ecf 100644 --- a/arch/mips/alchemy/devboards/db1200/setup.c +++ b/arch/mips/alchemy/devboards/db1200/setup.c | |||
@@ -63,20 +63,19 @@ void __init board_setup(void) | |||
63 | static int __init db1200_arch_init(void) | 63 | static int __init db1200_arch_init(void) |
64 | { | 64 | { |
65 | /* GPIO7 is low-level triggered CPLD cascade */ | 65 | /* GPIO7 is low-level triggered CPLD cascade */ |
66 | set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); | 66 | irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); |
67 | bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); | 67 | bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); |
68 | 68 | ||
69 | /* insert/eject pairs: one of both is always screaming. To avoid | 69 | /* insert/eject pairs: one of both is always screaming. To avoid |
70 | * issues they must not be automatically enabled when initially | 70 | * issues they must not be automatically enabled when initially |
71 | * requested. | 71 | * requested. |
72 | */ | 72 | */ |
73 | irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; | 73 | irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN); |
74 | irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; | 74 | irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN); |
75 | irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN; | 75 | irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN); |
76 | irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN; | 76 | irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN); |
77 | irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN; | 77 | irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN); |
78 | irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN; | 78 | irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN); |
79 | |||
80 | return 0; | 79 | return 0; |
81 | } | 80 | } |
82 | arch_initcall(db1200_arch_init); | 81 | arch_initcall(db1200_arch_init); |
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 9e45971343ed..05f120ff90f9 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c | |||
@@ -215,35 +215,35 @@ void __init board_setup(void) | |||
215 | static int __init db1x00_init_irq(void) | 215 | static int __init db1x00_init_irq(void) |
216 | { | 216 | { |
217 | #if defined(CONFIG_MIPS_MIRAGE) | 217 | #if defined(CONFIG_MIPS_MIRAGE) |
218 | set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ | 218 | irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ |
219 | #elif defined(CONFIG_MIPS_DB1550) | 219 | #elif defined(CONFIG_MIPS_DB1550) |
220 | set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | 220 | irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ |
221 | set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ | 221 | irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ |
222 | set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | 222 | irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ |
223 | set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | 223 | irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ |
224 | set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | 224 | irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ |
225 | set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | 225 | irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ |
226 | #elif defined(CONFIG_MIPS_DB1500) | 226 | #elif defined(CONFIG_MIPS_DB1500) |
227 | set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | 227 | irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ |
228 | set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ | 228 | irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ |
229 | set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | 229 | irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ |
230 | set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | 230 | irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ |
231 | set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | 231 | irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ |
232 | set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | 232 | irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ |
233 | #elif defined(CONFIG_MIPS_DB1100) | 233 | #elif defined(CONFIG_MIPS_DB1100) |
234 | set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | 234 | irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ |
235 | set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ | 235 | irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ |
236 | set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | 236 | irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ |
237 | set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | 237 | irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ |
238 | set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | 238 | irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ |
239 | set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | 239 | irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ |
240 | #elif defined(CONFIG_MIPS_DB1000) | 240 | #elif defined(CONFIG_MIPS_DB1000) |
241 | set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ | 241 | irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ |
242 | set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ | 242 | irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ |
243 | set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ | 243 | irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ |
244 | set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ | 244 | irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ |
245 | set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | 245 | irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ |
246 | set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ | 246 | irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ |
247 | #endif | 247 | #endif |
248 | return 0; | 248 | return 0; |
249 | } | 249 | } |
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index f6540ec47a64..2d85c4b5be09 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c | |||
@@ -197,7 +197,7 @@ void __init board_setup(void) | |||
197 | 197 | ||
198 | static int __init pb1000_init_irq(void) | 198 | static int __init pb1000_init_irq(void) |
199 | { | 199 | { |
200 | set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); | 200 | irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); |
201 | return 0; | 201 | return 0; |
202 | } | 202 | } |
203 | arch_initcall(pb1000_init_irq); | 203 | arch_initcall(pb1000_init_irq); |
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c index 90dda5f3ecc5..d108fd573aaf 100644 --- a/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c | |||
@@ -117,10 +117,10 @@ void __init board_setup(void) | |||
117 | 117 | ||
118 | static int __init pb1100_init_irq(void) | 118 | static int __init pb1100_init_irq(void) |
119 | { | 119 | { |
120 | set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ | 120 | irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ |
121 | set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ | 121 | irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ |
122 | set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ | 122 | irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ |
123 | set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ | 123 | irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ |
124 | 124 | ||
125 | return 0; | 125 | return 0; |
126 | } | 126 | } |
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c index 8b4466f2d44a..6d06b07c2381 100644 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c | |||
@@ -142,7 +142,7 @@ static int __init pb1200_init_irq(void) | |||
142 | panic("Game over. Your score is 0."); | 142 | panic("Game over. Your score is 0."); |
143 | } | 143 | } |
144 | 144 | ||
145 | set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); | 145 | irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); |
146 | bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); | 146 | bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); |
147 | 147 | ||
148 | return 0; | 148 | return 0; |
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index 9cd9dfa698e7..83f46215eb0c 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c | |||
@@ -134,14 +134,14 @@ void __init board_setup(void) | |||
134 | 134 | ||
135 | static int __init pb1500_init_irq(void) | 135 | static int __init pb1500_init_irq(void) |
136 | { | 136 | { |
137 | set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ | 137 | irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ |
138 | set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ | 138 | irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ |
139 | set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ | 139 | irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ |
140 | set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); | 140 | irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); |
141 | set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); | 141 | irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); |
142 | set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); | 142 | irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); |
143 | set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); | 143 | irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); |
144 | set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); | 144 | irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); |
145 | 145 | ||
146 | return 0; | 146 | return 0; |
147 | } | 147 | } |
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index 9d7d6edafa8d..b790213848bd 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c | |||
@@ -73,9 +73,9 @@ void __init board_setup(void) | |||
73 | 73 | ||
74 | static int __init pb1550_init_irq(void) | 74 | static int __init pb1550_init_irq(void) |
75 | { | 75 | { |
76 | set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); | 76 | irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); |
77 | set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); | 77 | irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); |
78 | set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); | 78 | irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); |
79 | 79 | ||
80 | /* enable both PCMCIA card irqs in the shared line */ | 80 | /* enable both PCMCIA card irqs in the shared line */ |
81 | alchemy_gpio2_enable_int(201); | 81 | alchemy_gpio2_enable_int(201); |
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 40b84b991191..cf436ab679ae 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c | |||
@@ -123,11 +123,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert) | |||
123 | 123 | ||
124 | static int __init mtx1_init_irq(void) | 124 | static int __init mtx1_init_irq(void) |
125 | { | 125 | { |
126 | set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); | 126 | irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); |
127 | set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); | 127 | irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); |
128 | set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); | 128 | irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); |
129 | set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); | 129 | irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); |
130 | set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); | 130 | irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); |
131 | 131 | ||
132 | return 0; | 132 | return 0; |
133 | } | 133 | } |
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index 80c521e5290d..febfb0fb0896 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c | |||
@@ -85,19 +85,19 @@ void __init board_setup(void) | |||
85 | 85 | ||
86 | static int __init xxs1500_init_irq(void) | 86 | static int __init xxs1500_init_irq(void) |
87 | { | 87 | { |
88 | set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); | 88 | irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); |
89 | set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); | 89 | irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); |
90 | set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); | 90 | irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); |
91 | set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); | 91 | irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); |
92 | set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); | 92 | irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); |
93 | set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); | 93 | irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); |
94 | 94 | ||
95 | set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); | 95 | irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); |
96 | set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); | 96 | irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); |
97 | set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); | 97 | irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); |
98 | set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); | 98 | irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); |
99 | set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ | 99 | irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ |
100 | set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); | 100 | irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); |
101 | 101 | ||
102 | return 0; | 102 | return 0; |
103 | } | 103 | } |
diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c index a6484b60642f..03db3daadbd8 100644 --- a/arch/mips/ar7/irq.c +++ b/arch/mips/ar7/irq.c | |||
@@ -119,11 +119,11 @@ static void __init ar7_irq_init(int base) | |||
119 | for (i = 0; i < 40; i++) { | 119 | for (i = 0; i < 40; i++) { |
120 | writel(i, REG(CHNL_OFFSET(i))); | 120 | writel(i, REG(CHNL_OFFSET(i))); |
121 | /* Primary IRQ's */ | 121 | /* Primary IRQ's */ |
122 | set_irq_chip_and_handler(base + i, &ar7_irq_type, | 122 | irq_set_chip_and_handler(base + i, &ar7_irq_type, |
123 | handle_level_irq); | 123 | handle_level_irq); |
124 | /* Secondary IRQ's */ | 124 | /* Secondary IRQ's */ |
125 | if (i < 32) | 125 | if (i < 32) |
126 | set_irq_chip_and_handler(base + i + 40, | 126 | irq_set_chip_and_handler(base + i + 40, |
127 | &ar7_sec_irq_type, | 127 | &ar7_sec_irq_type, |
128 | handle_level_irq); | 128 | handle_level_irq); |
129 | } | 129 | } |
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index 7c02bc948a31..ac610d5fe3ba 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c | |||
@@ -124,11 +124,11 @@ static void __init ath79_misc_irq_init(void) | |||
124 | 124 | ||
125 | for (i = ATH79_MISC_IRQ_BASE; | 125 | for (i = ATH79_MISC_IRQ_BASE; |
126 | i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { | 126 | i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { |
127 | set_irq_chip_and_handler(i, &ath79_misc_irq_chip, | 127 | irq_set_chip_and_handler(i, &ath79_misc_irq_chip, |
128 | handle_level_irq); | 128 | handle_level_irq); |
129 | } | 129 | } |
130 | 130 | ||
131 | set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); | 131 | irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); |
132 | } | 132 | } |
133 | 133 | ||
134 | asmlinkage void plat_irq_dispatch(void) | 134 | asmlinkage void plat_irq_dispatch(void) |
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c index 1691531aa34d..cea6021cb8d7 100644 --- a/arch/mips/bcm63xx/irq.c +++ b/arch/mips/bcm63xx/irq.c | |||
@@ -230,11 +230,11 @@ void __init arch_init_irq(void) | |||
230 | 230 | ||
231 | mips_cpu_irq_init(); | 231 | mips_cpu_irq_init(); |
232 | for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) | 232 | for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) |
233 | set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip, | 233 | irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, |
234 | handle_level_irq); | 234 | handle_level_irq); |
235 | 235 | ||
236 | for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) | 236 | for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) |
237 | set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip, | 237 | irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, |
238 | handle_edge_irq); | 238 | handle_edge_irq); |
239 | 239 | ||
240 | setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); | 240 | setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); |
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index ce7500cdf5b7..ffd4ae660f79 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c | |||
@@ -3,10 +3,13 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks | 6 | * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks |
7 | */ | 7 | */ |
8 | #include <linux/irq.h> | 8 | |
9 | #include <linux/interrupt.h> | 9 | #include <linux/interrupt.h> |
10 | #include <linux/bitops.h> | ||
11 | #include <linux/percpu.h> | ||
12 | #include <linux/irq.h> | ||
10 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
11 | 14 | ||
12 | #include <asm/octeon/octeon.h> | 15 | #include <asm/octeon/octeon.h> |
@@ -14,6 +17,47 @@ | |||
14 | static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); | 17 | static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); |
15 | static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); | 18 | static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); |
16 | 19 | ||
20 | static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror); | ||
21 | static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror); | ||
22 | |||
23 | static __read_mostly u8 octeon_irq_ciu_to_irq[8][64]; | ||
24 | |||
25 | union octeon_ciu_chip_data { | ||
26 | void *p; | ||
27 | unsigned long l; | ||
28 | struct { | ||
29 | unsigned int line:6; | ||
30 | unsigned int bit:6; | ||
31 | } s; | ||
32 | }; | ||
33 | |||
34 | struct octeon_core_chip_data { | ||
35 | struct mutex core_irq_mutex; | ||
36 | bool current_en; | ||
37 | bool desired_en; | ||
38 | u8 bit; | ||
39 | }; | ||
40 | |||
41 | #define MIPS_CORE_IRQ_LINES 8 | ||
42 | |||
43 | static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; | ||
44 | |||
45 | static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, | ||
46 | struct irq_chip *chip, | ||
47 | irq_flow_handler_t handler) | ||
48 | { | ||
49 | union octeon_ciu_chip_data cd; | ||
50 | |||
51 | irq_set_chip_and_handler(irq, chip, handler); | ||
52 | |||
53 | cd.l = 0; | ||
54 | cd.s.line = line; | ||
55 | cd.s.bit = bit; | ||
56 | |||
57 | irq_set_chip_data(irq, cd.p); | ||
58 | octeon_irq_ciu_to_irq[line][bit] = irq; | ||
59 | } | ||
60 | |||
17 | static int octeon_coreid_for_cpu(int cpu) | 61 | static int octeon_coreid_for_cpu(int cpu) |
18 | { | 62 | { |
19 | #ifdef CONFIG_SMP | 63 | #ifdef CONFIG_SMP |
@@ -23,9 +67,20 @@ static int octeon_coreid_for_cpu(int cpu) | |||
23 | #endif | 67 | #endif |
24 | } | 68 | } |
25 | 69 | ||
26 | static void octeon_irq_core_ack(unsigned int irq) | 70 | static int octeon_cpu_for_coreid(int coreid) |
71 | { | ||
72 | #ifdef CONFIG_SMP | ||
73 | return cpu_number_map(coreid); | ||
74 | #else | ||
75 | return smp_processor_id(); | ||
76 | #endif | ||
77 | } | ||
78 | |||
79 | static void octeon_irq_core_ack(struct irq_data *data) | ||
27 | { | 80 | { |
28 | unsigned int bit = irq - OCTEON_IRQ_SW0; | 81 | struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); |
82 | unsigned int bit = cd->bit; | ||
83 | |||
29 | /* | 84 | /* |
30 | * We don't need to disable IRQs to make these atomic since | 85 | * We don't need to disable IRQs to make these atomic since |
31 | * they are already disabled earlier in the low level | 86 | * they are already disabled earlier in the low level |
@@ -37,131 +92,121 @@ static void octeon_irq_core_ack(unsigned int irq) | |||
37 | clear_c0_cause(0x100 << bit); | 92 | clear_c0_cause(0x100 << bit); |
38 | } | 93 | } |
39 | 94 | ||
40 | static void octeon_irq_core_eoi(unsigned int irq) | 95 | static void octeon_irq_core_eoi(struct irq_data *data) |
41 | { | 96 | { |
42 | struct irq_desc *desc = irq_to_desc(irq); | 97 | struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); |
43 | unsigned int bit = irq - OCTEON_IRQ_SW0; | 98 | |
44 | /* | ||
45 | * If an IRQ is being processed while we are disabling it the | ||
46 | * handler will attempt to unmask the interrupt after it has | ||
47 | * been disabled. | ||
48 | */ | ||
49 | if ((unlikely(desc->status & IRQ_DISABLED))) | ||
50 | return; | ||
51 | /* | 99 | /* |
52 | * We don't need to disable IRQs to make these atomic since | 100 | * We don't need to disable IRQs to make these atomic since |
53 | * they are already disabled earlier in the low level | 101 | * they are already disabled earlier in the low level |
54 | * interrupt code. | 102 | * interrupt code. |
55 | */ | 103 | */ |
56 | set_c0_status(0x100 << bit); | 104 | set_c0_status(0x100 << cd->bit); |
57 | } | 105 | } |
58 | 106 | ||
59 | static void octeon_irq_core_enable(unsigned int irq) | 107 | static void octeon_irq_core_set_enable_local(void *arg) |
60 | { | 108 | { |
61 | unsigned long flags; | 109 | struct irq_data *data = arg; |
62 | unsigned int bit = irq - OCTEON_IRQ_SW0; | 110 | struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); |
111 | unsigned int mask = 0x100 << cd->bit; | ||
63 | 112 | ||
64 | /* | 113 | /* |
65 | * We need to disable interrupts to make sure our updates are | 114 | * Interrupts are already disabled, so these are atomic. |
66 | * atomic. | ||
67 | */ | 115 | */ |
68 | local_irq_save(flags); | 116 | if (cd->desired_en) |
69 | set_c0_status(0x100 << bit); | 117 | set_c0_status(mask); |
70 | local_irq_restore(flags); | 118 | else |
119 | clear_c0_status(mask); | ||
120 | |||
71 | } | 121 | } |
72 | 122 | ||
73 | static void octeon_irq_core_disable_local(unsigned int irq) | 123 | static void octeon_irq_core_disable(struct irq_data *data) |
74 | { | 124 | { |
75 | unsigned long flags; | 125 | struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); |
76 | unsigned int bit = irq - OCTEON_IRQ_SW0; | 126 | cd->desired_en = false; |
77 | /* | ||
78 | * We need to disable interrupts to make sure our updates are | ||
79 | * atomic. | ||
80 | */ | ||
81 | local_irq_save(flags); | ||
82 | clear_c0_status(0x100 << bit); | ||
83 | local_irq_restore(flags); | ||
84 | } | 127 | } |
85 | 128 | ||
86 | static void octeon_irq_core_disable(unsigned int irq) | 129 | static void octeon_irq_core_enable(struct irq_data *data) |
87 | { | 130 | { |
88 | #ifdef CONFIG_SMP | 131 | struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); |
89 | on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local, | 132 | cd->desired_en = true; |
90 | (void *) (long) irq, 1); | ||
91 | #else | ||
92 | octeon_irq_core_disable_local(irq); | ||
93 | #endif | ||
94 | } | 133 | } |
95 | 134 | ||
96 | static struct irq_chip octeon_irq_chip_core = { | 135 | static void octeon_irq_core_bus_lock(struct irq_data *data) |
97 | .name = "Core", | 136 | { |
98 | .enable = octeon_irq_core_enable, | 137 | struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); |
99 | .disable = octeon_irq_core_disable, | ||
100 | .ack = octeon_irq_core_ack, | ||
101 | .eoi = octeon_irq_core_eoi, | ||
102 | }; | ||
103 | 138 | ||
139 | mutex_lock(&cd->core_irq_mutex); | ||
140 | } | ||
104 | 141 | ||
105 | static void octeon_irq_ciu0_ack(unsigned int irq) | 142 | static void octeon_irq_core_bus_sync_unlock(struct irq_data *data) |
106 | { | 143 | { |
107 | switch (irq) { | 144 | struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data); |
108 | case OCTEON_IRQ_GMX_DRP0: | 145 | |
109 | case OCTEON_IRQ_GMX_DRP1: | 146 | if (cd->desired_en != cd->current_en) { |
110 | case OCTEON_IRQ_IPD_DRP: | 147 | on_each_cpu(octeon_irq_core_set_enable_local, data, 1); |
111 | case OCTEON_IRQ_KEY_ZERO: | 148 | |
112 | case OCTEON_IRQ_TIMER0: | 149 | cd->current_en = cd->desired_en; |
113 | case OCTEON_IRQ_TIMER1: | ||
114 | case OCTEON_IRQ_TIMER2: | ||
115 | case OCTEON_IRQ_TIMER3: | ||
116 | { | ||
117 | int index = cvmx_get_core_num() * 2; | ||
118 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | ||
119 | /* | ||
120 | * CIU timer type interrupts must be acknoleged by | ||
121 | * writing a '1' bit to their sum0 bit. | ||
122 | */ | ||
123 | cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); | ||
124 | break; | ||
125 | } | ||
126 | default: | ||
127 | break; | ||
128 | } | 150 | } |
129 | 151 | ||
130 | /* | 152 | mutex_unlock(&cd->core_irq_mutex); |
131 | * In order to avoid any locking accessing the CIU, we | ||
132 | * acknowledge CIU interrupts by disabling all of them. This | ||
133 | * way we can use a per core register and avoid any out of | ||
134 | * core locking requirements. This has the side affect that | ||
135 | * CIU interrupts can't be processed recursively. | ||
136 | * | ||
137 | * We don't need to disable IRQs to make these atomic since | ||
138 | * they are already disabled earlier in the low level | ||
139 | * interrupt code. | ||
140 | */ | ||
141 | clear_c0_status(0x100 << 2); | ||
142 | } | 153 | } |
143 | 154 | ||
144 | static void octeon_irq_ciu0_eoi(unsigned int irq) | 155 | static struct irq_chip octeon_irq_chip_core = { |
156 | .name = "Core", | ||
157 | .irq_enable = octeon_irq_core_enable, | ||
158 | .irq_disable = octeon_irq_core_disable, | ||
159 | .irq_ack = octeon_irq_core_ack, | ||
160 | .irq_eoi = octeon_irq_core_eoi, | ||
161 | .irq_bus_lock = octeon_irq_core_bus_lock, | ||
162 | .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock, | ||
163 | |||
164 | .irq_cpu_online = octeon_irq_core_eoi, | ||
165 | .irq_cpu_offline = octeon_irq_core_ack, | ||
166 | .flags = IRQCHIP_ONOFFLINE_ENABLED, | ||
167 | }; | ||
168 | |||
169 | static void __init octeon_irq_init_core(void) | ||
145 | { | 170 | { |
146 | /* | 171 | int i; |
147 | * Enable all CIU interrupts again. We don't need to disable | 172 | int irq; |
148 | * IRQs to make these atomic since they are already disabled | 173 | struct octeon_core_chip_data *cd; |
149 | * earlier in the low level interrupt code. | 174 | |
150 | */ | 175 | for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) { |
151 | set_c0_status(0x100 << 2); | 176 | cd = &octeon_irq_core_chip_data[i]; |
177 | cd->current_en = false; | ||
178 | cd->desired_en = false; | ||
179 | cd->bit = i; | ||
180 | mutex_init(&cd->core_irq_mutex); | ||
181 | |||
182 | irq = OCTEON_IRQ_SW0 + i; | ||
183 | switch (irq) { | ||
184 | case OCTEON_IRQ_TIMER: | ||
185 | case OCTEON_IRQ_SW0: | ||
186 | case OCTEON_IRQ_SW1: | ||
187 | case OCTEON_IRQ_5: | ||
188 | case OCTEON_IRQ_PERF: | ||
189 | irq_set_chip_data(irq, cd); | ||
190 | irq_set_chip_and_handler(irq, &octeon_irq_chip_core, | ||
191 | handle_percpu_irq); | ||
192 | break; | ||
193 | default: | ||
194 | break; | ||
195 | } | ||
196 | } | ||
152 | } | 197 | } |
153 | 198 | ||
154 | static int next_coreid_for_irq(struct irq_desc *desc) | 199 | static int next_cpu_for_irq(struct irq_data *data) |
155 | { | 200 | { |
156 | 201 | ||
157 | #ifdef CONFIG_SMP | 202 | #ifdef CONFIG_SMP |
158 | int coreid; | 203 | int cpu; |
159 | int weight = cpumask_weight(desc->affinity); | 204 | int weight = cpumask_weight(data->affinity); |
160 | 205 | ||
161 | if (weight > 1) { | 206 | if (weight > 1) { |
162 | int cpu = smp_processor_id(); | 207 | cpu = smp_processor_id(); |
163 | for (;;) { | 208 | for (;;) { |
164 | cpu = cpumask_next(cpu, desc->affinity); | 209 | cpu = cpumask_next(cpu, data->affinity); |
165 | if (cpu >= nr_cpu_ids) { | 210 | if (cpu >= nr_cpu_ids) { |
166 | cpu = -1; | 211 | cpu = -1; |
167 | continue; | 212 | continue; |
@@ -169,83 +214,175 @@ static int next_coreid_for_irq(struct irq_desc *desc) | |||
169 | break; | 214 | break; |
170 | } | 215 | } |
171 | } | 216 | } |
172 | coreid = octeon_coreid_for_cpu(cpu); | ||
173 | } else if (weight == 1) { | 217 | } else if (weight == 1) { |
174 | coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity)); | 218 | cpu = cpumask_first(data->affinity); |
175 | } else { | 219 | } else { |
176 | coreid = cvmx_get_core_num(); | 220 | cpu = smp_processor_id(); |
177 | } | 221 | } |
178 | return coreid; | 222 | return cpu; |
179 | #else | 223 | #else |
180 | return cvmx_get_core_num(); | 224 | return smp_processor_id(); |
181 | #endif | 225 | #endif |
182 | } | 226 | } |
183 | 227 | ||
184 | static void octeon_irq_ciu0_enable(unsigned int irq) | 228 | static void octeon_irq_ciu_enable(struct irq_data *data) |
185 | { | 229 | { |
186 | struct irq_desc *desc = irq_to_desc(irq); | 230 | int cpu = next_cpu_for_irq(data); |
187 | int coreid = next_coreid_for_irq(desc); | 231 | int coreid = octeon_coreid_for_cpu(cpu); |
232 | unsigned long *pen; | ||
188 | unsigned long flags; | 233 | unsigned long flags; |
189 | uint64_t en0; | 234 | union octeon_ciu_chip_data cd; |
190 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | 235 | |
236 | cd.p = irq_data_get_irq_chip_data(data); | ||
191 | 237 | ||
192 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); | 238 | if (cd.s.line == 0) { |
193 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 239 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); |
194 | en0 |= 1ull << bit; | 240 | pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); |
195 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | 241 | set_bit(cd.s.bit, pen); |
196 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 242 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); |
197 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); | 243 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); |
244 | } else { | ||
245 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | ||
246 | pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); | ||
247 | set_bit(cd.s.bit, pen); | ||
248 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); | ||
249 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
250 | } | ||
198 | } | 251 | } |
199 | 252 | ||
200 | static void octeon_irq_ciu0_enable_mbox(unsigned int irq) | 253 | static void octeon_irq_ciu_enable_local(struct irq_data *data) |
201 | { | 254 | { |
202 | int coreid = cvmx_get_core_num(); | 255 | unsigned long *pen; |
256 | unsigned long flags; | ||
257 | union octeon_ciu_chip_data cd; | ||
258 | |||
259 | cd.p = irq_data_get_irq_chip_data(data); | ||
260 | |||
261 | if (cd.s.line == 0) { | ||
262 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); | ||
263 | pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); | ||
264 | set_bit(cd.s.bit, pen); | ||
265 | cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); | ||
266 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); | ||
267 | } else { | ||
268 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | ||
269 | pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); | ||
270 | set_bit(cd.s.bit, pen); | ||
271 | cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); | ||
272 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
273 | } | ||
274 | } | ||
275 | |||
276 | static void octeon_irq_ciu_disable_local(struct irq_data *data) | ||
277 | { | ||
278 | unsigned long *pen; | ||
203 | unsigned long flags; | 279 | unsigned long flags; |
204 | uint64_t en0; | 280 | union octeon_ciu_chip_data cd; |
205 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | 281 | |
282 | cd.p = irq_data_get_irq_chip_data(data); | ||
206 | 283 | ||
207 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); | 284 | if (cd.s.line == 0) { |
208 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 285 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); |
209 | en0 |= 1ull << bit; | 286 | pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror); |
210 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | 287 | clear_bit(cd.s.bit, pen); |
211 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 288 | cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen); |
212 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); | 289 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); |
290 | } else { | ||
291 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | ||
292 | pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror); | ||
293 | clear_bit(cd.s.bit, pen); | ||
294 | cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen); | ||
295 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
296 | } | ||
213 | } | 297 | } |
214 | 298 | ||
215 | static void octeon_irq_ciu0_disable(unsigned int irq) | 299 | static void octeon_irq_ciu_disable_all(struct irq_data *data) |
216 | { | 300 | { |
217 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | ||
218 | unsigned long flags; | 301 | unsigned long flags; |
219 | uint64_t en0; | 302 | unsigned long *pen; |
220 | int cpu; | 303 | int cpu; |
221 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); | 304 | union octeon_ciu_chip_data cd; |
222 | for_each_online_cpu(cpu) { | 305 | |
223 | int coreid = octeon_coreid_for_cpu(cpu); | 306 | wmb(); /* Make sure flag changes arrive before register updates. */ |
224 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 307 | |
225 | en0 &= ~(1ull << bit); | 308 | cd.p = irq_data_get_irq_chip_data(data); |
226 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | 309 | |
310 | if (cd.s.line == 0) { | ||
311 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); | ||
312 | for_each_online_cpu(cpu) { | ||
313 | int coreid = octeon_coreid_for_cpu(cpu); | ||
314 | pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); | ||
315 | clear_bit(cd.s.bit, pen); | ||
316 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); | ||
317 | } | ||
318 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); | ||
319 | } else { | ||
320 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | ||
321 | for_each_online_cpu(cpu) { | ||
322 | int coreid = octeon_coreid_for_cpu(cpu); | ||
323 | pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); | ||
324 | clear_bit(cd.s.bit, pen); | ||
325 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); | ||
326 | } | ||
327 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
328 | } | ||
329 | } | ||
330 | |||
331 | static void octeon_irq_ciu_enable_all(struct irq_data *data) | ||
332 | { | ||
333 | unsigned long flags; | ||
334 | unsigned long *pen; | ||
335 | int cpu; | ||
336 | union octeon_ciu_chip_data cd; | ||
337 | |||
338 | cd.p = irq_data_get_irq_chip_data(data); | ||
339 | |||
340 | if (cd.s.line == 0) { | ||
341 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); | ||
342 | for_each_online_cpu(cpu) { | ||
343 | int coreid = octeon_coreid_for_cpu(cpu); | ||
344 | pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); | ||
345 | set_bit(cd.s.bit, pen); | ||
346 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); | ||
347 | } | ||
348 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); | ||
349 | } else { | ||
350 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | ||
351 | for_each_online_cpu(cpu) { | ||
352 | int coreid = octeon_coreid_for_cpu(cpu); | ||
353 | pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); | ||
354 | set_bit(cd.s.bit, pen); | ||
355 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); | ||
356 | } | ||
357 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
227 | } | 358 | } |
228 | /* | ||
229 | * We need to do a read after the last update to make sure all | ||
230 | * of them are done. | ||
231 | */ | ||
232 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); | ||
233 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); | ||
234 | } | 359 | } |
235 | 360 | ||
236 | /* | 361 | /* |
237 | * Enable the irq on the next core in the affinity set for chips that | 362 | * Enable the irq on the next core in the affinity set for chips that |
238 | * have the EN*_W1{S,C} registers. | 363 | * have the EN*_W1{S,C} registers. |
239 | */ | 364 | */ |
240 | static void octeon_irq_ciu0_enable_v2(unsigned int irq) | 365 | static void octeon_irq_ciu_enable_v2(struct irq_data *data) |
241 | { | 366 | { |
242 | int index; | 367 | u64 mask; |
243 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | 368 | int cpu = next_cpu_for_irq(data); |
244 | struct irq_desc *desc = irq_to_desc(irq); | 369 | union octeon_ciu_chip_data cd; |
370 | |||
371 | cd.p = irq_data_get_irq_chip_data(data); | ||
372 | mask = 1ull << (cd.s.bit); | ||
245 | 373 | ||
246 | if ((desc->status & IRQ_DISABLED) == 0) { | 374 | /* |
247 | index = next_coreid_for_irq(desc) * 2; | 375 | * Called under the desc lock, so these should never get out |
376 | * of sync. | ||
377 | */ | ||
378 | if (cd.s.line == 0) { | ||
379 | int index = octeon_coreid_for_cpu(cpu) * 2; | ||
380 | set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); | ||
248 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | 381 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); |
382 | } else { | ||
383 | int index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
384 | set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); | ||
385 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | ||
249 | } | 386 | } |
250 | } | 387 | } |
251 | 388 | ||
@@ -253,83 +390,155 @@ static void octeon_irq_ciu0_enable_v2(unsigned int irq) | |||
253 | * Enable the irq on the current CPU for chips that | 390 | * Enable the irq on the current CPU for chips that |
254 | * have the EN*_W1{S,C} registers. | 391 | * have the EN*_W1{S,C} registers. |
255 | */ | 392 | */ |
256 | static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq) | 393 | static void octeon_irq_ciu_enable_local_v2(struct irq_data *data) |
394 | { | ||
395 | u64 mask; | ||
396 | union octeon_ciu_chip_data cd; | ||
397 | |||
398 | cd.p = irq_data_get_irq_chip_data(data); | ||
399 | mask = 1ull << (cd.s.bit); | ||
400 | |||
401 | if (cd.s.line == 0) { | ||
402 | int index = cvmx_get_core_num() * 2; | ||
403 | set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror)); | ||
404 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | ||
405 | } else { | ||
406 | int index = cvmx_get_core_num() * 2 + 1; | ||
407 | set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror)); | ||
408 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | ||
409 | } | ||
410 | } | ||
411 | |||
412 | static void octeon_irq_ciu_disable_local_v2(struct irq_data *data) | ||
257 | { | 413 | { |
258 | int index; | 414 | u64 mask; |
259 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | 415 | union octeon_ciu_chip_data cd; |
260 | 416 | ||
261 | index = cvmx_get_core_num() * 2; | 417 | cd.p = irq_data_get_irq_chip_data(data); |
262 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | 418 | mask = 1ull << (cd.s.bit); |
419 | |||
420 | if (cd.s.line == 0) { | ||
421 | int index = cvmx_get_core_num() * 2; | ||
422 | clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror)); | ||
423 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | ||
424 | } else { | ||
425 | int index = cvmx_get_core_num() * 2 + 1; | ||
426 | clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror)); | ||
427 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
428 | } | ||
263 | } | 429 | } |
264 | 430 | ||
265 | /* | 431 | /* |
266 | * Disable the irq on the current core for chips that have the EN*_W1{S,C} | 432 | * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq. |
267 | * registers. | ||
268 | */ | 433 | */ |
269 | static void octeon_irq_ciu0_ack_v2(unsigned int irq) | 434 | static void octeon_irq_ciu_ack(struct irq_data *data) |
270 | { | 435 | { |
271 | int index = cvmx_get_core_num() * 2; | 436 | u64 mask; |
272 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | 437 | union octeon_ciu_chip_data cd; |
273 | 438 | ||
274 | switch (irq) { | 439 | cd.p = data->chip_data; |
275 | case OCTEON_IRQ_GMX_DRP0: | 440 | mask = 1ull << (cd.s.bit); |
276 | case OCTEON_IRQ_GMX_DRP1: | 441 | |
277 | case OCTEON_IRQ_IPD_DRP: | 442 | if (cd.s.line == 0) { |
278 | case OCTEON_IRQ_KEY_ZERO: | 443 | int index = cvmx_get_core_num() * 2; |
279 | case OCTEON_IRQ_TIMER0: | ||
280 | case OCTEON_IRQ_TIMER1: | ||
281 | case OCTEON_IRQ_TIMER2: | ||
282 | case OCTEON_IRQ_TIMER3: | ||
283 | /* | ||
284 | * CIU timer type interrupts must be acknoleged by | ||
285 | * writing a '1' bit to their sum0 bit. | ||
286 | */ | ||
287 | cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); | 444 | cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); |
288 | break; | 445 | } else { |
289 | default: | 446 | cvmx_write_csr(CVMX_CIU_INT_SUM1, mask); |
290 | break; | ||
291 | } | 447 | } |
292 | |||
293 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | ||
294 | } | 448 | } |
295 | 449 | ||
296 | /* | 450 | /* |
297 | * Enable the irq on the current core for chips that have the EN*_W1{S,C} | 451 | * Disable the irq on the all cores for chips that have the EN*_W1{S,C} |
298 | * registers. | 452 | * registers. |
299 | */ | 453 | */ |
300 | static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq) | 454 | static void octeon_irq_ciu_disable_all_v2(struct irq_data *data) |
301 | { | 455 | { |
302 | struct irq_desc *desc = irq_to_desc(irq); | 456 | int cpu; |
303 | int index = cvmx_get_core_num() * 2; | 457 | u64 mask; |
304 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | 458 | union octeon_ciu_chip_data cd; |
305 | 459 | ||
306 | if (likely((desc->status & IRQ_DISABLED) == 0)) | 460 | wmb(); /* Make sure flag changes arrive before register updates. */ |
307 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | 461 | |
462 | cd.p = data->chip_data; | ||
463 | mask = 1ull << (cd.s.bit); | ||
464 | |||
465 | if (cd.s.line == 0) { | ||
466 | for_each_online_cpu(cpu) { | ||
467 | int index = octeon_coreid_for_cpu(cpu) * 2; | ||
468 | clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); | ||
469 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | ||
470 | } | ||
471 | } else { | ||
472 | for_each_online_cpu(cpu) { | ||
473 | int index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
474 | clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); | ||
475 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
476 | } | ||
477 | } | ||
308 | } | 478 | } |
309 | 479 | ||
310 | /* | 480 | /* |
311 | * Disable the irq on the all cores for chips that have the EN*_W1{S,C} | 481 | * Enable the irq on the all cores for chips that have the EN*_W1{S,C} |
312 | * registers. | 482 | * registers. |
313 | */ | 483 | */ |
314 | static void octeon_irq_ciu0_disable_all_v2(unsigned int irq) | 484 | static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) |
315 | { | 485 | { |
316 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | ||
317 | int index; | ||
318 | int cpu; | 486 | int cpu; |
319 | for_each_online_cpu(cpu) { | 487 | u64 mask; |
320 | index = octeon_coreid_for_cpu(cpu) * 2; | 488 | union octeon_ciu_chip_data cd; |
321 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | 489 | |
490 | cd.p = data->chip_data; | ||
491 | mask = 1ull << (cd.s.bit); | ||
492 | |||
493 | if (cd.s.line == 0) { | ||
494 | for_each_online_cpu(cpu) { | ||
495 | int index = octeon_coreid_for_cpu(cpu) * 2; | ||
496 | set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu)); | ||
497 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | ||
498 | } | ||
499 | } else { | ||
500 | for_each_online_cpu(cpu) { | ||
501 | int index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
502 | set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); | ||
503 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | ||
504 | } | ||
322 | } | 505 | } |
323 | } | 506 | } |
324 | 507 | ||
325 | #ifdef CONFIG_SMP | 508 | #ifdef CONFIG_SMP |
326 | static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) | 509 | |
510 | static void octeon_irq_cpu_offline_ciu(struct irq_data *data) | ||
511 | { | ||
512 | int cpu = smp_processor_id(); | ||
513 | cpumask_t new_affinity; | ||
514 | |||
515 | if (!cpumask_test_cpu(cpu, data->affinity)) | ||
516 | return; | ||
517 | |||
518 | if (cpumask_weight(data->affinity) > 1) { | ||
519 | /* | ||
520 | * It has multi CPU affinity, just remove this CPU | ||
521 | * from the affinity set. | ||
522 | */ | ||
523 | cpumask_copy(&new_affinity, data->affinity); | ||
524 | cpumask_clear_cpu(cpu, &new_affinity); | ||
525 | } else { | ||
526 | /* Otherwise, put it on lowest numbered online CPU. */ | ||
527 | cpumask_clear(&new_affinity); | ||
528 | cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); | ||
529 | } | ||
530 | __irq_set_affinity_locked(data, &new_affinity); | ||
531 | } | ||
532 | |||
533 | static int octeon_irq_ciu_set_affinity(struct irq_data *data, | ||
534 | const struct cpumask *dest, bool force) | ||
327 | { | 535 | { |
328 | int cpu; | 536 | int cpu; |
329 | struct irq_desc *desc = irq_to_desc(irq); | 537 | bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); |
330 | int enable_one = (desc->status & IRQ_DISABLED) == 0; | ||
331 | unsigned long flags; | 538 | unsigned long flags; |
332 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | 539 | union octeon_ciu_chip_data cd; |
540 | |||
541 | cd.p = data->chip_data; | ||
333 | 542 | ||
334 | /* | 543 | /* |
335 | * For non-v2 CIU, we will allow only single CPU affinity. | 544 | * For non-v2 CIU, we will allow only single CPU affinity. |
@@ -339,26 +548,40 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * | |||
339 | if (cpumask_weight(dest) != 1) | 548 | if (cpumask_weight(dest) != 1) |
340 | return -EINVAL; | 549 | return -EINVAL; |
341 | 550 | ||
342 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); | 551 | if (!enable_one) |
343 | for_each_online_cpu(cpu) { | 552 | return 0; |
344 | int coreid = octeon_coreid_for_cpu(cpu); | 553 | |
345 | uint64_t en0 = | 554 | if (cd.s.line == 0) { |
346 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 555 | raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); |
347 | if (cpumask_test_cpu(cpu, dest) && enable_one) { | 556 | for_each_online_cpu(cpu) { |
348 | enable_one = 0; | 557 | int coreid = octeon_coreid_for_cpu(cpu); |
349 | en0 |= 1ull << bit; | 558 | unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); |
350 | } else { | 559 | |
351 | en0 &= ~(1ull << bit); | 560 | if (cpumask_test_cpu(cpu, dest) && enable_one) { |
561 | enable_one = false; | ||
562 | set_bit(cd.s.bit, pen); | ||
563 | } else { | ||
564 | clear_bit(cd.s.bit, pen); | ||
565 | } | ||
566 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen); | ||
352 | } | 567 | } |
353 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | 568 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); |
569 | } else { | ||
570 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | ||
571 | for_each_online_cpu(cpu) { | ||
572 | int coreid = octeon_coreid_for_cpu(cpu); | ||
573 | unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); | ||
574 | |||
575 | if (cpumask_test_cpu(cpu, dest) && enable_one) { | ||
576 | enable_one = false; | ||
577 | set_bit(cd.s.bit, pen); | ||
578 | } else { | ||
579 | clear_bit(cd.s.bit, pen); | ||
580 | } | ||
581 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); | ||
582 | } | ||
583 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
354 | } | 584 | } |
355 | /* | ||
356 | * We need to do a read after the last update to make sure all | ||
357 | * of them are done. | ||
358 | */ | ||
359 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); | ||
360 | raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); | ||
361 | |||
362 | return 0; | 585 | return 0; |
363 | } | 586 | } |
364 | 587 | ||
@@ -366,22 +589,46 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * | |||
366 | * Set affinity for the irq for chips that have the EN*_W1{S,C} | 589 | * Set affinity for the irq for chips that have the EN*_W1{S,C} |
367 | * registers. | 590 | * registers. |
368 | */ | 591 | */ |
369 | static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, | 592 | static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data, |
370 | const struct cpumask *dest) | 593 | const struct cpumask *dest, |
594 | bool force) | ||
371 | { | 595 | { |
372 | int cpu; | 596 | int cpu; |
373 | int index; | 597 | bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data); |
374 | struct irq_desc *desc = irq_to_desc(irq); | 598 | u64 mask; |
375 | int enable_one = (desc->status & IRQ_DISABLED) == 0; | 599 | union octeon_ciu_chip_data cd; |
376 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | 600 | |
377 | 601 | if (!enable_one) | |
378 | for_each_online_cpu(cpu) { | 602 | return 0; |
379 | index = octeon_coreid_for_cpu(cpu) * 2; | 603 | |
380 | if (cpumask_test_cpu(cpu, dest) && enable_one) { | 604 | cd.p = data->chip_data; |
381 | enable_one = 0; | 605 | mask = 1ull << cd.s.bit; |
382 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | 606 | |
383 | } else { | 607 | if (cd.s.line == 0) { |
384 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | 608 | for_each_online_cpu(cpu) { |
609 | unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu); | ||
610 | int index = octeon_coreid_for_cpu(cpu) * 2; | ||
611 | if (cpumask_test_cpu(cpu, dest) && enable_one) { | ||
612 | enable_one = false; | ||
613 | set_bit(cd.s.bit, pen); | ||
614 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | ||
615 | } else { | ||
616 | clear_bit(cd.s.bit, pen); | ||
617 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | ||
618 | } | ||
619 | } | ||
620 | } else { | ||
621 | for_each_online_cpu(cpu) { | ||
622 | unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); | ||
623 | int index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
624 | if (cpumask_test_cpu(cpu, dest) && enable_one) { | ||
625 | enable_one = false; | ||
626 | set_bit(cd.s.bit, pen); | ||
627 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | ||
628 | } else { | ||
629 | clear_bit(cd.s.bit, pen); | ||
630 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
631 | } | ||
385 | } | 632 | } |
386 | } | 633 | } |
387 | return 0; | 634 | return 0; |
@@ -389,80 +636,102 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, | |||
389 | #endif | 636 | #endif |
390 | 637 | ||
391 | /* | 638 | /* |
639 | * The v1 CIU code already masks things, so supply a dummy version to | ||
640 | * the core chip code. | ||
641 | */ | ||
642 | static void octeon_irq_dummy_mask(struct irq_data *data) | ||
643 | { | ||
644 | } | ||
645 | |||
646 | /* | ||
392 | * Newer octeon chips have support for lockless CIU operation. | 647 | * Newer octeon chips have support for lockless CIU operation. |
393 | */ | 648 | */ |
394 | static struct irq_chip octeon_irq_chip_ciu0_v2 = { | 649 | static struct irq_chip octeon_irq_chip_ciu_v2 = { |
395 | .name = "CIU0", | 650 | .name = "CIU", |
396 | .enable = octeon_irq_ciu0_enable_v2, | 651 | .irq_enable = octeon_irq_ciu_enable_v2, |
397 | .disable = octeon_irq_ciu0_disable_all_v2, | 652 | .irq_disable = octeon_irq_ciu_disable_all_v2, |
398 | .eoi = octeon_irq_ciu0_enable_v2, | 653 | .irq_mask = octeon_irq_ciu_disable_local_v2, |
654 | .irq_unmask = octeon_irq_ciu_enable_v2, | ||
399 | #ifdef CONFIG_SMP | 655 | #ifdef CONFIG_SMP |
400 | .set_affinity = octeon_irq_ciu0_set_affinity_v2, | 656 | .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, |
657 | .irq_cpu_offline = octeon_irq_cpu_offline_ciu, | ||
401 | #endif | 658 | #endif |
402 | }; | 659 | }; |
403 | 660 | ||
404 | static struct irq_chip octeon_irq_chip_ciu0 = { | 661 | static struct irq_chip octeon_irq_chip_ciu_edge_v2 = { |
405 | .name = "CIU0", | 662 | .name = "CIU-E", |
406 | .enable = octeon_irq_ciu0_enable, | 663 | .irq_enable = octeon_irq_ciu_enable_v2, |
407 | .disable = octeon_irq_ciu0_disable, | 664 | .irq_disable = octeon_irq_ciu_disable_all_v2, |
408 | .eoi = octeon_irq_ciu0_eoi, | 665 | .irq_ack = octeon_irq_ciu_ack, |
666 | .irq_mask = octeon_irq_ciu_disable_local_v2, | ||
667 | .irq_unmask = octeon_irq_ciu_enable_v2, | ||
409 | #ifdef CONFIG_SMP | 668 | #ifdef CONFIG_SMP |
410 | .set_affinity = octeon_irq_ciu0_set_affinity, | 669 | .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, |
670 | .irq_cpu_offline = octeon_irq_cpu_offline_ciu, | ||
411 | #endif | 671 | #endif |
412 | }; | 672 | }; |
413 | 673 | ||
414 | /* The mbox versions don't do any affinity or round-robin. */ | 674 | static struct irq_chip octeon_irq_chip_ciu = { |
415 | static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = { | 675 | .name = "CIU", |
416 | .name = "CIU0-M", | 676 | .irq_enable = octeon_irq_ciu_enable, |
417 | .enable = octeon_irq_ciu0_enable_mbox_v2, | 677 | .irq_disable = octeon_irq_ciu_disable_all, |
418 | .disable = octeon_irq_ciu0_disable, | 678 | .irq_mask = octeon_irq_dummy_mask, |
419 | .eoi = octeon_irq_ciu0_eoi_mbox_v2, | 679 | #ifdef CONFIG_SMP |
680 | .irq_set_affinity = octeon_irq_ciu_set_affinity, | ||
681 | .irq_cpu_offline = octeon_irq_cpu_offline_ciu, | ||
682 | #endif | ||
420 | }; | 683 | }; |
421 | 684 | ||
422 | static struct irq_chip octeon_irq_chip_ciu0_mbox = { | 685 | static struct irq_chip octeon_irq_chip_ciu_edge = { |
423 | .name = "CIU0-M", | 686 | .name = "CIU-E", |
424 | .enable = octeon_irq_ciu0_enable_mbox, | 687 | .irq_enable = octeon_irq_ciu_enable, |
425 | .disable = octeon_irq_ciu0_disable, | 688 | .irq_disable = octeon_irq_ciu_disable_all, |
426 | .eoi = octeon_irq_ciu0_eoi, | 689 | .irq_mask = octeon_irq_dummy_mask, |
690 | .irq_ack = octeon_irq_ciu_ack, | ||
691 | #ifdef CONFIG_SMP | ||
692 | .irq_set_affinity = octeon_irq_ciu_set_affinity, | ||
693 | .irq_cpu_offline = octeon_irq_cpu_offline_ciu, | ||
694 | #endif | ||
427 | }; | 695 | }; |
428 | 696 | ||
429 | static void octeon_irq_ciu1_ack(unsigned int irq) | 697 | /* The mbox versions don't do any affinity or round-robin. */ |
430 | { | 698 | static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = { |
431 | /* | 699 | .name = "CIU-M", |
432 | * In order to avoid any locking accessing the CIU, we | 700 | .irq_enable = octeon_irq_ciu_enable_all_v2, |
433 | * acknowledge CIU interrupts by disabling all of them. This | 701 | .irq_disable = octeon_irq_ciu_disable_all_v2, |
434 | * way we can use a per core register and avoid any out of | 702 | .irq_ack = octeon_irq_ciu_disable_local_v2, |
435 | * core locking requirements. This has the side affect that | 703 | .irq_eoi = octeon_irq_ciu_enable_local_v2, |
436 | * CIU interrupts can't be processed recursively. We don't | 704 | |
437 | * need to disable IRQs to make these atomic since they are | 705 | .irq_cpu_online = octeon_irq_ciu_enable_local_v2, |
438 | * already disabled earlier in the low level interrupt code. | 706 | .irq_cpu_offline = octeon_irq_ciu_disable_local_v2, |
439 | */ | 707 | .flags = IRQCHIP_ONOFFLINE_ENABLED, |
440 | clear_c0_status(0x100 << 3); | 708 | }; |
441 | } | ||
442 | 709 | ||
443 | static void octeon_irq_ciu1_eoi(unsigned int irq) | 710 | static struct irq_chip octeon_irq_chip_ciu_mbox = { |
444 | { | 711 | .name = "CIU-M", |
445 | /* | 712 | .irq_enable = octeon_irq_ciu_enable_all, |
446 | * Enable all CIU interrupts again. We don't need to disable | 713 | .irq_disable = octeon_irq_ciu_disable_all, |
447 | * IRQs to make these atomic since they are already disabled | 714 | |
448 | * earlier in the low level interrupt code. | 715 | .irq_cpu_online = octeon_irq_ciu_enable_local, |
449 | */ | 716 | .irq_cpu_offline = octeon_irq_ciu_disable_local, |
450 | set_c0_status(0x100 << 3); | 717 | .flags = IRQCHIP_ONOFFLINE_ENABLED, |
451 | } | 718 | }; |
452 | 719 | ||
453 | static void octeon_irq_ciu1_enable(unsigned int irq) | 720 | /* |
721 | * Watchdog interrupts are special. They are associated with a single | ||
722 | * core, so we hardwire the affinity to that core. | ||
723 | */ | ||
724 | static void octeon_irq_ciu_wd_enable(struct irq_data *data) | ||
454 | { | 725 | { |
455 | struct irq_desc *desc = irq_to_desc(irq); | ||
456 | int coreid = next_coreid_for_irq(desc); | ||
457 | unsigned long flags; | 726 | unsigned long flags; |
458 | uint64_t en1; | 727 | unsigned long *pen; |
459 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | 728 | int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ |
729 | int cpu = octeon_cpu_for_coreid(coreid); | ||
460 | 730 | ||
461 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | 731 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); |
462 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | 732 | pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu); |
463 | en1 |= 1ull << bit; | 733 | set_bit(coreid, pen); |
464 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | 734 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen); |
465 | cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | ||
466 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | 735 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); |
467 | } | 736 | } |
468 | 737 | ||
@@ -470,286 +739,281 @@ static void octeon_irq_ciu1_enable(unsigned int irq) | |||
470 | * Watchdog interrupts are special. They are associated with a single | 739 | * Watchdog interrupts are special. They are associated with a single |
471 | * core, so we hardwire the affinity to that core. | 740 | * core, so we hardwire the affinity to that core. |
472 | */ | 741 | */ |
473 | static void octeon_irq_ciu1_wd_enable(unsigned int irq) | 742 | static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data) |
474 | { | 743 | { |
475 | unsigned long flags; | 744 | int coreid = data->irq - OCTEON_IRQ_WDOG0; |
476 | uint64_t en1; | 745 | int cpu = octeon_cpu_for_coreid(coreid); |
477 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | ||
478 | int coreid = bit; | ||
479 | 746 | ||
480 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | 747 | set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu)); |
481 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | 748 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid); |
482 | en1 |= 1ull << bit; | ||
483 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | ||
484 | cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | ||
485 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
486 | } | 749 | } |
487 | 750 | ||
488 | static void octeon_irq_ciu1_disable(unsigned int irq) | 751 | |
752 | static struct irq_chip octeon_irq_chip_ciu_wd_v2 = { | ||
753 | .name = "CIU-W", | ||
754 | .irq_enable = octeon_irq_ciu1_wd_enable_v2, | ||
755 | .irq_disable = octeon_irq_ciu_disable_all_v2, | ||
756 | .irq_mask = octeon_irq_ciu_disable_local_v2, | ||
757 | .irq_unmask = octeon_irq_ciu_enable_local_v2, | ||
758 | }; | ||
759 | |||
760 | static struct irq_chip octeon_irq_chip_ciu_wd = { | ||
761 | .name = "CIU-W", | ||
762 | .irq_enable = octeon_irq_ciu_wd_enable, | ||
763 | .irq_disable = octeon_irq_ciu_disable_all, | ||
764 | .irq_mask = octeon_irq_dummy_mask, | ||
765 | }; | ||
766 | |||
767 | static void octeon_irq_ip2_v1(void) | ||
489 | { | 768 | { |
490 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | 769 | const unsigned long core_id = cvmx_get_core_num(); |
491 | unsigned long flags; | 770 | u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); |
492 | uint64_t en1; | 771 | |
493 | int cpu; | 772 | ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); |
494 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | 773 | clear_c0_status(STATUSF_IP2); |
495 | for_each_online_cpu(cpu) { | 774 | if (likely(ciu_sum)) { |
496 | int coreid = octeon_coreid_for_cpu(cpu); | 775 | int bit = fls64(ciu_sum) - 1; |
497 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | 776 | int irq = octeon_irq_ciu_to_irq[0][bit]; |
498 | en1 &= ~(1ull << bit); | 777 | if (likely(irq)) |
499 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | 778 | do_IRQ(irq); |
779 | else | ||
780 | spurious_interrupt(); | ||
781 | } else { | ||
782 | spurious_interrupt(); | ||
500 | } | 783 | } |
501 | /* | 784 | set_c0_status(STATUSF_IP2); |
502 | * We need to do a read after the last update to make sure all | ||
503 | * of them are done. | ||
504 | */ | ||
505 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); | ||
506 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | ||
507 | } | 785 | } |
508 | 786 | ||
509 | /* | 787 | static void octeon_irq_ip2_v2(void) |
510 | * Enable the irq on the current core for chips that have the EN*_W1{S,C} | ||
511 | * registers. | ||
512 | */ | ||
513 | static void octeon_irq_ciu1_enable_v2(unsigned int irq) | ||
514 | { | 788 | { |
515 | int index; | 789 | const unsigned long core_id = cvmx_get_core_num(); |
516 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | 790 | u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2)); |
517 | struct irq_desc *desc = irq_to_desc(irq); | 791 | |
518 | 792 | ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror); | |
519 | if ((desc->status & IRQ_DISABLED) == 0) { | 793 | if (likely(ciu_sum)) { |
520 | index = next_coreid_for_irq(desc) * 2 + 1; | 794 | int bit = fls64(ciu_sum) - 1; |
521 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | 795 | int irq = octeon_irq_ciu_to_irq[0][bit]; |
796 | if (likely(irq)) | ||
797 | do_IRQ(irq); | ||
798 | else | ||
799 | spurious_interrupt(); | ||
800 | } else { | ||
801 | spurious_interrupt(); | ||
522 | } | 802 | } |
523 | } | 803 | } |
524 | 804 | static void octeon_irq_ip3_v1(void) | |
525 | /* | ||
526 | * Watchdog interrupts are special. They are associated with a single | ||
527 | * core, so we hardwire the affinity to that core. | ||
528 | */ | ||
529 | static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq) | ||
530 | { | 805 | { |
531 | int index; | 806 | u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); |
532 | int coreid = irq - OCTEON_IRQ_WDOG0; | 807 | |
533 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | 808 | ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); |
534 | struct irq_desc *desc = irq_to_desc(irq); | 809 | clear_c0_status(STATUSF_IP3); |
535 | 810 | if (likely(ciu_sum)) { | |
536 | if ((desc->status & IRQ_DISABLED) == 0) { | 811 | int bit = fls64(ciu_sum) - 1; |
537 | index = coreid * 2 + 1; | 812 | int irq = octeon_irq_ciu_to_irq[1][bit]; |
538 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | 813 | if (likely(irq)) |
814 | do_IRQ(irq); | ||
815 | else | ||
816 | spurious_interrupt(); | ||
817 | } else { | ||
818 | spurious_interrupt(); | ||
539 | } | 819 | } |
820 | set_c0_status(STATUSF_IP3); | ||
540 | } | 821 | } |
541 | 822 | ||
542 | /* | 823 | static void octeon_irq_ip3_v2(void) |
543 | * Disable the irq on the current core for chips that have the EN*_W1{S,C} | ||
544 | * registers. | ||
545 | */ | ||
546 | static void octeon_irq_ciu1_ack_v2(unsigned int irq) | ||
547 | { | 824 | { |
548 | int index = cvmx_get_core_num() * 2 + 1; | 825 | u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1); |
549 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | 826 | |
550 | 827 | ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror); | |
551 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | 828 | if (likely(ciu_sum)) { |
829 | int bit = fls64(ciu_sum) - 1; | ||
830 | int irq = octeon_irq_ciu_to_irq[1][bit]; | ||
831 | if (likely(irq)) | ||
832 | do_IRQ(irq); | ||
833 | else | ||
834 | spurious_interrupt(); | ||
835 | } else { | ||
836 | spurious_interrupt(); | ||
837 | } | ||
552 | } | 838 | } |
553 | 839 | ||
554 | /* | 840 | static void octeon_irq_ip4_mask(void) |
555 | * Disable the irq on the all cores for chips that have the EN*_W1{S,C} | ||
556 | * registers. | ||
557 | */ | ||
558 | static void octeon_irq_ciu1_disable_all_v2(unsigned int irq) | ||
559 | { | 841 | { |
560 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | 842 | clear_c0_status(STATUSF_IP4); |
561 | int index; | 843 | spurious_interrupt(); |
562 | int cpu; | ||
563 | for_each_online_cpu(cpu) { | ||
564 | index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
565 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
566 | } | ||
567 | } | 844 | } |
568 | 845 | ||
569 | #ifdef CONFIG_SMP | 846 | static void (*octeon_irq_ip2)(void); |
570 | static int octeon_irq_ciu1_set_affinity(unsigned int irq, | 847 | static void (*octeon_irq_ip3)(void); |
571 | const struct cpumask *dest) | 848 | static void (*octeon_irq_ip4)(void); |
572 | { | ||
573 | int cpu; | ||
574 | struct irq_desc *desc = irq_to_desc(irq); | ||
575 | int enable_one = (desc->status & IRQ_DISABLED) == 0; | ||
576 | unsigned long flags; | ||
577 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | ||
578 | 849 | ||
579 | /* | 850 | void __cpuinitdata (*octeon_irq_setup_secondary)(void); |
580 | * For non-v2 CIU, we will allow only single CPU affinity. | ||
581 | * This removes the need to do locking in the .ack/.eoi | ||
582 | * functions. | ||
583 | */ | ||
584 | if (cpumask_weight(dest) != 1) | ||
585 | return -EINVAL; | ||
586 | 851 | ||
587 | raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); | 852 | static void __cpuinit octeon_irq_percpu_enable(void) |
588 | for_each_online_cpu(cpu) { | 853 | { |
589 | int coreid = octeon_coreid_for_cpu(cpu); | 854 | irq_cpu_online(); |
590 | uint64_t en1 = | 855 | } |
591 | cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | 856 | |
592 | if (cpumask_test_cpu(cpu, dest) && enable_one) { | 857 | static void __cpuinit octeon_irq_init_ciu_percpu(void) |
593 | enable_one = 0; | 858 | { |
594 | en1 |= 1ull << bit; | 859 | int coreid = cvmx_get_core_num(); |
595 | } else { | ||
596 | en1 &= ~(1ull << bit); | ||
597 | } | ||
598 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | ||
599 | } | ||
600 | /* | 860 | /* |
601 | * We need to do a read after the last update to make sure all | 861 | * Disable All CIU Interrupts. The ones we need will be |
602 | * of them are done. | 862 | * enabled later. Read the SUM register so we know the write |
863 | * completed. | ||
603 | */ | 864 | */ |
604 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); | 865 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); |
605 | raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); | 866 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); |
606 | 867 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); | |
607 | return 0; | 868 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); |
869 | cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); | ||
608 | } | 870 | } |
609 | 871 | ||
610 | /* | 872 | static void __cpuinit octeon_irq_setup_secondary_ciu(void) |
611 | * Set affinity for the irq for chips that have the EN*_W1{S,C} | ||
612 | * registers. | ||
613 | */ | ||
614 | static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq, | ||
615 | const struct cpumask *dest) | ||
616 | { | 873 | { |
617 | int cpu; | ||
618 | int index; | ||
619 | struct irq_desc *desc = irq_to_desc(irq); | ||
620 | int enable_one = (desc->status & IRQ_DISABLED) == 0; | ||
621 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | ||
622 | for_each_online_cpu(cpu) { | ||
623 | index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
624 | if (cpumask_test_cpu(cpu, dest) && enable_one) { | ||
625 | enable_one = 0; | ||
626 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | ||
627 | } else { | ||
628 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
629 | } | ||
630 | } | ||
631 | return 0; | ||
632 | } | ||
633 | #endif | ||
634 | 874 | ||
635 | /* | 875 | __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0; |
636 | * Newer octeon chips have support for lockless CIU operation. | 876 | __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0; |
637 | */ | ||
638 | static struct irq_chip octeon_irq_chip_ciu1_v2 = { | ||
639 | .name = "CIU1", | ||
640 | .enable = octeon_irq_ciu1_enable_v2, | ||
641 | .disable = octeon_irq_ciu1_disable_all_v2, | ||
642 | .eoi = octeon_irq_ciu1_enable_v2, | ||
643 | #ifdef CONFIG_SMP | ||
644 | .set_affinity = octeon_irq_ciu1_set_affinity_v2, | ||
645 | #endif | ||
646 | }; | ||
647 | 877 | ||
648 | static struct irq_chip octeon_irq_chip_ciu1 = { | 878 | octeon_irq_init_ciu_percpu(); |
649 | .name = "CIU1", | 879 | octeon_irq_percpu_enable(); |
650 | .enable = octeon_irq_ciu1_enable, | ||
651 | .disable = octeon_irq_ciu1_disable, | ||
652 | .eoi = octeon_irq_ciu1_eoi, | ||
653 | #ifdef CONFIG_SMP | ||
654 | .set_affinity = octeon_irq_ciu1_set_affinity, | ||
655 | #endif | ||
656 | }; | ||
657 | 880 | ||
658 | static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = { | 881 | /* Enable the CIU lines */ |
659 | .name = "CIU1-W", | 882 | set_c0_status(STATUSF_IP3 | STATUSF_IP2); |
660 | .enable = octeon_irq_ciu1_wd_enable_v2, | 883 | clear_c0_status(STATUSF_IP4); |
661 | .disable = octeon_irq_ciu1_disable_all_v2, | 884 | } |
662 | .eoi = octeon_irq_ciu1_wd_enable_v2, | ||
663 | }; | ||
664 | 885 | ||
665 | static struct irq_chip octeon_irq_chip_ciu1_wd = { | 886 | static void __init octeon_irq_init_ciu(void) |
666 | .name = "CIU1-W", | 887 | { |
667 | .enable = octeon_irq_ciu1_wd_enable, | 888 | unsigned int i; |
668 | .disable = octeon_irq_ciu1_disable, | 889 | struct irq_chip *chip; |
669 | .eoi = octeon_irq_ciu1_eoi, | 890 | struct irq_chip *chip_edge; |
670 | }; | 891 | struct irq_chip *chip_mbox; |
892 | struct irq_chip *chip_wd; | ||
893 | |||
894 | octeon_irq_init_ciu_percpu(); | ||
895 | octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; | ||
671 | 896 | ||
672 | static void (*octeon_ciu0_ack)(unsigned int); | 897 | if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || |
673 | static void (*octeon_ciu1_ack)(unsigned int); | 898 | OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || |
899 | OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) || | ||
900 | OCTEON_IS_MODEL(OCTEON_CN6XXX)) { | ||
901 | octeon_irq_ip2 = octeon_irq_ip2_v2; | ||
902 | octeon_irq_ip3 = octeon_irq_ip3_v2; | ||
903 | chip = &octeon_irq_chip_ciu_v2; | ||
904 | chip_edge = &octeon_irq_chip_ciu_edge_v2; | ||
905 | chip_mbox = &octeon_irq_chip_ciu_mbox_v2; | ||
906 | chip_wd = &octeon_irq_chip_ciu_wd_v2; | ||
907 | } else { | ||
908 | octeon_irq_ip2 = octeon_irq_ip2_v1; | ||
909 | octeon_irq_ip3 = octeon_irq_ip3_v1; | ||
910 | chip = &octeon_irq_chip_ciu; | ||
911 | chip_edge = &octeon_irq_chip_ciu_edge; | ||
912 | chip_mbox = &octeon_irq_chip_ciu_mbox; | ||
913 | chip_wd = &octeon_irq_chip_ciu_wd; | ||
914 | } | ||
915 | octeon_irq_ip4 = octeon_irq_ip4_mask; | ||
916 | |||
917 | /* Mips internal */ | ||
918 | octeon_irq_init_core(); | ||
919 | |||
920 | /* CIU_0 */ | ||
921 | for (i = 0; i < 16; i++) | ||
922 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); | ||
923 | for (i = 0; i < 16; i++) | ||
924 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); | ||
925 | |||
926 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); | ||
927 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); | ||
928 | |||
929 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); | ||
930 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); | ||
931 | |||
932 | for (i = 0; i < 4; i++) | ||
933 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); | ||
934 | for (i = 0; i < 4; i++) | ||
935 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); | ||
936 | |||
937 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); | ||
938 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); | ||
939 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); | ||
940 | |||
941 | for (i = 0; i < 2; i++) | ||
942 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); | ||
943 | |||
944 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); | ||
945 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); | ||
946 | |||
947 | for (i = 0; i < 4; i++) | ||
948 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); | ||
949 | |||
950 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); | ||
951 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); | ||
952 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); | ||
953 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); | ||
954 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); | ||
955 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); | ||
956 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); | ||
957 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); | ||
958 | |||
959 | /* CIU_1 */ | ||
960 | for (i = 0; i < 16; i++) | ||
961 | octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); | ||
962 | |||
963 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); | ||
964 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); | ||
965 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); | ||
966 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); | ||
967 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); | ||
968 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); | ||
969 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); | ||
970 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); | ||
971 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); | ||
972 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); | ||
973 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); | ||
974 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); | ||
975 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); | ||
976 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); | ||
977 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); | ||
978 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); | ||
979 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); | ||
980 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); | ||
981 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); | ||
982 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); | ||
983 | |||
984 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); | ||
985 | |||
986 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); | ||
987 | |||
988 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); | ||
989 | |||
990 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); | ||
991 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); | ||
992 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); | ||
993 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); | ||
994 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); | ||
995 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); | ||
996 | octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); | ||
997 | |||
998 | /* Enable the CIU lines */ | ||
999 | set_c0_status(STATUSF_IP3 | STATUSF_IP2); | ||
1000 | clear_c0_status(STATUSF_IP4); | ||
1001 | } | ||
674 | 1002 | ||
675 | void __init arch_init_irq(void) | 1003 | void __init arch_init_irq(void) |
676 | { | 1004 | { |
677 | unsigned int irq; | ||
678 | struct irq_chip *chip0; | ||
679 | struct irq_chip *chip0_mbox; | ||
680 | struct irq_chip *chip1; | ||
681 | struct irq_chip *chip1_wd; | ||
682 | |||
683 | #ifdef CONFIG_SMP | 1005 | #ifdef CONFIG_SMP |
684 | /* Set the default affinity to the boot cpu. */ | 1006 | /* Set the default affinity to the boot cpu. */ |
685 | cpumask_clear(irq_default_affinity); | 1007 | cpumask_clear(irq_default_affinity); |
686 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); | 1008 | cpumask_set_cpu(smp_processor_id(), irq_default_affinity); |
687 | #endif | 1009 | #endif |
688 | 1010 | octeon_irq_init_ciu(); | |
689 | if (NR_IRQS < OCTEON_IRQ_LAST) | ||
690 | pr_err("octeon_irq_init: NR_IRQS is set too low\n"); | ||
691 | |||
692 | if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || | ||
693 | OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || | ||
694 | OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { | ||
695 | octeon_ciu0_ack = octeon_irq_ciu0_ack_v2; | ||
696 | octeon_ciu1_ack = octeon_irq_ciu1_ack_v2; | ||
697 | chip0 = &octeon_irq_chip_ciu0_v2; | ||
698 | chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2; | ||
699 | chip1 = &octeon_irq_chip_ciu1_v2; | ||
700 | chip1_wd = &octeon_irq_chip_ciu1_wd_v2; | ||
701 | } else { | ||
702 | octeon_ciu0_ack = octeon_irq_ciu0_ack; | ||
703 | octeon_ciu1_ack = octeon_irq_ciu1_ack; | ||
704 | chip0 = &octeon_irq_chip_ciu0; | ||
705 | chip0_mbox = &octeon_irq_chip_ciu0_mbox; | ||
706 | chip1 = &octeon_irq_chip_ciu1; | ||
707 | chip1_wd = &octeon_irq_chip_ciu1_wd; | ||
708 | } | ||
709 | |||
710 | /* 0 - 15 reserved for i8259 master and slave controller. */ | ||
711 | |||
712 | /* 17 - 23 Mips internal */ | ||
713 | for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) { | ||
714 | set_irq_chip_and_handler(irq, &octeon_irq_chip_core, | ||
715 | handle_percpu_irq); | ||
716 | } | ||
717 | |||
718 | /* 24 - 87 CIU_INT_SUM0 */ | ||
719 | for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { | ||
720 | switch (irq) { | ||
721 | case OCTEON_IRQ_MBOX0: | ||
722 | case OCTEON_IRQ_MBOX1: | ||
723 | set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq); | ||
724 | break; | ||
725 | default: | ||
726 | set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq); | ||
727 | break; | ||
728 | } | ||
729 | } | ||
730 | |||
731 | /* 88 - 151 CIU_INT_SUM1 */ | ||
732 | for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++) | ||
733 | set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq); | ||
734 | |||
735 | for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++) | ||
736 | set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq); | ||
737 | |||
738 | set_c0_status(0x300 << 2); | ||
739 | } | 1011 | } |
740 | 1012 | ||
741 | asmlinkage void plat_irq_dispatch(void) | 1013 | asmlinkage void plat_irq_dispatch(void) |
742 | { | 1014 | { |
743 | const unsigned long core_id = cvmx_get_core_num(); | ||
744 | const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2); | ||
745 | const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2); | ||
746 | const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1; | ||
747 | const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1); | ||
748 | unsigned long cop0_cause; | 1015 | unsigned long cop0_cause; |
749 | unsigned long cop0_status; | 1016 | unsigned long cop0_status; |
750 | uint64_t ciu_en; | ||
751 | uint64_t ciu_sum; | ||
752 | unsigned int irq; | ||
753 | 1017 | ||
754 | while (1) { | 1018 | while (1) { |
755 | cop0_cause = read_c0_cause(); | 1019 | cop0_cause = read_c0_cause(); |
@@ -757,33 +1021,16 @@ asmlinkage void plat_irq_dispatch(void) | |||
757 | cop0_cause &= cop0_status; | 1021 | cop0_cause &= cop0_status; |
758 | cop0_cause &= ST0_IM; | 1022 | cop0_cause &= ST0_IM; |
759 | 1023 | ||
760 | if (unlikely(cop0_cause & STATUSF_IP2)) { | 1024 | if (unlikely(cop0_cause & STATUSF_IP2)) |
761 | ciu_sum = cvmx_read_csr(ciu_sum0_address); | 1025 | octeon_irq_ip2(); |
762 | ciu_en = cvmx_read_csr(ciu_en0_address); | 1026 | else if (unlikely(cop0_cause & STATUSF_IP3)) |
763 | ciu_sum &= ciu_en; | 1027 | octeon_irq_ip3(); |
764 | if (likely(ciu_sum)) { | 1028 | else if (unlikely(cop0_cause & STATUSF_IP4)) |
765 | irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1; | 1029 | octeon_irq_ip4(); |
766 | octeon_ciu0_ack(irq); | 1030 | else if (likely(cop0_cause)) |
767 | do_IRQ(irq); | ||
768 | } else { | ||
769 | spurious_interrupt(); | ||
770 | } | ||
771 | } else if (unlikely(cop0_cause & STATUSF_IP3)) { | ||
772 | ciu_sum = cvmx_read_csr(ciu_sum1_address); | ||
773 | ciu_en = cvmx_read_csr(ciu_en1_address); | ||
774 | ciu_sum &= ciu_en; | ||
775 | if (likely(ciu_sum)) { | ||
776 | irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1; | ||
777 | octeon_ciu1_ack(irq); | ||
778 | do_IRQ(irq); | ||
779 | } else { | ||
780 | spurious_interrupt(); | ||
781 | } | ||
782 | } else if (likely(cop0_cause)) { | ||
783 | do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); | 1031 | do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); |
784 | } else { | 1032 | else |
785 | break; | 1033 | break; |
786 | } | ||
787 | } | 1034 | } |
788 | } | 1035 | } |
789 | 1036 | ||
@@ -791,83 +1038,7 @@ asmlinkage void plat_irq_dispatch(void) | |||
791 | 1038 | ||
792 | void fixup_irqs(void) | 1039 | void fixup_irqs(void) |
793 | { | 1040 | { |
794 | int irq; | 1041 | irq_cpu_offline(); |
795 | struct irq_desc *desc; | ||
796 | cpumask_t new_affinity; | ||
797 | unsigned long flags; | ||
798 | int do_set_affinity; | ||
799 | int cpu; | ||
800 | |||
801 | cpu = smp_processor_id(); | ||
802 | |||
803 | for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) | ||
804 | octeon_irq_core_disable_local(irq); | ||
805 | |||
806 | for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) { | ||
807 | desc = irq_to_desc(irq); | ||
808 | switch (irq) { | ||
809 | case OCTEON_IRQ_MBOX0: | ||
810 | case OCTEON_IRQ_MBOX1: | ||
811 | /* The eoi function will disable them on this CPU. */ | ||
812 | desc->chip->eoi(irq); | ||
813 | break; | ||
814 | case OCTEON_IRQ_WDOG0: | ||
815 | case OCTEON_IRQ_WDOG1: | ||
816 | case OCTEON_IRQ_WDOG2: | ||
817 | case OCTEON_IRQ_WDOG3: | ||
818 | case OCTEON_IRQ_WDOG4: | ||
819 | case OCTEON_IRQ_WDOG5: | ||
820 | case OCTEON_IRQ_WDOG6: | ||
821 | case OCTEON_IRQ_WDOG7: | ||
822 | case OCTEON_IRQ_WDOG8: | ||
823 | case OCTEON_IRQ_WDOG9: | ||
824 | case OCTEON_IRQ_WDOG10: | ||
825 | case OCTEON_IRQ_WDOG11: | ||
826 | case OCTEON_IRQ_WDOG12: | ||
827 | case OCTEON_IRQ_WDOG13: | ||
828 | case OCTEON_IRQ_WDOG14: | ||
829 | case OCTEON_IRQ_WDOG15: | ||
830 | /* | ||
831 | * These have special per CPU semantics and | ||
832 | * are handled in the watchdog driver. | ||
833 | */ | ||
834 | break; | ||
835 | default: | ||
836 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
837 | /* | ||
838 | * If this irq has an action, it is in use and | ||
839 | * must be migrated if it has affinity to this | ||
840 | * cpu. | ||
841 | */ | ||
842 | if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) { | ||
843 | if (cpumask_weight(desc->affinity) > 1) { | ||
844 | /* | ||
845 | * It has multi CPU affinity, | ||
846 | * just remove this CPU from | ||
847 | * the affinity set. | ||
848 | */ | ||
849 | cpumask_copy(&new_affinity, desc->affinity); | ||
850 | cpumask_clear_cpu(cpu, &new_affinity); | ||
851 | } else { | ||
852 | /* | ||
853 | * Otherwise, put it on lowest | ||
854 | * numbered online CPU. | ||
855 | */ | ||
856 | cpumask_clear(&new_affinity); | ||
857 | cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); | ||
858 | } | ||
859 | do_set_affinity = 1; | ||
860 | } else { | ||
861 | do_set_affinity = 0; | ||
862 | } | ||
863 | raw_spin_unlock_irqrestore(&desc->lock, flags); | ||
864 | |||
865 | if (do_set_affinity) | ||
866 | irq_set_affinity(irq, &new_affinity); | ||
867 | |||
868 | break; | ||
869 | } | ||
870 | } | ||
871 | } | 1042 | } |
872 | 1043 | ||
873 | #endif /* CONFIG_HOTPLUG_CPU */ | 1044 | #endif /* CONFIG_HOTPLUG_CPU */ |
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index b0c3686c96dd..8b139bf4a1b5 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c | |||
@@ -420,7 +420,6 @@ void octeon_user_io_init(void) | |||
420 | void __init prom_init(void) | 420 | void __init prom_init(void) |
421 | { | 421 | { |
422 | struct cvmx_sysinfo *sysinfo; | 422 | struct cvmx_sysinfo *sysinfo; |
423 | const int coreid = cvmx_get_core_num(); | ||
424 | int i; | 423 | int i; |
425 | int argc; | 424 | int argc; |
426 | #ifdef CONFIG_CAVIUM_RESERVE32 | 425 | #ifdef CONFIG_CAVIUM_RESERVE32 |
@@ -537,17 +536,6 @@ void __init prom_init(void) | |||
537 | 536 | ||
538 | octeon_uart = octeon_get_boot_uart(); | 537 | octeon_uart = octeon_get_boot_uart(); |
539 | 538 | ||
540 | /* | ||
541 | * Disable All CIU Interrupts. The ones we need will be | ||
542 | * enabled later. Read the SUM register so we know the write | ||
543 | * completed. | ||
544 | */ | ||
545 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); | ||
546 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); | ||
547 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); | ||
548 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); | ||
549 | cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); | ||
550 | |||
551 | #ifdef CONFIG_SMP | 539 | #ifdef CONFIG_SMP |
552 | octeon_write_lcd("LinuxSMP"); | 540 | octeon_write_lcd("LinuxSMP"); |
553 | #else | 541 | #else |
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 391cefe556b3..ba78b21cc8d0 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c | |||
@@ -171,41 +171,19 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle) | |||
171 | * After we've done initial boot, this function is called to allow the | 171 | * After we've done initial boot, this function is called to allow the |
172 | * board code to clean up state, if needed | 172 | * board code to clean up state, if needed |
173 | */ | 173 | */ |
174 | static void octeon_init_secondary(void) | 174 | static void __cpuinit octeon_init_secondary(void) |
175 | { | 175 | { |
176 | const int coreid = cvmx_get_core_num(); | ||
177 | union cvmx_ciu_intx_sum0 interrupt_enable; | ||
178 | unsigned int sr; | 176 | unsigned int sr; |
179 | 177 | ||
180 | #ifdef CONFIG_HOTPLUG_CPU | ||
181 | struct linux_app_boot_info *labi; | ||
182 | |||
183 | labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); | ||
184 | |||
185 | if (labi->labi_signature != LABI_SIGNATURE) | ||
186 | panic("The bootloader version on this board is incorrect."); | ||
187 | #endif | ||
188 | |||
189 | sr = set_c0_status(ST0_BEV); | 178 | sr = set_c0_status(ST0_BEV); |
190 | write_c0_ebase((u32)ebase); | 179 | write_c0_ebase((u32)ebase); |
191 | write_c0_status(sr); | 180 | write_c0_status(sr); |
192 | 181 | ||
193 | octeon_check_cpu_bist(); | 182 | octeon_check_cpu_bist(); |
194 | octeon_init_cvmcount(); | 183 | octeon_init_cvmcount(); |
195 | /* | 184 | |
196 | pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid); | 185 | octeon_irq_setup_secondary(); |
197 | */ | 186 | raw_local_irq_enable(); |
198 | /* Enable Mailbox interrupts to this core. These are the only | ||
199 | interrupts allowed on line 3 */ | ||
200 | cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff); | ||
201 | interrupt_enable.u64 = 0; | ||
202 | interrupt_enable.s.mbox = 0x3; | ||
203 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64); | ||
204 | cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); | ||
205 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); | ||
206 | cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); | ||
207 | /* Enable core interrupt processing for 2,3 and 7 */ | ||
208 | set_c0_status(0x8c01); | ||
209 | } | 187 | } |
210 | 188 | ||
211 | /** | 189 | /** |
@@ -214,6 +192,15 @@ static void octeon_init_secondary(void) | |||
214 | */ | 192 | */ |
215 | void octeon_prepare_cpus(unsigned int max_cpus) | 193 | void octeon_prepare_cpus(unsigned int max_cpus) |
216 | { | 194 | { |
195 | #ifdef CONFIG_HOTPLUG_CPU | ||
196 | struct linux_app_boot_info *labi; | ||
197 | |||
198 | labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER); | ||
199 | |||
200 | if (labi->labi_signature != LABI_SIGNATURE) | ||
201 | panic("The bootloader version on this board is incorrect."); | ||
202 | #endif | ||
203 | |||
217 | cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); | 204 | cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); |
218 | if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, | 205 | if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, |
219 | "mailbox0", mailbox_interrupt)) { | 206 | "mailbox0", mailbox_interrupt)) { |
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index 8d9a5fc607e4..824e08c73798 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c | |||
@@ -68,10 +68,10 @@ void __init init_ioasic_irqs(int base) | |||
68 | fast_iob(); | 68 | fast_iob(); |
69 | 69 | ||
70 | for (i = base; i < base + IO_INR_DMA; i++) | 70 | for (i = base; i < base + IO_INR_DMA; i++) |
71 | set_irq_chip_and_handler(i, &ioasic_irq_type, | 71 | irq_set_chip_and_handler(i, &ioasic_irq_type, |
72 | handle_level_irq); | 72 | handle_level_irq); |
73 | for (; i < base + IO_IRQ_LINES; i++) | 73 | for (; i < base + IO_IRQ_LINES; i++) |
74 | set_irq_chip(i, &ioasic_dma_irq_type); | 74 | irq_set_chip(i, &ioasic_dma_irq_type); |
75 | 75 | ||
76 | ioasic_irq_base = base; | 76 | ioasic_irq_base = base; |
77 | } | 77 | } |
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index ef31d98c4fb8..37199f742c45 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c | |||
@@ -73,7 +73,7 @@ void __init init_kn02_irqs(int base) | |||
73 | iob(); | 73 | iob(); |
74 | 74 | ||
75 | for (i = base; i < base + KN02_IRQ_LINES; i++) | 75 | for (i = base; i < base + KN02_IRQ_LINES; i++) |
76 | set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq); | 76 | irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq); |
77 | 77 | ||
78 | kn02_irq_base = base; | 78 | kn02_irq_base = base; |
79 | } | 79 | } |
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 9b1207ae2256..3dbd7a5a6ad3 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c | |||
@@ -69,7 +69,7 @@ void emma2rh_irq_init(void) | |||
69 | u32 i; | 69 | u32 i; |
70 | 70 | ||
71 | for (i = 0; i < NUM_EMMA2RH_IRQ; i++) | 71 | for (i = 0; i < NUM_EMMA2RH_IRQ; i++) |
72 | set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, | 72 | irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, |
73 | &emma2rh_irq_controller, | 73 | &emma2rh_irq_controller, |
74 | handle_level_irq, "level"); | 74 | handle_level_irq, "level"); |
75 | } | 75 | } |
@@ -105,7 +105,7 @@ void emma2rh_sw_irq_init(void) | |||
105 | u32 i; | 105 | u32 i; |
106 | 106 | ||
107 | for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) | 107 | for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) |
108 | set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, | 108 | irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, |
109 | &emma2rh_sw_irq_controller, | 109 | &emma2rh_sw_irq_controller, |
110 | handle_level_irq, "level"); | 110 | handle_level_irq, "level"); |
111 | } | 111 | } |
@@ -162,7 +162,7 @@ void emma2rh_gpio_irq_init(void) | |||
162 | u32 i; | 162 | u32 i; |
163 | 163 | ||
164 | for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) | 164 | for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) |
165 | set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, | 165 | irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, |
166 | &emma2rh_gpio_irq_controller, | 166 | &emma2rh_gpio_irq_controller, |
167 | handle_edge_irq, "edge"); | 167 | handle_edge_irq, "edge"); |
168 | } | 168 | } |
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h index 6ddab8aef644..5b05f186e395 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h | |||
@@ -11,172 +11,91 @@ | |||
11 | #define NR_IRQS OCTEON_IRQ_LAST | 11 | #define NR_IRQS OCTEON_IRQ_LAST |
12 | #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 | 12 | #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 |
13 | 13 | ||
14 | /* 0 - 7 represent the i8259 master */ | 14 | enum octeon_irq { |
15 | #define OCTEON_IRQ_I8259M0 0 | 15 | /* 1 - 8 represent the 8 MIPS standard interrupt sources */ |
16 | #define OCTEON_IRQ_I8259M1 1 | 16 | OCTEON_IRQ_SW0 = 1, |
17 | #define OCTEON_IRQ_I8259M2 2 | 17 | OCTEON_IRQ_SW1, |
18 | #define OCTEON_IRQ_I8259M3 3 | 18 | /* CIU0, CUI2, CIU4 are 3, 4, 5 */ |
19 | #define OCTEON_IRQ_I8259M4 4 | 19 | OCTEON_IRQ_5 = 6, |
20 | #define OCTEON_IRQ_I8259M5 5 | 20 | OCTEON_IRQ_PERF, |
21 | #define OCTEON_IRQ_I8259M6 6 | 21 | OCTEON_IRQ_TIMER, |
22 | #define OCTEON_IRQ_I8259M7 7 | 22 | /* sources in CIU_INTX_EN0 */ |
23 | /* 8 - 15 represent the i8259 slave */ | 23 | OCTEON_IRQ_WORKQ0, |
24 | #define OCTEON_IRQ_I8259S0 8 | 24 | OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16, |
25 | #define OCTEON_IRQ_I8259S1 9 | 25 | OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16, |
26 | #define OCTEON_IRQ_I8259S2 10 | 26 | OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15, |
27 | #define OCTEON_IRQ_I8259S3 11 | 27 | OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16, |
28 | #define OCTEON_IRQ_I8259S4 12 | 28 | OCTEON_IRQ_MBOX1, |
29 | #define OCTEON_IRQ_I8259S5 13 | 29 | OCTEON_IRQ_UART0, |
30 | #define OCTEON_IRQ_I8259S6 14 | 30 | OCTEON_IRQ_UART1, |
31 | #define OCTEON_IRQ_I8259S7 15 | 31 | OCTEON_IRQ_UART2, |
32 | /* 16 - 23 represent the 8 MIPS standard interrupt sources */ | 32 | OCTEON_IRQ_PCI_INT0, |
33 | #define OCTEON_IRQ_SW0 16 | 33 | OCTEON_IRQ_PCI_INT1, |
34 | #define OCTEON_IRQ_SW1 17 | 34 | OCTEON_IRQ_PCI_INT2, |
35 | #define OCTEON_IRQ_CIU0 18 | 35 | OCTEON_IRQ_PCI_INT3, |
36 | #define OCTEON_IRQ_CIU1 19 | 36 | OCTEON_IRQ_PCI_MSI0, |
37 | #define OCTEON_IRQ_CIU4 20 | 37 | OCTEON_IRQ_PCI_MSI1, |
38 | #define OCTEON_IRQ_5 21 | 38 | OCTEON_IRQ_PCI_MSI2, |
39 | #define OCTEON_IRQ_PERF 22 | 39 | OCTEON_IRQ_PCI_MSI3, |
40 | #define OCTEON_IRQ_TIMER 23 | 40 | |
41 | /* 24 - 87 represent the sources in CIU_INTX_EN0 */ | 41 | OCTEON_IRQ_TWSI, |
42 | #define OCTEON_IRQ_WORKQ0 24 | 42 | OCTEON_IRQ_TWSI2, |
43 | #define OCTEON_IRQ_WORKQ1 25 | 43 | OCTEON_IRQ_RML, |
44 | #define OCTEON_IRQ_WORKQ2 26 | 44 | OCTEON_IRQ_TRACE0, |
45 | #define OCTEON_IRQ_WORKQ3 27 | 45 | OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4, |
46 | #define OCTEON_IRQ_WORKQ4 28 | 46 | OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5, |
47 | #define OCTEON_IRQ_WORKQ5 29 | 47 | OCTEON_IRQ_KEY_ZERO, |
48 | #define OCTEON_IRQ_WORKQ6 30 | 48 | OCTEON_IRQ_TIMER0, |
49 | #define OCTEON_IRQ_WORKQ7 31 | 49 | OCTEON_IRQ_TIMER1, |
50 | #define OCTEON_IRQ_WORKQ8 32 | 50 | OCTEON_IRQ_TIMER2, |
51 | #define OCTEON_IRQ_WORKQ9 33 | 51 | OCTEON_IRQ_TIMER3, |
52 | #define OCTEON_IRQ_WORKQ10 34 | 52 | OCTEON_IRQ_USB0, |
53 | #define OCTEON_IRQ_WORKQ11 35 | 53 | OCTEON_IRQ_USB1, |
54 | #define OCTEON_IRQ_WORKQ12 36 | 54 | OCTEON_IRQ_PCM, |
55 | #define OCTEON_IRQ_WORKQ13 37 | 55 | OCTEON_IRQ_MPI, |
56 | #define OCTEON_IRQ_WORKQ14 38 | 56 | OCTEON_IRQ_POWIQ, |
57 | #define OCTEON_IRQ_WORKQ15 39 | 57 | OCTEON_IRQ_IPDPPTHR, |
58 | #define OCTEON_IRQ_GPIO0 40 | 58 | OCTEON_IRQ_MII0, |
59 | #define OCTEON_IRQ_GPIO1 41 | 59 | OCTEON_IRQ_MII1, |
60 | #define OCTEON_IRQ_GPIO2 42 | 60 | OCTEON_IRQ_BOOTDMA, |
61 | #define OCTEON_IRQ_GPIO3 43 | 61 | |
62 | #define OCTEON_IRQ_GPIO4 44 | 62 | OCTEON_IRQ_NAND, |
63 | #define OCTEON_IRQ_GPIO5 45 | 63 | OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ |
64 | #define OCTEON_IRQ_GPIO6 46 | 64 | OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */ |
65 | #define OCTEON_IRQ_GPIO7 47 | 65 | OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */ |
66 | #define OCTEON_IRQ_GPIO8 48 | 66 | OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */ |
67 | #define OCTEON_IRQ_GPIO9 49 | 67 | OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */ |
68 | #define OCTEON_IRQ_GPIO10 50 | 68 | OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */ |
69 | #define OCTEON_IRQ_GPIO11 51 | 69 | OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */ |
70 | #define OCTEON_IRQ_GPIO12 52 | 70 | OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */ |
71 | #define OCTEON_IRQ_GPIO13 53 | 71 | OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */ |
72 | #define OCTEON_IRQ_GPIO14 54 | 72 | OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */ |
73 | #define OCTEON_IRQ_GPIO15 55 | 73 | OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */ |
74 | #define OCTEON_IRQ_MBOX0 56 | 74 | OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */ |
75 | #define OCTEON_IRQ_MBOX1 57 | 75 | OCTEON_IRQ_DFA, /* Summary of DFA */ |
76 | #define OCTEON_IRQ_UART0 58 | 76 | OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */ |
77 | #define OCTEON_IRQ_UART1 59 | 77 | OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */ |
78 | #define OCTEON_IRQ_PCI_INT0 60 | 78 | OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */ |
79 | #define OCTEON_IRQ_PCI_INT1 61 | 79 | OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */ |
80 | #define OCTEON_IRQ_PCI_INT2 62 | 80 | OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5, |
81 | #define OCTEON_IRQ_PCI_INT3 63 | 81 | OCTEON_IRQ_PTP, |
82 | #define OCTEON_IRQ_PCI_MSI0 64 | 82 | OCTEON_IRQ_PEM0, |
83 | #define OCTEON_IRQ_PCI_MSI1 65 | 83 | OCTEON_IRQ_PEM1, |
84 | #define OCTEON_IRQ_PCI_MSI2 66 | 84 | OCTEON_IRQ_SRIO0, |
85 | #define OCTEON_IRQ_PCI_MSI3 67 | 85 | OCTEON_IRQ_SRIO1, |
86 | #define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ | 86 | OCTEON_IRQ_LMC0, |
87 | #define OCTEON_IRQ_TWSI 69 | 87 | OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */ |
88 | #define OCTEON_IRQ_RML 70 | 88 | OCTEON_IRQ_RST, |
89 | #define OCTEON_IRQ_TRACE 71 | 89 | }; |
90 | #define OCTEON_IRQ_GMX_DRP0 72 | ||
91 | #define OCTEON_IRQ_GMX_DRP1 73 | ||
92 | #define OCTEON_IRQ_IPD_DRP 74 | ||
93 | #define OCTEON_IRQ_KEY_ZERO 75 | ||
94 | #define OCTEON_IRQ_TIMER0 76 | ||
95 | #define OCTEON_IRQ_TIMER1 77 | ||
96 | #define OCTEON_IRQ_TIMER2 78 | ||
97 | #define OCTEON_IRQ_TIMER3 79 | ||
98 | #define OCTEON_IRQ_USB0 80 | ||
99 | #define OCTEON_IRQ_PCM 81 | ||
100 | #define OCTEON_IRQ_MPI 82 | ||
101 | #define OCTEON_IRQ_TWSI2 83 | ||
102 | #define OCTEON_IRQ_POWIQ 84 | ||
103 | #define OCTEON_IRQ_IPDPPTHR 85 | ||
104 | #define OCTEON_IRQ_MII0 86 | ||
105 | #define OCTEON_IRQ_BOOTDMA 87 | ||
106 | /* 88 - 151 represent the sources in CIU_INTX_EN1 */ | ||
107 | #define OCTEON_IRQ_WDOG0 88 | ||
108 | #define OCTEON_IRQ_WDOG1 89 | ||
109 | #define OCTEON_IRQ_WDOG2 90 | ||
110 | #define OCTEON_IRQ_WDOG3 91 | ||
111 | #define OCTEON_IRQ_WDOG4 92 | ||
112 | #define OCTEON_IRQ_WDOG5 93 | ||
113 | #define OCTEON_IRQ_WDOG6 94 | ||
114 | #define OCTEON_IRQ_WDOG7 95 | ||
115 | #define OCTEON_IRQ_WDOG8 96 | ||
116 | #define OCTEON_IRQ_WDOG9 97 | ||
117 | #define OCTEON_IRQ_WDOG10 98 | ||
118 | #define OCTEON_IRQ_WDOG11 99 | ||
119 | #define OCTEON_IRQ_WDOG12 100 | ||
120 | #define OCTEON_IRQ_WDOG13 101 | ||
121 | #define OCTEON_IRQ_WDOG14 102 | ||
122 | #define OCTEON_IRQ_WDOG15 103 | ||
123 | #define OCTEON_IRQ_UART2 104 | ||
124 | #define OCTEON_IRQ_USB1 105 | ||
125 | #define OCTEON_IRQ_MII1 106 | ||
126 | #define OCTEON_IRQ_RESERVED107 107 | ||
127 | #define OCTEON_IRQ_RESERVED108 108 | ||
128 | #define OCTEON_IRQ_RESERVED109 109 | ||
129 | #define OCTEON_IRQ_RESERVED110 110 | ||
130 | #define OCTEON_IRQ_RESERVED111 111 | ||
131 | #define OCTEON_IRQ_RESERVED112 112 | ||
132 | #define OCTEON_IRQ_RESERVED113 113 | ||
133 | #define OCTEON_IRQ_RESERVED114 114 | ||
134 | #define OCTEON_IRQ_RESERVED115 115 | ||
135 | #define OCTEON_IRQ_RESERVED116 116 | ||
136 | #define OCTEON_IRQ_RESERVED117 117 | ||
137 | #define OCTEON_IRQ_RESERVED118 118 | ||
138 | #define OCTEON_IRQ_RESERVED119 119 | ||
139 | #define OCTEON_IRQ_RESERVED120 120 | ||
140 | #define OCTEON_IRQ_RESERVED121 121 | ||
141 | #define OCTEON_IRQ_RESERVED122 122 | ||
142 | #define OCTEON_IRQ_RESERVED123 123 | ||
143 | #define OCTEON_IRQ_RESERVED124 124 | ||
144 | #define OCTEON_IRQ_RESERVED125 125 | ||
145 | #define OCTEON_IRQ_RESERVED126 126 | ||
146 | #define OCTEON_IRQ_RESERVED127 127 | ||
147 | #define OCTEON_IRQ_RESERVED128 128 | ||
148 | #define OCTEON_IRQ_RESERVED129 129 | ||
149 | #define OCTEON_IRQ_RESERVED130 130 | ||
150 | #define OCTEON_IRQ_RESERVED131 131 | ||
151 | #define OCTEON_IRQ_RESERVED132 132 | ||
152 | #define OCTEON_IRQ_RESERVED133 133 | ||
153 | #define OCTEON_IRQ_RESERVED134 134 | ||
154 | #define OCTEON_IRQ_RESERVED135 135 | ||
155 | #define OCTEON_IRQ_RESERVED136 136 | ||
156 | #define OCTEON_IRQ_RESERVED137 137 | ||
157 | #define OCTEON_IRQ_RESERVED138 138 | ||
158 | #define OCTEON_IRQ_RESERVED139 139 | ||
159 | #define OCTEON_IRQ_RESERVED140 140 | ||
160 | #define OCTEON_IRQ_RESERVED141 141 | ||
161 | #define OCTEON_IRQ_RESERVED142 142 | ||
162 | #define OCTEON_IRQ_RESERVED143 143 | ||
163 | #define OCTEON_IRQ_RESERVED144 144 | ||
164 | #define OCTEON_IRQ_RESERVED145 145 | ||
165 | #define OCTEON_IRQ_RESERVED146 146 | ||
166 | #define OCTEON_IRQ_RESERVED147 147 | ||
167 | #define OCTEON_IRQ_RESERVED148 148 | ||
168 | #define OCTEON_IRQ_RESERVED149 149 | ||
169 | #define OCTEON_IRQ_RESERVED150 150 | ||
170 | #define OCTEON_IRQ_RESERVED151 151 | ||
171 | 90 | ||
172 | #ifdef CONFIG_PCI_MSI | 91 | #ifdef CONFIG_PCI_MSI |
173 | /* 152 - 215 represent the MSI interrupts 0-63 */ | 92 | /* 152 - 407 represent the MSI interrupts 0-255 */ |
174 | #define OCTEON_IRQ_MSI_BIT0 152 | 93 | #define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) |
175 | #define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) | ||
176 | 94 | ||
177 | #define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) | 95 | #define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) |
96 | #define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) | ||
178 | #else | 97 | #else |
179 | #define OCTEON_IRQ_LAST 152 | 98 | #define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1) |
180 | #endif | 99 | #endif |
181 | 100 | ||
182 | #endif | 101 | #endif |
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index 6b34afd0d4e7..f72f768cd3a4 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h | |||
@@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo; | |||
257 | 257 | ||
258 | extern uint64_t octeon_bootloader_entry_addr; | 258 | extern uint64_t octeon_bootloader_entry_addr; |
259 | 259 | ||
260 | extern void (*octeon_irq_setup_secondary)(void); | ||
261 | |||
260 | #endif /* __ASM_OCTEON_OCTEON_H */ | 262 | #endif /* __ASM_OCTEON_OCTEON_H */ |
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h index dae22c1d2c82..fa2e37ea2be1 100644 --- a/arch/mips/include/asm/unistd.h +++ b/arch/mips/include/asm/unistd.h | |||
@@ -1005,7 +1005,7 @@ | |||
1005 | #define __NR_name_to_handle_at (__NR_Linux + 303) | 1005 | #define __NR_name_to_handle_at (__NR_Linux + 303) |
1006 | #define __NR_open_by_handle_at (__NR_Linux + 304) | 1006 | #define __NR_open_by_handle_at (__NR_Linux + 304) |
1007 | #define __NR_clock_adjtime (__NR_Linux + 305) | 1007 | #define __NR_clock_adjtime (__NR_Linux + 305) |
1008 | #define __NR_clock_adjtime (__NR_Linux + 306) | 1008 | #define __NR_syncfs (__NR_Linux + 306) |
1009 | 1009 | ||
1010 | /* | 1010 | /* |
1011 | * Offset of the last N32 flavoured syscall | 1011 | * Offset of the last N32 flavoured syscall |
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 40f7c6b1e260..260df4750949 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c | |||
@@ -56,7 +56,7 @@ void __init init_r4030_ints(void) | |||
56 | int i; | 56 | int i; |
57 | 57 | ||
58 | for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++) | 58 | for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++) |
59 | set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); | 59 | irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq); |
60 | 60 | ||
61 | r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); | 61 | r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); |
62 | r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ | 62 | r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ |
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c index bd2fc29b95e0..73031f7fc827 100644 --- a/arch/mips/jz4740/gpio.c +++ b/arch/mips/jz4740/gpio.c | |||
@@ -306,7 +306,7 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc) | |||
306 | uint32_t flag; | 306 | uint32_t flag; |
307 | unsigned int gpio_irq; | 307 | unsigned int gpio_irq; |
308 | unsigned int gpio_bank; | 308 | unsigned int gpio_bank; |
309 | struct jz_gpio_chip *chip = get_irq_desc_data(desc); | 309 | struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc); |
310 | 310 | ||
311 | gpio_bank = JZ4740_IRQ_GPIO0 - irq; | 311 | gpio_bank = JZ4740_IRQ_GPIO0 - irq; |
312 | 312 | ||
@@ -416,7 +416,7 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) | |||
416 | chip->wakeup &= ~IRQ_TO_BIT(data->irq); | 416 | chip->wakeup &= ~IRQ_TO_BIT(data->irq); |
417 | spin_unlock(&chip->lock); | 417 | spin_unlock(&chip->lock); |
418 | 418 | ||
419 | set_irq_wake(chip->irq, on); | 419 | irq_set_irq_wake(chip->irq, on); |
420 | return 0; | 420 | return 0; |
421 | } | 421 | } |
422 | 422 | ||
@@ -510,14 +510,14 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) | |||
510 | gpiochip_add(&chip->gpio_chip); | 510 | gpiochip_add(&chip->gpio_chip); |
511 | 511 | ||
512 | chip->irq = JZ4740_IRQ_INTC_GPIO(id); | 512 | chip->irq = JZ4740_IRQ_INTC_GPIO(id); |
513 | set_irq_data(chip->irq, chip); | 513 | irq_set_handler_data(chip->irq, chip); |
514 | set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); | 514 | irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler); |
515 | 515 | ||
516 | for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { | 516 | for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { |
517 | irq_set_lockdep_class(irq, &gpio_lock_class); | 517 | irq_set_lockdep_class(irq, &gpio_lock_class); |
518 | set_irq_chip_data(irq, chip); | 518 | irq_set_chip_data(irq, chip); |
519 | set_irq_chip_and_handler(irq, &jz_gpio_irq_chip, | 519 | irq_set_chip_and_handler(irq, &jz_gpio_irq_chip, |
520 | handle_level_irq); | 520 | handle_level_irq); |
521 | } | 521 | } |
522 | 522 | ||
523 | return 0; | 523 | return 0; |
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index dcc5593a9389..d82c0c430e03 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c | |||
@@ -104,8 +104,8 @@ void __init arch_init_irq(void) | |||
104 | writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); | 104 | writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); |
105 | 105 | ||
106 | for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { | 106 | for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { |
107 | set_irq_chip_data(i, (void *)IRQ_BIT(i)); | 107 | irq_set_chip_data(i, (void *)IRQ_BIT(i)); |
108 | set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); | 108 | irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq); |
109 | } | 109 | } |
110 | 110 | ||
111 | setup_irq(2, &jz4740_cascade_action); | 111 | setup_irq(2, &jz4740_cascade_action); |
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index e221662bb80c..c018696765d4 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c | |||
@@ -110,7 +110,7 @@ int i8259A_irq_pending(unsigned int irq) | |||
110 | void make_8259A_irq(unsigned int irq) | 110 | void make_8259A_irq(unsigned int irq) |
111 | { | 111 | { |
112 | disable_irq_nosync(irq); | 112 | disable_irq_nosync(irq); |
113 | set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); | 113 | irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq); |
114 | enable_irq(irq); | 114 | enable_irq(irq); |
115 | } | 115 | } |
116 | 116 | ||
@@ -336,8 +336,8 @@ void __init init_i8259_irqs(void) | |||
336 | init_8259A(0); | 336 | init_8259A(0); |
337 | 337 | ||
338 | for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) { | 338 | for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) { |
339 | set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); | 339 | irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq); |
340 | set_irq_probe(i); | 340 | irq_set_probe(i); |
341 | } | 341 | } |
342 | 342 | ||
343 | setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); | 343 | setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); |
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 43cd9628251a..0c527f652196 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c | |||
@@ -229,7 +229,7 @@ static void __init gic_basic_init(int numintrs, int numvpes, | |||
229 | vpe_local_setup(numvpes); | 229 | vpe_local_setup(numvpes); |
230 | 230 | ||
231 | for (i = _irqbase; i < (_irqbase + numintrs); i++) | 231 | for (i = _irqbase; i < (_irqbase + numintrs); i++) |
232 | set_irq_chip(i, &gic_irq_controller); | 232 | irq_set_chip(i, &gic_irq_controller); |
233 | } | 233 | } |
234 | 234 | ||
235 | void __init gic_init(unsigned long gic_base_addr, | 235 | void __init gic_init(unsigned long gic_base_addr, |
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c index 7fd176fa367a..883fc6cead36 100644 --- a/arch/mips/kernel/irq-gt641xx.c +++ b/arch/mips/kernel/irq-gt641xx.c | |||
@@ -126,6 +126,6 @@ void __init gt641xx_irq_init(void) | |||
126 | * bit31: logical or of bits[25:1]. | 126 | * bit31: logical or of bits[25:1]. |
127 | */ | 127 | */ |
128 | for (i = 1; i < 30; i++) | 128 | for (i = 1; i < 30; i++) |
129 | set_irq_chip_and_handler(GT641XX_IRQ_BASE + i, | 129 | irq_set_chip_and_handler(GT641XX_IRQ_BASE + i, |
130 | >641xx_irq_chip, handle_level_irq); | 130 | >641xx_irq_chip, handle_level_irq); |
131 | } | 131 | } |
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index fc800cd9947e..0c6afeed89d2 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -137,16 +137,20 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma | |||
137 | 137 | ||
138 | switch (imp->im_type) { | 138 | switch (imp->im_type) { |
139 | case MSC01_IRQ_EDGE: | 139 | case MSC01_IRQ_EDGE: |
140 | set_irq_chip_and_handler_name(irqbase + n, | 140 | irq_set_chip_and_handler_name(irqbase + n, |
141 | &msc_edgeirq_type, handle_edge_irq, "edge"); | 141 | &msc_edgeirq_type, |
142 | handle_edge_irq, | ||
143 | "edge"); | ||
142 | if (cpu_has_veic) | 144 | if (cpu_has_veic) |
143 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 145 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
144 | else | 146 | else |
145 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 147 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
146 | break; | 148 | break; |
147 | case MSC01_IRQ_LEVEL: | 149 | case MSC01_IRQ_LEVEL: |
148 | set_irq_chip_and_handler_name(irqbase+n, | 150 | irq_set_chip_and_handler_name(irqbase + n, |
149 | &msc_levelirq_type, handle_level_irq, "level"); | 151 | &msc_levelirq_type, |
152 | handle_level_irq, | ||
153 | "level"); | ||
150 | if (cpu_has_veic) | 154 | if (cpu_has_veic) |
151 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
152 | else | 156 | else |
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index fd24fd98b041..a8a8977d5887 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c | |||
@@ -45,6 +45,6 @@ void __init rm7k_cpu_irq_init(void) | |||
45 | clear_c0_intcontrol(0x00000f00); /* Mask all */ | 45 | clear_c0_intcontrol(0x00000f00); /* Mask all */ |
46 | 46 | ||
47 | for (i = base; i < base + 4; i++) | 47 | for (i = base; i < base + 4; i++) |
48 | set_irq_chip_and_handler(i, &rm7k_irq_controller, | 48 | irq_set_chip_and_handler(i, &rm7k_irq_controller, |
49 | handle_percpu_irq); | 49 | handle_percpu_irq); |
50 | } | 50 | } |
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index ca463ec9bad5..38874a4b9255 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c | |||
@@ -98,10 +98,10 @@ void __init rm9k_cpu_irq_init(void) | |||
98 | clear_c0_intcontrol(0x0000f000); /* Mask all */ | 98 | clear_c0_intcontrol(0x0000f000); /* Mask all */ |
99 | 99 | ||
100 | for (i = base; i < base + 4; i++) | 100 | for (i = base; i < base + 4; i++) |
101 | set_irq_chip_and_handler(i, &rm9k_irq_controller, | 101 | irq_set_chip_and_handler(i, &rm9k_irq_controller, |
102 | handle_level_irq); | 102 | handle_level_irq); |
103 | 103 | ||
104 | rm9000_perfcount_irq = base + 1; | 104 | rm9000_perfcount_irq = base + 1; |
105 | set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, | 105 | irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, |
106 | handle_percpu_irq); | 106 | handle_percpu_irq); |
107 | } | 107 | } |
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 1b68ebe1b458..9b734d74ae8e 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c | |||
@@ -102,7 +102,7 @@ void __init init_IRQ(void) | |||
102 | #endif | 102 | #endif |
103 | 103 | ||
104 | for (i = 0; i < NR_IRQS; i++) | 104 | for (i = 0; i < NR_IRQS; i++) |
105 | set_irq_noprobe(i); | 105 | irq_set_noprobe(i); |
106 | 106 | ||
107 | arch_init_irq(); | 107 | arch_init_irq(); |
108 | 108 | ||
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index fd945c56bc33..6e71b284f6c9 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -109,10 +109,10 @@ void __init mips_cpu_irq_init(void) | |||
109 | */ | 109 | */ |
110 | if (cpu_has_mipsmt) | 110 | if (cpu_has_mipsmt) |
111 | for (i = irq_base; i < irq_base + 2; i++) | 111 | for (i = irq_base; i < irq_base + 2; i++) |
112 | set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, | 112 | irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller, |
113 | handle_percpu_irq); | 113 | handle_percpu_irq); |
114 | 114 | ||
115 | for (i = irq_base + 2; i < irq_base + 8; i++) | 115 | for (i = irq_base + 2; i < irq_base + 8; i++) |
116 | set_irq_chip_and_handler(i, &mips_cpu_irq_controller, | 116 | irq_set_chip_and_handler(i, &mips_cpu_irq_controller, |
117 | handle_percpu_irq); | 117 | handle_percpu_irq); |
118 | } | 118 | } |
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c index 526e1581549a..b0c55b50218e 100644 --- a/arch/mips/kernel/irq_txx9.c +++ b/arch/mips/kernel/irq_txx9.c | |||
@@ -154,8 +154,8 @@ void __init txx9_irq_init(unsigned long baseaddr) | |||
154 | for (i = 0; i < TXx9_MAX_IR; i++) { | 154 | for (i = 0; i < TXx9_MAX_IR; i++) { |
155 | txx9irq[i].level = 4; /* middle level */ | 155 | txx9irq[i].level = 4; /* middle level */ |
156 | txx9irq[i].mode = TXx9_IRCR_LOW; | 156 | txx9irq[i].mode = TXx9_IRCR_LOW; |
157 | set_irq_chip_and_handler(TXX9_IRQ_BASE + i, | 157 | irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip, |
158 | &txx9_irq_chip, handle_level_irq); | 158 | handle_level_irq); |
159 | } | 159 | } |
160 | 160 | ||
161 | /* mask all IRC interrupts */ | 161 | /* mask all IRC interrupts */ |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index f7e2c7807d7b..5a88cc4ccd5a 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -1146,7 +1146,7 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe) | |||
1146 | 1146 | ||
1147 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); | 1147 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); |
1148 | 1148 | ||
1149 | set_irq_handler(cpu_ipi_irq, handle_percpu_irq); | 1149 | irq_set_handler(cpu_ipi_irq, handle_percpu_irq); |
1150 | } | 1150 | } |
1151 | 1151 | ||
1152 | /* | 1152 | /* |
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index 670e3e70d198..de4c165515d7 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c | |||
@@ -128,7 +128,7 @@ void __init arch_init_irq(void) | |||
128 | mips_cpu_irq_init(); | 128 | mips_cpu_irq_init(); |
129 | 129 | ||
130 | for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++) | 130 | for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++) |
131 | set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); | 131 | irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq); |
132 | 132 | ||
133 | setup_irq(LASAT_CASCADE_IRQ, &cascade); | 133 | setup_irq(LASAT_CASCADE_IRQ, &cascade); |
134 | } | 134 | } |
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c index 1549361696ad..f27d7ccca92a 100644 --- a/arch/mips/loongson/common/bonito-irq.c +++ b/arch/mips/loongson/common/bonito-irq.c | |||
@@ -44,7 +44,8 @@ void bonito_irq_init(void) | |||
44 | u32 i; | 44 | u32 i; |
45 | 45 | ||
46 | for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) | 46 | for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) |
47 | set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); | 47 | irq_set_chip_and_handler(i, &bonito_irq_type, |
48 | handle_level_irq); | ||
48 | 49 | ||
49 | #ifdef CONFIG_CPU_LOONGSON2E | 50 | #ifdef CONFIG_CPU_LOONGSON2E |
50 | setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); | 51 | setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); |
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index b79b24afe3a2..9027061f0ead 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c | |||
@@ -472,7 +472,7 @@ static void __init fill_ipi_map(void) | |||
472 | void __init arch_init_ipiirq(int irq, struct irqaction *action) | 472 | void __init arch_init_ipiirq(int irq, struct irqaction *action) |
473 | { | 473 | { |
474 | setup_irq(irq, action); | 474 | setup_irq(irq, action); |
475 | set_irq_handler(irq, handle_percpu_irq); | 475 | irq_set_handler(irq, handle_percpu_irq); |
476 | } | 476 | } |
477 | 477 | ||
478 | void __init arch_init_irq(void) | 478 | void __init arch_init_irq(void) |
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 3c6f190aa61c..1620b83cd13e 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c | |||
@@ -119,7 +119,7 @@ static void __init plat_perf_setup(void) | |||
119 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); | 119 | set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); |
120 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; | 120 | mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
121 | #ifdef CONFIG_SMP | 121 | #ifdef CONFIG_SMP |
122 | set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); | 122 | irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq); |
123 | #endif | 123 | #endif |
124 | } | 124 | } |
125 | } | 125 | } |
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c index d8080499872a..5d530f89d872 100644 --- a/arch/mips/pci/msi-octeon.c +++ b/arch/mips/pci/msi-octeon.c | |||
@@ -172,7 +172,7 @@ msi_irq_allocated: | |||
172 | pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, | 172 | pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, |
173 | control); | 173 | control); |
174 | 174 | ||
175 | set_irq_msi(irq, desc); | 175 | irq_set_msi_desc(irq, desc); |
176 | write_msi_msg(irq, &msg); | 176 | write_msi_msg(irq, &msg); |
177 | return 0; | 177 | return 0; |
178 | } | 178 | } |
@@ -259,11 +259,11 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); | |||
259 | static u64 msi_rcv_reg[4]; | 259 | static u64 msi_rcv_reg[4]; |
260 | static u64 mis_ena_reg[4]; | 260 | static u64 mis_ena_reg[4]; |
261 | 261 | ||
262 | static void octeon_irq_msi_enable_pcie(unsigned int irq) | 262 | static void octeon_irq_msi_enable_pcie(struct irq_data *data) |
263 | { | 263 | { |
264 | u64 en; | 264 | u64 en; |
265 | unsigned long flags; | 265 | unsigned long flags; |
266 | int msi_number = irq - OCTEON_IRQ_MSI_BIT0; | 266 | int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; |
267 | int irq_index = msi_number >> 6; | 267 | int irq_index = msi_number >> 6; |
268 | int irq_bit = msi_number & 0x3f; | 268 | int irq_bit = msi_number & 0x3f; |
269 | 269 | ||
@@ -275,11 +275,11 @@ static void octeon_irq_msi_enable_pcie(unsigned int irq) | |||
275 | raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); | 275 | raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); |
276 | } | 276 | } |
277 | 277 | ||
278 | static void octeon_irq_msi_disable_pcie(unsigned int irq) | 278 | static void octeon_irq_msi_disable_pcie(struct irq_data *data) |
279 | { | 279 | { |
280 | u64 en; | 280 | u64 en; |
281 | unsigned long flags; | 281 | unsigned long flags; |
282 | int msi_number = irq - OCTEON_IRQ_MSI_BIT0; | 282 | int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0; |
283 | int irq_index = msi_number >> 6; | 283 | int irq_index = msi_number >> 6; |
284 | int irq_bit = msi_number & 0x3f; | 284 | int irq_bit = msi_number & 0x3f; |
285 | 285 | ||
@@ -293,11 +293,11 @@ static void octeon_irq_msi_disable_pcie(unsigned int irq) | |||
293 | 293 | ||
294 | static struct irq_chip octeon_irq_chip_msi_pcie = { | 294 | static struct irq_chip octeon_irq_chip_msi_pcie = { |
295 | .name = "MSI", | 295 | .name = "MSI", |
296 | .enable = octeon_irq_msi_enable_pcie, | 296 | .irq_enable = octeon_irq_msi_enable_pcie, |
297 | .disable = octeon_irq_msi_disable_pcie, | 297 | .irq_disable = octeon_irq_msi_disable_pcie, |
298 | }; | 298 | }; |
299 | 299 | ||
300 | static void octeon_irq_msi_enable_pci(unsigned int irq) | 300 | static void octeon_irq_msi_enable_pci(struct irq_data *data) |
301 | { | 301 | { |
302 | /* | 302 | /* |
303 | * Octeon PCI doesn't have the ability to mask/unmask MSI | 303 | * Octeon PCI doesn't have the ability to mask/unmask MSI |
@@ -308,15 +308,15 @@ static void octeon_irq_msi_enable_pci(unsigned int irq) | |||
308 | */ | 308 | */ |
309 | } | 309 | } |
310 | 310 | ||
311 | static void octeon_irq_msi_disable_pci(unsigned int irq) | 311 | static void octeon_irq_msi_disable_pci(struct irq_data *data) |
312 | { | 312 | { |
313 | /* See comment in enable */ | 313 | /* See comment in enable */ |
314 | } | 314 | } |
315 | 315 | ||
316 | static struct irq_chip octeon_irq_chip_msi_pci = { | 316 | static struct irq_chip octeon_irq_chip_msi_pci = { |
317 | .name = "MSI", | 317 | .name = "MSI", |
318 | .enable = octeon_irq_msi_enable_pci, | 318 | .irq_enable = octeon_irq_msi_enable_pci, |
319 | .disable = octeon_irq_msi_disable_pci, | 319 | .irq_disable = octeon_irq_msi_disable_pci, |
320 | }; | 320 | }; |
321 | 321 | ||
322 | /* | 322 | /* |
@@ -388,7 +388,7 @@ int __init octeon_msi_initialize(void) | |||
388 | } | 388 | } |
389 | 389 | ||
390 | for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) | 390 | for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) |
391 | set_irq_chip_and_handler(irq, msi, handle_simple_irq); | 391 | irq_set_chip_and_handler(irq, msi, handle_simple_irq); |
392 | 392 | ||
393 | if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { | 393 | if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { |
394 | if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, | 394 | if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, |
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c index 352f29d9226f..c4fa2d775d8b 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c | |||
@@ -182,7 +182,7 @@ void __init msp_cic_irq_init(void) | |||
182 | 182 | ||
183 | /* initialize all the IRQ descriptors */ | 183 | /* initialize all the IRQ descriptors */ |
184 | for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) { | 184 | for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) { |
185 | set_irq_chip_and_handler(i, &msp_cic_irq_controller, | 185 | irq_set_chip_and_handler(i, &msp_cic_irq_controller, |
186 | handle_level_irq); | 186 | handle_level_irq); |
187 | #ifdef CONFIG_MIPS_MT_SMTC | 187 | #ifdef CONFIG_MIPS_MT_SMTC |
188 | /* Mask of CIC interrupt */ | 188 | /* Mask of CIC interrupt */ |
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c index 8f51e4adc438..5bbcc47da6b9 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c | |||
@@ -77,7 +77,7 @@ void __init msp_slp_irq_init(void) | |||
77 | 77 | ||
78 | /* initialize all the IRQ descriptors */ | 78 | /* initialize all the IRQ descriptors */ |
79 | for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) | 79 | for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) |
80 | set_irq_chip_and_handler(i, &msp_slp_irq_controller, | 80 | irq_set_chip_and_handler(i, &msp_slp_irq_controller, |
81 | handle_level_irq); | 81 | handle_level_irq); |
82 | } | 82 | } |
83 | 83 | ||
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c index 43a9e26e1c69..bec17901ff03 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_smp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c | |||
@@ -64,7 +64,7 @@ static struct irqaction irq_call = { | |||
64 | void __init arch_init_ipiirq(int irq, struct irqaction *action) | 64 | void __init arch_init_ipiirq(int irq, struct irqaction *action) |
65 | { | 65 | { |
66 | setup_irq(irq, action); | 66 | setup_irq(irq, action); |
67 | set_irq_handler(irq, handle_percpu_irq); | 67 | irq_set_handler(irq, handle_percpu_irq); |
68 | } | 68 | } |
69 | 69 | ||
70 | void __init msp_vsmp_int_init(void) | 70 | void __init msp_vsmp_int_init(void) |
diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c index b226bcb0a2f4..adc171c8846f 100644 --- a/arch/mips/pnx833x/common/interrupts.c +++ b/arch/mips/pnx833x/common/interrupts.c | |||
@@ -259,11 +259,13 @@ void __init arch_init_irq(void) | |||
259 | /* Set IRQ information in irq_desc */ | 259 | /* Set IRQ information in irq_desc */ |
260 | for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { | 260 | for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { |
261 | pnx833x_hard_disable_pic_irq(irq); | 261 | pnx833x_hard_disable_pic_irq(irq); |
262 | set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); | 262 | irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type, |
263 | handle_simple_irq); | ||
263 | } | 264 | } |
264 | 265 | ||
265 | for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) | 266 | for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) |
266 | set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); | 267 | irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type, |
268 | handle_simple_irq); | ||
267 | 269 | ||
268 | /* Set PIC priority limiter register to 0 */ | 270 | /* Set PIC priority limiter register to 0 */ |
269 | PNX833X_PIC_INT_PRIORITY = 0; | 271 | PNX833X_PIC_INT_PRIORITY = 0; |
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c index dbdc35c3531d..6b93c81779c1 100644 --- a/arch/mips/pnx8550/common/int.c +++ b/arch/mips/pnx8550/common/int.c | |||
@@ -183,7 +183,7 @@ void __init arch_init_irq(void) | |||
183 | int configPR; | 183 | int configPR; |
184 | 184 | ||
185 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) | 185 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) |
186 | set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); | 186 | irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); |
187 | 187 | ||
188 | /* init of GIC/IPC interrupts */ | 188 | /* init of GIC/IPC interrupts */ |
189 | /* should be done before cp0 since cp0 init enables the GIC int */ | 189 | /* should be done before cp0 since cp0 init enables the GIC int */ |
@@ -206,7 +206,7 @@ void __init arch_init_irq(void) | |||
206 | /* mask/priority is still 0 so we will not get any | 206 | /* mask/priority is still 0 so we will not get any |
207 | * interrupts until it is unmasked */ | 207 | * interrupts until it is unmasked */ |
208 | 208 | ||
209 | set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); | 209 | irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); |
210 | } | 210 | } |
211 | 211 | ||
212 | /* Priority level 0 */ | 212 | /* Priority level 0 */ |
@@ -215,20 +215,20 @@ void __init arch_init_irq(void) | |||
215 | /* Set int vector table address */ | 215 | /* Set int vector table address */ |
216 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; | 216 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; |
217 | 217 | ||
218 | set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, | 218 | irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, |
219 | handle_level_irq); | 219 | handle_level_irq); |
220 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); | 220 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); |
221 | 221 | ||
222 | /* init of Timer interrupts */ | 222 | /* init of Timer interrupts */ |
223 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) | 223 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) |
224 | set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); | 224 | irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); |
225 | 225 | ||
226 | /* Stop Timer 1-3 */ | 226 | /* Stop Timer 1-3 */ |
227 | configPR = read_c0_config7(); | 227 | configPR = read_c0_config7(); |
228 | configPR |= 0x00000038; | 228 | configPR |= 0x00000038; |
229 | write_c0_config7(configPR); | 229 | write_c0_config7(configPR); |
230 | 230 | ||
231 | set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, | 231 | irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, |
232 | handle_level_irq); | 232 | handle_level_irq); |
233 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); | 233 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); |
234 | } | 234 | } |
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c index 6f1c8ef6a719..7fb97fb0931e 100644 --- a/arch/mips/powertv/asic/irq_asic.c +++ b/arch/mips/powertv/asic/irq_asic.c | |||
@@ -112,5 +112,5 @@ void __init asic_irq_init(void) | |||
112 | * Initialize interrupt handlers. | 112 | * Initialize interrupt handlers. |
113 | */ | 113 | */ |
114 | for (i = 0; i < NR_IRQS; i++) | 114 | for (i = 0; i < NR_IRQS; i++) |
115 | set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); | 115 | irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq); |
116 | } | 116 | } |
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c index b32a768da894..7c6db74e3fad 100644 --- a/arch/mips/rb532/irq.c +++ b/arch/mips/rb532/irq.c | |||
@@ -207,8 +207,8 @@ void __init arch_init_irq(void) | |||
207 | pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); | 207 | pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); |
208 | 208 | ||
209 | for (i = 0; i < RC32434_NR_IRQS; i++) | 209 | for (i = 0; i < RC32434_NR_IRQS; i++) |
210 | set_irq_chip_and_handler(i, &rc32434_irq_type, | 210 | irq_set_chip_and_handler(i, &rc32434_irq_type, |
211 | handle_level_irq); | 211 | handle_level_irq); |
212 | } | 212 | } |
213 | 213 | ||
214 | /* Main Interrupt dispatcher */ | 214 | /* Main Interrupt dispatcher */ |
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index e6e64750e90a..476423a01296 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c | |||
@@ -312,7 +312,7 @@ void __init arch_init_irq(void) | |||
312 | else | 312 | else |
313 | handler = &ip22_local3_irq_type; | 313 | handler = &ip22_local3_irq_type; |
314 | 314 | ||
315 | set_irq_chip_and_handler(i, handler, handle_level_irq); | 315 | irq_set_chip_and_handler(i, handler, handle_level_irq); |
316 | } | 316 | } |
317 | 317 | ||
318 | /* vector handler. this register the IRQ as non-sharable */ | 318 | /* vector handler. this register the IRQ as non-sharable */ |
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index f2d09d7700dd..11488719dd97 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c | |||
@@ -337,7 +337,7 @@ static struct irq_chip bridge_irq_type = { | |||
337 | 337 | ||
338 | void __devinit register_bridge_irq(unsigned int irq) | 338 | void __devinit register_bridge_irq(unsigned int irq) |
339 | { | 339 | { |
340 | set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); | 340 | irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); |
341 | } | 341 | } |
342 | 342 | ||
343 | int __devinit request_bridge_irq(struct bridge_controller *bc) | 343 | int __devinit request_bridge_irq(struct bridge_controller *bc) |
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index c01f558a2a09..a152538d3c97 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c | |||
@@ -153,7 +153,7 @@ static void __init hub_rt_clock_event_global_init(void) | |||
153 | panic("Allocation of irq number for timer failed"); | 153 | panic("Allocation of irq number for timer failed"); |
154 | } while (xchg(&rt_timer_irq, irq)); | 154 | } while (xchg(&rt_timer_irq, irq)); |
155 | 155 | ||
156 | set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq); | 156 | irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq); |
157 | setup_irq(irq, &hub_rt_irqaction); | 157 | setup_irq(irq, &hub_rt_irqaction); |
158 | } | 158 | } |
159 | 159 | ||
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index e0a3ce4a8d48..c65ea76d56c7 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c | |||
@@ -451,43 +451,51 @@ void __init arch_init_irq(void) | |||
451 | for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { | 451 | for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { |
452 | switch (irq) { | 452 | switch (irq) { |
453 | case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: | 453 | case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: |
454 | set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, | 454 | irq_set_chip_and_handler_name(irq, |
455 | handle_level_irq, "level"); | 455 | &ip32_mace_interrupt, |
456 | handle_level_irq, | ||
457 | "level"); | ||
456 | break; | 458 | break; |
457 | 459 | ||
458 | case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: | 460 | case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: |
459 | set_irq_chip_and_handler_name(irq, | 461 | irq_set_chip_and_handler_name(irq, |
460 | &ip32_macepci_interrupt, handle_level_irq, | 462 | &ip32_macepci_interrupt, |
461 | "level"); | 463 | handle_level_irq, |
464 | "level"); | ||
462 | break; | 465 | break; |
463 | 466 | ||
464 | case CRIME_CPUERR_IRQ: | 467 | case CRIME_CPUERR_IRQ: |
465 | case CRIME_MEMERR_IRQ: | 468 | case CRIME_MEMERR_IRQ: |
466 | set_irq_chip_and_handler_name(irq, | 469 | irq_set_chip_and_handler_name(irq, |
467 | &crime_level_interrupt, handle_level_irq, | 470 | &crime_level_interrupt, |
468 | "level"); | 471 | handle_level_irq, |
472 | "level"); | ||
469 | break; | 473 | break; |
470 | 474 | ||
471 | case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: | 475 | case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: |
472 | case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: | 476 | case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: |
473 | case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: | 477 | case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: |
474 | case CRIME_VICE_IRQ: | 478 | case CRIME_VICE_IRQ: |
475 | set_irq_chip_and_handler_name(irq, | 479 | irq_set_chip_and_handler_name(irq, |
476 | &crime_edge_interrupt, handle_edge_irq, "edge"); | 480 | &crime_edge_interrupt, |
481 | handle_edge_irq, | ||
482 | "edge"); | ||
477 | break; | 483 | break; |
478 | 484 | ||
479 | case MACEISA_PARALLEL_IRQ: | 485 | case MACEISA_PARALLEL_IRQ: |
480 | case MACEISA_SERIAL1_TDMAPR_IRQ: | 486 | case MACEISA_SERIAL1_TDMAPR_IRQ: |
481 | case MACEISA_SERIAL2_TDMAPR_IRQ: | 487 | case MACEISA_SERIAL2_TDMAPR_IRQ: |
482 | set_irq_chip_and_handler_name(irq, | 488 | irq_set_chip_and_handler_name(irq, |
483 | &ip32_maceisa_edge_interrupt, handle_edge_irq, | 489 | &ip32_maceisa_edge_interrupt, |
484 | "edge"); | 490 | handle_edge_irq, |
491 | "edge"); | ||
485 | break; | 492 | break; |
486 | 493 | ||
487 | default: | 494 | default: |
488 | set_irq_chip_and_handler_name(irq, | 495 | irq_set_chip_and_handler_name(irq, |
489 | &ip32_maceisa_level_interrupt, handle_level_irq, | 496 | &ip32_maceisa_level_interrupt, |
490 | "level"); | 497 | handle_level_irq, |
498 | "level"); | ||
491 | break; | 499 | break; |
492 | } | 500 | } |
493 | } | 501 | } |
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 89e8188a4665..09740d60e187 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c | |||
@@ -216,7 +216,8 @@ void __init init_bcm1480_irqs(void) | |||
216 | int i; | 216 | int i; |
217 | 217 | ||
218 | for (i = 0; i < BCM1480_NR_IRQS; i++) { | 218 | for (i = 0; i < BCM1480_NR_IRQS; i++) { |
219 | set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq); | 219 | irq_set_chip_and_handler(i, &bcm1480_irq_type, |
220 | handle_level_irq); | ||
220 | bcm1480_irq_owner[i] = 0; | 221 | bcm1480_irq_owner[i] = 0; |
221 | } | 222 | } |
222 | } | 223 | } |
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index fd269ea8d8a8..be4460a5f6a8 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c | |||
@@ -190,7 +190,8 @@ void __init init_sb1250_irqs(void) | |||
190 | int i; | 190 | int i; |
191 | 191 | ||
192 | for (i = 0; i < SB1250_NR_IRQS; i++) { | 192 | for (i = 0; i < SB1250_NR_IRQS; i++) { |
193 | set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq); | 193 | irq_set_chip_and_handler(i, &sb1250_irq_type, |
194 | handle_level_irq); | ||
194 | sb1250_irq_owner[i] = 0; | 195 | sb1250_irq_owner[i] = 0; |
195 | } | 196 | } |
196 | } | 197 | } |
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c index 72b94155778d..c48194c3073b 100644 --- a/arch/mips/sni/a20r.c +++ b/arch/mips/sni/a20r.c | |||
@@ -209,7 +209,7 @@ void __init sni_a20r_irq_init(void) | |||
209 | int i; | 209 | int i; |
210 | 210 | ||
211 | for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) | 211 | for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) |
212 | set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq); | 212 | irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq); |
213 | sni_hwint = a20r_hwint; | 213 | sni_hwint = a20r_hwint; |
214 | change_c0_status(ST0_IM, IE_IRQ0); | 214 | change_c0_status(ST0_IM, IE_IRQ0); |
215 | setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); | 215 | setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); |
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index cfcc68abc5b2..ed3b3d317358 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c | |||
@@ -296,7 +296,7 @@ void __init sni_pcimt_irq_init(void) | |||
296 | mips_cpu_irq_init(); | 296 | mips_cpu_irq_init(); |
297 | /* Actually we've got more interrupts to handle ... */ | 297 | /* Actually we've got more interrupts to handle ... */ |
298 | for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) | 298 | for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) |
299 | set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); | 299 | irq_set_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); |
300 | sni_hwint = sni_pcimt_hwint; | 300 | sni_hwint = sni_pcimt_hwint; |
301 | change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); | 301 | change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); |
302 | } | 302 | } |
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 0846e99a6efe..b5246373d16b 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c | |||
@@ -238,7 +238,7 @@ void __init sni_pcit_irq_init(void) | |||
238 | 238 | ||
239 | mips_cpu_irq_init(); | 239 | mips_cpu_irq_init(); |
240 | for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) | 240 | for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) |
241 | set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); | 241 | irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); |
242 | *(volatile u32 *)SNI_PCIT_INT_REG = 0; | 242 | *(volatile u32 *)SNI_PCIT_INT_REG = 0; |
243 | sni_hwint = sni_pcit_hwint; | 243 | sni_hwint = sni_pcit_hwint; |
244 | change_c0_status(ST0_IM, IE_IRQ1); | 244 | change_c0_status(ST0_IM, IE_IRQ1); |
@@ -251,7 +251,7 @@ void __init sni_pcit_cplus_irq_init(void) | |||
251 | 251 | ||
252 | mips_cpu_irq_init(); | 252 | mips_cpu_irq_init(); |
253 | for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) | 253 | for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) |
254 | set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); | 254 | irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq); |
255 | *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; | 255 | *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; |
256 | sni_hwint = sni_pcit_hwint_cplus; | 256 | sni_hwint = sni_pcit_hwint_cplus; |
257 | change_c0_status(ST0_IM, IE_IRQ0); | 257 | change_c0_status(ST0_IM, IE_IRQ0); |
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index f05d8e593300..a7e5a6d917b1 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c | |||
@@ -413,7 +413,7 @@ void __init sni_rm200_i8259_irqs(void) | |||
413 | sni_rm200_init_8259A(); | 413 | sni_rm200_init_8259A(); |
414 | 414 | ||
415 | for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) | 415 | for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) |
416 | set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip, | 416 | irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip, |
417 | handle_level_irq); | 417 | handle_level_irq); |
418 | 418 | ||
419 | setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); | 419 | setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); |
@@ -477,7 +477,7 @@ void __init sni_rm200_irq_init(void) | |||
477 | mips_cpu_irq_init(); | 477 | mips_cpu_irq_init(); |
478 | /* Actually we've got more interrupts to handle ... */ | 478 | /* Actually we've got more interrupts to handle ... */ |
479 | for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) | 479 | for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) |
480 | set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq); | 480 | irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq); |
481 | sni_hwint = sni_rm200_hwint; | 481 | sni_hwint = sni_rm200_hwint; |
482 | change_c0_status(ST0_IM, IE_IRQ0); | 482 | change_c0_status(ST0_IM, IE_IRQ0); |
483 | setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); | 483 | setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); |
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c index e1828e8bcaef..7e3ac5782da4 100644 --- a/arch/mips/txx9/generic/irq_tx4927.c +++ b/arch/mips/txx9/generic/irq_tx4927.c | |||
@@ -35,7 +35,7 @@ void __init tx4927_irq_init(void) | |||
35 | 35 | ||
36 | mips_cpu_irq_init(); | 36 | mips_cpu_irq_init(); |
37 | txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); | 37 | txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); |
38 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, | 38 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, |
39 | handle_simple_irq); | 39 | handle_simple_irq); |
40 | /* raise priority for errors, timers, SIO */ | 40 | /* raise priority for errors, timers, SIO */ |
41 | txx9_irq_set_pri(TX4927_IR_ECCERR, 7); | 41 | txx9_irq_set_pri(TX4927_IR_ECCERR, 7); |
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c index a6e6e805097a..aace85653329 100644 --- a/arch/mips/txx9/generic/irq_tx4938.c +++ b/arch/mips/txx9/generic/irq_tx4938.c | |||
@@ -23,7 +23,7 @@ void __init tx4938_irq_init(void) | |||
23 | 23 | ||
24 | mips_cpu_irq_init(); | 24 | mips_cpu_irq_init(); |
25 | txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); | 25 | txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); |
26 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, | 26 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, |
27 | handle_simple_irq); | 27 | handle_simple_irq); |
28 | /* raise priority for errors, timers, SIO */ | 28 | /* raise priority for errors, timers, SIO */ |
29 | txx9_irq_set_pri(TX4938_IR_ECCERR, 7); | 29 | txx9_irq_set_pri(TX4938_IR_ECCERR, 7); |
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c index 93b6edbedd64..6b067dbd2ae1 100644 --- a/arch/mips/txx9/generic/irq_tx4939.c +++ b/arch/mips/txx9/generic/irq_tx4939.c | |||
@@ -176,8 +176,8 @@ void __init tx4939_irq_init(void) | |||
176 | for (i = 1; i < TX4939_NUM_IR; i++) { | 176 | for (i = 1; i < TX4939_NUM_IR; i++) { |
177 | tx4939irq[i].level = 4; /* middle level */ | 177 | tx4939irq[i].level = 4; /* middle level */ |
178 | tx4939irq[i].mode = TXx9_IRCR_LOW; | 178 | tx4939irq[i].mode = TXx9_IRCR_LOW; |
179 | set_irq_chip_and_handler(TXX9_IRQ_BASE + i, | 179 | irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip, |
180 | &tx4939_irq_chip, handle_level_irq); | 180 | handle_level_irq); |
181 | } | 181 | } |
182 | 182 | ||
183 | /* mask all IRC interrupts */ | 183 | /* mask all IRC interrupts */ |
@@ -193,7 +193,7 @@ void __init tx4939_irq_init(void) | |||
193 | __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); | 193 | __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); |
194 | __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); | 194 | __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); |
195 | 195 | ||
196 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, | 196 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, |
197 | handle_simple_irq); | 197 | handle_simple_irq); |
198 | 198 | ||
199 | /* raise priority for errors, timers, sio */ | 199 | /* raise priority for errors, timers, sio */ |
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index 92a5c1b400f0..c22c859a2c49 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c | |||
@@ -120,8 +120,9 @@ void __init jmr3927_irq_setup(void) | |||
120 | 120 | ||
121 | tx3927_irq_init(); | 121 | tx3927_irq_init(); |
122 | for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) | 122 | for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) |
123 | set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); | 123 | irq_set_chip_and_handler(i, &jmr3927_irq_ioc, |
124 | handle_level_irq); | ||
124 | 125 | ||
125 | /* setup IOC interrupt 1 (PCI, MODEM) */ | 126 | /* setup IOC interrupt 1 (PCI, MODEM) */ |
126 | set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); | 127 | irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); |
127 | } | 128 | } |
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c index 7c0a048b307c..6c22c496090b 100644 --- a/arch/mips/txx9/rbtx4927/irq.c +++ b/arch/mips/txx9/rbtx4927/irq.c | |||
@@ -164,9 +164,9 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void) | |||
164 | 164 | ||
165 | for (i = RBTX4927_IRQ_IOC; | 165 | for (i = RBTX4927_IRQ_IOC; |
166 | i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) | 166 | i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) |
167 | set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, | 167 | irq_set_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, |
168 | handle_level_irq); | 168 | handle_level_irq); |
169 | set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); | 169 | irq_set_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); |
170 | } | 170 | } |
171 | 171 | ||
172 | static int rbtx4927_irq_dispatch(int pending) | 172 | static int rbtx4927_irq_dispatch(int pending) |
@@ -194,5 +194,5 @@ void __init rbtx4927_irq_setup(void) | |||
194 | tx4927_irq_init(); | 194 | tx4927_irq_init(); |
195 | toshiba_rbtx4927_irq_ioc_init(); | 195 | toshiba_rbtx4927_irq_ioc_init(); |
196 | /* Onboard 10M Ether: High Active */ | 196 | /* Onboard 10M Ether: High Active */ |
197 | set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); | 197 | irq_set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); |
198 | } | 198 | } |
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c index 2ec4fe1b1670..58cd7a9272cc 100644 --- a/arch/mips/txx9/rbtx4938/irq.c +++ b/arch/mips/txx9/rbtx4938/irq.c | |||
@@ -132,10 +132,10 @@ static void __init toshiba_rbtx4938_irq_ioc_init(void) | |||
132 | 132 | ||
133 | for (i = RBTX4938_IRQ_IOC; | 133 | for (i = RBTX4938_IRQ_IOC; |
134 | i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) | 134 | i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) |
135 | set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, | 135 | irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, |
136 | handle_level_irq); | 136 | handle_level_irq); |
137 | 137 | ||
138 | set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); | 138 | irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); |
139 | } | 139 | } |
140 | 140 | ||
141 | void __init rbtx4938_irq_setup(void) | 141 | void __init rbtx4938_irq_setup(void) |
@@ -153,5 +153,5 @@ void __init rbtx4938_irq_setup(void) | |||
153 | tx4938_irq_init(); | 153 | tx4938_irq_init(); |
154 | toshiba_rbtx4938_irq_ioc_init(); | 154 | toshiba_rbtx4938_irq_ioc_init(); |
155 | /* Onboard 10M Ether: High Active */ | 155 | /* Onboard 10M Ether: High Active */ |
156 | set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); | 156 | irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); |
157 | } | 157 | } |
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c index 70074632fb99..69a80616f0c9 100644 --- a/arch/mips/txx9/rbtx4939/irq.c +++ b/arch/mips/txx9/rbtx4939/irq.c | |||
@@ -88,8 +88,8 @@ void __init rbtx4939_irq_setup(void) | |||
88 | tx4939_irq_init(); | 88 | tx4939_irq_init(); |
89 | for (i = RBTX4939_IRQ_IOC; | 89 | for (i = RBTX4939_IRQ_IOC; |
90 | i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++) | 90 | i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++) |
91 | set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip, | 91 | irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip, |
92 | handle_level_irq); | 92 | handle_level_irq); |
93 | 93 | ||
94 | set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); | 94 | irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); |
95 | } | 95 | } |
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index f53156bb9aa8..a39ef3207d71 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c | |||
@@ -710,11 +710,11 @@ static int __init vr41xx_icu_init(void) | |||
710 | icu2_write(MGIUINTHREG, 0xffff); | 710 | icu2_write(MGIUINTHREG, 0xffff); |
711 | 711 | ||
712 | for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) | 712 | for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) |
713 | set_irq_chip_and_handler(i, &sysint1_irq_type, | 713 | irq_set_chip_and_handler(i, &sysint1_irq_type, |
714 | handle_level_irq); | 714 | handle_level_irq); |
715 | 715 | ||
716 | for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) | 716 | for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) |
717 | set_irq_chip_and_handler(i, &sysint2_irq_type, | 717 | irq_set_chip_and_handler(i, &sysint2_irq_type, |
718 | handle_level_irq); | 718 | handle_level_irq); |
719 | 719 | ||
720 | cascade_irq(INT0_IRQ, icu_get_irq); | 720 | cascade_irq(INT0_IRQ, icu_get_irq); |
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 9ff7f397c0e1..70a3b85f3757 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c | |||
@@ -87,7 +87,7 @@ static void irq_dispatch(unsigned int irq) | |||
87 | atomic_inc(&irq_err_count); | 87 | atomic_inc(&irq_err_count); |
88 | else | 88 | else |
89 | irq_dispatch(irq); | 89 | irq_dispatch(irq); |
90 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) | 90 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
91 | chip->irq_unmask(idata); | 91 | chip->irq_unmask(idata); |
92 | } else | 92 | } else |
93 | do_IRQ(irq); | 93 | do_IRQ(irq); |
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig index d8ab97a73db2..feaf09cc8632 100644 --- a/arch/mn10300/Kconfig +++ b/arch/mn10300/Kconfig | |||
@@ -2,7 +2,7 @@ config MN10300 | |||
2 | def_bool y | 2 | def_bool y |
3 | select HAVE_OPROFILE | 3 | select HAVE_OPROFILE |
4 | select HAVE_GENERIC_HARDIRQS | 4 | select HAVE_GENERIC_HARDIRQS |
5 | select GENERIC_HARDIRQS_NO_DEPRECATED | 5 | select GENERIC_IRQ_SHOW |
6 | select HAVE_ARCH_TRACEHOOK | 6 | select HAVE_ARCH_TRACEHOOK |
7 | select HAVE_ARCH_KGDB | 7 | select HAVE_ARCH_KGDB |
8 | 8 | ||
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c index 5f7fc3eb45e6..86af0d7d0771 100644 --- a/arch/mn10300/kernel/irq.c +++ b/arch/mn10300/kernel/irq.c | |||
@@ -263,7 +263,7 @@ void set_intr_level(int irq, u16 level) | |||
263 | */ | 263 | */ |
264 | void mn10300_set_lateack_irq_type(int irq) | 264 | void mn10300_set_lateack_irq_type(int irq) |
265 | { | 265 | { |
266 | set_irq_chip_and_handler(irq, &mn10300_cpu_pic_level, | 266 | irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level, |
267 | handle_level_irq); | 267 | handle_level_irq); |
268 | } | 268 | } |
269 | 269 | ||
@@ -275,12 +275,12 @@ void __init init_IRQ(void) | |||
275 | int irq; | 275 | int irq; |
276 | 276 | ||
277 | for (irq = 0; irq < NR_IRQS; irq++) | 277 | for (irq = 0; irq < NR_IRQS; irq++) |
278 | if (get_irq_chip(irq) == &no_irq_chip) | 278 | if (irq_get_chip(irq) == &no_irq_chip) |
279 | /* due to the PIC latching interrupt requests, even | 279 | /* due to the PIC latching interrupt requests, even |
280 | * when the IRQ is disabled, IRQ_PENDING is superfluous | 280 | * when the IRQ is disabled, IRQ_PENDING is superfluous |
281 | * and we can use handle_level_irq() for edge-triggered | 281 | * and we can use handle_level_irq() for edge-triggered |
282 | * interrupts */ | 282 | * interrupts */ |
283 | set_irq_chip_and_handler(irq, &mn10300_cpu_pic_edge, | 283 | irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge, |
284 | handle_level_irq); | 284 | handle_level_irq); |
285 | 285 | ||
286 | unit_init_IRQ(); | 286 | unit_init_IRQ(); |
@@ -335,91 +335,42 @@ asmlinkage void do_IRQ(void) | |||
335 | /* | 335 | /* |
336 | * Display interrupt management information through /proc/interrupts | 336 | * Display interrupt management information through /proc/interrupts |
337 | */ | 337 | */ |
338 | int show_interrupts(struct seq_file *p, void *v) | 338 | int arch_show_interrupts(struct seq_file *p, int prec) |
339 | { | 339 | { |
340 | int i = *(loff_t *) v, j, cpu; | ||
341 | struct irqaction *action; | ||
342 | unsigned long flags; | ||
343 | |||
344 | switch (i) { | ||
345 | /* display column title bar naming CPUs */ | ||
346 | case 0: | ||
347 | seq_printf(p, " "); | ||
348 | for (j = 0; j < NR_CPUS; j++) | ||
349 | if (cpu_online(j)) | ||
350 | seq_printf(p, "CPU%d ", j); | ||
351 | seq_putc(p, '\n'); | ||
352 | break; | ||
353 | |||
354 | /* display information rows, one per active CPU */ | ||
355 | case 1 ... NR_IRQS - 1: | ||
356 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
357 | |||
358 | action = irq_desc[i].action; | ||
359 | if (action) { | ||
360 | seq_printf(p, "%3d: ", i); | ||
361 | for_each_present_cpu(cpu) | ||
362 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); | ||
363 | |||
364 | if (i < NR_CPU_IRQS) | ||
365 | seq_printf(p, " %14s.%u", | ||
366 | irq_desc[i].irq_data.chip->name, | ||
367 | (GxICR(i) & GxICR_LEVEL) >> | ||
368 | GxICR_LEVEL_SHIFT); | ||
369 | else | ||
370 | seq_printf(p, " %14s", | ||
371 | irq_desc[i].irq_data.chip->name); | ||
372 | |||
373 | seq_printf(p, " %s", action->name); | ||
374 | |||
375 | for (action = action->next; | ||
376 | action; | ||
377 | action = action->next) | ||
378 | seq_printf(p, ", %s", action->name); | ||
379 | |||
380 | seq_putc(p, '\n'); | ||
381 | } | ||
382 | |||
383 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
384 | break; | ||
385 | |||
386 | /* polish off with NMI and error counters */ | ||
387 | case NR_IRQS: | ||
388 | #ifdef CONFIG_MN10300_WD_TIMER | 340 | #ifdef CONFIG_MN10300_WD_TIMER |
389 | seq_printf(p, "NMI: "); | 341 | int j; |
390 | for (j = 0; j < NR_CPUS; j++) | ||
391 | if (cpu_online(j)) | ||
392 | seq_printf(p, "%10u ", nmi_count(j)); | ||
393 | seq_putc(p, '\n'); | ||
394 | #endif | ||
395 | 342 | ||
396 | seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); | 343 | seq_printf(p, "%*s: ", prec, "NMI"); |
397 | break; | 344 | for (j = 0; j < NR_CPUS; j++) |
398 | } | 345 | if (cpu_online(j)) |
346 | seq_printf(p, "%10u ", nmi_count(j)); | ||
347 | seq_putc(p, '\n'); | ||
348 | #endif | ||
399 | 349 | ||
350 | seq_printf(p, "%*s: ", prec, "ERR"); | ||
351 | seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); | ||
400 | return 0; | 352 | return 0; |
401 | } | 353 | } |
402 | 354 | ||
403 | #ifdef CONFIG_HOTPLUG_CPU | 355 | #ifdef CONFIG_HOTPLUG_CPU |
404 | void migrate_irqs(void) | 356 | void migrate_irqs(void) |
405 | { | 357 | { |
406 | irq_desc_t *desc; | ||
407 | int irq; | 358 | int irq; |
408 | unsigned int self, new; | 359 | unsigned int self, new; |
409 | unsigned long flags; | 360 | unsigned long flags; |
410 | 361 | ||
411 | self = smp_processor_id(); | 362 | self = smp_processor_id(); |
412 | for (irq = 0; irq < NR_IRQS; irq++) { | 363 | for (irq = 0; irq < NR_IRQS; irq++) { |
413 | desc = irq_desc + irq; | 364 | struct irq_data *data = irq_get_irq_data(irq); |
414 | 365 | ||
415 | if (desc->status == IRQ_PER_CPU) | 366 | if (irqd_is_per_cpu(data)) |
416 | continue; | 367 | continue; |
417 | 368 | ||
418 | if (cpu_isset(self, irq_desc[irq].affinity) && | 369 | if (cpu_isset(self, data->affinity) && |
419 | !cpus_intersects(irq_affinity[irq], cpu_online_map)) { | 370 | !cpus_intersects(irq_affinity[irq], cpu_online_map)) { |
420 | int cpu_id; | 371 | int cpu_id; |
421 | cpu_id = first_cpu(cpu_online_map); | 372 | cpu_id = first_cpu(cpu_online_map); |
422 | cpu_set(cpu_id, irq_desc[irq].affinity); | 373 | cpu_set(cpu_id, data->affinity); |
423 | } | 374 | } |
424 | /* We need to operate irq_affinity_online atomically. */ | 375 | /* We need to operate irq_affinity_online atomically. */ |
425 | arch_local_cli_save(flags); | 376 | arch_local_cli_save(flags); |
@@ -430,7 +381,7 @@ void migrate_irqs(void) | |||
430 | GxICR(irq) = x & GxICR_LEVEL; | 381 | GxICR(irq) = x & GxICR_LEVEL; |
431 | tmp = GxICR(irq); | 382 | tmp = GxICR(irq); |
432 | 383 | ||
433 | new = any_online_cpu(irq_desc[irq].affinity); | 384 | new = any_online_cpu(data->affinity); |
434 | irq_affinity_online[irq] = new; | 385 | irq_affinity_online[irq] = new; |
435 | 386 | ||
436 | CROSS_GxICR(irq, new) = | 387 | CROSS_GxICR(irq, new) = |
diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c index efca426a2ed4..94901c56baf1 100644 --- a/arch/mn10300/kernel/mn10300-serial.c +++ b/arch/mn10300/kernel/mn10300-serial.c | |||
@@ -933,7 +933,7 @@ static int mn10300_serial_startup(struct uart_port *_port) | |||
933 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); | 933 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); |
934 | set_intr_level(port->tx_irq, | 934 | set_intr_level(port->tx_irq, |
935 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); | 935 | NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)); |
936 | set_irq_chip(port->tm_irq, &mn10300_serial_pic); | 936 | irq_set_chip(port->tm_irq, &mn10300_serial_pic); |
937 | 937 | ||
938 | if (request_irq(port->rx_irq, mn10300_serial_interrupt, | 938 | if (request_irq(port->rx_irq, mn10300_serial_interrupt, |
939 | IRQF_DISABLED, port->rx_name, port) < 0) | 939 | IRQF_DISABLED, port->rx_name, port) < 0) |
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c index 51c02f97dcea..226c826a2194 100644 --- a/arch/mn10300/kernel/smp.c +++ b/arch/mn10300/kernel/smp.c | |||
@@ -156,15 +156,15 @@ static void init_ipi(void) | |||
156 | u16 tmp16; | 156 | u16 tmp16; |
157 | 157 | ||
158 | /* set up the reschedule IPI */ | 158 | /* set up the reschedule IPI */ |
159 | set_irq_chip_and_handler(RESCHEDULE_IPI, | 159 | irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type, |
160 | &mn10300_ipi_type, handle_percpu_irq); | 160 | handle_percpu_irq); |
161 | setup_irq(RESCHEDULE_IPI, &reschedule_ipi); | 161 | setup_irq(RESCHEDULE_IPI, &reschedule_ipi); |
162 | set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV); | 162 | set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV); |
163 | mn10300_ipi_enable(RESCHEDULE_IPI); | 163 | mn10300_ipi_enable(RESCHEDULE_IPI); |
164 | 164 | ||
165 | /* set up the call function IPI */ | 165 | /* set up the call function IPI */ |
166 | set_irq_chip_and_handler(CALL_FUNC_SINGLE_IPI, | 166 | irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type, |
167 | &mn10300_ipi_type, handle_percpu_irq); | 167 | handle_percpu_irq); |
168 | setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi); | 168 | setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi); |
169 | set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV); | 169 | set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV); |
170 | mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); | 170 | mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI); |
@@ -172,8 +172,8 @@ static void init_ipi(void) | |||
172 | /* set up the local timer IPI */ | 172 | /* set up the local timer IPI */ |
173 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ | 173 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \ |
174 | defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) | 174 | defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) |
175 | set_irq_chip_and_handler(LOCAL_TIMER_IPI, | 175 | irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type, |
176 | &mn10300_ipi_type, handle_percpu_irq); | 176 | handle_percpu_irq); |
177 | setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi); | 177 | setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi); |
178 | set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV); | 178 | set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV); |
179 | mn10300_ipi_enable(LOCAL_TIMER_IPI); | 179 | mn10300_ipi_enable(LOCAL_TIMER_IPI); |
diff --git a/arch/mn10300/unit-asb2364/irq-fpga.c b/arch/mn10300/unit-asb2364/irq-fpga.c index ee84e62b16ed..e16c216f31dc 100644 --- a/arch/mn10300/unit-asb2364/irq-fpga.c +++ b/arch/mn10300/unit-asb2364/irq-fpga.c | |||
@@ -100,7 +100,8 @@ void __init irq_fpga_init(void) | |||
100 | SyncExBus(); | 100 | SyncExBus(); |
101 | 101 | ||
102 | for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++) | 102 | for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++) |
103 | set_irq_chip_and_handler(irq, &asb2364_fpga_pic, handle_level_irq); | 103 | irq_set_chip_and_handler(irq, &asb2364_fpga_pic, |
104 | handle_level_irq); | ||
104 | 105 | ||
105 | /* the FPGA drives the XIRQ1 input on the CPU PIC */ | 106 | /* the FPGA drives the XIRQ1 input on the CPU PIC */ |
106 | setup_irq(XIRQ1, &fpga_irq[0]); | 107 | setup_irq(XIRQ1, &fpga_irq[0]); |
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 9b1f427cdc37..69ff049c8571 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig | |||
@@ -15,7 +15,6 @@ config PARISC | |||
15 | select HAVE_GENERIC_HARDIRQS | 15 | select HAVE_GENERIC_HARDIRQS |
16 | select GENERIC_IRQ_PROBE | 16 | select GENERIC_IRQ_PROBE |
17 | select IRQ_PER_CPU | 17 | select IRQ_PER_CPU |
18 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
19 | 18 | ||
20 | help | 19 | help |
21 | The PA-RISC microprocessor is designed by Hewlett-Packard and used | 20 | The PA-RISC microprocessor is designed by Hewlett-Packard and used |
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index cb450e1e79b3..c0b1affc06a8 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c | |||
@@ -113,13 +113,8 @@ int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest) | |||
113 | int cpu_dest; | 113 | int cpu_dest; |
114 | 114 | ||
115 | /* timer and ipi have to always be received on all CPUs */ | 115 | /* timer and ipi have to always be received on all CPUs */ |
116 | if (CHECK_IRQ_PER_CPU(irq_to_desc(d->irq)->status)) { | 116 | if (irqd_is_per_cpu(d)) |
117 | /* Bad linux design decision. The mask has already | ||
118 | * been set; we must reset it. Will fix - tglx | ||
119 | */ | ||
120 | cpumask_setall(d->affinity); | ||
121 | return -EINVAL; | 117 | return -EINVAL; |
122 | } | ||
123 | 118 | ||
124 | /* whatever mask they set, we just allow one CPU */ | 119 | /* whatever mask they set, we just allow one CPU */ |
125 | cpu_dest = first_cpu(*dest); | 120 | cpu_dest = first_cpu(*dest); |
@@ -174,10 +169,11 @@ int show_interrupts(struct seq_file *p, void *v) | |||
174 | } | 169 | } |
175 | 170 | ||
176 | if (i < NR_IRQS) { | 171 | if (i < NR_IRQS) { |
172 | struct irq_desc *desc = irq_to_desc(i); | ||
177 | struct irqaction *action; | 173 | struct irqaction *action; |
178 | 174 | ||
179 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | 175 | raw_spin_lock_irqsave(&desc->lock, flags); |
180 | action = irq_desc[i].action; | 176 | action = desc->action; |
181 | if (!action) | 177 | if (!action) |
182 | goto skip; | 178 | goto skip; |
183 | seq_printf(p, "%3d: ", i); | 179 | seq_printf(p, "%3d: ", i); |
@@ -188,7 +184,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
188 | seq_printf(p, "%10u ", kstat_irqs(i)); | 184 | seq_printf(p, "%10u ", kstat_irqs(i)); |
189 | #endif | 185 | #endif |
190 | 186 | ||
191 | seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); | 187 | seq_printf(p, " %14s", irq_desc_get_chip(desc)->name); |
192 | #ifndef PARISC_IRQ_CR16_COUNTS | 188 | #ifndef PARISC_IRQ_CR16_COUNTS |
193 | seq_printf(p, " %s", action->name); | 189 | seq_printf(p, " %s", action->name); |
194 | 190 | ||
@@ -220,7 +216,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
220 | 216 | ||
221 | seq_putc(p, '\n'); | 217 | seq_putc(p, '\n'); |
222 | skip: | 218 | skip: |
223 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | 219 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
224 | } | 220 | } |
225 | 221 | ||
226 | return 0; | 222 | return 0; |
@@ -238,15 +234,15 @@ int show_interrupts(struct seq_file *p, void *v) | |||
238 | 234 | ||
239 | int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) | 235 | int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) |
240 | { | 236 | { |
241 | if (irq_desc[irq].action) | 237 | if (irq_has_action(irq)) |
242 | return -EBUSY; | 238 | return -EBUSY; |
243 | if (get_irq_chip(irq) != &cpu_interrupt_type) | 239 | if (irq_get_chip(irq) != &cpu_interrupt_type) |
244 | return -EBUSY; | 240 | return -EBUSY; |
245 | 241 | ||
246 | /* for iosapic interrupts */ | 242 | /* for iosapic interrupts */ |
247 | if (type) { | 243 | if (type) { |
248 | set_irq_chip_and_handler(irq, type, handle_percpu_irq); | 244 | irq_set_chip_and_handler(irq, type, handle_percpu_irq); |
249 | set_irq_chip_data(irq, data); | 245 | irq_set_chip_data(irq, data); |
250 | __cpu_unmask_irq(irq); | 246 | __cpu_unmask_irq(irq); |
251 | } | 247 | } |
252 | return 0; | 248 | return 0; |
@@ -357,7 +353,7 @@ void do_cpu_irq_mask(struct pt_regs *regs) | |||
357 | #ifdef CONFIG_SMP | 353 | #ifdef CONFIG_SMP |
358 | desc = irq_to_desc(irq); | 354 | desc = irq_to_desc(irq); |
359 | cpumask_copy(&dest, desc->irq_data.affinity); | 355 | cpumask_copy(&dest, desc->irq_data.affinity); |
360 | if (CHECK_IRQ_PER_CPU(desc->status) && | 356 | if (irqd_is_per_cpu(&desc->irq_data) && |
361 | !cpu_isset(smp_processor_id(), dest)) { | 357 | !cpu_isset(smp_processor_id(), dest)) { |
362 | int cpu = first_cpu(dest); | 358 | int cpu = first_cpu(dest); |
363 | 359 | ||
@@ -398,14 +394,14 @@ static void claim_cpu_irqs(void) | |||
398 | { | 394 | { |
399 | int i; | 395 | int i; |
400 | for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { | 396 | for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { |
401 | set_irq_chip_and_handler(i, &cpu_interrupt_type, | 397 | irq_set_chip_and_handler(i, &cpu_interrupt_type, |
402 | handle_percpu_irq); | 398 | handle_percpu_irq); |
403 | } | 399 | } |
404 | 400 | ||
405 | set_irq_handler(TIMER_IRQ, handle_percpu_irq); | 401 | irq_set_handler(TIMER_IRQ, handle_percpu_irq); |
406 | setup_irq(TIMER_IRQ, &timer_action); | 402 | setup_irq(TIMER_IRQ, &timer_action); |
407 | #ifdef CONFIG_SMP | 403 | #ifdef CONFIG_SMP |
408 | set_irq_handler(IPI_IRQ, handle_percpu_irq); | 404 | irq_set_handler(IPI_IRQ, handle_percpu_irq); |
409 | setup_irq(IPI_IRQ, &ipi_action); | 405 | setup_irq(IPI_IRQ, &ipi_action); |
410 | #endif | 406 | #endif |
411 | } | 407 | } |
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 3584e4d4a4ad..b6ff882f695b 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig | |||
@@ -138,7 +138,8 @@ config PPC | |||
138 | select HAVE_GENERIC_HARDIRQS | 138 | select HAVE_GENERIC_HARDIRQS |
139 | select HAVE_SPARSE_IRQ | 139 | select HAVE_SPARSE_IRQ |
140 | select IRQ_PER_CPU | 140 | select IRQ_PER_CPU |
141 | select GENERIC_HARDIRQS_NO_DEPRECATED | 141 | select GENERIC_IRQ_SHOW |
142 | select GENERIC_IRQ_SHOW_LEVEL | ||
142 | 143 | ||
143 | config EARLY_PRINTK | 144 | config EARLY_PRINTK |
144 | bool | 145 | bool |
diff --git a/arch/powerpc/configs/44x/warp_defconfig b/arch/powerpc/configs/44x/warp_defconfig index 6cf9d6614805..abf74dc1f79c 100644 --- a/arch/powerpc/configs/44x/warp_defconfig +++ b/arch/powerpc/configs/44x/warp_defconfig | |||
@@ -47,6 +47,7 @@ CONFIG_MTD_NAND_NDFC=y | |||
47 | CONFIG_MTD_UBI=y | 47 | CONFIG_MTD_UBI=y |
48 | CONFIG_PROC_DEVICETREE=y | 48 | CONFIG_PROC_DEVICETREE=y |
49 | CONFIG_BLK_DEV_RAM=y | 49 | CONFIG_BLK_DEV_RAM=y |
50 | CONFIG_MISC_DEVICES=y | ||
50 | CONFIG_EEPROM_AT24=y | 51 | CONFIG_EEPROM_AT24=y |
51 | CONFIG_SCSI=y | 52 | CONFIG_SCSI=y |
52 | CONFIG_BLK_DEV_SD=y | 53 | CONFIG_BLK_DEV_SD=y |
diff --git a/arch/powerpc/configs/52xx/motionpro_defconfig b/arch/powerpc/configs/52xx/motionpro_defconfig index 6828eda02bdc..0c7de9620ea6 100644 --- a/arch/powerpc/configs/52xx/motionpro_defconfig +++ b/arch/powerpc/configs/52xx/motionpro_defconfig | |||
@@ -43,6 +43,7 @@ CONFIG_PROC_DEVICETREE=y | |||
43 | CONFIG_BLK_DEV_LOOP=y | 43 | CONFIG_BLK_DEV_LOOP=y |
44 | CONFIG_BLK_DEV_RAM=y | 44 | CONFIG_BLK_DEV_RAM=y |
45 | CONFIG_BLK_DEV_RAM_SIZE=32768 | 45 | CONFIG_BLK_DEV_RAM_SIZE=32768 |
46 | CONFIG_MISC_DEVICES=y | ||
46 | CONFIG_EEPROM_LEGACY=y | 47 | CONFIG_EEPROM_LEGACY=y |
47 | CONFIG_SCSI_TGT=y | 48 | CONFIG_SCSI_TGT=y |
48 | CONFIG_BLK_DEV_SD=y | 49 | CONFIG_BLK_DEV_SD=y |
diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig index 4b2441244eab..d41857a5152d 100644 --- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig | |||
@@ -85,6 +85,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m | |||
85 | CONFIG_BLK_DEV_NBD=m | 85 | CONFIG_BLK_DEV_NBD=m |
86 | CONFIG_BLK_DEV_RAM=y | 86 | CONFIG_BLK_DEV_RAM=y |
87 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 87 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
88 | CONFIG_MISC_DEVICES=y | ||
88 | CONFIG_DS1682=y | 89 | CONFIG_DS1682=y |
89 | CONFIG_IDE=y | 90 | CONFIG_IDE=y |
90 | CONFIG_BLK_DEV_IDECS=y | 91 | CONFIG_BLK_DEV_IDECS=y |
diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig index a360ba44b928..38303ec11bcd 100644 --- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig | |||
@@ -85,6 +85,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m | |||
85 | CONFIG_BLK_DEV_NBD=m | 85 | CONFIG_BLK_DEV_NBD=m |
86 | CONFIG_BLK_DEV_RAM=y | 86 | CONFIG_BLK_DEV_RAM=y |
87 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 87 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
88 | CONFIG_MISC_DEVICES=y | ||
88 | CONFIG_DS1682=y | 89 | CONFIG_DS1682=y |
89 | CONFIG_IDE=y | 90 | CONFIG_IDE=y |
90 | CONFIG_BLK_DEV_IDECS=y | 91 | CONFIG_BLK_DEV_IDECS=y |
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig index be2829dd129f..98533973d20f 100644 --- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig | |||
@@ -138,6 +138,7 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m | |||
138 | CONFIG_BLK_DEV_NBD=m | 138 | CONFIG_BLK_DEV_NBD=m |
139 | CONFIG_BLK_DEV_RAM=y | 139 | CONFIG_BLK_DEV_RAM=y |
140 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 140 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
141 | CONFIG_MISC_DEVICES=y | ||
141 | CONFIG_DS1682=y | 142 | CONFIG_DS1682=y |
142 | CONFIG_BLK_DEV_SD=y | 143 | CONFIG_BLK_DEV_SD=y |
143 | CONFIG_CHR_DEV_ST=y | 144 | CONFIG_CHR_DEV_ST=y |
diff --git a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig index 0c9c7ed7ec75..b614508d6fd2 100644 --- a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig +++ b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig | |||
@@ -63,6 +63,7 @@ CONFIG_BLK_DEV_LOOP=y | |||
63 | CONFIG_BLK_DEV_NBD=y | 63 | CONFIG_BLK_DEV_NBD=y |
64 | CONFIG_BLK_DEV_RAM=y | 64 | CONFIG_BLK_DEV_RAM=y |
65 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 65 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
66 | CONFIG_MISC_DEVICES=y | ||
66 | CONFIG_EEPROM_LEGACY=y | 67 | CONFIG_EEPROM_LEGACY=y |
67 | CONFIG_BLK_DEV_SD=y | 68 | CONFIG_BLK_DEV_SD=y |
68 | CONFIG_CHR_DEV_ST=y | 69 | CONFIG_CHR_DEV_ST=y |
diff --git a/arch/powerpc/configs/e55xx_smp_defconfig b/arch/powerpc/configs/e55xx_smp_defconfig index 06f95492afc7..9fa1613e5e2b 100644 --- a/arch/powerpc/configs/e55xx_smp_defconfig +++ b/arch/powerpc/configs/e55xx_smp_defconfig | |||
@@ -32,6 +32,7 @@ CONFIG_PROC_DEVICETREE=y | |||
32 | CONFIG_BLK_DEV_LOOP=y | 32 | CONFIG_BLK_DEV_LOOP=y |
33 | CONFIG_BLK_DEV_RAM=y | 33 | CONFIG_BLK_DEV_RAM=y |
34 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 34 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
35 | CONFIG_MISC_DEVICES=y | ||
35 | CONFIG_EEPROM_LEGACY=y | 36 | CONFIG_EEPROM_LEGACY=y |
36 | CONFIG_INPUT_FF_MEMLESS=m | 37 | CONFIG_INPUT_FF_MEMLESS=m |
37 | # CONFIG_INPUT_MOUSEDEV is not set | 38 | # CONFIG_INPUT_MOUSEDEV is not set |
diff --git a/arch/powerpc/configs/linkstation_defconfig b/arch/powerpc/configs/linkstation_defconfig index f39d0cf876dd..8a874b999867 100644 --- a/arch/powerpc/configs/linkstation_defconfig +++ b/arch/powerpc/configs/linkstation_defconfig | |||
@@ -78,6 +78,7 @@ CONFIG_BLK_DEV_LOOP=y | |||
78 | CONFIG_BLK_DEV_RAM=y | 78 | CONFIG_BLK_DEV_RAM=y |
79 | CONFIG_BLK_DEV_RAM_COUNT=2 | 79 | CONFIG_BLK_DEV_RAM_COUNT=2 |
80 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 80 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
81 | CONFIG_MISC_DEVICES=y | ||
81 | CONFIG_EEPROM_LEGACY=m | 82 | CONFIG_EEPROM_LEGACY=m |
82 | CONFIG_BLK_DEV_SD=y | 83 | CONFIG_BLK_DEV_SD=y |
83 | CONFIG_CHR_DEV_SG=y | 84 | CONFIG_CHR_DEV_SG=y |
diff --git a/arch/powerpc/configs/mpc512x_defconfig b/arch/powerpc/configs/mpc512x_defconfig index 62db8a3df162..c02bbb2fddf8 100644 --- a/arch/powerpc/configs/mpc512x_defconfig +++ b/arch/powerpc/configs/mpc512x_defconfig | |||
@@ -61,6 +61,7 @@ CONFIG_BLK_DEV_RAM=y | |||
61 | CONFIG_BLK_DEV_RAM_COUNT=1 | 61 | CONFIG_BLK_DEV_RAM_COUNT=1 |
62 | CONFIG_BLK_DEV_RAM_SIZE=8192 | 62 | CONFIG_BLK_DEV_RAM_SIZE=8192 |
63 | CONFIG_BLK_DEV_XIP=y | 63 | CONFIG_BLK_DEV_XIP=y |
64 | CONFIG_MISC_DEVICES=y | ||
64 | CONFIG_EEPROM_AT24=y | 65 | CONFIG_EEPROM_AT24=y |
65 | CONFIG_SCSI=y | 66 | CONFIG_SCSI=y |
66 | # CONFIG_SCSI_PROC_FS is not set | 67 | # CONFIG_SCSI_PROC_FS is not set |
diff --git a/arch/powerpc/configs/mpc5200_defconfig b/arch/powerpc/configs/mpc5200_defconfig index 7376e27b8ed4..e63f537b854a 100644 --- a/arch/powerpc/configs/mpc5200_defconfig +++ b/arch/powerpc/configs/mpc5200_defconfig | |||
@@ -52,6 +52,7 @@ CONFIG_PROC_DEVICETREE=y | |||
52 | CONFIG_BLK_DEV_LOOP=y | 52 | CONFIG_BLK_DEV_LOOP=y |
53 | CONFIG_BLK_DEV_RAM=y | 53 | CONFIG_BLK_DEV_RAM=y |
54 | CONFIG_BLK_DEV_RAM_SIZE=32768 | 54 | CONFIG_BLK_DEV_RAM_SIZE=32768 |
55 | CONFIG_MISC_DEVICES=y | ||
55 | CONFIG_EEPROM_AT24=y | 56 | CONFIG_EEPROM_AT24=y |
56 | CONFIG_SCSI_TGT=y | 57 | CONFIG_SCSI_TGT=y |
57 | CONFIG_BLK_DEV_SD=y | 58 | CONFIG_BLK_DEV_SD=y |
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 99a19d1e9bf8..c06a86c33098 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig | |||
@@ -82,6 +82,7 @@ CONFIG_BLK_DEV_LOOP=y | |||
82 | CONFIG_BLK_DEV_NBD=y | 82 | CONFIG_BLK_DEV_NBD=y |
83 | CONFIG_BLK_DEV_RAM=y | 83 | CONFIG_BLK_DEV_RAM=y |
84 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 84 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
85 | CONFIG_MISC_DEVICES=y | ||
85 | CONFIG_EEPROM_LEGACY=y | 86 | CONFIG_EEPROM_LEGACY=y |
86 | CONFIG_BLK_DEV_SD=y | 87 | CONFIG_BLK_DEV_SD=y |
87 | CONFIG_CHR_DEV_ST=y | 88 | CONFIG_CHR_DEV_ST=y |
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index c636f23f8c92..942ced90557c 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig | |||
@@ -84,6 +84,7 @@ CONFIG_BLK_DEV_LOOP=y | |||
84 | CONFIG_BLK_DEV_NBD=y | 84 | CONFIG_BLK_DEV_NBD=y |
85 | CONFIG_BLK_DEV_RAM=y | 85 | CONFIG_BLK_DEV_RAM=y |
86 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 86 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
87 | CONFIG_MISC_DEVICES=y | ||
87 | CONFIG_EEPROM_LEGACY=y | 88 | CONFIG_EEPROM_LEGACY=y |
88 | CONFIG_BLK_DEV_SD=y | 89 | CONFIG_BLK_DEV_SD=y |
89 | CONFIG_CHR_DEV_ST=y | 90 | CONFIG_CHR_DEV_ST=y |
diff --git a/arch/powerpc/configs/mpc86xx_defconfig b/arch/powerpc/configs/mpc86xx_defconfig index 55b54318fef6..038a308cbfc4 100644 --- a/arch/powerpc/configs/mpc86xx_defconfig +++ b/arch/powerpc/configs/mpc86xx_defconfig | |||
@@ -66,6 +66,7 @@ CONFIG_BLK_DEV_LOOP=y | |||
66 | CONFIG_BLK_DEV_NBD=y | 66 | CONFIG_BLK_DEV_NBD=y |
67 | CONFIG_BLK_DEV_RAM=y | 67 | CONFIG_BLK_DEV_RAM=y |
68 | CONFIG_BLK_DEV_RAM_SIZE=131072 | 68 | CONFIG_BLK_DEV_RAM_SIZE=131072 |
69 | CONFIG_MISC_DEVICES=y | ||
69 | CONFIG_EEPROM_LEGACY=y | 70 | CONFIG_EEPROM_LEGACY=y |
70 | CONFIG_BLK_DEV_SD=y | 71 | CONFIG_BLK_DEV_SD=y |
71 | CONFIG_CHR_DEV_ST=y | 72 | CONFIG_CHR_DEV_ST=y |
diff --git a/arch/powerpc/configs/pasemi_defconfig b/arch/powerpc/configs/pasemi_defconfig index edd2d54c8196..f4deb0b78cf0 100644 --- a/arch/powerpc/configs/pasemi_defconfig +++ b/arch/powerpc/configs/pasemi_defconfig | |||
@@ -59,6 +59,7 @@ CONFIG_PROC_DEVICETREE=y | |||
59 | CONFIG_BLK_DEV_LOOP=y | 59 | CONFIG_BLK_DEV_LOOP=y |
60 | CONFIG_BLK_DEV_RAM=y | 60 | CONFIG_BLK_DEV_RAM=y |
61 | CONFIG_BLK_DEV_RAM_SIZE=16384 | 61 | CONFIG_BLK_DEV_RAM_SIZE=16384 |
62 | CONFIG_MISC_DEVICES=y | ||
62 | CONFIG_EEPROM_LEGACY=y | 63 | CONFIG_EEPROM_LEGACY=y |
63 | CONFIG_IDE=y | 64 | CONFIG_IDE=y |
64 | CONFIG_BLK_DEV_IDECD=y | 65 | CONFIG_BLK_DEV_IDECD=y |
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index 9d64a6822d86..0a10fb009ef7 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig | |||
@@ -398,6 +398,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 | |||
398 | CONFIG_CDROM_PKTCDVD=m | 398 | CONFIG_CDROM_PKTCDVD=m |
399 | CONFIG_VIRTIO_BLK=m | 399 | CONFIG_VIRTIO_BLK=m |
400 | CONFIG_BLK_DEV_HD=y | 400 | CONFIG_BLK_DEV_HD=y |
401 | CONFIG_MISC_DEVICES=y | ||
401 | CONFIG_ENCLOSURE_SERVICES=m | 402 | CONFIG_ENCLOSURE_SERVICES=m |
402 | CONFIG_SENSORS_TSL2550=m | 403 | CONFIG_SENSORS_TSL2550=m |
403 | CONFIG_EEPROM_AT24=m | 404 | CONFIG_EEPROM_AT24=m |
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index 9c3f22c6cde1..249ddd0a27cd 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig | |||
@@ -189,6 +189,7 @@ CONFIG_TIGON3=y | |||
189 | CONFIG_BNX2=m | 189 | CONFIG_BNX2=m |
190 | CONFIG_CHELSIO_T1=m | 190 | CONFIG_CHELSIO_T1=m |
191 | CONFIG_CHELSIO_T3=m | 191 | CONFIG_CHELSIO_T3=m |
192 | CONFIG_CHELSIO_T4=m | ||
192 | CONFIG_EHEA=y | 193 | CONFIG_EHEA=y |
193 | CONFIG_IXGBE=m | 194 | CONFIG_IXGBE=m |
194 | CONFIG_IXGB=m | 195 | CONFIG_IXGB=m |
@@ -255,6 +256,8 @@ CONFIG_INFINIBAND_USER_MAD=m | |||
255 | CONFIG_INFINIBAND_USER_ACCESS=m | 256 | CONFIG_INFINIBAND_USER_ACCESS=m |
256 | CONFIG_INFINIBAND_MTHCA=m | 257 | CONFIG_INFINIBAND_MTHCA=m |
257 | CONFIG_INFINIBAND_EHCA=m | 258 | CONFIG_INFINIBAND_EHCA=m |
259 | CONFIG_INFINIBAND_CXGB3=m | ||
260 | CONFIG_INFINIBAND_CXGB4=m | ||
258 | CONFIG_MLX4_INFINIBAND=m | 261 | CONFIG_MLX4_INFINIBAND=m |
259 | CONFIG_INFINIBAND_IPOIB=m | 262 | CONFIG_INFINIBAND_IPOIB=m |
260 | CONFIG_INFINIBAND_IPOIB_CM=y | 263 | CONFIG_INFINIBAND_IPOIB_CM=y |
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index 6d2416a85709..dd70fac57ec8 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h | |||
@@ -42,6 +42,7 @@ extern void __dma_free_coherent(size_t size, void *vaddr); | |||
42 | extern void __dma_sync(void *vaddr, size_t size, int direction); | 42 | extern void __dma_sync(void *vaddr, size_t size, int direction); |
43 | extern void __dma_sync_page(struct page *page, unsigned long offset, | 43 | extern void __dma_sync_page(struct page *page, unsigned long offset, |
44 | size_t size, int direction); | 44 | size_t size, int direction); |
45 | extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr); | ||
45 | 46 | ||
46 | #else /* ! CONFIG_NOT_COHERENT_CACHE */ | 47 | #else /* ! CONFIG_NOT_COHERENT_CACHE */ |
47 | /* | 48 | /* |
@@ -198,6 +199,11 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) | |||
198 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) | 199 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) |
199 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | 200 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) |
200 | 201 | ||
202 | extern int dma_mmap_coherent(struct device *, struct vm_area_struct *, | ||
203 | void *, dma_addr_t, size_t); | ||
204 | #define ARCH_HAS_DMA_MMAP_COHERENT | ||
205 | |||
206 | |||
201 | static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, | 207 | static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
202 | enum dma_data_direction direction) | 208 | enum dma_data_direction direction) |
203 | { | 209 | { |
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index fe56a23e1ff0..e4f01915fbb0 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h | |||
@@ -35,9 +35,9 @@ struct smp_ops_t { | |||
35 | int (*probe)(void); | 35 | int (*probe)(void); |
36 | void (*kick_cpu)(int nr); | 36 | void (*kick_cpu)(int nr); |
37 | void (*setup_cpu)(int nr); | 37 | void (*setup_cpu)(int nr); |
38 | void (*bringup_done)(void); | ||
38 | void (*take_timebase)(void); | 39 | void (*take_timebase)(void); |
39 | void (*give_timebase)(void); | 40 | void (*give_timebase)(void); |
40 | int (*cpu_enable)(unsigned int nr); | ||
41 | int (*cpu_disable)(void); | 41 | int (*cpu_disable)(void); |
42 | void (*cpu_die)(unsigned int nr); | 42 | void (*cpu_die)(unsigned int nr); |
43 | int (*cpu_bootable)(unsigned int nr); | 43 | int (*cpu_bootable)(unsigned int nr); |
@@ -267,7 +267,6 @@ struct machdep_calls { | |||
267 | 267 | ||
268 | extern void e500_idle(void); | 268 | extern void e500_idle(void); |
269 | extern void power4_idle(void); | 269 | extern void power4_idle(void); |
270 | extern void power4_cpu_offline_powersave(void); | ||
271 | extern void ppc6xx_idle(void); | 270 | extern void ppc6xx_idle(void); |
272 | extern void book3e_idle(void); | 271 | extern void book3e_idle(void); |
273 | 272 | ||
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h index acac35d5b382..ae7b3efec8e5 100644 --- a/arch/powerpc/include/asm/mmu-hash64.h +++ b/arch/powerpc/include/asm/mmu-hash64.h | |||
@@ -27,7 +27,7 @@ | |||
27 | #define STE_VSID_SHIFT 12 | 27 | #define STE_VSID_SHIFT 12 |
28 | 28 | ||
29 | /* Location of cpu0's segment table */ | 29 | /* Location of cpu0's segment table */ |
30 | #define STAB0_PAGE 0x6 | 30 | #define STAB0_PAGE 0x8 |
31 | #define STAB0_OFFSET (STAB0_PAGE << 12) | 31 | #define STAB0_OFFSET (STAB0_PAGE << 12) |
32 | #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START) | 32 | #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START) |
33 | 33 | ||
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h index da4b20008541..2cd664ef0a5e 100644 --- a/arch/powerpc/include/asm/page.h +++ b/arch/powerpc/include/asm/page.h | |||
@@ -100,7 +100,7 @@ extern phys_addr_t kernstart_addr; | |||
100 | #endif | 100 | #endif |
101 | 101 | ||
102 | #ifdef CONFIG_FLATMEM | 102 | #ifdef CONFIG_FLATMEM |
103 | #define ARCH_PFN_OFFSET (MEMORY_START >> PAGE_SHIFT) | 103 | #define ARCH_PFN_OFFSET ((unsigned long)(MEMORY_START >> PAGE_SHIFT)) |
104 | #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) | 104 | #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) |
105 | #endif | 105 | #endif |
106 | 106 | ||
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h index 9e2cb2019161..f706164b0bd0 100644 --- a/arch/powerpc/include/asm/qe_ic.h +++ b/arch/powerpc/include/asm/qe_ic.h | |||
@@ -81,7 +81,7 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); | |||
81 | static inline void qe_ic_cascade_low_ipic(unsigned int irq, | 81 | static inline void qe_ic_cascade_low_ipic(unsigned int irq, |
82 | struct irq_desc *desc) | 82 | struct irq_desc *desc) |
83 | { | 83 | { |
84 | struct qe_ic *qe_ic = get_irq_desc_data(desc); | 84 | struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); |
85 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); | 85 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); |
86 | 86 | ||
87 | if (cascade_irq != NO_IRQ) | 87 | if (cascade_irq != NO_IRQ) |
@@ -91,7 +91,7 @@ static inline void qe_ic_cascade_low_ipic(unsigned int irq, | |||
91 | static inline void qe_ic_cascade_high_ipic(unsigned int irq, | 91 | static inline void qe_ic_cascade_high_ipic(unsigned int irq, |
92 | struct irq_desc *desc) | 92 | struct irq_desc *desc) |
93 | { | 93 | { |
94 | struct qe_ic *qe_ic = get_irq_desc_data(desc); | 94 | struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); |
95 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); | 95 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); |
96 | 96 | ||
97 | if (cascade_irq != NO_IRQ) | 97 | if (cascade_irq != NO_IRQ) |
@@ -101,9 +101,9 @@ static inline void qe_ic_cascade_high_ipic(unsigned int irq, | |||
101 | static inline void qe_ic_cascade_low_mpic(unsigned int irq, | 101 | static inline void qe_ic_cascade_low_mpic(unsigned int irq, |
102 | struct irq_desc *desc) | 102 | struct irq_desc *desc) |
103 | { | 103 | { |
104 | struct qe_ic *qe_ic = get_irq_desc_data(desc); | 104 | struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); |
105 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); | 105 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); |
106 | struct irq_chip *chip = get_irq_desc_chip(desc); | 106 | struct irq_chip *chip = irq_desc_get_chip(desc); |
107 | 107 | ||
108 | if (cascade_irq != NO_IRQ) | 108 | if (cascade_irq != NO_IRQ) |
109 | generic_handle_irq(cascade_irq); | 109 | generic_handle_irq(cascade_irq); |
@@ -114,9 +114,9 @@ static inline void qe_ic_cascade_low_mpic(unsigned int irq, | |||
114 | static inline void qe_ic_cascade_high_mpic(unsigned int irq, | 114 | static inline void qe_ic_cascade_high_mpic(unsigned int irq, |
115 | struct irq_desc *desc) | 115 | struct irq_desc *desc) |
116 | { | 116 | { |
117 | struct qe_ic *qe_ic = get_irq_desc_data(desc); | 117 | struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); |
118 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); | 118 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); |
119 | struct irq_chip *chip = get_irq_desc_chip(desc); | 119 | struct irq_chip *chip = irq_desc_get_chip(desc); |
120 | 120 | ||
121 | if (cascade_irq != NO_IRQ) | 121 | if (cascade_irq != NO_IRQ) |
122 | generic_handle_irq(cascade_irq); | 122 | generic_handle_irq(cascade_irq); |
@@ -127,9 +127,9 @@ static inline void qe_ic_cascade_high_mpic(unsigned int irq, | |||
127 | static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, | 127 | static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, |
128 | struct irq_desc *desc) | 128 | struct irq_desc *desc) |
129 | { | 129 | { |
130 | struct qe_ic *qe_ic = get_irq_desc_data(desc); | 130 | struct qe_ic *qe_ic = irq_desc_get_handler_data(desc); |
131 | unsigned int cascade_irq; | 131 | unsigned int cascade_irq; |
132 | struct irq_chip *chip = get_irq_desc_chip(desc); | 132 | struct irq_chip *chip = irq_desc_get_chip(desc); |
133 | 133 | ||
134 | cascade_irq = qe_ic_get_high_irq(qe_ic); | 134 | cascade_irq = qe_ic_get_high_irq(qe_ic); |
135 | if (cascade_irq == NO_IRQ) | 135 | if (cascade_irq == NO_IRQ) |
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 86ad8128963a..3b1a9b707362 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h | |||
@@ -110,7 +110,7 @@ | |||
110 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | 110 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ |
111 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | 111 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ |
112 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | 112 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ |
113 | #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ | 113 | #define SPRN_MAS5 0x153 /* MMU Assist Register 5 */ |
114 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ | 114 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ |
115 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ | 115 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ |
116 | #define SPRN_PID2 0x27A /* Process ID Register 2 */ | 116 | #define SPRN_PID2 0x27A /* Process ID Register 2 */ |
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h index 66e237bbe15f..a902a0d3ae0d 100644 --- a/arch/powerpc/include/asm/smp.h +++ b/arch/powerpc/include/asm/smp.h | |||
@@ -36,15 +36,16 @@ extern void cpu_die(void); | |||
36 | 36 | ||
37 | extern void smp_send_debugger_break(int cpu); | 37 | extern void smp_send_debugger_break(int cpu); |
38 | extern void smp_message_recv(int); | 38 | extern void smp_message_recv(int); |
39 | extern void start_secondary_resume(void); | ||
39 | 40 | ||
40 | DECLARE_PER_CPU(unsigned int, cpu_pvr); | 41 | DECLARE_PER_CPU(unsigned int, cpu_pvr); |
41 | 42 | ||
42 | #ifdef CONFIG_HOTPLUG_CPU | 43 | #ifdef CONFIG_HOTPLUG_CPU |
43 | extern void fixup_irqs(const struct cpumask *map); | 44 | extern void migrate_irqs(void); |
44 | int generic_cpu_disable(void); | 45 | int generic_cpu_disable(void); |
45 | int generic_cpu_enable(unsigned int cpu); | ||
46 | void generic_cpu_die(unsigned int cpu); | 46 | void generic_cpu_die(unsigned int cpu); |
47 | void generic_mach_cpu_die(void); | 47 | void generic_mach_cpu_die(void); |
48 | void generic_set_cpu_dead(unsigned int cpu); | ||
48 | #endif | 49 | #endif |
49 | 50 | ||
50 | #ifdef CONFIG_PPC64 | 51 | #ifdef CONFIG_PPC64 |
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h index aa0f1ebb4aaf..60f64b132bd4 100644 --- a/arch/powerpc/include/asm/systbl.h +++ b/arch/powerpc/include/asm/systbl.h | |||
@@ -348,3 +348,7 @@ COMPAT_SYS_SPU(sendmsg) | |||
348 | COMPAT_SYS_SPU(recvmsg) | 348 | COMPAT_SYS_SPU(recvmsg) |
349 | COMPAT_SYS_SPU(recvmmsg) | 349 | COMPAT_SYS_SPU(recvmmsg) |
350 | SYSCALL_SPU(accept4) | 350 | SYSCALL_SPU(accept4) |
351 | SYSCALL_SPU(name_to_handle_at) | ||
352 | COMPAT_SYS_SPU(open_by_handle_at) | ||
353 | COMPAT_SYS_SPU(clock_adjtime) | ||
354 | SYSCALL_SPU(syncfs) | ||
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h index 6151937657f6..3c215648ce6d 100644 --- a/arch/powerpc/include/asm/unistd.h +++ b/arch/powerpc/include/asm/unistd.h | |||
@@ -367,10 +367,14 @@ | |||
367 | #define __NR_recvmsg 342 | 367 | #define __NR_recvmsg 342 |
368 | #define __NR_recvmmsg 343 | 368 | #define __NR_recvmmsg 343 |
369 | #define __NR_accept4 344 | 369 | #define __NR_accept4 344 |
370 | #define __NR_name_to_handle_at 345 | ||
371 | #define __NR_open_by_handle_at 346 | ||
372 | #define __NR_clock_adjtime 347 | ||
373 | #define __NR_syncfs 348 | ||
370 | 374 | ||
371 | #ifdef __KERNEL__ | 375 | #ifdef __KERNEL__ |
372 | 376 | ||
373 | #define __NR_syscalls 345 | 377 | #define __NR_syscalls 349 |
374 | 378 | ||
375 | #define __NR__exit __NR_exit | 379 | #define __NR__exit __NR_exit |
376 | #define NR_syscalls __NR_syscalls | 380 | #define NR_syscalls __NR_syscalls |
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c index cf02cad62d9a..d238c082c3c5 100644 --- a/arch/powerpc/kernel/dma.c +++ b/arch/powerpc/kernel/dma.c | |||
@@ -179,3 +179,21 @@ static int __init dma_init(void) | |||
179 | return 0; | 179 | return 0; |
180 | } | 180 | } |
181 | fs_initcall(dma_init); | 181 | fs_initcall(dma_init); |
182 | |||
183 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | ||
184 | void *cpu_addr, dma_addr_t handle, size_t size) | ||
185 | { | ||
186 | unsigned long pfn; | ||
187 | |||
188 | #ifdef CONFIG_NOT_COHERENT_CACHE | ||
189 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | ||
190 | pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr); | ||
191 | #else | ||
192 | pfn = page_to_pfn(virt_to_page(cpu_addr)); | ||
193 | #endif | ||
194 | return remap_pfn_range(vma, vma->vm_start, | ||
195 | pfn + vma->vm_pgoff, | ||
196 | vma->vm_end - vma->vm_start, | ||
197 | vma->vm_page_prot); | ||
198 | } | ||
199 | EXPORT_SYMBOL_GPL(dma_mmap_coherent); | ||
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 8a817995b4cd..c532cb2c927a 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S | |||
@@ -977,20 +977,6 @@ _GLOBAL(do_stab_bolted) | |||
977 | rfid | 977 | rfid |
978 | b . /* prevent speculative execution */ | 978 | b . /* prevent speculative execution */ |
979 | 979 | ||
980 | /* | ||
981 | * Space for CPU0's segment table. | ||
982 | * | ||
983 | * On iSeries, the hypervisor must fill in at least one entry before | ||
984 | * we get control (with relocate on). The address is given to the hv | ||
985 | * as a page number (see xLparMap below), so this must be at a | ||
986 | * fixed address (the linker can't compute (u64)&initial_stab >> | ||
987 | * PAGE_SHIFT). | ||
988 | */ | ||
989 | . = STAB0_OFFSET /* 0x6000 */ | ||
990 | .globl initial_stab | ||
991 | initial_stab: | ||
992 | .space 4096 | ||
993 | |||
994 | #ifdef CONFIG_PPC_PSERIES | 980 | #ifdef CONFIG_PPC_PSERIES |
995 | /* | 981 | /* |
996 | * Data area reserved for FWNMI option. | 982 | * Data area reserved for FWNMI option. |
@@ -1027,3 +1013,17 @@ xLparMap: | |||
1027 | #ifdef CONFIG_PPC_PSERIES | 1013 | #ifdef CONFIG_PPC_PSERIES |
1028 | . = 0x8000 | 1014 | . = 0x8000 |
1029 | #endif /* CONFIG_PPC_PSERIES */ | 1015 | #endif /* CONFIG_PPC_PSERIES */ |
1016 | |||
1017 | /* | ||
1018 | * Space for CPU0's segment table. | ||
1019 | * | ||
1020 | * On iSeries, the hypervisor must fill in at least one entry before | ||
1021 | * we get control (with relocate on). The address is given to the hv | ||
1022 | * as a page number (see xLparMap above), so this must be at a | ||
1023 | * fixed address (the linker can't compute (u64)&initial_stab >> | ||
1024 | * PAGE_SHIFT). | ||
1025 | */ | ||
1026 | . = STAB0_OFFSET /* 0x8000 */ | ||
1027 | .globl initial_stab | ||
1028 | initial_stab: | ||
1029 | .space 4096 | ||
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 98c4b29a56f4..c5c24beb8387 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S | |||
@@ -890,6 +890,15 @@ __secondary_start: | |||
890 | mtspr SPRN_SRR1,r4 | 890 | mtspr SPRN_SRR1,r4 |
891 | SYNC | 891 | SYNC |
892 | RFI | 892 | RFI |
893 | |||
894 | _GLOBAL(start_secondary_resume) | ||
895 | /* Reset stack */ | ||
896 | rlwinm r1,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */ | ||
897 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | ||
898 | li r3,0 | ||
899 | std r3,0(r1) /* Zero the stack frame pointer */ | ||
900 | bl start_secondary | ||
901 | b . | ||
893 | #endif /* CONFIG_SMP */ | 902 | #endif /* CONFIG_SMP */ |
894 | 903 | ||
895 | #ifdef CONFIG_KVM_BOOK3S_HANDLER | 904 | #ifdef CONFIG_KVM_BOOK3S_HANDLER |
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 782f23df7c85..271140b38b6f 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S | |||
@@ -536,6 +536,13 @@ _GLOBAL(pmac_secondary_start) | |||
536 | add r13,r13,r4 /* for this processor. */ | 536 | add r13,r13,r4 /* for this processor. */ |
537 | mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/ | 537 | mtspr SPRN_SPRG_PACA,r13 /* Save vaddr of paca in an SPRG*/ |
538 | 538 | ||
539 | /* Mark interrupts soft and hard disabled (they might be enabled | ||
540 | * in the PACA when doing hotplug) | ||
541 | */ | ||
542 | li r0,0 | ||
543 | stb r0,PACASOFTIRQEN(r13) | ||
544 | stb r0,PACAHARDIRQEN(r13) | ||
545 | |||
539 | /* Create a temp kernel stack for use before relocation is on. */ | 546 | /* Create a temp kernel stack for use before relocation is on. */ |
540 | ld r1,PACAEMERGSP(r13) | 547 | ld r1,PACAEMERGSP(r13) |
541 | subi r1,r1,STACK_FRAME_OVERHEAD | 548 | subi r1,r1,STACK_FRAME_OVERHEAD |
diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S index 5328709eeedc..ba3195478600 100644 --- a/arch/powerpc/kernel/idle_power4.S +++ b/arch/powerpc/kernel/idle_power4.S | |||
@@ -53,24 +53,3 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
53 | isync | 53 | isync |
54 | b 1b | 54 | b 1b |
55 | 55 | ||
56 | _GLOBAL(power4_cpu_offline_powersave) | ||
57 | /* Go to NAP now */ | ||
58 | mfmsr r7 | ||
59 | rldicl r0,r7,48,1 | ||
60 | rotldi r0,r0,16 | ||
61 | mtmsrd r0,1 /* hard-disable interrupts */ | ||
62 | li r0,1 | ||
63 | li r6,0 | ||
64 | stb r0,PACAHARDIRQEN(r13) /* we'll hard-enable shortly */ | ||
65 | stb r6,PACASOFTIRQEN(r13) /* soft-disable irqs */ | ||
66 | BEGIN_FTR_SECTION | ||
67 | DSSALL | ||
68 | sync | ||
69 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | ||
70 | ori r7,r7,MSR_EE | ||
71 | oris r7,r7,MSR_POW@h | ||
72 | sync | ||
73 | isync | ||
74 | mtmsrd r7 | ||
75 | isync | ||
76 | blr | ||
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 0a5570338b96..f621b7d2d869 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c | |||
@@ -195,7 +195,7 @@ notrace void arch_local_irq_restore(unsigned long en) | |||
195 | EXPORT_SYMBOL(arch_local_irq_restore); | 195 | EXPORT_SYMBOL(arch_local_irq_restore); |
196 | #endif /* CONFIG_PPC64 */ | 196 | #endif /* CONFIG_PPC64 */ |
197 | 197 | ||
198 | static int show_other_interrupts(struct seq_file *p, int prec) | 198 | int arch_show_interrupts(struct seq_file *p, int prec) |
199 | { | 199 | { |
200 | int j; | 200 | int j; |
201 | 201 | ||
@@ -231,65 +231,6 @@ static int show_other_interrupts(struct seq_file *p, int prec) | |||
231 | return 0; | 231 | return 0; |
232 | } | 232 | } |
233 | 233 | ||
234 | int show_interrupts(struct seq_file *p, void *v) | ||
235 | { | ||
236 | unsigned long flags, any_count = 0; | ||
237 | int i = *(loff_t *) v, j, prec; | ||
238 | struct irqaction *action; | ||
239 | struct irq_desc *desc; | ||
240 | struct irq_chip *chip; | ||
241 | |||
242 | if (i > nr_irqs) | ||
243 | return 0; | ||
244 | |||
245 | for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec) | ||
246 | j *= 10; | ||
247 | |||
248 | if (i == nr_irqs) | ||
249 | return show_other_interrupts(p, prec); | ||
250 | |||
251 | /* print header */ | ||
252 | if (i == 0) { | ||
253 | seq_printf(p, "%*s", prec + 8, ""); | ||
254 | for_each_online_cpu(j) | ||
255 | seq_printf(p, "CPU%-8d", j); | ||
256 | seq_putc(p, '\n'); | ||
257 | } | ||
258 | |||
259 | desc = irq_to_desc(i); | ||
260 | if (!desc) | ||
261 | return 0; | ||
262 | |||
263 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
264 | for_each_online_cpu(j) | ||
265 | any_count |= kstat_irqs_cpu(i, j); | ||
266 | action = desc->action; | ||
267 | if (!action && !any_count) | ||
268 | goto out; | ||
269 | |||
270 | seq_printf(p, "%*d: ", prec, i); | ||
271 | for_each_online_cpu(j) | ||
272 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | ||
273 | |||
274 | chip = get_irq_desc_chip(desc); | ||
275 | if (chip) | ||
276 | seq_printf(p, " %-16s", chip->name); | ||
277 | else | ||
278 | seq_printf(p, " %-16s", "None"); | ||
279 | seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge"); | ||
280 | |||
281 | if (action) { | ||
282 | seq_printf(p, " %s", action->name); | ||
283 | while ((action = action->next) != NULL) | ||
284 | seq_printf(p, ", %s", action->name); | ||
285 | } | ||
286 | |||
287 | seq_putc(p, '\n'); | ||
288 | out: | ||
289 | raw_spin_unlock_irqrestore(&desc->lock, flags); | ||
290 | return 0; | ||
291 | } | ||
292 | |||
293 | /* | 234 | /* |
294 | * /proc/stat helpers | 235 | * /proc/stat helpers |
295 | */ | 236 | */ |
@@ -305,34 +246,37 @@ u64 arch_irq_stat_cpu(unsigned int cpu) | |||
305 | } | 246 | } |
306 | 247 | ||
307 | #ifdef CONFIG_HOTPLUG_CPU | 248 | #ifdef CONFIG_HOTPLUG_CPU |
308 | void fixup_irqs(const struct cpumask *map) | 249 | void migrate_irqs(void) |
309 | { | 250 | { |
310 | struct irq_desc *desc; | 251 | struct irq_desc *desc; |
311 | unsigned int irq; | 252 | unsigned int irq; |
312 | static int warned; | 253 | static int warned; |
313 | cpumask_var_t mask; | 254 | cpumask_var_t mask; |
255 | const struct cpumask *map = cpu_online_mask; | ||
314 | 256 | ||
315 | alloc_cpumask_var(&mask, GFP_KERNEL); | 257 | alloc_cpumask_var(&mask, GFP_KERNEL); |
316 | 258 | ||
317 | for_each_irq(irq) { | 259 | for_each_irq(irq) { |
260 | struct irq_data *data; | ||
318 | struct irq_chip *chip; | 261 | struct irq_chip *chip; |
319 | 262 | ||
320 | desc = irq_to_desc(irq); | 263 | desc = irq_to_desc(irq); |
321 | if (!desc) | 264 | if (!desc) |
322 | continue; | 265 | continue; |
323 | 266 | ||
324 | if (desc->status & IRQ_PER_CPU) | 267 | data = irq_desc_get_irq_data(desc); |
268 | if (irqd_is_per_cpu(data)) | ||
325 | continue; | 269 | continue; |
326 | 270 | ||
327 | chip = get_irq_desc_chip(desc); | 271 | chip = irq_data_get_irq_chip(data); |
328 | 272 | ||
329 | cpumask_and(mask, desc->irq_data.affinity, map); | 273 | cpumask_and(mask, data->affinity, map); |
330 | if (cpumask_any(mask) >= nr_cpu_ids) { | 274 | if (cpumask_any(mask) >= nr_cpu_ids) { |
331 | printk("Breaking affinity for irq %i\n", irq); | 275 | printk("Breaking affinity for irq %i\n", irq); |
332 | cpumask_copy(mask, map); | 276 | cpumask_copy(mask, map); |
333 | } | 277 | } |
334 | if (chip->irq_set_affinity) | 278 | if (chip->irq_set_affinity) |
335 | chip->irq_set_affinity(&desc->irq_data, mask, true); | 279 | chip->irq_set_affinity(data, mask, true); |
336 | else if (desc->action && !(warned++)) | 280 | else if (desc->action && !(warned++)) |
337 | printk("Cannot set affinity for irq %i\n", irq); | 281 | printk("Cannot set affinity for irq %i\n", irq); |
338 | } | 282 | } |
@@ -618,7 +562,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node, | |||
618 | smp_wmb(); | 562 | smp_wmb(); |
619 | 563 | ||
620 | /* Clear norequest flags */ | 564 | /* Clear norequest flags */ |
621 | irq_to_desc(i)->status &= ~IRQ_NOREQUEST; | 565 | irq_clear_status_flags(i, IRQ_NOREQUEST); |
622 | 566 | ||
623 | /* Legacy flags are left to default at this point, | 567 | /* Legacy flags are left to default at this point, |
624 | * one can then use irq_create_mapping() to | 568 | * one can then use irq_create_mapping() to |
@@ -827,8 +771,8 @@ unsigned int irq_create_of_mapping(struct device_node *controller, | |||
827 | 771 | ||
828 | /* Set type if specified and different than the current one */ | 772 | /* Set type if specified and different than the current one */ |
829 | if (type != IRQ_TYPE_NONE && | 773 | if (type != IRQ_TYPE_NONE && |
830 | type != (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK)) | 774 | type != (irqd_get_trigger_type(irq_get_irq_data(virq)))) |
831 | set_irq_type(virq, type); | 775 | irq_set_irq_type(virq, type); |
832 | return virq; | 776 | return virq; |
833 | } | 777 | } |
834 | EXPORT_SYMBOL_GPL(irq_create_of_mapping); | 778 | EXPORT_SYMBOL_GPL(irq_create_of_mapping); |
@@ -851,7 +795,7 @@ void irq_dispose_mapping(unsigned int virq) | |||
851 | return; | 795 | return; |
852 | 796 | ||
853 | /* remove chip and handler */ | 797 | /* remove chip and handler */ |
854 | set_irq_chip_and_handler(virq, NULL, NULL); | 798 | irq_set_chip_and_handler(virq, NULL, NULL); |
855 | 799 | ||
856 | /* Make sure it's completed */ | 800 | /* Make sure it's completed */ |
857 | synchronize_irq(virq); | 801 | synchronize_irq(virq); |
@@ -1156,7 +1100,7 @@ static int virq_debug_show(struct seq_file *m, void *private) | |||
1156 | seq_printf(m, "%5d ", i); | 1100 | seq_printf(m, "%5d ", i); |
1157 | seq_printf(m, "0x%05lx ", virq_to_hw(i)); | 1101 | seq_printf(m, "0x%05lx ", virq_to_hw(i)); |
1158 | 1102 | ||
1159 | chip = get_irq_desc_chip(desc); | 1103 | chip = irq_desc_get_chip(desc); |
1160 | if (chip && chip->name) | 1104 | if (chip && chip->name) |
1161 | p = chip->name; | 1105 | p = chip->name; |
1162 | else | 1106 | else |
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index bd1e1ff17b2d..7ee50f0547cb 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c | |||
@@ -31,17 +31,17 @@ void machine_kexec_mask_interrupts(void) { | |||
31 | if (!desc) | 31 | if (!desc) |
32 | continue; | 32 | continue; |
33 | 33 | ||
34 | chip = get_irq_desc_chip(desc); | 34 | chip = irq_desc_get_chip(desc); |
35 | if (!chip) | 35 | if (!chip) |
36 | continue; | 36 | continue; |
37 | 37 | ||
38 | if (chip->irq_eoi && desc->status & IRQ_INPROGRESS) | 38 | if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) |
39 | chip->irq_eoi(&desc->irq_data); | 39 | chip->irq_eoi(&desc->irq_data); |
40 | 40 | ||
41 | if (chip->irq_mask) | 41 | if (chip->irq_mask) |
42 | chip->irq_mask(&desc->irq_data); | 42 | chip->irq_mask(&desc->irq_data); |
43 | 43 | ||
44 | if (chip->irq_disable && !(desc->status & IRQ_DISABLED)) | 44 | if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) |
45 | chip->irq_disable(&desc->irq_data); | 45 | chip->irq_disable(&desc->irq_data); |
46 | } | 46 | } |
47 | } | 47 | } |
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index 3cd85faa8ac6..893af2a9cd03 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c | |||
@@ -261,7 +261,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev) | |||
261 | 261 | ||
262 | virq = irq_create_mapping(NULL, line); | 262 | virq = irq_create_mapping(NULL, line); |
263 | if (virq != NO_IRQ) | 263 | if (virq != NO_IRQ) |
264 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | 264 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
265 | } else { | 265 | } else { |
266 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", | 266 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
267 | oirq.size, oirq.specifier[0], oirq.specifier[1], | 267 | oirq.size, oirq.specifier[0], oirq.specifier[1], |
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 981360509172..cbdbb14be4b0 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c | |||
@@ -57,6 +57,25 @@ | |||
57 | #define DBG(fmt...) | 57 | #define DBG(fmt...) |
58 | #endif | 58 | #endif |
59 | 59 | ||
60 | |||
61 | /* Store all idle threads, this can be reused instead of creating | ||
62 | * a new thread. Also avoids complicated thread destroy functionality | ||
63 | * for idle threads. | ||
64 | */ | ||
65 | #ifdef CONFIG_HOTPLUG_CPU | ||
66 | /* | ||
67 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | ||
68 | * removed after init for !CONFIG_HOTPLUG_CPU. | ||
69 | */ | ||
70 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | ||
71 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | ||
72 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | ||
73 | #else | ||
74 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | ||
75 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | ||
76 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | ||
77 | #endif | ||
78 | |||
60 | struct thread_info *secondary_ti; | 79 | struct thread_info *secondary_ti; |
61 | 80 | ||
62 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); | 81 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
@@ -238,23 +257,6 @@ static void __devinit smp_store_cpu_info(int id) | |||
238 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); | 257 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
239 | } | 258 | } |
240 | 259 | ||
241 | static void __init smp_create_idle(unsigned int cpu) | ||
242 | { | ||
243 | struct task_struct *p; | ||
244 | |||
245 | /* create a process for the processor */ | ||
246 | p = fork_idle(cpu); | ||
247 | if (IS_ERR(p)) | ||
248 | panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p)); | ||
249 | #ifdef CONFIG_PPC64 | ||
250 | paca[cpu].__current = p; | ||
251 | paca[cpu].kstack = (unsigned long) task_thread_info(p) | ||
252 | + THREAD_SIZE - STACK_FRAME_OVERHEAD; | ||
253 | #endif | ||
254 | current_set[cpu] = task_thread_info(p); | ||
255 | task_thread_info(p)->cpu = cpu; | ||
256 | } | ||
257 | |||
258 | void __init smp_prepare_cpus(unsigned int max_cpus) | 260 | void __init smp_prepare_cpus(unsigned int max_cpus) |
259 | { | 261 | { |
260 | unsigned int cpu; | 262 | unsigned int cpu; |
@@ -288,10 +290,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
288 | max_cpus = NR_CPUS; | 290 | max_cpus = NR_CPUS; |
289 | else | 291 | else |
290 | max_cpus = 1; | 292 | max_cpus = 1; |
291 | |||
292 | for_each_possible_cpu(cpu) | ||
293 | if (cpu != boot_cpuid) | ||
294 | smp_create_idle(cpu); | ||
295 | } | 293 | } |
296 | 294 | ||
297 | void __devinit smp_prepare_boot_cpu(void) | 295 | void __devinit smp_prepare_boot_cpu(void) |
@@ -305,7 +303,7 @@ void __devinit smp_prepare_boot_cpu(void) | |||
305 | 303 | ||
306 | #ifdef CONFIG_HOTPLUG_CPU | 304 | #ifdef CONFIG_HOTPLUG_CPU |
307 | /* State of each CPU during hotplug phases */ | 305 | /* State of each CPU during hotplug phases */ |
308 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | 306 | static DEFINE_PER_CPU(int, cpu_state) = { 0 }; |
309 | 307 | ||
310 | int generic_cpu_disable(void) | 308 | int generic_cpu_disable(void) |
311 | { | 309 | { |
@@ -317,30 +315,8 @@ int generic_cpu_disable(void) | |||
317 | set_cpu_online(cpu, false); | 315 | set_cpu_online(cpu, false); |
318 | #ifdef CONFIG_PPC64 | 316 | #ifdef CONFIG_PPC64 |
319 | vdso_data->processorCount--; | 317 | vdso_data->processorCount--; |
320 | fixup_irqs(cpu_online_mask); | ||
321 | #endif | ||
322 | return 0; | ||
323 | } | ||
324 | |||
325 | int generic_cpu_enable(unsigned int cpu) | ||
326 | { | ||
327 | /* Do the normal bootup if we haven't | ||
328 | * already bootstrapped. */ | ||
329 | if (system_state != SYSTEM_RUNNING) | ||
330 | return -ENOSYS; | ||
331 | |||
332 | /* get the target out of it's holding state */ | ||
333 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | ||
334 | smp_wmb(); | ||
335 | |||
336 | while (!cpu_online(cpu)) | ||
337 | cpu_relax(); | ||
338 | |||
339 | #ifdef CONFIG_PPC64 | ||
340 | fixup_irqs(cpu_online_mask); | ||
341 | /* counter the irq disable in fixup_irqs */ | ||
342 | local_irq_enable(); | ||
343 | #endif | 318 | #endif |
319 | migrate_irqs(); | ||
344 | return 0; | 320 | return 0; |
345 | } | 321 | } |
346 | 322 | ||
@@ -362,37 +338,89 @@ void generic_mach_cpu_die(void) | |||
362 | unsigned int cpu; | 338 | unsigned int cpu; |
363 | 339 | ||
364 | local_irq_disable(); | 340 | local_irq_disable(); |
341 | idle_task_exit(); | ||
365 | cpu = smp_processor_id(); | 342 | cpu = smp_processor_id(); |
366 | printk(KERN_DEBUG "CPU%d offline\n", cpu); | 343 | printk(KERN_DEBUG "CPU%d offline\n", cpu); |
367 | __get_cpu_var(cpu_state) = CPU_DEAD; | 344 | __get_cpu_var(cpu_state) = CPU_DEAD; |
368 | smp_wmb(); | 345 | smp_wmb(); |
369 | while (__get_cpu_var(cpu_state) != CPU_UP_PREPARE) | 346 | while (__get_cpu_var(cpu_state) != CPU_UP_PREPARE) |
370 | cpu_relax(); | 347 | cpu_relax(); |
371 | set_cpu_online(cpu, true); | 348 | } |
372 | local_irq_enable(); | 349 | |
350 | void generic_set_cpu_dead(unsigned int cpu) | ||
351 | { | ||
352 | per_cpu(cpu_state, cpu) = CPU_DEAD; | ||
373 | } | 353 | } |
374 | #endif | 354 | #endif |
375 | 355 | ||
376 | static int __devinit cpu_enable(unsigned int cpu) | 356 | struct create_idle { |
357 | struct work_struct work; | ||
358 | struct task_struct *idle; | ||
359 | struct completion done; | ||
360 | int cpu; | ||
361 | }; | ||
362 | |||
363 | static void __cpuinit do_fork_idle(struct work_struct *work) | ||
377 | { | 364 | { |
378 | if (smp_ops && smp_ops->cpu_enable) | 365 | struct create_idle *c_idle = |
379 | return smp_ops->cpu_enable(cpu); | 366 | container_of(work, struct create_idle, work); |
367 | |||
368 | c_idle->idle = fork_idle(c_idle->cpu); | ||
369 | complete(&c_idle->done); | ||
370 | } | ||
371 | |||
372 | static int __cpuinit create_idle(unsigned int cpu) | ||
373 | { | ||
374 | struct thread_info *ti; | ||
375 | struct create_idle c_idle = { | ||
376 | .cpu = cpu, | ||
377 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | ||
378 | }; | ||
379 | INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); | ||
380 | |||
381 | c_idle.idle = get_idle_for_cpu(cpu); | ||
382 | |||
383 | /* We can't use kernel_thread since we must avoid to | ||
384 | * reschedule the child. We use a workqueue because | ||
385 | * we want to fork from a kernel thread, not whatever | ||
386 | * userspace process happens to be trying to online us. | ||
387 | */ | ||
388 | if (!c_idle.idle) { | ||
389 | schedule_work(&c_idle.work); | ||
390 | wait_for_completion(&c_idle.done); | ||
391 | } else | ||
392 | init_idle(c_idle.idle, cpu); | ||
393 | if (IS_ERR(c_idle.idle)) { | ||
394 | pr_err("Failed fork for CPU %u: %li", cpu, PTR_ERR(c_idle.idle)); | ||
395 | return PTR_ERR(c_idle.idle); | ||
396 | } | ||
397 | ti = task_thread_info(c_idle.idle); | ||
398 | |||
399 | #ifdef CONFIG_PPC64 | ||
400 | paca[cpu].__current = c_idle.idle; | ||
401 | paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD; | ||
402 | #endif | ||
403 | ti->cpu = cpu; | ||
404 | current_set[cpu] = ti; | ||
380 | 405 | ||
381 | return -ENOSYS; | 406 | return 0; |
382 | } | 407 | } |
383 | 408 | ||
384 | int __cpuinit __cpu_up(unsigned int cpu) | 409 | int __cpuinit __cpu_up(unsigned int cpu) |
385 | { | 410 | { |
386 | int c; | 411 | int rc, c; |
387 | 412 | ||
388 | secondary_ti = current_set[cpu]; | 413 | secondary_ti = current_set[cpu]; |
389 | if (!cpu_enable(cpu)) | ||
390 | return 0; | ||
391 | 414 | ||
392 | if (smp_ops == NULL || | 415 | if (smp_ops == NULL || |
393 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) | 416 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) |
394 | return -EINVAL; | 417 | return -EINVAL; |
395 | 418 | ||
419 | /* Make sure we have an idle thread */ | ||
420 | rc = create_idle(cpu); | ||
421 | if (rc) | ||
422 | return rc; | ||
423 | |||
396 | /* Make sure callin-map entry is 0 (can be leftover a CPU | 424 | /* Make sure callin-map entry is 0 (can be leftover a CPU |
397 | * hotplug | 425 | * hotplug |
398 | */ | 426 | */ |
@@ -502,7 +530,7 @@ static struct device_node *cpu_to_l2cache(int cpu) | |||
502 | } | 530 | } |
503 | 531 | ||
504 | /* Activate a secondary processor. */ | 532 | /* Activate a secondary processor. */ |
505 | int __devinit start_secondary(void *unused) | 533 | void __devinit start_secondary(void *unused) |
506 | { | 534 | { |
507 | unsigned int cpu = smp_processor_id(); | 535 | unsigned int cpu = smp_processor_id(); |
508 | struct device_node *l2_cache; | 536 | struct device_node *l2_cache; |
@@ -523,6 +551,10 @@ int __devinit start_secondary(void *unused) | |||
523 | 551 | ||
524 | secondary_cpu_time_init(); | 552 | secondary_cpu_time_init(); |
525 | 553 | ||
554 | #ifdef CONFIG_PPC64 | ||
555 | if (system_state == SYSTEM_RUNNING) | ||
556 | vdso_data->processorCount++; | ||
557 | #endif | ||
526 | ipi_call_lock(); | 558 | ipi_call_lock(); |
527 | notify_cpu_starting(cpu); | 559 | notify_cpu_starting(cpu); |
528 | set_cpu_online(cpu, true); | 560 | set_cpu_online(cpu, true); |
@@ -558,7 +590,8 @@ int __devinit start_secondary(void *unused) | |||
558 | local_irq_enable(); | 590 | local_irq_enable(); |
559 | 591 | ||
560 | cpu_idle(); | 592 | cpu_idle(); |
561 | return 0; | 593 | |
594 | BUG(); | ||
562 | } | 595 | } |
563 | 596 | ||
564 | int setup_profiling_timer(unsigned int multiplier) | 597 | int setup_profiling_timer(unsigned int multiplier) |
@@ -585,7 +618,11 @@ void __init smp_cpus_done(unsigned int max_cpus) | |||
585 | 618 | ||
586 | free_cpumask_var(old_mask); | 619 | free_cpumask_var(old_mask); |
587 | 620 | ||
621 | if (smp_ops && smp_ops->bringup_done) | ||
622 | smp_ops->bringup_done(); | ||
623 | |||
588 | dump_numa_cpu_topology(); | 624 | dump_numa_cpu_topology(); |
625 | |||
589 | } | 626 | } |
590 | 627 | ||
591 | int arch_sd_sibling_asym_packing(void) | 628 | int arch_sd_sibling_asym_packing(void) |
@@ -660,5 +697,9 @@ void cpu_die(void) | |||
660 | { | 697 | { |
661 | if (ppc_md.cpu_die) | 698 | if (ppc_md.cpu_die) |
662 | ppc_md.cpu_die(); | 699 | ppc_md.cpu_die(); |
700 | |||
701 | /* If we return, we re-enter start_secondary */ | ||
702 | start_secondary_resume(); | ||
663 | } | 703 | } |
704 | |||
664 | #endif | 705 | #endif |
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c index 09d31dbf43f9..375480c56eb9 100644 --- a/arch/powerpc/kernel/time.c +++ b/arch/powerpc/kernel/time.c | |||
@@ -356,7 +356,7 @@ void account_system_vtime(struct task_struct *tsk) | |||
356 | } | 356 | } |
357 | get_paca()->user_time_scaled += user_scaled; | 357 | get_paca()->user_time_scaled += user_scaled; |
358 | 358 | ||
359 | if (in_irq() || idle_task(smp_processor_id()) != tsk) { | 359 | if (in_interrupt() || idle_task(smp_processor_id()) != tsk) { |
360 | account_system_time(tsk, 0, delta, sys_scaled); | 360 | account_system_time(tsk, 0, delta, sys_scaled); |
361 | if (stolen) | 361 | if (stolen) |
362 | account_steal_time(stolen); | 362 | account_steal_time(stolen); |
@@ -577,14 +577,21 @@ void timer_interrupt(struct pt_regs * regs) | |||
577 | struct clock_event_device *evt = &decrementer->event; | 577 | struct clock_event_device *evt = &decrementer->event; |
578 | u64 now; | 578 | u64 now; |
579 | 579 | ||
580 | /* Ensure a positive value is written to the decrementer, or else | ||
581 | * some CPUs will continue to take decrementer exceptions. | ||
582 | */ | ||
583 | set_dec(DECREMENTER_MAX); | ||
584 | |||
585 | /* Some implementations of hotplug will get timer interrupts while | ||
586 | * offline, just ignore these | ||
587 | */ | ||
588 | if (!cpu_online(smp_processor_id())) | ||
589 | return; | ||
590 | |||
580 | trace_timer_interrupt_entry(regs); | 591 | trace_timer_interrupt_entry(regs); |
581 | 592 | ||
582 | __get_cpu_var(irq_stat).timer_irqs++; | 593 | __get_cpu_var(irq_stat).timer_irqs++; |
583 | 594 | ||
584 | /* Ensure a positive value is written to the decrementer, or else | ||
585 | * some CPUs will continuue to take decrementer exceptions */ | ||
586 | set_dec(DECREMENTER_MAX); | ||
587 | |||
588 | #if defined(CONFIG_PPC32) && defined(CONFIG_PMAC) | 595 | #if defined(CONFIG_PPC32) && defined(CONFIG_PMAC) |
589 | if (atomic_read(&ppc_n_lost_interrupts) != 0) | 596 | if (atomic_read(&ppc_n_lost_interrupts) != 0) |
590 | do_IRQ(regs); | 597 | do_IRQ(regs); |
diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c index 757c0bed9a91..b42f76c4948d 100644 --- a/arch/powerpc/mm/dma-noncoherent.c +++ b/arch/powerpc/mm/dma-noncoherent.c | |||
@@ -399,3 +399,23 @@ void __dma_sync_page(struct page *page, unsigned long offset, | |||
399 | #endif | 399 | #endif |
400 | } | 400 | } |
401 | EXPORT_SYMBOL(__dma_sync_page); | 401 | EXPORT_SYMBOL(__dma_sync_page); |
402 | |||
403 | /* | ||
404 | * Return the PFN for a given cpu virtual address returned by | ||
405 | * __dma_alloc_coherent. This is used by dma_mmap_coherent() | ||
406 | */ | ||
407 | unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr) | ||
408 | { | ||
409 | /* This should always be populated, so we don't test every | ||
410 | * level. If that fails, we'll have a nice crash which | ||
411 | * will be as good as a BUG_ON() | ||
412 | */ | ||
413 | pgd_t *pgd = pgd_offset_k(cpu_addr); | ||
414 | pud_t *pud = pud_offset(pgd, cpu_addr); | ||
415 | pmd_t *pmd = pmd_offset(pud, cpu_addr); | ||
416 | pte_t *ptep = pte_offset_kernel(pmd, cpu_addr); | ||
417 | |||
418 | if (pte_none(*ptep) || !pte_present(*ptep)) | ||
419 | return 0; | ||
420 | return pte_pfn(*ptep); | ||
421 | } | ||
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c index fde0ea50c97d..cfc4b2009982 100644 --- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c +++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c | |||
@@ -132,8 +132,8 @@ static int | |||
132 | cpld_pic_host_map(struct irq_host *h, unsigned int virq, | 132 | cpld_pic_host_map(struct irq_host *h, unsigned int virq, |
133 | irq_hw_number_t hw) | 133 | irq_hw_number_t hw) |
134 | { | 134 | { |
135 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 135 | irq_set_status_flags(virq, IRQ_LEVEL); |
136 | set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq); | 136 | irq_set_chip_and_handler(virq, &cpld_pic, handle_level_irq); |
137 | return 0; | 137 | return 0; |
138 | } | 138 | } |
139 | 139 | ||
@@ -198,7 +198,7 @@ mpc5121_ads_cpld_pic_init(void) | |||
198 | goto end; | 198 | goto end; |
199 | } | 199 | } |
200 | 200 | ||
201 | set_irq_chained_handler(cascade_irq, cpld_pic_cascade); | 201 | irq_set_chained_handler(cascade_irq, cpld_pic_cascade); |
202 | end: | 202 | end: |
203 | of_node_put(np); | 203 | of_node_put(np); |
204 | } | 204 | } |
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c index 2bd1e6cf1f58..57a6a349e932 100644 --- a/arch/powerpc/platforms/52xx/media5200.c +++ b/arch/powerpc/platforms/52xx/media5200.c | |||
@@ -82,7 +82,7 @@ static struct irq_chip media5200_irq_chip = { | |||
82 | 82 | ||
83 | void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | 83 | void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) |
84 | { | 84 | { |
85 | struct irq_chip *chip = get_irq_desc_chip(desc); | 85 | struct irq_chip *chip = irq_desc_get_chip(desc); |
86 | int sub_virq, val; | 86 | int sub_virq, val; |
87 | u32 status, enable; | 87 | u32 status, enable; |
88 | 88 | ||
@@ -107,7 +107,7 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
107 | /* Processing done; can reenable the cascade now */ | 107 | /* Processing done; can reenable the cascade now */ |
108 | raw_spin_lock(&desc->lock); | 108 | raw_spin_lock(&desc->lock); |
109 | chip->irq_ack(&desc->irq_data); | 109 | chip->irq_ack(&desc->irq_data); |
110 | if (!(desc->status & IRQ_DISABLED)) | 110 | if (!irqd_irq_disabled(&desc->irq_data)) |
111 | chip->irq_unmask(&desc->irq_data); | 111 | chip->irq_unmask(&desc->irq_data); |
112 | raw_spin_unlock(&desc->lock); | 112 | raw_spin_unlock(&desc->lock); |
113 | } | 113 | } |
@@ -115,15 +115,10 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
115 | static int media5200_irq_map(struct irq_host *h, unsigned int virq, | 115 | static int media5200_irq_map(struct irq_host *h, unsigned int virq, |
116 | irq_hw_number_t hw) | 116 | irq_hw_number_t hw) |
117 | { | 117 | { |
118 | struct irq_desc *desc = irq_to_desc(virq); | ||
119 | |||
120 | pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); | 118 | pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); |
121 | set_irq_chip_data(virq, &media5200_irq); | 119 | irq_set_chip_data(virq, &media5200_irq); |
122 | set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); | 120 | irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); |
123 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | 121 | irq_set_status_flags(virq, IRQ_LEVEL); |
124 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
125 | desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL; | ||
126 | |||
127 | return 0; | 122 | return 0; |
128 | } | 123 | } |
129 | 124 | ||
@@ -187,8 +182,8 @@ static void __init media5200_init_irq(void) | |||
187 | 182 | ||
188 | media5200_irq.irqhost->host_data = &media5200_irq; | 183 | media5200_irq.irqhost->host_data = &media5200_irq; |
189 | 184 | ||
190 | set_irq_data(cascade_virq, &media5200_irq); | 185 | irq_set_handler_data(cascade_virq, &media5200_irq); |
191 | set_irq_chained_handler(cascade_virq, media5200_irq_cascade); | 186 | irq_set_chained_handler(cascade_virq, media5200_irq_cascade); |
192 | 187 | ||
193 | return; | 188 | return; |
194 | 189 | ||
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 6da44f0f2934..6c39b9cc2fa3 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c | |||
@@ -192,7 +192,7 @@ static struct irq_chip mpc52xx_gpt_irq_chip = { | |||
192 | 192 | ||
193 | void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) | 193 | void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) |
194 | { | 194 | { |
195 | struct mpc52xx_gpt_priv *gpt = get_irq_data(virq); | 195 | struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq); |
196 | int sub_virq; | 196 | int sub_virq; |
197 | u32 status; | 197 | u32 status; |
198 | 198 | ||
@@ -209,8 +209,8 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq, | |||
209 | struct mpc52xx_gpt_priv *gpt = h->host_data; | 209 | struct mpc52xx_gpt_priv *gpt = h->host_data; |
210 | 210 | ||
211 | dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); | 211 | dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); |
212 | set_irq_chip_data(virq, gpt); | 212 | irq_set_chip_data(virq, gpt); |
213 | set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); | 213 | irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); |
214 | 214 | ||
215 | return 0; | 215 | return 0; |
216 | } | 216 | } |
@@ -259,8 +259,8 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) | |||
259 | } | 259 | } |
260 | 260 | ||
261 | gpt->irqhost->host_data = gpt; | 261 | gpt->irqhost->host_data = gpt; |
262 | set_irq_data(cascade_virq, gpt); | 262 | irq_set_handler_data(cascade_virq, gpt); |
263 | set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); | 263 | irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); |
264 | 264 | ||
265 | /* If the GPT is currently disabled, then change it to be in Input | 265 | /* If the GPT is currently disabled, then change it to be in Input |
266 | * Capture mode. If the mode is non-zero, then the pin could be | 266 | * Capture mode. If the mode is non-zero, then the pin could be |
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c index 9f3ed582d082..3ddea96273ca 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c | |||
@@ -214,7 +214,7 @@ static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type) | |||
214 | ctrl_reg |= (type << (22 - (l2irq * 2))); | 214 | ctrl_reg |= (type << (22 - (l2irq * 2))); |
215 | out_be32(&intr->ctrl, ctrl_reg); | 215 | out_be32(&intr->ctrl, ctrl_reg); |
216 | 216 | ||
217 | __set_irq_handler_unlocked(d->irq, handler); | 217 | __irq_set_handler_locked(d->irq, handler); |
218 | 218 | ||
219 | return 0; | 219 | return 0; |
220 | } | 220 | } |
@@ -414,7 +414,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, | |||
414 | else | 414 | else |
415 | hndlr = handle_level_irq; | 415 | hndlr = handle_level_irq; |
416 | 416 | ||
417 | set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr); | 417 | irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr); |
418 | pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n", | 418 | pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n", |
419 | __func__, l2irq, virq, (int)irq, type); | 419 | __func__, l2irq, virq, (int)irq, type); |
420 | return 0; | 420 | return 0; |
@@ -431,7 +431,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, | |||
431 | return -EINVAL; | 431 | return -EINVAL; |
432 | } | 432 | } |
433 | 433 | ||
434 | set_irq_chip_and_handler(virq, irqchip, handle_level_irq); | 434 | irq_set_chip_and_handler(virq, irqchip, handle_level_irq); |
435 | pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq); | 435 | pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq); |
436 | 436 | ||
437 | return 0; | 437 | return 0; |
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c index 926dfdaaf57a..4a4eb6ffa12f 100644 --- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c +++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | |||
@@ -81,7 +81,7 @@ static struct irq_chip pq2ads_pci_ic = { | |||
81 | 81 | ||
82 | static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) | 82 | static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) |
83 | { | 83 | { |
84 | struct pq2ads_pci_pic *priv = get_irq_desc_data(desc); | 84 | struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc); |
85 | u32 stat, mask, pend; | 85 | u32 stat, mask, pend; |
86 | int bit; | 86 | int bit; |
87 | 87 | ||
@@ -106,17 +106,17 @@ static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) | |||
106 | static int pci_pic_host_map(struct irq_host *h, unsigned int virq, | 106 | static int pci_pic_host_map(struct irq_host *h, unsigned int virq, |
107 | irq_hw_number_t hw) | 107 | irq_hw_number_t hw) |
108 | { | 108 | { |
109 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 109 | irq_set_status_flags(virq, IRQ_LEVEL); |
110 | set_irq_chip_data(virq, h->host_data); | 110 | irq_set_chip_data(virq, h->host_data); |
111 | set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq); | 111 | irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq); |
112 | return 0; | 112 | return 0; |
113 | } | 113 | } |
114 | 114 | ||
115 | static void pci_host_unmap(struct irq_host *h, unsigned int virq) | 115 | static void pci_host_unmap(struct irq_host *h, unsigned int virq) |
116 | { | 116 | { |
117 | /* remove chip and handler */ | 117 | /* remove chip and handler */ |
118 | set_irq_chip_data(virq, NULL); | 118 | irq_set_chip_data(virq, NULL); |
119 | set_irq_chip(virq, NULL); | 119 | irq_set_chip(virq, NULL); |
120 | } | 120 | } |
121 | 121 | ||
122 | static struct irq_host_ops pci_pic_host_ops = { | 122 | static struct irq_host_ops pci_pic_host_ops = { |
@@ -175,8 +175,8 @@ int __init pq2ads_pci_init_irq(void) | |||
175 | 175 | ||
176 | priv->host = host; | 176 | priv->host = host; |
177 | host->host_data = priv; | 177 | host->host_data = priv; |
178 | set_irq_data(irq, priv); | 178 | irq_set_handler_data(irq, priv); |
179 | set_irq_chained_handler(irq, pq2ads_pci_irq_demux); | 179 | irq_set_chained_handler(irq, pq2ads_pci_irq_demux); |
180 | 180 | ||
181 | of_node_put(np); | 181 | of_node_put(np); |
182 | return 0; | 182 | return 0; |
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c index 64447e48f3d5..c46f9359be15 100644 --- a/arch/powerpc/platforms/85xx/ksi8560.c +++ b/arch/powerpc/platforms/85xx/ksi8560.c | |||
@@ -56,7 +56,7 @@ static void machine_restart(char *cmd) | |||
56 | 56 | ||
57 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 57 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
58 | { | 58 | { |
59 | struct irq_chip *chip = get_irq_desc_chip(desc); | 59 | struct irq_chip *chip = irq_desc_get_chip(desc); |
60 | int cascade_irq; | 60 | int cascade_irq; |
61 | 61 | ||
62 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 62 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -106,7 +106,7 @@ static void __init ksi8560_pic_init(void) | |||
106 | 106 | ||
107 | cpm2_pic_init(np); | 107 | cpm2_pic_init(np); |
108 | of_node_put(np); | 108 | of_node_put(np); |
109 | set_irq_chained_handler(irq, cpm2_cascade); | 109 | irq_set_chained_handler(irq, cpm2_cascade); |
110 | #endif | 110 | #endif |
111 | } | 111 | } |
112 | 112 | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c index 1352d1107bfd..3b2c9bb66199 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c | |||
@@ -50,7 +50,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose, | |||
50 | 50 | ||
51 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 51 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
52 | { | 52 | { |
53 | struct irq_chip *chip = get_irq_desc_chip(desc); | 53 | struct irq_chip *chip = irq_desc_get_chip(desc); |
54 | int cascade_irq; | 54 | int cascade_irq; |
55 | 55 | ||
56 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 56 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -101,7 +101,7 @@ static void __init mpc85xx_ads_pic_init(void) | |||
101 | 101 | ||
102 | cpm2_pic_init(np); | 102 | cpm2_pic_init(np); |
103 | of_node_put(np); | 103 | of_node_put(np); |
104 | set_irq_chained_handler(irq, cpm2_cascade); | 104 | irq_set_chained_handler(irq, cpm2_cascade); |
105 | #endif | 105 | #endif |
106 | } | 106 | } |
107 | 107 | ||
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c index 458d91fba91d..6299a2a51ae8 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c | |||
@@ -255,7 +255,7 @@ static int mpc85xx_cds_8259_attach(void) | |||
255 | } | 255 | } |
256 | 256 | ||
257 | /* Success. Connect our low-level cascade handler. */ | 257 | /* Success. Connect our low-level cascade handler. */ |
258 | set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler); | 258 | irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler); |
259 | 259 | ||
260 | return 0; | 260 | return 0; |
261 | } | 261 | } |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index 793ead7993ab..c7b97f70312e 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c | |||
@@ -47,7 +47,7 @@ | |||
47 | #ifdef CONFIG_PPC_I8259 | 47 | #ifdef CONFIG_PPC_I8259 |
48 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) | 48 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
49 | { | 49 | { |
50 | struct irq_chip *chip = get_irq_desc_chip(desc); | 50 | struct irq_chip *chip = irq_desc_get_chip(desc); |
51 | unsigned int cascade_irq = i8259_irq(); | 51 | unsigned int cascade_irq = i8259_irq(); |
52 | 52 | ||
53 | if (cascade_irq != NO_IRQ) { | 53 | if (cascade_irq != NO_IRQ) { |
@@ -122,7 +122,7 @@ void __init mpc85xx_ds_pic_init(void) | |||
122 | i8259_init(cascade_node, 0); | 122 | i8259_init(cascade_node, 0); |
123 | of_node_put(cascade_node); | 123 | of_node_put(cascade_node); |
124 | 124 | ||
125 | set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); | 125 | irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade); |
126 | #endif /* CONFIG_PPC_I8259 */ | 126 | #endif /* CONFIG_PPC_I8259 */ |
127 | } | 127 | } |
128 | 128 | ||
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c index d7e28ec3e072..d2dfd465fbf6 100644 --- a/arch/powerpc/platforms/85xx/sbc8560.c +++ b/arch/powerpc/platforms/85xx/sbc8560.c | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 42 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
43 | { | 43 | { |
44 | struct irq_chip *chip = get_irq_desc_chip(desc); | 44 | struct irq_chip *chip = irq_desc_get_chip(desc); |
45 | int cascade_irq; | 45 | int cascade_irq; |
46 | 46 | ||
47 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 47 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -92,7 +92,7 @@ static void __init sbc8560_pic_init(void) | |||
92 | 92 | ||
93 | cpm2_pic_init(np); | 93 | cpm2_pic_init(np); |
94 | of_node_put(np); | 94 | of_node_put(np); |
95 | set_irq_chained_handler(irq, cpm2_cascade); | 95 | irq_set_chained_handler(irq, cpm2_cascade); |
96 | #endif | 96 | #endif |
97 | } | 97 | } |
98 | 98 | ||
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c index 79d85aca4767..db864623b4ae 100644 --- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c +++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c | |||
@@ -93,7 +93,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq) | |||
93 | 93 | ||
94 | void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) | 94 | void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) |
95 | { | 95 | { |
96 | struct irq_chip *chip = get_irq_desc_chip(desc); | 96 | struct irq_chip *chip = irq_desc_get_chip(desc); |
97 | unsigned int cascade_irq; | 97 | unsigned int cascade_irq; |
98 | 98 | ||
99 | /* | 99 | /* |
@@ -245,9 +245,9 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq, | |||
245 | irq_hw_number_t hwirq) | 245 | irq_hw_number_t hwirq) |
246 | { | 246 | { |
247 | /* All interrupts are LEVEL sensitive */ | 247 | /* All interrupts are LEVEL sensitive */ |
248 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 248 | irq_set_status_flags(virq, IRQ_LEVEL); |
249 | set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip, | 249 | irq_set_chip_and_handler(virq, &socrates_fpga_pic_chip, |
250 | handle_fasteoi_irq); | 250 | handle_fasteoi_irq); |
251 | 251 | ||
252 | return 0; | 252 | return 0; |
253 | } | 253 | } |
@@ -308,8 +308,8 @@ void socrates_fpga_pic_init(struct device_node *pic) | |||
308 | pr_warning("FPGA PIC: can't get irq%d.\n", i); | 308 | pr_warning("FPGA PIC: can't get irq%d.\n", i); |
309 | continue; | 309 | continue; |
310 | } | 310 | } |
311 | set_irq_chained_handler(socrates_fpga_irqs[i], | 311 | irq_set_chained_handler(socrates_fpga_irqs[i], |
312 | socrates_fpga_pic_cascade); | 312 | socrates_fpga_pic_cascade); |
313 | } | 313 | } |
314 | 314 | ||
315 | socrates_fpga_pic_iobase = of_iomap(pic, 0); | 315 | socrates_fpga_pic_iobase = of_iomap(pic, 0); |
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c index 2b62b064eac7..5387e9f06bdb 100644 --- a/arch/powerpc/platforms/85xx/stx_gp3.c +++ b/arch/powerpc/platforms/85xx/stx_gp3.c | |||
@@ -46,7 +46,7 @@ | |||
46 | 46 | ||
47 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 47 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
48 | { | 48 | { |
49 | struct irq_chip *chip = get_irq_desc_chip(desc); | 49 | struct irq_chip *chip = irq_desc_get_chip(desc); |
50 | int cascade_irq; | 50 | int cascade_irq; |
51 | 51 | ||
52 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 52 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -102,7 +102,7 @@ static void __init stx_gp3_pic_init(void) | |||
102 | 102 | ||
103 | cpm2_pic_init(np); | 103 | cpm2_pic_init(np); |
104 | of_node_put(np); | 104 | of_node_put(np); |
105 | set_irq_chained_handler(irq, cpm2_cascade); | 105 | irq_set_chained_handler(irq, cpm2_cascade); |
106 | #endif | 106 | #endif |
107 | } | 107 | } |
108 | 108 | ||
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c index 2265b68e3279..325de772725a 100644 --- a/arch/powerpc/platforms/85xx/tqm85xx.c +++ b/arch/powerpc/platforms/85xx/tqm85xx.c | |||
@@ -44,7 +44,7 @@ | |||
44 | 44 | ||
45 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 45 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
46 | { | 46 | { |
47 | struct irq_chip *chip = get_irq_desc_chip(desc); | 47 | struct irq_chip *chip = irq_desc_get_chip(desc); |
48 | int cascade_irq; | 48 | int cascade_irq; |
49 | 49 | ||
50 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 50 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
@@ -100,7 +100,7 @@ static void __init tqm85xx_pic_init(void) | |||
100 | 100 | ||
101 | cpm2_pic_init(np); | 101 | cpm2_pic_init(np); |
102 | of_node_put(np); | 102 | of_node_put(np); |
103 | set_irq_chained_handler(irq, cpm2_cascade); | 103 | irq_set_chained_handler(irq, cpm2_cascade); |
104 | #endif | 104 | #endif |
105 | } | 105 | } |
106 | 106 | ||
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c index 0adfe3b740cd..0beec7d5566b 100644 --- a/arch/powerpc/platforms/86xx/gef_pic.c +++ b/arch/powerpc/platforms/86xx/gef_pic.c | |||
@@ -95,7 +95,7 @@ static int gef_pic_cascade_irq; | |||
95 | 95 | ||
96 | void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) | 96 | void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) |
97 | { | 97 | { |
98 | struct irq_chip *chip = get_irq_desc_chip(desc); | 98 | struct irq_chip *chip = irq_desc_get_chip(desc); |
99 | unsigned int cascade_irq; | 99 | unsigned int cascade_irq; |
100 | 100 | ||
101 | /* | 101 | /* |
@@ -163,8 +163,8 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq, | |||
163 | irq_hw_number_t hwirq) | 163 | irq_hw_number_t hwirq) |
164 | { | 164 | { |
165 | /* All interrupts are LEVEL sensitive */ | 165 | /* All interrupts are LEVEL sensitive */ |
166 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 166 | irq_set_status_flags(virq, IRQ_LEVEL); |
167 | set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq); | 167 | irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq); |
168 | 168 | ||
169 | return 0; | 169 | return 0; |
170 | } | 170 | } |
@@ -225,7 +225,7 @@ void __init gef_pic_init(struct device_node *np) | |||
225 | return; | 225 | return; |
226 | 226 | ||
227 | /* Chain with parent controller */ | 227 | /* Chain with parent controller */ |
228 | set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade); | 228 | irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade); |
229 | } | 229 | } |
230 | 230 | ||
231 | /* | 231 | /* |
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c index cbe33639b478..8ef8960abda6 100644 --- a/arch/powerpc/platforms/86xx/pic.c +++ b/arch/powerpc/platforms/86xx/pic.c | |||
@@ -19,7 +19,7 @@ | |||
19 | #ifdef CONFIG_PPC_I8259 | 19 | #ifdef CONFIG_PPC_I8259 |
20 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) | 20 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
21 | { | 21 | { |
22 | struct irq_chip *chip = get_irq_desc_chip(desc); | 22 | struct irq_chip *chip = irq_desc_get_chip(desc); |
23 | unsigned int cascade_irq = i8259_irq(); | 23 | unsigned int cascade_irq = i8259_irq(); |
24 | 24 | ||
25 | if (cascade_irq != NO_IRQ) | 25 | if (cascade_irq != NO_IRQ) |
@@ -77,6 +77,6 @@ void __init mpc86xx_init_irq(void) | |||
77 | i8259_init(cascade_node, 0); | 77 | i8259_init(cascade_node, 0); |
78 | of_node_put(cascade_node); | 78 | of_node_put(cascade_node); |
79 | 79 | ||
80 | set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade); | 80 | irq_set_chained_handler(cascade_irq, mpc86xx_8259_cascade); |
81 | #endif | 81 | #endif |
82 | } | 82 | } |
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index fabb108e8744..9ecce995dd4b 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c | |||
@@ -226,11 +226,11 @@ static void cpm_cascade(unsigned int irq, struct irq_desc *desc) | |||
226 | 226 | ||
227 | generic_handle_irq(cascade_irq); | 227 | generic_handle_irq(cascade_irq); |
228 | 228 | ||
229 | chip = get_irq_desc_chip(cdesc); | 229 | chip = irq_desc_get_chip(cdesc); |
230 | chip->irq_eoi(&cdesc->irq_data); | 230 | chip->irq_eoi(&cdesc->irq_data); |
231 | } | 231 | } |
232 | 232 | ||
233 | chip = get_irq_desc_chip(desc); | 233 | chip = irq_desc_get_chip(desc); |
234 | chip->irq_eoi(&desc->irq_data); | 234 | chip->irq_eoi(&desc->irq_data); |
235 | } | 235 | } |
236 | 236 | ||
@@ -251,5 +251,5 @@ void __init mpc8xx_pics_init(void) | |||
251 | 251 | ||
252 | irq = cpm_pic_init(); | 252 | irq = cpm_pic_init(); |
253 | if (irq != NO_IRQ) | 253 | if (irq != NO_IRQ) |
254 | set_irq_chained_handler(irq, cpm_cascade); | 254 | irq_set_chained_handler(irq, cpm_cascade); |
255 | } | 255 | } |
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index c48b66a67e42..bb5ebf8fa80b 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c | |||
@@ -93,8 +93,8 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) | |||
93 | 93 | ||
94 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | 94 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) |
95 | { | 95 | { |
96 | struct irq_chip *chip = get_irq_desc_chip(desc); | 96 | struct irq_chip *chip = irq_desc_get_chip(desc); |
97 | struct axon_msic *msic = get_irq_data(irq); | 97 | struct axon_msic *msic = irq_get_handler_data(irq); |
98 | u32 write_offset, msi; | 98 | u32 write_offset, msi; |
99 | int idx; | 99 | int idx; |
100 | int retry = 0; | 100 | int retry = 0; |
@@ -287,7 +287,7 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) | |||
287 | } | 287 | } |
288 | dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); | 288 | dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq); |
289 | 289 | ||
290 | set_irq_msi(virq, entry); | 290 | irq_set_msi_desc(virq, entry); |
291 | msg.data = virq; | 291 | msg.data = virq; |
292 | write_msi_msg(virq, &msg); | 292 | write_msi_msg(virq, &msg); |
293 | } | 293 | } |
@@ -305,7 +305,7 @@ static void axon_msi_teardown_msi_irqs(struct pci_dev *dev) | |||
305 | if (entry->irq == NO_IRQ) | 305 | if (entry->irq == NO_IRQ) |
306 | continue; | 306 | continue; |
307 | 307 | ||
308 | set_irq_msi(entry->irq, NULL); | 308 | irq_set_msi_desc(entry->irq, NULL); |
309 | irq_dispose_mapping(entry->irq); | 309 | irq_dispose_mapping(entry->irq); |
310 | } | 310 | } |
311 | } | 311 | } |
@@ -320,7 +320,7 @@ static struct irq_chip msic_irq_chip = { | |||
320 | static int msic_host_map(struct irq_host *h, unsigned int virq, | 320 | static int msic_host_map(struct irq_host *h, unsigned int virq, |
321 | irq_hw_number_t hw) | 321 | irq_hw_number_t hw) |
322 | { | 322 | { |
323 | set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); | 323 | irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq); |
324 | 324 | ||
325 | return 0; | 325 | return 0; |
326 | } | 326 | } |
@@ -400,8 +400,8 @@ static int axon_msi_probe(struct platform_device *device) | |||
400 | 400 | ||
401 | msic->irq_host->host_data = msic; | 401 | msic->irq_host->host_data = msic; |
402 | 402 | ||
403 | set_irq_data(virq, msic); | 403 | irq_set_handler_data(virq, msic); |
404 | set_irq_chained_handler(virq, axon_msi_cascade); | 404 | irq_set_chained_handler(virq, axon_msi_cascade); |
405 | pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq); | 405 | pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq); |
406 | 406 | ||
407 | /* Enable the MSIC hardware */ | 407 | /* Enable the MSIC hardware */ |
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c index 0b8f7d7135c5..4cb9e147c307 100644 --- a/arch/powerpc/platforms/cell/beat_interrupt.c +++ b/arch/powerpc/platforms/cell/beat_interrupt.c | |||
@@ -136,15 +136,14 @@ static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq) | |||
136 | static int beatic_pic_host_map(struct irq_host *h, unsigned int virq, | 136 | static int beatic_pic_host_map(struct irq_host *h, unsigned int virq, |
137 | irq_hw_number_t hw) | 137 | irq_hw_number_t hw) |
138 | { | 138 | { |
139 | struct irq_desc *desc = irq_to_desc(virq); | ||
140 | int64_t err; | 139 | int64_t err; |
141 | 140 | ||
142 | err = beat_construct_and_connect_irq_plug(virq, hw); | 141 | err = beat_construct_and_connect_irq_plug(virq, hw); |
143 | if (err < 0) | 142 | if (err < 0) |
144 | return -EIO; | 143 | return -EIO; |
145 | 144 | ||
146 | desc->status |= IRQ_LEVEL; | 145 | irq_set_status_flags(virq, IRQ_LEVEL); |
147 | set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq); | 146 | irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq); |
148 | return 0; | 147 | return 0; |
149 | } | 148 | } |
150 | 149 | ||
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c index ec9fc7d82068..44cfd1bef89b 100644 --- a/arch/powerpc/platforms/cell/interrupt.c +++ b/arch/powerpc/platforms/cell/interrupt.c | |||
@@ -101,9 +101,9 @@ static void iic_ioexc_eoi(struct irq_data *d) | |||
101 | 101 | ||
102 | static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) | 102 | static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) |
103 | { | 103 | { |
104 | struct irq_chip *chip = get_irq_desc_chip(desc); | 104 | struct irq_chip *chip = irq_desc_get_chip(desc); |
105 | struct cbe_iic_regs __iomem *node_iic = | 105 | struct cbe_iic_regs __iomem *node_iic = |
106 | (void __iomem *)get_irq_desc_data(desc); | 106 | (void __iomem *)irq_desc_get_handler_data(desc); |
107 | unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; | 107 | unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; |
108 | unsigned long bits, ack; | 108 | unsigned long bits, ack; |
109 | int cascade; | 109 | int cascade; |
@@ -240,14 +240,14 @@ static int iic_host_map(struct irq_host *h, unsigned int virq, | |||
240 | { | 240 | { |
241 | switch (hw & IIC_IRQ_TYPE_MASK) { | 241 | switch (hw & IIC_IRQ_TYPE_MASK) { |
242 | case IIC_IRQ_TYPE_IPI: | 242 | case IIC_IRQ_TYPE_IPI: |
243 | set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq); | 243 | irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq); |
244 | break; | 244 | break; |
245 | case IIC_IRQ_TYPE_IOEXC: | 245 | case IIC_IRQ_TYPE_IOEXC: |
246 | set_irq_chip_and_handler(virq, &iic_ioexc_chip, | 246 | irq_set_chip_and_handler(virq, &iic_ioexc_chip, |
247 | handle_iic_irq); | 247 | handle_edge_eoi_irq); |
248 | break; | 248 | break; |
249 | default: | 249 | default: |
250 | set_irq_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq); | 250 | irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq); |
251 | } | 251 | } |
252 | return 0; | 252 | return 0; |
253 | } | 253 | } |
@@ -364,8 +364,8 @@ static int __init setup_iic(void) | |||
364 | * irq_data is a generic pointer that gets passed back | 364 | * irq_data is a generic pointer that gets passed back |
365 | * to us later, so the forced cast is fine. | 365 | * to us later, so the forced cast is fine. |
366 | */ | 366 | */ |
367 | set_irq_data(cascade, (void __force *)node_iic); | 367 | irq_set_handler_data(cascade, (void __force *)node_iic); |
368 | set_irq_chained_handler(cascade , iic_ioexc_cascade); | 368 | irq_set_chained_handler(cascade, iic_ioexc_cascade); |
369 | out_be64(&node_iic->iic_ir, | 369 | out_be64(&node_iic->iic_ir, |
370 | (1 << 12) /* priority */ | | 370 | (1 << 12) /* priority */ | |
371 | (node << 4) /* dest node */ | | 371 | (node << 4) /* dest node */ | |
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c index 6a28d027d959..fd57bfe00edf 100644 --- a/arch/powerpc/platforms/cell/setup.c +++ b/arch/powerpc/platforms/cell/setup.c | |||
@@ -187,8 +187,8 @@ machine_subsys_initcall(cell, cell_publish_devices); | |||
187 | 187 | ||
188 | static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) | 188 | static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) |
189 | { | 189 | { |
190 | struct irq_chip *chip = get_irq_desc_chip(desc); | 190 | struct irq_chip *chip = irq_desc_get_chip(desc); |
191 | struct mpic *mpic = get_irq_desc_data(desc); | 191 | struct mpic *mpic = irq_desc_get_handler_data(desc); |
192 | unsigned int virq; | 192 | unsigned int virq; |
193 | 193 | ||
194 | virq = mpic_get_one_irq(mpic); | 194 | virq = mpic_get_one_irq(mpic); |
@@ -223,8 +223,8 @@ static void __init mpic_init_IRQ(void) | |||
223 | 223 | ||
224 | printk(KERN_INFO "%s : hooking up to IRQ %d\n", | 224 | printk(KERN_INFO "%s : hooking up to IRQ %d\n", |
225 | dn->full_name, virq); | 225 | dn->full_name, virq); |
226 | set_irq_data(virq, mpic); | 226 | irq_set_handler_data(virq, mpic); |
227 | set_irq_chained_handler(virq, cell_mpic_cascade); | 227 | irq_set_chained_handler(virq, cell_mpic_cascade); |
228 | } | 228 | } |
229 | } | 229 | } |
230 | 230 | ||
diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c index b38cdfc1deb8..c5cf50e6b45a 100644 --- a/arch/powerpc/platforms/cell/spider-pic.c +++ b/arch/powerpc/platforms/cell/spider-pic.c | |||
@@ -102,7 +102,7 @@ static void spider_ack_irq(struct irq_data *d) | |||
102 | 102 | ||
103 | /* Reset edge detection logic if necessary | 103 | /* Reset edge detection logic if necessary |
104 | */ | 104 | */ |
105 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) | 105 | if (irqd_is_level_type(d)) |
106 | return; | 106 | return; |
107 | 107 | ||
108 | /* Only interrupts 47 to 50 can be set to edge */ | 108 | /* Only interrupts 47 to 50 can be set to edge */ |
@@ -119,7 +119,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type) | |||
119 | struct spider_pic *pic = spider_virq_to_pic(d->irq); | 119 | struct spider_pic *pic = spider_virq_to_pic(d->irq); |
120 | unsigned int hw = irq_map[d->irq].hwirq; | 120 | unsigned int hw = irq_map[d->irq].hwirq; |
121 | void __iomem *cfg = spider_get_irq_config(pic, hw); | 121 | void __iomem *cfg = spider_get_irq_config(pic, hw); |
122 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
123 | u32 old_mask; | 122 | u32 old_mask; |
124 | u32 ic; | 123 | u32 ic; |
125 | 124 | ||
@@ -147,12 +146,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type) | |||
147 | return -EINVAL; | 146 | return -EINVAL; |
148 | } | 147 | } |
149 | 148 | ||
150 | /* Update irq_desc */ | ||
151 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
152 | desc->status |= type & IRQ_TYPE_SENSE_MASK; | ||
153 | if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
154 | desc->status |= IRQ_LEVEL; | ||
155 | |||
156 | /* Configure the source. One gross hack that was there before and | 149 | /* Configure the source. One gross hack that was there before and |
157 | * that I've kept around is the priority to the BE which I set to | 150 | * that I've kept around is the priority to the BE which I set to |
158 | * be the same as the interrupt source number. I don't know wether | 151 | * be the same as the interrupt source number. I don't know wether |
@@ -178,10 +171,10 @@ static struct irq_chip spider_pic = { | |||
178 | static int spider_host_map(struct irq_host *h, unsigned int virq, | 171 | static int spider_host_map(struct irq_host *h, unsigned int virq, |
179 | irq_hw_number_t hw) | 172 | irq_hw_number_t hw) |
180 | { | 173 | { |
181 | set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq); | 174 | irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq); |
182 | 175 | ||
183 | /* Set default irq type */ | 176 | /* Set default irq type */ |
184 | set_irq_type(virq, IRQ_TYPE_NONE); | 177 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
185 | 178 | ||
186 | return 0; | 179 | return 0; |
187 | } | 180 | } |
@@ -207,8 +200,8 @@ static struct irq_host_ops spider_host_ops = { | |||
207 | 200 | ||
208 | static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) | 201 | static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) |
209 | { | 202 | { |
210 | struct irq_chip *chip = get_irq_desc_chip(desc); | 203 | struct irq_chip *chip = irq_desc_get_chip(desc); |
211 | struct spider_pic *pic = get_irq_desc_data(desc); | 204 | struct spider_pic *pic = irq_desc_get_handler_data(desc); |
212 | unsigned int cs, virq; | 205 | unsigned int cs, virq; |
213 | 206 | ||
214 | cs = in_be32(pic->regs + TIR_CS) >> 24; | 207 | cs = in_be32(pic->regs + TIR_CS) >> 24; |
@@ -328,8 +321,8 @@ static void __init spider_init_one(struct device_node *of_node, int chip, | |||
328 | virq = spider_find_cascade_and_node(pic); | 321 | virq = spider_find_cascade_and_node(pic); |
329 | if (virq == NO_IRQ) | 322 | if (virq == NO_IRQ) |
330 | return; | 323 | return; |
331 | set_irq_data(virq, pic); | 324 | irq_set_handler_data(virq, pic); |
332 | set_irq_chained_handler(virq, spider_irq_cascade); | 325 | irq_set_chained_handler(virq, spider_irq_cascade); |
333 | 326 | ||
334 | printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", | 327 | printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n", |
335 | pic->node_id, addr, of_node->full_name); | 328 | pic->node_id, addr, of_node->full_name); |
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c index 4c1288451a21..122786498419 100644 --- a/arch/powerpc/platforms/chrp/setup.c +++ b/arch/powerpc/platforms/chrp/setup.c | |||
@@ -365,7 +365,7 @@ void __init chrp_setup_arch(void) | |||
365 | 365 | ||
366 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) | 366 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) |
367 | { | 367 | { |
368 | struct irq_chip *chip = get_irq_desc_chip(desc); | 368 | struct irq_chip *chip = irq_desc_get_chip(desc); |
369 | unsigned int cascade_irq = i8259_irq(); | 369 | unsigned int cascade_irq = i8259_irq(); |
370 | 370 | ||
371 | if (cascade_irq != NO_IRQ) | 371 | if (cascade_irq != NO_IRQ) |
@@ -517,7 +517,7 @@ static void __init chrp_find_8259(void) | |||
517 | if (cascade_irq == NO_IRQ) | 517 | if (cascade_irq == NO_IRQ) |
518 | printk(KERN_ERR "i8259: failed to map cascade irq\n"); | 518 | printk(KERN_ERR "i8259: failed to map cascade irq\n"); |
519 | else | 519 | else |
520 | set_irq_chained_handler(cascade_irq, | 520 | irq_set_chained_handler(cascade_irq, |
521 | chrp_8259_cascade); | 521 | chrp_8259_cascade); |
522 | } | 522 | } |
523 | } | 523 | } |
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c index 0aca0e28a8e5..12aa62b6f227 100644 --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c | |||
@@ -101,16 +101,16 @@ static struct irq_host *flipper_irq_host; | |||
101 | static int flipper_pic_map(struct irq_host *h, unsigned int virq, | 101 | static int flipper_pic_map(struct irq_host *h, unsigned int virq, |
102 | irq_hw_number_t hwirq) | 102 | irq_hw_number_t hwirq) |
103 | { | 103 | { |
104 | set_irq_chip_data(virq, h->host_data); | 104 | irq_set_chip_data(virq, h->host_data); |
105 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 105 | irq_set_status_flags(virq, IRQ_LEVEL); |
106 | set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq); | 106 | irq_set_chip_and_handler(virq, &flipper_pic, handle_level_irq); |
107 | return 0; | 107 | return 0; |
108 | } | 108 | } |
109 | 109 | ||
110 | static void flipper_pic_unmap(struct irq_host *h, unsigned int irq) | 110 | static void flipper_pic_unmap(struct irq_host *h, unsigned int irq) |
111 | { | 111 | { |
112 | set_irq_chip_data(irq, NULL); | 112 | irq_set_chip_data(irq, NULL); |
113 | set_irq_chip(irq, NULL); | 113 | irq_set_chip(irq, NULL); |
114 | } | 114 | } |
115 | 115 | ||
116 | static int flipper_pic_match(struct irq_host *h, struct device_node *np) | 116 | static int flipper_pic_match(struct irq_host *h, struct device_node *np) |
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c index 35e448bd8479..2bdddfc9d520 100644 --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c | |||
@@ -94,16 +94,16 @@ static struct irq_host *hlwd_irq_host; | |||
94 | static int hlwd_pic_map(struct irq_host *h, unsigned int virq, | 94 | static int hlwd_pic_map(struct irq_host *h, unsigned int virq, |
95 | irq_hw_number_t hwirq) | 95 | irq_hw_number_t hwirq) |
96 | { | 96 | { |
97 | set_irq_chip_data(virq, h->host_data); | 97 | irq_set_chip_data(virq, h->host_data); |
98 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 98 | irq_set_status_flags(virq, IRQ_LEVEL); |
99 | set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq); | 99 | irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq); |
100 | return 0; | 100 | return 0; |
101 | } | 101 | } |
102 | 102 | ||
103 | static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq) | 103 | static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq) |
104 | { | 104 | { |
105 | set_irq_chip_data(irq, NULL); | 105 | irq_set_chip_data(irq, NULL); |
106 | set_irq_chip(irq, NULL); | 106 | irq_set_chip(irq, NULL); |
107 | } | 107 | } |
108 | 108 | ||
109 | static struct irq_host_ops hlwd_irq_host_ops = { | 109 | static struct irq_host_ops hlwd_irq_host_ops = { |
@@ -129,8 +129,8 @@ static unsigned int __hlwd_pic_get_irq(struct irq_host *h) | |||
129 | static void hlwd_pic_irq_cascade(unsigned int cascade_virq, | 129 | static void hlwd_pic_irq_cascade(unsigned int cascade_virq, |
130 | struct irq_desc *desc) | 130 | struct irq_desc *desc) |
131 | { | 131 | { |
132 | struct irq_chip *chip = get_irq_desc_chip(desc); | 132 | struct irq_chip *chip = irq_desc_get_chip(desc); |
133 | struct irq_host *irq_host = get_irq_data(cascade_virq); | 133 | struct irq_host *irq_host = irq_get_handler_data(cascade_virq); |
134 | unsigned int virq; | 134 | unsigned int virq; |
135 | 135 | ||
136 | raw_spin_lock(&desc->lock); | 136 | raw_spin_lock(&desc->lock); |
@@ -145,7 +145,7 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq, | |||
145 | 145 | ||
146 | raw_spin_lock(&desc->lock); | 146 | raw_spin_lock(&desc->lock); |
147 | chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ | 147 | chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ |
148 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) | 148 | if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask) |
149 | chip->irq_unmask(&desc->irq_data); | 149 | chip->irq_unmask(&desc->irq_data); |
150 | raw_spin_unlock(&desc->lock); | 150 | raw_spin_unlock(&desc->lock); |
151 | } | 151 | } |
@@ -218,8 +218,8 @@ void hlwd_pic_probe(void) | |||
218 | host = hlwd_pic_init(np); | 218 | host = hlwd_pic_init(np); |
219 | BUG_ON(!host); | 219 | BUG_ON(!host); |
220 | cascade_virq = irq_of_parse_and_map(np, 0); | 220 | cascade_virq = irq_of_parse_and_map(np, 0); |
221 | set_irq_data(cascade_virq, host); | 221 | irq_set_handler_data(cascade_virq, host); |
222 | set_irq_chained_handler(cascade_virq, | 222 | irq_set_chained_handler(cascade_virq, |
223 | hlwd_pic_irq_cascade); | 223 | hlwd_pic_irq_cascade); |
224 | hlwd_irq_host = host; | 224 | hlwd_irq_host = host; |
225 | break; | 225 | break; |
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c index b21fde589ca7..487bda0d18d8 100644 --- a/arch/powerpc/platforms/embedded6xx/holly.c +++ b/arch/powerpc/platforms/embedded6xx/holly.c | |||
@@ -198,8 +198,8 @@ static void __init holly_init_IRQ(void) | |||
198 | cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); | 198 | cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); |
199 | pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); | 199 | pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); |
200 | tsi108_pci_int_init(cascade_node); | 200 | tsi108_pci_int_init(cascade_node); |
201 | set_irq_data(cascade_pci_irq, mpic); | 201 | irq_set_handler_data(cascade_pci_irq, mpic); |
202 | set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade); | 202 | irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); |
203 | #endif | 203 | #endif |
204 | /* Configure MPIC outputs to CPU0 */ | 204 | /* Configure MPIC outputs to CPU0 */ |
205 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); | 205 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); |
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c index 7a2ba39d7811..1cb907c94359 100644 --- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c +++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | |||
@@ -153,8 +153,8 @@ static void __init mpc7448_hpc2_init_IRQ(void) | |||
153 | DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, | 153 | DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, |
154 | (u32) cascade_pci_irq); | 154 | (u32) cascade_pci_irq); |
155 | tsi108_pci_int_init(cascade_node); | 155 | tsi108_pci_int_init(cascade_node); |
156 | set_irq_data(cascade_pci_irq, mpic); | 156 | irq_set_handler_data(cascade_pci_irq, mpic); |
157 | set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade); | 157 | irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); |
158 | #endif | 158 | #endif |
159 | /* Configure MPIC outputs to CPU0 */ | 159 | /* Configure MPIC outputs to CPU0 */ |
160 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); | 160 | tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); |
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c index 4fb96f0b2df6..52a6889832c7 100644 --- a/arch/powerpc/platforms/iseries/irq.c +++ b/arch/powerpc/platforms/iseries/irq.c | |||
@@ -220,7 +220,7 @@ void __init iSeries_activate_IRQs() | |||
220 | if (!desc) | 220 | if (!desc) |
221 | continue; | 221 | continue; |
222 | 222 | ||
223 | chip = get_irq_desc_chip(desc); | 223 | chip = irq_desc_get_chip(desc); |
224 | if (chip && chip->irq_startup) { | 224 | if (chip && chip->irq_startup) { |
225 | raw_spin_lock_irqsave(&desc->lock, flags); | 225 | raw_spin_lock_irqsave(&desc->lock, flags); |
226 | chip->irq_startup(&desc->irq_data); | 226 | chip->irq_startup(&desc->irq_data); |
@@ -346,7 +346,7 @@ unsigned int iSeries_get_irq(void) | |||
346 | static int iseries_irq_host_map(struct irq_host *h, unsigned int virq, | 346 | static int iseries_irq_host_map(struct irq_host *h, unsigned int virq, |
347 | irq_hw_number_t hw) | 347 | irq_hw_number_t hw) |
348 | { | 348 | { |
349 | set_irq_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq); | 349 | irq_set_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq); |
350 | 350 | ||
351 | return 0; | 351 | return 0; |
352 | } | 352 | } |
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c index 04296ffff8bf..dd2e48b28508 100644 --- a/arch/powerpc/platforms/maple/pci.c +++ b/arch/powerpc/platforms/maple/pci.c | |||
@@ -498,7 +498,7 @@ void __devinit maple_pci_irq_fixup(struct pci_dev *dev) | |||
498 | printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); | 498 | printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); |
499 | dev->irq = irq_create_mapping(NULL, 1); | 499 | dev->irq = irq_create_mapping(NULL, 1); |
500 | if (dev->irq != NO_IRQ) | 500 | if (dev->irq != NO_IRQ) |
501 | set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); | 501 | irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); |
502 | } | 502 | } |
503 | 503 | ||
504 | /* Hide AMD8111 IDE interrupt when in legacy mode so | 504 | /* Hide AMD8111 IDE interrupt when in legacy mode so |
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index a6067b38d2ca..7c858e6f843c 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c | |||
@@ -239,7 +239,7 @@ static __init void pas_init_IRQ(void) | |||
239 | if (nmiprop) { | 239 | if (nmiprop) { |
240 | nmi_virq = irq_create_mapping(NULL, *nmiprop); | 240 | nmi_virq = irq_create_mapping(NULL, *nmiprop); |
241 | mpic_irq_set_priority(nmi_virq, 15); | 241 | mpic_irq_set_priority(nmi_virq, 15); |
242 | set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); | 242 | irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); |
243 | mpic_unmask_irq(irq_get_irq_data(nmi_virq)); | 243 | mpic_unmask_irq(irq_get_irq_data(nmi_virq)); |
244 | } | 244 | } |
245 | 245 | ||
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c index 3bc075c788ef..ab6898942700 100644 --- a/arch/powerpc/platforms/powermac/pci.c +++ b/arch/powerpc/platforms/powermac/pci.c | |||
@@ -988,7 +988,7 @@ void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) | |||
988 | dev->vendor == PCI_VENDOR_ID_DEC && | 988 | dev->vendor == PCI_VENDOR_ID_DEC && |
989 | dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { | 989 | dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { |
990 | dev->irq = irq_create_mapping(NULL, 60); | 990 | dev->irq = irq_create_mapping(NULL, 60); |
991 | set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); | 991 | irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); |
992 | } | 992 | } |
993 | #endif /* CONFIG_PPC32 */ | 993 | #endif /* CONFIG_PPC32 */ |
994 | } | 994 | } |
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index c55812bb6a51..023f24086a0a 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c | |||
@@ -157,7 +157,7 @@ static unsigned int pmac_startup_irq(struct irq_data *d) | |||
157 | int i = src >> 5; | 157 | int i = src >> 5; |
158 | 158 | ||
159 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); | 159 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
160 | if ((irq_to_desc(d->irq)->status & IRQ_LEVEL) == 0) | 160 | if (!irqd_is_level_type(d)) |
161 | out_le32(&pmac_irq_hw[i]->ack, bit); | 161 | out_le32(&pmac_irq_hw[i]->ack, bit); |
162 | __set_bit(src, ppc_cached_irq_mask); | 162 | __set_bit(src, ppc_cached_irq_mask); |
163 | __pmac_set_irq_mask(src, 0); | 163 | __pmac_set_irq_mask(src, 0); |
@@ -289,7 +289,6 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) | |||
289 | static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, | 289 | static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, |
290 | irq_hw_number_t hw) | 290 | irq_hw_number_t hw) |
291 | { | 291 | { |
292 | struct irq_desc *desc = irq_to_desc(virq); | ||
293 | int level; | 292 | int level; |
294 | 293 | ||
295 | if (hw >= max_irqs) | 294 | if (hw >= max_irqs) |
@@ -300,9 +299,9 @@ static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, | |||
300 | */ | 299 | */ |
301 | level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); | 300 | level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); |
302 | if (level) | 301 | if (level) |
303 | desc->status |= IRQ_LEVEL; | 302 | irq_set_status_flags(virq, IRQ_LEVEL); |
304 | set_irq_chip_and_handler(virq, &pmac_pic, level ? | 303 | irq_set_chip_and_handler(virq, &pmac_pic, |
305 | handle_level_irq : handle_edge_irq); | 304 | level ? handle_level_irq : handle_edge_irq); |
306 | return 0; | 305 | return 0; |
307 | } | 306 | } |
308 | 307 | ||
@@ -472,8 +471,8 @@ int of_irq_map_oldworld(struct device_node *device, int index, | |||
472 | 471 | ||
473 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) | 472 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) |
474 | { | 473 | { |
475 | struct irq_chip *chip = get_irq_desc_chip(desc); | 474 | struct irq_chip *chip = irq_desc_get_chip(desc); |
476 | struct mpic *mpic = get_irq_desc_data(desc); | 475 | struct mpic *mpic = irq_desc_get_handler_data(desc); |
477 | unsigned int cascade_irq = mpic_get_one_irq(mpic); | 476 | unsigned int cascade_irq = mpic_get_one_irq(mpic); |
478 | 477 | ||
479 | if (cascade_irq != NO_IRQ) | 478 | if (cascade_irq != NO_IRQ) |
@@ -591,8 +590,8 @@ static int __init pmac_pic_probe_mpic(void) | |||
591 | of_node_put(slave); | 590 | of_node_put(slave); |
592 | return 0; | 591 | return 0; |
593 | } | 592 | } |
594 | set_irq_data(cascade, mpic2); | 593 | irq_set_handler_data(cascade, mpic2); |
595 | set_irq_chained_handler(cascade, pmac_u3_cascade); | 594 | irq_set_chained_handler(cascade, pmac_u3_cascade); |
596 | 595 | ||
597 | of_node_put(slave); | 596 | of_node_put(slave); |
598 | return 0; | 597 | return 0; |
diff --git a/arch/powerpc/platforms/powermac/pmac.h b/arch/powerpc/platforms/powermac/pmac.h index f0bc08f6c1f0..20468f49aec0 100644 --- a/arch/powerpc/platforms/powermac/pmac.h +++ b/arch/powerpc/platforms/powermac/pmac.h | |||
@@ -33,7 +33,6 @@ extern void pmac_setup_pci_dma(void); | |||
33 | extern void pmac_check_ht_link(void); | 33 | extern void pmac_check_ht_link(void); |
34 | 34 | ||
35 | extern void pmac_setup_smp(void); | 35 | extern void pmac_setup_smp(void); |
36 | extern void pmac32_cpu_die(void); | ||
37 | extern void low_cpu_die(void) __attribute__((noreturn)); | 36 | extern void low_cpu_die(void) __attribute__((noreturn)); |
38 | 37 | ||
39 | extern int pmac_nvram_init(void); | 38 | extern int pmac_nvram_init(void); |
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c index d5aceb7fb125..aa45281bd296 100644 --- a/arch/powerpc/platforms/powermac/setup.c +++ b/arch/powerpc/platforms/powermac/setup.c | |||
@@ -650,51 +650,6 @@ static int pmac_pci_probe_mode(struct pci_bus *bus) | |||
650 | return PCI_PROBE_NORMAL; | 650 | return PCI_PROBE_NORMAL; |
651 | return PCI_PROBE_DEVTREE; | 651 | return PCI_PROBE_DEVTREE; |
652 | } | 652 | } |
653 | |||
654 | #ifdef CONFIG_HOTPLUG_CPU | ||
655 | /* access per cpu vars from generic smp.c */ | ||
656 | DECLARE_PER_CPU(int, cpu_state); | ||
657 | |||
658 | static void pmac64_cpu_die(void) | ||
659 | { | ||
660 | /* | ||
661 | * turn off as much as possible, we'll be | ||
662 | * kicked out as this will only be invoked | ||
663 | * on core99 platforms for now ... | ||
664 | */ | ||
665 | |||
666 | printk(KERN_INFO "CPU#%d offline\n", smp_processor_id()); | ||
667 | __get_cpu_var(cpu_state) = CPU_DEAD; | ||
668 | smp_wmb(); | ||
669 | |||
670 | /* | ||
671 | * during the path that leads here preemption is disabled, | ||
672 | * reenable it now so that when coming up preempt count is | ||
673 | * zero correctly | ||
674 | */ | ||
675 | preempt_enable(); | ||
676 | |||
677 | /* | ||
678 | * hard-disable interrupts for the non-NAP case, the NAP code | ||
679 | * needs to re-enable interrupts (but soft-disables them) | ||
680 | */ | ||
681 | hard_irq_disable(); | ||
682 | |||
683 | while (1) { | ||
684 | /* let's not take timer interrupts too often ... */ | ||
685 | set_dec(0x7fffffff); | ||
686 | |||
687 | /* should always be true at this point */ | ||
688 | if (cpu_has_feature(CPU_FTR_CAN_NAP)) | ||
689 | power4_cpu_offline_powersave(); | ||
690 | else { | ||
691 | HMT_low(); | ||
692 | HMT_very_low(); | ||
693 | } | ||
694 | } | ||
695 | } | ||
696 | #endif /* CONFIG_HOTPLUG_CPU */ | ||
697 | |||
698 | #endif /* CONFIG_PPC64 */ | 653 | #endif /* CONFIG_PPC64 */ |
699 | 654 | ||
700 | define_machine(powermac) { | 655 | define_machine(powermac) { |
@@ -726,15 +681,4 @@ define_machine(powermac) { | |||
726 | .pcibios_after_init = pmac_pcibios_after_init, | 681 | .pcibios_after_init = pmac_pcibios_after_init, |
727 | .phys_mem_access_prot = pci_phys_mem_access_prot, | 682 | .phys_mem_access_prot = pci_phys_mem_access_prot, |
728 | #endif | 683 | #endif |
729 | #ifdef CONFIG_HOTPLUG_CPU | ||
730 | #ifdef CONFIG_PPC64 | ||
731 | .cpu_die = pmac64_cpu_die, | ||
732 | #endif | ||
733 | #ifdef CONFIG_PPC32 | ||
734 | .cpu_die = pmac32_cpu_die, | ||
735 | #endif | ||
736 | #endif | ||
737 | #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) | ||
738 | .cpu_die = generic_mach_cpu_die, | ||
739 | #endif | ||
740 | }; | 684 | }; |
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c index c95215f4f8b6..a830c5e80657 100644 --- a/arch/powerpc/platforms/powermac/smp.c +++ b/arch/powerpc/platforms/powermac/smp.c | |||
@@ -840,92 +840,149 @@ static void __devinit smp_core99_setup_cpu(int cpu_nr) | |||
840 | 840 | ||
841 | /* Setup openpic */ | 841 | /* Setup openpic */ |
842 | mpic_setup_this_cpu(); | 842 | mpic_setup_this_cpu(); |
843 | } | ||
843 | 844 | ||
844 | if (cpu_nr == 0) { | 845 | #ifdef CONFIG_HOTPLUG_CPU |
845 | #ifdef CONFIG_PPC64 | 846 | static int smp_core99_cpu_notify(struct notifier_block *self, |
846 | extern void g5_phy_disable_cpu1(void); | 847 | unsigned long action, void *hcpu) |
848 | { | ||
849 | int rc; | ||
847 | 850 | ||
848 | /* Close i2c bus if it was used for tb sync */ | 851 | switch(action) { |
852 | case CPU_UP_PREPARE: | ||
853 | case CPU_UP_PREPARE_FROZEN: | ||
854 | /* Open i2c bus if it was used for tb sync */ | ||
849 | if (pmac_tb_clock_chip_host) { | 855 | if (pmac_tb_clock_chip_host) { |
850 | pmac_i2c_close(pmac_tb_clock_chip_host); | 856 | rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1); |
851 | pmac_tb_clock_chip_host = NULL; | 857 | if (rc) { |
858 | pr_err("Failed to open i2c bus for time sync\n"); | ||
859 | return notifier_from_errno(rc); | ||
860 | } | ||
852 | } | 861 | } |
862 | break; | ||
863 | case CPU_ONLINE: | ||
864 | case CPU_UP_CANCELED: | ||
865 | /* Close i2c bus if it was used for tb sync */ | ||
866 | if (pmac_tb_clock_chip_host) | ||
867 | pmac_i2c_close(pmac_tb_clock_chip_host); | ||
868 | break; | ||
869 | default: | ||
870 | break; | ||
871 | } | ||
872 | return NOTIFY_OK; | ||
873 | } | ||
853 | 874 | ||
854 | /* If we didn't start the second CPU, we must take | 875 | static struct notifier_block __cpuinitdata smp_core99_cpu_nb = { |
855 | * it off the bus | 876 | .notifier_call = smp_core99_cpu_notify, |
856 | */ | 877 | }; |
857 | if (of_machine_is_compatible("MacRISC4") && | 878 | #endif /* CONFIG_HOTPLUG_CPU */ |
858 | num_online_cpus() < 2) | 879 | |
859 | g5_phy_disable_cpu1(); | 880 | static void __init smp_core99_bringup_done(void) |
860 | #endif /* CONFIG_PPC64 */ | 881 | { |
882 | #ifdef CONFIG_PPC64 | ||
883 | extern void g5_phy_disable_cpu1(void); | ||
884 | |||
885 | /* Close i2c bus if it was used for tb sync */ | ||
886 | if (pmac_tb_clock_chip_host) | ||
887 | pmac_i2c_close(pmac_tb_clock_chip_host); | ||
861 | 888 | ||
862 | if (ppc_md.progress) | 889 | /* If we didn't start the second CPU, we must take |
863 | ppc_md.progress("core99_setup_cpu 0 done", 0x349); | 890 | * it off the bus. |
891 | */ | ||
892 | if (of_machine_is_compatible("MacRISC4") && | ||
893 | num_online_cpus() < 2) { | ||
894 | set_cpu_present(1, false); | ||
895 | g5_phy_disable_cpu1(); | ||
864 | } | 896 | } |
865 | } | 897 | #endif /* CONFIG_PPC64 */ |
866 | 898 | ||
899 | #ifdef CONFIG_HOTPLUG_CPU | ||
900 | register_cpu_notifier(&smp_core99_cpu_nb); | ||
901 | #endif | ||
902 | if (ppc_md.progress) | ||
903 | ppc_md.progress("smp_core99_bringup_done", 0x349); | ||
904 | } | ||
867 | 905 | ||
868 | #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) | 906 | #ifdef CONFIG_HOTPLUG_CPU |
869 | 907 | ||
870 | int smp_core99_cpu_disable(void) | 908 | static int smp_core99_cpu_disable(void) |
871 | { | 909 | { |
872 | set_cpu_online(smp_processor_id(), false); | 910 | int rc = generic_cpu_disable(); |
911 | if (rc) | ||
912 | return rc; | ||
873 | 913 | ||
874 | /* XXX reset cpu affinity here */ | ||
875 | mpic_cpu_set_priority(0xf); | 914 | mpic_cpu_set_priority(0xf); |
876 | asm volatile("mtdec %0" : : "r" (0x7fffffff)); | 915 | |
877 | mb(); | ||
878 | udelay(20); | ||
879 | asm volatile("mtdec %0" : : "r" (0x7fffffff)); | ||
880 | return 0; | 916 | return 0; |
881 | } | 917 | } |
882 | 918 | ||
883 | static int cpu_dead[NR_CPUS]; | 919 | #ifdef CONFIG_PPC32 |
884 | 920 | ||
885 | void pmac32_cpu_die(void) | 921 | static void pmac_cpu_die(void) |
886 | { | 922 | { |
923 | int cpu = smp_processor_id(); | ||
924 | |||
887 | local_irq_disable(); | 925 | local_irq_disable(); |
888 | cpu_dead[smp_processor_id()] = 1; | 926 | idle_task_exit(); |
927 | pr_debug("CPU%d offline\n", cpu); | ||
928 | generic_set_cpu_dead(cpu); | ||
929 | smp_wmb(); | ||
889 | mb(); | 930 | mb(); |
890 | low_cpu_die(); | 931 | low_cpu_die(); |
891 | } | 932 | } |
892 | 933 | ||
893 | void smp_core99_cpu_die(unsigned int cpu) | 934 | #else /* CONFIG_PPC32 */ |
935 | |||
936 | static void pmac_cpu_die(void) | ||
894 | { | 937 | { |
895 | int timeout; | 938 | int cpu = smp_processor_id(); |
896 | 939 | ||
897 | timeout = 1000; | 940 | local_irq_disable(); |
898 | while (!cpu_dead[cpu]) { | 941 | idle_task_exit(); |
899 | if (--timeout == 0) { | 942 | |
900 | printk("CPU %u refused to die!\n", cpu); | 943 | /* |
901 | break; | 944 | * turn off as much as possible, we'll be |
902 | } | 945 | * kicked out as this will only be invoked |
903 | msleep(1); | 946 | * on core99 platforms for now ... |
947 | */ | ||
948 | |||
949 | printk(KERN_INFO "CPU#%d offline\n", cpu); | ||
950 | generic_set_cpu_dead(cpu); | ||
951 | smp_wmb(); | ||
952 | |||
953 | /* | ||
954 | * Re-enable interrupts. The NAP code needs to enable them | ||
955 | * anyways, do it now so we deal with the case where one already | ||
956 | * happened while soft-disabled. | ||
957 | * We shouldn't get any external interrupts, only decrementer, and the | ||
958 | * decrementer handler is safe for use on offline CPUs | ||
959 | */ | ||
960 | local_irq_enable(); | ||
961 | |||
962 | while (1) { | ||
963 | /* let's not take timer interrupts too often ... */ | ||
964 | set_dec(0x7fffffff); | ||
965 | |||
966 | /* Enter NAP mode */ | ||
967 | power4_idle(); | ||
904 | } | 968 | } |
905 | cpu_dead[cpu] = 0; | ||
906 | } | 969 | } |
907 | 970 | ||
908 | #endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */ | 971 | #endif /* else CONFIG_PPC32 */ |
972 | #endif /* CONFIG_HOTPLUG_CPU */ | ||
909 | 973 | ||
910 | /* Core99 Macs (dual G4s and G5s) */ | 974 | /* Core99 Macs (dual G4s and G5s) */ |
911 | struct smp_ops_t core99_smp_ops = { | 975 | struct smp_ops_t core99_smp_ops = { |
912 | .message_pass = smp_mpic_message_pass, | 976 | .message_pass = smp_mpic_message_pass, |
913 | .probe = smp_core99_probe, | 977 | .probe = smp_core99_probe, |
978 | .bringup_done = smp_core99_bringup_done, | ||
914 | .kick_cpu = smp_core99_kick_cpu, | 979 | .kick_cpu = smp_core99_kick_cpu, |
915 | .setup_cpu = smp_core99_setup_cpu, | 980 | .setup_cpu = smp_core99_setup_cpu, |
916 | .give_timebase = smp_core99_give_timebase, | 981 | .give_timebase = smp_core99_give_timebase, |
917 | .take_timebase = smp_core99_take_timebase, | 982 | .take_timebase = smp_core99_take_timebase, |
918 | #if defined(CONFIG_HOTPLUG_CPU) | 983 | #if defined(CONFIG_HOTPLUG_CPU) |
919 | # if defined(CONFIG_PPC32) | ||
920 | .cpu_disable = smp_core99_cpu_disable, | 984 | .cpu_disable = smp_core99_cpu_disable, |
921 | .cpu_die = smp_core99_cpu_die, | ||
922 | # endif | ||
923 | # if defined(CONFIG_PPC64) | ||
924 | .cpu_disable = generic_cpu_disable, | ||
925 | .cpu_die = generic_cpu_die, | 985 | .cpu_die = generic_cpu_die, |
926 | /* intentionally do *NOT* assign cpu_enable, | ||
927 | * the generic code will use kick_cpu then! */ | ||
928 | # endif | ||
929 | #endif | 986 | #endif |
930 | }; | 987 | }; |
931 | 988 | ||
@@ -957,5 +1014,10 @@ void __init pmac_setup_smp(void) | |||
957 | smp_ops = &psurge_smp_ops; | 1014 | smp_ops = &psurge_smp_ops; |
958 | } | 1015 | } |
959 | #endif /* CONFIG_PPC32 */ | 1016 | #endif /* CONFIG_PPC32 */ |
1017 | |||
1018 | #ifdef CONFIG_HOTPLUG_CPU | ||
1019 | ppc_md.cpu_die = pmac_cpu_die; | ||
1020 | #endif | ||
960 | } | 1021 | } |
961 | 1022 | ||
1023 | |||
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c index 3988c86682a5..f2f6413b81d3 100644 --- a/arch/powerpc/platforms/ps3/interrupt.c +++ b/arch/powerpc/platforms/ps3/interrupt.c | |||
@@ -194,7 +194,7 @@ static int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet, | |||
194 | pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__, | 194 | pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__, |
195 | outlet, cpu, *virq); | 195 | outlet, cpu, *virq); |
196 | 196 | ||
197 | result = set_irq_chip_data(*virq, pd); | 197 | result = irq_set_chip_data(*virq, pd); |
198 | 198 | ||
199 | if (result) { | 199 | if (result) { |
200 | pr_debug("%s:%d: set_irq_chip_data failed\n", | 200 | pr_debug("%s:%d: set_irq_chip_data failed\n", |
@@ -221,12 +221,12 @@ fail_create: | |||
221 | 221 | ||
222 | static int ps3_virq_destroy(unsigned int virq) | 222 | static int ps3_virq_destroy(unsigned int virq) |
223 | { | 223 | { |
224 | const struct ps3_private *pd = get_irq_chip_data(virq); | 224 | const struct ps3_private *pd = irq_get_chip_data(virq); |
225 | 225 | ||
226 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, | 226 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, |
227 | __LINE__, pd->ppe_id, pd->thread_id, virq); | 227 | __LINE__, pd->ppe_id, pd->thread_id, virq); |
228 | 228 | ||
229 | set_irq_chip_data(virq, NULL); | 229 | irq_set_chip_data(virq, NULL); |
230 | irq_dispose_mapping(virq); | 230 | irq_dispose_mapping(virq); |
231 | 231 | ||
232 | pr_debug("%s:%d <-\n", __func__, __LINE__); | 232 | pr_debug("%s:%d <-\n", __func__, __LINE__); |
@@ -256,7 +256,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet, | |||
256 | goto fail_setup; | 256 | goto fail_setup; |
257 | } | 257 | } |
258 | 258 | ||
259 | pd = get_irq_chip_data(*virq); | 259 | pd = irq_get_chip_data(*virq); |
260 | 260 | ||
261 | /* Binds outlet to cpu + virq. */ | 261 | /* Binds outlet to cpu + virq. */ |
262 | 262 | ||
@@ -291,7 +291,7 @@ EXPORT_SYMBOL_GPL(ps3_irq_plug_setup); | |||
291 | int ps3_irq_plug_destroy(unsigned int virq) | 291 | int ps3_irq_plug_destroy(unsigned int virq) |
292 | { | 292 | { |
293 | int result; | 293 | int result; |
294 | const struct ps3_private *pd = get_irq_chip_data(virq); | 294 | const struct ps3_private *pd = irq_get_chip_data(virq); |
295 | 295 | ||
296 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, | 296 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, |
297 | __LINE__, pd->ppe_id, pd->thread_id, virq); | 297 | __LINE__, pd->ppe_id, pd->thread_id, virq); |
@@ -661,7 +661,7 @@ static void dump_bmp(struct ps3_private* pd) {}; | |||
661 | 661 | ||
662 | static void ps3_host_unmap(struct irq_host *h, unsigned int virq) | 662 | static void ps3_host_unmap(struct irq_host *h, unsigned int virq) |
663 | { | 663 | { |
664 | set_irq_chip_data(virq, NULL); | 664 | irq_set_chip_data(virq, NULL); |
665 | } | 665 | } |
666 | 666 | ||
667 | static int ps3_host_map(struct irq_host *h, unsigned int virq, | 667 | static int ps3_host_map(struct irq_host *h, unsigned int virq, |
@@ -670,7 +670,7 @@ static int ps3_host_map(struct irq_host *h, unsigned int virq, | |||
670 | pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq, | 670 | pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq, |
671 | virq); | 671 | virq); |
672 | 672 | ||
673 | set_irq_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq); | 673 | irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq); |
674 | 674 | ||
675 | return 0; | 675 | return 0; |
676 | } | 676 | } |
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c index 18ac801f8e90..38d24e7e7bb1 100644 --- a/arch/powerpc/platforms/pseries/msi.c +++ b/arch/powerpc/platforms/pseries/msi.c | |||
@@ -137,7 +137,7 @@ static void rtas_teardown_msi_irqs(struct pci_dev *pdev) | |||
137 | if (entry->irq == NO_IRQ) | 137 | if (entry->irq == NO_IRQ) |
138 | continue; | 138 | continue; |
139 | 139 | ||
140 | set_irq_msi(entry->irq, NULL); | 140 | irq_set_msi_desc(entry->irq, NULL); |
141 | irq_dispose_mapping(entry->irq); | 141 | irq_dispose_mapping(entry->irq); |
142 | } | 142 | } |
143 | 143 | ||
@@ -437,7 +437,7 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
437 | } | 437 | } |
438 | 438 | ||
439 | dev_dbg(&pdev->dev, "rtas_msi: allocated virq %d\n", virq); | 439 | dev_dbg(&pdev->dev, "rtas_msi: allocated virq %d\n", virq); |
440 | set_irq_msi(virq, entry); | 440 | irq_set_msi_desc(virq, entry); |
441 | 441 | ||
442 | /* Read config space back so we can restore after reset */ | 442 | /* Read config space back so we can restore after reset */ |
443 | read_msi_msg(virq, &msg); | 443 | read_msi_msg(virq, &msg); |
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c index 419707b07248..00cc3a094885 100644 --- a/arch/powerpc/platforms/pseries/nvram.c +++ b/arch/powerpc/platforms/pseries/nvram.c | |||
@@ -480,8 +480,32 @@ static void oops_to_nvram(struct kmsg_dumper *dumper, | |||
480 | const char *new_msgs, unsigned long new_len) | 480 | const char *new_msgs, unsigned long new_len) |
481 | { | 481 | { |
482 | static unsigned int oops_count = 0; | 482 | static unsigned int oops_count = 0; |
483 | static bool panicking = false; | ||
483 | size_t text_len; | 484 | size_t text_len; |
484 | 485 | ||
486 | switch (reason) { | ||
487 | case KMSG_DUMP_RESTART: | ||
488 | case KMSG_DUMP_HALT: | ||
489 | case KMSG_DUMP_POWEROFF: | ||
490 | /* These are almost always orderly shutdowns. */ | ||
491 | return; | ||
492 | case KMSG_DUMP_OOPS: | ||
493 | case KMSG_DUMP_KEXEC: | ||
494 | break; | ||
495 | case KMSG_DUMP_PANIC: | ||
496 | panicking = true; | ||
497 | break; | ||
498 | case KMSG_DUMP_EMERG: | ||
499 | if (panicking) | ||
500 | /* Panic report already captured. */ | ||
501 | return; | ||
502 | break; | ||
503 | default: | ||
504 | pr_err("%s: ignoring unrecognized KMSG_DUMP_* reason %d\n", | ||
505 | __FUNCTION__, (int) reason); | ||
506 | return; | ||
507 | } | ||
508 | |||
485 | if (clobbering_unread_rtas_event()) | 509 | if (clobbering_unread_rtas_event()) |
486 | return; | 510 | return; |
487 | 511 | ||
diff --git a/arch/powerpc/platforms/pseries/offline_states.h b/arch/powerpc/platforms/pseries/offline_states.h index 75a6f480d931..08672d9136ab 100644 --- a/arch/powerpc/platforms/pseries/offline_states.h +++ b/arch/powerpc/platforms/pseries/offline_states.h | |||
@@ -34,6 +34,4 @@ static inline void set_default_offline_state(int cpu) | |||
34 | #endif | 34 | #endif |
35 | 35 | ||
36 | extern enum cpu_state_vals get_preferred_offline_state(int cpu); | 36 | extern enum cpu_state_vals get_preferred_offline_state(int cpu); |
37 | extern int start_secondary(void); | ||
38 | extern void start_secondary_resume(void); | ||
39 | #endif | 37 | #endif |
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 2a0089a2c829..c319d04aa799 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c | |||
@@ -114,7 +114,7 @@ static void __init fwnmi_init(void) | |||
114 | 114 | ||
115 | static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc) | 115 | static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc) |
116 | { | 116 | { |
117 | struct irq_chip *chip = get_irq_desc_chip(desc); | 117 | struct irq_chip *chip = irq_desc_get_chip(desc); |
118 | unsigned int cascade_irq = i8259_irq(); | 118 | unsigned int cascade_irq = i8259_irq(); |
119 | 119 | ||
120 | if (cascade_irq != NO_IRQ) | 120 | if (cascade_irq != NO_IRQ) |
@@ -169,7 +169,7 @@ static void __init pseries_setup_i8259_cascade(void) | |||
169 | printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); | 169 | printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack); |
170 | i8259_init(found, intack); | 170 | i8259_init(found, intack); |
171 | of_node_put(found); | 171 | of_node_put(found); |
172 | set_irq_chained_handler(cascade, pseries_8259_cascade); | 172 | irq_set_chained_handler(cascade, pseries_8259_cascade); |
173 | } | 173 | } |
174 | 174 | ||
175 | static void __init pseries_mpic_init_IRQ(void) | 175 | static void __init pseries_mpic_init_IRQ(void) |
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c index 0317cce877c6..d6479f9738f0 100644 --- a/arch/powerpc/platforms/pseries/smp.c +++ b/arch/powerpc/platforms/pseries/smp.c | |||
@@ -64,8 +64,8 @@ int smp_query_cpu_stopped(unsigned int pcpu) | |||
64 | int qcss_tok = rtas_token("query-cpu-stopped-state"); | 64 | int qcss_tok = rtas_token("query-cpu-stopped-state"); |
65 | 65 | ||
66 | if (qcss_tok == RTAS_UNKNOWN_SERVICE) { | 66 | if (qcss_tok == RTAS_UNKNOWN_SERVICE) { |
67 | printk(KERN_INFO "Firmware doesn't support " | 67 | printk_once(KERN_INFO |
68 | "query-cpu-stopped-state\n"); | 68 | "Firmware doesn't support query-cpu-stopped-state\n"); |
69 | return QCSS_HARDWARE_ERROR; | 69 | return QCSS_HARDWARE_ERROR; |
70 | } | 70 | } |
71 | 71 | ||
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index 01fea46c0335..ec8fe22047b7 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c | |||
@@ -204,33 +204,33 @@ static int get_irq_server(unsigned int virq, const struct cpumask *cpumask, | |||
204 | 204 | ||
205 | static void xics_unmask_irq(struct irq_data *d) | 205 | static void xics_unmask_irq(struct irq_data *d) |
206 | { | 206 | { |
207 | unsigned int irq; | 207 | unsigned int hwirq; |
208 | int call_status; | 208 | int call_status; |
209 | int server; | 209 | int server; |
210 | 210 | ||
211 | pr_devel("xics: unmask virq %d\n", d->irq); | 211 | pr_devel("xics: unmask virq %d\n", d->irq); |
212 | 212 | ||
213 | irq = (unsigned int)irq_map[d->irq].hwirq; | 213 | hwirq = (unsigned int)irq_map[d->irq].hwirq; |
214 | pr_devel(" -> map to hwirq 0x%x\n", irq); | 214 | pr_devel(" -> map to hwirq 0x%x\n", hwirq); |
215 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 215 | if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) |
216 | return; | 216 | return; |
217 | 217 | ||
218 | server = get_irq_server(d->irq, d->affinity, 0); | 218 | server = get_irq_server(d->irq, d->affinity, 0); |
219 | 219 | ||
220 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, | 220 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq, server, |
221 | DEFAULT_PRIORITY); | 221 | DEFAULT_PRIORITY); |
222 | if (call_status != 0) { | 222 | if (call_status != 0) { |
223 | printk(KERN_ERR | 223 | printk(KERN_ERR |
224 | "%s: ibm_set_xive irq %u server %x returned %d\n", | 224 | "%s: ibm_set_xive irq %u server %x returned %d\n", |
225 | __func__, irq, server, call_status); | 225 | __func__, hwirq, server, call_status); |
226 | return; | 226 | return; |
227 | } | 227 | } |
228 | 228 | ||
229 | /* Now unmask the interrupt (often a no-op) */ | 229 | /* Now unmask the interrupt (often a no-op) */ |
230 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq); | 230 | call_status = rtas_call(ibm_int_on, 1, 1, NULL, hwirq); |
231 | if (call_status != 0) { | 231 | if (call_status != 0) { |
232 | printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", | 232 | printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n", |
233 | __func__, irq, call_status); | 233 | __func__, hwirq, call_status); |
234 | return; | 234 | return; |
235 | } | 235 | } |
236 | } | 236 | } |
@@ -250,46 +250,46 @@ static unsigned int xics_startup(struct irq_data *d) | |||
250 | return 0; | 250 | return 0; |
251 | } | 251 | } |
252 | 252 | ||
253 | static void xics_mask_real_irq(struct irq_data *d) | 253 | static void xics_mask_real_irq(unsigned int hwirq) |
254 | { | 254 | { |
255 | int call_status; | 255 | int call_status; |
256 | 256 | ||
257 | if (d->irq == XICS_IPI) | 257 | if (hwirq == XICS_IPI) |
258 | return; | 258 | return; |
259 | 259 | ||
260 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, d->irq); | 260 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, hwirq); |
261 | if (call_status != 0) { | 261 | if (call_status != 0) { |
262 | printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", | 262 | printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", |
263 | __func__, d->irq, call_status); | 263 | __func__, hwirq, call_status); |
264 | return; | 264 | return; |
265 | } | 265 | } |
266 | 266 | ||
267 | /* Have to set XIVE to 0xff to be able to remove a slot */ | 267 | /* Have to set XIVE to 0xff to be able to remove a slot */ |
268 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, d->irq, | 268 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq, |
269 | default_server, 0xff); | 269 | default_server, 0xff); |
270 | if (call_status != 0) { | 270 | if (call_status != 0) { |
271 | printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", | 271 | printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", |
272 | __func__, d->irq, call_status); | 272 | __func__, hwirq, call_status); |
273 | return; | 273 | return; |
274 | } | 274 | } |
275 | } | 275 | } |
276 | 276 | ||
277 | static void xics_mask_irq(struct irq_data *d) | 277 | static void xics_mask_irq(struct irq_data *d) |
278 | { | 278 | { |
279 | unsigned int irq; | 279 | unsigned int hwirq; |
280 | 280 | ||
281 | pr_devel("xics: mask virq %d\n", d->irq); | 281 | pr_devel("xics: mask virq %d\n", d->irq); |
282 | 282 | ||
283 | irq = (unsigned int)irq_map[d->irq].hwirq; | 283 | hwirq = (unsigned int)irq_map[d->irq].hwirq; |
284 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 284 | if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) |
285 | return; | 285 | return; |
286 | xics_mask_real_irq(d); | 286 | xics_mask_real_irq(hwirq); |
287 | } | 287 | } |
288 | 288 | ||
289 | static void xics_mask_unknown_vec(unsigned int vec) | 289 | static void xics_mask_unknown_vec(unsigned int vec) |
290 | { | 290 | { |
291 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); | 291 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); |
292 | xics_mask_real_irq(irq_get_irq_data(vec)); | 292 | xics_mask_real_irq(vec); |
293 | } | 293 | } |
294 | 294 | ||
295 | static inline unsigned int xics_xirr_vector(unsigned int xirr) | 295 | static inline unsigned int xics_xirr_vector(unsigned int xirr) |
@@ -373,37 +373,37 @@ static unsigned char pop_cppr(void) | |||
373 | 373 | ||
374 | static void xics_eoi_direct(struct irq_data *d) | 374 | static void xics_eoi_direct(struct irq_data *d) |
375 | { | 375 | { |
376 | unsigned int irq = (unsigned int)irq_map[d->irq].hwirq; | 376 | unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq; |
377 | 377 | ||
378 | iosync(); | 378 | iosync(); |
379 | direct_xirr_info_set((pop_cppr() << 24) | irq); | 379 | direct_xirr_info_set((pop_cppr() << 24) | hwirq); |
380 | } | 380 | } |
381 | 381 | ||
382 | static void xics_eoi_lpar(struct irq_data *d) | 382 | static void xics_eoi_lpar(struct irq_data *d) |
383 | { | 383 | { |
384 | unsigned int irq = (unsigned int)irq_map[d->irq].hwirq; | 384 | unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq; |
385 | 385 | ||
386 | iosync(); | 386 | iosync(); |
387 | lpar_xirr_info_set((pop_cppr() << 24) | irq); | 387 | lpar_xirr_info_set((pop_cppr() << 24) | hwirq); |
388 | } | 388 | } |
389 | 389 | ||
390 | static int | 390 | static int |
391 | xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) | 391 | xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) |
392 | { | 392 | { |
393 | unsigned int irq; | 393 | unsigned int hwirq; |
394 | int status; | 394 | int status; |
395 | int xics_status[2]; | 395 | int xics_status[2]; |
396 | int irq_server; | 396 | int irq_server; |
397 | 397 | ||
398 | irq = (unsigned int)irq_map[d->irq].hwirq; | 398 | hwirq = (unsigned int)irq_map[d->irq].hwirq; |
399 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 399 | if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) |
400 | return -1; | 400 | return -1; |
401 | 401 | ||
402 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | 402 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq); |
403 | 403 | ||
404 | if (status) { | 404 | if (status) { |
405 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", | 405 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
406 | __func__, irq, status); | 406 | __func__, hwirq, status); |
407 | return -1; | 407 | return -1; |
408 | } | 408 | } |
409 | 409 | ||
@@ -418,11 +418,11 @@ xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) | |||
418 | } | 418 | } |
419 | 419 | ||
420 | status = rtas_call(ibm_set_xive, 3, 1, NULL, | 420 | status = rtas_call(ibm_set_xive, 3, 1, NULL, |
421 | irq, irq_server, xics_status[1]); | 421 | hwirq, irq_server, xics_status[1]); |
422 | 422 | ||
423 | if (status) { | 423 | if (status) { |
424 | printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", | 424 | printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n", |
425 | __func__, irq, status); | 425 | __func__, hwirq, status); |
426 | return -1; | 426 | return -1; |
427 | } | 427 | } |
428 | 428 | ||
@@ -470,8 +470,8 @@ static int xics_host_map(struct irq_host *h, unsigned int virq, | |||
470 | /* Insert the interrupt mapping into the radix tree for fast lookup */ | 470 | /* Insert the interrupt mapping into the radix tree for fast lookup */ |
471 | irq_radix_revmap_insert(xics_host, virq, hw); | 471 | irq_radix_revmap_insert(xics_host, virq, hw); |
472 | 472 | ||
473 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 473 | irq_set_status_flags(virq, IRQ_LEVEL); |
474 | set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); | 474 | irq_set_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq); |
475 | return 0; | 475 | return 0; |
476 | } | 476 | } |
477 | 477 | ||
@@ -600,7 +600,7 @@ static void xics_request_ipi(void) | |||
600 | * IPIs are marked IRQF_DISABLED as they must run with irqs | 600 | * IPIs are marked IRQF_DISABLED as they must run with irqs |
601 | * disabled | 601 | * disabled |
602 | */ | 602 | */ |
603 | set_irq_handler(ipi, handle_percpu_irq); | 603 | irq_set_handler(ipi, handle_percpu_irq); |
604 | if (firmware_has_feature(FW_FEATURE_LPAR)) | 604 | if (firmware_has_feature(FW_FEATURE_LPAR)) |
605 | rc = request_irq(ipi, xics_ipi_action_lpar, | 605 | rc = request_irq(ipi, xics_ipi_action_lpar, |
606 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); | 606 | IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL); |
@@ -874,7 +874,7 @@ void xics_kexec_teardown_cpu(int secondary) | |||
874 | void xics_migrate_irqs_away(void) | 874 | void xics_migrate_irqs_away(void) |
875 | { | 875 | { |
876 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); | 876 | int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); |
877 | unsigned int irq, virq; | 877 | int virq; |
878 | 878 | ||
879 | /* If we used to be the default server, move to the new "boot_cpuid" */ | 879 | /* If we used to be the default server, move to the new "boot_cpuid" */ |
880 | if (hw_cpu == default_server) | 880 | if (hw_cpu == default_server) |
@@ -892,6 +892,7 @@ void xics_migrate_irqs_away(void) | |||
892 | for_each_irq(virq) { | 892 | for_each_irq(virq) { |
893 | struct irq_desc *desc; | 893 | struct irq_desc *desc; |
894 | struct irq_chip *chip; | 894 | struct irq_chip *chip; |
895 | unsigned int hwirq; | ||
895 | int xics_status[2]; | 896 | int xics_status[2]; |
896 | int status; | 897 | int status; |
897 | unsigned long flags; | 898 | unsigned long flags; |
@@ -901,9 +902,9 @@ void xics_migrate_irqs_away(void) | |||
901 | continue; | 902 | continue; |
902 | if (irq_map[virq].host != xics_host) | 903 | if (irq_map[virq].host != xics_host) |
903 | continue; | 904 | continue; |
904 | irq = (unsigned int)irq_map[virq].hwirq; | 905 | hwirq = (unsigned int)irq_map[virq].hwirq; |
905 | /* We need to get IPIs still. */ | 906 | /* We need to get IPIs still. */ |
906 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 907 | if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS) |
907 | continue; | 908 | continue; |
908 | 909 | ||
909 | desc = irq_to_desc(virq); | 910 | desc = irq_to_desc(virq); |
@@ -912,16 +913,16 @@ void xics_migrate_irqs_away(void) | |||
912 | if (desc == NULL || desc->action == NULL) | 913 | if (desc == NULL || desc->action == NULL) |
913 | continue; | 914 | continue; |
914 | 915 | ||
915 | chip = get_irq_desc_chip(desc); | 916 | chip = irq_desc_get_chip(desc); |
916 | if (chip == NULL || chip->irq_set_affinity == NULL) | 917 | if (chip == NULL || chip->irq_set_affinity == NULL) |
917 | continue; | 918 | continue; |
918 | 919 | ||
919 | raw_spin_lock_irqsave(&desc->lock, flags); | 920 | raw_spin_lock_irqsave(&desc->lock, flags); |
920 | 921 | ||
921 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq); | 922 | status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq); |
922 | if (status) { | 923 | if (status) { |
923 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", | 924 | printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n", |
924 | __func__, irq, status); | 925 | __func__, hwirq, status); |
925 | goto unlock; | 926 | goto unlock; |
926 | } | 927 | } |
927 | 928 | ||
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c index 0476bcc7c3e1..8b5aba263323 100644 --- a/arch/powerpc/sysdev/cpm1.c +++ b/arch/powerpc/sysdev/cpm1.c | |||
@@ -103,8 +103,8 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq, | |||
103 | { | 103 | { |
104 | pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); | 104 | pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); |
105 | 105 | ||
106 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 106 | irq_set_status_flags(virq, IRQ_LEVEL); |
107 | set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); | 107 | irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); |
108 | return 0; | 108 | return 0; |
109 | } | 109 | } |
110 | 110 | ||
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c index 473032556715..5495c1be472b 100644 --- a/arch/powerpc/sysdev/cpm2_pic.c +++ b/arch/powerpc/sysdev/cpm2_pic.c | |||
@@ -115,32 +115,25 @@ static void cpm2_ack(struct irq_data *d) | |||
115 | 115 | ||
116 | static void cpm2_end_irq(struct irq_data *d) | 116 | static void cpm2_end_irq(struct irq_data *d) |
117 | { | 117 | { |
118 | struct irq_desc *desc; | ||
119 | int bit, word; | 118 | int bit, word; |
120 | unsigned int irq_nr = virq_to_hw(d->irq); | 119 | unsigned int irq_nr = virq_to_hw(d->irq); |
121 | 120 | ||
122 | desc = irq_to_desc(irq_nr); | 121 | bit = irq_to_siubit[irq_nr]; |
123 | if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) | 122 | word = irq_to_siureg[irq_nr]; |
124 | && desc->action) { | ||
125 | |||
126 | bit = irq_to_siubit[irq_nr]; | ||
127 | word = irq_to_siureg[irq_nr]; | ||
128 | 123 | ||
129 | ppc_cached_irq_mask[word] |= 1 << bit; | 124 | ppc_cached_irq_mask[word] |= 1 << bit; |
130 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); | 125 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); |
131 | 126 | ||
132 | /* | 127 | /* |
133 | * Work around large numbers of spurious IRQs on PowerPC 82xx | 128 | * Work around large numbers of spurious IRQs on PowerPC 82xx |
134 | * systems. | 129 | * systems. |
135 | */ | 130 | */ |
136 | mb(); | 131 | mb(); |
137 | } | ||
138 | } | 132 | } |
139 | 133 | ||
140 | static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | 134 | static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) |
141 | { | 135 | { |
142 | unsigned int src = virq_to_hw(d->irq); | 136 | unsigned int src = virq_to_hw(d->irq); |
143 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
144 | unsigned int vold, vnew, edibit; | 137 | unsigned int vold, vnew, edibit; |
145 | 138 | ||
146 | /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or | 139 | /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or |
@@ -162,13 +155,11 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
162 | goto err_sense; | 155 | goto err_sense; |
163 | } | 156 | } |
164 | 157 | ||
165 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 158 | irqd_set_trigger_type(d, flow_type); |
166 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | 159 | if (flow_type & IRQ_TYPE_LEVEL_LOW) |
167 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { | 160 | __irq_set_handler_locked(d->irq, handle_level_irq); |
168 | desc->status |= IRQ_LEVEL; | 161 | else |
169 | desc->handle_irq = handle_level_irq; | 162 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
170 | } else | ||
171 | desc->handle_irq = handle_edge_irq; | ||
172 | 163 | ||
173 | /* internal IRQ senses are LEVEL_LOW | 164 | /* internal IRQ senses are LEVEL_LOW |
174 | * EXT IRQ and Port C IRQ senses are programmable | 165 | * EXT IRQ and Port C IRQ senses are programmable |
@@ -179,7 +170,8 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
179 | if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) | 170 | if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) |
180 | edibit = (31 - (CPM2_IRQ_PORTC0 - src)); | 171 | edibit = (31 - (CPM2_IRQ_PORTC0 - src)); |
181 | else | 172 | else |
182 | return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; | 173 | return (flow_type & IRQ_TYPE_LEVEL_LOW) ? |
174 | IRQ_SET_MASK_OK_NOCOPY : -EINVAL; | ||
183 | 175 | ||
184 | vold = in_be32(&cpm2_intctl->ic_siexr); | 176 | vold = in_be32(&cpm2_intctl->ic_siexr); |
185 | 177 | ||
@@ -190,7 +182,7 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
190 | 182 | ||
191 | if (vold != vnew) | 183 | if (vold != vnew) |
192 | out_be32(&cpm2_intctl->ic_siexr, vnew); | 184 | out_be32(&cpm2_intctl->ic_siexr, vnew); |
193 | return 0; | 185 | return IRQ_SET_MASK_OK_NOCOPY; |
194 | 186 | ||
195 | err_sense: | 187 | err_sense: |
196 | pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); | 188 | pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type); |
@@ -204,6 +196,7 @@ static struct irq_chip cpm2_pic = { | |||
204 | .irq_ack = cpm2_ack, | 196 | .irq_ack = cpm2_ack, |
205 | .irq_eoi = cpm2_end_irq, | 197 | .irq_eoi = cpm2_end_irq, |
206 | .irq_set_type = cpm2_set_irq_type, | 198 | .irq_set_type = cpm2_set_irq_type, |
199 | .flags = IRQCHIP_EOI_IF_HANDLED, | ||
207 | }; | 200 | }; |
208 | 201 | ||
209 | unsigned int cpm2_get_irq(void) | 202 | unsigned int cpm2_get_irq(void) |
@@ -226,8 +219,8 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq, | |||
226 | { | 219 | { |
227 | pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); | 220 | pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw); |
228 | 221 | ||
229 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 222 | irq_set_status_flags(virq, IRQ_LEVEL); |
230 | set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq); | 223 | irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq); |
231 | return 0; | 224 | return 0; |
232 | } | 225 | } |
233 | 226 | ||
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index 58e09b2833f2..d5679dc1e20f 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c | |||
@@ -64,10 +64,10 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq, | |||
64 | struct fsl_msi *msi_data = h->host_data; | 64 | struct fsl_msi *msi_data = h->host_data; |
65 | struct irq_chip *chip = &fsl_msi_chip; | 65 | struct irq_chip *chip = &fsl_msi_chip; |
66 | 66 | ||
67 | irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING; | 67 | irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING); |
68 | 68 | ||
69 | set_irq_chip_data(virq, msi_data); | 69 | irq_set_chip_data(virq, msi_data); |
70 | set_irq_chip_and_handler(virq, chip, handle_edge_irq); | 70 | irq_set_chip_and_handler(virq, chip, handle_edge_irq); |
71 | 71 | ||
72 | return 0; | 72 | return 0; |
73 | } | 73 | } |
@@ -110,8 +110,8 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev) | |||
110 | list_for_each_entry(entry, &pdev->msi_list, list) { | 110 | list_for_each_entry(entry, &pdev->msi_list, list) { |
111 | if (entry->irq == NO_IRQ) | 111 | if (entry->irq == NO_IRQ) |
112 | continue; | 112 | continue; |
113 | msi_data = get_irq_data(entry->irq); | 113 | msi_data = irq_get_handler_data(entry->irq); |
114 | set_irq_msi(entry->irq, NULL); | 114 | irq_set_msi_desc(entry->irq, NULL); |
115 | msi_bitmap_free_hwirqs(&msi_data->bitmap, | 115 | msi_bitmap_free_hwirqs(&msi_data->bitmap, |
116 | virq_to_hw(entry->irq), 1); | 116 | virq_to_hw(entry->irq), 1); |
117 | irq_dispose_mapping(entry->irq); | 117 | irq_dispose_mapping(entry->irq); |
@@ -168,8 +168,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
168 | rc = -ENOSPC; | 168 | rc = -ENOSPC; |
169 | goto out_free; | 169 | goto out_free; |
170 | } | 170 | } |
171 | set_irq_data(virq, msi_data); | 171 | irq_set_handler_data(virq, msi_data); |
172 | set_irq_msi(virq, entry); | 172 | irq_set_msi_desc(virq, entry); |
173 | 173 | ||
174 | fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); | 174 | fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data); |
175 | write_msi_msg(virq, &msg); | 175 | write_msi_msg(virq, &msg); |
@@ -183,7 +183,8 @@ out_free: | |||
183 | 183 | ||
184 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | 184 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) |
185 | { | 185 | { |
186 | struct irq_chip *chip = get_irq_desc_chip(desc); | 186 | struct irq_chip *chip = irq_desc_get_chip(desc); |
187 | struct irq_data *idata = irq_desc_get_irq_data(desc); | ||
187 | unsigned int cascade_irq; | 188 | unsigned int cascade_irq; |
188 | struct fsl_msi *msi_data; | 189 | struct fsl_msi *msi_data; |
189 | int msir_index = -1; | 190 | int msir_index = -1; |
@@ -192,20 +193,20 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
192 | u32 have_shift = 0; | 193 | u32 have_shift = 0; |
193 | struct fsl_msi_cascade_data *cascade_data; | 194 | struct fsl_msi_cascade_data *cascade_data; |
194 | 195 | ||
195 | cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq); | 196 | cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq); |
196 | msi_data = cascade_data->msi_data; | 197 | msi_data = cascade_data->msi_data; |
197 | 198 | ||
198 | raw_spin_lock(&desc->lock); | 199 | raw_spin_lock(&desc->lock); |
199 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { | 200 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { |
200 | if (chip->irq_mask_ack) | 201 | if (chip->irq_mask_ack) |
201 | chip->irq_mask_ack(&desc->irq_data); | 202 | chip->irq_mask_ack(idata); |
202 | else { | 203 | else { |
203 | chip->irq_mask(&desc->irq_data); | 204 | chip->irq_mask(idata); |
204 | chip->irq_ack(&desc->irq_data); | 205 | chip->irq_ack(idata); |
205 | } | 206 | } |
206 | } | 207 | } |
207 | 208 | ||
208 | if (unlikely(desc->status & IRQ_INPROGRESS)) | 209 | if (unlikely(irqd_irq_inprogress(idata))) |
209 | goto unlock; | 210 | goto unlock; |
210 | 211 | ||
211 | msir_index = cascade_data->index; | 212 | msir_index = cascade_data->index; |
@@ -213,7 +214,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
213 | if (msir_index >= NR_MSI_REG) | 214 | if (msir_index >= NR_MSI_REG) |
214 | cascade_irq = NO_IRQ; | 215 | cascade_irq = NO_IRQ; |
215 | 216 | ||
216 | desc->status |= IRQ_INPROGRESS; | 217 | irqd_set_chained_irq_inprogress(idata); |
217 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | 218 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
218 | case FSL_PIC_IP_MPIC: | 219 | case FSL_PIC_IP_MPIC: |
219 | msir_value = fsl_msi_read(msi_data->msi_regs, | 220 | msir_value = fsl_msi_read(msi_data->msi_regs, |
@@ -235,15 +236,15 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
235 | have_shift += intr_index + 1; | 236 | have_shift += intr_index + 1; |
236 | msir_value = msir_value >> (intr_index + 1); | 237 | msir_value = msir_value >> (intr_index + 1); |
237 | } | 238 | } |
238 | desc->status &= ~IRQ_INPROGRESS; | 239 | irqd_clr_chained_irq_inprogress(idata); |
239 | 240 | ||
240 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | 241 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
241 | case FSL_PIC_IP_MPIC: | 242 | case FSL_PIC_IP_MPIC: |
242 | chip->irq_eoi(&desc->irq_data); | 243 | chip->irq_eoi(idata); |
243 | break; | 244 | break; |
244 | case FSL_PIC_IP_IPIC: | 245 | case FSL_PIC_IP_IPIC: |
245 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) | 246 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
246 | chip->irq_unmask(&desc->irq_data); | 247 | chip->irq_unmask(idata); |
247 | break; | 248 | break; |
248 | } | 249 | } |
249 | unlock: | 250 | unlock: |
@@ -261,7 +262,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev) | |||
261 | for (i = 0; i < NR_MSI_REG; i++) { | 262 | for (i = 0; i < NR_MSI_REG; i++) { |
262 | virq = msi->msi_virqs[i]; | 263 | virq = msi->msi_virqs[i]; |
263 | if (virq != NO_IRQ) { | 264 | if (virq != NO_IRQ) { |
264 | cascade_data = get_irq_data(virq); | 265 | cascade_data = irq_get_handler_data(virq); |
265 | kfree(cascade_data); | 266 | kfree(cascade_data); |
266 | irq_dispose_mapping(virq); | 267 | irq_dispose_mapping(virq); |
267 | } | 268 | } |
@@ -297,8 +298,8 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi, | |||
297 | msi->msi_virqs[irq_index] = virt_msir; | 298 | msi->msi_virqs[irq_index] = virt_msir; |
298 | cascade_data->index = offset + irq_index; | 299 | cascade_data->index = offset + irq_index; |
299 | cascade_data->msi_data = msi; | 300 | cascade_data->msi_data = msi; |
300 | set_irq_data(virt_msir, cascade_data); | 301 | irq_set_handler_data(virt_msir, cascade_data); |
301 | set_irq_chained_handler(virt_msir, fsl_msi_cascade); | 302 | irq_set_chained_handler(virt_msir, fsl_msi_cascade); |
302 | 303 | ||
303 | return 0; | 304 | return 0; |
304 | } | 305 | } |
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c index aeda4c8d0a0a..142770cb84b6 100644 --- a/arch/powerpc/sysdev/i8259.c +++ b/arch/powerpc/sysdev/i8259.c | |||
@@ -175,13 +175,13 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq, | |||
175 | 175 | ||
176 | /* We block the internal cascade */ | 176 | /* We block the internal cascade */ |
177 | if (hw == 2) | 177 | if (hw == 2) |
178 | irq_to_desc(virq)->status |= IRQ_NOREQUEST; | 178 | irq_set_status_flags(virq, IRQ_NOREQUEST); |
179 | 179 | ||
180 | /* We use the level handler only for now, we might want to | 180 | /* We use the level handler only for now, we might want to |
181 | * be more cautious here but that works for now | 181 | * be more cautious here but that works for now |
182 | */ | 182 | */ |
183 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 183 | irq_set_status_flags(virq, IRQ_LEVEL); |
184 | set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq); | 184 | irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq); |
185 | return 0; | 185 | return 0; |
186 | } | 186 | } |
187 | 187 | ||
@@ -191,7 +191,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq) | |||
191 | i8259_mask_irq(irq_get_irq_data(virq)); | 191 | i8259_mask_irq(irq_get_irq_data(virq)); |
192 | 192 | ||
193 | /* remove chip and handler */ | 193 | /* remove chip and handler */ |
194 | set_irq_chip_and_handler(virq, NULL, NULL); | 194 | irq_set_chip_and_handler(virq, NULL, NULL); |
195 | 195 | ||
196 | /* Make sure it's completed */ | 196 | /* Make sure it's completed */ |
197 | synchronize_irq(virq); | 197 | synchronize_irq(virq); |
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index 497047dc986e..fa438be962b7 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c | |||
@@ -605,7 +605,6 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
605 | { | 605 | { |
606 | struct ipic *ipic = ipic_from_irq(d->irq); | 606 | struct ipic *ipic = ipic_from_irq(d->irq); |
607 | unsigned int src = ipic_irq_to_hw(d->irq); | 607 | unsigned int src = ipic_irq_to_hw(d->irq); |
608 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
609 | unsigned int vold, vnew, edibit; | 608 | unsigned int vold, vnew, edibit; |
610 | 609 | ||
611 | if (flow_type == IRQ_TYPE_NONE) | 610 | if (flow_type == IRQ_TYPE_NONE) |
@@ -623,17 +622,16 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
623 | printk(KERN_ERR "ipic: edge sense not supported on internal " | 622 | printk(KERN_ERR "ipic: edge sense not supported on internal " |
624 | "interrupts\n"); | 623 | "interrupts\n"); |
625 | return -EINVAL; | 624 | return -EINVAL; |
625 | |||
626 | } | 626 | } |
627 | 627 | ||
628 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 628 | irqd_set_trigger_type(d, flow_type); |
629 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
630 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { | 629 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { |
631 | desc->status |= IRQ_LEVEL; | 630 | __irq_set_handler_locked(d->irq, handle_level_irq); |
632 | desc->handle_irq = handle_level_irq; | 631 | d->chip = &ipic_level_irq_chip; |
633 | desc->irq_data.chip = &ipic_level_irq_chip; | ||
634 | } else { | 632 | } else { |
635 | desc->handle_irq = handle_edge_irq; | 633 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
636 | desc->irq_data.chip = &ipic_edge_irq_chip; | 634 | d->chip = &ipic_edge_irq_chip; |
637 | } | 635 | } |
638 | 636 | ||
639 | /* only EXT IRQ senses are programmable on ipic | 637 | /* only EXT IRQ senses are programmable on ipic |
@@ -655,7 +653,7 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
655 | } | 653 | } |
656 | if (vold != vnew) | 654 | if (vold != vnew) |
657 | ipic_write(ipic->regs, IPIC_SECNR, vnew); | 655 | ipic_write(ipic->regs, IPIC_SECNR, vnew); |
658 | return 0; | 656 | return IRQ_SET_MASK_OK_NOCOPY; |
659 | } | 657 | } |
660 | 658 | ||
661 | /* level interrupts and edge interrupts have different ack operations */ | 659 | /* level interrupts and edge interrupts have different ack operations */ |
@@ -687,11 +685,11 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq, | |||
687 | { | 685 | { |
688 | struct ipic *ipic = h->host_data; | 686 | struct ipic *ipic = h->host_data; |
689 | 687 | ||
690 | set_irq_chip_data(virq, ipic); | 688 | irq_set_chip_data(virq, ipic); |
691 | set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); | 689 | irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq); |
692 | 690 | ||
693 | /* Set default irq type */ | 691 | /* Set default irq type */ |
694 | set_irq_type(virq, IRQ_TYPE_NONE); | 692 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
695 | 693 | ||
696 | return 0; | 694 | return 0; |
697 | } | 695 | } |
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c index 1a75a7fb4a99..a88800ff4d01 100644 --- a/arch/powerpc/sysdev/mpc8xx_pic.c +++ b/arch/powerpc/sysdev/mpc8xx_pic.c | |||
@@ -72,13 +72,6 @@ static void mpc8xx_end_irq(struct irq_data *d) | |||
72 | 72 | ||
73 | static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) | 73 | static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) |
74 | { | 74 | { |
75 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
76 | |||
77 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
78 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
79 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
80 | desc->status |= IRQ_LEVEL; | ||
81 | |||
82 | if (flow_type & IRQ_TYPE_EDGE_FALLING) { | 75 | if (flow_type & IRQ_TYPE_EDGE_FALLING) { |
83 | irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; | 76 | irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; |
84 | unsigned int siel = in_be32(&siu_reg->sc_siel); | 77 | unsigned int siel = in_be32(&siu_reg->sc_siel); |
@@ -87,7 +80,7 @@ static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
87 | if ((hw & 1) == 0) { | 80 | if ((hw & 1) == 0) { |
88 | siel |= (0x80000000 >> hw); | 81 | siel |= (0x80000000 >> hw); |
89 | out_be32(&siu_reg->sc_siel, siel); | 82 | out_be32(&siu_reg->sc_siel, siel); |
90 | desc->handle_irq = handle_edge_irq; | 83 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
91 | } | 84 | } |
92 | } | 85 | } |
93 | return 0; | 86 | return 0; |
@@ -124,7 +117,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq, | |||
124 | pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); | 117 | pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw); |
125 | 118 | ||
126 | /* Set default irq handle */ | 119 | /* Set default irq handle */ |
127 | set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); | 120 | irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq); |
128 | return 0; | 121 | return 0; |
129 | } | 122 | } |
130 | 123 | ||
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c index 232e701245d7..0892a2841c2b 100644 --- a/arch/powerpc/sysdev/mpc8xxx_gpio.c +++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c | |||
@@ -145,7 +145,7 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |||
145 | 145 | ||
146 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) | 146 | static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) |
147 | { | 147 | { |
148 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc); | 148 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); |
149 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; | 149 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
150 | unsigned int mask; | 150 | unsigned int mask; |
151 | 151 | ||
@@ -278,9 +278,9 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, | |||
278 | if (mpc8xxx_gc->of_dev_id_data) | 278 | if (mpc8xxx_gc->of_dev_id_data) |
279 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; | 279 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
280 | 280 | ||
281 | set_irq_chip_data(virq, h->host_data); | 281 | irq_set_chip_data(virq, h->host_data); |
282 | set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); | 282 | irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); |
283 | set_irq_type(virq, IRQ_TYPE_NONE); | 283 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
284 | 284 | ||
285 | return 0; | 285 | return 0; |
286 | } | 286 | } |
@@ -369,8 +369,8 @@ static void __init mpc8xxx_add_controller(struct device_node *np) | |||
369 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); | 369 | out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); |
370 | out_be32(mm_gc->regs + GPIO_IMR, 0); | 370 | out_be32(mm_gc->regs + GPIO_IMR, 0); |
371 | 371 | ||
372 | set_irq_data(hwirq, mpc8xxx_gc); | 372 | irq_set_handler_data(hwirq, mpc8xxx_gc); |
373 | set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); | 373 | irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); |
374 | 374 | ||
375 | skip_irq: | 375 | skip_irq: |
376 | return; | 376 | return; |
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 0f7c6718d261..f91c065bed5a 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
@@ -361,7 +361,7 @@ static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) | |||
361 | } | 361 | } |
362 | 362 | ||
363 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, | 363 | static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, |
364 | unsigned int irqflags) | 364 | bool level) |
365 | { | 365 | { |
366 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | 366 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
367 | unsigned long flags; | 367 | unsigned long flags; |
@@ -370,14 +370,14 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, | |||
370 | if (fixup->base == NULL) | 370 | if (fixup->base == NULL) |
371 | return; | 371 | return; |
372 | 372 | ||
373 | DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n", | 373 | DBG("startup_ht_interrupt(0x%x) index: %d\n", |
374 | source, irqflags, fixup->index); | 374 | source, fixup->index); |
375 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); | 375 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
376 | /* Enable and configure */ | 376 | /* Enable and configure */ |
377 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); | 377 | writeb(0x10 + 2 * fixup->index, fixup->base + 2); |
378 | tmp = readl(fixup->base + 4); | 378 | tmp = readl(fixup->base + 4); |
379 | tmp &= ~(0x23U); | 379 | tmp &= ~(0x23U); |
380 | if (irqflags & IRQ_LEVEL) | 380 | if (level) |
381 | tmp |= 0x22; | 381 | tmp |= 0x22; |
382 | writel(tmp, fixup->base + 4); | 382 | writel(tmp, fixup->base + 4); |
383 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); | 383 | raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); |
@@ -389,8 +389,7 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, | |||
389 | #endif | 389 | #endif |
390 | } | 390 | } |
391 | 391 | ||
392 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, | 392 | static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) |
393 | unsigned int irqflags) | ||
394 | { | 393 | { |
395 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; | 394 | struct mpic_irq_fixup *fixup = &mpic->fixups[source]; |
396 | unsigned long flags; | 395 | unsigned long flags; |
@@ -399,7 +398,7 @@ static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source, | |||
399 | if (fixup->base == NULL) | 398 | if (fixup->base == NULL) |
400 | return; | 399 | return; |
401 | 400 | ||
402 | DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags); | 401 | DBG("shutdown_ht_interrupt(0x%x)\n", source); |
403 | 402 | ||
404 | /* Disable */ | 403 | /* Disable */ |
405 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); | 404 | raw_spin_lock_irqsave(&mpic->fixup_lock, flags); |
@@ -616,7 +615,7 @@ static struct mpic *mpic_find(unsigned int irq) | |||
616 | if (irq < NUM_ISA_INTERRUPTS) | 615 | if (irq < NUM_ISA_INTERRUPTS) |
617 | return NULL; | 616 | return NULL; |
618 | 617 | ||
619 | return get_irq_chip_data(irq); | 618 | return irq_get_chip_data(irq); |
620 | } | 619 | } |
621 | 620 | ||
622 | /* Determine if the linux irq is an IPI */ | 621 | /* Determine if the linux irq is an IPI */ |
@@ -650,7 +649,7 @@ static inline struct mpic * mpic_from_ipi(struct irq_data *d) | |||
650 | /* Get the mpic structure from the irq number */ | 649 | /* Get the mpic structure from the irq number */ |
651 | static inline struct mpic * mpic_from_irq(unsigned int irq) | 650 | static inline struct mpic * mpic_from_irq(unsigned int irq) |
652 | { | 651 | { |
653 | return get_irq_chip_data(irq); | 652 | return irq_get_chip_data(irq); |
654 | } | 653 | } |
655 | 654 | ||
656 | /* Get the mpic structure from the irq data */ | 655 | /* Get the mpic structure from the irq data */ |
@@ -738,7 +737,7 @@ static void mpic_unmask_ht_irq(struct irq_data *d) | |||
738 | 737 | ||
739 | mpic_unmask_irq(d); | 738 | mpic_unmask_irq(d); |
740 | 739 | ||
741 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) | 740 | if (irqd_is_level_type(d)) |
742 | mpic_ht_end_irq(mpic, src); | 741 | mpic_ht_end_irq(mpic, src); |
743 | } | 742 | } |
744 | 743 | ||
@@ -748,7 +747,7 @@ static unsigned int mpic_startup_ht_irq(struct irq_data *d) | |||
748 | unsigned int src = mpic_irq_to_hw(d->irq); | 747 | unsigned int src = mpic_irq_to_hw(d->irq); |
749 | 748 | ||
750 | mpic_unmask_irq(d); | 749 | mpic_unmask_irq(d); |
751 | mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); | 750 | mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); |
752 | 751 | ||
753 | return 0; | 752 | return 0; |
754 | } | 753 | } |
@@ -758,7 +757,7 @@ static void mpic_shutdown_ht_irq(struct irq_data *d) | |||
758 | struct mpic *mpic = mpic_from_irq_data(d); | 757 | struct mpic *mpic = mpic_from_irq_data(d); |
759 | unsigned int src = mpic_irq_to_hw(d->irq); | 758 | unsigned int src = mpic_irq_to_hw(d->irq); |
760 | 759 | ||
761 | mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); | 760 | mpic_shutdown_ht_interrupt(mpic, src); |
762 | mpic_mask_irq(d); | 761 | mpic_mask_irq(d); |
763 | } | 762 | } |
764 | 763 | ||
@@ -775,7 +774,7 @@ static void mpic_end_ht_irq(struct irq_data *d) | |||
775 | * latched another edge interrupt coming in anyway | 774 | * latched another edge interrupt coming in anyway |
776 | */ | 775 | */ |
777 | 776 | ||
778 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) | 777 | if (irqd_is_level_type(d)) |
779 | mpic_ht_end_irq(mpic, src); | 778 | mpic_ht_end_irq(mpic, src); |
780 | mpic_eoi(mpic); | 779 | mpic_eoi(mpic); |
781 | } | 780 | } |
@@ -864,7 +863,6 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
864 | { | 863 | { |
865 | struct mpic *mpic = mpic_from_irq_data(d); | 864 | struct mpic *mpic = mpic_from_irq_data(d); |
866 | unsigned int src = mpic_irq_to_hw(d->irq); | 865 | unsigned int src = mpic_irq_to_hw(d->irq); |
867 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
868 | unsigned int vecpri, vold, vnew; | 866 | unsigned int vecpri, vold, vnew; |
869 | 867 | ||
870 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", | 868 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
@@ -879,10 +877,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
879 | if (flow_type == IRQ_TYPE_NONE) | 877 | if (flow_type == IRQ_TYPE_NONE) |
880 | flow_type = IRQ_TYPE_LEVEL_LOW; | 878 | flow_type = IRQ_TYPE_LEVEL_LOW; |
881 | 879 | ||
882 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 880 | irqd_set_trigger_type(d, flow_type); |
883 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
884 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
885 | desc->status |= IRQ_LEVEL; | ||
886 | 881 | ||
887 | if (mpic_is_ht_interrupt(mpic, src)) | 882 | if (mpic_is_ht_interrupt(mpic, src)) |
888 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | | 883 | vecpri = MPIC_VECPRI_POLARITY_POSITIVE | |
@@ -897,7 +892,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
897 | if (vold != vnew) | 892 | if (vold != vnew) |
898 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); | 893 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew); |
899 | 894 | ||
900 | return 0; | 895 | return IRQ_SET_MASK_OK_NOCOPY;; |
901 | } | 896 | } |
902 | 897 | ||
903 | void mpic_set_vector(unsigned int virq, unsigned int vector) | 898 | void mpic_set_vector(unsigned int virq, unsigned int vector) |
@@ -983,8 +978,8 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, | |||
983 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); | 978 | WARN_ON(!(mpic->flags & MPIC_PRIMARY)); |
984 | 979 | ||
985 | DBG("mpic: mapping as IPI\n"); | 980 | DBG("mpic: mapping as IPI\n"); |
986 | set_irq_chip_data(virq, mpic); | 981 | irq_set_chip_data(virq, mpic); |
987 | set_irq_chip_and_handler(virq, &mpic->hc_ipi, | 982 | irq_set_chip_and_handler(virq, &mpic->hc_ipi, |
988 | handle_percpu_irq); | 983 | handle_percpu_irq); |
989 | return 0; | 984 | return 0; |
990 | } | 985 | } |
@@ -1006,11 +1001,11 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, | |||
1006 | 1001 | ||
1007 | DBG("mpic: mapping to irq chip @%p\n", chip); | 1002 | DBG("mpic: mapping to irq chip @%p\n", chip); |
1008 | 1003 | ||
1009 | set_irq_chip_data(virq, mpic); | 1004 | irq_set_chip_data(virq, mpic); |
1010 | set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq); | 1005 | irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq); |
1011 | 1006 | ||
1012 | /* Set default irq type */ | 1007 | /* Set default irq type */ |
1013 | set_irq_type(virq, IRQ_TYPE_NONE); | 1008 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
1014 | 1009 | ||
1015 | /* If the MPIC was reset, then all vectors have already been | 1010 | /* If the MPIC was reset, then all vectors have already been |
1016 | * initialized. Otherwise, a per source lazy initialization | 1011 | * initialized. Otherwise, a per source lazy initialization |
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c index 0b7794acfce1..38e62382070c 100644 --- a/arch/powerpc/sysdev/mpic_pasemi_msi.c +++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c | |||
@@ -81,7 +81,7 @@ static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev) | |||
81 | if (entry->irq == NO_IRQ) | 81 | if (entry->irq == NO_IRQ) |
82 | continue; | 82 | continue; |
83 | 83 | ||
84 | set_irq_msi(entry->irq, NULL); | 84 | irq_set_msi_desc(entry->irq, NULL); |
85 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, | 85 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, |
86 | virq_to_hw(entry->irq), ALLOC_CHUNK); | 86 | virq_to_hw(entry->irq), ALLOC_CHUNK); |
87 | irq_dispose_mapping(entry->irq); | 87 | irq_dispose_mapping(entry->irq); |
@@ -131,9 +131,9 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
131 | */ | 131 | */ |
132 | mpic_set_vector(virq, 0); | 132 | mpic_set_vector(virq, 0); |
133 | 133 | ||
134 | set_irq_msi(virq, entry); | 134 | irq_set_msi_desc(virq, entry); |
135 | set_irq_chip(virq, &mpic_pasemi_msi_chip); | 135 | irq_set_chip(virq, &mpic_pasemi_msi_chip); |
136 | set_irq_type(virq, IRQ_TYPE_EDGE_RISING); | 136 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
137 | 137 | ||
138 | pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ | 138 | pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ |
139 | "addr 0x%x\n", virq, hwirq, msg.address_lo); | 139 | "addr 0x%x\n", virq, hwirq, msg.address_lo); |
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c index 71900ac78270..9a7aa0ed9c1c 100644 --- a/arch/powerpc/sysdev/mpic_u3msi.c +++ b/arch/powerpc/sysdev/mpic_u3msi.c | |||
@@ -129,7 +129,7 @@ static void u3msi_teardown_msi_irqs(struct pci_dev *pdev) | |||
129 | if (entry->irq == NO_IRQ) | 129 | if (entry->irq == NO_IRQ) |
130 | continue; | 130 | continue; |
131 | 131 | ||
132 | set_irq_msi(entry->irq, NULL); | 132 | irq_set_msi_desc(entry->irq, NULL); |
133 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, | 133 | msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, |
134 | virq_to_hw(entry->irq), 1); | 134 | virq_to_hw(entry->irq), 1); |
135 | irq_dispose_mapping(entry->irq); | 135 | irq_dispose_mapping(entry->irq); |
@@ -166,9 +166,9 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) | |||
166 | return -ENOSPC; | 166 | return -ENOSPC; |
167 | } | 167 | } |
168 | 168 | ||
169 | set_irq_msi(virq, entry); | 169 | irq_set_msi_desc(virq, entry); |
170 | set_irq_chip(virq, &mpic_u3msi_chip); | 170 | irq_set_chip(virq, &mpic_u3msi_chip); |
171 | set_irq_type(virq, IRQ_TYPE_EDGE_RISING); | 171 | irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); |
172 | 172 | ||
173 | pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", | 173 | pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n", |
174 | virq, hwirq, (unsigned long)addr); | 174 | virq, hwirq, (unsigned long)addr); |
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c index bc61ebb8987c..e9c633c7c083 100644 --- a/arch/powerpc/sysdev/mv64x60_pic.c +++ b/arch/powerpc/sysdev/mv64x60_pic.c | |||
@@ -213,11 +213,12 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq, | |||
213 | { | 213 | { |
214 | int level1; | 214 | int level1; |
215 | 215 | ||
216 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 216 | irq_set_status_flags(virq, IRQ_LEVEL); |
217 | 217 | ||
218 | level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; | 218 | level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET; |
219 | BUG_ON(level1 > MV64x60_LEVEL1_GPP); | 219 | BUG_ON(level1 > MV64x60_LEVEL1_GPP); |
220 | set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq); | 220 | irq_set_chip_and_handler(virq, mv64x60_chips[level1], |
221 | handle_level_irq); | ||
221 | 222 | ||
222 | return 0; | 223 | return 0; |
223 | } | 224 | } |
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c index 8c9ded8ea07c..832d6924ad1c 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_ic.c +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c | |||
@@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg | |||
189 | 189 | ||
190 | static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) | 190 | static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) |
191 | { | 191 | { |
192 | return get_irq_chip_data(virq); | 192 | return irq_get_chip_data(virq); |
193 | } | 193 | } |
194 | 194 | ||
195 | static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) | 195 | static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) |
@@ -267,10 +267,10 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq, | |||
267 | /* Default chip */ | 267 | /* Default chip */ |
268 | chip = &qe_ic->hc_irq; | 268 | chip = &qe_ic->hc_irq; |
269 | 269 | ||
270 | set_irq_chip_data(virq, qe_ic); | 270 | irq_set_chip_data(virq, qe_ic); |
271 | irq_to_desc(virq)->status |= IRQ_LEVEL; | 271 | irq_set_status_flags(virq, IRQ_LEVEL); |
272 | 272 | ||
273 | set_irq_chip_and_handler(virq, chip, handle_level_irq); | 273 | irq_set_chip_and_handler(virq, chip, handle_level_irq); |
274 | 274 | ||
275 | return 0; | 275 | return 0; |
276 | } | 276 | } |
@@ -386,13 +386,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags, | |||
386 | 386 | ||
387 | qe_ic_write(qe_ic->regs, QEIC_CICR, temp); | 387 | qe_ic_write(qe_ic->regs, QEIC_CICR, temp); |
388 | 388 | ||
389 | set_irq_data(qe_ic->virq_low, qe_ic); | 389 | irq_set_handler_data(qe_ic->virq_low, qe_ic); |
390 | set_irq_chained_handler(qe_ic->virq_low, low_handler); | 390 | irq_set_chained_handler(qe_ic->virq_low, low_handler); |
391 | 391 | ||
392 | if (qe_ic->virq_high != NO_IRQ && | 392 | if (qe_ic->virq_high != NO_IRQ && |
393 | qe_ic->virq_high != qe_ic->virq_low) { | 393 | qe_ic->virq_high != qe_ic->virq_low) { |
394 | set_irq_data(qe_ic->virq_high, qe_ic); | 394 | irq_set_handler_data(qe_ic->virq_high, qe_ic); |
395 | set_irq_chained_handler(qe_ic->virq_high, high_handler); | 395 | irq_set_chained_handler(qe_ic->virq_high, high_handler); |
396 | } | 396 | } |
397 | } | 397 | } |
398 | 398 | ||
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 02c91db90037..4d18658116e5 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c | |||
@@ -391,8 +391,8 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq, | |||
391 | DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); | 391 | DBG("%s(%d, 0x%lx)\n", __func__, virq, hw); |
392 | if ((virq >= 1) && (virq <= 4)){ | 392 | if ((virq >= 1) && (virq <= 4)){ |
393 | irq = virq + IRQ_PCI_INTAD_BASE - 1; | 393 | irq = virq + IRQ_PCI_INTAD_BASE - 1; |
394 | irq_to_desc(irq)->status |= IRQ_LEVEL; | 394 | irq_set_status_flags(irq, IRQ_LEVEL); |
395 | set_irq_chip(irq, &tsi108_pci_irq); | 395 | irq_set_chip(irq, &tsi108_pci_irq); |
396 | } | 396 | } |
397 | return 0; | 397 | return 0; |
398 | } | 398 | } |
@@ -431,7 +431,7 @@ void __init tsi108_pci_int_init(struct device_node *node) | |||
431 | 431 | ||
432 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) | 432 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) |
433 | { | 433 | { |
434 | struct irq_chip *chip = get_irq_desc_chip(desc); | 434 | struct irq_chip *chip = irq_desc_get_chip(desc); |
435 | unsigned int cascade_irq = get_pci_source(); | 435 | unsigned int cascade_irq = get_pci_source(); |
436 | 436 | ||
437 | if (cascade_irq != NO_IRQ) | 437 | if (cascade_irq != NO_IRQ) |
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c index 835f7958b237..5d9138516628 100644 --- a/arch/powerpc/sysdev/uic.c +++ b/arch/powerpc/sysdev/uic.c | |||
@@ -57,7 +57,6 @@ struct uic { | |||
57 | 57 | ||
58 | static void uic_unmask_irq(struct irq_data *d) | 58 | static void uic_unmask_irq(struct irq_data *d) |
59 | { | 59 | { |
60 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
61 | struct uic *uic = irq_data_get_irq_chip_data(d); | 60 | struct uic *uic = irq_data_get_irq_chip_data(d); |
62 | unsigned int src = uic_irq_to_hw(d->irq); | 61 | unsigned int src = uic_irq_to_hw(d->irq); |
63 | unsigned long flags; | 62 | unsigned long flags; |
@@ -66,7 +65,7 @@ static void uic_unmask_irq(struct irq_data *d) | |||
66 | sr = 1 << (31-src); | 65 | sr = 1 << (31-src); |
67 | spin_lock_irqsave(&uic->lock, flags); | 66 | spin_lock_irqsave(&uic->lock, flags); |
68 | /* ack level-triggered interrupts here */ | 67 | /* ack level-triggered interrupts here */ |
69 | if (desc->status & IRQ_LEVEL) | 68 | if (irqd_is_level_type(d)) |
70 | mtdcr(uic->dcrbase + UIC_SR, sr); | 69 | mtdcr(uic->dcrbase + UIC_SR, sr); |
71 | er = mfdcr(uic->dcrbase + UIC_ER); | 70 | er = mfdcr(uic->dcrbase + UIC_ER); |
72 | er |= sr; | 71 | er |= sr; |
@@ -101,7 +100,6 @@ static void uic_ack_irq(struct irq_data *d) | |||
101 | 100 | ||
102 | static void uic_mask_ack_irq(struct irq_data *d) | 101 | static void uic_mask_ack_irq(struct irq_data *d) |
103 | { | 102 | { |
104 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
105 | struct uic *uic = irq_data_get_irq_chip_data(d); | 103 | struct uic *uic = irq_data_get_irq_chip_data(d); |
106 | unsigned int src = uic_irq_to_hw(d->irq); | 104 | unsigned int src = uic_irq_to_hw(d->irq); |
107 | unsigned long flags; | 105 | unsigned long flags; |
@@ -120,7 +118,7 @@ static void uic_mask_ack_irq(struct irq_data *d) | |||
120 | * level interrupts are ack'ed after the actual | 118 | * level interrupts are ack'ed after the actual |
121 | * isr call in the uic_unmask_irq() | 119 | * isr call in the uic_unmask_irq() |
122 | */ | 120 | */ |
123 | if (!(desc->status & IRQ_LEVEL)) | 121 | if (!irqd_is_level_type(d)) |
124 | mtdcr(uic->dcrbase + UIC_SR, sr); | 122 | mtdcr(uic->dcrbase + UIC_SR, sr); |
125 | spin_unlock_irqrestore(&uic->lock, flags); | 123 | spin_unlock_irqrestore(&uic->lock, flags); |
126 | } | 124 | } |
@@ -129,7 +127,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
129 | { | 127 | { |
130 | struct uic *uic = irq_data_get_irq_chip_data(d); | 128 | struct uic *uic = irq_data_get_irq_chip_data(d); |
131 | unsigned int src = uic_irq_to_hw(d->irq); | 129 | unsigned int src = uic_irq_to_hw(d->irq); |
132 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
133 | unsigned long flags; | 130 | unsigned long flags; |
134 | int trigger, polarity; | 131 | int trigger, polarity; |
135 | u32 tr, pr, mask; | 132 | u32 tr, pr, mask; |
@@ -166,11 +163,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) | |||
166 | mtdcr(uic->dcrbase + UIC_PR, pr); | 163 | mtdcr(uic->dcrbase + UIC_PR, pr); |
167 | mtdcr(uic->dcrbase + UIC_TR, tr); | 164 | mtdcr(uic->dcrbase + UIC_TR, tr); |
168 | 165 | ||
169 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
170 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
171 | if (!trigger) | ||
172 | desc->status |= IRQ_LEVEL; | ||
173 | |||
174 | spin_unlock_irqrestore(&uic->lock, flags); | 166 | spin_unlock_irqrestore(&uic->lock, flags); |
175 | 167 | ||
176 | return 0; | 168 | return 0; |
@@ -190,13 +182,13 @@ static int uic_host_map(struct irq_host *h, unsigned int virq, | |||
190 | { | 182 | { |
191 | struct uic *uic = h->host_data; | 183 | struct uic *uic = h->host_data; |
192 | 184 | ||
193 | set_irq_chip_data(virq, uic); | 185 | irq_set_chip_data(virq, uic); |
194 | /* Despite the name, handle_level_irq() works for both level | 186 | /* Despite the name, handle_level_irq() works for both level |
195 | * and edge irqs on UIC. FIXME: check this is correct */ | 187 | * and edge irqs on UIC. FIXME: check this is correct */ |
196 | set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); | 188 | irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); |
197 | 189 | ||
198 | /* Set default irq type */ | 190 | /* Set default irq type */ |
199 | set_irq_type(virq, IRQ_TYPE_NONE); | 191 | irq_set_irq_type(virq, IRQ_TYPE_NONE); |
200 | 192 | ||
201 | return 0; | 193 | return 0; |
202 | } | 194 | } |
@@ -220,17 +212,18 @@ static struct irq_host_ops uic_host_ops = { | |||
220 | 212 | ||
221 | void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) | 213 | void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) |
222 | { | 214 | { |
223 | struct irq_chip *chip = get_irq_desc_chip(desc); | 215 | struct irq_chip *chip = irq_desc_get_chip(desc); |
224 | struct uic *uic = get_irq_data(virq); | 216 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
217 | struct uic *uic = irq_get_handler_data(virq); | ||
225 | u32 msr; | 218 | u32 msr; |
226 | int src; | 219 | int src; |
227 | int subvirq; | 220 | int subvirq; |
228 | 221 | ||
229 | raw_spin_lock(&desc->lock); | 222 | raw_spin_lock(&desc->lock); |
230 | if (desc->status & IRQ_LEVEL) | 223 | if (irqd_is_level_type(idata)) |
231 | chip->irq_mask(&desc->irq_data); | 224 | chip->irq_mask(idata); |
232 | else | 225 | else |
233 | chip->irq_mask_ack(&desc->irq_data); | 226 | chip->irq_mask_ack(idata); |
234 | raw_spin_unlock(&desc->lock); | 227 | raw_spin_unlock(&desc->lock); |
235 | 228 | ||
236 | msr = mfdcr(uic->dcrbase + UIC_MSR); | 229 | msr = mfdcr(uic->dcrbase + UIC_MSR); |
@@ -244,10 +237,10 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
244 | 237 | ||
245 | uic_irq_ret: | 238 | uic_irq_ret: |
246 | raw_spin_lock(&desc->lock); | 239 | raw_spin_lock(&desc->lock); |
247 | if (desc->status & IRQ_LEVEL) | 240 | if (irqd_is_level_type(idata)) |
248 | chip->irq_ack(&desc->irq_data); | 241 | chip->irq_ack(idata); |
249 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) | 242 | if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
250 | chip->irq_unmask(&desc->irq_data); | 243 | chip->irq_unmask(idata); |
251 | raw_spin_unlock(&desc->lock); | 244 | raw_spin_unlock(&desc->lock); |
252 | } | 245 | } |
253 | 246 | ||
@@ -336,8 +329,8 @@ void __init uic_init_tree(void) | |||
336 | 329 | ||
337 | cascade_virq = irq_of_parse_and_map(np, 0); | 330 | cascade_virq = irq_of_parse_and_map(np, 0); |
338 | 331 | ||
339 | set_irq_data(cascade_virq, uic); | 332 | irq_set_handler_data(cascade_virq, uic); |
340 | set_irq_chained_handler(cascade_virq, uic_irq_cascade); | 333 | irq_set_chained_handler(cascade_virq, uic_irq_cascade); |
341 | 334 | ||
342 | /* FIXME: setup critical cascade?? */ | 335 | /* FIXME: setup critical cascade?? */ |
343 | } | 336 | } |
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index 7436f3ed4df6..0a13fc19e287 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c | |||
@@ -79,12 +79,6 @@ static void xilinx_intc_mask(struct irq_data *d) | |||
79 | 79 | ||
80 | static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) | 80 | static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) |
81 | { | 81 | { |
82 | struct irq_desc *desc = irq_to_desc(d->irq); | ||
83 | |||
84 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | ||
85 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | ||
86 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | ||
87 | desc->status |= IRQ_LEVEL; | ||
88 | return 0; | 82 | return 0; |
89 | } | 83 | } |
90 | 84 | ||
@@ -170,15 +164,15 @@ static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct, | |||
170 | static int xilinx_intc_map(struct irq_host *h, unsigned int virq, | 164 | static int xilinx_intc_map(struct irq_host *h, unsigned int virq, |
171 | irq_hw_number_t irq) | 165 | irq_hw_number_t irq) |
172 | { | 166 | { |
173 | set_irq_chip_data(virq, h->host_data); | 167 | irq_set_chip_data(virq, h->host_data); |
174 | 168 | ||
175 | if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH || | 169 | if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH || |
176 | xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) { | 170 | xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) { |
177 | set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip, | 171 | irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip, |
178 | handle_level_irq); | 172 | handle_level_irq); |
179 | } else { | 173 | } else { |
180 | set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip, | 174 | irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip, |
181 | handle_edge_irq); | 175 | handle_edge_irq); |
182 | } | 176 | } |
183 | return 0; | 177 | return 0; |
184 | } | 178 | } |
@@ -229,7 +223,7 @@ int xilinx_intc_get_irq(void) | |||
229 | */ | 223 | */ |
230 | static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) | 224 | static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) |
231 | { | 225 | { |
232 | struct irq_chip *chip = get_irq_desc_chip(desc); | 226 | struct irq_chip *chip = irq_desc_get_chip(desc); |
233 | unsigned int cascade_irq = i8259_irq(); | 227 | unsigned int cascade_irq = i8259_irq(); |
234 | 228 | ||
235 | if (cascade_irq) | 229 | if (cascade_irq) |
@@ -256,7 +250,7 @@ static void __init xilinx_i8259_setup_cascade(void) | |||
256 | } | 250 | } |
257 | 251 | ||
258 | i8259_init(cascade_node, 0); | 252 | i8259_init(cascade_node, 0); |
259 | set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade); | 253 | irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade); |
260 | 254 | ||
261 | /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ | 255 | /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */ |
262 | /* This looks like a dirty hack to me --gcl */ | 256 | /* This looks like a dirty hack to me --gcl */ |
diff --git a/arch/score/Kconfig b/arch/score/Kconfig index 4278bbc032ce..e73bc781cc14 100644 --- a/arch/score/Kconfig +++ b/arch/score/Kconfig | |||
@@ -3,7 +3,6 @@ menu "Machine selection" | |||
3 | config SCORE | 3 | config SCORE |
4 | def_bool y | 4 | def_bool y |
5 | select HAVE_GENERIC_HARDIRQS | 5 | select HAVE_GENERIC_HARDIRQS |
6 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
7 | select GENERIC_IRQ_SHOW | 6 | select GENERIC_IRQ_SHOW |
8 | 7 | ||
9 | choice | 8 | choice |
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 9af3c8d0776b..bc439de48cd1 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig | |||
@@ -23,7 +23,6 @@ config SUPERH | |||
23 | select HAVE_SPARSE_IRQ | 23 | select HAVE_SPARSE_IRQ |
24 | select RTC_LIB | 24 | select RTC_LIB |
25 | select GENERIC_ATOMIC64 | 25 | select GENERIC_ATOMIC64 |
26 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
27 | select GENERIC_IRQ_SHOW | 26 | select GENERIC_IRQ_SHOW |
28 | help | 27 | help |
29 | The SuperH is a RISC processor targeted for use in embedded systems | 28 | The SuperH is a RISC processor targeted for use in embedded systems |
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c index efba450a0518..93f5039099b7 100644 --- a/arch/sh/boards/board-magicpanelr2.c +++ b/arch/sh/boards/board-magicpanelr2.c | |||
@@ -388,12 +388,12 @@ static void __init init_mpr2_IRQ(void) | |||
388 | { | 388 | { |
389 | plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ | 389 | plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ |
390 | 390 | ||
391 | set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ | 391 | irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ |
392 | set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ | 392 | irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ |
393 | set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ | 393 | irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ |
394 | set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ | 394 | irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ |
395 | set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ | 395 | irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ |
396 | set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ | 396 | irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ |
397 | 397 | ||
398 | intc_set_priority(32, 13); /* IRQ0 CAN1 */ | 398 | intc_set_priority(32, 13); /* IRQ0 CAN1 */ |
399 | intc_set_priority(33, 13); /* IRQ0 CAN2 */ | 399 | intc_set_priority(33, 13); /* IRQ0 CAN2 */ |
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c index 3e5fc3bbf3ed..636d8318a72a 100644 --- a/arch/sh/boards/mach-ap325rxa/setup.c +++ b/arch/sh/boards/mach-ap325rxa/setup.c | |||
@@ -14,8 +14,8 @@ | |||
14 | #include <linux/device.h> | 14 | #include <linux/device.h> |
15 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
18 | #include <linux/mmc/host.h> | 17 | #include <linux/mmc/host.h> |
18 | #include <linux/mmc/sh_mobile_sdhi.h> | ||
19 | #include <linux/mtd/physmap.h> | 19 | #include <linux/mtd/physmap.h> |
20 | #include <linux/mtd/sh_flctl.h> | 20 | #include <linux/mtd/sh_flctl.h> |
21 | #include <linux/delay.h> | 21 | #include <linux/delay.h> |
@@ -423,7 +423,7 @@ static struct resource sdhi0_cn3_resources[] = { | |||
423 | [0] = { | 423 | [0] = { |
424 | .name = "SDHI0", | 424 | .name = "SDHI0", |
425 | .start = 0x04ce0000, | 425 | .start = 0x04ce0000, |
426 | .end = 0x04ce01ff, | 426 | .end = 0x04ce00ff, |
427 | .flags = IORESOURCE_MEM, | 427 | .flags = IORESOURCE_MEM, |
428 | }, | 428 | }, |
429 | [1] = { | 429 | [1] = { |
@@ -453,7 +453,7 @@ static struct resource sdhi1_cn7_resources[] = { | |||
453 | [0] = { | 453 | [0] = { |
454 | .name = "SDHI1", | 454 | .name = "SDHI1", |
455 | .start = 0x04cf0000, | 455 | .start = 0x04cf0000, |
456 | .end = 0x04cf01ff, | 456 | .end = 0x04cf00ff, |
457 | .flags = IORESOURCE_MEM, | 457 | .flags = IORESOURCE_MEM, |
458 | }, | 458 | }, |
459 | [1] = { | 459 | [1] = { |
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c index d7ac5af9d102..311bcebdbd07 100644 --- a/arch/sh/boards/mach-cayman/irq.c +++ b/arch/sh/boards/mach-cayman/irq.c | |||
@@ -149,8 +149,8 @@ void init_cayman_irq(void) | |||
149 | } | 149 | } |
150 | 150 | ||
151 | for (i = 0; i < NR_EXT_IRQS; i++) { | 151 | for (i = 0; i < NR_EXT_IRQS; i++) { |
152 | set_irq_chip_and_handler(START_EXT_IRQS + i, &cayman_irq_type, | 152 | irq_set_chip_and_handler(START_EXT_IRQS + i, |
153 | handle_level_irq); | 153 | &cayman_irq_type, handle_level_irq); |
154 | } | 154 | } |
155 | 155 | ||
156 | /* Setup the SMSC interrupt */ | 156 | /* Setup the SMSC interrupt */ |
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c index 72e7ac9549da..78cf2ab89d7a 100644 --- a/arch/sh/boards/mach-dreamcast/irq.c +++ b/arch/sh/boards/mach-dreamcast/irq.c | |||
@@ -161,7 +161,6 @@ void systemasic_irq_init(void) | |||
161 | return; | 161 | return; |
162 | } | 162 | } |
163 | 163 | ||
164 | set_irq_chip_and_handler(i, &systemasic_int, | 164 | irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq); |
165 | handle_level_irq); | ||
166 | } | 165 | } |
167 | } | 166 | } |
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c index e44480ce2ea8..fd4ff25f23b2 100644 --- a/arch/sh/boards/mach-ecovec24/setup.c +++ b/arch/sh/boards/mach-ecovec24/setup.c | |||
@@ -11,9 +11,9 @@ | |||
11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
12 | #include <linux/device.h> | 12 | #include <linux/device.h> |
13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
14 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
15 | #include <linux/mmc/host.h> | 14 | #include <linux/mmc/host.h> |
16 | #include <linux/mmc/sh_mmcif.h> | 15 | #include <linux/mmc/sh_mmcif.h> |
16 | #include <linux/mmc/sh_mobile_sdhi.h> | ||
17 | #include <linux/mtd/physmap.h> | 17 | #include <linux/mtd/physmap.h> |
18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
@@ -464,7 +464,7 @@ static struct i2c_board_info ts_i2c_clients = { | |||
464 | .irq = IRQ0, | 464 | .irq = IRQ0, |
465 | }; | 465 | }; |
466 | 466 | ||
467 | #ifdef CONFIG_MFD_SH_MOBILE_SDHI | 467 | #if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE) |
468 | /* SDHI0 */ | 468 | /* SDHI0 */ |
469 | static void sdhi0_set_pwr(struct platform_device *pdev, int state) | 469 | static void sdhi0_set_pwr(struct platform_device *pdev, int state) |
470 | { | 470 | { |
@@ -482,7 +482,7 @@ static struct resource sdhi0_resources[] = { | |||
482 | [0] = { | 482 | [0] = { |
483 | .name = "SDHI0", | 483 | .name = "SDHI0", |
484 | .start = 0x04ce0000, | 484 | .start = 0x04ce0000, |
485 | .end = 0x04ce01ff, | 485 | .end = 0x04ce00ff, |
486 | .flags = IORESOURCE_MEM, | 486 | .flags = IORESOURCE_MEM, |
487 | }, | 487 | }, |
488 | [1] = { | 488 | [1] = { |
@@ -522,7 +522,7 @@ static struct resource sdhi1_resources[] = { | |||
522 | [0] = { | 522 | [0] = { |
523 | .name = "SDHI1", | 523 | .name = "SDHI1", |
524 | .start = 0x04cf0000, | 524 | .start = 0x04cf0000, |
525 | .end = 0x04cf01ff, | 525 | .end = 0x04cf00ff, |
526 | .flags = IORESOURCE_MEM, | 526 | .flags = IORESOURCE_MEM, |
527 | }, | 527 | }, |
528 | [1] = { | 528 | [1] = { |
@@ -880,7 +880,7 @@ static struct platform_device *ecovec_devices[] __initdata = { | |||
880 | &ceu0_device, | 880 | &ceu0_device, |
881 | &ceu1_device, | 881 | &ceu1_device, |
882 | &keysc_device, | 882 | &keysc_device, |
883 | #ifdef CONFIG_MFD_SH_MOBILE_SDHI | 883 | #if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE) |
884 | &sdhi0_device, | 884 | &sdhi0_device, |
885 | #if !defined(CONFIG_MMC_SH_MMCIF) | 885 | #if !defined(CONFIG_MMC_SH_MMCIF) |
886 | &sdhi1_device, | 886 | &sdhi1_device, |
@@ -1102,7 +1102,7 @@ static int __init arch_setup(void) | |||
1102 | 1102 | ||
1103 | /* enable TouchScreen */ | 1103 | /* enable TouchScreen */ |
1104 | i2c_register_board_info(0, &ts_i2c_clients, 1); | 1104 | i2c_register_board_info(0, &ts_i2c_clients, 1); |
1105 | set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); | 1105 | irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); |
1106 | } | 1106 | } |
1107 | 1107 | ||
1108 | /* enable CEU0 */ | 1108 | /* enable CEU0 */ |
@@ -1162,7 +1162,7 @@ static int __init arch_setup(void) | |||
1162 | gpio_direction_input(GPIO_PTR5); | 1162 | gpio_direction_input(GPIO_PTR5); |
1163 | gpio_direction_input(GPIO_PTR6); | 1163 | gpio_direction_input(GPIO_PTR6); |
1164 | 1164 | ||
1165 | #ifdef CONFIG_MFD_SH_MOBILE_SDHI | 1165 | #if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE) |
1166 | /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */ | 1166 | /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */ |
1167 | gpio_request(GPIO_FN_SDHI0CD, NULL); | 1167 | gpio_request(GPIO_FN_SDHI0CD, NULL); |
1168 | gpio_request(GPIO_FN_SDHI0WP, NULL); | 1168 | gpio_request(GPIO_FN_SDHI0WP, NULL); |
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c index 7504daaa85da..8b4abbbd1477 100644 --- a/arch/sh/boards/mach-kfr2r09/setup.c +++ b/arch/sh/boards/mach-kfr2r09/setup.c | |||
@@ -10,8 +10,8 @@ | |||
10 | #include <linux/init.h> | 10 | #include <linux/init.h> |
11 | #include <linux/platform_device.h> | 11 | #include <linux/platform_device.h> |
12 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
13 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
14 | #include <linux/mmc/host.h> | 13 | #include <linux/mmc/host.h> |
14 | #include <linux/mmc/sh_mobile_sdhi.h> | ||
15 | #include <linux/mfd/tmio.h> | 15 | #include <linux/mfd/tmio.h> |
16 | #include <linux/mtd/physmap.h> | 16 | #include <linux/mtd/physmap.h> |
17 | #include <linux/mtd/onenand.h> | 17 | #include <linux/mtd/onenand.h> |
@@ -354,7 +354,7 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = { | |||
354 | [0] = { | 354 | [0] = { |
355 | .name = "SDHI0", | 355 | .name = "SDHI0", |
356 | .start = 0x04ce0000, | 356 | .start = 0x04ce0000, |
357 | .end = 0x04ce01ff, | 357 | .end = 0x04ce00ff, |
358 | .flags = IORESOURCE_MEM, | 358 | .flags = IORESOURCE_MEM, |
359 | }, | 359 | }, |
360 | [1] = { | 360 | [1] = { |
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c index c35001fd9032..4fb00369f0e2 100644 --- a/arch/sh/boards/mach-microdev/irq.c +++ b/arch/sh/boards/mach-microdev/irq.c | |||
@@ -117,7 +117,7 @@ static struct irq_chip microdev_irq_type = { | |||
117 | static void __init make_microdev_irq(unsigned int irq) | 117 | static void __init make_microdev_irq(unsigned int irq) |
118 | { | 118 | { |
119 | disable_irq_nosync(irq); | 119 | disable_irq_nosync(irq); |
120 | set_irq_chip_and_handler(irq, µdev_irq_type, handle_level_irq); | 120 | irq_set_chip_and_handler(irq, µdev_irq_type, handle_level_irq); |
121 | disable_microdev_irq(irq_get_irq_data(irq)); | 121 | disable_microdev_irq(irq_get_irq_data(irq)); |
122 | } | 122 | } |
123 | 123 | ||
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c index 03a7ffe729d5..184fde169132 100644 --- a/arch/sh/boards/mach-migor/setup.c +++ b/arch/sh/boards/mach-migor/setup.c | |||
@@ -12,8 +12,8 @@ | |||
12 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
13 | #include <linux/input.h> | 13 | #include <linux/input.h> |
14 | #include <linux/input/sh_keysc.h> | 14 | #include <linux/input/sh_keysc.h> |
15 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
16 | #include <linux/mmc/host.h> | 15 | #include <linux/mmc/host.h> |
16 | #include <linux/mmc/sh_mobile_sdhi.h> | ||
17 | #include <linux/mtd/physmap.h> | 17 | #include <linux/mtd/physmap.h> |
18 | #include <linux/mtd/nand.h> | 18 | #include <linux/mtd/nand.h> |
19 | #include <linux/i2c.h> | 19 | #include <linux/i2c.h> |
@@ -399,7 +399,7 @@ static struct resource sdhi_cn9_resources[] = { | |||
399 | [0] = { | 399 | [0] = { |
400 | .name = "SDHI", | 400 | .name = "SDHI", |
401 | .start = 0x04ce0000, | 401 | .start = 0x04ce0000, |
402 | .end = 0x04ce01ff, | 402 | .end = 0x04ce00ff, |
403 | .flags = IORESOURCE_MEM, | 403 | .flags = IORESOURCE_MEM, |
404 | }, | 404 | }, |
405 | [1] = { | 405 | [1] = { |
diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c index 9070d7e60704..0db058e709e9 100644 --- a/arch/sh/boards/mach-se/7206/irq.c +++ b/arch/sh/boards/mach-se/7206/irq.c | |||
@@ -92,9 +92,8 @@ static void eoi_se7206_irq(struct irq_data *data) | |||
92 | { | 92 | { |
93 | unsigned short sts0,sts1; | 93 | unsigned short sts0,sts1; |
94 | unsigned int irq = data->irq; | 94 | unsigned int irq = data->irq; |
95 | struct irq_desc *desc = irq_to_desc(irq); | ||
96 | 95 | ||
97 | if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | 96 | if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data)) |
98 | enable_se7206_irq(data); | 97 | enable_se7206_irq(data); |
99 | /* FPGA isr clear */ | 98 | /* FPGA isr clear */ |
100 | sts0 = __raw_readw(INTSTS0); | 99 | sts0 = __raw_readw(INTSTS0); |
@@ -126,7 +125,7 @@ static struct irq_chip se7206_irq_chip __read_mostly = { | |||
126 | static void make_se7206_irq(unsigned int irq) | 125 | static void make_se7206_irq(unsigned int irq) |
127 | { | 126 | { |
128 | disable_irq_nosync(irq); | 127 | disable_irq_nosync(irq); |
129 | set_irq_chip_and_handler_name(irq, &se7206_irq_chip, | 128 | irq_set_chip_and_handler_name(irq, &se7206_irq_chip, |
130 | handle_level_irq, "level"); | 129 | handle_level_irq, "level"); |
131 | disable_se7206_irq(irq_get_irq_data(irq)); | 130 | disable_se7206_irq(irq_get_irq_data(irq)); |
132 | } | 131 | } |
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c index 76255a19417f..fd45ffc48340 100644 --- a/arch/sh/boards/mach-se/7343/irq.c +++ b/arch/sh/boards/mach-se/7343/irq.c | |||
@@ -67,19 +67,20 @@ void __init init_7343se_IRQ(void) | |||
67 | return; | 67 | return; |
68 | se7343_fpga_irq[i] = irq; | 68 | se7343_fpga_irq[i] = irq; |
69 | 69 | ||
70 | set_irq_chip_and_handler_name(se7343_fpga_irq[i], | 70 | irq_set_chip_and_handler_name(se7343_fpga_irq[i], |
71 | &se7343_irq_chip, | 71 | &se7343_irq_chip, |
72 | handle_level_irq, "level"); | 72 | handle_level_irq, |
73 | "level"); | ||
73 | 74 | ||
74 | set_irq_chip_data(se7343_fpga_irq[i], (void *)i); | 75 | irq_set_chip_data(se7343_fpga_irq[i], (void *)i); |
75 | } | 76 | } |
76 | 77 | ||
77 | set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux); | 78 | irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux); |
78 | set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); | 79 | irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); |
79 | set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux); | 80 | irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux); |
80 | set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); | 81 | irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); |
81 | set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux); | 82 | irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux); |
82 | set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); | 83 | irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); |
83 | set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux); | 84 | irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux); |
84 | set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); | 85 | irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); |
85 | } | 86 | } |
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c index c013f95628ed..aac92f21ebd2 100644 --- a/arch/sh/boards/mach-se/7722/irq.c +++ b/arch/sh/boards/mach-se/7722/irq.c | |||
@@ -67,16 +67,17 @@ void __init init_se7722_IRQ(void) | |||
67 | return; | 67 | return; |
68 | se7722_fpga_irq[i] = irq; | 68 | se7722_fpga_irq[i] = irq; |
69 | 69 | ||
70 | set_irq_chip_and_handler_name(se7722_fpga_irq[i], | 70 | irq_set_chip_and_handler_name(se7722_fpga_irq[i], |
71 | &se7722_irq_chip, | 71 | &se7722_irq_chip, |
72 | handle_level_irq, "level"); | 72 | handle_level_irq, |
73 | "level"); | ||
73 | 74 | ||
74 | set_irq_chip_data(se7722_fpga_irq[i], (void *)i); | 75 | irq_set_chip_data(se7722_fpga_irq[i], (void *)i); |
75 | } | 76 | } |
76 | 77 | ||
77 | set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux); | 78 | irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux); |
78 | set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); | 79 | irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); |
79 | 80 | ||
80 | set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux); | 81 | irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux); |
81 | set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); | 82 | irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); |
82 | } | 83 | } |
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c index 5bd87c22b65b..c6342ce7768d 100644 --- a/arch/sh/boards/mach-se/7724/irq.c +++ b/arch/sh/boards/mach-se/7724/irq.c | |||
@@ -140,17 +140,16 @@ void __init init_se7724_IRQ(void) | |||
140 | return; | 140 | return; |
141 | } | 141 | } |
142 | 142 | ||
143 | set_irq_chip_and_handler_name(irq, | 143 | irq_set_chip_and_handler_name(irq, &se7724_irq_chip, |
144 | &se7724_irq_chip, | ||
145 | handle_level_irq, "level"); | 144 | handle_level_irq, "level"); |
146 | } | 145 | } |
147 | 146 | ||
148 | set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux); | 147 | irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux); |
149 | set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); | 148 | irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); |
150 | 149 | ||
151 | set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux); | 150 | irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux); |
152 | set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); | 151 | irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); |
153 | 152 | ||
154 | set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux); | 153 | irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux); |
155 | set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW); | 154 | irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW); |
156 | } | 155 | } |
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c index c8bcf6a19b55..12357671023e 100644 --- a/arch/sh/boards/mach-se/7724/setup.c +++ b/arch/sh/boards/mach-se/7724/setup.c | |||
@@ -14,8 +14,8 @@ | |||
14 | #include <linux/device.h> | 14 | #include <linux/device.h> |
15 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/mfd/sh_mobile_sdhi.h> | ||
18 | #include <linux/mmc/host.h> | 17 | #include <linux/mmc/host.h> |
18 | #include <linux/mmc/sh_mobile_sdhi.h> | ||
19 | #include <linux/mtd/physmap.h> | 19 | #include <linux/mtd/physmap.h> |
20 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
21 | #include <linux/smc91x.h> | 21 | #include <linux/smc91x.h> |
@@ -456,7 +456,7 @@ static struct resource sdhi0_cn7_resources[] = { | |||
456 | [0] = { | 456 | [0] = { |
457 | .name = "SDHI0", | 457 | .name = "SDHI0", |
458 | .start = 0x04ce0000, | 458 | .start = 0x04ce0000, |
459 | .end = 0x04ce01ff, | 459 | .end = 0x04ce00ff, |
460 | .flags = IORESOURCE_MEM, | 460 | .flags = IORESOURCE_MEM, |
461 | }, | 461 | }, |
462 | [1] = { | 462 | [1] = { |
@@ -488,7 +488,7 @@ static struct resource sdhi1_cn8_resources[] = { | |||
488 | [0] = { | 488 | [0] = { |
489 | .name = "SDHI1", | 489 | .name = "SDHI1", |
490 | .start = 0x04cf0000, | 490 | .start = 0x04cf0000, |
491 | .end = 0x04cf01ff, | 491 | .end = 0x04cf00ff, |
492 | .flags = IORESOURCE_MEM, | 492 | .flags = IORESOURCE_MEM, |
493 | }, | 493 | }, |
494 | [1] = { | 494 | [1] = { |
diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c index 239e74066253..f33b2b57019c 100644 --- a/arch/sh/boards/mach-x3proto/gpio.c +++ b/arch/sh/boards/mach-x3proto/gpio.c | |||
@@ -102,8 +102,8 @@ int __init x3proto_gpio_setup(void) | |||
102 | 102 | ||
103 | spin_lock_irqsave(&x3proto_gpio_lock, flags); | 103 | spin_lock_irqsave(&x3proto_gpio_lock, flags); |
104 | x3proto_gpio_irq_map[i] = irq; | 104 | x3proto_gpio_irq_map[i] = irq; |
105 | set_irq_chip_and_handler_name(irq, &dummy_irq_chip, | 105 | irq_set_chip_and_handler_name(irq, &dummy_irq_chip, |
106 | handle_simple_irq, "gpio"); | 106 | handle_simple_irq, "gpio"); |
107 | spin_unlock_irqrestore(&x3proto_gpio_lock, flags); | 107 | spin_unlock_irqrestore(&x3proto_gpio_lock, flags); |
108 | } | 108 | } |
109 | 109 | ||
@@ -113,8 +113,8 @@ int __init x3proto_gpio_setup(void) | |||
113 | x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio, | 113 | x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio, |
114 | ilsel); | 114 | ilsel); |
115 | 115 | ||
116 | set_irq_chained_handler(ilsel, x3proto_gpio_irq_handler); | 116 | irq_set_chained_handler(ilsel, x3proto_gpio_irq_handler); |
117 | set_irq_wake(ilsel, 1); | 117 | irq_set_irq_wake(ilsel, 1); |
118 | 118 | ||
119 | return 0; | 119 | return 0; |
120 | 120 | ||
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c index 177a10b25cad..eb4ea4d44d59 100644 --- a/arch/sh/cchips/hd6446x/hd64461.c +++ b/arch/sh/cchips/hd6446x/hd64461.c | |||
@@ -107,12 +107,12 @@ int __init setup_hd64461(void) | |||
107 | return -EINVAL; | 107 | return -EINVAL; |
108 | } | 108 | } |
109 | 109 | ||
110 | set_irq_chip_and_handler(i, &hd64461_irq_chip, | 110 | irq_set_chip_and_handler(i, &hd64461_irq_chip, |
111 | handle_level_irq); | 111 | handle_level_irq); |
112 | } | 112 | } |
113 | 113 | ||
114 | set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); | 114 | irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux); |
115 | set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); | 115 | irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW); |
116 | 116 | ||
117 | #ifdef CONFIG_HD64461_ENABLER | 117 | #ifdef CONFIG_HD64461_ENABLER |
118 | printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); | 118 | printk(KERN_INFO "HD64461: enabling PCMCIA devices\n"); |
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c index 32c825c9488e..39b6a24c159d 100644 --- a/arch/sh/kernel/cpu/irq/imask.c +++ b/arch/sh/kernel/cpu/irq/imask.c | |||
@@ -80,6 +80,6 @@ static struct irq_chip imask_irq_chip = { | |||
80 | 80 | ||
81 | void make_imask_irq(unsigned int irq) | 81 | void make_imask_irq(unsigned int irq) |
82 | { | 82 | { |
83 | set_irq_chip_and_handler_name(irq, &imask_irq_chip, | 83 | irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq, |
84 | handle_level_irq, "level"); | 84 | "level"); |
85 | } | 85 | } |
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c index 5af48f8357e5..9e056a3a0c73 100644 --- a/arch/sh/kernel/cpu/irq/intc-sh5.c +++ b/arch/sh/kernel/cpu/irq/intc-sh5.c | |||
@@ -135,7 +135,7 @@ void __init plat_irq_setup(void) | |||
135 | 135 | ||
136 | /* Set default: per-line enable/disable, priority driven ack/eoi */ | 136 | /* Set default: per-line enable/disable, priority driven ack/eoi */ |
137 | for (i = 0; i < NR_INTC_IRQS; i++) | 137 | for (i = 0; i < NR_INTC_IRQS; i++) |
138 | set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); | 138 | irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq); |
139 | 139 | ||
140 | 140 | ||
141 | /* Disable all interrupts and set all priorities to 0 to avoid trouble */ | 141 | /* Disable all interrupts and set all priorities to 0 to avoid trouble */ |
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c index 7516c35ee514..5de6dff5c21b 100644 --- a/arch/sh/kernel/cpu/irq/ipr.c +++ b/arch/sh/kernel/cpu/irq/ipr.c | |||
@@ -74,9 +74,9 @@ void register_ipr_controller(struct ipr_desc *desc) | |||
74 | } | 74 | } |
75 | 75 | ||
76 | disable_irq_nosync(p->irq); | 76 | disable_irq_nosync(p->irq); |
77 | set_irq_chip_and_handler_name(p->irq, &desc->chip, | 77 | irq_set_chip_and_handler_name(p->irq, &desc->chip, |
78 | handle_level_irq, "level"); | 78 | handle_level_irq, "level"); |
79 | set_irq_chip_data(p->irq, p); | 79 | irq_set_chip_data(p->irq, p); |
80 | disable_ipr_irq(irq_get_irq_data(p->irq)); | 80 | disable_ipr_irq(irq_get_irq_data(p->irq)); |
81 | } | 81 | } |
82 | } | 82 | } |
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index f766e6bf370e..e560d102215a 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig | |||
@@ -51,7 +51,8 @@ config SPARC64 | |||
51 | select HAVE_PERF_EVENTS | 51 | select HAVE_PERF_EVENTS |
52 | select PERF_USE_VMALLOC | 52 | select PERF_USE_VMALLOC |
53 | select HAVE_GENERIC_HARDIRQS | 53 | select HAVE_GENERIC_HARDIRQS |
54 | select GENERIC_HARDIRQS_NO_DEPRECATED | 54 | select GENERIC_IRQ_SHOW |
55 | select IRQ_PREFLOW_FASTEOI | ||
55 | 56 | ||
56 | config ARCH_DEFCONFIG | 57 | config ARCH_DEFCONFIG |
57 | string | 58 | string |
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h index 2f475d7c0b53..9d897b6db983 100644 --- a/arch/sparc/include/asm/unistd.h +++ b/arch/sparc/include/asm/unistd.h | |||
@@ -403,8 +403,9 @@ | |||
403 | #define __NR_name_to_handle_at 332 | 403 | #define __NR_name_to_handle_at 332 |
404 | #define __NR_open_by_handle_at 333 | 404 | #define __NR_open_by_handle_at 333 |
405 | #define __NR_clock_adjtime 334 | 405 | #define __NR_clock_adjtime 334 |
406 | #define __NR_syncfs 335 | ||
406 | 407 | ||
407 | #define NR_syscalls 335 | 408 | #define NR_syscalls 336 |
408 | 409 | ||
409 | #ifdef __32bit_syscall_numbers__ | 410 | #ifdef __32bit_syscall_numbers__ |
410 | /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants, | 411 | /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants, |
diff --git a/arch/sparc/kernel/auxio_64.c b/arch/sparc/kernel/auxio_64.c index 2abace076c7d..773091ac71a3 100644 --- a/arch/sparc/kernel/auxio_64.c +++ b/arch/sparc/kernel/auxio_64.c | |||
@@ -93,7 +93,7 @@ void auxio_set_lte(int on) | |||
93 | } | 93 | } |
94 | EXPORT_SYMBOL(auxio_set_lte); | 94 | EXPORT_SYMBOL(auxio_set_lte); |
95 | 95 | ||
96 | static struct of_device_id __initdata auxio_match[] = { | 96 | static const struct of_device_id auxio_match[] = { |
97 | { | 97 | { |
98 | .name = "auxio", | 98 | .name = "auxio", |
99 | }, | 99 | }, |
diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c index 136d3718a74a..7eef3f741963 100644 --- a/arch/sparc/kernel/central.c +++ b/arch/sparc/kernel/central.c | |||
@@ -140,7 +140,7 @@ out_free: | |||
140 | goto out; | 140 | goto out; |
141 | } | 141 | } |
142 | 142 | ||
143 | static struct of_device_id __initdata clock_board_match[] = { | 143 | static const struct of_device_id clock_board_match[] = { |
144 | { | 144 | { |
145 | .name = "clock-board", | 145 | .name = "clock-board", |
146 | }, | 146 | }, |
@@ -245,7 +245,7 @@ out_free: | |||
245 | goto out; | 245 | goto out; |
246 | } | 246 | } |
247 | 247 | ||
248 | static struct of_device_id __initdata fhc_match[] = { | 248 | static const struct of_device_id fhc_match[] = { |
249 | { | 249 | { |
250 | .name = "fhc", | 250 | .name = "fhc", |
251 | }, | 251 | }, |
diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c index 4a700f4b79ce..3add4de8a1a9 100644 --- a/arch/sparc/kernel/ds.c +++ b/arch/sparc/kernel/ds.c | |||
@@ -1218,7 +1218,7 @@ static int ds_remove(struct vio_dev *vdev) | |||
1218 | return 0; | 1218 | return 0; |
1219 | } | 1219 | } |
1220 | 1220 | ||
1221 | static struct vio_device_id __initdata ds_match[] = { | 1221 | static const struct vio_device_id ds_match[] = { |
1222 | { | 1222 | { |
1223 | .type = "domain-services-port", | 1223 | .type = "domain-services-port", |
1224 | }, | 1224 | }, |
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S index 1504df8ddf70..906ee3e24cc9 100644 --- a/arch/sparc/kernel/entry.S +++ b/arch/sparc/kernel/entry.S | |||
@@ -1283,7 +1283,7 @@ linux_syscall_trace: | |||
1283 | .globl ret_from_fork | 1283 | .globl ret_from_fork |
1284 | ret_from_fork: | 1284 | ret_from_fork: |
1285 | call schedule_tail | 1285 | call schedule_tail |
1286 | mov %g3, %o0 | 1286 | ld [%g3 + TI_TASK], %o0 |
1287 | b ret_sys_call | 1287 | b ret_sys_call |
1288 | ld [%sp + STACKFRAME_SZ + PT_I0], %o0 | 1288 | ld [%sp + STACKFRAME_SZ + PT_I0], %o0 |
1289 | 1289 | ||
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index eb16e3b8a2dd..b1d275ce3435 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c | |||
@@ -162,47 +162,14 @@ void irq_free(unsigned int irq) | |||
162 | /* | 162 | /* |
163 | * /proc/interrupts printing: | 163 | * /proc/interrupts printing: |
164 | */ | 164 | */ |
165 | 165 | int arch_show_interrupts(struct seq_file *p, int prec) | |
166 | int show_interrupts(struct seq_file *p, void *v) | ||
167 | { | 166 | { |
168 | int i = *(loff_t *) v, j; | 167 | int j; |
169 | struct irqaction * action; | ||
170 | unsigned long flags; | ||
171 | 168 | ||
172 | if (i == 0) { | 169 | seq_printf(p, "NMI: "); |
173 | seq_printf(p, " "); | 170 | for_each_online_cpu(j) |
174 | for_each_online_cpu(j) | 171 | seq_printf(p, "%10u ", cpu_data(j).__nmi_count); |
175 | seq_printf(p, "CPU%d ",j); | 172 | seq_printf(p, " Non-maskable interrupts\n"); |
176 | seq_putc(p, '\n'); | ||
177 | } | ||
178 | |||
179 | if (i < NR_IRQS) { | ||
180 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
181 | action = irq_desc[i].action; | ||
182 | if (!action) | ||
183 | goto skip; | ||
184 | seq_printf(p, "%3d: ",i); | ||
185 | #ifndef CONFIG_SMP | ||
186 | seq_printf(p, "%10u ", kstat_irqs(i)); | ||
187 | #else | ||
188 | for_each_online_cpu(j) | ||
189 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | ||
190 | #endif | ||
191 | seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name); | ||
192 | seq_printf(p, " %s", action->name); | ||
193 | |||
194 | for (action=action->next; action; action = action->next) | ||
195 | seq_printf(p, ", %s", action->name); | ||
196 | |||
197 | seq_putc(p, '\n'); | ||
198 | skip: | ||
199 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
200 | } else if (i == NR_IRQS) { | ||
201 | seq_printf(p, "NMI: "); | ||
202 | for_each_online_cpu(j) | ||
203 | seq_printf(p, "%10u ", cpu_data(j).__nmi_count); | ||
204 | seq_printf(p, " Non-maskable interrupts\n"); | ||
205 | } | ||
206 | return 0; | 173 | return 0; |
207 | } | 174 | } |
208 | 175 | ||
@@ -344,10 +311,6 @@ static void sun4u_irq_disable(struct irq_data *data) | |||
344 | static void sun4u_irq_eoi(struct irq_data *data) | 311 | static void sun4u_irq_eoi(struct irq_data *data) |
345 | { | 312 | { |
346 | struct irq_handler_data *handler_data = data->handler_data; | 313 | struct irq_handler_data *handler_data = data->handler_data; |
347 | struct irq_desc *desc = irq_desc + data->irq; | ||
348 | |||
349 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
350 | return; | ||
351 | 314 | ||
352 | if (likely(handler_data)) | 315 | if (likely(handler_data)) |
353 | upa_writeq(ICLR_IDLE, handler_data->iclr); | 316 | upa_writeq(ICLR_IDLE, handler_data->iclr); |
@@ -402,12 +365,8 @@ static void sun4v_irq_disable(struct irq_data *data) | |||
402 | static void sun4v_irq_eoi(struct irq_data *data) | 365 | static void sun4v_irq_eoi(struct irq_data *data) |
403 | { | 366 | { |
404 | unsigned int ino = irq_table[data->irq].dev_ino; | 367 | unsigned int ino = irq_table[data->irq].dev_ino; |
405 | struct irq_desc *desc = irq_desc + data->irq; | ||
406 | int err; | 368 | int err; |
407 | 369 | ||
408 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
409 | return; | ||
410 | |||
411 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); | 370 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
412 | if (err != HV_EOK) | 371 | if (err != HV_EOK) |
413 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | 372 | printk(KERN_ERR "sun4v_intr_setstate(%x): " |
@@ -481,13 +440,9 @@ static void sun4v_virq_disable(struct irq_data *data) | |||
481 | 440 | ||
482 | static void sun4v_virq_eoi(struct irq_data *data) | 441 | static void sun4v_virq_eoi(struct irq_data *data) |
483 | { | 442 | { |
484 | struct irq_desc *desc = irq_desc + data->irq; | ||
485 | unsigned long dev_handle, dev_ino; | 443 | unsigned long dev_handle, dev_ino; |
486 | int err; | 444 | int err; |
487 | 445 | ||
488 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
489 | return; | ||
490 | |||
491 | dev_handle = irq_table[data->irq].dev_handle; | 446 | dev_handle = irq_table[data->irq].dev_handle; |
492 | dev_ino = irq_table[data->irq].dev_ino; | 447 | dev_ino = irq_table[data->irq].dev_ino; |
493 | 448 | ||
@@ -505,6 +460,7 @@ static struct irq_chip sun4u_irq = { | |||
505 | .irq_disable = sun4u_irq_disable, | 460 | .irq_disable = sun4u_irq_disable, |
506 | .irq_eoi = sun4u_irq_eoi, | 461 | .irq_eoi = sun4u_irq_eoi, |
507 | .irq_set_affinity = sun4u_set_affinity, | 462 | .irq_set_affinity = sun4u_set_affinity, |
463 | .flags = IRQCHIP_EOI_IF_HANDLED, | ||
508 | }; | 464 | }; |
509 | 465 | ||
510 | static struct irq_chip sun4v_irq = { | 466 | static struct irq_chip sun4v_irq = { |
@@ -513,6 +469,7 @@ static struct irq_chip sun4v_irq = { | |||
513 | .irq_disable = sun4v_irq_disable, | 469 | .irq_disable = sun4v_irq_disable, |
514 | .irq_eoi = sun4v_irq_eoi, | 470 | .irq_eoi = sun4v_irq_eoi, |
515 | .irq_set_affinity = sun4v_set_affinity, | 471 | .irq_set_affinity = sun4v_set_affinity, |
472 | .flags = IRQCHIP_EOI_IF_HANDLED, | ||
516 | }; | 473 | }; |
517 | 474 | ||
518 | static struct irq_chip sun4v_virq = { | 475 | static struct irq_chip sun4v_virq = { |
@@ -521,30 +478,28 @@ static struct irq_chip sun4v_virq = { | |||
521 | .irq_disable = sun4v_virq_disable, | 478 | .irq_disable = sun4v_virq_disable, |
522 | .irq_eoi = sun4v_virq_eoi, | 479 | .irq_eoi = sun4v_virq_eoi, |
523 | .irq_set_affinity = sun4v_virt_set_affinity, | 480 | .irq_set_affinity = sun4v_virt_set_affinity, |
481 | .flags = IRQCHIP_EOI_IF_HANDLED, | ||
524 | }; | 482 | }; |
525 | 483 | ||
526 | static void pre_flow_handler(unsigned int irq, struct irq_desc *desc) | 484 | static void pre_flow_handler(struct irq_data *d) |
527 | { | 485 | { |
528 | struct irq_handler_data *handler_data = get_irq_data(irq); | 486 | struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d); |
529 | unsigned int ino = irq_table[irq].dev_ino; | 487 | unsigned int ino = irq_table[d->irq].dev_ino; |
530 | 488 | ||
531 | handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2); | 489 | handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2); |
532 | |||
533 | handle_fasteoi_irq(irq, desc); | ||
534 | } | 490 | } |
535 | 491 | ||
536 | void irq_install_pre_handler(int irq, | 492 | void irq_install_pre_handler(int irq, |
537 | void (*func)(unsigned int, void *, void *), | 493 | void (*func)(unsigned int, void *, void *), |
538 | void *arg1, void *arg2) | 494 | void *arg1, void *arg2) |
539 | { | 495 | { |
540 | struct irq_handler_data *handler_data = get_irq_data(irq); | 496 | struct irq_handler_data *handler_data = irq_get_handler_data(irq); |
541 | struct irq_desc *desc = irq_desc + irq; | ||
542 | 497 | ||
543 | handler_data->pre_handler = func; | 498 | handler_data->pre_handler = func; |
544 | handler_data->arg1 = arg1; | 499 | handler_data->arg1 = arg1; |
545 | handler_data->arg2 = arg2; | 500 | handler_data->arg2 = arg2; |
546 | 501 | ||
547 | desc->handle_irq = pre_flow_handler; | 502 | __irq_set_preflow_handler(irq, pre_flow_handler); |
548 | } | 503 | } |
549 | 504 | ||
550 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) | 505 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
@@ -562,13 +517,11 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) | |||
562 | if (!irq) { | 517 | if (!irq) { |
563 | irq = irq_alloc(0, ino); | 518 | irq = irq_alloc(0, ino); |
564 | bucket_set_irq(__pa(bucket), irq); | 519 | bucket_set_irq(__pa(bucket), irq); |
565 | set_irq_chip_and_handler_name(irq, | 520 | irq_set_chip_and_handler_name(irq, &sun4u_irq, |
566 | &sun4u_irq, | 521 | handle_fasteoi_irq, "IVEC"); |
567 | handle_fasteoi_irq, | ||
568 | "IVEC"); | ||
569 | } | 522 | } |
570 | 523 | ||
571 | handler_data = get_irq_data(irq); | 524 | handler_data = irq_get_handler_data(irq); |
572 | if (unlikely(handler_data)) | 525 | if (unlikely(handler_data)) |
573 | goto out; | 526 | goto out; |
574 | 527 | ||
@@ -577,7 +530,7 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) | |||
577 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | 530 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
578 | prom_halt(); | 531 | prom_halt(); |
579 | } | 532 | } |
580 | set_irq_data(irq, handler_data); | 533 | irq_set_handler_data(irq, handler_data); |
581 | 534 | ||
582 | handler_data->imap = imap; | 535 | handler_data->imap = imap; |
583 | handler_data->iclr = iclr; | 536 | handler_data->iclr = iclr; |
@@ -600,12 +553,11 @@ static unsigned int sun4v_build_common(unsigned long sysino, | |||
600 | if (!irq) { | 553 | if (!irq) { |
601 | irq = irq_alloc(0, sysino); | 554 | irq = irq_alloc(0, sysino); |
602 | bucket_set_irq(__pa(bucket), irq); | 555 | bucket_set_irq(__pa(bucket), irq); |
603 | set_irq_chip_and_handler_name(irq, chip, | 556 | irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, |
604 | handle_fasteoi_irq, | ||
605 | "IVEC"); | 557 | "IVEC"); |
606 | } | 558 | } |
607 | 559 | ||
608 | handler_data = get_irq_data(irq); | 560 | handler_data = irq_get_handler_data(irq); |
609 | if (unlikely(handler_data)) | 561 | if (unlikely(handler_data)) |
610 | goto out; | 562 | goto out; |
611 | 563 | ||
@@ -614,7 +566,7 @@ static unsigned int sun4v_build_common(unsigned long sysino, | |||
614 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | 566 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
615 | prom_halt(); | 567 | prom_halt(); |
616 | } | 568 | } |
617 | set_irq_data(irq, handler_data); | 569 | irq_set_handler_data(irq, handler_data); |
618 | 570 | ||
619 | /* Catch accidental accesses to these things. IMAP/ICLR handling | 571 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
620 | * is done by hypervisor calls on sun4v platforms, not by direct | 572 | * is done by hypervisor calls on sun4v platforms, not by direct |
@@ -639,7 +591,6 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |||
639 | struct irq_handler_data *handler_data; | 591 | struct irq_handler_data *handler_data; |
640 | unsigned long hv_err, cookie; | 592 | unsigned long hv_err, cookie; |
641 | struct ino_bucket *bucket; | 593 | struct ino_bucket *bucket; |
642 | struct irq_desc *desc; | ||
643 | unsigned int irq; | 594 | unsigned int irq; |
644 | 595 | ||
645 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); | 596 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); |
@@ -660,8 +611,7 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |||
660 | irq = irq_alloc(devhandle, devino); | 611 | irq = irq_alloc(devhandle, devino); |
661 | bucket_set_irq(__pa(bucket), irq); | 612 | bucket_set_irq(__pa(bucket), irq); |
662 | 613 | ||
663 | set_irq_chip_and_handler_name(irq, &sun4v_virq, | 614 | irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq, |
664 | handle_fasteoi_irq, | ||
665 | "IVEC"); | 615 | "IVEC"); |
666 | 616 | ||
667 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); | 617 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
@@ -672,10 +622,8 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |||
672 | * especially wrt. locking, we do not let request_irq() enable | 622 | * especially wrt. locking, we do not let request_irq() enable |
673 | * the interrupt. | 623 | * the interrupt. |
674 | */ | 624 | */ |
675 | desc = irq_desc + irq; | 625 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
676 | desc->status |= IRQ_NOAUTOEN; | 626 | irq_set_handler_data(irq, handler_data); |
677 | |||
678 | set_irq_data(irq, handler_data); | ||
679 | 627 | ||
680 | /* Catch accidental accesses to these things. IMAP/ICLR handling | 628 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
681 | * is done by hypervisor calls on sun4v platforms, not by direct | 629 | * is done by hypervisor calls on sun4v platforms, not by direct |
@@ -734,7 +682,6 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs) | |||
734 | orig_sp = set_hardirq_stack(); | 682 | orig_sp = set_hardirq_stack(); |
735 | 683 | ||
736 | while (bucket_pa) { | 684 | while (bucket_pa) { |
737 | struct irq_desc *desc; | ||
738 | unsigned long next_pa; | 685 | unsigned long next_pa; |
739 | unsigned int irq; | 686 | unsigned int irq; |
740 | 687 | ||
@@ -742,10 +689,7 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs) | |||
742 | irq = bucket_get_irq(bucket_pa); | 689 | irq = bucket_get_irq(bucket_pa); |
743 | bucket_clear_chain_pa(bucket_pa); | 690 | bucket_clear_chain_pa(bucket_pa); |
744 | 691 | ||
745 | desc = irq_desc + irq; | 692 | generic_handle_irq(irq); |
746 | |||
747 | if (!(desc->status & IRQ_DISABLED)) | ||
748 | desc->handle_irq(irq, desc); | ||
749 | 693 | ||
750 | bucket_pa = next_pa; | 694 | bucket_pa = next_pa; |
751 | } | 695 | } |
@@ -788,19 +732,18 @@ void fixup_irqs(void) | |||
788 | unsigned int irq; | 732 | unsigned int irq; |
789 | 733 | ||
790 | for (irq = 0; irq < NR_IRQS; irq++) { | 734 | for (irq = 0; irq < NR_IRQS; irq++) { |
735 | struct irq_desc *desc = irq_to_desc(irq); | ||
736 | struct irq_data *data = irq_desc_get_irq_data(desc); | ||
791 | unsigned long flags; | 737 | unsigned long flags; |
792 | 738 | ||
793 | raw_spin_lock_irqsave(&irq_desc[irq].lock, flags); | 739 | raw_spin_lock_irqsave(&desc->lock, flags); |
794 | if (irq_desc[irq].action && | 740 | if (desc->action && !irqd_is_per_cpu(data)) { |
795 | !(irq_desc[irq].status & IRQ_PER_CPU)) { | ||
796 | struct irq_data *data = irq_get_irq_data(irq); | ||
797 | |||
798 | if (data->chip->irq_set_affinity) | 741 | if (data->chip->irq_set_affinity) |
799 | data->chip->irq_set_affinity(data, | 742 | data->chip->irq_set_affinity(data, |
800 | data->affinity, | 743 | data->affinity, |
801 | false); | 744 | false); |
802 | } | 745 | } |
803 | raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags); | 746 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
804 | } | 747 | } |
805 | 748 | ||
806 | tick_ops->disable_irq(); | 749 | tick_ops->disable_irq(); |
@@ -1038,5 +981,5 @@ void __init init_IRQ(void) | |||
1038 | : "i" (PSTATE_IE) | 981 | : "i" (PSTATE_IE) |
1039 | : "g1"); | 982 | : "g1"); |
1040 | 983 | ||
1041 | irq_desc[0].action = &timer_irq_action; | 984 | irq_to_desc(0)->action = &timer_irq_action; |
1042 | } | 985 | } |
diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c index 6addb914fcc8..56db06432ce9 100644 --- a/arch/sparc/kernel/mdesc.c +++ b/arch/sparc/kernel/mdesc.c | |||
@@ -107,7 +107,7 @@ static struct mdesc_handle * __init mdesc_memblock_alloc(unsigned int mdesc_size | |||
107 | return hp; | 107 | return hp; |
108 | } | 108 | } |
109 | 109 | ||
110 | static void mdesc_memblock_free(struct mdesc_handle *hp) | 110 | static void __init mdesc_memblock_free(struct mdesc_handle *hp) |
111 | { | 111 | { |
112 | unsigned int alloc_size; | 112 | unsigned int alloc_size; |
113 | unsigned long start; | 113 | unsigned long start; |
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index 44f41e312f73..713dc91020a6 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c | |||
@@ -1012,7 +1012,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |||
1012 | 1012 | ||
1013 | void arch_teardown_msi_irq(unsigned int irq) | 1013 | void arch_teardown_msi_irq(unsigned int irq) |
1014 | { | 1014 | { |
1015 | struct msi_desc *entry = get_irq_msi(irq); | 1015 | struct msi_desc *entry = irq_get_msi_desc(irq); |
1016 | struct pci_dev *pdev = entry->dev; | 1016 | struct pci_dev *pdev = entry->dev; |
1017 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | 1017 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1018 | 1018 | ||
diff --git a/arch/sparc/kernel/pci_fire.c b/arch/sparc/kernel/pci_fire.c index 3d70f8326efd..d29a32fcc5e4 100644 --- a/arch/sparc/kernel/pci_fire.c +++ b/arch/sparc/kernel/pci_fire.c | |||
@@ -496,7 +496,7 @@ out_err: | |||
496 | return err; | 496 | return err; |
497 | } | 497 | } |
498 | 498 | ||
499 | static struct of_device_id __initdata fire_match[] = { | 499 | static const struct of_device_id fire_match[] = { |
500 | { | 500 | { |
501 | .name = "pci", | 501 | .name = "pci", |
502 | .compatible = "pciex108e,80f0", | 502 | .compatible = "pciex108e,80f0", |
diff --git a/arch/sparc/kernel/pci_msi.c b/arch/sparc/kernel/pci_msi.c index 550e937720e7..30982e9ab626 100644 --- a/arch/sparc/kernel/pci_msi.c +++ b/arch/sparc/kernel/pci_msi.c | |||
@@ -30,13 +30,10 @@ static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie) | |||
30 | 30 | ||
31 | err = ops->dequeue_msi(pbm, msiqid, &head, &msi); | 31 | err = ops->dequeue_msi(pbm, msiqid, &head, &msi); |
32 | if (likely(err > 0)) { | 32 | if (likely(err > 0)) { |
33 | struct irq_desc *desc; | ||
34 | unsigned int irq; | 33 | unsigned int irq; |
35 | 34 | ||
36 | irq = pbm->msi_irq_table[msi - pbm->msi_first]; | 35 | irq = pbm->msi_irq_table[msi - pbm->msi_first]; |
37 | desc = irq_desc + irq; | 36 | generic_handle_irq(irq); |
38 | |||
39 | desc->handle_irq(irq, desc); | ||
40 | } | 37 | } |
41 | 38 | ||
42 | if (unlikely(err < 0)) | 39 | if (unlikely(err < 0)) |
@@ -136,8 +133,8 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p, | |||
136 | if (!*irq_p) | 133 | if (!*irq_p) |
137 | goto out_err; | 134 | goto out_err; |
138 | 135 | ||
139 | set_irq_chip_and_handler_name(*irq_p, &msi_irq, | 136 | irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq, |
140 | handle_simple_irq, "MSI"); | 137 | "MSI"); |
141 | 138 | ||
142 | err = alloc_msi(pbm); | 139 | err = alloc_msi(pbm); |
143 | if (unlikely(err < 0)) | 140 | if (unlikely(err < 0)) |
@@ -163,7 +160,7 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p, | |||
163 | } | 160 | } |
164 | msg.data = msi; | 161 | msg.data = msi; |
165 | 162 | ||
166 | set_irq_msi(*irq_p, entry); | 163 | irq_set_msi_desc(*irq_p, entry); |
167 | write_msi_msg(*irq_p, &msg); | 164 | write_msi_msg(*irq_p, &msg); |
168 | 165 | ||
169 | return 0; | 166 | return 0; |
@@ -172,7 +169,7 @@ out_msi_free: | |||
172 | free_msi(pbm, msi); | 169 | free_msi(pbm, msi); |
173 | 170 | ||
174 | out_irq_free: | 171 | out_irq_free: |
175 | set_irq_chip(*irq_p, NULL); | 172 | irq_set_chip(*irq_p, NULL); |
176 | irq_free(*irq_p); | 173 | irq_free(*irq_p); |
177 | *irq_p = 0; | 174 | *irq_p = 0; |
178 | 175 | ||
@@ -211,7 +208,7 @@ static void sparc64_teardown_msi_irq(unsigned int irq, | |||
211 | 208 | ||
212 | free_msi(pbm, msi_num); | 209 | free_msi(pbm, msi_num); |
213 | 210 | ||
214 | set_irq_chip(irq, NULL); | 211 | irq_set_chip(irq, NULL); |
215 | irq_free(irq); | 212 | irq_free(irq); |
216 | } | 213 | } |
217 | 214 | ||
diff --git a/arch/sparc/kernel/pci_psycho.c b/arch/sparc/kernel/pci_psycho.c index 56ee745064de..86ae08d9b6ee 100644 --- a/arch/sparc/kernel/pci_psycho.c +++ b/arch/sparc/kernel/pci_psycho.c | |||
@@ -592,7 +592,7 @@ out_err: | |||
592 | return err; | 592 | return err; |
593 | } | 593 | } |
594 | 594 | ||
595 | static struct of_device_id __initdata psycho_match[] = { | 595 | static const struct of_device_id psycho_match[] = { |
596 | { | 596 | { |
597 | .name = "pci", | 597 | .name = "pci", |
598 | .compatible = "pci108e,8000", | 598 | .compatible = "pci108e,8000", |
diff --git a/arch/sparc/kernel/pci_sabre.c b/arch/sparc/kernel/pci_sabre.c index 2857073342d2..948068a083fc 100644 --- a/arch/sparc/kernel/pci_sabre.c +++ b/arch/sparc/kernel/pci_sabre.c | |||
@@ -581,7 +581,7 @@ out_err: | |||
581 | return err; | 581 | return err; |
582 | } | 582 | } |
583 | 583 | ||
584 | static struct of_device_id __initdata sabre_match[] = { | 584 | static const struct of_device_id sabre_match[] = { |
585 | { | 585 | { |
586 | .name = "pci", | 586 | .name = "pci", |
587 | .compatible = "pci108e,a001", | 587 | .compatible = "pci108e,a001", |
diff --git a/arch/sparc/kernel/pci_schizo.c b/arch/sparc/kernel/pci_schizo.c index 1d41af73a92f..fecfcb2063c8 100644 --- a/arch/sparc/kernel/pci_schizo.c +++ b/arch/sparc/kernel/pci_schizo.c | |||
@@ -1470,7 +1470,7 @@ static int __devinit schizo_probe(struct platform_device *op) | |||
1470 | * and pci108e,8001. So list the chips in reverse chronological | 1470 | * and pci108e,8001. So list the chips in reverse chronological |
1471 | * order. | 1471 | * order. |
1472 | */ | 1472 | */ |
1473 | static struct of_device_id __initdata schizo_match[] = { | 1473 | static const struct of_device_id schizo_match[] = { |
1474 | { | 1474 | { |
1475 | .name = "pci", | 1475 | .name = "pci", |
1476 | .compatible = "pci108e,a801", | 1476 | .compatible = "pci108e,a801", |
diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c index 6cf534681788..b01a06e9ae4e 100644 --- a/arch/sparc/kernel/pci_sun4v.c +++ b/arch/sparc/kernel/pci_sun4v.c | |||
@@ -998,7 +998,7 @@ out_err: | |||
998 | return err; | 998 | return err; |
999 | } | 999 | } |
1000 | 1000 | ||
1001 | static struct of_device_id __initdata pci_sun4v_match[] = { | 1001 | static const struct of_device_id pci_sun4v_match[] = { |
1002 | { | 1002 | { |
1003 | .name = "pci", | 1003 | .name = "pci", |
1004 | .compatible = "SUNW,sun4v-pci", | 1004 | .compatible = "SUNW,sun4v-pci", |
diff --git a/arch/sparc/kernel/power.c b/arch/sparc/kernel/power.c index cd725fe238b2..cb4c0f57c024 100644 --- a/arch/sparc/kernel/power.c +++ b/arch/sparc/kernel/power.c | |||
@@ -52,7 +52,7 @@ static int __devinit power_probe(struct platform_device *op) | |||
52 | return 0; | 52 | return 0; |
53 | } | 53 | } |
54 | 54 | ||
55 | static struct of_device_id __initdata power_match[] = { | 55 | static const struct of_device_id power_match[] = { |
56 | { | 56 | { |
57 | .name = "power", | 57 | .name = "power", |
58 | }, | 58 | }, |
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S index 4b86eaf04fe5..47ac73c32e88 100644 --- a/arch/sparc/kernel/systbls_32.S +++ b/arch/sparc/kernel/systbls_32.S | |||
@@ -84,4 +84,4 @@ sys_call_table: | |||
84 | /*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv | 84 | /*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv |
85 | /*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init | 85 | /*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init |
86 | /*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime | 86 | /*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime |
87 | 87 | /*335*/ .long sys_syncfs | |
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S index 0331bafdf3a3..4f3170c1ef47 100644 --- a/arch/sparc/kernel/systbls_64.S +++ b/arch/sparc/kernel/systbls_64.S | |||
@@ -85,6 +85,7 @@ sys_call_table32: | |||
85 | /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv | 85 | /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv |
86 | .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init | 86 | .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init |
87 | /*330*/ .word sys32_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime | 87 | /*330*/ .word sys32_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime |
88 | .word sys_syncfs | ||
88 | 89 | ||
89 | #endif /* CONFIG_COMPAT */ | 90 | #endif /* CONFIG_COMPAT */ |
90 | 91 | ||
@@ -161,3 +162,4 @@ sys_call_table: | |||
161 | /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv | 162 | /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv |
162 | .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init | 163 | .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init |
163 | /*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime | 164 | /*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime |
165 | .word sys_syncfs | ||
diff --git a/arch/sparc/kernel/time_64.c b/arch/sparc/kernel/time_64.c index 95ec25faba39..2b8d54b2d850 100644 --- a/arch/sparc/kernel/time_64.c +++ b/arch/sparc/kernel/time_64.c | |||
@@ -442,7 +442,7 @@ static int __devinit rtc_probe(struct platform_device *op) | |||
442 | return platform_device_register(&rtc_cmos_device); | 442 | return platform_device_register(&rtc_cmos_device); |
443 | } | 443 | } |
444 | 444 | ||
445 | static struct of_device_id __initdata rtc_match[] = { | 445 | static const struct of_device_id rtc_match[] = { |
446 | { | 446 | { |
447 | .name = "rtc", | 447 | .name = "rtc", |
448 | .compatible = "m5819", | 448 | .compatible = "m5819", |
@@ -487,7 +487,7 @@ static int __devinit bq4802_probe(struct platform_device *op) | |||
487 | return platform_device_register(&rtc_bq4802_device); | 487 | return platform_device_register(&rtc_bq4802_device); |
488 | } | 488 | } |
489 | 489 | ||
490 | static struct of_device_id __initdata bq4802_match[] = { | 490 | static const struct of_device_id bq4802_match[] = { |
491 | { | 491 | { |
492 | .name = "rtc", | 492 | .name = "rtc", |
493 | .compatible = "bq4802", | 493 | .compatible = "bq4802", |
@@ -552,7 +552,7 @@ static int __devinit mostek_probe(struct platform_device *op) | |||
552 | return platform_device_register(&m48t59_rtc); | 552 | return platform_device_register(&m48t59_rtc); |
553 | } | 553 | } |
554 | 554 | ||
555 | static struct of_device_id __initdata mostek_match[] = { | 555 | static const struct of_device_id mostek_match[] = { |
556 | { | 556 | { |
557 | .name = "eeprom", | 557 | .name = "eeprom", |
558 | }, | 558 | }, |
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig index 5e34a9fee9b3..6e2cdd5ae96b 100644 --- a/arch/tile/Kconfig +++ b/arch/tile/Kconfig | |||
@@ -11,7 +11,6 @@ config TILE | |||
11 | select HAVE_GENERIC_HARDIRQS | 11 | select HAVE_GENERIC_HARDIRQS |
12 | select GENERIC_IRQ_PROBE | 12 | select GENERIC_IRQ_PROBE |
13 | select GENERIC_PENDING_IRQ if SMP | 13 | select GENERIC_PENDING_IRQ if SMP |
14 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
15 | select GENERIC_IRQ_SHOW | 14 | select GENERIC_IRQ_SHOW |
16 | 15 | ||
17 | # FIXME: investigate whether we need/want these options. | 16 | # FIXME: investigate whether we need/want these options. |
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common index 109ddc0071c6..a9234838e8a2 100644 --- a/arch/um/Kconfig.common +++ b/arch/um/Kconfig.common | |||
@@ -7,7 +7,6 @@ config UML | |||
7 | bool | 7 | bool |
8 | default y | 8 | default y |
9 | select HAVE_GENERIC_HARDIRQS | 9 | select HAVE_GENERIC_HARDIRQS |
10 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
11 | select GENERIC_IRQ_SHOW | 10 | select GENERIC_IRQ_SHOW |
12 | 11 | ||
13 | config MMU | 12 | config MMU |
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig index 4a36db45fb3d..d3a303246c9f 100644 --- a/arch/unicore32/Kconfig +++ b/arch/unicore32/Kconfig | |||
@@ -10,7 +10,7 @@ config UNICORE32 | |||
10 | select HAVE_KERNEL_LZMA | 10 | select HAVE_KERNEL_LZMA |
11 | select GENERIC_FIND_FIRST_BIT | 11 | select GENERIC_FIND_FIRST_BIT |
12 | select GENERIC_IRQ_PROBE | 12 | select GENERIC_IRQ_PROBE |
13 | select GENERIC_HARDIRQS_NO_DEPRECATED | 13 | select GENERIC_IRQ_SHOW |
14 | select ARCH_WANT_FRAME_POINTERS | 14 | select ARCH_WANT_FRAME_POINTERS |
15 | help | 15 | help |
16 | UniCore-32 is 32-bit Instruction Set Architecture, | 16 | UniCore-32 is 32-bit Instruction Set Architecture, |
diff --git a/arch/unicore32/Makefile b/arch/unicore32/Makefile index e08d6d370a8a..76a8beec7d03 100644 --- a/arch/unicore32/Makefile +++ b/arch/unicore32/Makefile | |||
@@ -48,7 +48,7 @@ ASM_GENERIC_HEADERS += bitsperlong.h bug.h bugs.h | |||
48 | ASM_GENERIC_HEADERS += cputime.h current.h | 48 | ASM_GENERIC_HEADERS += cputime.h current.h |
49 | ASM_GENERIC_HEADERS += device.h div64.h | 49 | ASM_GENERIC_HEADERS += device.h div64.h |
50 | ASM_GENERIC_HEADERS += emergency-restart.h errno.h | 50 | ASM_GENERIC_HEADERS += emergency-restart.h errno.h |
51 | ASM_GENERIC_HEADERS += fb.h fcntl.h ftrace.h | 51 | ASM_GENERIC_HEADERS += fb.h fcntl.h ftrace.h futex.h |
52 | ASM_GENERIC_HEADERS += hardirq.h hw_irq.h | 52 | ASM_GENERIC_HEADERS += hardirq.h hw_irq.h |
53 | ASM_GENERIC_HEADERS += ioctl.h ioctls.h ipcbuf.h irq_regs.h | 53 | ASM_GENERIC_HEADERS += ioctl.h ioctls.h ipcbuf.h irq_regs.h |
54 | ASM_GENERIC_HEADERS += kdebug.h kmap_types.h | 54 | ASM_GENERIC_HEADERS += kdebug.h kmap_types.h |
diff --git a/arch/unicore32/include/asm/futex.h b/arch/unicore32/include/asm/futex.h deleted file mode 100644 index 07dea6170558..000000000000 --- a/arch/unicore32/include/asm/futex.h +++ /dev/null | |||
@@ -1,143 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/unicore32/include/asm/futex.h | ||
3 | * | ||
4 | * Code specific to PKUnity SoC and UniCore ISA | ||
5 | * | ||
6 | * Copyright (C) 2001-2010 GUAN Xue-tao | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __UNICORE_FUTEX_H__ | ||
14 | #define __UNICORE_FUTEX_H__ | ||
15 | |||
16 | #ifdef __KERNEL__ | ||
17 | |||
18 | #include <linux/futex.h> | ||
19 | #include <linux/preempt.h> | ||
20 | #include <linux/uaccess.h> | ||
21 | #include <linux/errno.h> | ||
22 | |||
23 | #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ | ||
24 | __asm__ __volatile__( \ | ||
25 | "1: ldw.u %1, [%2]\n" \ | ||
26 | " " insn "\n" \ | ||
27 | "2: stw.u %0, [%2]\n" \ | ||
28 | " mov %0, #0\n" \ | ||
29 | "3:\n" \ | ||
30 | " .pushsection __ex_table,\"a\"\n" \ | ||
31 | " .align 3\n" \ | ||
32 | " .long 1b, 4f, 2b, 4f\n" \ | ||
33 | " .popsection\n" \ | ||
34 | " .pushsection .fixup,\"ax\"\n" \ | ||
35 | "4: mov %0, %4\n" \ | ||
36 | " b 3b\n" \ | ||
37 | " .popsection" \ | ||
38 | : "=&r" (ret), "=&r" (oldval) \ | ||
39 | : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ | ||
40 | : "cc", "memory") | ||
41 | |||
42 | static inline int | ||
43 | futex_atomic_op_inuser(int encoded_op, int __user *uaddr) | ||
44 | { | ||
45 | int op = (encoded_op >> 28) & 7; | ||
46 | int cmp = (encoded_op >> 24) & 15; | ||
47 | int oparg = (encoded_op << 8) >> 20; | ||
48 | int cmparg = (encoded_op << 20) >> 20; | ||
49 | int oldval = 0, ret; | ||
50 | |||
51 | if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) | ||
52 | oparg = 1 << oparg; | ||
53 | |||
54 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) | ||
55 | return -EFAULT; | ||
56 | |||
57 | pagefault_disable(); /* implies preempt_disable() */ | ||
58 | |||
59 | switch (op) { | ||
60 | case FUTEX_OP_SET: | ||
61 | __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); | ||
62 | break; | ||
63 | case FUTEX_OP_ADD: | ||
64 | __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); | ||
65 | break; | ||
66 | case FUTEX_OP_OR: | ||
67 | __futex_atomic_op("or %0, %1, %3", ret, oldval, uaddr, oparg); | ||
68 | break; | ||
69 | case FUTEX_OP_ANDN: | ||
70 | __futex_atomic_op("and %0, %1, %3", | ||
71 | ret, oldval, uaddr, ~oparg); | ||
72 | break; | ||
73 | case FUTEX_OP_XOR: | ||
74 | __futex_atomic_op("xor %0, %1, %3", ret, oldval, uaddr, oparg); | ||
75 | break; | ||
76 | default: | ||
77 | ret = -ENOSYS; | ||
78 | } | ||
79 | |||
80 | pagefault_enable(); /* subsumes preempt_enable() */ | ||
81 | |||
82 | if (!ret) { | ||
83 | switch (cmp) { | ||
84 | case FUTEX_OP_CMP_EQ: | ||
85 | ret = (oldval == cmparg); | ||
86 | break; | ||
87 | case FUTEX_OP_CMP_NE: | ||
88 | ret = (oldval != cmparg); | ||
89 | break; | ||
90 | case FUTEX_OP_CMP_LT: | ||
91 | ret = (oldval < cmparg); | ||
92 | break; | ||
93 | case FUTEX_OP_CMP_GE: | ||
94 | ret = (oldval >= cmparg); | ||
95 | break; | ||
96 | case FUTEX_OP_CMP_LE: | ||
97 | ret = (oldval <= cmparg); | ||
98 | break; | ||
99 | case FUTEX_OP_CMP_GT: | ||
100 | ret = (oldval > cmparg); | ||
101 | break; | ||
102 | default: | ||
103 | ret = -ENOSYS; | ||
104 | } | ||
105 | } | ||
106 | return ret; | ||
107 | } | ||
108 | |||
109 | static inline int | ||
110 | futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) | ||
111 | { | ||
112 | int val; | ||
113 | |||
114 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) | ||
115 | return -EFAULT; | ||
116 | |||
117 | pagefault_disable(); /* implies preempt_disable() */ | ||
118 | |||
119 | __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n" | ||
120 | "1: ldw.u %0, [%3]\n" | ||
121 | " cmpxor.a %0, %1\n" | ||
122 | " bne 3f\n" | ||
123 | "2: stw.u %2, [%3]\n" | ||
124 | "3:\n" | ||
125 | " .pushsection __ex_table,\"a\"\n" | ||
126 | " .align 3\n" | ||
127 | " .long 1b, 4f, 2b, 4f\n" | ||
128 | " .popsection\n" | ||
129 | " .pushsection .fixup,\"ax\"\n" | ||
130 | "4: mov %0, %4\n" | ||
131 | " b 3b\n" | ||
132 | " .popsection" | ||
133 | : "=&r" (val) | ||
134 | : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT) | ||
135 | : "cc", "memory"); | ||
136 | |||
137 | pagefault_enable(); /* subsumes preempt_enable() */ | ||
138 | |||
139 | return val; | ||
140 | } | ||
141 | |||
142 | #endif /* __KERNEL__ */ | ||
143 | #endif /* __UNICORE_FUTEX_H__ */ | ||
diff --git a/arch/unicore32/include/mach/PKUnity.h b/arch/unicore32/include/mach/PKUnity.h index a18bdc3810e6..8040d575dddb 100644 --- a/arch/unicore32/include/mach/PKUnity.h +++ b/arch/unicore32/include/mach/PKUnity.h | |||
@@ -24,16 +24,6 @@ | |||
24 | #define PKUNITY_MMIO_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */ | 24 | #define PKUNITY_MMIO_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */ |
25 | 25 | ||
26 | /* | 26 | /* |
27 | * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB) | ||
28 | * 0x0D000000 - 0x0DFFFFFF 16MB: for UVC | ||
29 | * 0x0E000000 - 0x0EFFFFFF 16MB: for UNIGFX | ||
30 | */ | ||
31 | #define PKUNITY_UVC_MMAP_BASE 0x0D000000 | ||
32 | #define PKUNITY_UVC_MMAP_SIZE 0x01000000 /* 16MB */ | ||
33 | #define PKUNITY_UNIGFX_MMAP_BASE 0x0E000000 | ||
34 | #define PKUNITY_UNIGFX_MMAP_SIZE 0x01000000 /* 16MB */ | ||
35 | |||
36 | /* | ||
37 | * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB) | 27 | * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB) |
38 | * 0x80000000 - 0x8000000B 12B PCI Configuration regs | 28 | * 0x80000000 - 0x8000000B 12B PCI Configuration regs |
39 | * 0x80010000 - 0x80010250 592B PCI Bridge Base | 29 | * 0x80010000 - 0x80010250 592B PCI Bridge Base |
diff --git a/arch/unicore32/include/mach/memory.h b/arch/unicore32/include/mach/memory.h index 0bf21c944710..4be72c21d491 100644 --- a/arch/unicore32/include/mach/memory.h +++ b/arch/unicore32/include/mach/memory.h | |||
@@ -50,7 +50,6 @@ void puv3_pci_adjust_zones(unsigned long *size, unsigned long *holes); | |||
50 | 50 | ||
51 | /* kuser area */ | 51 | /* kuser area */ |
52 | #define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000)) | 52 | #define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000)) |
53 | #define KUSER_UNIGFX_BASE (PAGE_OFFSET + PKUNITY_UNIGFX_MMAP_BASE) | ||
54 | /* kuser_vecpage (0xbfff0000) is ro, and vectors page (0xffff0000) is rw */ | 53 | /* kuser_vecpage (0xbfff0000) is ro, and vectors page (0xffff0000) is rw */ |
55 | #define kuser_vecpage_to_vectors(x) ((x) - (KUSER_VECPAGE_BASE) \ | 54 | #define kuser_vecpage_to_vectors(x) ((x) - (KUSER_VECPAGE_BASE) \ |
56 | + (VECTORS_BASE)) | 55 | + (VECTORS_BASE)) |
diff --git a/arch/unicore32/kernel/irq.c b/arch/unicore32/kernel/irq.c index b23624cf3062..2aa30a364bbe 100644 --- a/arch/unicore32/kernel/irq.c +++ b/arch/unicore32/kernel/irq.c | |||
@@ -321,24 +321,24 @@ void __init init_IRQ(void) | |||
321 | writel(1, INTC_ICCR); | 321 | writel(1, INTC_ICCR); |
322 | 322 | ||
323 | for (irq = 0; irq < IRQ_GPIOHIGH; irq++) { | 323 | for (irq = 0; irq < IRQ_GPIOHIGH; irq++) { |
324 | set_irq_chip(irq, &puv3_low_gpio_chip); | 324 | irq_set_chip(irq, &puv3_low_gpio_chip); |
325 | set_irq_handler(irq, handle_edge_irq); | 325 | irq_set_handler(irq, handle_edge_irq); |
326 | irq_modify_status(irq, | 326 | irq_modify_status(irq, |
327 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, | 327 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, |
328 | 0); | 328 | 0); |
329 | } | 329 | } |
330 | 330 | ||
331 | for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) { | 331 | for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) { |
332 | set_irq_chip(irq, &puv3_normal_chip); | 332 | irq_set_chip(irq, &puv3_normal_chip); |
333 | set_irq_handler(irq, handle_level_irq); | 333 | irq_set_handler(irq, handle_level_irq); |
334 | irq_modify_status(irq, | 334 | irq_modify_status(irq, |
335 | IRQ_NOREQUEST | IRQ_NOAUTOEN, | 335 | IRQ_NOREQUEST | IRQ_NOAUTOEN, |
336 | IRQ_NOPROBE); | 336 | IRQ_NOPROBE); |
337 | } | 337 | } |
338 | 338 | ||
339 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) { | 339 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) { |
340 | set_irq_chip(irq, &puv3_high_gpio_chip); | 340 | irq_set_chip(irq, &puv3_high_gpio_chip); |
341 | set_irq_handler(irq, handle_edge_irq); | 341 | irq_set_handler(irq, handle_edge_irq); |
342 | irq_modify_status(irq, | 342 | irq_modify_status(irq, |
343 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, | 343 | IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, |
344 | 0); | 344 | 0); |
@@ -347,56 +347,14 @@ void __init init_IRQ(void) | |||
347 | /* | 347 | /* |
348 | * Install handler for GPIO 0-27 edge detect interrupts | 348 | * Install handler for GPIO 0-27 edge detect interrupts |
349 | */ | 349 | */ |
350 | set_irq_chip(IRQ_GPIOHIGH, &puv3_normal_chip); | 350 | irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip); |
351 | set_irq_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler); | 351 | irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler); |
352 | 352 | ||
353 | #ifdef CONFIG_PUV3_GPIO | 353 | #ifdef CONFIG_PUV3_GPIO |
354 | puv3_init_gpio(); | 354 | puv3_init_gpio(); |
355 | #endif | 355 | #endif |
356 | } | 356 | } |
357 | 357 | ||
358 | int show_interrupts(struct seq_file *p, void *v) | ||
359 | { | ||
360 | int i = *(loff_t *) v, cpu; | ||
361 | struct irq_desc *desc; | ||
362 | struct irqaction *action; | ||
363 | unsigned long flags; | ||
364 | |||
365 | if (i == 0) { | ||
366 | char cpuname[12]; | ||
367 | |||
368 | seq_printf(p, " "); | ||
369 | for_each_present_cpu(cpu) { | ||
370 | sprintf(cpuname, "CPU%d", cpu); | ||
371 | seq_printf(p, " %10s", cpuname); | ||
372 | } | ||
373 | seq_putc(p, '\n'); | ||
374 | } | ||
375 | |||
376 | if (i < nr_irqs) { | ||
377 | desc = irq_to_desc(i); | ||
378 | raw_spin_lock_irqsave(&desc->lock, flags); | ||
379 | action = desc->action; | ||
380 | if (!action) | ||
381 | goto unlock; | ||
382 | |||
383 | seq_printf(p, "%3d: ", i); | ||
384 | for_each_present_cpu(cpu) | ||
385 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu)); | ||
386 | seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-"); | ||
387 | seq_printf(p, " %s", action->name); | ||
388 | for (action = action->next; action; action = action->next) | ||
389 | seq_printf(p, ", %s", action->name); | ||
390 | |||
391 | seq_putc(p, '\n'); | ||
392 | unlock: | ||
393 | raw_spin_unlock_irqrestore(&desc->lock, flags); | ||
394 | } else if (i == nr_irqs) { | ||
395 | seq_printf(p, "Error in interrupt!\n"); | ||
396 | } | ||
397 | return 0; | ||
398 | } | ||
399 | |||
400 | /* | 358 | /* |
401 | * do_IRQ handles all hardware IRQ's. Decoded IRQs should not | 359 | * do_IRQ handles all hardware IRQ's. Decoded IRQs should not |
402 | * come via this function. Instead, they should provide their | 360 | * come via this function. Instead, they should provide their |
diff --git a/arch/unicore32/kernel/puv3-core.c b/arch/unicore32/kernel/puv3-core.c index 8b1b6beb858e..1a505a787765 100644 --- a/arch/unicore32/kernel/puv3-core.c +++ b/arch/unicore32/kernel/puv3-core.c | |||
@@ -99,11 +99,6 @@ static struct resource puv3_unigfx_resources[] = { | |||
99 | .end = io_v2p(PKUNITY_UNIGFX_BASE) + 0xfff, | 99 | .end = io_v2p(PKUNITY_UNIGFX_BASE) + 0xfff, |
100 | .flags = IORESOURCE_MEM, | 100 | .flags = IORESOURCE_MEM, |
101 | }, | 101 | }, |
102 | [1] = { | ||
103 | .start = PKUNITY_UNIGFX_MMAP_BASE, | ||
104 | .end = PKUNITY_UNIGFX_MMAP_BASE + PKUNITY_UNIGFX_MMAP_SIZE, | ||
105 | .flags = IORESOURCE_MEM, | ||
106 | }, | ||
107 | }; | 102 | }; |
108 | 103 | ||
109 | static struct resource puv3_rtc_resources[] = { | 104 | static struct resource puv3_rtc_resources[] = { |
diff --git a/arch/unicore32/kernel/rtc.c b/arch/unicore32/kernel/rtc.c index c5f068295b51..8cad70b3302c 100644 --- a/arch/unicore32/kernel/rtc.c +++ b/arch/unicore32/kernel/rtc.c | |||
@@ -88,11 +88,6 @@ static int puv3_rtc_setpie(struct device *dev, int enabled) | |||
88 | return 0; | 88 | return 0; |
89 | } | 89 | } |
90 | 90 | ||
91 | static int puv3_rtc_setfreq(struct device *dev, int freq) | ||
92 | { | ||
93 | return 0; | ||
94 | } | ||
95 | |||
96 | /* Time read/write */ | 91 | /* Time read/write */ |
97 | 92 | ||
98 | static int puv3_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) | 93 | static int puv3_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) |
@@ -214,8 +209,6 @@ static const struct rtc_class_ops puv3_rtcops = { | |||
214 | .set_time = puv3_rtc_settime, | 209 | .set_time = puv3_rtc_settime, |
215 | .read_alarm = puv3_rtc_getalarm, | 210 | .read_alarm = puv3_rtc_getalarm, |
216 | .set_alarm = puv3_rtc_setalarm, | 211 | .set_alarm = puv3_rtc_setalarm, |
217 | .irq_set_freq = puv3_rtc_setfreq, | ||
218 | .irq_set_state = puv3_rtc_setpie, | ||
219 | .proc = puv3_rtc_proc, | 212 | .proc = puv3_rtc_proc, |
220 | }; | 213 | }; |
221 | 214 | ||
@@ -294,8 +287,6 @@ static int puv3_rtc_probe(struct platform_device *pdev) | |||
294 | 287 | ||
295 | puv3_rtc_enable(pdev, 1); | 288 | puv3_rtc_enable(pdev, 1); |
296 | 289 | ||
297 | puv3_rtc_setfreq(&pdev->dev, 1); | ||
298 | |||
299 | /* register RTC and exit */ | 290 | /* register RTC and exit */ |
300 | 291 | ||
301 | rtc = rtc_device_register("pkunity", &pdev->dev, &puv3_rtcops, | 292 | rtc = rtc_device_register("pkunity", &pdev->dev, &puv3_rtcops, |
diff --git a/arch/unicore32/kernel/setup.c b/arch/unicore32/kernel/setup.c index 1e175a82844d..471b6bca8da4 100644 --- a/arch/unicore32/kernel/setup.c +++ b/arch/unicore32/kernel/setup.c | |||
@@ -64,12 +64,6 @@ static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; | |||
64 | */ | 64 | */ |
65 | static struct resource mem_res[] = { | 65 | static struct resource mem_res[] = { |
66 | { | 66 | { |
67 | .name = "Video RAM", | ||
68 | .start = 0, | ||
69 | .end = 0, | ||
70 | .flags = IORESOURCE_MEM | ||
71 | }, | ||
72 | { | ||
73 | .name = "Kernel text", | 67 | .name = "Kernel text", |
74 | .start = 0, | 68 | .start = 0, |
75 | .end = 0, | 69 | .end = 0, |
@@ -83,9 +77,8 @@ static struct resource mem_res[] = { | |||
83 | } | 77 | } |
84 | }; | 78 | }; |
85 | 79 | ||
86 | #define video_ram mem_res[0] | 80 | #define kernel_code mem_res[0] |
87 | #define kernel_code mem_res[1] | 81 | #define kernel_data mem_res[1] |
88 | #define kernel_data mem_res[2] | ||
89 | 82 | ||
90 | /* | 83 | /* |
91 | * These functions re-use the assembly code in head.S, which | 84 | * These functions re-use the assembly code in head.S, which |
@@ -224,10 +217,6 @@ request_standard_resources(struct meminfo *mi) | |||
224 | kernel_data.end <= res->end) | 217 | kernel_data.end <= res->end) |
225 | request_resource(res, &kernel_data); | 218 | request_resource(res, &kernel_data); |
226 | } | 219 | } |
227 | |||
228 | video_ram.start = PKUNITY_UNIGFX_MMAP_BASE; | ||
229 | video_ram.end = PKUNITY_UNIGFX_MMAP_BASE + PKUNITY_UNIGFX_MMAP_SIZE; | ||
230 | request_resource(&iomem_resource, &video_ram); | ||
231 | } | 220 | } |
232 | 221 | ||
233 | static void (*init_machine)(void) __initdata; | 222 | static void (*init_machine)(void) __initdata; |
diff --git a/arch/unicore32/kernel/traps.c b/arch/unicore32/kernel/traps.c index 25abbb101729..254e36fa9513 100644 --- a/arch/unicore32/kernel/traps.c +++ b/arch/unicore32/kernel/traps.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
23 | #include <linux/hardirq.h> | 23 | #include <linux/hardirq.h> |
24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
25 | #include <linux/uaccess.h> | ||
26 | #include <linux/atomic.h> | 25 | #include <linux/atomic.h> |
27 | #include <linux/unistd.h> | 26 | #include <linux/unistd.h> |
28 | 27 | ||
diff --git a/arch/unicore32/kernel/vmlinux.lds.S b/arch/unicore32/kernel/vmlinux.lds.S index 0b4eb89729e7..9bf7f7af52c5 100644 --- a/arch/unicore32/kernel/vmlinux.lds.S +++ b/arch/unicore32/kernel/vmlinux.lds.S | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <asm/thread_info.h> | 14 | #include <asm/thread_info.h> |
15 | #include <asm/memory.h> | 15 | #include <asm/memory.h> |
16 | #include <asm/page.h> | 16 | #include <asm/page.h> |
17 | #include <asm/cache.h> | ||
17 | 18 | ||
18 | OUTPUT_ARCH(unicore32) | 19 | OUTPUT_ARCH(unicore32) |
19 | ENTRY(stext) | 20 | ENTRY(stext) |
@@ -29,7 +30,7 @@ SECTIONS | |||
29 | HEAD_TEXT_SECTION | 30 | HEAD_TEXT_SECTION |
30 | INIT_TEXT_SECTION(PAGE_SIZE) | 31 | INIT_TEXT_SECTION(PAGE_SIZE) |
31 | INIT_DATA_SECTION(16) | 32 | INIT_DATA_SECTION(16) |
32 | PERCPU(PAGE_SIZE) | 33 | PERCPU(L1_CACHE_BYTES, PAGE_SIZE) |
33 | __init_end = .; | 34 | __init_end = .; |
34 | 35 | ||
35 | _stext = .; | 36 | _stext = .; |
@@ -45,10 +46,10 @@ SECTIONS | |||
45 | 46 | ||
46 | _sdata = .; | 47 | _sdata = .; |
47 | RO_DATA_SECTION(PAGE_SIZE) | 48 | RO_DATA_SECTION(PAGE_SIZE) |
48 | RW_DATA_SECTION(32, PAGE_SIZE, THREAD_SIZE) | 49 | RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) |
49 | _edata = .; | 50 | _edata = .; |
50 | 51 | ||
51 | EXCEPTION_TABLE(32) | 52 | EXCEPTION_TABLE(L1_CACHE_BYTES) |
52 | NOTES | 53 | NOTES |
53 | 54 | ||
54 | BSS_SECTION(0, 0, 0) | 55 | BSS_SECTION(0, 0, 0) |
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c index 7bf3d588631f..db2d334941b4 100644 --- a/arch/unicore32/mm/mmu.c +++ b/arch/unicore32/mm/mmu.c | |||
@@ -338,15 +338,6 @@ void __init uc32_mm_memblock_reserve(void) | |||
338 | * and can only be in node 0. | 338 | * and can only be in node 0. |
339 | */ | 339 | */ |
340 | memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); | 340 | memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); |
341 | |||
342 | #ifdef CONFIG_PUV3_UNIGFX | ||
343 | /* | ||
344 | * These should likewise go elsewhere. They pre-reserve the | ||
345 | * screen/video memory region at the 48M~64M of main system memory. | ||
346 | */ | ||
347 | memblock_reserve(PKUNITY_UNIGFX_MMAP_BASE, PKUNITY_UNIGFX_MMAP_SIZE); | ||
348 | memblock_reserve(PKUNITY_UVC_MMAP_BASE, PKUNITY_UVC_MMAP_SIZE); | ||
349 | #endif | ||
350 | } | 341 | } |
351 | 342 | ||
352 | /* | 343 | /* |
@@ -371,17 +362,6 @@ static void __init devicemaps_init(void) | |||
371 | pmd_clear(pmd_off_k(addr)); | 362 | pmd_clear(pmd_off_k(addr)); |
372 | 363 | ||
373 | /* | 364 | /* |
374 | * Create a mapping for UniGFX VRAM | ||
375 | */ | ||
376 | #ifdef CONFIG_PUV3_UNIGFX | ||
377 | map.pfn = __phys_to_pfn(PKUNITY_UNIGFX_MMAP_BASE); | ||
378 | map.virtual = KUSER_UNIGFX_BASE; | ||
379 | map.length = PKUNITY_UNIGFX_MMAP_SIZE; | ||
380 | map.type = MT_KUSER; | ||
381 | create_mapping(&map); | ||
382 | #endif | ||
383 | |||
384 | /* | ||
385 | * Create a mapping for the machine vectors at the high-vectors | 365 | * Create a mapping for the machine vectors at the high-vectors |
386 | * location (0xffff0000). If we aren't using high-vectors, also | 366 | * location (0xffff0000). If we aren't using high-vectors, also |
387 | * create a mapping at the low-vectors virtual address. | 367 | * create a mapping at the low-vectors virtual address. |
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c index 1293c709ee85..cd1ffed4ee22 100644 --- a/arch/x86/kernel/apb_timer.c +++ b/arch/x86/kernel/apb_timer.c | |||
@@ -316,7 +316,7 @@ static void apbt_setup_irq(struct apbt_dev *adev) | |||
316 | irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); | 316 | irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT); |
317 | irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); | 317 | irq_set_affinity(adev->irq, cpumask_of(adev->cpu)); |
318 | /* APB timer irqs are set up as mp_irqs, timer is edge type */ | 318 | /* APB timer irqs are set up as mp_irqs, timer is edge type */ |
319 | __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge"); | 319 | __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge"); |
320 | 320 | ||
321 | if (system_state == SYSTEM_BOOTING) { | 321 | if (system_state == SYSTEM_BOOTING) { |
322 | if (request_irq(adev->irq, apbt_interrupt_handler, | 322 | if (request_irq(adev->irq, apbt_interrupt_handler, |
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 5a05ef63eb4a..3385ea26f684 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c | |||
@@ -1626,7 +1626,7 @@ out: | |||
1626 | static unsigned int mce_poll(struct file *file, poll_table *wait) | 1626 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1627 | { | 1627 | { |
1628 | poll_wait(file, &mce_wait, wait); | 1628 | poll_wait(file, &mce_wait, wait); |
1629 | if (rcu_dereference_check_mce(mcelog.next)) | 1629 | if (rcu_access_index(mcelog.next)) |
1630 | return POLLIN | POLLRDNORM; | 1630 | return POLLIN | POLLRDNORM; |
1631 | if (!mce_apei_read_done && apei_check_mce()) | 1631 | if (!mce_apei_read_done && apei_check_mce()) |
1632 | return POLLIN | POLLRDNORM; | 1632 | return POLLIN | POLLRDNORM; |
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c index 8dace181c88e..cf9750004a08 100644 --- a/arch/x86/oprofile/nmi_int.c +++ b/arch/x86/oprofile/nmi_int.c | |||
@@ -49,6 +49,10 @@ u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, | |||
49 | val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; | 49 | val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; |
50 | val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; | 50 | val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; |
51 | val |= (counter_config->unit_mask & 0xFF) << 8; | 51 | val |= (counter_config->unit_mask & 0xFF) << 8; |
52 | counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV | | ||
53 | ARCH_PERFMON_EVENTSEL_EDGE | | ||
54 | ARCH_PERFMON_EVENTSEL_CMASK); | ||
55 | val |= counter_config->extra; | ||
52 | event &= model->event_mask ? model->event_mask : 0xFF; | 56 | event &= model->event_mask ? model->event_mask : 0xFF; |
53 | val |= event & 0xFF; | 57 | val |= event & 0xFF; |
54 | val |= (event & 0x0F00) << 24; | 58 | val |= (event & 0x0F00) << 24; |
@@ -440,6 +444,7 @@ static int nmi_create_files(struct super_block *sb, struct dentry *root) | |||
440 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | 444 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); |
441 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | 445 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); |
442 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | 446 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); |
447 | oprofilefs_create_ulong(sb, dir, "extra", &counter_config[i].extra); | ||
443 | } | 448 | } |
444 | 449 | ||
445 | return 0; | 450 | return 0; |
diff --git a/arch/x86/oprofile/op_counter.h b/arch/x86/oprofile/op_counter.h index e28398df0df2..0b7b7b179cbe 100644 --- a/arch/x86/oprofile/op_counter.h +++ b/arch/x86/oprofile/op_counter.h | |||
@@ -22,6 +22,7 @@ struct op_counter_config { | |||
22 | unsigned long kernel; | 22 | unsigned long kernel; |
23 | unsigned long user; | 23 | unsigned long user; |
24 | unsigned long unit_mask; | 24 | unsigned long unit_mask; |
25 | unsigned long extra; | ||
25 | }; | 26 | }; |
26 | 27 | ||
27 | extern struct op_counter_config counter_config[]; | 28 | extern struct op_counter_config counter_config[]; |
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c index 215a3ce61068..141eb0de8b06 100644 --- a/arch/x86/xen/p2m.c +++ b/arch/x86/xen/p2m.c | |||
@@ -497,7 +497,7 @@ static bool alloc_p2m(unsigned long pfn) | |||
497 | return true; | 497 | return true; |
498 | } | 498 | } |
499 | 499 | ||
500 | bool __early_alloc_p2m(unsigned long pfn) | 500 | static bool __init __early_alloc_p2m(unsigned long pfn) |
501 | { | 501 | { |
502 | unsigned topidx, mididx, idx; | 502 | unsigned topidx, mididx, idx; |
503 | 503 | ||
@@ -530,7 +530,7 @@ bool __early_alloc_p2m(unsigned long pfn) | |||
530 | } | 530 | } |
531 | return idx != 0; | 531 | return idx != 0; |
532 | } | 532 | } |
533 | unsigned long set_phys_range_identity(unsigned long pfn_s, | 533 | unsigned long __init set_phys_range_identity(unsigned long pfn_s, |
534 | unsigned long pfn_e) | 534 | unsigned long pfn_e) |
535 | { | 535 | { |
536 | unsigned long pfn; | 536 | unsigned long pfn; |
@@ -671,7 +671,9 @@ int m2p_add_override(unsigned long mfn, struct page *page) | |||
671 | page->private = mfn; | 671 | page->private = mfn; |
672 | page->index = pfn_to_mfn(pfn); | 672 | page->index = pfn_to_mfn(pfn); |
673 | 673 | ||
674 | __set_phys_to_machine(pfn, FOREIGN_FRAME(mfn)); | 674 | if (unlikely(!set_phys_to_machine(pfn, FOREIGN_FRAME(mfn)))) |
675 | return -ENOMEM; | ||
676 | |||
675 | if (!PageHighMem(page)) | 677 | if (!PageHighMem(page)) |
676 | /* Just zap old mapping for now */ | 678 | /* Just zap old mapping for now */ |
677 | pte_clear(&init_mm, address, ptep); | 679 | pte_clear(&init_mm, address, ptep); |
@@ -709,7 +711,7 @@ int m2p_remove_override(struct page *page) | |||
709 | spin_lock_irqsave(&m2p_override_lock, flags); | 711 | spin_lock_irqsave(&m2p_override_lock, flags); |
710 | list_del(&page->lru); | 712 | list_del(&page->lru); |
711 | spin_unlock_irqrestore(&m2p_override_lock, flags); | 713 | spin_unlock_irqrestore(&m2p_override_lock, flags); |
712 | __set_phys_to_machine(pfn, page->index); | 714 | set_phys_to_machine(pfn, page->index); |
713 | 715 | ||
714 | if (!PageHighMem(page)) | 716 | if (!PageHighMem(page)) |
715 | set_pte_at(&init_mm, address, ptep, | 717 | set_pte_at(&init_mm, address, ptep, |
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 1d730b5579a0..7c275f5d0df0 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig | |||
@@ -9,7 +9,6 @@ config XTENSA | |||
9 | select HAVE_IDE | 9 | select HAVE_IDE |
10 | select HAVE_GENERIC_HARDIRQS | 10 | select HAVE_GENERIC_HARDIRQS |
11 | select GENERIC_IRQ_SHOW | 11 | select GENERIC_IRQ_SHOW |
12 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
13 | help | 12 | help |
14 | Xtensa processors are 32-bit RISC machines designed by Tensilica | 13 | Xtensa processors are 32-bit RISC machines designed by Tensilica |
15 | primarily for embedded systems. These processors are both | 14 | primarily for embedded systems. These processors are both |