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-rw-r--r--arch/arm/Kconfig16
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/common/Kconfig2
-rw-r--r--arch/arm/configs/at91x40_defconfig48
-rw-r--r--arch/arm/configs/s5p6442_defconfig65
-rw-r--r--arch/arm/kernel/ptrace.c8
-rw-r--r--arch/arm/mach-at91/Kconfig1
-rw-r--r--arch/arm/mach-at91/board-eb01.c7
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h28
-rw-r--r--arch/arm/mach-s5p6442/Kconfig25
-rw-r--r--arch/arm/mach-s5p6442/Makefile24
-rw-r--r--arch/arm/mach-s5p6442/Makefile.boot2
-rw-r--r--arch/arm/mach-s5p6442/clock.c420
-rw-r--r--arch/arm/mach-s5p6442/cpu.c143
-rw-r--r--arch/arm/mach-s5p6442/dev-audio.c217
-rw-r--r--arch/arm/mach-s5p6442/dev-spi.c121
-rw-r--r--arch/arm/mach-s5p6442/dma.c105
-rw-r--r--arch/arm/mach-s5p6442/include/mach/debug-macro.S35
-rw-r--r--arch/arm/mach-s5p6442/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5p6442/include/mach/entry-macro.S48
-rw-r--r--arch/arm/mach-s5p6442/include/mach/gpio.h123
-rw-r--r--arch/arm/mach-s5p6442/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5p6442/include/mach/io.h17
-rw-r--r--arch/arm/mach-s5p6442/include/mach/irqs.h87
-rw-r--r--arch/arm/mach-s5p6442/include/mach/map.h76
-rw-r--r--arch/arm/mach-s5p6442/include/mach/memory.h19
-rw-r--r--arch/arm/mach-s5p6442/include/mach/pwm-clock.h70
-rw-r--r--arch/arm/mach-s5p6442/include/mach/regs-clock.h104
-rw-r--r--arch/arm/mach-s5p6442/include/mach/regs-irq.h19
-rw-r--r--arch/arm/mach-s5p6442/include/mach/spi-clocks.h17
-rw-r--r--arch/arm/mach-s5p6442/include/mach/system.h23
-rw-r--r--arch/arm/mach-s5p6442/include/mach/tick.h26
-rw-r--r--arch/arm/mach-s5p6442/include/mach/timex.h24
-rw-r--r--arch/arm/mach-s5p6442/include/mach/uncompress.h24
-rw-r--r--arch/arm/mach-s5p6442/include/mach/vmalloc.h17
-rw-r--r--arch/arm/mach-s5p6442/init.c44
-rw-r--r--arch/arm/mach-s5p6442/mach-smdk6442.c102
-rw-r--r--arch/arm/mach-s5p6442/setup-i2c0.c28
-rw-r--r--arch/arm/plat-s5p/Kconfig2
-rw-r--r--arch/arm/plat-s5p/cpu.c10
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p6442.h33
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/debug-macro.S2
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-serial.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h1
-rw-r--r--arch/powerpc/kernel/ptrace.c12
-rw-r--r--arch/sh/kernel/ptrace_32.c4
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel.c87
-rw-r--r--arch/x86/kernel/ptrace.c36
50 files changed, 190 insertions, 2186 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 377a7a595b08..e81c72c38fed 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -736,16 +736,6 @@ config ARCH_S5P64X0
736 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, 736 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
737 SMDK6450. 737 SMDK6450.
738 738
739config ARCH_S5P6442
740 bool "Samsung S5P6442"
741 select CPU_V6
742 select GENERIC_GPIO
743 select HAVE_CLK
744 select ARCH_USES_GETTIMEOFFSET
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 help
747 Samsung S5P6442 CPU based systems
748
749config ARCH_S5PC100 739config ARCH_S5PC100
750 bool "Samsung S5PC100" 740 bool "Samsung S5PC100"
751 select GENERIC_GPIO 741 select GENERIC_GPIO
@@ -995,8 +985,6 @@ endif
995 985
996source "arch/arm/mach-s5p64x0/Kconfig" 986source "arch/arm/mach-s5p64x0/Kconfig"
997 987
998source "arch/arm/mach-s5p6442/Kconfig"
999
1000source "arch/arm/mach-s5pc100/Kconfig" 988source "arch/arm/mach-s5pc100/Kconfig"
1001 989
1002source "arch/arm/mach-s5pv210/Kconfig" 990source "arch/arm/mach-s5pv210/Kconfig"
@@ -1424,7 +1412,7 @@ source kernel/Kconfig.preempt
1424config HZ 1412config HZ
1425 int 1413 int
1426 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1414 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1427 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4 1415 ARCH_S5PV210 || ARCH_EXYNOS4
1428 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1416 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1429 default AT91_TIMER_HZ if ARCH_AT91 1417 default AT91_TIMER_HZ if ARCH_AT91
1430 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1418 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
@@ -2010,7 +1998,7 @@ menu "Power management options"
2010source "kernel/power/Kconfig" 1998source "kernel/power/Kconfig"
2011 1999
2012config ARCH_SUSPEND_POSSIBLE 2000config ARCH_SUSPEND_POSSIBLE
2013 depends on !ARCH_S5P64X0 && !ARCH_S5P6442 2001 depends on !ARCH_S5P64X0
2014 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ 2002 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2015 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE 2003 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2016 def_bool y 2004 def_bool y
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c7d321a3d95d..c17304bf940b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -178,7 +178,6 @@ machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c24
178machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 178machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
179machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx 179machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
180machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 180machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
181machine-$(CONFIG_ARCH_S5P6442) := s5p6442
182machine-$(CONFIG_ARCH_S5PC100) := s5pc100 181machine-$(CONFIG_ARCH_S5PC100) := s5pc100
183machine-$(CONFIG_ARCH_S5PV210) := s5pv210 182machine-$(CONFIG_ARCH_S5PV210) := s5pv210
184machine-$(CONFIG_ARCH_EXYNOS4) := exynos4 183machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index ea5ee4d067f3..4b71766fb21d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -7,7 +7,7 @@ config ARM_VIC
7config ARM_VIC_NR 7config ARM_VIC_NR
8 int 8 int
9 default 4 if ARCH_S5PV210 9 default 4 if ARCH_S5PV210
10 default 3 if ARCH_S5P6442 || ARCH_S5PC100 10 default 3 if ARCH_S5PC100
11 default 2 11 default 2
12 depends on ARM_VIC 12 depends on ARM_VIC
13 help 13 help
diff --git a/arch/arm/configs/at91x40_defconfig b/arch/arm/configs/at91x40_defconfig
new file mode 100644
index 000000000000..c55e9212fcbb
--- /dev/null
+++ b/arch/arm/configs/at91x40_defconfig
@@ -0,0 +1,48 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOG_BUF_SHIFT=14
3CONFIG_EMBEDDED=y
4# CONFIG_HOTPLUG is not set
5# CONFIG_ELF_CORE is not set
6# CONFIG_FUTEX is not set
7# CONFIG_TIMERFD is not set
8# CONFIG_VM_EVENT_COUNTERS is not set
9# CONFIG_COMPAT_BRK is not set
10CONFIG_SLAB=y
11# CONFIG_LBDAF is not set
12# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_DEADLINE is not set
14# CONFIG_IOSCHED_CFQ is not set
15# CONFIG_MMU is not set
16CONFIG_ARCH_AT91=y
17CONFIG_ARCH_AT91X40=y
18CONFIG_MACH_AT91EB01=y
19CONFIG_AT91_EARLY_USART0=y
20CONFIG_CPU_ARM7TDMI=y
21CONFIG_SET_MEM_PARAM=y
22CONFIG_DRAM_BASE=0x01000000
23CONFIG_DRAM_SIZE=0x00400000
24CONFIG_FLASH_MEM_BASE=0x01400000
25CONFIG_PROCESSOR_ID=0x14000040
26CONFIG_ZBOOT_ROM_TEXT=0x0
27CONFIG_ZBOOT_ROM_BSS=0x0
28CONFIG_BINFMT_FLAT=y
29# CONFIG_SUSPEND is not set
30# CONFIG_FW_LOADER is not set
31CONFIG_MTD=y
32CONFIG_MTD_PARTITIONS=y
33CONFIG_MTD_CHAR=y
34CONFIG_MTD_BLOCK=y
35CONFIG_MTD_RAM=y
36CONFIG_MTD_ROM=y
37CONFIG_BLK_DEV_RAM=y
38# CONFIG_INPUT is not set
39# CONFIG_SERIO is not set
40# CONFIG_VT is not set
41# CONFIG_DEVKMEM is not set
42# CONFIG_HW_RANDOM is not set
43# CONFIG_HWMON is not set
44# CONFIG_USB_SUPPORT is not set
45CONFIG_EXT2_FS=y
46# CONFIG_DNOTIFY is not set
47CONFIG_ROMFS_FS=y
48# CONFIG_ENABLE_MUST_CHECK is not set
diff --git a/arch/arm/configs/s5p6442_defconfig b/arch/arm/configs/s5p6442_defconfig
deleted file mode 100644
index 0e92a784af66..000000000000
--- a/arch/arm/configs/s5p6442_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSFS_DEPRECATED_V2=y
3CONFIG_BLK_DEV_INITRD=y
4CONFIG_KALLSYMS_ALL=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_S5P6442=y
9CONFIG_S3C_LOWLEVEL_UART_PORT=1
10CONFIG_MACH_SMDK6442=y
11CONFIG_CPU_32v6K=y
12CONFIG_AEABI=y
13CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
14CONFIG_FPE_NWFPE=y
15CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
16# CONFIG_PREVENT_FIRMWARE_BUILD is not set
17CONFIG_BLK_DEV_LOOP=y
18CONFIG_BLK_DEV_RAM=y
19CONFIG_BLK_DEV_RAM_SIZE=8192
20# CONFIG_MISC_DEVICES is not set
21CONFIG_SCSI=y
22CONFIG_BLK_DEV_SD=y
23CONFIG_CHR_DEV_SG=y
24CONFIG_INPUT_EVDEV=y
25# CONFIG_INPUT_KEYBOARD is not set
26# CONFIG_INPUT_MOUSE is not set
27CONFIG_INPUT_TOUCHSCREEN=y
28CONFIG_SERIAL_8250=y
29CONFIG_SERIAL_8250_NR_UARTS=3
30CONFIG_SERIAL_SAMSUNG=y
31CONFIG_SERIAL_SAMSUNG_CONSOLE=y
32CONFIG_HW_RANDOM=y
33# CONFIG_HWMON is not set
34# CONFIG_VGA_CONSOLE is not set
35# CONFIG_HID_SUPPORT is not set
36# CONFIG_USB_SUPPORT is not set
37CONFIG_EXT2_FS=y
38CONFIG_INOTIFY=y
39CONFIG_MSDOS_FS=y
40CONFIG_VFAT_FS=y
41CONFIG_TMPFS=y
42CONFIG_TMPFS_POSIX_ACL=y
43CONFIG_CRAMFS=y
44CONFIG_ROMFS_FS=y
45CONFIG_PARTITION_ADVANCED=y
46CONFIG_BSD_DISKLABEL=y
47CONFIG_SOLARIS_X86_PARTITION=y
48CONFIG_NLS_CODEPAGE_437=y
49CONFIG_NLS_ASCII=y
50CONFIG_NLS_ISO8859_1=y
51CONFIG_MAGIC_SYSRQ=y
52CONFIG_DEBUG_KERNEL=y
53CONFIG_DEBUG_RT_MUTEXES=y
54CONFIG_DEBUG_SPINLOCK=y
55CONFIG_DEBUG_MUTEXES=y
56CONFIG_DEBUG_SPINLOCK_SLEEP=y
57CONFIG_DEBUG_INFO=y
58# CONFIG_RCU_CPU_STALL_DETECTOR is not set
59CONFIG_SYSCTL_SYSCALL_CHECK=y
60# CONFIG_ARM_UNWIND is not set
61CONFIG_DEBUG_USER=y
62CONFIG_DEBUG_ERRORS=y
63CONFIG_DEBUG_LL=y
64CONFIG_DEBUG_S3C_UART=1
65CONFIG_CRC_CCITT=y
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 2bf27f364d09..8182f45ca493 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -767,12 +767,20 @@ long arch_ptrace(struct task_struct *child, long request,
767 767
768#ifdef CONFIG_HAVE_HW_BREAKPOINT 768#ifdef CONFIG_HAVE_HW_BREAKPOINT
769 case PTRACE_GETHBPREGS: 769 case PTRACE_GETHBPREGS:
770 if (ptrace_get_breakpoints(child) < 0)
771 return -ESRCH;
772
770 ret = ptrace_gethbpregs(child, addr, 773 ret = ptrace_gethbpregs(child, addr,
771 (unsigned long __user *)data); 774 (unsigned long __user *)data);
775 ptrace_put_breakpoints(child);
772 break; 776 break;
773 case PTRACE_SETHBPREGS: 777 case PTRACE_SETHBPREGS:
778 if (ptrace_get_breakpoints(child) < 0)
779 return -ESRCH;
780
774 ret = ptrace_sethbpregs(child, addr, 781 ret = ptrace_sethbpregs(child, addr,
775 (unsigned long __user *)data); 782 (unsigned long __user *)data);
783 ptrace_put_breakpoints(child);
776 break; 784 break;
777#endif 785#endif
778 786
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 19390231a0e9..2d299bf5d72f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -83,6 +83,7 @@ config ARCH_AT91CAP9
83 select CPU_ARM926T 83 select CPU_ARM926T
84 select GENERIC_CLOCKEVENTS 84 select GENERIC_CLOCKEVENTS
85 select HAVE_FB_ATMEL 85 select HAVE_FB_ATMEL
86 select HAVE_NET_MACB
86 87
87config ARCH_AT572D940HF 88config ARCH_AT572D940HF
88 bool "AT572D940HF" 89 bool "AT572D940HF"
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index 1f9d3cb64c50..d8df59a3426d 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -30,6 +30,11 @@
30#include <mach/board.h> 30#include <mach/board.h>
31#include "generic.h" 31#include "generic.h"
32 32
33static void __init at91eb01_init_irq(void)
34{
35 at91x40_init_interrupts(NULL);
36}
37
33static void __init at91eb01_map_io(void) 38static void __init at91eb01_map_io(void)
34{ 39{
35 at91x40_initialize(40000000); 40 at91x40_initialize(40000000);
@@ -38,7 +43,7 @@ static void __init at91eb01_map_io(void)
38MACHINE_START(AT91EB01, "Atmel AT91 EB01") 43MACHINE_START(AT91EB01, "Atmel AT91 EB01")
39 /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ 44 /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
40 .timer = &at91x40_timer, 45 .timer = &at91x40_timer,
41 .init_irq = at91x40_init_interrupts, 46 .init_irq = at91eb01_init_irq,
42 .map_io = at91eb01_map_io, 47 .map_io = at91eb01_map_io,
43MACHINE_END 48MACHINE_END
44 49
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 3bef931d0b1c..0700f2125305 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -27,6 +27,7 @@
27#define ARCH_ID_AT91SAM9G45 0x819b05a0 27#define ARCH_ID_AT91SAM9G45 0x819b05a0
28#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ 28#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
29#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ 29#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
30#define ARCH_ID_AT91SAM9X5 0x819a05a0
30#define ARCH_ID_AT91CAP9 0x039A03A0 31#define ARCH_ID_AT91CAP9 0x039A03A0
31 32
32#define ARCH_ID_AT91SAM9XE128 0x329973a0 33#define ARCH_ID_AT91SAM9XE128 0x329973a0
@@ -55,6 +56,12 @@ static inline unsigned long at91_cpu_fully_identify(void)
55#define ARCH_EXID_AT91SAM9G46 0x00000003 56#define ARCH_EXID_AT91SAM9G46 0x00000003
56#define ARCH_EXID_AT91SAM9G45 0x00000004 57#define ARCH_EXID_AT91SAM9G45 0x00000004
57 58
59#define ARCH_EXID_AT91SAM9G15 0x00000000
60#define ARCH_EXID_AT91SAM9G35 0x00000001
61#define ARCH_EXID_AT91SAM9X35 0x00000002
62#define ARCH_EXID_AT91SAM9G25 0x00000003
63#define ARCH_EXID_AT91SAM9X25 0x00000004
64
58static inline unsigned long at91_exid_identify(void) 65static inline unsigned long at91_exid_identify(void)
59{ 66{
60 return at91_sys_read(AT91_DBGU_EXID); 67 return at91_sys_read(AT91_DBGU_EXID);
@@ -143,6 +150,27 @@ static inline unsigned long at91cap9_rev_identify(void)
143#define cpu_is_at91sam9m11() (0) 150#define cpu_is_at91sam9m11() (0)
144#endif 151#endif
145 152
153#ifdef CONFIG_ARCH_AT91SAM9X5
154#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
155#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
156 (at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
157#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
158 (at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
159#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
160 (at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
161#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
162 (at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
163#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
164 (at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
165#else
166#define cpu_is_at91sam9x5() (0)
167#define cpu_is_at91sam9g15() (0)
168#define cpu_is_at91sam9g35() (0)
169#define cpu_is_at91sam9x35() (0)
170#define cpu_is_at91sam9g25() (0)
171#define cpu_is_at91sam9x25() (0)
172#endif
173
146#ifdef CONFIG_ARCH_AT91CAP9 174#ifdef CONFIG_ARCH_AT91CAP9
147#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) 175#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
148#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) 176#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig
deleted file mode 100644
index 33569e4007c4..000000000000
--- a/arch/arm/mach-s5p6442/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
1# arch/arm/mach-s5p6442/Kconfig
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8# Configuration options for the S5P6442
9
10if ARCH_S5P6442
11
12config CPU_S5P6442
13 bool
14 select S3C_PL330_DMA
15 help
16 Enable S5P6442 CPU support
17
18config MACH_SMDK6442
19 bool "SMDK6442"
20 select CPU_S5P6442
21 select S3C_DEV_WDT
22 help
23 Machine support for Samsung SMDK6442
24
25endif
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile
deleted file mode 100644
index 90a3d8373416..000000000000
--- a/arch/arm/mach-s5p6442/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
1# arch/arm/mach-s5p6442/Makefile
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5P6442 system
14
15obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o
17
18# machine support
19
20obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o
21
22# device support
23obj-y += dev-audio.o
24obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
diff --git a/arch/arm/mach-s5p6442/Makefile.boot b/arch/arm/mach-s5p6442/Makefile.boot
deleted file mode 100644
index ff90aa13bd67..000000000000
--- a/arch/arm/mach-s5p6442/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y := 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
deleted file mode 100644
index fbbc7bede685..000000000000
--- a/arch/arm/mach-s5p6442/clock.c
+++ /dev/null
@@ -1,420 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/map.h>
22
23#include <plat/cpu-freq.h>
24#include <mach/regs-clock.h>
25#include <plat/clock.h>
26#include <plat/cpu.h>
27#include <plat/pll.h>
28#include <plat/s5p-clock.h>
29#include <plat/clock-clksrc.h>
30#include <plat/s5p6442.h>
31
32static struct clksrc_clk clk_mout_apll = {
33 .clk = {
34 .name = "mout_apll",
35 .id = -1,
36 },
37 .sources = &clk_src_apll,
38 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
39};
40
41static struct clksrc_clk clk_mout_mpll = {
42 .clk = {
43 .name = "mout_mpll",
44 .id = -1,
45 },
46 .sources = &clk_src_mpll,
47 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
48};
49
50static struct clksrc_clk clk_mout_epll = {
51 .clk = {
52 .name = "mout_epll",
53 .id = -1,
54 },
55 .sources = &clk_src_epll,
56 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
57};
58
59/* Possible clock sources for ARM Mux */
60static struct clk *clk_src_arm_list[] = {
61 [1] = &clk_mout_apll.clk,
62 [2] = &clk_mout_mpll.clk,
63};
64
65static struct clksrc_sources clk_src_arm = {
66 .sources = clk_src_arm_list,
67 .nr_sources = ARRAY_SIZE(clk_src_arm_list),
68};
69
70static struct clksrc_clk clk_mout_arm = {
71 .clk = {
72 .name = "mout_arm",
73 .id = -1,
74 },
75 .sources = &clk_src_arm,
76 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
77};
78
79static struct clk clk_dout_a2m = {
80 .name = "dout_a2m",
81 .id = -1,
82 .parent = &clk_mout_apll.clk,
83};
84
85/* Possible clock sources for D0 Mux */
86static struct clk *clk_src_d0_list[] = {
87 [1] = &clk_mout_mpll.clk,
88 [2] = &clk_dout_a2m,
89};
90
91static struct clksrc_sources clk_src_d0 = {
92 .sources = clk_src_d0_list,
93 .nr_sources = ARRAY_SIZE(clk_src_d0_list),
94};
95
96static struct clksrc_clk clk_mout_d0 = {
97 .clk = {
98 .name = "mout_d0",
99 .id = -1,
100 },
101 .sources = &clk_src_d0,
102 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 },
103};
104
105static struct clk clk_dout_apll = {
106 .name = "dout_apll",
107 .id = -1,
108 .parent = &clk_mout_arm.clk,
109};
110
111/* Possible clock sources for D0SYNC Mux */
112static struct clk *clk_src_d0sync_list[] = {
113 [1] = &clk_mout_d0.clk,
114 [2] = &clk_dout_apll,
115};
116
117static struct clksrc_sources clk_src_d0sync = {
118 .sources = clk_src_d0sync_list,
119 .nr_sources = ARRAY_SIZE(clk_src_d0sync_list),
120};
121
122static struct clksrc_clk clk_mout_d0sync = {
123 .clk = {
124 .name = "mout_d0sync",
125 .id = -1,
126 },
127 .sources = &clk_src_d0sync,
128 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
129};
130
131/* Possible clock sources for D1 Mux */
132static struct clk *clk_src_d1_list[] = {
133 [1] = &clk_mout_mpll.clk,
134 [2] = &clk_dout_a2m,
135};
136
137static struct clksrc_sources clk_src_d1 = {
138 .sources = clk_src_d1_list,
139 .nr_sources = ARRAY_SIZE(clk_src_d1_list),
140};
141
142static struct clksrc_clk clk_mout_d1 = {
143 .clk = {
144 .name = "mout_d1",
145 .id = -1,
146 },
147 .sources = &clk_src_d1,
148 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 },
149};
150
151/* Possible clock sources for D1SYNC Mux */
152static struct clk *clk_src_d1sync_list[] = {
153 [1] = &clk_mout_d1.clk,
154 [2] = &clk_dout_apll,
155};
156
157static struct clksrc_sources clk_src_d1sync = {
158 .sources = clk_src_d1sync_list,
159 .nr_sources = ARRAY_SIZE(clk_src_d1sync_list),
160};
161
162static struct clksrc_clk clk_mout_d1sync = {
163 .clk = {
164 .name = "mout_d1sync",
165 .id = -1,
166 },
167 .sources = &clk_src_d1sync,
168 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
169};
170
171static struct clk clk_hclkd0 = {
172 .name = "hclkd0",
173 .id = -1,
174 .parent = &clk_mout_d0sync.clk,
175};
176
177static struct clk clk_hclkd1 = {
178 .name = "hclkd1",
179 .id = -1,
180 .parent = &clk_mout_d1sync.clk,
181};
182
183static struct clk clk_pclkd0 = {
184 .name = "pclkd0",
185 .id = -1,
186 .parent = &clk_hclkd0,
187};
188
189static struct clk clk_pclkd1 = {
190 .name = "pclkd1",
191 .id = -1,
192 .parent = &clk_hclkd1,
193};
194
195int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
196{
197 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
198}
199
200int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
201{
202 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
203}
204
205static struct clksrc_clk clksrcs[] = {
206 {
207 .clk = {
208 .name = "dout_a2m",
209 .id = -1,
210 .parent = &clk_mout_apll.clk,
211 },
212 .sources = &clk_src_apll,
213 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
214 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
215 }, {
216 .clk = {
217 .name = "dout_apll",
218 .id = -1,
219 .parent = &clk_mout_arm.clk,
220 },
221 .sources = &clk_src_arm,
222 .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
223 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
224 }, {
225 .clk = {
226 .name = "hclkd1",
227 .id = -1,
228 .parent = &clk_mout_d1sync.clk,
229 },
230 .sources = &clk_src_d1sync,
231 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
232 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
233 }, {
234 .clk = {
235 .name = "hclkd0",
236 .id = -1,
237 .parent = &clk_mout_d0sync.clk,
238 },
239 .sources = &clk_src_d0sync,
240 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
241 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
242 }, {
243 .clk = {
244 .name = "pclkd0",
245 .id = -1,
246 .parent = &clk_hclkd0,
247 },
248 .sources = &clk_src_d0sync,
249 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
250 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
251 }, {
252 .clk = {
253 .name = "pclkd1",
254 .id = -1,
255 .parent = &clk_hclkd1,
256 },
257 .sources = &clk_src_d1sync,
258 .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
259 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
260 }
261};
262
263/* Clock initialisation code */
264static struct clksrc_clk *init_parents[] = {
265 &clk_mout_apll,
266 &clk_mout_mpll,
267 &clk_mout_epll,
268 &clk_mout_arm,
269 &clk_mout_d0,
270 &clk_mout_d0sync,
271 &clk_mout_d1,
272 &clk_mout_d1sync,
273};
274
275void __init_or_cpufreq s5p6442_setup_clocks(void)
276{
277 struct clk *pclkd0_clk;
278 struct clk *pclkd1_clk;
279
280 unsigned long xtal;
281 unsigned long arm;
282 unsigned long hclkd0 = 0;
283 unsigned long hclkd1 = 0;
284 unsigned long pclkd0 = 0;
285 unsigned long pclkd1 = 0;
286
287 unsigned long apll;
288 unsigned long mpll;
289 unsigned long epll;
290 unsigned int ptr;
291
292 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
293
294 xtal = clk_get_rate(&clk_xtal);
295
296 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
297
298 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
299 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
300 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
301
302 printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
303 apll, mpll, epll);
304
305 clk_fout_apll.rate = apll;
306 clk_fout_mpll.rate = mpll;
307 clk_fout_epll.rate = epll;
308
309 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
310 s3c_set_clksrc(init_parents[ptr], true);
311
312 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
313 s3c_set_clksrc(&clksrcs[ptr], true);
314
315 arm = clk_get_rate(&clk_dout_apll);
316 hclkd0 = clk_get_rate(&clk_hclkd0);
317 hclkd1 = clk_get_rate(&clk_hclkd1);
318
319 pclkd0_clk = clk_get(NULL, "pclkd0");
320 BUG_ON(IS_ERR(pclkd0_clk));
321
322 pclkd0 = clk_get_rate(pclkd0_clk);
323 clk_put(pclkd0_clk);
324
325 pclkd1_clk = clk_get(NULL, "pclkd1");
326 BUG_ON(IS_ERR(pclkd1_clk));
327
328 pclkd1 = clk_get_rate(pclkd1_clk);
329 clk_put(pclkd1_clk);
330
331 printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
332 hclkd0, hclkd1, pclkd0, pclkd1);
333
334 /* For backward compatibility */
335 clk_f.rate = arm;
336 clk_h.rate = hclkd1;
337 clk_p.rate = pclkd1;
338
339 clk_pclkd0.rate = pclkd0;
340 clk_pclkd1.rate = pclkd1;
341}
342
343static struct clk init_clocks_off[] = {
344 {
345 .name = "pdma",
346 .id = -1,
347 .parent = &clk_pclkd1,
348 .enable = s5p6442_clk_ip0_ctrl,
349 .ctrlbit = (1 << 3),
350 },
351};
352
353static struct clk init_clocks[] = {
354 {
355 .name = "systimer",
356 .id = -1,
357 .parent = &clk_pclkd1,
358 .enable = s5p6442_clk_ip3_ctrl,
359 .ctrlbit = (1<<16),
360 }, {
361 .name = "uart",
362 .id = 0,
363 .parent = &clk_pclkd1,
364 .enable = s5p6442_clk_ip3_ctrl,
365 .ctrlbit = (1<<17),
366 }, {
367 .name = "uart",
368 .id = 1,
369 .parent = &clk_pclkd1,
370 .enable = s5p6442_clk_ip3_ctrl,
371 .ctrlbit = (1<<18),
372 }, {
373 .name = "uart",
374 .id = 2,
375 .parent = &clk_pclkd1,
376 .enable = s5p6442_clk_ip3_ctrl,
377 .ctrlbit = (1<<19),
378 }, {
379 .name = "watchdog",
380 .id = -1,
381 .parent = &clk_pclkd1,
382 .enable = s5p6442_clk_ip3_ctrl,
383 .ctrlbit = (1 << 22),
384 }, {
385 .name = "timers",
386 .id = -1,
387 .parent = &clk_pclkd1,
388 .enable = s5p6442_clk_ip3_ctrl,
389 .ctrlbit = (1<<23),
390 },
391};
392
393static struct clk *clks[] __initdata = {
394 &clk_ext,
395 &clk_epll,
396 &clk_mout_apll.clk,
397 &clk_mout_mpll.clk,
398 &clk_mout_epll.clk,
399 &clk_mout_d0.clk,
400 &clk_mout_d0sync.clk,
401 &clk_mout_d1.clk,
402 &clk_mout_d1sync.clk,
403 &clk_hclkd0,
404 &clk_pclkd0,
405 &clk_hclkd1,
406 &clk_pclkd1,
407};
408
409void __init s5p6442_register_clocks(void)
410{
411 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
412
413 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
414 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
415
416 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
417 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
418
419 s3c_pwmclk_init();
420}
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
deleted file mode 100644
index 842af86bda6d..000000000000
--- a/arch/arm/mach-s5p6442/cpu.c
+++ /dev/null
@@ -1,143 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/cpu.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <asm/proc-fns.h>
29
30#include <mach/hardware.h>
31#include <mach/map.h>
32#include <asm/irq.h>
33
34#include <plat/regs-serial.h>
35#include <mach/regs-clock.h>
36
37#include <plat/cpu.h>
38#include <plat/devs.h>
39#include <plat/clock.h>
40#include <plat/s5p6442.h>
41
42/* Initial IO mappings */
43
44static struct map_desc s5p6442_iodesc[] __initdata = {
45 {
46 .virtual = (unsigned long)S5P_VA_SYSTIMER,
47 .pfn = __phys_to_pfn(S5P6442_PA_SYSTIMER),
48 .length = SZ_16K,
49 .type = MT_DEVICE,
50 }, {
51 .virtual = (unsigned long)S5P_VA_GPIO,
52 .pfn = __phys_to_pfn(S5P6442_PA_GPIO),
53 .length = SZ_4K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = (unsigned long)VA_VIC0,
57 .pfn = __phys_to_pfn(S5P6442_PA_VIC0),
58 .length = SZ_16K,
59 .type = MT_DEVICE,
60 }, {
61 .virtual = (unsigned long)VA_VIC1,
62 .pfn = __phys_to_pfn(S5P6442_PA_VIC1),
63 .length = SZ_16K,
64 .type = MT_DEVICE,
65 }, {
66 .virtual = (unsigned long)VA_VIC2,
67 .pfn = __phys_to_pfn(S5P6442_PA_VIC2),
68 .length = SZ_16K,
69 .type = MT_DEVICE,
70 }, {
71 .virtual = (unsigned long)S3C_VA_UART,
72 .pfn = __phys_to_pfn(S3C_PA_UART),
73 .length = SZ_512K,
74 .type = MT_DEVICE,
75 }
76};
77
78static void s5p6442_idle(void)
79{
80 if (!need_resched())
81 cpu_do_idle();
82
83 local_irq_enable();
84}
85
86/*
87 * s5p6442_map_io
88 *
89 * register the standard cpu IO areas
90 */
91
92void __init s5p6442_map_io(void)
93{
94 iotable_init(s5p6442_iodesc, ARRAY_SIZE(s5p6442_iodesc));
95}
96
97void __init s5p6442_init_clocks(int xtal)
98{
99 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
100
101 s3c24xx_register_baseclocks(xtal);
102 s5p_register_clocks(xtal);
103 s5p6442_register_clocks();
104 s5p6442_setup_clocks();
105}
106
107void __init s5p6442_init_irq(void)
108{
109 /* S5P6442 supports 3 VIC */
110 u32 vic[3];
111
112 /* VIC0, VIC1, and VIC2: some interrupt reserved */
113 vic[0] = 0x7fefffff;
114 vic[1] = 0X7f389c81;
115 vic[2] = 0X1bbbcfff;
116
117 s5p_init_irq(vic, ARRAY_SIZE(vic));
118}
119
120struct sysdev_class s5p6442_sysclass = {
121 .name = "s5p6442-core",
122};
123
124static struct sys_device s5p6442_sysdev = {
125 .cls = &s5p6442_sysclass,
126};
127
128static int __init s5p6442_core_init(void)
129{
130 return sysdev_class_register(&s5p6442_sysclass);
131}
132
133core_initcall(s5p6442_core_init);
134
135int __init s5p6442_init(void)
136{
137 printk(KERN_INFO "S5P6442: Initializing architecture\n");
138
139 /* set idle function */
140 pm_idle = s5p6442_idle;
141
142 return sysdev_register(&s5p6442_sysdev);
143}
diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c
deleted file mode 100644
index 8719dc41fe32..000000000000
--- a/arch/arm/mach-s5p6442/dev-audio.c
+++ /dev/null
@@ -1,217 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6442_cfg_i2s(struct platform_device *pdev)
23{
24 unsigned int base;
25
26 /* configure GPIO for i2s port */
27 switch (pdev->id) {
28 case 1:
29 base = S5P6442_GPC1(0);
30 break;
31
32 case 0:
33 base = S5P6442_GPC0(0);
34 break;
35
36 default:
37 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
38 return -EINVAL;
39 }
40
41 s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
42 return 0;
43}
44
45static const char *rclksrc_v35[] = {
46 [0] = "busclk",
47 [1] = "i2sclk",
48};
49
50static struct s3c_audio_pdata i2sv35_pdata = {
51 .cfg_gpio = s5p6442_cfg_i2s,
52 .type = {
53 .i2s = {
54 .quirks = QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR,
55 .src_clk = rclksrc_v35,
56 },
57 },
58};
59
60static struct resource s5p6442_iis0_resource[] = {
61 [0] = {
62 .start = S5P6442_PA_I2S0,
63 .end = S5P6442_PA_I2S0 + 0x100 - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = DMACH_I2S0_TX,
68 .end = DMACH_I2S0_TX,
69 .flags = IORESOURCE_DMA,
70 },
71 [2] = {
72 .start = DMACH_I2S0_RX,
73 .end = DMACH_I2S0_RX,
74 .flags = IORESOURCE_DMA,
75 },
76 [3] = {
77 .start = DMACH_I2S0S_TX,
78 .end = DMACH_I2S0S_TX,
79 .flags = IORESOURCE_DMA,
80 },
81};
82
83struct platform_device s5p6442_device_iis0 = {
84 .name = "samsung-i2s",
85 .id = 0,
86 .num_resources = ARRAY_SIZE(s5p6442_iis0_resource),
87 .resource = s5p6442_iis0_resource,
88 .dev = {
89 .platform_data = &i2sv35_pdata,
90 },
91};
92
93static const char *rclksrc_v3[] = {
94 [0] = "iis",
95 [1] = "sclk_audio",
96};
97
98static struct s3c_audio_pdata i2sv3_pdata = {
99 .cfg_gpio = s5p6442_cfg_i2s,
100 .type = {
101 .i2s = {
102 .src_clk = rclksrc_v3,
103 },
104 },
105};
106
107static struct resource s5p6442_iis1_resource[] = {
108 [0] = {
109 .start = S5P6442_PA_I2S1,
110 .end = S5P6442_PA_I2S1 + 0x100 - 1,
111 .flags = IORESOURCE_MEM,
112 },
113 [1] = {
114 .start = DMACH_I2S1_TX,
115 .end = DMACH_I2S1_TX,
116 .flags = IORESOURCE_DMA,
117 },
118 [2] = {
119 .start = DMACH_I2S1_RX,
120 .end = DMACH_I2S1_RX,
121 .flags = IORESOURCE_DMA,
122 },
123};
124
125struct platform_device s5p6442_device_iis1 = {
126 .name = "samsung-i2s",
127 .id = 1,
128 .num_resources = ARRAY_SIZE(s5p6442_iis1_resource),
129 .resource = s5p6442_iis1_resource,
130 .dev = {
131 .platform_data = &i2sv3_pdata,
132 },
133};
134
135/* PCM Controller platform_devices */
136
137static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
138{
139 unsigned int base;
140
141 switch (pdev->id) {
142 case 0:
143 base = S5P6442_GPC0(0);
144 break;
145
146 case 1:
147 base = S5P6442_GPC1(0);
148 break;
149
150 default:
151 printk(KERN_DEBUG "Invalid PCM Controller number!");
152 return -EINVAL;
153 }
154
155 s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
156 return 0;
157}
158
159static struct s3c_audio_pdata s3c_pcm_pdata = {
160 .cfg_gpio = s5p6442_pcm_cfg_gpio,
161};
162
163static struct resource s5p6442_pcm0_resource[] = {
164 [0] = {
165 .start = S5P6442_PA_PCM0,
166 .end = S5P6442_PA_PCM0 + 0x100 - 1,
167 .flags = IORESOURCE_MEM,
168 },
169 [1] = {
170 .start = DMACH_PCM0_TX,
171 .end = DMACH_PCM0_TX,
172 .flags = IORESOURCE_DMA,
173 },
174 [2] = {
175 .start = DMACH_PCM0_RX,
176 .end = DMACH_PCM0_RX,
177 .flags = IORESOURCE_DMA,
178 },
179};
180
181struct platform_device s5p6442_device_pcm0 = {
182 .name = "samsung-pcm",
183 .id = 0,
184 .num_resources = ARRAY_SIZE(s5p6442_pcm0_resource),
185 .resource = s5p6442_pcm0_resource,
186 .dev = {
187 .platform_data = &s3c_pcm_pdata,
188 },
189};
190
191static struct resource s5p6442_pcm1_resource[] = {
192 [0] = {
193 .start = S5P6442_PA_PCM1,
194 .end = S5P6442_PA_PCM1 + 0x100 - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 [1] = {
198 .start = DMACH_PCM1_TX,
199 .end = DMACH_PCM1_TX,
200 .flags = IORESOURCE_DMA,
201 },
202 [2] = {
203 .start = DMACH_PCM1_RX,
204 .end = DMACH_PCM1_RX,
205 .flags = IORESOURCE_DMA,
206 },
207};
208
209struct platform_device s5p6442_device_pcm1 = {
210 .name = "samsung-pcm",
211 .id = 1,
212 .num_resources = ARRAY_SIZE(s5p6442_pcm1_resource),
213 .resource = s5p6442_pcm1_resource,
214 .dev = {
215 .platform_data = &s3c_pcm_pdata,
216 },
217};
diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c
deleted file mode 100644
index cce8c2470709..000000000000
--- a/arch/arm/mach-s5p6442/dev-spi.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5P6442_SPI_SRCCLK_PCLK] = "pclk",
25 [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
37{
38 switch (pdev->id) {
39 case 0:
40 s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
41 s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
42 s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
43 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
44 break;
45
46 default:
47 dev_err(&pdev->dev, "Invalid SPI Controller number!");
48 return -EINVAL;
49 }
50
51 return 0;
52}
53
54static struct resource s5p6442_spi0_resource[] = {
55 [0] = {
56 .start = S5P6442_PA_SPI,
57 .end = S5P6442_PA_SPI + 0x100 - 1,
58 .flags = IORESOURCE_MEM,
59 },
60 [1] = {
61 .start = DMACH_SPI0_TX,
62 .end = DMACH_SPI0_TX,
63 .flags = IORESOURCE_DMA,
64 },
65 [2] = {
66 .start = DMACH_SPI0_RX,
67 .end = DMACH_SPI0_RX,
68 .flags = IORESOURCE_DMA,
69 },
70 [3] = {
71 .start = IRQ_SPI0,
72 .end = IRQ_SPI0,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77static struct s3c64xx_spi_info s5p6442_spi0_pdata = {
78 .cfg_gpio = s5p6442_spi_cfg_gpio,
79 .fifo_lvl_mask = 0x1ff,
80 .rx_lvl_offset = 15,
81};
82
83static u64 spi_dmamask = DMA_BIT_MASK(32);
84
85struct platform_device s5p6442_device_spi = {
86 .name = "s3c64xx-spi",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(s5p6442_spi0_resource),
89 .resource = s5p6442_spi0_resource,
90 .dev = {
91 .dma_mask = &spi_dmamask,
92 .coherent_dma_mask = DMA_BIT_MASK(32),
93 .platform_data = &s5p6442_spi0_pdata,
94 },
95};
96
97void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
98{
99 struct s3c64xx_spi_info *pd;
100
101 /* Reject invalid configuration */
102 if (!num_cs || src_clk_nr < 0
103 || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) {
104 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
105 return;
106 }
107
108 switch (cntrlr) {
109 case 0:
110 pd = &s5p6442_spi0_pdata;
111 break;
112 default:
113 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
114 __func__, cntrlr);
115 return;
116 }
117
118 pd->num_cs = num_cs;
119 pd->src_clk_nr = src_clk_nr;
120 pd->src_clk_name = spi_src_clks[src_clk_nr];
121}
diff --git a/arch/arm/mach-s5p6442/dma.c b/arch/arm/mach-s5p6442/dma.c
deleted file mode 100644
index 7dfb13654f8a..000000000000
--- a/arch/arm/mach-s5p6442/dma.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h>
27#include <mach/irqs.h>
28
29#include <plat/s3c-pl330-pdata.h>
30
31static u64 dma_dmamask = DMA_BIT_MASK(32);
32
33static struct resource s5p6442_pdma_resource[] = {
34 [0] = {
35 .start = S5P6442_PA_PDMA,
36 .end = S5P6442_PA_PDMA + SZ_4K,
37 .flags = IORESOURCE_MEM,
38 },
39 [1] = {
40 .start = IRQ_PDMA,
41 .end = IRQ_PDMA,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
47 .peri = {
48 [0] = DMACH_UART0_RX,
49 [1] = DMACH_UART0_TX,
50 [2] = DMACH_UART1_RX,
51 [3] = DMACH_UART1_TX,
52 [4] = DMACH_UART2_RX,
53 [5] = DMACH_UART2_TX,
54 [6] = DMACH_MAX,
55 [7] = DMACH_MAX,
56 [8] = DMACH_MAX,
57 [9] = DMACH_I2S0_RX,
58 [10] = DMACH_I2S0_TX,
59 [11] = DMACH_I2S0S_TX,
60 [12] = DMACH_I2S1_RX,
61 [13] = DMACH_I2S1_TX,
62 [14] = DMACH_MAX,
63 [15] = DMACH_MAX,
64 [16] = DMACH_SPI0_RX,
65 [17] = DMACH_SPI0_TX,
66 [18] = DMACH_MAX,
67 [19] = DMACH_MAX,
68 [20] = DMACH_PCM0_RX,
69 [21] = DMACH_PCM0_TX,
70 [22] = DMACH_PCM1_RX,
71 [23] = DMACH_PCM1_TX,
72 [24] = DMACH_MAX,
73 [25] = DMACH_MAX,
74 [26] = DMACH_MAX,
75 [27] = DMACH_MSM_REQ0,
76 [28] = DMACH_MSM_REQ1,
77 [29] = DMACH_MSM_REQ2,
78 [30] = DMACH_MSM_REQ3,
79 [31] = DMACH_MAX,
80 },
81};
82
83static struct platform_device s5p6442_device_pdma = {
84 .name = "s3c-pl330",
85 .id = -1,
86 .num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
87 .resource = s5p6442_pdma_resource,
88 .dev = {
89 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5p6442_pdma_pdata,
92 },
93};
94
95static struct platform_device *s5p6442_dmacs[] __initdata = {
96 &s5p6442_device_pdma,
97};
98
99static int __init s5p6442_dma_init(void)
100{
101 platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
102
103 return 0;
104}
105arch_initcall(s5p6442_dma_init);
diff --git a/arch/arm/mach-s5p6442/include/mach/debug-macro.S b/arch/arm/mach-s5p6442/include/mach/debug-macro.S
deleted file mode 100644
index e2213205d780..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/debug-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* pull in the relevant register and map files. */
14
15#include <mach/map.h>
16#include <plat/regs-serial.h>
17
18 .macro addruart, rp, rv
19 ldr \rp, = S3C_PA_UART
20 ldr \rv, = S3C_VA_UART
21#if CONFIG_DEBUG_S3C_UART != 0
22 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
23 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
24#endif
25 .endm
26
27#define fifo_full fifo_full_s5pv210
28#define fifo_level fifo_level_s5pv210
29
30/* include the reset of the code which will do the work, we're only
31 * compiling for a single cpu processor type so the default of s3c2440
32 * will be fine with us.
33 */
34
35#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6442/include/mach/dma.h b/arch/arm/mach-s5p6442/include/mach/dma.h
deleted file mode 100644
index 81209eb1409b..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common S3C DMA API driver for PL330 */
24#include <plat/s3c-dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/entry-macro.S b/arch/arm/mach-s5p6442/include/mach/entry-macro.S
deleted file mode 100644
index 6d574edbf1ae..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/entry-macro.S
+++ /dev/null
@@ -1,48 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/entry-macro.S
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Low-level IRQ helper macros for the Samsung S5P6442
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <asm/hardware/vic.h>
14#include <mach/map.h>
15#include <plat/irqs.h>
16
17 .macro disable_fiq
18 .endm
19
20 .macro get_irqnr_preamble, base, tmp
21 ldr \base, =VA_VIC0
22 .endm
23
24 .macro arch_ret_to_user, tmp1, tmp2
25 .endm
26
27 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
28
29 @ check the vic0
30 mov \irqnr, # S5P_IRQ_OFFSET + 31
31 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
32 teq \irqstat, #0
33
34 @ otherwise try vic1
35 addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
36 addeq \irqnr, \irqnr, #32
37 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
38 teqeq \irqstat, #0
39
40 @ otherwise try vic2
41 addeq \tmp, \base, #(VA_VIC2 - VA_VIC0)
42 addeq \irqnr, \irqnr, #32
43 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
44 teqeq \irqstat, #0
45
46 clzne \irqstat, \irqstat
47 subne \irqnr, \irqnr, \irqstat
48 .endm
diff --git a/arch/arm/mach-s5p6442/include/mach/gpio.h b/arch/arm/mach-s5p6442/include/mach/gpio.h
deleted file mode 100644
index b8715df2fdab..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/gpio.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22#define S5P6442_GPIO_A0_NR (8)
23#define S5P6442_GPIO_A1_NR (2)
24#define S5P6442_GPIO_B_NR (4)
25#define S5P6442_GPIO_C0_NR (5)
26#define S5P6442_GPIO_C1_NR (5)
27#define S5P6442_GPIO_D0_NR (2)
28#define S5P6442_GPIO_D1_NR (6)
29#define S5P6442_GPIO_E0_NR (8)
30#define S5P6442_GPIO_E1_NR (5)
31#define S5P6442_GPIO_F0_NR (8)
32#define S5P6442_GPIO_F1_NR (8)
33#define S5P6442_GPIO_F2_NR (8)
34#define S5P6442_GPIO_F3_NR (6)
35#define S5P6442_GPIO_G0_NR (7)
36#define S5P6442_GPIO_G1_NR (7)
37#define S5P6442_GPIO_G2_NR (7)
38#define S5P6442_GPIO_H0_NR (8)
39#define S5P6442_GPIO_H1_NR (8)
40#define S5P6442_GPIO_H2_NR (8)
41#define S5P6442_GPIO_H3_NR (8)
42#define S5P6442_GPIO_J0_NR (8)
43#define S5P6442_GPIO_J1_NR (6)
44#define S5P6442_GPIO_J2_NR (8)
45#define S5P6442_GPIO_J3_NR (8)
46#define S5P6442_GPIO_J4_NR (5)
47
48/* GPIO bank numbers */
49
50/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
51 * space for debugging purposes so that any accidental
52 * change from one gpio bank to another can be caught.
53*/
54
55#define S5P6442_GPIO_NEXT(__gpio) \
56 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
57
58enum s5p_gpio_number {
59 S5P6442_GPIO_A0_START = 0,
60 S5P6442_GPIO_A1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0),
61 S5P6442_GPIO_B_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1),
62 S5P6442_GPIO_C0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_B),
63 S5P6442_GPIO_C1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0),
64 S5P6442_GPIO_D0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1),
65 S5P6442_GPIO_D1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0),
66 S5P6442_GPIO_E0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1),
67 S5P6442_GPIO_E1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0),
68 S5P6442_GPIO_F0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1),
69 S5P6442_GPIO_F1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0),
70 S5P6442_GPIO_F2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1),
71 S5P6442_GPIO_F3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2),
72 S5P6442_GPIO_G0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3),
73 S5P6442_GPIO_G1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0),
74 S5P6442_GPIO_G2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1),
75 S5P6442_GPIO_H0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2),
76 S5P6442_GPIO_H1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0),
77 S5P6442_GPIO_H2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1),
78 S5P6442_GPIO_H3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2),
79 S5P6442_GPIO_J0_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3),
80 S5P6442_GPIO_J1_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0),
81 S5P6442_GPIO_J2_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1),
82 S5P6442_GPIO_J3_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2),
83 S5P6442_GPIO_J4_START = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3),
84};
85
86/* S5P6442 GPIO number definitions. */
87#define S5P6442_GPA0(_nr) (S5P6442_GPIO_A0_START + (_nr))
88#define S5P6442_GPA1(_nr) (S5P6442_GPIO_A1_START + (_nr))
89#define S5P6442_GPB(_nr) (S5P6442_GPIO_B_START + (_nr))
90#define S5P6442_GPC0(_nr) (S5P6442_GPIO_C0_START + (_nr))
91#define S5P6442_GPC1(_nr) (S5P6442_GPIO_C1_START + (_nr))
92#define S5P6442_GPD0(_nr) (S5P6442_GPIO_D0_START + (_nr))
93#define S5P6442_GPD1(_nr) (S5P6442_GPIO_D1_START + (_nr))
94#define S5P6442_GPE0(_nr) (S5P6442_GPIO_E0_START + (_nr))
95#define S5P6442_GPE1(_nr) (S5P6442_GPIO_E1_START + (_nr))
96#define S5P6442_GPF0(_nr) (S5P6442_GPIO_F0_START + (_nr))
97#define S5P6442_GPF1(_nr) (S5P6442_GPIO_F1_START + (_nr))
98#define S5P6442_GPF2(_nr) (S5P6442_GPIO_F2_START + (_nr))
99#define S5P6442_GPF3(_nr) (S5P6442_GPIO_F3_START + (_nr))
100#define S5P6442_GPG0(_nr) (S5P6442_GPIO_G0_START + (_nr))
101#define S5P6442_GPG1(_nr) (S5P6442_GPIO_G1_START + (_nr))
102#define S5P6442_GPG2(_nr) (S5P6442_GPIO_G2_START + (_nr))
103#define S5P6442_GPH0(_nr) (S5P6442_GPIO_H0_START + (_nr))
104#define S5P6442_GPH1(_nr) (S5P6442_GPIO_H1_START + (_nr))
105#define S5P6442_GPH2(_nr) (S5P6442_GPIO_H2_START + (_nr))
106#define S5P6442_GPH3(_nr) (S5P6442_GPIO_H3_START + (_nr))
107#define S5P6442_GPJ0(_nr) (S5P6442_GPIO_J0_START + (_nr))
108#define S5P6442_GPJ1(_nr) (S5P6442_GPIO_J1_START + (_nr))
109#define S5P6442_GPJ2(_nr) (S5P6442_GPIO_J2_START + (_nr))
110#define S5P6442_GPJ3(_nr) (S5P6442_GPIO_J3_START + (_nr))
111#define S5P6442_GPJ4(_nr) (S5P6442_GPIO_J4_START + (_nr))
112
113/* the end of the S5P6442 specific gpios */
114#define S5P6442_GPIO_END (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1)
115#define S3C_GPIO_END S5P6442_GPIO_END
116
117/* define the number of gpios we need to the one after the GPJ4() range */
118#define ARCH_NR_GPIOS (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + \
119 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
120
121#include <asm-generic/gpio.h>
122
123#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/hardware.h b/arch/arm/mach-s5p6442/include/mach/hardware.h
deleted file mode 100644
index 8cd7b67b49d4..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/hardware.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h
deleted file mode 100644
index 5d2195ad0b67..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/io.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-s5p6442/include/mach/io.h
2 *
3 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
4 *
5 * Default IO routines for S5P6442
6 */
7
8#ifndef __ASM_ARM_ARCH_IO_H
9#define __ASM_ARM_ARCH_IO_H
10
11/* No current ISA/PCI bus support. */
12#define __io(a) __typesafe_io(a)
13#define __mem_pci(a) (a)
14
15#define IO_SPACE_LIMIT (0xFFFFFFFF)
16
17#endif
diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h
deleted file mode 100644
index 3fbc6c3ad2da..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/irqs.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/irqs.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
20#define IRQ_BATF S5P_IRQ_VIC0(17)
21#define IRQ_MDMA S5P_IRQ_VIC0(18)
22#define IRQ_PDMA S5P_IRQ_VIC0(19)
23#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
24#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
25#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
26#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
27#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
28#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
29#define IRQ_WDT S5P_IRQ_VIC0(27)
30#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
31#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
32#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
33
34/* VIC1 */
35#define IRQ_PMU S5P_IRQ_VIC1(0)
36#define IRQ_ONENAND S5P_IRQ_VIC1(7)
37#define IRQ_UART0 S5P_IRQ_VIC1(10)
38#define IRQ_UART1 S5P_IRQ_VIC1(11)
39#define IRQ_UART2 S5P_IRQ_VIC1(12)
40#define IRQ_SPI0 S5P_IRQ_VIC1(15)
41#define IRQ_IIC S5P_IRQ_VIC1(19)
42#define IRQ_IIC1 S5P_IRQ_VIC1(20)
43#define IRQ_IIC2 S5P_IRQ_VIC1(21)
44#define IRQ_OTG S5P_IRQ_VIC1(24)
45#define IRQ_MSM S5P_IRQ_VIC1(25)
46#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
47#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
48#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
49#define IRQ_COMMRX S5P_IRQ_VIC1(29)
50#define IRQ_COMMTX S5P_IRQ_VIC1(30)
51
52/* VIC2 */
53#define IRQ_LCD0 S5P_IRQ_VIC2(0)
54#define IRQ_LCD1 S5P_IRQ_VIC2(1)
55#define IRQ_LCD2 S5P_IRQ_VIC2(2)
56#define IRQ_LCD3 S5P_IRQ_VIC2(3)
57#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
58#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
59#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
60#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
61#define IRQ_JPEG S5P_IRQ_VIC2(8)
62#define IRQ_3D S5P_IRQ_VIC2(10)
63#define IRQ_Mixer S5P_IRQ_VIC2(11)
64#define IRQ_MFC S5P_IRQ_VIC2(14)
65#define IRQ_TVENC S5P_IRQ_VIC2(15)
66#define IRQ_I2S0 S5P_IRQ_VIC2(16)
67#define IRQ_I2S1 S5P_IRQ_VIC2(17)
68#define IRQ_RP S5P_IRQ_VIC2(19)
69#define IRQ_PCM0 S5P_IRQ_VIC2(20)
70#define IRQ_PCM1 S5P_IRQ_VIC2(21)
71#define IRQ_ADC S5P_IRQ_VIC2(23)
72#define IRQ_PENDN S5P_IRQ_VIC2(24)
73#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
74#define IRQ_SSS_INT S5P_IRQ_VIC2(27)
75#define IRQ_SSS_HASH S5P_IRQ_VIC2(28)
76#define IRQ_VIC_END S5P_IRQ_VIC2(31)
77
78#define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1)
79
80#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
81#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE)
82
83/* Set the default NR_IRQS */
84
85#define NR_IRQS (IRQ_EINT(31) + 1)
86
87#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
deleted file mode 100644
index 058dab4482a1..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ /dev/null
@@ -1,76 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P6442_PA_SDRAM 0x20000000
20
21#define S5P6442_PA_I2S0 0xC0B00000
22#define S5P6442_PA_I2S1 0xF2200000
23
24#define S5P6442_PA_CHIPID 0xE0000000
25
26#define S5P6442_PA_SYSCON 0xE0100000
27
28#define S5P6442_PA_GPIO 0xE0200000
29
30#define S5P6442_PA_VIC0 0xE4000000
31#define S5P6442_PA_VIC1 0xE4100000
32#define S5P6442_PA_VIC2 0xE4200000
33
34#define S5P6442_PA_SROMC 0xE7000000
35
36#define S5P6442_PA_MDMA 0xE8000000
37#define S5P6442_PA_PDMA 0xE9000000
38
39#define S5P6442_PA_TIMER 0xEA000000
40
41#define S5P6442_PA_SYSTIMER 0xEA100000
42
43#define S5P6442_PA_WATCHDOG 0xEA200000
44
45#define S5P6442_PA_UART 0xEC000000
46
47#define S5P6442_PA_IIC0 0xEC100000
48
49#define S5P6442_PA_SPI 0xEC300000
50
51#define S5P6442_PA_PCM0 0xF2400000
52#define S5P6442_PA_PCM1 0xF2500000
53
54/* Compatibiltiy Defines */
55
56#define S3C_PA_IIC S5P6442_PA_IIC0
57#define S3C_PA_WDT S5P6442_PA_WATCHDOG
58
59#define S5P_PA_CHIPID S5P6442_PA_CHIPID
60#define S5P_PA_SDRAM S5P6442_PA_SDRAM
61#define S5P_PA_SROMC S5P6442_PA_SROMC
62#define S5P_PA_SYSCON S5P6442_PA_SYSCON
63#define S5P_PA_TIMER S5P6442_PA_TIMER
64
65/* UART */
66
67#define S3C_PA_UART S5P6442_PA_UART
68
69#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
70#define S5P_PA_UART0 S5P_PA_UART(0)
71#define S5P_PA_UART1 S5P_PA_UART(1)
72#define S5P_PA_UART2 S5P_PA_UART(2)
73
74#define S5P_SZ_UART SZ_256
75
76#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h
deleted file mode 100644
index cfe259dded33..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/memory.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PLAT_PHYS_OFFSET UL(0x20000000)
17#define CONSISTENT_DMA_SIZE SZ_8M
18
19#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
deleted file mode 100644
index 2724b37def31..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
12 *
13 * S5P6442 - pwm clock and timer support
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#ifndef __ASM_ARCH_PWMCLK_H
21#define __ASM_ARCH_PWMCLK_H __FILE__
22
23/**
24 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
25 * @tcfg: The timer TCFG1 register bits shifted down to 0.
26 *
27 * Return true if the given configuration from TCFG1 is a TCLK instead
28 * any of the TDIV clocks.
29 */
30static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
31{
32 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
33}
34
35/**
36 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
37 * @tcfg1: The tcfg1 setting, shifted down.
38 *
39 * Get the divisor value for the given tcfg1 setting. We assume the
40 * caller has already checked to see if this is not a TCLK source.
41 */
42static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
43{
44 return 1 << tcfg1;
45}
46
47/**
48 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
49 *
50 * Return true if we have a /1 in the tdiv setting.
51 */
52static inline unsigned int pwm_tdiv_has_div1(void)
53{
54 return 1;
55}
56
57/**
58 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
59 * @div: The divisor to calculate the bit information for.
60 *
61 * Turn a divisor into the necessary bit field for TCFG1.
62 */
63static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
64{
65 return ilog2(div);
66}
67
68#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
69
70#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
deleted file mode 100644
index 00828a336991..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/regs-clock.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
23#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
24
25#define S5P_APLL_CON S5P_CLKREG(0x100)
26#define S5P_MPLL_CON S5P_CLKREG(0x108)
27#define S5P_EPLL_CON S5P_CLKREG(0x110)
28#define S5P_VPLL_CON S5P_CLKREG(0x120)
29
30#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
31#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
32#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
33#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
34#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
35#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
36#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
37
38#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
39#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
40
41#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
42#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
43#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
44#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
45#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
46#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
47#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
48
49#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
50#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
51
52/* CLK_OUT */
53#define S5P_CLK_OUT_SHIFT (12)
54#define S5P_CLK_OUT_MASK (0x1F << S5P_CLK_OUT_SHIFT)
55#define S5P_CLK_OUT S5P_CLKREG(0x500)
56
57#define S5P_CLK_DIV_STAT0 S5P_CLKREG(0x1000)
58#define S5P_CLK_DIV_STAT1 S5P_CLKREG(0x1004)
59
60#define S5P_CLK_MUX_STAT0 S5P_CLKREG(0x1100)
61#define S5P_CLK_MUX_STAT1 S5P_CLKREG(0x1104)
62
63#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
64
65/* Register Bit definition */
66#define S5P_EPLL_EN (1<<31)
67#define S5P_EPLL_MASK 0xffffffff
68#define S5P_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
69
70/* CLKDIV0 */
71#define S5P_CLKDIV0_APLL_SHIFT (0)
72#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
73#define S5P_CLKDIV0_A2M_SHIFT (4)
74#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
75#define S5P_CLKDIV0_D0CLK_SHIFT (16)
76#define S5P_CLKDIV0_D0CLK_MASK (0xF << S5P_CLKDIV0_D0CLK_SHIFT)
77#define S5P_CLKDIV0_P0CLK_SHIFT (20)
78#define S5P_CLKDIV0_P0CLK_MASK (0x7 << S5P_CLKDIV0_P0CLK_SHIFT)
79#define S5P_CLKDIV0_D1CLK_SHIFT (24)
80#define S5P_CLKDIV0_D1CLK_MASK (0xF << S5P_CLKDIV0_D1CLK_SHIFT)
81#define S5P_CLKDIV0_P1CLK_SHIFT (28)
82#define S5P_CLKDIV0_P1CLK_MASK (0x7 << S5P_CLKDIV0_P1CLK_SHIFT)
83
84/* Clock MUX status Registers */
85#define S5P_CLK_MUX_STAT0_APLL_SHIFT (0)
86#define S5P_CLK_MUX_STAT0_APLL_MASK (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT)
87#define S5P_CLK_MUX_STAT0_MPLL_SHIFT (4)
88#define S5P_CLK_MUX_STAT0_MPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT)
89#define S5P_CLK_MUX_STAT0_EPLL_SHIFT (8)
90#define S5P_CLK_MUX_STAT0_EPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT)
91#define S5P_CLK_MUX_STAT0_VPLL_SHIFT (12)
92#define S5P_CLK_MUX_STAT0_VPLL_MASK (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT)
93#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT (16)
94#define S5P_CLK_MUX_STAT0_MUXARM_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT)
95#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT (20)
96#define S5P_CLK_MUX_STAT0_MUXD0_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT)
97#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT (24)
98#define S5P_CLK_MUX_STAT0_MUXD1_MASK (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT)
99#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT (24)
100#define S5P_CLK_MUX_STAT1_D1SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT)
101#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT (28)
102#define S5P_CLK_MUX_STAT1_D0SYNC_MASK (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT)
103
104#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-irq.h b/arch/arm/mach-s5p6442/include/mach/regs-irq.h
deleted file mode 100644
index 73782b52a83b..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/regs-irq.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <asm/hardware/vic.h>
17#include <mach/map.h>
18
19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
deleted file mode 100644
index 7fd88205a97c..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S5P6442_PLAT_SPI_CLKS_H
12#define __S5P6442_PLAT_SPI_CLKS_H __FILE__
13
14#define S5P6442_SPI_SRCCLK_PCLK 0
15#define S5P6442_SPI_SRCCLK_SCLK 1
16
17#endif /* __S5P6442_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h
deleted file mode 100644
index c30c1cc1b97e..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/system.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - system support header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_SYSTEM_H
14#define __ASM_ARCH_SYSTEM_H __FILE__
15
16#include <plat/system-reset.h>
17
18static void arch_idle(void)
19{
20 /* nothing here yet */
21}
22
23#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/tick.h b/arch/arm/mach-s5p6442/include/mach/tick.h
deleted file mode 100644
index e1d4cabf8297..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/tick.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/tick.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/tick.h
7 *
8 * S5P6442 - Timer tick support definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_TICK_H
16#define __ASM_ARCH_TICK_H __FILE__
17
18static inline u32 s3c24xx_ostimer_pending(void)
19{
20 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
21 return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
22}
23
24#define TICK_MAX (0xffffffff)
25
26#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/timex.h b/arch/arm/mach-s5p6442/include/mach/timex.h
deleted file mode 100644
index ff8f2fcadeb7..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* arch/arm/mach-s5p6442/include/mach/timex.h
2 *
3 * Copyright (c) 2003-2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S5P6442 - time parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_TIMEX_H
14#define __ASM_ARCH_TIMEX_H
15
16/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
17 * a variable is useless. It seems as long as we make our timers an
18 * exact multiple of HZ, any value that makes a 1->1 correspondence
19 * for the time conversion functions to/from jiffies is acceptable.
20*/
21
22#define CLOCK_TICK_RATE 12000000
23
24#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/uncompress.h b/arch/arm/mach-s5p6442/include/mach/uncompress.h
deleted file mode 100644
index 5ac7cbeeb987..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/uncompress.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6442 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22}
23
24#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
deleted file mode 100644
index 4aa55e55ac47..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* arch/arm/mach-s5p6442/include/mach/vmalloc.h
2 *
3 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S5P6442 vmalloc definition
10*/
11
12#ifndef __ASM_ARCH_VMALLOC_H
13#define __ASM_ARCH_VMALLOC_H
14
15#define VMALLOC_END 0xF6000000UL
16
17#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6442/init.c b/arch/arm/mach-s5p6442/init.c
deleted file mode 100644
index 1874bdb71e1d..000000000000
--- a/arch/arm/mach-s5p6442/init.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/s5p6442-init.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15
16#include <plat/cpu.h>
17#include <plat/devs.h>
18#include <plat/s5p6442.h>
19#include <plat/regs-serial.h>
20
21static struct s3c24xx_uart_clksrc s5p6442_serial_clocks[] = {
22 [0] = {
23 .name = "pclk",
24 .divisor = 1,
25 .min_baud = 0,
26 .max_baud = 0,
27 },
28};
29
30/* uart registration process */
31void __init s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
32{
33 struct s3c2410_uartcfg *tcfg = cfg;
34 u32 ucnt;
35
36 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
37 if (!tcfg->clocks) {
38 tcfg->clocks = s5p6442_serial_clocks;
39 tcfg->clocks_size = ARRAY_SIZE(s5p6442_serial_clocks);
40 }
41 }
42
43 s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
44}
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
deleted file mode 100644
index eaf6b9c489ff..000000000000
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/mach-smdk6442.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/serial_core.h>
15#include <linux/i2c.h>
16
17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
19#include <asm/setup.h>
20#include <asm/mach-types.h>
21
22#include <mach/map.h>
23#include <mach/regs-clock.h>
24
25#include <plat/regs-serial.h>
26#include <plat/s5p6442.h>
27#include <plat/devs.h>
28#include <plat/cpu.h>
29#include <plat/iic.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define SMDK6442_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define SMDK6442_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define SMDK6442_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG4 | \
43 S5PV210_UFCON_RXTRIG4)
44
45static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .flags = 0,
49 .ucon = SMDK6442_UCON_DEFAULT,
50 .ulcon = SMDK6442_ULCON_DEFAULT,
51 .ufcon = SMDK6442_UFCON_DEFAULT,
52 },
53 [1] = {
54 .hwport = 1,
55 .flags = 0,
56 .ucon = SMDK6442_UCON_DEFAULT,
57 .ulcon = SMDK6442_ULCON_DEFAULT,
58 .ufcon = SMDK6442_UFCON_DEFAULT,
59 },
60 [2] = {
61 .hwport = 2,
62 .flags = 0,
63 .ucon = SMDK6442_UCON_DEFAULT,
64 .ulcon = SMDK6442_ULCON_DEFAULT,
65 .ufcon = SMDK6442_UFCON_DEFAULT,
66 },
67};
68
69static struct platform_device *smdk6442_devices[] __initdata = {
70 &s3c_device_i2c0,
71 &samsung_asoc_dma,
72 &s5p6442_device_iis0,
73 &s3c_device_wdt,
74};
75
76static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = {
77 { I2C_BOARD_INFO("wm8580", 0x1b), },
78};
79
80static void __init smdk6442_map_io(void)
81{
82 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
83 s3c24xx_init_clocks(12000000);
84 s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs));
85}
86
87static void __init smdk6442_machine_init(void)
88{
89 s3c_i2c0_set_platdata(NULL);
90 i2c_register_board_info(0, smdk6442_i2c_devs0,
91 ARRAY_SIZE(smdk6442_i2c_devs0));
92 platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
93}
94
95MACHINE_START(SMDK6442, "SMDK6442")
96 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
97 .boot_params = S5P_PA_SDRAM + 0x100,
98 .init_irq = s5p6442_init_irq,
99 .map_io = smdk6442_map_io,
100 .init_machine = smdk6442_machine_init,
101 .timer = &s3c24xx_timer,
102MACHINE_END
diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c
deleted file mode 100644
index aad85656b0cc..000000000000
--- a/arch/arm/mach-s5p6442/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5p6442/setup-i2c0.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * I2C0 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <plat/gpio-cfg.h>
22#include <plat/iic.h>
23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 849229716586..5878bd9fbad3 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
7 7
8config PLAT_S5P 8config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4) 10 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
11 default y 11 default y
12 select ARM_VIC if !ARCH_EXYNOS4 12 select ARM_VIC if !ARCH_EXYNOS4
13 select ARM_GIC if ARCH_EXYNOS4 13 select ARM_GIC if ARCH_EXYNOS4
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 5cf5e721e6ca..bbc2aa7449ca 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -21,7 +21,6 @@
21 21
22#include <plat/cpu.h> 22#include <plat/cpu.h>
23#include <plat/s5p6440.h> 23#include <plat/s5p6440.h>
24#include <plat/s5p6442.h>
25#include <plat/s5p6450.h> 24#include <plat/s5p6450.h>
26#include <plat/s5pc100.h> 25#include <plat/s5pc100.h>
27#include <plat/s5pv210.h> 26#include <plat/s5pv210.h>
@@ -30,7 +29,6 @@
30/* table of supported CPUs */ 29/* table of supported CPUs */
31 30
32static const char name_s5p6440[] = "S5P6440"; 31static const char name_s5p6440[] = "S5P6440";
33static const char name_s5p6442[] = "S5P6442";
34static const char name_s5p6450[] = "S5P6450"; 32static const char name_s5p6450[] = "S5P6450";
35static const char name_s5pc100[] = "S5PC100"; 33static const char name_s5pc100[] = "S5PC100";
36static const char name_s5pv210[] = "S5PV210/S5PC110"; 34static const char name_s5pv210[] = "S5PV210/S5PC110";
@@ -46,14 +44,6 @@ static struct cpu_table cpu_ids[] __initdata = {
46 .init = s5p64x0_init, 44 .init = s5p64x0_init,
47 .name = name_s5p6440, 45 .name = name_s5p6440,
48 }, { 46 }, {
49 .idcode = 0x36442000,
50 .idmask = 0xfffff000,
51 .map_io = s5p6442_map_io,
52 .init_clocks = s5p6442_init_clocks,
53 .init_uarts = s5p6442_init_uarts,
54 .init = s5p6442_init,
55 .name = name_s5p6442,
56 }, {
57 .idcode = 0x36450000, 47 .idcode = 0x36450000,
58 .idmask = 0xfffff000, 48 .idmask = 0xfffff000,
59 .map_io = s5p6450_map_io, 49 .map_io = s5p6450_map_io,
diff --git a/arch/arm/plat-s5p/include/plat/s5p6442.h b/arch/arm/plat-s5p/include/plat/s5p6442.h
deleted file mode 100644
index 7b8801349c94..000000000000
--- a/arch/arm/plat-s5p/include/plat/s5p6442.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/* arch/arm/plat-s5p/include/plat/s5p6442.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5p6442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5P6442 related SoCs */
14
15extern void s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5p6442_register_clocks(void);
17extern void s5p6442_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5P6442
20
21extern int s5p6442_init(void);
22extern void s5p6442_init_irq(void);
23extern void s5p6442_map_io(void);
24extern void s5p6442_init_clocks(int xtal);
25
26#define s5p6442_init_uarts s5p6442_common_init_uarts
27
28#else
29#define s5p6442_init_clocks NULL
30#define s5p6442_init_uarts NULL
31#define s5p6442_map_io NULL
32#define s5p6442_init NULL
33#endif
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index cedfff51c82b..6ff205b7e4ae 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -80,7 +80,6 @@ extern struct sysdev_class s3c2443_sysclass;
80extern struct sysdev_class s3c6410_sysclass; 80extern struct sysdev_class s3c6410_sysclass;
81extern struct sysdev_class s3c64xx_sysclass; 81extern struct sysdev_class s3c64xx_sysclass;
82extern struct sysdev_class s5p64x0_sysclass; 82extern struct sysdev_class s5p64x0_sysclass;
83extern struct sysdev_class s5p6442_sysclass;
84extern struct sysdev_class s5pv210_sysclass; 83extern struct sysdev_class s5pv210_sysclass;
85extern struct sysdev_class exynos4_sysclass; 84extern struct sysdev_class exynos4_sysclass;
86 85
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S
index dc6efd90e8ff..207e275362a8 100644
--- a/arch/arm/plat-samsung/include/plat/debug-macro.S
+++ b/arch/arm/plat-samsung/include/plat/debug-macro.S
@@ -11,7 +11,7 @@
11 11
12#include <plat/regs-serial.h> 12#include <plat/regs-serial.h>
13 13
14/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */ 14/* The S5PV210/S5PC110 implementations are as belows. */
15 15
16 .macro fifo_level_s5pv210 rd, rx 16 .macro fifo_level_s5pv210 rd, rx
17 ldr \rd, [ \rx, # S3C2410_UFSTAT ] 17 ldr \rd, [ \rx, # S3C2410_UFSTAT ]
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index f0da6b70fba4..d64adf16d533 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -110,12 +110,6 @@ extern struct platform_device exynos4_device_spdif;
110extern struct platform_device exynos4_device_pd[]; 110extern struct platform_device exynos4_device_pd[];
111extern struct platform_device exynos4_device_ahci; 111extern struct platform_device exynos4_device_ahci;
112 112
113extern struct platform_device s5p6442_device_pcm0;
114extern struct platform_device s5p6442_device_pcm1;
115extern struct platform_device s5p6442_device_iis0;
116extern struct platform_device s5p6442_device_iis1;
117extern struct platform_device s5p6442_device_spi;
118
119extern struct platform_device s5p6440_device_pcm; 113extern struct platform_device s5p6440_device_pcm;
120extern struct platform_device s5p6440_device_iis; 114extern struct platform_device s5p6440_device_iis;
121 115
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 788837e99cb3..c151c5f94a87 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -194,7 +194,7 @@
194#define S3C64XX_UINTSP 0x34 194#define S3C64XX_UINTSP 0x34
195#define S3C64XX_UINTM 0x38 195#define S3C64XX_UINTM 0x38
196 196
197/* Following are specific to S5PV210 and S5P6442 */ 197/* Following are specific to S5PV210 */
198#define S5PV210_UCON_CLKMASK (1<<10) 198#define S5PV210_UCON_CLKMASK (1<<10)
199#define S5PV210_UCON_PCLK (0<<10) 199#define S5PV210_UCON_PCLK (0<<10)
200#define S5PV210_UCON_UCLK (1<<10) 200#define S5PV210_UCON_UCLK (1<<10)
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index ff1a561b326e..0ffe34a21554 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -69,6 +69,5 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
69extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 69extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
70extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 70extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
71extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 71extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
72extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
73 72
74#endif /* __S3C64XX_PLAT_SPI_H */ 73#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 55613e33e263..a6ae1cfad86c 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -933,12 +933,16 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
933 if (data && !(data & DABR_TRANSLATION)) 933 if (data && !(data & DABR_TRANSLATION))
934 return -EIO; 934 return -EIO;
935#ifdef CONFIG_HAVE_HW_BREAKPOINT 935#ifdef CONFIG_HAVE_HW_BREAKPOINT
936 if (ptrace_get_breakpoints(task) < 0)
937 return -ESRCH;
938
936 bp = thread->ptrace_bps[0]; 939 bp = thread->ptrace_bps[0];
937 if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) { 940 if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
938 if (bp) { 941 if (bp) {
939 unregister_hw_breakpoint(bp); 942 unregister_hw_breakpoint(bp);
940 thread->ptrace_bps[0] = NULL; 943 thread->ptrace_bps[0] = NULL;
941 } 944 }
945 ptrace_put_breakpoints(task);
942 return 0; 946 return 0;
943 } 947 }
944 if (bp) { 948 if (bp) {
@@ -948,9 +952,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
948 (DABR_DATA_WRITE | DABR_DATA_READ), 952 (DABR_DATA_WRITE | DABR_DATA_READ),
949 &attr.bp_type); 953 &attr.bp_type);
950 ret = modify_user_hw_breakpoint(bp, &attr); 954 ret = modify_user_hw_breakpoint(bp, &attr);
951 if (ret) 955 if (ret) {
956 ptrace_put_breakpoints(task);
952 return ret; 957 return ret;
958 }
953 thread->ptrace_bps[0] = bp; 959 thread->ptrace_bps[0] = bp;
960 ptrace_put_breakpoints(task);
954 thread->dabr = data; 961 thread->dabr = data;
955 return 0; 962 return 0;
956 } 963 }
@@ -965,9 +972,12 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
965 ptrace_triggered, task); 972 ptrace_triggered, task);
966 if (IS_ERR(bp)) { 973 if (IS_ERR(bp)) {
967 thread->ptrace_bps[0] = NULL; 974 thread->ptrace_bps[0] = NULL;
975 ptrace_put_breakpoints(task);
968 return PTR_ERR(bp); 976 return PTR_ERR(bp);
969 } 977 }
970 978
979 ptrace_put_breakpoints(task);
980
971#endif /* CONFIG_HAVE_HW_BREAKPOINT */ 981#endif /* CONFIG_HAVE_HW_BREAKPOINT */
972 982
973 /* Move contents to the DABR register */ 983 /* Move contents to the DABR register */
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 2130ca674e9b..3d7b209b2178 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -117,7 +117,11 @@ void user_enable_single_step(struct task_struct *child)
117 117
118 set_tsk_thread_flag(child, TIF_SINGLESTEP); 118 set_tsk_thread_flag(child, TIF_SINGLESTEP);
119 119
120 if (ptrace_get_breakpoints(child) < 0)
121 return;
122
120 set_single_step(child, pc); 123 set_single_step(child, pc);
124 ptrace_put_breakpoints(child);
121} 125}
122 126
123void user_disable_single_step(struct task_struct *child) 127void user_disable_single_step(struct task_struct *child)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index e61539b07d2c..447a28de6f09 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -184,26 +184,23 @@ static __initconst const u64 snb_hw_cache_event_ids
184 }, 184 },
185 }, 185 },
186 [ C(LL ) ] = { 186 [ C(LL ) ] = {
187 /*
188 * TBD: Need Off-core Response Performance Monitoring support
189 */
190 [ C(OP_READ) ] = { 187 [ C(OP_READ) ] = {
191 /* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */ 188 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
192 [ C(RESULT_ACCESS) ] = 0x01b7, 189 [ C(RESULT_ACCESS) ] = 0x01b7,
193 /* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */ 190 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
194 [ C(RESULT_MISS) ] = 0x01bb, 191 [ C(RESULT_MISS) ] = 0x01b7,
195 }, 192 },
196 [ C(OP_WRITE) ] = { 193 [ C(OP_WRITE) ] = {
197 /* OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE */ 194 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
198 [ C(RESULT_ACCESS) ] = 0x01b7, 195 [ C(RESULT_ACCESS) ] = 0x01b7,
199 /* OFFCORE_RESPONSE_1.ANY_RFO.ANY_LLC_MISS */ 196 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
200 [ C(RESULT_MISS) ] = 0x01bb, 197 [ C(RESULT_MISS) ] = 0x01b7,
201 }, 198 },
202 [ C(OP_PREFETCH) ] = { 199 [ C(OP_PREFETCH) ] = {
203 /* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */ 200 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
204 [ C(RESULT_ACCESS) ] = 0x01b7, 201 [ C(RESULT_ACCESS) ] = 0x01b7,
205 /* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */ 202 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
206 [ C(RESULT_MISS) ] = 0x01bb, 203 [ C(RESULT_MISS) ] = 0x01b7,
207 }, 204 },
208 }, 205 },
209 [ C(DTLB) ] = { 206 [ C(DTLB) ] = {
@@ -285,26 +282,26 @@ static __initconst const u64 westmere_hw_cache_event_ids
285 }, 282 },
286 [ C(LL ) ] = { 283 [ C(LL ) ] = {
287 [ C(OP_READ) ] = { 284 [ C(OP_READ) ] = {
288 /* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */ 285 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
289 [ C(RESULT_ACCESS) ] = 0x01b7, 286 [ C(RESULT_ACCESS) ] = 0x01b7,
290 /* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */ 287 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
291 [ C(RESULT_MISS) ] = 0x01bb, 288 [ C(RESULT_MISS) ] = 0x01b7,
292 }, 289 },
293 /* 290 /*
294 * Use RFO, not WRITEBACK, because a write miss would typically occur 291 * Use RFO, not WRITEBACK, because a write miss would typically occur
295 * on RFO. 292 * on RFO.
296 */ 293 */
297 [ C(OP_WRITE) ] = { 294 [ C(OP_WRITE) ] = {
298 /* OFFCORE_RESPONSE_1.ANY_RFO.LOCAL_CACHE */ 295 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
299 [ C(RESULT_ACCESS) ] = 0x01bb, 296 [ C(RESULT_ACCESS) ] = 0x01b7,
300 /* OFFCORE_RESPONSE_0.ANY_RFO.ANY_LLC_MISS */ 297 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
301 [ C(RESULT_MISS) ] = 0x01b7, 298 [ C(RESULT_MISS) ] = 0x01b7,
302 }, 299 },
303 [ C(OP_PREFETCH) ] = { 300 [ C(OP_PREFETCH) ] = {
304 /* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */ 301 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
305 [ C(RESULT_ACCESS) ] = 0x01b7, 302 [ C(RESULT_ACCESS) ] = 0x01b7,
306 /* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */ 303 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
307 [ C(RESULT_MISS) ] = 0x01bb, 304 [ C(RESULT_MISS) ] = 0x01b7,
308 }, 305 },
309 }, 306 },
310 [ C(DTLB) ] = { 307 [ C(DTLB) ] = {
@@ -352,16 +349,36 @@ static __initconst const u64 westmere_hw_cache_event_ids
352}; 349};
353 350
354/* 351/*
355 * OFFCORE_RESPONSE MSR bits (subset), See IA32 SDM Vol 3 30.6.1.3 352 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
353 * See IA32 SDM Vol 3B 30.6.1.3
356 */ 354 */
357 355
358#define DMND_DATA_RD (1 << 0) 356#define NHM_DMND_DATA_RD (1 << 0)
359#define DMND_RFO (1 << 1) 357#define NHM_DMND_RFO (1 << 1)
360#define DMND_WB (1 << 3) 358#define NHM_DMND_IFETCH (1 << 2)
361#define PF_DATA_RD (1 << 4) 359#define NHM_DMND_WB (1 << 3)
362#define PF_DATA_RFO (1 << 5) 360#define NHM_PF_DATA_RD (1 << 4)
363#define RESP_UNCORE_HIT (1 << 8) 361#define NHM_PF_DATA_RFO (1 << 5)
364#define RESP_MISS (0xf600) /* non uncore hit */ 362#define NHM_PF_IFETCH (1 << 6)
363#define NHM_OFFCORE_OTHER (1 << 7)
364#define NHM_UNCORE_HIT (1 << 8)
365#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
366#define NHM_OTHER_CORE_HITM (1 << 10)
367 /* reserved */
368#define NHM_REMOTE_CACHE_FWD (1 << 12)
369#define NHM_REMOTE_DRAM (1 << 13)
370#define NHM_LOCAL_DRAM (1 << 14)
371#define NHM_NON_DRAM (1 << 15)
372
373#define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
374
375#define NHM_DMND_READ (NHM_DMND_DATA_RD)
376#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
377#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
378
379#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
380#define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
381#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
365 382
366static __initconst const u64 nehalem_hw_cache_extra_regs 383static __initconst const u64 nehalem_hw_cache_extra_regs
367 [PERF_COUNT_HW_CACHE_MAX] 384 [PERF_COUNT_HW_CACHE_MAX]
@@ -370,16 +387,16 @@ static __initconst const u64 nehalem_hw_cache_extra_regs
370{ 387{
371 [ C(LL ) ] = { 388 [ C(LL ) ] = {
372 [ C(OP_READ) ] = { 389 [ C(OP_READ) ] = {
373 [ C(RESULT_ACCESS) ] = DMND_DATA_RD|RESP_UNCORE_HIT, 390 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
374 [ C(RESULT_MISS) ] = DMND_DATA_RD|RESP_MISS, 391 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
375 }, 392 },
376 [ C(OP_WRITE) ] = { 393 [ C(OP_WRITE) ] = {
377 [ C(RESULT_ACCESS) ] = DMND_RFO|DMND_WB|RESP_UNCORE_HIT, 394 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
378 [ C(RESULT_MISS) ] = DMND_RFO|DMND_WB|RESP_MISS, 395 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
379 }, 396 },
380 [ C(OP_PREFETCH) ] = { 397 [ C(OP_PREFETCH) ] = {
381 [ C(RESULT_ACCESS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_UNCORE_HIT, 398 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
382 [ C(RESULT_MISS) ] = PF_DATA_RD|PF_DATA_RFO|RESP_MISS, 399 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
383 }, 400 },
384 } 401 }
385}; 402};
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 45892dc4b72a..f65e5b521dbd 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -608,6 +608,9 @@ static int ptrace_write_dr7(struct task_struct *tsk, unsigned long data)
608 unsigned len, type; 608 unsigned len, type;
609 struct perf_event *bp; 609 struct perf_event *bp;
610 610
611 if (ptrace_get_breakpoints(tsk) < 0)
612 return -ESRCH;
613
611 data &= ~DR_CONTROL_RESERVED; 614 data &= ~DR_CONTROL_RESERVED;
612 old_dr7 = ptrace_get_dr7(thread->ptrace_bps); 615 old_dr7 = ptrace_get_dr7(thread->ptrace_bps);
613restore: 616restore:
@@ -655,6 +658,9 @@ restore:
655 } 658 }
656 goto restore; 659 goto restore;
657 } 660 }
661
662 ptrace_put_breakpoints(tsk);
663
658 return ((orig_ret < 0) ? orig_ret : rc); 664 return ((orig_ret < 0) ? orig_ret : rc);
659} 665}
660 666
@@ -668,10 +674,17 @@ static unsigned long ptrace_get_debugreg(struct task_struct *tsk, int n)
668 674
669 if (n < HBP_NUM) { 675 if (n < HBP_NUM) {
670 struct perf_event *bp; 676 struct perf_event *bp;
677
678 if (ptrace_get_breakpoints(tsk) < 0)
679 return -ESRCH;
680
671 bp = thread->ptrace_bps[n]; 681 bp = thread->ptrace_bps[n];
672 if (!bp) 682 if (!bp)
673 return 0; 683 val = 0;
674 val = bp->hw.info.address; 684 else
685 val = bp->hw.info.address;
686
687 ptrace_put_breakpoints(tsk);
675 } else if (n == 6) { 688 } else if (n == 6) {
676 val = thread->debugreg6; 689 val = thread->debugreg6;
677 } else if (n == 7) { 690 } else if (n == 7) {
@@ -686,6 +699,10 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
686 struct perf_event *bp; 699 struct perf_event *bp;
687 struct thread_struct *t = &tsk->thread; 700 struct thread_struct *t = &tsk->thread;
688 struct perf_event_attr attr; 701 struct perf_event_attr attr;
702 int err = 0;
703
704 if (ptrace_get_breakpoints(tsk) < 0)
705 return -ESRCH;
689 706
690 if (!t->ptrace_bps[nr]) { 707 if (!t->ptrace_bps[nr]) {
691 ptrace_breakpoint_init(&attr); 708 ptrace_breakpoint_init(&attr);
@@ -709,24 +726,23 @@ static int ptrace_set_breakpoint_addr(struct task_struct *tsk, int nr,
709 * writing for the user. And anyway this is the previous 726 * writing for the user. And anyway this is the previous
710 * behaviour. 727 * behaviour.
711 */ 728 */
712 if (IS_ERR(bp)) 729 if (IS_ERR(bp)) {
713 return PTR_ERR(bp); 730 err = PTR_ERR(bp);
731 goto put;
732 }
714 733
715 t->ptrace_bps[nr] = bp; 734 t->ptrace_bps[nr] = bp;
716 } else { 735 } else {
717 int err;
718
719 bp = t->ptrace_bps[nr]; 736 bp = t->ptrace_bps[nr];
720 737
721 attr = bp->attr; 738 attr = bp->attr;
722 attr.bp_addr = addr; 739 attr.bp_addr = addr;
723 err = modify_user_hw_breakpoint(bp, &attr); 740 err = modify_user_hw_breakpoint(bp, &attr);
724 if (err)
725 return err;
726 } 741 }
727 742
728 743put:
729 return 0; 744 ptrace_put_breakpoints(tsk);
745 return err;
730} 746}
731 747
732/* 748/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 20:33:58 -0500