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-rw-r--r--arch/arm/configs/rx51_defconfig2
-rw-r--r--arch/arm/mach-omap1/Kconfig1
-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c13
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c114
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c84
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c204
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c330
-rw-r--r--arch/arm/mach-omap2/gpmc-smc91x.c189
-rw-r--r--arch/arm/plat-omap/dma.c79
-rw-r--r--arch/arm/plat-omap/i2c.c2
-rw-r--r--arch/arm/plat-omap/include/mach/dma.h3
-rw-r--r--arch/arm/plat-omap/include/mach/gpmc-smc91x.h42
-rw-r--r--arch/arm/plat-omap/include/mach/hwa742.h4
-rw-r--r--arch/arm/plat-omap/include/mach/onenand.h22
-rw-r--r--arch/arm/plat-omap/include/mach/vmalloc.h2
-rw-r--r--arch/arm/plat-omap/mcbsp.c30
-rw-r--r--arch/arm/plat-omap/sram.c4
19 files changed, 837 insertions, 298 deletions
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
index 593102da8cd7..eb2cb31825c0 100644
--- a/arch/arm/configs/rx51_defconfig
+++ b/arch/arm/configs/rx51_defconfig
@@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
282# 282#
283CONFIG_ZBOOT_ROM_TEXT=0x0 283CONFIG_ZBOOT_ROM_TEXT=0x0
284CONFIG_ZBOOT_ROM_BSS=0x0 284CONFIG_ZBOOT_ROM_BSS=0x0
285CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw console=ttyMTD5" 285CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0"
286# CONFIG_XIP_KERNEL is not set 286# CONFIG_XIP_KERNEL is not set
287# CONFIG_KEXEC is not set 287# CONFIG_KEXEC is not set
288 288
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index cd8de89c5fad..55ecc01ea206 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -46,7 +46,6 @@ config MACH_OMAP_H2
46config MACH_OMAP_H3 46config MACH_OMAP_H3
47 bool "TI H3 Support" 47 bool "TI H3 Support"
48 depends on ARCH_OMAP1 && ARCH_OMAP16XX 48 depends on ARCH_OMAP1 && ARCH_OMAP16XX
49# select GPIOEXPANDER_OMAP
50 help 49 help
51 TI OMAP 1710 H3 board support. Say Y here if you have such 50 TI OMAP 1710 H3 board support. Say Y here if you have such
52 a board. 51 a board.
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 1bda8f5d7546..6867cd3ad0b4 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -13,6 +13,10 @@ obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
13# Power Management 13# Power Management
14obj-$(CONFIG_PM) += pm.o sleep.o 14obj-$(CONFIG_PM) += pm.o sleep.o
15 15
16# DSP
17obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
18mailbox_mach-objs := mailbox.o
19
16led-y := leds.o 20led-y := leds.o
17 21
18# Specific board support 22# Specific board support
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index d1ed1365319e..e70fc7c66bbb 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -33,8 +33,11 @@
33#include <mach/common.h> 33#include <mach/common.h>
34#include <mach/dsp_common.h> 34#include <mach/dsp_common.h>
35#include <mach/omapfb.h> 35#include <mach/omapfb.h>
36#include <mach/hwa742.h>
36#include <mach/lcd_mipid.h> 37#include <mach/lcd_mipid.h>
37#include <mach/mmc.h> 38#include <mach/mmc.h>
39#include <mach/usb.h>
40#include <mach/clock.h>
38 41
39#define ADS7846_PENDOWN_GPIO 15 42#define ADS7846_PENDOWN_GPIO 15
40 43
@@ -162,6 +165,15 @@ static struct spi_board_info nokia770_spi_board_info[] __initdata = {
162 }, 165 },
163}; 166};
164 167
168static struct hwa742_platform_data nokia770_hwa742_platform_data = {
169 .te_connected = 1,
170};
171
172static void hwa742_dev_init(void)
173{
174 clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL);
175 omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data);
176}
165 177
166/* assume no Mini-AB port */ 178/* assume no Mini-AB port */
167 179
@@ -370,6 +382,7 @@ static void __init omap_nokia770_init(void)
370 omap_serial_init(); 382 omap_serial_init();
371 omap_register_i2c_bus(1, 100, NULL, 0); 383 omap_register_i2c_bus(1, 100, NULL, 0);
372 omap_dsp_init(); 384 omap_dsp_init();
385 hwa742_dev_init();
373 ads7846_dev_init(); 386 ads7846_dev_init();
374 mipid_dev_init(); 387 mipid_dev_init();
375 omap_usb_init(&nokia770_usb_config); 388 omap_usb_init(&nokia770_usb_config);
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 3935a359e7e9..516477ee5690 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -58,3 +58,9 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
58 58
59# Platform specific device init code 59# Platform specific device init code
60obj-y += usb-musb.o 60obj-y += usb-musb.o
61
62onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
63obj-y += $(onenand-m) $(onenand-y)
64
65smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o
66obj-y += $(smc91x-m) $(smc91x-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 22143651037e..9c3fdcdf76c3 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -36,14 +36,12 @@
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/gpmc.h> 37#include <mach/gpmc.h>
38#include <mach/usb.h> 38#include <mach/usb.h>
39#include <mach/gpmc-smc91x.h>
39 40
40#include "mmc-twl4030.h" 41#include "mmc-twl4030.h"
41 42
42#define SDP2430_CS0_BASE 0x04000000 43#define SDP2430_CS0_BASE 0x04000000
43#define SDP2430_FLASH_CS 0 44#define SECONDARY_LCD_GPIO 147
44#define SDP2430_SMC91X_CS 5
45
46#define SDP2430_ETHR_GPIO_IRQ 149
47 45
48static struct mtd_partition sdp2430_partitions[] = { 46static struct mtd_partition sdp2430_partitions[] = {
49 /* bootloader (U-Boot, etc) in first sector */ 47 /* bootloader (U-Boot, etc) in first sector */
@@ -99,100 +97,53 @@ static struct platform_device sdp2430_flash_device = {
99 .resource = &sdp2430_flash_resource, 97 .resource = &sdp2430_flash_resource,
100}; 98};
101 99
102static struct resource sdp2430_smc91x_resources[] = { 100static struct platform_device sdp2430_lcd_device = {
103 [0] = { 101 .name = "sdp2430_lcd",
104 .start = SDP2430_CS0_BASE,
105 .end = SDP2430_CS0_BASE + SZ_64M - 1,
106 .flags = IORESOURCE_MEM,
107 },
108 [1] = {
109 .start = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ),
110 .end = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ),
111 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
112 },
113};
114
115static struct platform_device sdp2430_smc91x_device = {
116 .name = "smc91x",
117 .id = -1, 102 .id = -1,
118 .num_resources = ARRAY_SIZE(sdp2430_smc91x_resources),
119 .resource = sdp2430_smc91x_resources,
120}; 103};
121 104
122static struct platform_device *sdp2430_devices[] __initdata = { 105static struct platform_device *sdp2430_devices[] __initdata = {
123 &sdp2430_smc91x_device,
124 &sdp2430_flash_device, 106 &sdp2430_flash_device,
107 &sdp2430_lcd_device,
125}; 108};
126 109
127static inline void __init sdp2430_init_smc91x(void) 110static struct omap_lcd_config sdp2430_lcd_config __initdata = {
128{ 111 .ctrl_name = "internal",
129 int eth_cs; 112};
130 unsigned long cs_mem_base;
131 unsigned int rate;
132 struct clk *gpmc_fck;
133 113
134 eth_cs = SDP2430_SMC91X_CS; 114#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
135 115
136 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ 116static struct omap_smc91x_platform_data board_smc91x_data = {
137 if (IS_ERR(gpmc_fck)) { 117 .cs = 5,
138 WARN_ON(1); 118 .gpio_irq = 149,
139 return; 119 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
140 } 120 IORESOURCE_IRQ_LOWLEVEL,
141 121
142 clk_enable(gpmc_fck); 122};
143 rate = clk_get_rate(gpmc_fck);
144
145 /* Make sure CS1 timings are correct, for 2430 always muxed */
146 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
147
148 if (rate >= 160000000) {
149 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
150 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
151 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
152 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
153 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
154 } else if (rate >= 130000000) {
155 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
156 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
157 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
158 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
159 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
160 } else { /* rate = 100000000 */
161 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
162 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
163 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
164 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
165 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
166 }
167 123
168 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { 124static void __init board_smc91x_init(void)
169 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); 125{
170 goto out; 126 if (omap_rev() > OMAP3430_REV_ES1_0)
171 } 127 board_smc91x_data.gpio_irq = 6;
128 else
129 board_smc91x_data.gpio_irq = 29;
172 130
173 sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; 131 gpmc_smc91x_init(&board_smc91x_data);
174 sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; 132}
175 udelay(100);
176 133
177 if (gpio_request(SDP2430_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { 134#else
178 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
179 SDP2430_ETHR_GPIO_IRQ);
180 gpmc_cs_free(eth_cs);
181 goto out;
182 }
183 gpio_direction_input(SDP2430_ETHR_GPIO_IRQ);
184 135
185out: 136static inline void board_smc91x_init(void)
186 clk_disable(gpmc_fck); 137{
187 clk_put(gpmc_fck);
188} 138}
189 139
140#endif
141
190static void __init omap_2430sdp_init_irq(void) 142static void __init omap_2430sdp_init_irq(void)
191{ 143{
192 omap2_init_common_hw(NULL); 144 omap2_init_common_hw(NULL);
193 omap_init_irq(); 145 omap_init_irq();
194 omap_gpio_init(); 146 omap_gpio_init();
195 sdp2430_init_smc91x();
196} 147}
197 148
198static struct omap_uart_config sdp2430_uart_config __initdata = { 149static struct omap_uart_config sdp2430_uart_config __initdata = {
@@ -201,6 +152,7 @@ static struct omap_uart_config sdp2430_uart_config __initdata = {
201 152
202static struct omap_board_config_kernel sdp2430_config[] = { 153static struct omap_board_config_kernel sdp2430_config[] = {
203 {OMAP_TAG_UART, &sdp2430_uart_config}, 154 {OMAP_TAG_UART, &sdp2430_uart_config},
155 {OMAP_TAG_LCD, &sdp2430_lcd_config},
204}; 156};
205 157
206 158
@@ -248,6 +200,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
248 200
249static void __init omap_2430sdp_init(void) 201static void __init omap_2430sdp_init(void)
250{ 202{
203 int ret;
204
251 omap2430_i2c_init(); 205 omap2430_i2c_init();
252 206
253 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); 207 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
@@ -256,6 +210,12 @@ static void __init omap_2430sdp_init(void)
256 omap_serial_init(); 210 omap_serial_init();
257 twl4030_mmc_init(mmc); 211 twl4030_mmc_init(mmc);
258 usb_musb_init(); 212 usb_musb_init();
213 board_smc91x_init();
214
215 /* Turn off secondary LCD backlight */
216 ret = gpio_request(SECONDARY_LCD_GPIO, "Secondary LCD backlight");
217 if (ret == 0)
218 gpio_direction_output(SECONDARY_LCD_GPIO, 0);
259} 219}
260 220
261static void __init omap_2430sdp_map_io(void) 221static void __init omap_2430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index ed9274972122..0e6369583958 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -39,15 +39,12 @@
39 39
40#include <mach/control.h> 40#include <mach/control.h>
41#include <mach/keypad.h> 41#include <mach/keypad.h>
42#include <mach/gpmc-smc91x.h>
42 43
43#include "mmc-twl4030.h" 44#include "mmc-twl4030.h"
44 45
45#define CONFIG_DISABLE_HFCLK 1 46#define CONFIG_DISABLE_HFCLK 1
46 47
47#define SDP3430_ETHR_GPIO_IRQ_SDPV1 29
48#define SDP3430_ETHR_GPIO_IRQ_SDPV2 6
49#define SDP3430_SMC91X_CS 3
50
51#define SDP3430_TS_GPIO_IRQ_SDPV1 3 48#define SDP3430_TS_GPIO_IRQ_SDPV1 3
52#define SDP3430_TS_GPIO_IRQ_SDPV2 2 49#define SDP3430_TS_GPIO_IRQ_SDPV2 2
53 50
@@ -56,24 +53,6 @@
56 53
57#define TWL4030_MSECURE_GPIO 22 54#define TWL4030_MSECURE_GPIO 22
58 55
59static struct resource sdp3430_smc91x_resources[] = {
60 [0] = {
61 .flags = IORESOURCE_MEM,
62 },
63 [1] = {
64 .start = 0,
65 .end = 0,
66 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
67 },
68};
69
70static struct platform_device sdp3430_smc91x_device = {
71 .name = "smc91x",
72 .id = -1,
73 .num_resources = ARRAY_SIZE(sdp3430_smc91x_resources),
74 .resource = sdp3430_smc91x_resources,
75};
76
77static int sdp3430_keymap[] = { 56static int sdp3430_keymap[] = {
78 KEY(0, 0, KEY_LEFT), 57 KEY(0, 0, KEY_LEFT),
79 KEY(0, 1, KEY_RIGHT), 58 KEY(0, 1, KEY_RIGHT),
@@ -184,48 +163,14 @@ static struct regulator_consumer_supply sdp3430_vdvi_supply = {
184}; 163};
185 164
186static struct platform_device *sdp3430_devices[] __initdata = { 165static struct platform_device *sdp3430_devices[] __initdata = {
187 &sdp3430_smc91x_device,
188 &sdp3430_lcd_device, 166 &sdp3430_lcd_device,
189}; 167};
190 168
191static inline void __init sdp3430_init_smc91x(void)
192{
193 int eth_cs;
194 unsigned long cs_mem_base;
195 int eth_gpio = 0;
196
197 eth_cs = SDP3430_SMC91X_CS;
198
199 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
200 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
201 return;
202 }
203
204 sdp3430_smc91x_resources[0].start = cs_mem_base + 0x300;
205 sdp3430_smc91x_resources[0].end = cs_mem_base + 0x30f;
206 udelay(100);
207
208 if (omap_rev() > OMAP3430_REV_ES1_0)
209 eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV2;
210 else
211 eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV1;
212
213 sdp3430_smc91x_resources[1].start = gpio_to_irq(eth_gpio);
214
215 if (gpio_request(eth_gpio, "SMC91x irq") < 0) {
216 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
217 eth_gpio);
218 return;
219 }
220 gpio_direction_input(eth_gpio);
221}
222
223static void __init omap_3430sdp_init_irq(void) 169static void __init omap_3430sdp_init_irq(void)
224{ 170{
225 omap2_init_common_hw(NULL); 171 omap2_init_common_hw(NULL);
226 omap_init_irq(); 172 omap_init_irq();
227 omap_gpio_init(); 173 omap_gpio_init();
228 sdp3430_init_smc91x();
229} 174}
230 175
231static struct omap_uart_config sdp3430_uart_config __initdata = { 176static struct omap_uart_config sdp3430_uart_config __initdata = {
@@ -506,6 +451,32 @@ static int __init omap3430_i2c_init(void)
506 return 0; 451 return 0;
507} 452}
508 453
454#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
455
456static struct omap_smc91x_platform_data board_smc91x_data = {
457 .cs = 3,
458 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
459 IORESOURCE_IRQ_LOWLEVEL,
460};
461
462static void __init board_smc91x_init(void)
463{
464 if (omap_rev() > OMAP3430_REV_ES1_0)
465 board_smc91x_data.gpio_irq = 6;
466 else
467 board_smc91x_data.gpio_irq = 29;
468
469 gpmc_smc91x_init(&board_smc91x_data);
470}
471
472#else
473
474static inline void board_smc91x_init(void)
475{
476}
477
478#endif
479
509static void __init omap_3430sdp_init(void) 480static void __init omap_3430sdp_init(void)
510{ 481{
511 omap3430_i2c_init(); 482 omap3430_i2c_init();
@@ -522,6 +493,7 @@ static void __init omap_3430sdp_init(void)
522 ads7846_dev_init(); 493 ads7846_dev_init();
523 omap_serial_init(); 494 omap_serial_init();
524 usb_musb_init(); 495 usb_musb_init();
496 board_smc91x_init();
525} 497}
526 498
527static void __init omap_3430sdp_map_io(void) 499static void __init omap_3430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index a7381729645c..233c7454d84f 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -27,31 +27,11 @@
27#include <mach/dma.h> 27#include <mach/dma.h>
28#include <mach/gpmc.h> 28#include <mach/gpmc.h>
29#include <mach/keypad.h> 29#include <mach/keypad.h>
30#include <mach/onenand.h>
31#include <mach/gpmc-smc91x.h>
30 32
31#include "mmc-twl4030.h" 33#include "mmc-twl4030.h"
32 34
33
34#define SMC91X_CS 1
35#define SMC91X_GPIO_IRQ 54
36#define SMC91X_GPIO_RESET 164
37#define SMC91X_GPIO_PWRDWN 86
38
39static struct resource rx51_smc91x_resources[] = {
40 [0] = {
41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
44 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
45 },
46};
47
48static struct platform_device rx51_smc91x_device = {
49 .name = "smc91x",
50 .id = -1,
51 .num_resources = ARRAY_SIZE(rx51_smc91x_resources),
52 .resource = rx51_smc91x_resources,
53};
54
55static int rx51_keymap[] = { 35static int rx51_keymap[] = {
56 KEY(0, 0, KEY_Q), 36 KEY(0, 0, KEY_Q),
57 KEY(0, 1, KEY_W), 37 KEY(0, 1, KEY_W),
@@ -107,98 +87,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
107 .rep = 1, 87 .rep = 1,
108}; 88};
109 89
110static struct platform_device *rx51_peripherals_devices[] = {
111 &rx51_smc91x_device,
112};
113
114/*
115 * Timings are taken from smsc-lan91c96-ms.pdf
116 */
117static int smc91x_init_gpmc(int cs)
118{
119 struct gpmc_timings t;
120 const int t2_r = 45; /* t2 in Figure 12.10 */
121 const int t2_w = 30; /* t2 in Figure 12.11 */
122 const int t3 = 15; /* t3 in Figure 12.10 */
123 const int t5_r = 0; /* t5 in Figure 12.10 */
124 const int t6_r = 45; /* t6 in Figure 12.10 */
125 const int t6_w = 0; /* t6 in Figure 12.11 */
126 const int t7_w = 15; /* t7 in Figure 12.11 */
127 const int t15 = 12; /* t15 in Figure 12.2 */
128 const int t20 = 185; /* t20 in Figure 12.2 */
129
130 memset(&t, 0, sizeof(t));
131
132 t.cs_on = t15;
133 t.cs_rd_off = t3 + t2_r + t5_r; /* Figure 12.10 */
134 t.cs_wr_off = t3 + t2_w + t6_w; /* Figure 12.11 */
135 t.adv_on = t3; /* Figure 12.10 */
136 t.adv_rd_off = t3 + t2_r; /* Figure 12.10 */
137 t.adv_wr_off = t3 + t2_w; /* Figure 12.11 */
138 t.oe_off = t3 + t2_r + t5_r; /* Figure 12.10 */
139 t.oe_on = t.oe_off - t6_r; /* Figure 12.10 */
140 t.we_off = t3 + t2_w + t6_w; /* Figure 12.11 */
141 t.we_on = t.we_off - t7_w; /* Figure 12.11 */
142 t.rd_cycle = t20; /* Figure 12.2 */
143 t.wr_cycle = t20; /* Figure 12.4 */
144 t.access = t3 + t2_r + t5_r; /* Figure 12.10 */
145 t.wr_access = t3 + t2_w + t6_w; /* Figure 12.11 */
146
147 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16);
148
149 return gpmc_cs_set_timings(cs, &t);
150}
151
152static void __init rx51_init_smc91x(void)
153{
154 unsigned long cs_mem_base;
155 int ret;
156
157 omap_cfg_reg(U8_34XX_GPIO54_DOWN);
158 omap_cfg_reg(G25_34XX_GPIO86_OUT);
159 omap_cfg_reg(H19_34XX_GPIO164_OUT);
160
161 if (gpmc_cs_request(SMC91X_CS, SZ_16M, &cs_mem_base) < 0) {
162 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
163 return;
164 }
165
166 rx51_smc91x_resources[0].start = cs_mem_base + 0x300;
167 rx51_smc91x_resources[0].end = cs_mem_base + 0x30f;
168
169 smc91x_init_gpmc(SMC91X_CS);
170
171 if (gpio_request(SMC91X_GPIO_IRQ, "SMC91X irq") < 0)
172 goto free1;
173
174 gpio_direction_input(SMC91X_GPIO_IRQ);
175 rx51_smc91x_resources[1].start = gpio_to_irq(SMC91X_GPIO_IRQ);
176
177 ret = gpio_request(SMC91X_GPIO_PWRDWN, "SMC91X powerdown");
178 if (ret)
179 goto free2;
180 gpio_direction_output(SMC91X_GPIO_PWRDWN, 0);
181
182 ret = gpio_request(SMC91X_GPIO_RESET, "SMC91X reset");
183 if (ret)
184 goto free3;
185 gpio_direction_output(SMC91X_GPIO_RESET, 0);
186 gpio_set_value(SMC91X_GPIO_RESET, 1);
187 msleep(100);
188 gpio_set_value(SMC91X_GPIO_RESET, 0);
189
190 return;
191
192free3:
193 gpio_free(SMC91X_GPIO_PWRDWN);
194free2:
195 gpio_free(SMC91X_GPIO_IRQ);
196free1:
197 gpmc_cs_free(SMC91X_CS);
198
199 printk(KERN_ERR "Could not initialize smc91x\n");
200}
201
202static struct twl4030_madc_platform_data rx51_madc_data = { 90static struct twl4030_madc_platform_data rx51_madc_data = {
203 .irq_line = 1, 91 .irq_line = 1,
204}; 92};
@@ -408,12 +296,94 @@ static int __init rx51_i2c_init(void)
408 return 0; 296 return 0;
409} 297}
410 298
299#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
300 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
301
302static struct mtd_partition onenand_partitions[] = {
303 {
304 .name = "bootloader",
305 .offset = 0,
306 .size = 0x20000,
307 .mask_flags = MTD_WRITEABLE, /* Force read-only */
308 },
309 {
310 .name = "config",
311 .offset = MTDPART_OFS_APPEND,
312 .size = 0x60000,
313 },
314 {
315 .name = "log",
316 .offset = MTDPART_OFS_APPEND,
317 .size = 0x40000,
318 },
319 {
320 .name = "kernel",
321 .offset = MTDPART_OFS_APPEND,
322 .size = 0x200000,
323 },
324 {
325 .name = "initfs",
326 .offset = MTDPART_OFS_APPEND,
327 .size = 0x200000,
328 },
329 {
330 .name = "rootfs",
331 .offset = MTDPART_OFS_APPEND,
332 .size = MTDPART_SIZ_FULL,
333 },
334};
335
336static struct omap_onenand_platform_data board_onenand_data = {
337 .cs = 0,
338 .gpio_irq = 65,
339 .parts = onenand_partitions,
340 .nr_parts = ARRAY_SIZE(onenand_partitions),
341};
342
343static void __init board_onenand_init(void)
344{
345 gpmc_onenand_init(&board_onenand_data);
346}
347
348#else
349
350static inline void board_onenand_init(void)
351{
352}
353
354#endif
355
356#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
357
358static struct omap_smc91x_platform_data board_smc91x_data = {
359 .cs = 1,
360 .gpio_irq = 54,
361 .gpio_pwrdwn = 86,
362 .gpio_reset = 164,
363 .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_HIGHLEVEL,
364};
365
366static void __init board_smc91x_init(void)
367{
368 omap_cfg_reg(U8_34XX_GPIO54_DOWN);
369 omap_cfg_reg(G25_34XX_GPIO86_OUT);
370 omap_cfg_reg(H19_34XX_GPIO164_OUT);
371
372 gpmc_smc91x_init(&board_smc91x_data);
373}
374
375#else
376
377static inline void board_smc91x_init(void)
378{
379}
380
381#endif
411 382
412void __init rx51_peripherals_init(void) 383void __init rx51_peripherals_init(void)
413{ 384{
414 platform_add_devices(rx51_peripherals_devices,
415 ARRAY_SIZE(rx51_peripherals_devices));
416 rx51_i2c_init(); 385 rx51_i2c_init();
417 rx51_init_smc91x(); 386 board_onenand_init();
387 board_smc91x_init();
418} 388}
419 389
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
new file mode 100644
index 000000000000..2fd22f9c5f0e
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -0,0 +1,330 @@
1/*
2 * linux/arch/arm/mach-omap2/gpmc-onenand.c
3 *
4 * Copyright (C) 2006 - 2009 Nokia Corporation
5 * Contacts: Juha Yrjola
6 * Tony Lindgren
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/mtd/onenand_regs.h>
16#include <linux/io.h>
17
18#include <asm/mach/flash.h>
19
20#include <mach/onenand.h>
21#include <mach/board.h>
22#include <mach/gpmc.h>
23
24static struct omap_onenand_platform_data *gpmc_onenand_data;
25
26static struct platform_device gpmc_onenand_device = {
27 .name = "omap2-onenand",
28 .id = -1,
29};
30
31static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
32{
33 struct gpmc_timings t;
34
35 const int t_cer = 15;
36 const int t_avdp = 12;
37 const int t_aavdh = 7;
38 const int t_ce = 76;
39 const int t_aa = 76;
40 const int t_oe = 20;
41 const int t_cez = 20; /* max of t_cez, t_oez */
42 const int t_ds = 30;
43 const int t_wpl = 40;
44 const int t_wph = 30;
45
46 memset(&t, 0, sizeof(t));
47 t.sync_clk = 0;
48 t.cs_on = 0;
49 t.adv_on = 0;
50
51 /* Read */
52 t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
53 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
54 t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
55 t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
56 t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
57 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
58 t.cs_rd_off = t.oe_off;
59 t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
60
61 /* Write */
62 t.adv_wr_off = t.adv_rd_off;
63 t.we_on = t.oe_on;
64 if (cpu_is_omap34xx()) {
65 t.wr_data_mux_bus = t.we_on;
66 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
67 }
68 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
69 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
70 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
71
72 /* Configure GPMC for asynchronous read */
73 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
74 GPMC_CONFIG1_DEVICESIZE_16 |
75 GPMC_CONFIG1_MUXADDDATA);
76
77 return gpmc_cs_set_timings(cs, &t);
78}
79
80static void set_onenand_cfg(void __iomem *onenand_base, int latency,
81 int sync_read, int sync_write, int hf)
82{
83 u32 reg;
84
85 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
86 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
87 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
88 ONENAND_SYS_CFG1_BL_16;
89 if (sync_read)
90 reg |= ONENAND_SYS_CFG1_SYNC_READ;
91 else
92 reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
93 if (sync_write)
94 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
95 else
96 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
97 if (hf)
98 reg |= ONENAND_SYS_CFG1_HF;
99 else
100 reg &= ~ONENAND_SYS_CFG1_HF;
101 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
102}
103
104static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
105 void __iomem *onenand_base,
106 int freq)
107{
108 struct gpmc_timings t;
109 const int t_cer = 15;
110 const int t_avdp = 12;
111 const int t_cez = 20; /* max of t_cez, t_oez */
112 const int t_ds = 30;
113 const int t_wpl = 40;
114 const int t_wph = 30;
115 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
116 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
117 int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
118 int err, ticks_cez;
119 int cs = cfg->cs;
120 u32 reg;
121
122 if (cfg->flags & ONENAND_SYNC_READ) {
123 sync_read = 1;
124 } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
125 sync_read = 1;
126 sync_write = 1;
127 }
128
129 if (!freq) {
130 /* Very first call freq is not known */
131 err = omap2_onenand_set_async_mode(cs, onenand_base);
132 if (err)
133 return err;
134 reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
135 switch ((reg >> 4) & 0xf) {
136 case 0:
137 freq = 40;
138 break;
139 case 1:
140 freq = 54;
141 break;
142 case 2:
143 freq = 66;
144 break;
145 case 3:
146 freq = 83;
147 break;
148 case 4:
149 freq = 104;
150 break;
151 default:
152 freq = 54;
153 break;
154 }
155 first_time = 1;
156 }
157
158 switch (freq) {
159 case 83:
160 min_gpmc_clk_period = 12; /* 83 MHz */
161 t_ces = 5;
162 t_avds = 4;
163 t_avdh = 2;
164 t_ach = 6;
165 t_aavdh = 6;
166 t_rdyo = 9;
167 break;
168 case 66:
169 min_gpmc_clk_period = 15; /* 66 MHz */
170 t_ces = 6;
171 t_avds = 5;
172 t_avdh = 2;
173 t_ach = 6;
174 t_aavdh = 6;
175 t_rdyo = 11;
176 break;
177 default:
178 min_gpmc_clk_period = 18; /* 54 MHz */
179 t_ces = 7;
180 t_avds = 7;
181 t_avdh = 7;
182 t_ach = 9;
183 t_aavdh = 7;
184 t_rdyo = 15;
185 sync_write = 0;
186 break;
187 }
188
189 tick_ns = gpmc_ticks_to_ns(1);
190 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
191 gpmc_clk_ns = gpmc_ticks_to_ns(div);
192 if (gpmc_clk_ns < 15) /* >66Mhz */
193 hf = 1;
194 if (hf)
195 latency = 6;
196 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
197 latency = 3;
198 else
199 latency = 4;
200
201 if (first_time)
202 set_onenand_cfg(onenand_base, latency,
203 sync_read, sync_write, hf);
204
205 if (div == 1) {
206 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
207 reg |= (1 << 7);
208 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
209 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
210 reg |= (1 << 7);
211 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
212 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
213 reg |= (1 << 7);
214 reg |= (1 << 23);
215 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
216 } else {
217 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
218 reg &= ~(1 << 7);
219 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
220 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
221 reg &= ~(1 << 7);
222 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
223 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
224 reg &= ~(1 << 7);
225 reg &= ~(1 << 23);
226 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
227 }
228
229 /* Set synchronous read timings */
230 memset(&t, 0, sizeof(t));
231 t.sync_clk = min_gpmc_clk_period;
232 t.cs_on = 0;
233 t.adv_on = 0;
234 fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
235 fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
236 t.page_burst_access = gpmc_clk_ns;
237
238 /* Read */
239 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
240 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
241 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
242 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
243 t.cs_rd_off = t.oe_off;
244 ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
245 t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
246 ticks_cez);
247
248 /* Write */
249 if (sync_write) {
250 t.adv_wr_off = t.adv_rd_off;
251 t.we_on = 0;
252 t.we_off = t.cs_rd_off;
253 t.cs_wr_off = t.cs_rd_off;
254 t.wr_cycle = t.rd_cycle;
255 if (cpu_is_omap34xx()) {
256 t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
257 gpmc_ns_to_ticks(min_gpmc_clk_period +
258 t_rdyo));
259 t.wr_access = t.access;
260 }
261 } else {
262 t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,
263 t_avdp, t_cer));
264 t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
265 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
266 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
267 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
268 if (cpu_is_omap34xx()) {
269 t.wr_data_mux_bus = t.we_on;
270 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
271 }
272 }
273
274 /* Configure GPMC for synchronous read */
275 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
276 GPMC_CONFIG1_WRAPBURST_SUPP |
277 GPMC_CONFIG1_READMULTIPLE_SUPP |
278 (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |
279 (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
280 (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
281 GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
282 GPMC_CONFIG1_PAGE_LEN(2) |
283 (cpu_is_omap34xx() ? 0 :
284 (GPMC_CONFIG1_WAIT_READ_MON |
285 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
286 GPMC_CONFIG1_DEVICESIZE_16 |
287 GPMC_CONFIG1_DEVICETYPE_NOR |
288 GPMC_CONFIG1_MUXADDDATA);
289
290 err = gpmc_cs_set_timings(cs, &t);
291 if (err)
292 return err;
293
294 set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
295
296 return 0;
297}
298
299static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
300{
301 struct device *dev = &gpmc_onenand_device.dev;
302
303 /* Set sync timings in GPMC */
304 if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
305 freq) < 0) {
306 dev_err(dev, "Unable to set synchronous mode\n");
307 return -EINVAL;
308 }
309
310 return 0;
311}
312
313void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
314{
315 gpmc_onenand_data = _onenand_data;
316 gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
317 gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
318
319 if (cpu_is_omap24xx() &&
320 (gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
321 printk(KERN_ERR "Onenand using only SYNC_READ on 24xx\n");
322 gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
323 gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
324 }
325
326 if (platform_device_register(&gpmc_onenand_device) < 0) {
327 printk(KERN_ERR "Unable to register OneNAND device\n");
328 return;
329 }
330}
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
new file mode 100644
index 000000000000..df99d31d8b64
--- /dev/null
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -0,0 +1,189 @@
1/*
2 * linux/arch/arm/mach-omap2/gpmc-smc91x.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Contact: Tony Lindgren
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/smc91x.h>
19
20#include <mach/board.h>
21#include <mach/gpmc.h>
22#include <mach/gpmc-smc91x.h>
23
24static struct omap_smc91x_platform_data *gpmc_cfg;
25
26static struct resource gpmc_smc91x_resources[] = {
27 [0] = {
28 .flags = IORESOURCE_MEM,
29 },
30 [1] = {
31 .flags = IORESOURCE_IRQ,
32 },
33};
34
35static struct smc91x_platdata gpmc_smc91x_info = {
36 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
37};
38
39static struct platform_device gpmc_smc91x_device = {
40 .name = "smc91x",
41 .id = -1,
42 .num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
43 .resource = gpmc_smc91x_resources,
44 .dev = {
45 .platform_data = &gpmc_smc91x_info,
46 },
47};
48
49/*
50 * Set the gpmc timings for smc91c96. The timings are taken
51 * from the data sheet available at:
52 * http://www.smsc.com/main/catalog/lan91c96.html
53 * REVISIT: Level shifters can add at least to the access latency.
54 */
55static int smc91c96_gpmc_retime(void)
56{
57 struct gpmc_timings t;
58 const int t3 = 10; /* Figure 12.2 read and 12.4 write */
59 const int t4_r = 20; /* Figure 12.2 read */
60 const int t4_w = 5; /* Figure 12.4 write */
61 const int t5 = 25; /* Figure 12.2 read */
62 const int t6 = 15; /* Figure 12.2 read */
63 const int t7 = 5; /* Figure 12.4 write */
64 const int t8 = 5; /* Figure 12.4 write */
65 const int t20 = 185; /* Figure 12.2 read and 12.4 write */
66 u32 l;
67
68 memset(&t, 0, sizeof(t));
69
70 /* Read timings */
71 t.cs_on = 0;
72 t.adv_on = t.cs_on;
73 t.oe_on = t.adv_on + t3;
74 t.access = t.oe_on + t5;
75 t.oe_off = t.access;
76 t.adv_rd_off = t.oe_off + max(t4_r, t6);
77 t.cs_rd_off = t.oe_off;
78 t.rd_cycle = t20 - t.oe_on;
79
80 /* Write timings */
81 t.we_on = t.adv_on + t3;
82
83 if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) {
84 t.wr_data_mux_bus = t.we_on;
85 t.we_off = t.wr_data_mux_bus + t7;
86 } else
87 t.we_off = t.we_on + t7;
88 if (cpu_is_omap34xx())
89 t.wr_access = t.we_off;
90 t.adv_wr_off = t.we_off + max(t4_w, t8);
91 t.cs_wr_off = t.we_off + t4_w;
92 t.wr_cycle = t20 - t.we_on;
93
94 l = GPMC_CONFIG1_DEVICESIZE_16;
95 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
96 l |= GPMC_CONFIG1_MUXADDDATA;
97 if (gpmc_cfg->flags & GPMC_READ_MON)
98 l |= GPMC_CONFIG1_WAIT_READ_MON;
99 if (gpmc_cfg->flags & GPMC_WRITE_MON)
100 l |= GPMC_CONFIG1_WAIT_WRITE_MON;
101 if (gpmc_cfg->wait_pin)
102 l |= GPMC_CONFIG1_WAIT_PIN_SEL(gpmc_cfg->wait_pin);
103 gpmc_cs_write_reg(gpmc_cfg->cs, GPMC_CS_CONFIG1, l);
104
105 /*
106 * FIXME: Calculate the address and data bus muxed timings.
107 * Note that at least adv_rd_off needs to be changed according
108 * to omap3430 TRM Figure 11-11. Are the sdp boards using the
109 * FPGA in between smc91x and omap as the timings are different
110 * from above?
111 */
112 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
113 return 0;
114
115 return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
116}
117
118/*
119 * Initialize smc91x device connected to the GPMC. Note that we
120 * assume that pin multiplexing is done in the board-*.c file,
121 * or in the bootloader.
122 */
123void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
124{
125 unsigned long cs_mem_base;
126 int ret;
127
128 gpmc_cfg = board_data;
129
130 if (gpmc_cfg->flags & GPMC_TIMINGS_SMC91C96)
131 gpmc_cfg->retime = smc91c96_gpmc_retime;
132
133 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
134 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
135 return;
136 }
137
138 gpmc_smc91x_resources[0].start = cs_mem_base + 0x300;
139 gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
140 gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
141
142 if (gpmc_cfg->retime) {
143 ret = gpmc_cfg->retime();
144 if (ret != 0)
145 goto free1;
146 }
147
148 if (gpio_request(gpmc_cfg->gpio_irq, "SMC91X irq") < 0)
149 goto free1;
150
151 gpio_direction_input(gpmc_cfg->gpio_irq);
152 gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
153
154 if (gpmc_cfg->gpio_pwrdwn) {
155 ret = gpio_request(gpmc_cfg->gpio_pwrdwn, "SMC91X powerdown");
156 if (ret)
157 goto free2;
158 gpio_direction_output(gpmc_cfg->gpio_pwrdwn, 0);
159 }
160
161 if (gpmc_cfg->gpio_reset) {
162 ret = gpio_request(gpmc_cfg->gpio_reset, "SMC91X reset");
163 if (ret)
164 goto free3;
165
166 gpio_direction_output(gpmc_cfg->gpio_reset, 0);
167 gpio_set_value(gpmc_cfg->gpio_reset, 1);
168 msleep(100);
169 gpio_set_value(gpmc_cfg->gpio_reset, 0);
170 }
171
172 if (platform_device_register(&gpmc_smc91x_device) < 0) {
173 printk(KERN_ERR "Unable to register smc91x device\n");
174 gpio_free(gpmc_cfg->gpio_reset);
175 goto free3;
176 }
177
178 return;
179
180free3:
181 if (gpmc_cfg->gpio_pwrdwn)
182 gpio_free(gpmc_cfg->gpio_pwrdwn);
183free2:
184 gpio_free(gpmc_cfg->gpio_irq);
185free1:
186 gpmc_cs_free(gpmc_cfg->cs);
187
188 printk(KERN_ERR "Could not initialize smc91x\n");
189}
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7fc8c045ad5d..06e9cbe8b8eb 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -310,41 +310,62 @@ EXPORT_SYMBOL(omap_set_dma_transfer_params);
310 310
311void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) 311void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
312{ 312{
313 u16 w;
314
315 BUG_ON(omap_dma_in_1510_mode()); 313 BUG_ON(omap_dma_in_1510_mode());
316 314
317 if (cpu_class_is_omap2()) { 315 if (cpu_class_is_omap1()) {
318 REVISIT_24XX(); 316 u16 w;
319 return;
320 }
321 317
322 w = dma_read(CCR2(lch)); 318 w = dma_read(CCR2(lch));
323 w &= ~0x03; 319 w &= ~0x03;
324 320
325 switch (mode) { 321 switch (mode) {
326 case OMAP_DMA_CONSTANT_FILL: 322 case OMAP_DMA_CONSTANT_FILL:
327 w |= 0x01; 323 w |= 0x01;
328 break; 324 break;
329 case OMAP_DMA_TRANSPARENT_COPY: 325 case OMAP_DMA_TRANSPARENT_COPY:
330 w |= 0x02; 326 w |= 0x02;
331 break; 327 break;
332 case OMAP_DMA_COLOR_DIS: 328 case OMAP_DMA_COLOR_DIS:
333 break; 329 break;
334 default: 330 default:
335 BUG(); 331 BUG();
332 }
333 dma_write(w, CCR2(lch));
334
335 w = dma_read(LCH_CTRL(lch));
336 w &= ~0x0f;
337 /* Default is channel type 2D */
338 if (mode) {
339 dma_write((u16)color, COLOR_L(lch));
340 dma_write((u16)(color >> 16), COLOR_U(lch));
341 w |= 1; /* Channel type G */
342 }
343 dma_write(w, LCH_CTRL(lch));
336 } 344 }
337 dma_write(w, CCR2(lch));
338 345
339 w = dma_read(LCH_CTRL(lch)); 346 if (cpu_class_is_omap2()) {
340 w &= ~0x0f; 347 u32 val;
341 /* Default is channel type 2D */ 348
342 if (mode) { 349 val = dma_read(CCR(lch));
343 dma_write((u16)color, COLOR_L(lch)); 350 val &= ~((1 << 17) | (1 << 16));
344 dma_write((u16)(color >> 16), COLOR_U(lch)); 351
345 w |= 1; /* Channel type G */ 352 switch (mode) {
353 case OMAP_DMA_CONSTANT_FILL:
354 val |= 1 << 16;
355 break;
356 case OMAP_DMA_TRANSPARENT_COPY:
357 val |= 1 << 17;
358 break;
359 case OMAP_DMA_COLOR_DIS:
360 break;
361 default:
362 BUG();
363 }
364 dma_write(val, CCR(lch));
365
366 color &= 0xffffff;
367 dma_write(color, COLOR(lch));
346 } 368 }
347 dma_write(w, LCH_CTRL(lch));
348} 369}
349EXPORT_SYMBOL(omap_set_dma_color_mode); 370EXPORT_SYMBOL(omap_set_dma_color_mode);
350 371
@@ -1199,7 +1220,7 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
1199 * Failure: -EINVAL/-ENOMEM 1220 * Failure: -EINVAL/-ENOMEM
1200 */ 1221 */
1201int omap_request_dma_chain(int dev_id, const char *dev_name, 1222int omap_request_dma_chain(int dev_id, const char *dev_name,
1202 void (*callback) (int chain_id, u16 ch_status, 1223 void (*callback) (int lch, u16 ch_status,
1203 void *data), 1224 void *data),
1204 int *chain_id, int no_of_chans, int chain_mode, 1225 int *chain_id, int no_of_chans, int chain_mode,
1205 struct omap_dma_channel_params params) 1226 struct omap_dma_channel_params params)
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a303071d5e36..8b848391f0c8 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -5,7 +5,7 @@
5 * 5 *
6 * Copyright (C) 2007 Nokia Corporation. 6 * Copyright (C) 2007 Nokia Corporation.
7 * 7 *
8 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> 8 * Contact: Jarkko Nikula <jhnikula@gmail.com>
9 * 9 *
10 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License 11 * modify it under the terms of the GNU General Public License
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 54fe9665b182..19df76f97ab3 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -144,6 +144,7 @@
144#define OMAP_DMA4_CSSA_U(n) 0 144#define OMAP_DMA4_CSSA_U(n) 0
145#define OMAP_DMA4_CDSA_L(n) 0 145#define OMAP_DMA4_CDSA_L(n) 0
146#define OMAP_DMA4_CDSA_U(n) 0 146#define OMAP_DMA4_CDSA_U(n) 0
147#define OMAP1_DMA_COLOR(n) 0
147 148
148/*----------------------------------------------------------------------------*/ 149/*----------------------------------------------------------------------------*/
149 150
@@ -531,7 +532,7 @@ extern int omap_get_dma_index(int lch, int *ei, int *fi);
531/* Chaining APIs */ 532/* Chaining APIs */
532#ifndef CONFIG_ARCH_OMAP1 533#ifndef CONFIG_ARCH_OMAP1
533extern int omap_request_dma_chain(int dev_id, const char *dev_name, 534extern int omap_request_dma_chain(int dev_id, const char *dev_name,
534 void (*callback) (int chain_id, u16 ch_status, 535 void (*callback) (int lch, u16 ch_status,
535 void *data), 536 void *data),
536 int *chain_id, int no_of_chans, 537 int *chain_id, int no_of_chans,
537 int chain_mode, 538 int chain_mode,
diff --git a/arch/arm/plat-omap/include/mach/gpmc-smc91x.h b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
new file mode 100644
index 000000000000..b64fbee4d567
--- /dev/null
+++ b/arch/arm/plat-omap/include/mach/gpmc-smc91x.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
12
13#define GPMC_TIMINGS_SMC91C96 (1 << 4)
14#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
15#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
16#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
17
18struct omap_smc91x_platform_data {
19 int cs;
20 int gpio_irq;
21 int gpio_pwrdwn;
22 int gpio_reset;
23 int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
24 u32 flags;
25 int (*retime)(void);
26};
27
28#if defined(CONFIG_SMC91X) || \
29 defined(CONFIG_SMC91X_MODULE)
30
31extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
32
33#else
34
35#define board_smc91x_data NULL
36
37static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
38{
39}
40
41#endif
42#endif
diff --git a/arch/arm/plat-omap/include/mach/hwa742.h b/arch/arm/plat-omap/include/mach/hwa742.h
index 577f492f2d3c..886248d32b49 100644
--- a/arch/arm/plat-omap/include/mach/hwa742.h
+++ b/arch/arm/plat-omap/include/mach/hwa742.h
@@ -2,10 +2,6 @@
2#define _HWA742_H 2#define _HWA742_H
3 3
4struct hwa742_platform_data { 4struct hwa742_platform_data {
5 void (*power_up)(struct device *dev);
6 void (*power_down)(struct device *dev);
7 unsigned long (*get_clock_rate)(struct device *dev);
8
9 unsigned te_connected:1; 5 unsigned te_connected:1;
10}; 6};
11 7
diff --git a/arch/arm/plat-omap/include/mach/onenand.h b/arch/arm/plat-omap/include/mach/onenand.h
index 4649d302c263..72f433d7d827 100644
--- a/arch/arm/plat-omap/include/mach/onenand.h
+++ b/arch/arm/plat-omap/include/mach/onenand.h
@@ -9,8 +9,12 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h> 13#include <linux/mtd/partitions.h>
13 14
15#define ONENAND_SYNC_READ (1 << 0)
16#define ONENAND_SYNC_READWRITE (1 << 1)
17
14struct omap_onenand_platform_data { 18struct omap_onenand_platform_data {
15 int cs; 19 int cs;
16 int gpio_irq; 20 int gpio_irq;
@@ -18,8 +22,22 @@ struct omap_onenand_platform_data {
18 int nr_parts; 22 int nr_parts;
19 int (*onenand_setup)(void __iomem *, int freq); 23 int (*onenand_setup)(void __iomem *, int freq);
20 int dma_channel; 24 int dma_channel;
25 u8 flags;
21}; 26};
22 27
23int omap2_onenand_rephase(void);
24
25#define ONENAND_MAX_PARTITIONS 8 28#define ONENAND_MAX_PARTITIONS 8
29
30#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
31 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
32
33extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
34
35#else
36
37#define board_onenand_data NULL
38
39static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
40{
41}
42
43#endif
diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
index dc104cd96197..b97dfafeebda 100644
--- a/arch/arm/plat-omap/include/mach/vmalloc.h
+++ b/arch/arm/plat-omap/include/mach/vmalloc.h
@@ -17,5 +17,5 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 20#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
21 21
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 28b0a824b8cf..efa0e0111f38 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -91,11 +91,20 @@ static void omap_mcbsp_dump_reg(u8 id)
91static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) 91static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
92{ 92{
93 struct omap_mcbsp *mcbsp_tx = dev_id; 93 struct omap_mcbsp *mcbsp_tx = dev_id;
94 u16 irqst_spcr2;
94 95
95 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", 96 irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
96 OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2)); 97 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
97 98
98 complete(&mcbsp_tx->tx_irq_completion); 99 if (irqst_spcr2 & XSYNC_ERR) {
100 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
101 irqst_spcr2);
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
104 irqst_spcr2 & ~(XSYNC_ERR));
105 } else {
106 complete(&mcbsp_tx->tx_irq_completion);
107 }
99 108
100 return IRQ_HANDLED; 109 return IRQ_HANDLED;
101} 110}
@@ -103,11 +112,20 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
103static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id) 112static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
104{ 113{
105 struct omap_mcbsp *mcbsp_rx = dev_id; 114 struct omap_mcbsp *mcbsp_rx = dev_id;
115 u16 irqst_spcr1;
106 116
107 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", 117 irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
108 OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2)); 118 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
109 119
110 complete(&mcbsp_rx->rx_irq_completion); 120 if (irqst_spcr1 & RSYNC_ERR) {
121 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
122 irqst_spcr1);
123 /* Writing zero to RSYNC_ERR clears the IRQ */
124 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
125 irqst_spcr1 & ~(RSYNC_ERR));
126 } else {
127 complete(&mcbsp_rx->tx_irq_completion);
128 }
111 129
112 return IRQ_HANDLED; 130 return IRQ_HANDLED;
113} 131}
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4f0145d26246..bd44d1a9df9c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -38,8 +38,8 @@
38#define OMAP1_SRAM_VA VMALLOC_END 38#define OMAP1_SRAM_VA VMALLOC_END
39#define OMAP2_SRAM_PA 0x40200000 39#define OMAP2_SRAM_PA 0x40200000
40#define OMAP2_SRAM_PUB_PA 0x4020f800 40#define OMAP2_SRAM_PUB_PA 0x4020f800
41#define OMAP2_SRAM_VA VMALLOC_END 41#define OMAP2_SRAM_VA 0xe3000000
42#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800) 42#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
43#define OMAP3_SRAM_PA 0x40200000 43#define OMAP3_SRAM_PA 0x40200000
44#define OMAP3_SRAM_VA 0xd7000000 44#define OMAP3_SRAM_VA 0xd7000000
45#define OMAP3_SRAM_PUB_PA 0x40208000 45#define OMAP3_SRAM_PUB_PA 0x40208000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 19:27:22 -0500