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-rw-r--r--arch/xtensa/Kconfig3
-rw-r--r--arch/xtensa/boot/dts/xtfpga.dtsi12
-rw-r--r--arch/xtensa/include/asm/io.h2
-rw-r--r--arch/xtensa/include/asm/traps.h44
-rw-r--r--arch/xtensa/include/asm/vectors.h2
-rw-r--r--arch/xtensa/include/uapi/asm/unistd.h7
-rw-r--r--arch/xtensa/kernel/entry.S449
-rw-r--r--arch/xtensa/kernel/setup.c2
-rw-r--r--arch/xtensa/kernel/time.c1
-rw-r--r--arch/xtensa/kernel/vectors.S2
-rw-r--r--arch/xtensa/kernel/xtensa_ksyms.c2
-rw-r--r--arch/xtensa/mm/init.c13
-rw-r--r--arch/xtensa/mm/mmu.c2
-rw-r--r--arch/xtensa/platforms/xtfpga/setup.c7
-rw-r--r--arch/xtensa/variants/fsf/include/variant/tie.h9
15 files changed, 297 insertions, 260 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index ba56e11cbf77..c87ae7c6e5f9 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -20,6 +20,7 @@ config XTENSA
20 select HAVE_FUNCTION_TRACER 20 select HAVE_FUNCTION_TRACER
21 select HAVE_IRQ_TIME_ACCOUNTING 21 select HAVE_IRQ_TIME_ACCOUNTING
22 select HAVE_PERF_EVENTS 22 select HAVE_PERF_EVENTS
23 select COMMON_CLK
23 help 24 help
24 Xtensa processors are 32-bit RISC machines designed by Tensilica 25 Xtensa processors are 32-bit RISC machines designed by Tensilica
25 primarily for embedded systems. These processors are both 26 primarily for embedded systems. These processors are both
@@ -80,7 +81,6 @@ choice
80config XTENSA_VARIANT_FSF 81config XTENSA_VARIANT_FSF
81 bool "fsf - default (not generic) configuration" 82 bool "fsf - default (not generic) configuration"
82 select MMU 83 select MMU
83 select HAVE_XTENSA_GPIO32
84 84
85config XTENSA_VARIANT_DC232B 85config XTENSA_VARIANT_DC232B
86 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 86 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
@@ -135,7 +135,6 @@ config HAVE_SMP
135config SMP 135config SMP
136 bool "Enable Symmetric multi-processing support" 136 bool "Enable Symmetric multi-processing support"
137 depends on HAVE_SMP 137 depends on HAVE_SMP
138 select USE_GENERIC_SMP_HELPERS
139 select GENERIC_SMP_IDLE_THREAD 138 select GENERIC_SMP_IDLE_THREAD
140 help 139 help
141 Enabled SMP Software; allows more than one CPU/CORE 140 Enabled SMP Software; allows more than one CPU/CORE
diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
index 46b4f5eab421..e7370b11348e 100644
--- a/arch/xtensa/boot/dts/xtfpga.dtsi
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -35,6 +35,13 @@
35 interrupt-controller; 35 interrupt-controller;
36 }; 36 };
37 37
38 clocks {
39 osc: main-oscillator {
40 #clock-cells = <0>;
41 compatible = "fixed-clock";
42 };
43 };
44
38 serial0: serial@fd050020 { 45 serial0: serial@fd050020 {
39 device_type = "serial"; 46 device_type = "serial";
40 compatible = "ns16550a"; 47 compatible = "ns16550a";
@@ -42,9 +49,7 @@
42 reg = <0xfd050020 0x20>; 49 reg = <0xfd050020 0x20>;
43 reg-shift = <2>; 50 reg-shift = <2>;
44 interrupts = <0 1>; /* external irq 0 */ 51 interrupts = <0 1>; /* external irq 0 */
45 /* Filled in by platform_setup from FPGA register 52 clocks = <&osc>;
46 * clock-frequency = <100000000>;
47 */
48 }; 53 };
49 54
50 enet0: ethoc@fd030000 { 55 enet0: ethoc@fd030000 {
@@ -52,5 +57,6 @@
52 reg = <0xfd030000 0x4000 0xfd800000 0x4000>; 57 reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
53 interrupts = <1 1>; /* external irq 1 */ 58 interrupts = <1 1>; /* external irq 1 */
54 local-mac-address = [00 50 c2 13 6f 00]; 59 local-mac-address = [00 50 c2 13 6f 00];
60 clocks = <&osc>;
55 }; 61 };
56}; 62};
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 2a042d430c25..74944207167e 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -25,7 +25,7 @@
25 25
26#ifdef CONFIG_MMU 26#ifdef CONFIG_MMU
27 27
28#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF 28#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
29extern unsigned long xtensa_kio_paddr; 29extern unsigned long xtensa_kio_paddr;
30 30
31static inline unsigned long xtensa_get_kio_paddr(void) 31static inline unsigned long xtensa_get_kio_paddr(void)
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h
index 8c194f6af45e..677bfcf4ee5d 100644
--- a/arch/xtensa/include/asm/traps.h
+++ b/arch/xtensa/include/asm/traps.h
@@ -23,25 +23,37 @@ void secondary_trap_init(void);
23 23
24static inline void spill_registers(void) 24static inline void spill_registers(void)
25{ 25{
26 26#if XCHAL_NUM_AREGS > 16
27 __asm__ __volatile__ ( 27 __asm__ __volatile__ (
28 "movi a14, "__stringify((1 << PS_EXCM_BIT) | LOCKLEVEL)"\n\t" 28 " call12 1f\n"
29 "mov a12, a0\n\t" 29 " _j 2f\n"
30 "rsr a13, sar\n\t" 30 " retw\n"
31 "xsr a14, ps\n\t" 31 " .align 4\n"
32 "movi a0, _spill_registers\n\t" 32 "1:\n"
33 "rsync\n\t" 33 " _entry a1, 48\n"
34 "callx0 a0\n\t" 34 " addi a12, a0, 3\n"
35 "mov a0, a12\n\t" 35#if XCHAL_NUM_AREGS > 32
36 "wsr a13, sar\n\t" 36 " .rept (" __stringify(XCHAL_NUM_AREGS) " - 32) / 12\n"
37 "wsr a14, ps\n\t" 37 " _entry a1, 48\n"
38 : : 38 " mov a12, a0\n"
39#if defined(CONFIG_FRAME_POINTER) 39 " .endr\n"
40 : "a2", "a3", "a4", "a11", "a12", "a13", "a14", "a15", 40#endif
41 " _entry a1, 48\n"
42#if XCHAL_NUM_AREGS % 12 == 0
43 " mov a8, a8\n"
44#elif XCHAL_NUM_AREGS % 12 == 4
45 " mov a12, a12\n"
46#elif XCHAL_NUM_AREGS % 12 == 8
47 " mov a4, a4\n"
48#endif
49 " retw\n"
50 "2:\n"
51 : : : "a12", "a13", "memory");
41#else 52#else
42 : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", 53 __asm__ __volatile__ (
54 " mov a12, a12\n"
55 : : : "memory");
43#endif 56#endif
44 "memory");
45} 57}
46 58
47#endif /* _XTENSA_TRAPS_H */ 59#endif /* _XTENSA_TRAPS_H */
diff --git a/arch/xtensa/include/asm/vectors.h b/arch/xtensa/include/asm/vectors.h
index 5791b45d5a5d..f74ddfbb92ef 100644
--- a/arch/xtensa/include/asm/vectors.h
+++ b/arch/xtensa/include/asm/vectors.h
@@ -25,7 +25,7 @@
25#define XCHAL_KIO_DEFAULT_PADDR 0xf0000000 25#define XCHAL_KIO_DEFAULT_PADDR 0xf0000000
26#define XCHAL_KIO_SIZE 0x10000000 26#define XCHAL_KIO_SIZE 0x10000000
27 27
28#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF 28#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
29#define XCHAL_KIO_PADDR xtensa_get_kio_paddr() 29#define XCHAL_KIO_PADDR xtensa_get_kio_paddr()
30#else 30#else
31#define XCHAL_KIO_PADDR XCHAL_KIO_DEFAULT_PADDR 31#define XCHAL_KIO_PADDR XCHAL_KIO_DEFAULT_PADDR
diff --git a/arch/xtensa/include/uapi/asm/unistd.h b/arch/xtensa/include/uapi/asm/unistd.h
index 51940fec6990..b9395529f02d 100644
--- a/arch/xtensa/include/uapi/asm/unistd.h
+++ b/arch/xtensa/include/uapi/asm/unistd.h
@@ -734,7 +734,12 @@ __SYSCALL(332, sys_finit_module, 3)
734#define __NR_accept4 333 734#define __NR_accept4 333
735__SYSCALL(333, sys_accept4, 4) 735__SYSCALL(333, sys_accept4, 4)
736 736
737#define __NR_syscall_count 334 737#define __NR_sched_setattr 334
738__SYSCALL(334, sys_sched_setattr, 2)
739#define __NR_sched_getattr 335
740__SYSCALL(335, sys_sched_getattr, 3)
741
742#define __NR_syscall_count 336
738 743
739/* 744/*
740 * sysxtensa syscall handler 745 * sysxtensa syscall handler
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index 21dbe6bdb8ed..ef7f4990722b 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -1081,196 +1081,53 @@ ENTRY(fast_syscall_spill_registers)
1081 1081
1082 rsr a0, sar 1082 rsr a0, sar
1083 s32i a3, a2, PT_AREG3 1083 s32i a3, a2, PT_AREG3
1084 s32i a4, a2, PT_AREG4 1084 s32i a0, a2, PT_SAR
1085 s32i a0, a2, PT_AREG5 # store SAR to PT_AREG5
1086 1085
1087 /* The spill routine might clobber a7, a11, and a15. */ 1086 /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */
1088 1087
1088 s32i a4, a2, PT_AREG4
1089 s32i a7, a2, PT_AREG7 1089 s32i a7, a2, PT_AREG7
1090 s32i a8, a2, PT_AREG8
1090 s32i a11, a2, PT_AREG11 1091 s32i a11, a2, PT_AREG11
1092 s32i a12, a2, PT_AREG12
1091 s32i a15, a2, PT_AREG15 1093 s32i a15, a2, PT_AREG15
1092 1094
1093 call0 _spill_registers # destroys a3, a4, and SAR
1094
1095 /* Advance PC, restore registers and SAR, and return from exception. */
1096
1097 l32i a3, a2, PT_AREG5
1098 l32i a4, a2, PT_AREG4
1099 l32i a0, a2, PT_AREG0
1100 wsr a3, sar
1101 l32i a3, a2, PT_AREG3
1102
1103 /* Restore clobbered registers. */
1104
1105 l32i a7, a2, PT_AREG7
1106 l32i a11, a2, PT_AREG11
1107 l32i a15, a2, PT_AREG15
1108
1109 movi a2, 0
1110 rfe
1111
1112ENDPROC(fast_syscall_spill_registers)
1113
1114/* Fixup handler.
1115 *
1116 * We get here if the spill routine causes an exception, e.g. tlb miss.
1117 * We basically restore WINDOWBASE and WINDOWSTART to the condition when
1118 * we entered the spill routine and jump to the user exception handler.
1119 *
1120 * a0: value of depc, original value in depc
1121 * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
1122 * a3: exctable, original value in excsave1
1123 */
1124
1125ENTRY(fast_syscall_spill_registers_fixup)
1126
1127 rsr a2, windowbase # get current windowbase (a2 is saved)
1128 xsr a0, depc # restore depc and a0
1129 ssl a2 # set shift (32 - WB)
1130
1131 /* We need to make sure the current registers (a0-a3) are preserved.
1132 * To do this, we simply set the bit for the current window frame
1133 * in WS, so that the exception handlers save them to the task stack.
1134 */
1135
1136 xsr a3, excsave1 # get spill-mask
1137 slli a3, a3, 1 # shift left by one
1138
1139 slli a2, a3, 32-WSBITS
1140 src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy......
1141 wsr a2, windowstart # set corrected windowstart
1142
1143 srli a3, a3, 1
1144 rsr a2, excsave1
1145 l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2
1146 xsr a2, excsave1
1147 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3
1148 l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task)
1149 xsr a2, excsave1
1150
1151 /* Return to the original (user task) WINDOWBASE.
1152 * We leave the following frame behind:
1153 * a0, a1, a2 same
1154 * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE)
1155 * depc: depc (we have to return to that address)
1156 * excsave_1: exctable
1157 */
1158
1159 wsr a3, windowbase
1160 rsync
1161
1162 /* We are now in the original frame when we entered _spill_registers:
1163 * a0: return address
1164 * a1: used, stack pointer
1165 * a2: kernel stack pointer
1166 * a3: available
1167 * depc: exception address
1168 * excsave: exctable
1169 * Note: This frame might be the same as above.
1170 */
1171
1172 /* Setup stack pointer. */
1173
1174 addi a2, a2, -PT_USER_SIZE
1175 s32i a0, a2, PT_AREG0
1176
1177 /* Make sure we return to this fixup handler. */
1178
1179 movi a3, fast_syscall_spill_registers_fixup_return
1180 s32i a3, a2, PT_DEPC # setup depc
1181
1182 /* Jump to the exception handler. */
1183
1184 rsr a3, excsave1
1185 rsr a0, exccause
1186 addx4 a0, a0, a3 # find entry in table
1187 l32i a0, a0, EXC_TABLE_FAST_USER # load handler
1188 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1189 jx a0
1190
1191ENDPROC(fast_syscall_spill_registers_fixup)
1192
1193ENTRY(fast_syscall_spill_registers_fixup_return)
1194
1195 /* When we return here, all registers have been restored (a2: DEPC) */
1196
1197 wsr a2, depc # exception address
1198
1199 /* Restore fixup handler. */
1200
1201 rsr a2, excsave1
1202 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE
1203 movi a3, fast_syscall_spill_registers_fixup
1204 s32i a3, a2, EXC_TABLE_FIXUP
1205 rsr a3, windowbase
1206 s32i a3, a2, EXC_TABLE_PARAM
1207 l32i a2, a2, EXC_TABLE_KSTK
1208
1209 /* Load WB at the time the exception occurred. */
1210
1211 rsr a3, sar # WB is still in SAR
1212 neg a3, a3
1213 wsr a3, windowbase
1214 rsync
1215
1216 rsr a3, excsave1
1217 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1218
1219 rfde
1220
1221ENDPROC(fast_syscall_spill_registers_fixup_return)
1222
1223/*
1224 * spill all registers.
1225 *
1226 * This is not a real function. The following conditions must be met:
1227 *
1228 * - must be called with call0.
1229 * - uses a3, a4 and SAR.
1230 * - the last 'valid' register of each frame are clobbered.
1231 * - the caller must have registered a fixup handler
1232 * (or be inside a critical section)
1233 * - PS_EXCM must be set (PS_WOE cleared?)
1234 */
1235
1236ENTRY(_spill_registers)
1237
1238 /* 1095 /*
1239 * Rotate ws so that the current windowbase is at bit 0. 1096 * Rotate ws so that the current windowbase is at bit 0.
1240 * Assume ws = xxxwww1yy (www1 current window frame). 1097 * Assume ws = xxxwww1yy (www1 current window frame).
1241 * Rotate ws right so that a4 = yyxxxwww1. 1098 * Rotate ws right so that a4 = yyxxxwww1.
1242 */ 1099 */
1243 1100
1244 rsr a4, windowbase 1101 rsr a0, windowbase
1245 rsr a3, windowstart # a3 = xxxwww1yy 1102 rsr a3, windowstart # a3 = xxxwww1yy
1246 ssr a4 # holds WB 1103 ssr a0 # holds WB
1247 slli a4, a3, WSBITS 1104 slli a0, a3, WSBITS
1248 or a3, a3, a4 # a3 = xxxwww1yyxxxwww1yy 1105 or a3, a3, a0 # a3 = xxxwww1yyxxxwww1yy
1249 srl a3, a3 # a3 = 00xxxwww1yyxxxwww1 1106 srl a3, a3 # a3 = 00xxxwww1yyxxxwww1
1250 1107
1251 /* We are done if there are no more than the current register frame. */ 1108 /* We are done if there are no more than the current register frame. */
1252 1109
1253 extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww 1110 extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww
1254 movi a4, (1 << (WSBITS-1)) 1111 movi a0, (1 << (WSBITS-1))
1255 _beqz a3, .Lnospill # only one active frame? jump 1112 _beqz a3, .Lnospill # only one active frame? jump
1256 1113
1257 /* We want 1 at the top, so that we return to the current windowbase */ 1114 /* We want 1 at the top, so that we return to the current windowbase */
1258 1115
1259 or a3, a3, a4 # 1yyxxxwww 1116 or a3, a3, a0 # 1yyxxxwww
1260 1117
1261 /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */ 1118 /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
1262 1119
1263 wsr a3, windowstart # save shifted windowstart 1120 wsr a3, windowstart # save shifted windowstart
1264 neg a4, a3 1121 neg a0, a3
1265 and a3, a4, a3 # first bit set from right: 000010000 1122 and a3, a0, a3 # first bit set from right: 000010000
1266 1123
1267 ffs_ws a4, a3 # a4: shifts to skip empty frames 1124 ffs_ws a0, a3 # a0: shifts to skip empty frames
1268 movi a3, WSBITS 1125 movi a3, WSBITS
1269 sub a4, a3, a4 # WSBITS-a4:number of 0-bits from right 1126 sub a0, a3, a0 # WSBITS-a0:number of 0-bits from right
1270 ssr a4 # save in SAR for later. 1127 ssr a0 # save in SAR for later.
1271 1128
1272 rsr a3, windowbase 1129 rsr a3, windowbase
1273 add a3, a3, a4 1130 add a3, a3, a0
1274 wsr a3, windowbase 1131 wsr a3, windowbase
1275 rsync 1132 rsync
1276 1133
@@ -1285,22 +1142,6 @@ ENTRY(_spill_registers)
1285 * we have to save 4,8. or 12 registers. 1142 * we have to save 4,8. or 12 registers.
1286 */ 1143 */
1287 1144
1288 _bbsi.l a3, 1, .Lc4
1289 _bbsi.l a3, 2, .Lc8
1290
1291 /* Special case: we have a call12-frame starting at a4. */
1292
1293 _bbci.l a3, 3, .Lc12 # bit 3 shouldn't be zero! (Jump to Lc12 first)
1294
1295 s32e a4, a1, -16 # a1 is valid with an empty spill area
1296 l32e a4, a5, -12
1297 s32e a8, a4, -48
1298 mov a8, a4
1299 l32e a4, a1, -16
1300 j .Lc12c
1301
1302.Lnospill:
1303 ret
1304 1145
1305.Lloop: _bbsi.l a3, 1, .Lc4 1146.Lloop: _bbsi.l a3, 1, .Lc4
1306 _bbci.l a3, 2, .Lc12 1147 _bbci.l a3, 2, .Lc12
@@ -1314,20 +1155,10 @@ ENTRY(_spill_registers)
1314 s32e a9, a4, -28 1155 s32e a9, a4, -28
1315 s32e a10, a4, -24 1156 s32e a10, a4, -24
1316 s32e a11, a4, -20 1157 s32e a11, a4, -20
1317
1318 srli a11, a3, 2 # shift windowbase by 2 1158 srli a11, a3, 2 # shift windowbase by 2
1319 rotw 2 1159 rotw 2
1320 _bnei a3, 1, .Lloop 1160 _bnei a3, 1, .Lloop
1321 1161 j .Lexit
1322.Lexit: /* Done. Do the final rotation, set WS, and return. */
1323
1324 rotw 1
1325 rsr a3, windowbase
1326 ssl a3
1327 movi a3, 1
1328 sll a3, a3
1329 wsr a3, windowstart
1330 ret
1331 1162
1332.Lc4: s32e a4, a9, -16 1163.Lc4: s32e a4, a9, -16
1333 s32e a5, a9, -12 1164 s32e a5, a9, -12
@@ -1343,11 +1174,11 @@ ENTRY(_spill_registers)
1343 1174
1344 /* 12-register frame (call12) */ 1175 /* 12-register frame (call12) */
1345 1176
1346 l32e a2, a5, -12 1177 l32e a0, a5, -12
1347 s32e a8, a2, -48 1178 s32e a8, a0, -48
1348 mov a8, a2 1179 mov a8, a0
1349 1180
1350.Lc12c: s32e a9, a8, -44 1181 s32e a9, a8, -44
1351 s32e a10, a8, -40 1182 s32e a10, a8, -40
1352 s32e a11, a8, -36 1183 s32e a11, a8, -36
1353 s32e a12, a8, -32 1184 s32e a12, a8, -32
@@ -1367,30 +1198,54 @@ ENTRY(_spill_registers)
1367 */ 1198 */
1368 1199
1369 rotw 1 1200 rotw 1
1370 mov a5, a13 1201 mov a4, a13
1371 rotw -1 1202 rotw -1
1372 1203
1373 s32e a4, a9, -16 1204 s32e a4, a8, -16
1374 s32e a5, a9, -12 1205 s32e a5, a8, -12
1375 s32e a6, a9, -8 1206 s32e a6, a8, -8
1376 s32e a7, a9, -4 1207 s32e a7, a8, -4
1377 1208
1378 rotw 3 1209 rotw 3
1379 1210
1380 _beqi a3, 1, .Lexit 1211 _beqi a3, 1, .Lexit
1381 j .Lloop 1212 j .Lloop
1382 1213
1383.Linvalid_mask: 1214.Lexit:
1384 1215
1385 /* We get here because of an unrecoverable error in the window 1216 /* Done. Do the final rotation and set WS */
1386 * registers. If we are in user space, we kill the application, 1217
1387 * however, this condition is unrecoverable in kernel space. 1218 rotw 1
1388 */ 1219 rsr a3, windowbase
1220 ssl a3
1221 movi a3, 1
1222 sll a3, a3
1223 wsr a3, windowstart
1224.Lnospill:
1225
1226 /* Advance PC, restore registers and SAR, and return from exception. */
1227
1228 l32i a3, a2, PT_SAR
1229 l32i a0, a2, PT_AREG0
1230 wsr a3, sar
1231 l32i a3, a2, PT_AREG3
1389 1232
1390 rsr a0, ps 1233 /* Restore clobbered registers. */
1391 _bbci.l a0, PS_UM_BIT, 1f
1392 1234
1393 /* User space: Setup a dummy frame and kill application. 1235 l32i a4, a2, PT_AREG4
1236 l32i a7, a2, PT_AREG7
1237 l32i a8, a2, PT_AREG8
1238 l32i a11, a2, PT_AREG11
1239 l32i a12, a2, PT_AREG12
1240 l32i a15, a2, PT_AREG15
1241
1242 movi a2, 0
1243 rfe
1244
1245.Linvalid_mask:
1246
1247 /* We get here because of an unrecoverable error in the window
1248 * registers, so set up a dummy frame and kill the user application.
1394 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. 1249 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
1395 */ 1250 */
1396 1251
@@ -1414,14 +1269,136 @@ ENTRY(_spill_registers)
1414 movi a4, do_exit 1269 movi a4, do_exit
1415 callx4 a4 1270 callx4 a4
1416 1271
14171: /* Kernel space: PANIC! */ 1272 /* shouldn't return, so panic */
1418 1273
1419 wsr a0, excsave1 1274 wsr a0, excsave1
1420 movi a0, unrecoverable_exception 1275 movi a0, unrecoverable_exception
1421 callx0 a0 # should not return 1276 callx0 a0 # should not return
14221: j 1b 12771: j 1b
1423 1278
1424ENDPROC(_spill_registers) 1279
1280ENDPROC(fast_syscall_spill_registers)
1281
1282/* Fixup handler.
1283 *
1284 * We get here if the spill routine causes an exception, e.g. tlb miss.
1285 * We basically restore WINDOWBASE and WINDOWSTART to the condition when
1286 * we entered the spill routine and jump to the user exception handler.
1287 *
1288 * Note that we only need to restore the bits in windowstart that have not
1289 * been spilled yet by the _spill_register routine. Luckily, a3 contains a
1290 * rotated windowstart with only those bits set for frames that haven't been
1291 * spilled yet. Because a3 is rotated such that bit 0 represents the register
1292 * frame for the current windowbase - 1, we need to rotate a3 left by the
1293 * value of the current windowbase + 1 and move it to windowstart.
1294 *
1295 * a0: value of depc, original value in depc
1296 * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
1297 * a3: exctable, original value in excsave1
1298 */
1299
1300ENTRY(fast_syscall_spill_registers_fixup)
1301
1302 rsr a2, windowbase # get current windowbase (a2 is saved)
1303 xsr a0, depc # restore depc and a0
1304 ssl a2 # set shift (32 - WB)
1305
1306 /* We need to make sure the current registers (a0-a3) are preserved.
1307 * To do this, we simply set the bit for the current window frame
1308 * in WS, so that the exception handlers save them to the task stack.
1309 *
1310 * Note: we use a3 to set the windowbase, so we take a special care
1311 * of it, saving it in the original _spill_registers frame across
1312 * the exception handler call.
1313 */
1314
1315 xsr a3, excsave1 # get spill-mask
1316 slli a3, a3, 1 # shift left by one
1317 addi a3, a3, 1 # set the bit for the current window frame
1318
1319 slli a2, a3, 32-WSBITS
1320 src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy......
1321 wsr a2, windowstart # set corrected windowstart
1322
1323 srli a3, a3, 1
1324 rsr a2, excsave1
1325 l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2
1326 xsr a2, excsave1
1327 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3
1328 l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task)
1329 xsr a2, excsave1
1330
1331 /* Return to the original (user task) WINDOWBASE.
1332 * We leave the following frame behind:
1333 * a0, a1, a2 same
1334 * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE)
1335 * depc: depc (we have to return to that address)
1336 * excsave_1: exctable
1337 */
1338
1339 wsr a3, windowbase
1340 rsync
1341
1342 /* We are now in the original frame when we entered _spill_registers:
1343 * a0: return address
1344 * a1: used, stack pointer
1345 * a2: kernel stack pointer
1346 * a3: available
1347 * depc: exception address
1348 * excsave: exctable
1349 * Note: This frame might be the same as above.
1350 */
1351
1352 /* Setup stack pointer. */
1353
1354 addi a2, a2, -PT_USER_SIZE
1355 s32i a0, a2, PT_AREG0
1356
1357 /* Make sure we return to this fixup handler. */
1358
1359 movi a3, fast_syscall_spill_registers_fixup_return
1360 s32i a3, a2, PT_DEPC # setup depc
1361
1362 /* Jump to the exception handler. */
1363
1364 rsr a3, excsave1
1365 rsr a0, exccause
1366 addx4 a0, a0, a3 # find entry in table
1367 l32i a0, a0, EXC_TABLE_FAST_USER # load handler
1368 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1369 jx a0
1370
1371ENDPROC(fast_syscall_spill_registers_fixup)
1372
1373ENTRY(fast_syscall_spill_registers_fixup_return)
1374
1375 /* When we return here, all registers have been restored (a2: DEPC) */
1376
1377 wsr a2, depc # exception address
1378
1379 /* Restore fixup handler. */
1380
1381 rsr a2, excsave1
1382 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE
1383 movi a3, fast_syscall_spill_registers_fixup
1384 s32i a3, a2, EXC_TABLE_FIXUP
1385 rsr a3, windowbase
1386 s32i a3, a2, EXC_TABLE_PARAM
1387 l32i a2, a2, EXC_TABLE_KSTK
1388
1389 /* Load WB at the time the exception occurred. */
1390
1391 rsr a3, sar # WB is still in SAR
1392 neg a3, a3
1393 wsr a3, windowbase
1394 rsync
1395
1396 rsr a3, excsave1
1397 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE
1398
1399 rfde
1400
1401ENDPROC(fast_syscall_spill_registers_fixup_return)
1425 1402
1426#ifdef CONFIG_MMU 1403#ifdef CONFIG_MMU
1427/* 1404/*
@@ -1794,6 +1771,43 @@ ENTRY(system_call)
1794 1771
1795ENDPROC(system_call) 1772ENDPROC(system_call)
1796 1773
1774/*
1775 * Spill live registers on the kernel stack macro.
1776 *
1777 * Entry condition: ps.woe is set, ps.excm is cleared
1778 * Exit condition: windowstart has single bit set
1779 * May clobber: a12, a13
1780 */
1781 .macro spill_registers_kernel
1782
1783#if XCHAL_NUM_AREGS > 16
1784 call12 1f
1785 _j 2f
1786 retw
1787 .align 4
17881:
1789 _entry a1, 48
1790 addi a12, a0, 3
1791#if XCHAL_NUM_AREGS > 32
1792 .rept (XCHAL_NUM_AREGS - 32) / 12
1793 _entry a1, 48
1794 mov a12, a0
1795 .endr
1796#endif
1797 _entry a1, 48
1798#if XCHAL_NUM_AREGS % 12 == 0
1799 mov a8, a8
1800#elif XCHAL_NUM_AREGS % 12 == 4
1801 mov a12, a12
1802#elif XCHAL_NUM_AREGS % 12 == 8
1803 mov a4, a4
1804#endif
1805 retw
18062:
1807#else
1808 mov a12, a12
1809#endif
1810 .endm
1797 1811
1798/* 1812/*
1799 * Task switch. 1813 * Task switch.
@@ -1806,21 +1820,20 @@ ENTRY(_switch_to)
1806 1820
1807 entry a1, 16 1821 entry a1, 16
1808 1822
1809 mov a12, a2 # preserve 'prev' (a2) 1823 mov a10, a2 # preserve 'prev' (a2)
1810 mov a13, a3 # and 'next' (a3) 1824 mov a11, a3 # and 'next' (a3)
1811 1825
1812 l32i a4, a2, TASK_THREAD_INFO 1826 l32i a4, a2, TASK_THREAD_INFO
1813 l32i a5, a3, TASK_THREAD_INFO 1827 l32i a5, a3, TASK_THREAD_INFO
1814 1828
1815 save_xtregs_user a4 a6 a8 a9 a10 a11 THREAD_XTREGS_USER 1829 save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
1816 1830
1817 s32i a0, a12, THREAD_RA # save return address 1831 s32i a0, a10, THREAD_RA # save return address
1818 s32i a1, a12, THREAD_SP # save stack pointer 1832 s32i a1, a10, THREAD_SP # save stack pointer
1819 1833
1820 /* Disable ints while we manipulate the stack pointer. */ 1834 /* Disable ints while we manipulate the stack pointer. */
1821 1835
1822 movi a14, (1 << PS_EXCM_BIT) | LOCKLEVEL 1836 rsil a14, LOCKLEVEL
1823 xsr a14, ps
1824 rsr a3, excsave1 1837 rsr a3, excsave1
1825 rsync 1838 rsync
1826 s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */ 1839 s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */
@@ -1835,7 +1848,7 @@ ENTRY(_switch_to)
1835 1848
1836 /* Flush register file. */ 1849 /* Flush register file. */
1837 1850
1838 call0 _spill_registers # destroys a3, a4, and SAR 1851 spill_registers_kernel
1839 1852
1840 /* Set kernel stack (and leave critical section) 1853 /* Set kernel stack (and leave critical section)
1841 * Note: It's save to set it here. The stack will not be overwritten 1854 * Note: It's save to set it here. The stack will not be overwritten
@@ -1851,13 +1864,13 @@ ENTRY(_switch_to)
1851 1864
1852 /* restore context of the task 'next' */ 1865 /* restore context of the task 'next' */
1853 1866
1854 l32i a0, a13, THREAD_RA # restore return address 1867 l32i a0, a11, THREAD_RA # restore return address
1855 l32i a1, a13, THREAD_SP # restore stack pointer 1868 l32i a1, a11, THREAD_SP # restore stack pointer
1856 1869
1857 load_xtregs_user a5 a6 a8 a9 a10 a11 THREAD_XTREGS_USER 1870 load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER
1858 1871
1859 wsr a14, ps 1872 wsr a14, ps
1860 mov a2, a12 # return 'prev' 1873 mov a2, a10 # return 'prev'
1861 rsync 1874 rsync
1862 1875
1863 retw 1876 retw
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 7d12af1317f1..84fe931bb60e 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -22,6 +22,7 @@
22#include <linux/bootmem.h> 22#include <linux/bootmem.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/percpu.h> 24#include <linux/percpu.h>
25#include <linux/clk-provider.h>
25#include <linux/cpu.h> 26#include <linux/cpu.h>
26#include <linux/of_fdt.h> 27#include <linux/of_fdt.h>
27#include <linux/of_platform.h> 28#include <linux/of_platform.h>
@@ -276,6 +277,7 @@ void __init early_init_devtree(void *params)
276 277
277static int __init xtensa_device_probe(void) 278static int __init xtensa_device_probe(void)
278{ 279{
280 of_clk_init(NULL);
279 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 281 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
280 return 0; 282 return 0;
281} 283}
diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c
index 08b769d3b3a1..2a1823de69cc 100644
--- a/arch/xtensa/kernel/time.c
+++ b/arch/xtensa/kernel/time.c
@@ -30,6 +30,7 @@
30#include <asm/platform.h> 30#include <asm/platform.h>
31 31
32unsigned long ccount_freq; /* ccount Hz */ 32unsigned long ccount_freq; /* ccount Hz */
33EXPORT_SYMBOL(ccount_freq);
33 34
34static cycle_t ccount_read(struct clocksource *cs) 35static cycle_t ccount_read(struct clocksource *cs)
35{ 36{
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S
index cb8fd44caabc..f9e1ec346e35 100644
--- a/arch/xtensa/kernel/vectors.S
+++ b/arch/xtensa/kernel/vectors.S
@@ -235,7 +235,7 @@ ENTRY(_DoubleExceptionVector)
235 235
236 /* Check for overflow/underflow exception, jump if overflow. */ 236 /* Check for overflow/underflow exception, jump if overflow. */
237 237
238 _bbci.l a0, 6, _DoubleExceptionVector_WindowOverflow 238 bbci.l a0, 6, _DoubleExceptionVector_WindowOverflow
239 239
240 /* 240 /*
241 * Restart window underflow exception. 241 * Restart window underflow exception.
diff --git a/arch/xtensa/kernel/xtensa_ksyms.c b/arch/xtensa/kernel/xtensa_ksyms.c
index 74a60c7e085e..80b33ed51f31 100644
--- a/arch/xtensa/kernel/xtensa_ksyms.c
+++ b/arch/xtensa/kernel/xtensa_ksyms.c
@@ -122,9 +122,7 @@ EXPORT_SYMBOL(insw);
122EXPORT_SYMBOL(insl); 122EXPORT_SYMBOL(insl);
123 123
124extern long common_exception_return; 124extern long common_exception_return;
125extern long _spill_registers;
126EXPORT_SYMBOL(common_exception_return); 125EXPORT_SYMBOL(common_exception_return);
127EXPORT_SYMBOL(_spill_registers);
128 126
129#ifdef CONFIG_FUNCTION_TRACER 127#ifdef CONFIG_FUNCTION_TRACER
130EXPORT_SYMBOL(_mcount); 128EXPORT_SYMBOL(_mcount);
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index 479d7537a32a..aff108df92d3 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -90,7 +90,7 @@ int __init mem_reserve(unsigned long start, unsigned long end, int must_exist)
90 90
91 91
92/* 92/*
93 * Initialize the bootmem system and give it all the memory we have available. 93 * Initialize the bootmem system and give it all low memory we have available.
94 */ 94 */
95 95
96void __init bootmem_init(void) 96void __init bootmem_init(void)
@@ -142,9 +142,14 @@ void __init bootmem_init(void)
142 142
143 /* Add all remaining memory pieces into the bootmem map */ 143 /* Add all remaining memory pieces into the bootmem map */
144 144
145 for (i=0; i<sysmem.nr_banks; i++) 145 for (i = 0; i < sysmem.nr_banks; i++) {
146 free_bootmem(sysmem.bank[i].start, 146 if (sysmem.bank[i].start >> PAGE_SHIFT < max_low_pfn) {
147 sysmem.bank[i].end - sysmem.bank[i].start); 147 unsigned long end = min(max_low_pfn << PAGE_SHIFT,
148 sysmem.bank[i].end);
149 free_bootmem(sysmem.bank[i].start,
150 end - sysmem.bank[i].start);
151 }
152 }
148 153
149} 154}
150 155
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
index 36ec171698b8..861203e958da 100644
--- a/arch/xtensa/mm/mmu.c
+++ b/arch/xtensa/mm/mmu.c
@@ -39,7 +39,7 @@ void init_mmu(void)
39 set_itlbcfg_register(0); 39 set_itlbcfg_register(0);
40 set_dtlbcfg_register(0); 40 set_dtlbcfg_register(0);
41#endif 41#endif
42#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF 42#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)
43 /* 43 /*
44 * Update the IO area mapping in case xtensa_kio_paddr has changed 44 * Update the IO area mapping in case xtensa_kio_paddr has changed
45 */ 45 */
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index 800227862fe8..57fd08b36f51 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -135,11 +135,11 @@ static void __init update_local_mac(struct device_node *node)
135 135
136static int __init machine_setup(void) 136static int __init machine_setup(void)
137{ 137{
138 struct device_node *serial; 138 struct device_node *clock;
139 struct device_node *eth = NULL; 139 struct device_node *eth = NULL;
140 140
141 for_each_compatible_node(serial, NULL, "ns16550a") 141 for_each_node_by_name(clock, "main-oscillator")
142 update_clock_frequency(serial); 142 update_clock_frequency(clock);
143 143
144 if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc"))) 144 if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
145 update_local_mac(eth); 145 update_local_mac(eth);
@@ -290,6 +290,7 @@ static int __init xtavnet_init(void)
290 * knows whether they set it correctly on the DIP switches. 290 * knows whether they set it correctly on the DIP switches.
291 */ 291 */
292 pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr); 292 pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr);
293 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR;
293 294
294 return 0; 295 return 0;
295} 296}
diff --git a/arch/xtensa/variants/fsf/include/variant/tie.h b/arch/xtensa/variants/fsf/include/variant/tie.h
index bf4020116df5..244cdea4dee5 100644
--- a/arch/xtensa/variants/fsf/include/variant/tie.h
+++ b/arch/xtensa/variants/fsf/include/variant/tie.h
@@ -18,13 +18,6 @@
18#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ 18#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20 20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP7_NAME "XTIOP"
23#define XCHAL_CP7_IDENT XTIOP
24#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
25#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
26#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
27
28/* Filler info for unassigned coprocessors, to simplify arrays etc: */ 21/* Filler info for unassigned coprocessors, to simplify arrays etc: */
29#define XCHAL_NCP_SA_SIZE 0 22#define XCHAL_NCP_SA_SIZE 0
30#define XCHAL_NCP_SA_ALIGN 1 23#define XCHAL_NCP_SA_ALIGN 1
@@ -42,6 +35,8 @@
42#define XCHAL_CP5_SA_ALIGN 1 35#define XCHAL_CP5_SA_ALIGN 1
43#define XCHAL_CP6_SA_SIZE 0 36#define XCHAL_CP6_SA_SIZE 0
44#define XCHAL_CP6_SA_ALIGN 1 37#define XCHAL_CP6_SA_ALIGN 1
38#define XCHAL_CP7_SA_SIZE 0
39#define XCHAL_CP7_SA_ALIGN 1
45 40
46/* Save area for non-coprocessor optional and custom (TIE) state: */ 41/* Save area for non-coprocessor optional and custom (TIE) state: */
47#define XCHAL_NCP_SA_SIZE 0 42#define XCHAL_NCP_SA_SIZE 0
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 20:56:52 -0500