diff options
Diffstat (limited to 'arch/xtensa/kernel')
-rw-r--r-- | arch/xtensa/kernel/align.S | 42 | ||||
-rw-r--r-- | arch/xtensa/kernel/coprocessor.S | 2 | ||||
-rw-r--r-- | arch/xtensa/kernel/entry.S | 28 | ||||
-rw-r--r-- | arch/xtensa/kernel/head.S | 53 | ||||
-rw-r--r-- | arch/xtensa/kernel/pci-dma.c | 44 | ||||
-rw-r--r-- | arch/xtensa/kernel/process.c | 37 | ||||
-rw-r--r-- | arch/xtensa/kernel/ptrace.c | 2 | ||||
-rw-r--r-- | arch/xtensa/kernel/setup.c | 41 | ||||
-rw-r--r-- | arch/xtensa/kernel/signal.c | 16 | ||||
-rw-r--r-- | arch/xtensa/kernel/syscalls.c | 4 | ||||
-rw-r--r-- | arch/xtensa/kernel/traps.c | 56 | ||||
-rw-r--r-- | arch/xtensa/kernel/vectors.S | 12 | ||||
-rw-r--r-- | arch/xtensa/kernel/vmlinux.lds.S | 27 |
13 files changed, 157 insertions, 207 deletions
diff --git a/arch/xtensa/kernel/align.S b/arch/xtensa/kernel/align.S index a4956578a24d..33d6e9d2e83c 100644 --- a/arch/xtensa/kernel/align.S +++ b/arch/xtensa/kernel/align.S | |||
@@ -16,14 +16,9 @@ | |||
16 | */ | 16 | */ |
17 | 17 | ||
18 | #include <linux/linkage.h> | 18 | #include <linux/linkage.h> |
19 | #include <asm/ptrace.h> | ||
20 | #include <asm/ptrace.h> | ||
21 | #include <asm/current.h> | 19 | #include <asm/current.h> |
22 | #include <asm/asm-offsets.h> | 20 | #include <asm/asm-offsets.h> |
23 | #include <asm/pgtable.h> | ||
24 | #include <asm/processor.h> | 21 | #include <asm/processor.h> |
25 | #include <asm/page.h> | ||
26 | #include <asm/thread_info.h> | ||
27 | 22 | ||
28 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION | 23 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION |
29 | 24 | ||
@@ -216,7 +211,7 @@ ENTRY(fast_unaligned) | |||
216 | 211 | ||
217 | extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble | 212 | extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble |
218 | 213 | ||
219 | #if XCHAL_HAVE_NARROW | 214 | #if XCHAL_HAVE_DENSITY |
220 | _beqi a5, OP0_L32I_N, .Lload # L32I.N, jump | 215 | _beqi a5, OP0_L32I_N, .Lload # L32I.N, jump |
221 | addi a6, a5, -OP0_S32I_N | 216 | addi a6, a5, -OP0_S32I_N |
222 | _beqz a6, .Lstore # S32I.N, do a store | 217 | _beqz a6, .Lstore # S32I.N, do a store |
@@ -251,7 +246,7 @@ ENTRY(fast_unaligned) | |||
251 | #endif | 246 | #endif |
252 | __src_b a3, a5, a6 # a3 has the data word | 247 | __src_b a3, a5, a6 # a3 has the data word |
253 | 248 | ||
254 | #if XCHAL_HAVE_NARROW | 249 | #if XCHAL_HAVE_DENSITY |
255 | addi a7, a7, 2 # increment PC (assume 16-bit insn) | 250 | addi a7, a7, 2 # increment PC (assume 16-bit insn) |
256 | 251 | ||
257 | extui a5, a4, INSN_OP0, 4 | 252 | extui a5, a4, INSN_OP0, 4 |
@@ -279,14 +274,14 @@ ENTRY(fast_unaligned) | |||
279 | 274 | ||
280 | 1: | 275 | 1: |
281 | 276 | ||
282 | #if XCHAL_HAVE_LOOP | 277 | #if XCHAL_HAVE_LOOPS |
283 | rsr a3, LEND # check if we reached LEND | 278 | rsr a5, LEND # check if we reached LEND |
284 | bne a7, a3, 1f | 279 | bne a7, a5, 1f |
285 | rsr a3, LCOUNT # and LCOUNT != 0 | 280 | rsr a5, LCOUNT # and LCOUNT != 0 |
286 | beqz a3, 1f | 281 | beqz a5, 1f |
287 | addi a3, a3, -1 # decrement LCOUNT and set | 282 | addi a5, a5, -1 # decrement LCOUNT and set |
288 | rsr a7, LBEG # set PC to LBEGIN | 283 | rsr a7, LBEG # set PC to LBEGIN |
289 | wsr a3, LCOUNT | 284 | wsr a5, LCOUNT |
290 | #endif | 285 | #endif |
291 | 286 | ||
292 | 1: wsr a7, EPC_1 # skip load instruction | 287 | 1: wsr a7, EPC_1 # skip load instruction |
@@ -336,7 +331,7 @@ ENTRY(fast_unaligned) | |||
336 | 331 | ||
337 | movi a6, 0 # mask: ffffffff:00000000 | 332 | movi a6, 0 # mask: ffffffff:00000000 |
338 | 333 | ||
339 | #if XCHAL_HAVE_NARROW | 334 | #if XCHAL_HAVE_DENSITY |
340 | addi a7, a7, 2 # incr. PC,assume 16-bit instruction | 335 | addi a7, a7, 2 # incr. PC,assume 16-bit instruction |
341 | 336 | ||
342 | extui a5, a4, INSN_OP0, 4 # extract OP0 | 337 | extui a5, a4, INSN_OP0, 4 # extract OP0 |
@@ -359,14 +354,14 @@ ENTRY(fast_unaligned) | |||
359 | /* Get memory address */ | 354 | /* Get memory address */ |
360 | 355 | ||
361 | 1: | 356 | 1: |
362 | #if XCHAL_HAVE_LOOP | 357 | #if XCHAL_HAVE_LOOPS |
363 | rsr a3, LEND # check if we reached LEND | 358 | rsr a4, LEND # check if we reached LEND |
364 | bne a7, a3, 1f | 359 | bne a7, a4, 1f |
365 | rsr a3, LCOUNT # and LCOUNT != 0 | 360 | rsr a4, LCOUNT # and LCOUNT != 0 |
366 | beqz a3, 1f | 361 | beqz a4, 1f |
367 | addi a3, a3, -1 # decrement LCOUNT and set | 362 | addi a4, a4, -1 # decrement LCOUNT and set |
368 | rsr a7, LBEG # set PC to LBEGIN | 363 | rsr a7, LBEG # set PC to LBEGIN |
369 | wsr a3, LCOUNT | 364 | wsr a4, LCOUNT |
370 | #endif | 365 | #endif |
371 | 366 | ||
372 | 1: wsr a7, EPC_1 # skip store instruction | 367 | 1: wsr a7, EPC_1 # skip store instruction |
@@ -416,6 +411,7 @@ ENTRY(fast_unaligned) | |||
416 | 411 | ||
417 | /* Restore working register */ | 412 | /* Restore working register */ |
418 | 413 | ||
414 | l32i a8, a2, PT_AREG8 | ||
419 | l32i a7, a2, PT_AREG7 | 415 | l32i a7, a2, PT_AREG7 |
420 | l32i a6, a2, PT_AREG6 | 416 | l32i a6, a2, PT_AREG6 |
421 | l32i a5, a2, PT_AREG5 | 417 | l32i a5, a2, PT_AREG5 |
@@ -446,7 +442,7 @@ ENTRY(fast_unaligned) | |||
446 | mov a1, a2 | 442 | mov a1, a2 |
447 | 443 | ||
448 | rsr a0, PS | 444 | rsr a0, PS |
449 | bbsi.l a2, PS_UM_SHIFT, 1f # jump if user mode | 445 | bbsi.l a2, PS_UM_BIT, 1f # jump if user mode |
450 | 446 | ||
451 | movi a0, _kernel_exception | 447 | movi a0, _kernel_exception |
452 | jx a0 | 448 | jx a0 |
diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S index cf5a93fb6a2e..01bcb9fcfcbd 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S | |||
@@ -90,7 +90,6 @@ ENTRY(enable_coprocessor) | |||
90 | rsync | 90 | rsync |
91 | retw | 91 | retw |
92 | 92 | ||
93 | #endif | ||
94 | 93 | ||
95 | ENTRY(save_coprocessor_extra) | 94 | ENTRY(save_coprocessor_extra) |
96 | entry sp, 16 | 95 | entry sp, 16 |
@@ -197,4 +196,5 @@ _xtensa_reginfo_tables: | |||
197 | XCHAL_CP7_SA_CONTENTS_LIBDB | 196 | XCHAL_CP7_SA_CONTENTS_LIBDB |
198 | .word 0xFC000000 /* invalid register number,marks end of table*/ | 197 | .word 0xFC000000 /* invalid register number,marks end of table*/ |
199 | _xtensa_reginfo_table_end: | 198 | _xtensa_reginfo_table_end: |
199 | #endif | ||
200 | 200 | ||
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index 89e409e9e0de..c0b56b17927f 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S | |||
@@ -24,7 +24,7 @@ | |||
24 | #include <asm/pgtable.h> | 24 | #include <asm/pgtable.h> |
25 | #include <asm/page.h> | 25 | #include <asm/page.h> |
26 | #include <asm/signal.h> | 26 | #include <asm/signal.h> |
27 | #include <xtensa/coreasm.h> | 27 | #include <asm/tlbflush.h> |
28 | 28 | ||
29 | /* Unimplemented features. */ | 29 | /* Unimplemented features. */ |
30 | 30 | ||
@@ -364,7 +364,7 @@ common_exception: | |||
364 | movi a2, 1 | 364 | movi a2, 1 |
365 | extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0] | 365 | extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0] |
366 | moveqz a3, a2, a0 # a3 = 1 iff interrupt exception | 366 | moveqz a3, a2, a0 # a3 = 1 iff interrupt exception |
367 | movi a2, PS_WOE_MASK | 367 | movi a2, 1 << PS_WOE_BIT |
368 | or a3, a3, a2 | 368 | or a3, a3, a2 |
369 | rsr a0, EXCCAUSE | 369 | rsr a0, EXCCAUSE |
370 | xsr a3, PS | 370 | xsr a3, PS |
@@ -399,7 +399,7 @@ common_exception_return: | |||
399 | /* Jump if we are returning from kernel exceptions. */ | 399 | /* Jump if we are returning from kernel exceptions. */ |
400 | 400 | ||
401 | 1: l32i a3, a1, PT_PS | 401 | 1: l32i a3, a1, PT_PS |
402 | _bbsi.l a3, PS_UM_SHIFT, 2f | 402 | _bbsi.l a3, PS_UM_BIT, 2f |
403 | j kernel_exception_exit | 403 | j kernel_exception_exit |
404 | 404 | ||
405 | /* Specific to a user exception exit: | 405 | /* Specific to a user exception exit: |
@@ -422,7 +422,7 @@ common_exception_return: | |||
422 | * (Hint: There is only one user exception frame on stack) | 422 | * (Hint: There is only one user exception frame on stack) |
423 | */ | 423 | */ |
424 | 424 | ||
425 | movi a3, PS_WOE_MASK | 425 | movi a3, 1 << PS_WOE_BIT |
426 | 426 | ||
427 | _bbsi.l a4, TIF_NEED_RESCHED, 3f | 427 | _bbsi.l a4, TIF_NEED_RESCHED, 3f |
428 | _bbci.l a4, TIF_SIGPENDING, 4f | 428 | _bbci.l a4, TIF_SIGPENDING, 4f |
@@ -694,7 +694,7 @@ common_exception_exit: | |||
694 | ENTRY(debug_exception) | 694 | ENTRY(debug_exception) |
695 | 695 | ||
696 | rsr a0, EPS + XCHAL_DEBUGLEVEL | 696 | rsr a0, EPS + XCHAL_DEBUGLEVEL |
697 | bbsi.l a0, PS_EXCM_SHIFT, 1f # exception mode | 697 | bbsi.l a0, PS_EXCM_BIT, 1f # exception mode |
698 | 698 | ||
699 | /* Set EPC_1 and EXCCAUSE */ | 699 | /* Set EPC_1 and EXCCAUSE */ |
700 | 700 | ||
@@ -707,7 +707,7 @@ ENTRY(debug_exception) | |||
707 | 707 | ||
708 | /* Restore PS to the value before the debug exc but with PS.EXCM set.*/ | 708 | /* Restore PS to the value before the debug exc but with PS.EXCM set.*/ |
709 | 709 | ||
710 | movi a2, 1 << PS_EXCM_SHIFT | 710 | movi a2, 1 << PS_EXCM_BIT |
711 | or a2, a0, a2 | 711 | or a2, a0, a2 |
712 | movi a0, debug_exception # restore a3, debug jump vector | 712 | movi a0, debug_exception # restore a3, debug jump vector |
713 | wsr a2, PS | 713 | wsr a2, PS |
@@ -715,7 +715,7 @@ ENTRY(debug_exception) | |||
715 | 715 | ||
716 | /* Switch to kernel/user stack, restore jump vector, and save a0 */ | 716 | /* Switch to kernel/user stack, restore jump vector, and save a0 */ |
717 | 717 | ||
718 | bbsi.l a2, PS_UM_SHIFT, 2f # jump if user mode | 718 | bbsi.l a2, PS_UM_BIT, 2f # jump if user mode |
719 | 719 | ||
720 | addi a2, a1, -16-PT_SIZE # assume kernel stack | 720 | addi a2, a1, -16-PT_SIZE # assume kernel stack |
721 | s32i a0, a2, PT_AREG0 | 721 | s32i a0, a2, PT_AREG0 |
@@ -778,7 +778,7 @@ ENTRY(unrecoverable_exception) | |||
778 | wsr a1, WINDOWBASE | 778 | wsr a1, WINDOWBASE |
779 | rsync | 779 | rsync |
780 | 780 | ||
781 | movi a1, PS_WOE_MASK | 1 | 781 | movi a1, (1 << PS_WOE_BIT) | 1 |
782 | wsr a1, PS | 782 | wsr a1, PS |
783 | rsync | 783 | rsync |
784 | 784 | ||
@@ -1491,7 +1491,7 @@ ENTRY(_spill_registers) | |||
1491 | */ | 1491 | */ |
1492 | 1492 | ||
1493 | rsr a0, PS | 1493 | rsr a0, PS |
1494 | _bbci.l a0, PS_UM_SHIFT, 1f | 1494 | _bbci.l a0, PS_UM_BIT, 1f |
1495 | 1495 | ||
1496 | /* User space: Setup a dummy frame and kill application. | 1496 | /* User space: Setup a dummy frame and kill application. |
1497 | * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. | 1497 | * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. |
@@ -1510,7 +1510,7 @@ ENTRY(_spill_registers) | |||
1510 | l32i a1, a3, EXC_TABLE_KSTK | 1510 | l32i a1, a3, EXC_TABLE_KSTK |
1511 | wsr a3, EXCSAVE_1 | 1511 | wsr a3, EXCSAVE_1 |
1512 | 1512 | ||
1513 | movi a4, PS_WOE_MASK | 1 | 1513 | movi a4, (1 << PS_WOE_BIT) | 1 |
1514 | wsr a4, PS | 1514 | wsr a4, PS |
1515 | rsync | 1515 | rsync |
1516 | 1516 | ||
@@ -1612,7 +1612,7 @@ ENTRY(fast_second_level_miss) | |||
1612 | rsr a1, PTEVADDR | 1612 | rsr a1, PTEVADDR |
1613 | srli a1, a1, PAGE_SHIFT | 1613 | srli a1, a1, PAGE_SHIFT |
1614 | slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK | 1614 | slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK |
1615 | addi a1, a1, DTLB_WAY_PGTABLE # ... + way_number | 1615 | addi a1, a1, DTLB_WAY_PGD # ... + way_number |
1616 | 1616 | ||
1617 | wdtlb a0, a1 | 1617 | wdtlb a0, a1 |
1618 | dsync | 1618 | dsync |
@@ -1654,7 +1654,7 @@ ENTRY(fast_second_level_miss) | |||
1654 | mov a1, a2 | 1654 | mov a1, a2 |
1655 | 1655 | ||
1656 | rsr a2, PS | 1656 | rsr a2, PS |
1657 | bbsi.l a2, PS_UM_SHIFT, 1f | 1657 | bbsi.l a2, PS_UM_BIT, 1f |
1658 | j _kernel_exception | 1658 | j _kernel_exception |
1659 | 1: j _user_exception | 1659 | 1: j _user_exception |
1660 | 1660 | ||
@@ -1753,7 +1753,7 @@ ENTRY(fast_store_prohibited) | |||
1753 | mov a1, a2 | 1753 | mov a1, a2 |
1754 | 1754 | ||
1755 | rsr a2, PS | 1755 | rsr a2, PS |
1756 | bbsi.l a2, PS_UM_SHIFT, 1f | 1756 | bbsi.l a2, PS_UM_BIT, 1f |
1757 | j _kernel_exception | 1757 | j _kernel_exception |
1758 | 1: j _user_exception | 1758 | 1: j _user_exception |
1759 | 1759 | ||
@@ -1924,7 +1924,7 @@ ENTRY(_switch_to) | |||
1924 | 1924 | ||
1925 | /* Disable ints while we manipulate the stack pointer; spill regs. */ | 1925 | /* Disable ints while we manipulate the stack pointer; spill regs. */ |
1926 | 1926 | ||
1927 | movi a5, PS_EXCM_MASK | LOCKLEVEL | 1927 | movi a5, (1 << PS_EXCM_BIT) | LOCKLEVEL |
1928 | xsr a5, PS | 1928 | xsr a5, PS |
1929 | rsr a3, EXCSAVE_1 | 1929 | rsr a3, EXCSAVE_1 |
1930 | rsync | 1930 | rsync |
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S index c07cb2522993..ea89910efa44 100644 --- a/arch/xtensa/kernel/head.S +++ b/arch/xtensa/kernel/head.S | |||
@@ -15,9 +15,9 @@ | |||
15 | * Kevin Chea | 15 | * Kevin Chea |
16 | */ | 16 | */ |
17 | 17 | ||
18 | #include <xtensa/cacheasm.h> | ||
19 | #include <asm/processor.h> | 18 | #include <asm/processor.h> |
20 | #include <asm/page.h> | 19 | #include <asm/page.h> |
20 | #include <asm/cacheasm.h> | ||
21 | 21 | ||
22 | /* | 22 | /* |
23 | * This module contains the entry code for kernel images. It performs the | 23 | * This module contains the entry code for kernel images. It performs the |
@@ -32,13 +32,6 @@ | |||
32 | * | 32 | * |
33 | */ | 33 | */ |
34 | 34 | ||
35 | .macro iterate from, to , cmd | ||
36 | .ifeq ((\to - \from) & ~0xfff) | ||
37 | \cmd \from | ||
38 | iterate "(\from+1)", \to, \cmd | ||
39 | .endif | ||
40 | .endm | ||
41 | |||
42 | /* | 35 | /* |
43 | * _start | 36 | * _start |
44 | * | 37 | * |
@@ -64,7 +57,7 @@ _startup: | |||
64 | 57 | ||
65 | /* Disable interrupts and exceptions. */ | 58 | /* Disable interrupts and exceptions. */ |
66 | 59 | ||
67 | movi a0, XCHAL_PS_EXCM_MASK | 60 | movi a0, LOCKLEVEL |
68 | wsr a0, PS | 61 | wsr a0, PS |
69 | 62 | ||
70 | /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ | 63 | /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ |
@@ -91,11 +84,11 @@ _startup: | |||
91 | movi a1, 15 | 84 | movi a1, 15 |
92 | wsr a0, ICOUNTLEVEL | 85 | wsr a0, ICOUNTLEVEL |
93 | 86 | ||
94 | .macro reset_dbreak num | 87 | .set _index, 0 |
95 | wsr a0, DBREAKC + \num | 88 | .rept XCHAL_NUM_DBREAK - 1 |
96 | .endm | 89 | wsr a0, DBREAKC + _index |
97 | 90 | .set _index, _index + 1 | |
98 | iterate 0, XCHAL_NUM_IBREAK-1, reset_dbreak | 91 | .endr |
99 | #endif | 92 | #endif |
100 | 93 | ||
101 | /* Clear CCOUNT (not really necessary, but nice) */ | 94 | /* Clear CCOUNT (not really necessary, but nice) */ |
@@ -110,10 +103,11 @@ _startup: | |||
110 | 103 | ||
111 | /* Disable all timers. */ | 104 | /* Disable all timers. */ |
112 | 105 | ||
113 | .macro reset_timer num | 106 | .set _index, 0 |
114 | wsr a0, CCOMPARE_0 + \num | 107 | .rept XCHAL_NUM_TIMERS - 1 |
115 | .endm | 108 | wsr a0, CCOMPARE + _index |
116 | iterate 0, XCHAL_NUM_TIMERS-1, reset_timer | 109 | .set _index, _index + 1 |
110 | .endr | ||
117 | 111 | ||
118 | /* Interrupt initialization. */ | 112 | /* Interrupt initialization. */ |
119 | 113 | ||
@@ -139,12 +133,21 @@ _startup: | |||
139 | rsync | 133 | rsync |
140 | 134 | ||
141 | /* Initialize the caches. | 135 | /* Initialize the caches. |
142 | * Does not include flushing writeback d-cache. | 136 | * a2, a3 are just working registers (clobbered). |
143 | * a6, a7 are just working registers (clobbered). | ||
144 | */ | 137 | */ |
145 | 138 | ||
146 | icache_reset a2, a3 | 139 | #if XCHAL_DCACHE_LINE_LOCKABLE |
147 | dcache_reset a2, a3 | 140 | ___unlock_dcache_all a2 a3 |
141 | #endif | ||
142 | |||
143 | #if XCHAL_ICACHE_LINE_LOCKABLE | ||
144 | ___unlock_icache_all a2 a3 | ||
145 | #endif | ||
146 | |||
147 | ___invalidate_dcache_all a2 a3 | ||
148 | ___invalidate_icache_all a2 a3 | ||
149 | |||
150 | isync | ||
148 | 151 | ||
149 | /* Unpack data sections | 152 | /* Unpack data sections |
150 | * | 153 | * |
@@ -181,9 +184,9 @@ _startup: | |||
181 | movi a2, _bss_start # start of BSS | 184 | movi a2, _bss_start # start of BSS |
182 | movi a3, _bss_end # end of BSS | 185 | movi a3, _bss_end # end of BSS |
183 | 186 | ||
184 | 1: addi a2, a2, 4 | 187 | __loopt a2, a3, a4, 2 |
185 | s32i a0, a2, 0 | 188 | s32i a0, a2, 0 |
186 | blt a2, a3, 1b | 189 | __endla a2, a4, 4 |
187 | 190 | ||
188 | #if XCHAL_DCACHE_IS_WRITEBACK | 191 | #if XCHAL_DCACHE_IS_WRITEBACK |
189 | 192 | ||
@@ -191,7 +194,7 @@ _startup: | |||
191 | * instructions/data are available. | 194 | * instructions/data are available. |
192 | */ | 195 | */ |
193 | 196 | ||
194 | dcache_writeback_all a2, a3 | 197 | ___flush_dcache_all a2 a3 |
195 | #endif | 198 | #endif |
196 | 199 | ||
197 | /* Setup stack and enable window exceptions (keep irqs disabled) */ | 200 | /* Setup stack and enable window exceptions (keep irqs disabled) */ |
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c index 6648fa9d9192..ca76f071666e 100644 --- a/arch/xtensa/kernel/pci-dma.c +++ b/arch/xtensa/kernel/pci-dma.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * arch/xtensa/kernel/pci-dma.c | 2 | * arch/xtensa/pci-dma.c |
3 | * | 3 | * |
4 | * DMA coherent memory allocation. | 4 | * DMA coherent memory allocation. |
5 | * | 5 | * |
@@ -29,28 +29,48 @@ | |||
29 | */ | 29 | */ |
30 | 30 | ||
31 | void * | 31 | void * |
32 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) | 32 | dma_alloc_coherent(struct device *dev,size_t size,dma_addr_t *handle,gfp_t flag) |
33 | { | 33 | { |
34 | void *ret; | 34 | unsigned long ret; |
35 | unsigned long uncached = 0; | ||
35 | 36 | ||
36 | /* ignore region speicifiers */ | 37 | /* ignore region speicifiers */ |
37 | gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); | ||
38 | 38 | ||
39 | if (dev == NULL || (*dev->dma_mask < 0xffffffff)) | 39 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM); |
40 | gfp |= GFP_DMA; | ||
41 | ret = (void *)__get_free_pages(gfp, get_order(size)); | ||
42 | 40 | ||
43 | if (ret != NULL) { | 41 | if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff)) |
44 | memset(ret, 0, size); | 42 | flag |= GFP_DMA; |
45 | *handle = virt_to_bus(ret); | 43 | ret = (unsigned long)__get_free_pages(flag, get_order(size)); |
44 | |||
45 | if (ret == 0) | ||
46 | return NULL; | ||
47 | |||
48 | /* We currently don't support coherent memory outside KSEG */ | ||
49 | |||
50 | if (ret < XCHAL_KSEG_CACHED_VADDR | ||
51 | || ret >= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE) | ||
52 | BUG(); | ||
53 | |||
54 | |||
55 | if (ret != 0) { | ||
56 | memset((void*) ret, 0, size); | ||
57 | uncached = ret+XCHAL_KSEG_BYPASS_VADDR-XCHAL_KSEG_CACHED_VADDR; | ||
58 | *handle = virt_to_bus((void*)ret); | ||
59 | __flush_invalidate_dcache_range(ret, size); | ||
46 | } | 60 | } |
47 | return (void*) BYPASS_ADDR((unsigned long)ret); | 61 | |
62 | return (void*)uncached; | ||
48 | } | 63 | } |
49 | 64 | ||
50 | void dma_free_coherent(struct device *hwdev, size_t size, | 65 | void dma_free_coherent(struct device *hwdev, size_t size, |
51 | void *vaddr, dma_addr_t dma_handle) | 66 | void *vaddr, dma_addr_t dma_handle) |
52 | { | 67 | { |
53 | free_pages(CACHED_ADDR((unsigned long)vaddr), get_order(size)); | 68 | long addr=(long)vaddr+XCHAL_KSEG_CACHED_VADDR-XCHAL_KSEG_BYPASS_VADDR; |
69 | |||
70 | if (addr < 0 || addr >= XCHAL_KSEG_SIZE) | ||
71 | BUG(); | ||
72 | |||
73 | free_pages(addr, get_order(size)); | ||
54 | } | 74 | } |
55 | 75 | ||
56 | 76 | ||
diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c index a7c4178c2a8c..3785f3481d71 100644 --- a/arch/xtensa/kernel/process.c +++ b/arch/xtensa/kernel/process.c | |||
@@ -1,4 +1,3 @@ | |||
1 | // TODO verify coprocessor handling | ||
2 | /* | 1 | /* |
3 | * arch/xtensa/kernel/process.c | 2 | * arch/xtensa/kernel/process.c |
4 | * | 3 | * |
@@ -43,7 +42,7 @@ | |||
43 | #include <asm/irq.h> | 42 | #include <asm/irq.h> |
44 | #include <asm/atomic.h> | 43 | #include <asm/atomic.h> |
45 | #include <asm/asm-offsets.h> | 44 | #include <asm/asm-offsets.h> |
46 | #include <asm/coprocessor.h> | 45 | #include <asm/regs.h> |
47 | 46 | ||
48 | extern void ret_from_fork(void); | 47 | extern void ret_from_fork(void); |
49 | 48 | ||
@@ -67,25 +66,6 @@ void (*pm_power_off)(void) = NULL; | |||
67 | EXPORT_SYMBOL(pm_power_off); | 66 | EXPORT_SYMBOL(pm_power_off); |
68 | 67 | ||
69 | 68 | ||
70 | #if XCHAL_CP_NUM > 0 | ||
71 | |||
72 | /* | ||
73 | * Coprocessor ownership. | ||
74 | */ | ||
75 | |||
76 | coprocessor_info_t coprocessor_info[] = { | ||
77 | { 0, XTENSA_CPE_CP0_OFFSET }, | ||
78 | { 0, XTENSA_CPE_CP1_OFFSET }, | ||
79 | { 0, XTENSA_CPE_CP2_OFFSET }, | ||
80 | { 0, XTENSA_CPE_CP3_OFFSET }, | ||
81 | { 0, XTENSA_CPE_CP4_OFFSET }, | ||
82 | { 0, XTENSA_CPE_CP5_OFFSET }, | ||
83 | { 0, XTENSA_CPE_CP6_OFFSET }, | ||
84 | { 0, XTENSA_CPE_CP7_OFFSET }, | ||
85 | }; | ||
86 | |||
87 | #endif | ||
88 | |||
89 | /* | 69 | /* |
90 | * Powermanagement idle function, if any is provided by the platform. | 70 | * Powermanagement idle function, if any is provided by the platform. |
91 | */ | 71 | */ |
@@ -110,12 +90,10 @@ void cpu_idle(void) | |||
110 | 90 | ||
111 | void exit_thread(void) | 91 | void exit_thread(void) |
112 | { | 92 | { |
113 | release_coprocessors(current); /* Empty macro if no CPs are defined */ | ||
114 | } | 93 | } |
115 | 94 | ||
116 | void flush_thread(void) | 95 | void flush_thread(void) |
117 | { | 96 | { |
118 | release_coprocessors(current); /* Empty macro if no CPs are defined */ | ||
119 | } | 97 | } |
120 | 98 | ||
121 | /* | 99 | /* |
@@ -275,7 +253,7 @@ void do_copy_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs, | |||
275 | */ | 253 | */ |
276 | 254 | ||
277 | elfregs->pc = regs->pc; | 255 | elfregs->pc = regs->pc; |
278 | elfregs->ps = (regs->ps & ~XCHAL_PS_EXCM_MASK); | 256 | elfregs->ps = (regs->ps & ~(1 << PS_EXCM_BIT)); |
279 | elfregs->exccause = regs->exccause; | 257 | elfregs->exccause = regs->exccause; |
280 | elfregs->excvaddr = regs->excvaddr; | 258 | elfregs->excvaddr = regs->excvaddr; |
281 | elfregs->windowbase = regs->windowbase; | 259 | elfregs->windowbase = regs->windowbase; |
@@ -325,7 +303,7 @@ void do_restore_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs, | |||
325 | */ | 303 | */ |
326 | 304 | ||
327 | regs->pc = elfregs->pc; | 305 | regs->pc = elfregs->pc; |
328 | regs->ps = (elfregs->ps | XCHAL_PS_EXCM_MASK); | 306 | regs->ps = (elfregs->ps | (1 << PS_EXCM_BIT)); |
329 | regs->exccause = elfregs->exccause; | 307 | regs->exccause = elfregs->exccause; |
330 | regs->excvaddr = elfregs->excvaddr; | 308 | regs->excvaddr = elfregs->excvaddr; |
331 | regs->windowbase = elfregs->windowbase; | 309 | regs->windowbase = elfregs->windowbase; |
@@ -459,16 +437,7 @@ int do_restore_fpregs (elf_fpregset_t *fpregs, struct pt_regs *regs, | |||
459 | int | 437 | int |
460 | dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r) | 438 | dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r) |
461 | { | 439 | { |
462 | /* see asm/coprocessor.h for this magic number 16 */ | ||
463 | #if XTENSA_CP_EXTRA_SIZE > 16 | ||
464 | do_save_fpregs (r, regs, task); | ||
465 | |||
466 | /* For now, bit 16 means some extra state may be present: */ | ||
467 | // FIXME!! need to track to return more accurate mask | ||
468 | return 0x10000 | XCHAL_CP_MASK; | ||
469 | #else | ||
470 | return 0; /* no coprocessors active on this processor */ | 440 | return 0; /* no coprocessors active on this processor */ |
471 | #endif | ||
472 | } | 441 | } |
473 | 442 | ||
474 | /* | 443 | /* |
diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c index 9aea23cc0dc5..604c3c3c6759 100644 --- a/arch/xtensa/kernel/ptrace.c +++ b/arch/xtensa/kernel/ptrace.c | |||
@@ -96,7 +96,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
96 | /* Note: PS.EXCM is not set while user task is running; | 96 | /* Note: PS.EXCM is not set while user task is running; |
97 | * its being set in regs is for exception handling | 97 | * its being set in regs is for exception handling |
98 | * convenience. */ | 98 | * convenience. */ |
99 | tmp = (regs->ps & ~XCHAL_PS_EXCM_MASK); | 99 | tmp = (regs->ps & ~(1 << PS_EXCM_BIT)); |
100 | break; | 100 | break; |
101 | case REG_WB: | 101 | case REG_WB: |
102 | tmp = regs->windowbase; | 102 | tmp = regs->windowbase; |
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index c99ab72b41b6..b6374c09de20 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c | |||
@@ -42,8 +42,6 @@ | |||
42 | #include <asm/page.h> | 42 | #include <asm/page.h> |
43 | #include <asm/setup.h> | 43 | #include <asm/setup.h> |
44 | 44 | ||
45 | #include <xtensa/config/system.h> | ||
46 | |||
47 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) | 45 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) |
48 | struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; | 46 | struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; |
49 | #endif | 47 | #endif |
@@ -336,7 +334,7 @@ c_show(struct seq_file *f, void *slot) | |||
336 | /* high-level stuff */ | 334 | /* high-level stuff */ |
337 | seq_printf(f,"processor\t: 0\n" | 335 | seq_printf(f,"processor\t: 0\n" |
338 | "vendor_id\t: Tensilica\n" | 336 | "vendor_id\t: Tensilica\n" |
339 | "model\t\t: Xtensa " XCHAL_HW_RELEASE_NAME "\n" | 337 | "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n" |
340 | "core ID\t\t: " XCHAL_CORE_ID "\n" | 338 | "core ID\t\t: " XCHAL_CORE_ID "\n" |
341 | "build ID\t: 0x%x\n" | 339 | "build ID\t: 0x%x\n" |
342 | "byte order\t: %s\n" | 340 | "byte order\t: %s\n" |
@@ -420,25 +418,6 @@ c_show(struct seq_file *f, void *slot) | |||
420 | XCHAL_NUM_TIMERS, | 418 | XCHAL_NUM_TIMERS, |
421 | XCHAL_DEBUGLEVEL); | 419 | XCHAL_DEBUGLEVEL); |
422 | 420 | ||
423 | /* Coprocessors */ | ||
424 | #if XCHAL_HAVE_CP | ||
425 | seq_printf(f, "coprocessors\t: %d\n", XCHAL_CP_NUM); | ||
426 | #else | ||
427 | seq_printf(f, "coprocessors\t: none\n"); | ||
428 | #endif | ||
429 | |||
430 | /* {I,D}{RAM,ROM} and XLMI */ | ||
431 | seq_printf(f,"inst ROMs\t: %d\n" | ||
432 | "inst RAMs\t: %d\n" | ||
433 | "data ROMs\t: %d\n" | ||
434 | "data RAMs\t: %d\n" | ||
435 | "XLMI ports\t: %d\n", | ||
436 | XCHAL_NUM_IROM, | ||
437 | XCHAL_NUM_IRAM, | ||
438 | XCHAL_NUM_DROM, | ||
439 | XCHAL_NUM_DRAM, | ||
440 | XCHAL_NUM_XLMI); | ||
441 | |||
442 | /* Cache */ | 421 | /* Cache */ |
443 | seq_printf(f,"icache line size: %d\n" | 422 | seq_printf(f,"icache line size: %d\n" |
444 | "icache ways\t: %d\n" | 423 | "icache ways\t: %d\n" |
@@ -466,24 +445,6 @@ c_show(struct seq_file *f, void *slot) | |||
466 | XCHAL_DCACHE_WAYS, | 445 | XCHAL_DCACHE_WAYS, |
467 | XCHAL_DCACHE_SIZE); | 446 | XCHAL_DCACHE_SIZE); |
468 | 447 | ||
469 | /* MMU */ | ||
470 | seq_printf(f,"ASID bits\t: %d\n" | ||
471 | "ASID invalid\t: %d\n" | ||
472 | "ASID kernel\t: %d\n" | ||
473 | "rings\t\t: %d\n" | ||
474 | "itlb ways\t: %d\n" | ||
475 | "itlb AR ways\t: %d\n" | ||
476 | "dtlb ways\t: %d\n" | ||
477 | "dtlb AR ways\t: %d\n", | ||
478 | XCHAL_MMU_ASID_BITS, | ||
479 | XCHAL_MMU_ASID_INVALID, | ||
480 | XCHAL_MMU_ASID_KERNEL, | ||
481 | XCHAL_MMU_RINGS, | ||
482 | XCHAL_ITLB_WAYS, | ||
483 | XCHAL_ITLB_ARF_WAYS, | ||
484 | XCHAL_DTLB_WAYS, | ||
485 | XCHAL_DTLB_ARF_WAYS); | ||
486 | |||
487 | return 0; | 448 | return 0; |
488 | } | 449 | } |
489 | 450 | ||
diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c index c494f0826fc5..6af7f4145990 100644 --- a/arch/xtensa/kernel/signal.c +++ b/arch/xtensa/kernel/signal.c | |||
@@ -12,8 +12,8 @@ | |||
12 | * | 12 | * |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <xtensa/config/core.h> | 15 | #include <asm/variant/core.h> |
16 | #include <xtensa/hal.h> | 16 | #include <asm/coprocessor.h> |
17 | #include <linux/sched.h> | 17 | #include <linux/sched.h> |
18 | #include <linux/mm.h> | 18 | #include <linux/mm.h> |
19 | #include <linux/smp.h> | 19 | #include <linux/smp.h> |
@@ -216,8 +216,8 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) | |||
216 | * handler, or the user mode value doesn't matter (e.g. PS.OWB). | 216 | * handler, or the user mode value doesn't matter (e.g. PS.OWB). |
217 | */ | 217 | */ |
218 | err |= __get_user(ps, &sc->sc_ps); | 218 | err |= __get_user(ps, &sc->sc_ps); |
219 | regs->ps = (regs->ps & ~XCHAL_PS_CALLINC_MASK) | 219 | regs->ps = (regs->ps & ~PS_CALLINC_MASK) |
220 | | (ps & XCHAL_PS_CALLINC_MASK); | 220 | | (ps & PS_CALLINC_MASK); |
221 | 221 | ||
222 | /* Additional corruption checks */ | 222 | /* Additional corruption checks */ |
223 | 223 | ||
@@ -280,7 +280,7 @@ flush_my_cpstate(struct task_struct *tsk) | |||
280 | static int | 280 | static int |
281 | save_cpextra (struct _cpstate *buf) | 281 | save_cpextra (struct _cpstate *buf) |
282 | { | 282 | { |
283 | #if (XCHAL_EXTRA_SA_SIZE == 0) && (XCHAL_CP_NUM == 0) | 283 | #if XCHAL_CP_NUM == 0 |
284 | return 0; | 284 | return 0; |
285 | #else | 285 | #else |
286 | 286 | ||
@@ -497,8 +497,10 @@ gen_return_code(unsigned char *codemem, unsigned int use_rt_sigreturn) | |||
497 | 497 | ||
498 | /* Flush generated code out of the data cache */ | 498 | /* Flush generated code out of the data cache */ |
499 | 499 | ||
500 | if (err == 0) | 500 | if (err == 0) { |
501 | __flush_invalidate_cache_range((unsigned long)codemem, 6UL); | 501 | __invalidate_icache_range((unsigned long)codemem, 6UL); |
502 | __flush_invalidate_dcache_range((unsigned long)codemem, 6UL); | ||
503 | } | ||
502 | 504 | ||
503 | return err; | 505 | return err; |
504 | } | 506 | } |
diff --git a/arch/xtensa/kernel/syscalls.c b/arch/xtensa/kernel/syscalls.c index f49cb239e603..f9a5a752ca69 100644 --- a/arch/xtensa/kernel/syscalls.c +++ b/arch/xtensa/kernel/syscalls.c | |||
@@ -175,8 +175,8 @@ void system_call (struct pt_regs *regs) | |||
175 | * interrupts in the first place: | 175 | * interrupts in the first place: |
176 | */ | 176 | */ |
177 | local_save_flags (ps); | 177 | local_save_flags (ps); |
178 | local_irq_restore((ps & ~XCHAL_PS_INTLEVEL_MASK) | | 178 | local_irq_restore((ps & ~PS_INTLEVEL_MASK) | |
179 | (regs->ps & XCHAL_PS_INTLEVEL_MASK) ); | 179 | (regs->ps & PS_INTLEVEL_MASK) ); |
180 | 180 | ||
181 | if (syscallnr > __NR_Linux_syscalls) { | 181 | if (syscallnr > __NR_Linux_syscalls) { |
182 | regs->areg[2] = -ENOSYS; | 182 | regs->areg[2] = -ENOSYS; |
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index ce077d6bf3a0..693ab268485e 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c | |||
@@ -75,7 +75,7 @@ extern void system_call (struct pt_regs*); | |||
75 | #define USER 0x02 | 75 | #define USER 0x02 |
76 | 76 | ||
77 | #define COPROCESSOR(x) \ | 77 | #define COPROCESSOR(x) \ |
78 | { XCHAL_EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor } | 78 | { EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor } |
79 | 79 | ||
80 | typedef struct { | 80 | typedef struct { |
81 | int cause; | 81 | int cause; |
@@ -85,38 +85,38 @@ typedef struct { | |||
85 | 85 | ||
86 | dispatch_init_table_t __init dispatch_init_table[] = { | 86 | dispatch_init_table_t __init dispatch_init_table[] = { |
87 | 87 | ||
88 | { XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction}, | 88 | { EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction}, |
89 | { XCHAL_EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel }, | 89 | { EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel }, |
90 | { XCHAL_EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user }, | 90 | { EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user }, |
91 | { XCHAL_EXCCAUSE_SYSTEM_CALL, 0, system_call }, | 91 | { EXCCAUSE_SYSTEM_CALL, 0, system_call }, |
92 | /* XCHAL_EXCCAUSE_INSTRUCTION_FETCH unhandled */ | 92 | /* EXCCAUSE_INSTRUCTION_FETCH unhandled */ |
93 | /* XCHAL_EXCCAUSE_LOAD_STORE_ERROR unhandled*/ | 93 | /* EXCCAUSE_LOAD_STORE_ERROR unhandled*/ |
94 | { XCHAL_EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt }, | 94 | { EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt }, |
95 | { XCHAL_EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca }, | 95 | { EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca }, |
96 | /* XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */ | 96 | /* EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */ |
97 | /* XCHAL_EXCCAUSE_PRIVILEGED unhandled */ | 97 | /* EXCCAUSE_PRIVILEGED unhandled */ |
98 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION | 98 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION |
99 | #ifdef CONFIG_UNALIGNED_USER | 99 | #ifdef CONFIG_UNALIGNED_USER |
100 | { XCHAL_EXCCAUSE_UNALIGNED, USER, fast_unaligned }, | 100 | { EXCCAUSE_UNALIGNED, USER, fast_unaligned }, |
101 | #else | 101 | #else |
102 | { XCHAL_EXCCAUSE_UNALIGNED, 0, do_unaligned_user }, | 102 | { EXCCAUSE_UNALIGNED, 0, do_unaligned_user }, |
103 | #endif | 103 | #endif |
104 | { XCHAL_EXCCAUSE_UNALIGNED, KRNL, fast_unaligned }, | 104 | { EXCCAUSE_UNALIGNED, KRNL, fast_unaligned }, |
105 | #endif | 105 | #endif |
106 | { XCHAL_EXCCAUSE_ITLB_MISS, 0, do_page_fault }, | 106 | { EXCCAUSE_ITLB_MISS, 0, do_page_fault }, |
107 | { XCHAL_EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss}, | 107 | { EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss}, |
108 | { XCHAL_EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit }, | 108 | { EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit }, |
109 | { XCHAL_EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault }, | 109 | { EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault }, |
110 | /* XCHAL_EXCCAUSE_SIZE_RESTRICTION unhandled */ | 110 | /* EXCCAUSE_SIZE_RESTRICTION unhandled */ |
111 | { XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault }, | 111 | { EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault }, |
112 | { XCHAL_EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss}, | 112 | { EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss}, |
113 | { XCHAL_EXCCAUSE_DTLB_MISS, 0, do_page_fault }, | 113 | { EXCCAUSE_DTLB_MISS, 0, do_page_fault }, |
114 | { XCHAL_EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit }, | 114 | { EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit }, |
115 | { XCHAL_EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault }, | 115 | { EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault }, |
116 | /* XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */ | 116 | /* EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */ |
117 | { XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited }, | 117 | { EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited }, |
118 | { XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, | 118 | { EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, |
119 | { XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, | 119 | { EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, |
120 | /* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */ | 120 | /* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */ |
121 | #if (XCHAL_CP_MASK & 1) | 121 | #if (XCHAL_CP_MASK & 1) |
122 | COPROCESSOR(0), | 122 | COPROCESSOR(0), |
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S index 0e74397bfa2b..eb2d7bb69ee0 100644 --- a/arch/xtensa/kernel/vectors.S +++ b/arch/xtensa/kernel/vectors.S | |||
@@ -53,6 +53,8 @@ | |||
53 | #include <asm/thread_info.h> | 53 | #include <asm/thread_info.h> |
54 | #include <asm/processor.h> | 54 | #include <asm/processor.h> |
55 | 55 | ||
56 | #define WINDOW_VECTORS_SIZE 0x180 | ||
57 | |||
56 | 58 | ||
57 | /* | 59 | /* |
58 | * User exception vector. (Exceptions with PS.UM == 1, PS.EXCM == 0) | 60 | * User exception vector. (Exceptions with PS.UM == 1, PS.EXCM == 0) |
@@ -210,7 +212,7 @@ ENTRY(_DoubleExceptionVector) | |||
210 | /* Check for kernel double exception (usually fatal). */ | 212 | /* Check for kernel double exception (usually fatal). */ |
211 | 213 | ||
212 | rsr a3, PS | 214 | rsr a3, PS |
213 | _bbci.l a3, PS_UM_SHIFT, .Lksp | 215 | _bbci.l a3, PS_UM_BIT, .Lksp |
214 | 216 | ||
215 | /* Check if we are currently handling a window exception. */ | 217 | /* Check if we are currently handling a window exception. */ |
216 | /* Note: We don't need to indicate that we enter a critical section. */ | 218 | /* Note: We don't need to indicate that we enter a critical section. */ |
@@ -219,7 +221,7 @@ ENTRY(_DoubleExceptionVector) | |||
219 | 221 | ||
220 | movi a3, XCHAL_WINDOW_VECTORS_VADDR | 222 | movi a3, XCHAL_WINDOW_VECTORS_VADDR |
221 | _bltu a0, a3, .Lfixup | 223 | _bltu a0, a3, .Lfixup |
222 | addi a3, a3, XSHAL_WINDOW_VECTORS_SIZE | 224 | addi a3, a3, WINDOW_VECTORS_SIZE |
223 | _bgeu a0, a3, .Lfixup | 225 | _bgeu a0, a3, .Lfixup |
224 | 226 | ||
225 | /* Window overflow/underflow exception. Get stack pointer. */ | 227 | /* Window overflow/underflow exception. Get stack pointer. */ |
@@ -245,7 +247,7 @@ ENTRY(_DoubleExceptionVector) | |||
245 | 247 | ||
246 | wsr a2, DEPC # save stack pointer temporarily | 248 | wsr a2, DEPC # save stack pointer temporarily |
247 | rsr a0, PS | 249 | rsr a0, PS |
248 | extui a0, a0, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS | 250 | extui a0, a0, PS_OWB_SHIFT, 4 |
249 | wsr a0, WINDOWBASE | 251 | wsr a0, WINDOWBASE |
250 | rsync | 252 | rsync |
251 | 253 | ||
@@ -312,8 +314,8 @@ ENTRY(_DoubleExceptionVector) | |||
312 | .Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */ | 314 | .Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */ |
313 | 315 | ||
314 | rsr a3, EXCCAUSE | 316 | rsr a3, EXCCAUSE |
315 | beqi a3, XCHAL_EXCCAUSE_ITLB_MISS, 1f | 317 | beqi a3, EXCCAUSE_ITLB_MISS, 1f |
316 | addi a3, a3, -XCHAL_EXCCAUSE_DTLB_MISS | 318 | addi a3, a3, -EXCCAUSE_DTLB_MISS |
317 | bnez a3, .Lunrecoverable | 319 | bnez a3, .Lunrecoverable |
318 | 1: movi a3, fast_second_level_miss_double_kernel | 320 | 1: movi a3, fast_second_level_miss_double_kernel |
319 | jx a3 | 321 | jx a3 |
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S index e01131fec69e..a36c104c3a52 100644 --- a/arch/xtensa/kernel/vmlinux.lds.S +++ b/arch/xtensa/kernel/vmlinux.lds.S | |||
@@ -16,20 +16,17 @@ | |||
16 | 16 | ||
17 | #include <asm-generic/vmlinux.lds.h> | 17 | #include <asm-generic/vmlinux.lds.h> |
18 | 18 | ||
19 | #define _NOCLANGUAGE | 19 | #include <asm/variant/core.h> |
20 | #undef __ASSEMBLER__ | ||
21 | #include <xtensa/config/core.h> | ||
22 | #include <xtensa/config/system.h> | ||
23 | OUTPUT_ARCH(xtensa) | 20 | OUTPUT_ARCH(xtensa) |
24 | ENTRY(_start) | 21 | ENTRY(_start) |
25 | 22 | ||
26 | #if XCHAL_MEMORY_ORDER == XTHAL_BIGENDIAN | 23 | #ifdef __XTENSA_EB__ |
27 | jiffies = jiffies_64 + 4; | 24 | jiffies = jiffies_64 + 4; |
28 | #else | 25 | #else |
29 | jiffies = jiffies_64; | 26 | jiffies = jiffies_64; |
30 | #endif | 27 | #endif |
31 | 28 | ||
32 | #define KERNELOFFSET 0x1000 | 29 | #define KERNELOFFSET 0xd0001000 |
33 | 30 | ||
34 | /* Note: In the following macros, it would be nice to specify only the | 31 | /* Note: In the following macros, it would be nice to specify only the |
35 | vector name and section kind and construct "sym" and "section" using | 32 | vector name and section kind and construct "sym" and "section" using |
@@ -76,7 +73,7 @@ jiffies = jiffies_64; | |||
76 | 73 | ||
77 | SECTIONS | 74 | SECTIONS |
78 | { | 75 | { |
79 | . = XCHAL_KSEG_CACHED_VADDR + KERNELOFFSET; | 76 | . = KERNELOFFSET; |
80 | /* .text section */ | 77 | /* .text section */ |
81 | 78 | ||
82 | _text = .; | 79 | _text = .; |
@@ -160,7 +157,7 @@ SECTIONS | |||
160 | 157 | ||
161 | /* Initialization code and data: */ | 158 | /* Initialization code and data: */ |
162 | 159 | ||
163 | . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE); | 160 | . = ALIGN(1 << 12); |
164 | __init_begin = .; | 161 | __init_begin = .; |
165 | .init.text : { | 162 | .init.text : { |
166 | _sinittext = .; | 163 | _sinittext = .; |
@@ -224,32 +221,32 @@ SECTIONS | |||
224 | .dummy) | 221 | .dummy) |
225 | SECTION_VECTOR (_DebugInterruptVector_literal, | 222 | SECTION_VECTOR (_DebugInterruptVector_literal, |
226 | .DebugInterruptVector.literal, | 223 | .DebugInterruptVector.literal, |
227 | XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) - 4, | 224 | XCHAL_DEBUG_VECTOR_VADDR - 4, |
228 | SIZEOF(.WindowVectors.text), | 225 | SIZEOF(.WindowVectors.text), |
229 | .WindowVectors.text) | 226 | .WindowVectors.text) |
230 | SECTION_VECTOR (_DebugInterruptVector_text, | 227 | SECTION_VECTOR (_DebugInterruptVector_text, |
231 | .DebugInterruptVector.text, | 228 | .DebugInterruptVector.text, |
232 | XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL), | 229 | XCHAL_DEBUG_VECTOR_VADDR, |
233 | 4, | 230 | 4, |
234 | .DebugInterruptVector.literal) | 231 | .DebugInterruptVector.literal) |
235 | SECTION_VECTOR (_KernelExceptionVector_literal, | 232 | SECTION_VECTOR (_KernelExceptionVector_literal, |
236 | .KernelExceptionVector.literal, | 233 | .KernelExceptionVector.literal, |
237 | XCHAL_KERNELEXC_VECTOR_VADDR - 4, | 234 | XCHAL_KERNEL_VECTOR_VADDR - 4, |
238 | SIZEOF(.DebugInterruptVector.text), | 235 | SIZEOF(.DebugInterruptVector.text), |
239 | .DebugInterruptVector.text) | 236 | .DebugInterruptVector.text) |
240 | SECTION_VECTOR (_KernelExceptionVector_text, | 237 | SECTION_VECTOR (_KernelExceptionVector_text, |
241 | .KernelExceptionVector.text, | 238 | .KernelExceptionVector.text, |
242 | XCHAL_KERNELEXC_VECTOR_VADDR, | 239 | XCHAL_KERNEL_VECTOR_VADDR, |
243 | 4, | 240 | 4, |
244 | .KernelExceptionVector.literal) | 241 | .KernelExceptionVector.literal) |
245 | SECTION_VECTOR (_UserExceptionVector_literal, | 242 | SECTION_VECTOR (_UserExceptionVector_literal, |
246 | .UserExceptionVector.literal, | 243 | .UserExceptionVector.literal, |
247 | XCHAL_USEREXC_VECTOR_VADDR - 4, | 244 | XCHAL_USER_VECTOR_VADDR - 4, |
248 | SIZEOF(.KernelExceptionVector.text), | 245 | SIZEOF(.KernelExceptionVector.text), |
249 | .KernelExceptionVector.text) | 246 | .KernelExceptionVector.text) |
250 | SECTION_VECTOR (_UserExceptionVector_text, | 247 | SECTION_VECTOR (_UserExceptionVector_text, |
251 | .UserExceptionVector.text, | 248 | .UserExceptionVector.text, |
252 | XCHAL_USEREXC_VECTOR_VADDR, | 249 | XCHAL_USER_VECTOR_VADDR, |
253 | 4, | 250 | 4, |
254 | .UserExceptionVector.literal) | 251 | .UserExceptionVector.literal) |
255 | SECTION_VECTOR (_DoubleExceptionVector_literal, | 252 | SECTION_VECTOR (_DoubleExceptionVector_literal, |
@@ -264,7 +261,7 @@ SECTIONS | |||
264 | .DoubleExceptionVector.literal) | 261 | .DoubleExceptionVector.literal) |
265 | 262 | ||
266 | . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3; | 263 | . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3; |
267 | . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE); | 264 | . = ALIGN(1 << 12); |
268 | 265 | ||
269 | __init_end = .; | 266 | __init_end = .; |
270 | 267 | ||