diff options
Diffstat (limited to 'arch/xtensa/kernel/traps.c')
-rw-r--r-- | arch/xtensa/kernel/traps.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index bc1e14cf9369..5caf2b64d43a 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c | |||
@@ -97,7 +97,7 @@ static dispatch_init_table_t __initdata dispatch_init_table[] = { | |||
97 | /* EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */ | 97 | /* EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */ |
98 | /* EXCCAUSE_PRIVILEGED unhandled */ | 98 | /* EXCCAUSE_PRIVILEGED unhandled */ |
99 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION | 99 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION |
100 | #ifdef CONFIG_UNALIGNED_USER | 100 | #ifdef CONFIG_XTENSA_UNALIGNED_USER |
101 | { EXCCAUSE_UNALIGNED, USER, fast_unaligned }, | 101 | { EXCCAUSE_UNALIGNED, USER, fast_unaligned }, |
102 | #else | 102 | #else |
103 | { EXCCAUSE_UNALIGNED, 0, do_unaligned_user }, | 103 | { EXCCAUSE_UNALIGNED, 0, do_unaligned_user }, |
@@ -202,8 +202,8 @@ extern void do_IRQ(int, struct pt_regs *); | |||
202 | 202 | ||
203 | void do_interrupt (struct pt_regs *regs) | 203 | void do_interrupt (struct pt_regs *regs) |
204 | { | 204 | { |
205 | unsigned long intread = get_sr (INTREAD); | 205 | unsigned long intread = get_sr (interrupt); |
206 | unsigned long intenable = get_sr (INTENABLE); | 206 | unsigned long intenable = get_sr (intenable); |
207 | int i, mask; | 207 | int i, mask; |
208 | 208 | ||
209 | /* Handle all interrupts (no priorities). | 209 | /* Handle all interrupts (no priorities). |
@@ -213,7 +213,7 @@ void do_interrupt (struct pt_regs *regs) | |||
213 | 213 | ||
214 | for (i=0, mask = 1; i < XCHAL_NUM_INTERRUPTS; i++, mask <<= 1) { | 214 | for (i=0, mask = 1; i < XCHAL_NUM_INTERRUPTS; i++, mask <<= 1) { |
215 | if (mask & (intread & intenable)) { | 215 | if (mask & (intread & intenable)) { |
216 | set_sr (mask, INTCLEAR); | 216 | set_sr (mask, intclear); |
217 | do_IRQ (i,regs); | 217 | do_IRQ (i,regs); |
218 | } | 218 | } |
219 | } | 219 | } |
@@ -244,7 +244,7 @@ do_illegal_instruction(struct pt_regs *regs) | |||
244 | */ | 244 | */ |
245 | 245 | ||
246 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION | 246 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION |
247 | #ifndef CONFIG_UNALIGNED_USER | 247 | #ifndef CONFIG_XTENSA_UNALIGNED_USER |
248 | void | 248 | void |
249 | do_unaligned_user (struct pt_regs *regs) | 249 | do_unaligned_user (struct pt_regs *regs) |
250 | { | 250 | { |
@@ -339,7 +339,7 @@ void __init trap_init(void) | |||
339 | /* Initialize EXCSAVE_1 to hold the address of the exception table. */ | 339 | /* Initialize EXCSAVE_1 to hold the address of the exception table. */ |
340 | 340 | ||
341 | i = (unsigned long)exc_table; | 341 | i = (unsigned long)exc_table; |
342 | __asm__ __volatile__("wsr %0, "__stringify(EXCSAVE_1)"\n" : : "a" (i)); | 342 | __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (i)); |
343 | } | 343 | } |
344 | 344 | ||
345 | /* | 345 | /* |
@@ -386,16 +386,16 @@ static inline void spill_registers(void) | |||
386 | unsigned int a0, ps; | 386 | unsigned int a0, ps; |
387 | 387 | ||
388 | __asm__ __volatile__ ( | 388 | __asm__ __volatile__ ( |
389 | "movi a14," __stringify (PS_EXCM_BIT) " | 1\n\t" | 389 | "movi a14, " __stringify(PS_EXCM_BIT | 1) "\n\t" |
390 | "mov a12, a0\n\t" | 390 | "mov a12, a0\n\t" |
391 | "rsr a13," __stringify(SAR) "\n\t" | 391 | "rsr a13, sar\n\t" |
392 | "xsr a14," __stringify(PS) "\n\t" | 392 | "xsr a14, ps\n\t" |
393 | "movi a0, _spill_registers\n\t" | 393 | "movi a0, _spill_registers\n\t" |
394 | "rsync\n\t" | 394 | "rsync\n\t" |
395 | "callx0 a0\n\t" | 395 | "callx0 a0\n\t" |
396 | "mov a0, a12\n\t" | 396 | "mov a0, a12\n\t" |
397 | "wsr a13," __stringify(SAR) "\n\t" | 397 | "wsr a13, sar\n\t" |
398 | "wsr a14," __stringify(PS) "\n\t" | 398 | "wsr a14, ps\n\t" |
399 | :: "a" (&a0), "a" (&ps) | 399 | :: "a" (&a0), "a" (&ps) |
400 | : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory"); | 400 | : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory"); |
401 | } | 401 | } |