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-rw-r--r--arch/xtensa/kernel/coprocessor.S443
1 files changed, 289 insertions, 154 deletions
diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S
index 01bcb9fcfcbd..2bc1e145c0a4 100644
--- a/arch/xtensa/kernel/coprocessor.S
+++ b/arch/xtensa/kernel/coprocessor.S
@@ -8,193 +8,328 @@
8 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details. 9 * for more details.
10 * 10 *
11 * Copyright (C) 2003 - 2005 Tensilica Inc. 11 * Copyright (C) 2003 - 2007 Tensilica Inc.
12 *
13 * Marc Gauthier <marc@tensilica.com> <marc@alumni.uwaterloo.ca>
14 */ 12 */
15 13
16/*
17 * This module contains a table that describes the layout of the various
18 * custom registers and states associated with each coprocessor, as well
19 * as those not associated with any coprocessor ("extra state").
20 * This table is included with core dumps and is available via the ptrace
21 * interface, allowing the layout of such register/state information to
22 * be modified in the kernel without affecting the debugger. Each
23 * register or state is identified using a 32-bit "libdb target number"
24 * assigned when the Xtensa processor is generated.
25 */
26 14
27#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <asm/asm-offsets.h>
28#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/coprocessor.h>
19#include <asm/thread_info.h>
20#include <asm/uaccess.h>
21#include <asm/unistd.h>
22#include <asm/ptrace.h>
23#include <asm/current.h>
24#include <asm/pgtable.h>
25#include <asm/page.h>
26#include <asm/signal.h>
27#include <asm/tlbflush.h>
29 28
30#if XCHAL_HAVE_CP 29/*
30 * Entry condition:
31 *
32 * a0: trashed, original value saved on stack (PT_AREG0)
33 * a1: a1
34 * a2: new stack pointer, original in DEPC
35 * a3: dispatch table
36 * depc: a2, original value saved on stack (PT_DEPC)
37 * excsave_1: a3
38 *
39 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
40 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
41 */
31 42
32#define CP_LAST ((XCHAL_CP_MAX - 1) * COPROCESSOR_INFO_SIZE) 43/* IO protection is currently unsupported. */
33 44
34ENTRY(release_coprocessors) 45ENTRY(fast_io_protect)
46 wsr a0, EXCSAVE_1
47 movi a0, unrecoverable_exception
48 callx0 a0
35 49
36 entry a1, 16 50#if XTENSA_HAVE_COPROCESSORS
37 # a2: task
38 movi a3, 1 << XCHAL_CP_MAX # a3: coprocessor-bit
39 movi a4, coprocessor_info+CP_LAST # a4: owner-table
40 # a5: tmp
41 movi a6, 0 # a6: 0
42 rsil a7, LOCKLEVEL # a7: PS
43 51
441: /* Check if task is coprocessor owner of coprocessor[i]. */ 52/*
53 * Macros for lazy context switch.
54 */
45 55
46 l32i a5, a4, COPROCESSOR_INFO_OWNER 56#define SAVE_CP_REGS(x) \
47 srli a3, a3, 1 57 .align 4; \
48 beqz a3, 1f 58 .Lsave_cp_regs_cp##x: \
49 addi a4, a4, -8 59 .if XTENSA_HAVE_COPROCESSOR(x); \
50 beq a2, a5, 1b 60 xchal_cp##x##_store a2 a4 a5 a6 a7; \
61 .endif; \
62 jx a0
51 63
52 /* Found an entry: Clear entry CPENABLE bit to disable CP. */ 64#define SAVE_CP_REGS_TAB(x) \
65 .if XTENSA_HAVE_COPROCESSOR(x); \
66 .long .Lsave_cp_regs_cp##x - .Lsave_cp_regs_jump_table; \
67 .else; \
68 .long 0; \
69 .endif; \
70 .long THREAD_XTREGS_CP##x
53 71
54 rsr a5, CPENABLE
55 s32i a6, a4, COPROCESSOR_INFO_OWNER
56 xor a5, a3, a5
57 wsr a5, CPENABLE
58 72
59 bnez a3, 1b 73#define LOAD_CP_REGS(x) \
74 .align 4; \
75 .Lload_cp_regs_cp##x: \
76 .if XTENSA_HAVE_COPROCESSOR(x); \
77 xchal_cp##x##_load a2 a4 a5 a6 a7; \
78 .endif; \
79 jx a0
60 80
611: wsr a7, PS 81#define LOAD_CP_REGS_TAB(x) \
62 rsync 82 .if XTENSA_HAVE_COPROCESSOR(x); \
63 retw 83 .long .Lload_cp_regs_cp##x - .Lload_cp_regs_jump_table; \
84 .else; \
85 .long 0; \
86 .endif; \
87 .long THREAD_XTREGS_CP##x
64 88
89 SAVE_CP_REGS(0)
90 SAVE_CP_REGS(1)
91 SAVE_CP_REGS(2)
92 SAVE_CP_REGS(3)
93 SAVE_CP_REGS(4)
94 SAVE_CP_REGS(5)
95 SAVE_CP_REGS(6)
96 SAVE_CP_REGS(7)
65 97
66ENTRY(disable_coprocessor) 98 LOAD_CP_REGS(0)
67 entry sp, 16 99 LOAD_CP_REGS(1)
68 rsil a7, LOCKLEVEL 100 LOAD_CP_REGS(2)
69 rsr a3, CPENABLE 101 LOAD_CP_REGS(3)
70 movi a4, 1 102 LOAD_CP_REGS(4)
71 ssl a2 103 LOAD_CP_REGS(5)
72 sll a4, a4 104 LOAD_CP_REGS(6)
73 and a4, a3, a4 105 LOAD_CP_REGS(7)
74 xor a3, a3, a4
75 wsr a3, CPENABLE
76 wsr a7, PS
77 rsync
78 retw
79 106
80ENTRY(enable_coprocessor) 107 .align 4
81 entry sp, 16 108.Lsave_cp_regs_jump_table:
82 rsil a7, LOCKLEVEL 109 SAVE_CP_REGS_TAB(0)
83 rsr a3, CPENABLE 110 SAVE_CP_REGS_TAB(1)
84 movi a4, 1 111 SAVE_CP_REGS_TAB(2)
85 ssl a2 112 SAVE_CP_REGS_TAB(3)
86 sll a4, a4 113 SAVE_CP_REGS_TAB(4)
87 or a3, a3, a4 114 SAVE_CP_REGS_TAB(5)
88 wsr a3, CPENABLE 115 SAVE_CP_REGS_TAB(6)
89 wsr a7, PS 116 SAVE_CP_REGS_TAB(7)
90 rsync
91 retw
92 117
118.Lload_cp_regs_jump_table:
119 LOAD_CP_REGS_TAB(0)
120 LOAD_CP_REGS_TAB(1)
121 LOAD_CP_REGS_TAB(2)
122 LOAD_CP_REGS_TAB(3)
123 LOAD_CP_REGS_TAB(4)
124 LOAD_CP_REGS_TAB(5)
125 LOAD_CP_REGS_TAB(6)
126 LOAD_CP_REGS_TAB(7)
93 127
94ENTRY(save_coprocessor_extra) 128/*
95 entry sp, 16 129 * coprocessor_save(buffer, index)
96 xchal_extra_store_funcbody 130 * a2 a3
97 retw 131 * coprocessor_load(buffer, index)
132 * a2 a3
133 *
134 * Save or load coprocessor registers for coprocessor 'index'.
135 * The register values are saved to or loaded from them 'buffer' address.
136 *
137 * Note that these functions don't update the coprocessor_owner information!
138 *
139 */
98 140
99ENTRY(restore_coprocessor_extra) 141ENTRY(coprocessor_save)
100 entry sp, 16 142 entry a1, 32
101 xchal_extra_load_funcbody 143 s32i a0, a1, 0
144 movi a0, .Lsave_cp_regs_jump_table
145 addx8 a3, a3, a0
146 l32i a3, a3, 0
147 beqz a3, 1f
148 add a0, a0, a3
149 callx0 a0
1501: l32i a0, a1, 0
102 retw 151 retw
103 152
104ENTRY(save_coprocessor_registers) 153ENTRY(coprocessor_load)
105 entry sp, 16 154 entry a1, 32
106 xchal_cpi_store_funcbody 155 s32i a0, a1, 0
156 movi a0, .Lload_cp_regs_jump_table
157 addx4 a3, a3, a0
158 l32i a3, a3, 0
159 beqz a3, 1f
160 add a0, a0, a3
161 callx0 a0
1621: l32i a0, a1, 0
107 retw 163 retw
108 164
109ENTRY(restore_coprocessor_registers) 165/*
110 entry sp, 16 166 * coprocessor_flush(struct task_info*, index)
111 xchal_cpi_load_funcbody 167 * a2 a3
168 * coprocessor_restore(struct task_info*, index)
169 * a2 a3
170 *
171 * Save or load coprocessor registers for coprocessor 'index'.
172 * The register values are saved to or loaded from the coprocessor area
173 * inside the task_info structure.
174 *
175 * Note that these functions don't update the coprocessor_owner information!
176 *
177 */
178
179
180ENTRY(coprocessor_flush)
181 entry a1, 32
182 s32i a0, a1, 0
183 movi a0, .Lsave_cp_regs_jump_table
184 addx8 a3, a3, a0
185 l32i a4, a3, 4
186 l32i a3, a3, 0
187 add a2, a2, a4
188 beqz a3, 1f
189 add a0, a0, a3
190 callx0 a0
1911: l32i a0, a1, 0
112 retw 192 retw
113 193
194ENTRY(coprocessor_restore)
195 entry a1, 32
196 s32i a0, a1, 0
197 movi a0, .Lload_cp_regs_jump_table
198 addx4 a3, a3, a0
199 l32i a4, a3, 4
200 l32i a3, a3, 0
201 add a2, a2, a4
202 beqz a3, 1f
203 add a0, a0, a3
204 callx0 a0
2051: l32i a0, a1, 0
206 retw
114 207
115/* 208/*
116 * The Xtensa compile-time HAL (core.h) XCHAL_*_SA_CONTENTS_LIBDB macros 209 * Entry condition:
117 * describe the contents of coprocessor & extra save areas in terms of
118 * undefined CONTENTS_LIBDB_{SREG,UREG,REGF} macros. We define these
119 * latter macros here; they expand into a table of the format we want.
120 * The general format is:
121 * 210 *
122 * CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, 211 * a0: trashed, original value saved on stack (PT_AREG0)
123 * bitmask, rsv2, rsv3) 212 * a1: a1
124 * CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, 213 * a2: new stack pointer, original in DEPC
125 * bitmask, rsv2, rsv3) 214 * a3: dispatch table
126 * CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, 215 * depc: a2, original value saved on stack (PT_DEPC)
127 * numentries, contentsize, regname_base, 216 * excsave_1: a3
128 * regfile_name, rsv2, rsv3)
129 * 217 *
130 * For this table, we only care about the <libdbnum>, <offset> and <size> 218 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
131 * fields. 219 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
132 */ 220 */
133 221
134/* Map all XCHAL CONTENTS macros to the reg_entry asm macro defined below: */ 222ENTRY(fast_coprocessor_double)
135 223 wsr a0, EXCSAVE_1
136#define CONTENTS_LIBDB_SREG(libdbnum,offset,size,align,rsv1,name,sregnum, \ 224 movi a0, unrecoverable_exception
137 bitmask, rsv2, rsv3) \ 225 callx0 a0
138 reg_entry libdbnum, offset, size ;
139#define CONTENTS_LIBDB_UREG(libdbnum,offset,size,align,rsv1,name,uregnum, \
140 bitmask, rsv2, rsv3) \
141 reg_entry libdbnum, offset, size ;
142#define CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, \
143 numentries, contentsize, regname_base, \
144 regfile_name, rsv2, rsv3) \
145 reg_entry libdbnum, offset, size ;
146
147/* A single table entry: */
148 .macro reg_entry libdbnum, offset, size
149 .ifne (__last_offset-(__last_group_offset+\offset))
150 /* padding entry */
151 .word (0xFC000000+__last_offset-(__last_group_offset+\offset))
152 .endif
153 .word \libdbnum /* actual entry */
154 .set __last_offset, __last_group_offset+\offset+\size
155 .endm /* reg_entry */
156
157
158/* Table entry that marks the beginning of a group (coprocessor or "extra"): */
159 .macro reg_group cpnum, num_entries, align
160 .set __last_group_offset, (__last_offset + \align- 1) & -\align
161 .ifne \num_entries
162 .word 0xFD000000+(\cpnum<<16)+\num_entries
163 .endif
164 .endm /* reg_group */
165 226
166/*
167 * Register info tables.
168 */
169 227
170 .section .rodata, "a" 228ENTRY(fast_coprocessor)
171 .globl _xtensa_reginfo_tables 229
172 .globl _xtensa_reginfo_table_size 230 /* Save remaining registers a1-a3 and SAR */
173 .align 4 231
174_xtensa_reginfo_table_size: 232 xsr a3, EXCSAVE_1
175 .word _xtensa_reginfo_table_end - _xtensa_reginfo_tables 233 s32i a3, a2, PT_AREG3
176 234 rsr a3, SAR
177_xtensa_reginfo_tables: 235 s32i a1, a2, PT_AREG1
178 .set __last_offset, 0 236 s32i a3, a2, PT_SAR
179 reg_group 0xFF, XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM, XCHAL_EXTRA_SA_ALIGN 237 mov a1, a2
180 XCHAL_EXTRA_SA_CONTENTS_LIBDB 238 rsr a2, DEPC
181 reg_group 0, XCHAL_CP0_SA_CONTENTS_LIBDB_NUM, XCHAL_CP0_SA_ALIGN 239 s32i a2, a1, PT_AREG2
182 XCHAL_CP0_SA_CONTENTS_LIBDB 240
183 reg_group 1, XCHAL_CP1_SA_CONTENTS_LIBDB_NUM, XCHAL_CP1_SA_ALIGN 241 /*
184 XCHAL_CP1_SA_CONTENTS_LIBDB 242 * The hal macros require up to 4 temporary registers. We use a3..a6.
185 reg_group 2, XCHAL_CP2_SA_CONTENTS_LIBDB_NUM, XCHAL_CP2_SA_ALIGN 243 */
186 XCHAL_CP2_SA_CONTENTS_LIBDB 244
187 reg_group 3, XCHAL_CP3_SA_CONTENTS_LIBDB_NUM, XCHAL_CP3_SA_ALIGN 245 s32i a4, a1, PT_AREG4
188 XCHAL_CP3_SA_CONTENTS_LIBDB 246 s32i a5, a1, PT_AREG5
189 reg_group 4, XCHAL_CP4_SA_CONTENTS_LIBDB_NUM, XCHAL_CP4_SA_ALIGN 247 s32i a6, a1, PT_AREG6
190 XCHAL_CP4_SA_CONTENTS_LIBDB 248
191 reg_group 5, XCHAL_CP5_SA_CONTENTS_LIBDB_NUM, XCHAL_CP5_SA_ALIGN 249 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
192 XCHAL_CP5_SA_CONTENTS_LIBDB 250
193 reg_group 6, XCHAL_CP6_SA_CONTENTS_LIBDB_NUM, XCHAL_CP6_SA_ALIGN 251 rsr a3, EXCCAUSE
194 XCHAL_CP6_SA_CONTENTS_LIBDB 252 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
195 reg_group 7, XCHAL_CP7_SA_CONTENTS_LIBDB_NUM, XCHAL_CP7_SA_ALIGN 253
196 XCHAL_CP7_SA_CONTENTS_LIBDB 254 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
197 .word 0xFC000000 /* invalid register number,marks end of table*/ 255
198_xtensa_reginfo_table_end: 256 ssl a3 # SAR: 32 - coprocessor_number
199#endif 257 movi a2, 1
258 rsr a0, CPENABLE
259 sll a2, a2
260 or a0, a0, a2
261 wsr a0, CPENABLE
262 rsync
263
264 /* Retrieve previous owner. (a3 still holds CP number) */
265
266 movi a0, coprocessor_owner # list of owners
267 addx4 a0, a3, a0 # entry for CP
268 l32i a4, a0, 0
269
270 beqz a4, 1f # skip 'save' if no previous owner
271
272 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
273
274 l32i a5, a4, THREAD_CPENABLE
275 xor a5, a5, a2 # (1 << cp-id) still in a2
276 s32i a5, a4, THREAD_CPENABLE
277
278 /*
279 * Get context save area and 'call' save routine.
280 * (a4 still holds previous owner (thread_info), a3 CP number)
281 */
282
283 movi a5, .Lsave_cp_regs_jump_table
284 movi a0, 2f # a0: 'return' address
285 addx8 a3, a3, a5 # a3: coprocessor number
286 l32i a2, a3, 4 # a2: xtregs offset
287 l32i a3, a3, 0 # a3: jump offset
288 add a2, a2, a4
289 add a4, a3, a5 # a4: address of save routine
290 jx a4
291
292 /* Note that only a0 and a1 were preserved. */
293
2942: rsr a3, EXCCAUSE
295 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
296 movi a0, coprocessor_owner
297 addx4 a0, a3, a0
298
299 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */
300
3011: GET_THREAD_INFO (a4, a1)
302 s32i a4, a0, 0
303
304 /* Get context save area and 'call' load routine. */
305
306 movi a5, .Lload_cp_regs_jump_table
307 movi a0, 1f
308 addx8 a3, a3, a5
309 l32i a2, a3, 4 # a2: xtregs offset
310 l32i a3, a3, 0 # a3: jump offset
311 add a2, a2, a4
312 add a4, a3, a5
313 jx a4
314
315 /* Restore all registers and return from exception handler. */
316
3171: l32i a6, a1, PT_AREG6
318 l32i a5, a1, PT_AREG5
319 l32i a4, a1, PT_AREG4
320
321 l32i a0, a1, PT_SAR
322 l32i a3, a1, PT_AREG3
323 l32i a2, a1, PT_AREG2
324 wsr a0, SAR
325 l32i a0, a1, PT_AREG0
326 l32i a1, a1, PT_AREG1
327
328 rfe
329
330 .data
331ENTRY(coprocessor_owner)
332 .fill XCHAL_CP_MAX, 4, 0
333
334#endif /* XTENSA_HAVE_COPROCESSORS */
200 335
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