3 files changed, 110 insertions, 5 deletions

diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 8fc1c0c8de07..b7b8fbe47c77 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -155,5 +155,100 @@ extern void copy_from_user_page(struct vm_area_struct*, struct page*,
 
 #endif
 
+#define XTENSA_CACHEBLK_LOG2    29
+#define XTENSA_CACHEBLK_SIZE    (1 << XTENSA_CACHEBLK_LOG2)
+#define XTENSA_CACHEBLK_MASK    (7 << XTENSA_CACHEBLK_LOG2)
+
+#if XCHAL_HAVE_CACHEATTR
+static inline u32 xtensa_get_cacheattr(void)
+{
+        u32 r;
+        asm volatile("  rsr %0, CACHEATTR" : "=a"(r));
+        return r;
+}
+
+static inline u32 xtensa_get_dtlb1(u32 addr)
+{
+        u32 r = addr & XTENSA_CACHEBLK_MASK;
+        return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2)))
+                        & 0xF);
+}
+#else
+static inline u32 xtensa_get_dtlb1(u32 addr)
+{
+        u32 r;
+        asm volatile("  rdtlb1 %0, %1" : "=a"(r) : "a"(addr));
+        asm volatile("  dsync");
+        return r;
+}
+
+static inline u32 xtensa_get_cacheattr(void)
+{
+        u32 r = 0;
+        u32 a = 0;
+        do {
+                a -= XTENSA_CACHEBLK_SIZE;
+                r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF);
+        } while (a);
+        return r;
+}
+#endif
+
+static inline int xtensa_need_flush_dma_source(u32 addr)
+{
+        return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4;
+}
+
+static inline int xtensa_need_invalidate_dma_destination(u32 addr)
+{
+        return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2;
+}
+
+static inline void flush_dcache_unaligned(u32 addr, u32 size)
+{
+        u32 cnt;
+        if (size) {
+                cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
+                        + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
+                while (cnt--) {
+                        asm volatile("  dhwb %0, 0" : : "a"(addr));
+                        addr += XCHAL_DCACHE_LINESIZE;
+                }
+                asm volatile("  dsync");
+        }
+}
+
+static inline void invalidate_dcache_unaligned(u32 addr, u32 size)
+{
+        int cnt;
+        if (size) {
+                asm volatile("  dhwbi %0, 0 ;" : : "a"(addr));
+                cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
+                        - XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
+                while (cnt-- > 0) {
+                        asm volatile("  dhi %0, %1" : : "a"(addr),
+                                                "n"(XCHAL_DCACHE_LINESIZE));
+                        addr += XCHAL_DCACHE_LINESIZE;
+                }
+                asm volatile("  dhwbi %0, %1" : : "a"(addr),
+                                                "n"(XCHAL_DCACHE_LINESIZE));
+                asm volatile("  dsync");
+        }
+}
+
+static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size)
+{
+        u32 cnt;
+        if (size) {
+                cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
+                        + XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
+                while (cnt--) {
+                        asm volatile("  dhwbi %0, 0" : : "a"(addr));
+                        addr += XCHAL_DCACHE_LINESIZE;
+                }
+                asm volatile("  dsync");
+        }
+}
+
 #endif /* __KERNEL__ */
 #endif /* _XTENSA_CACHEFLUSH_H */
diff --git a/arch/xtensa/include/asm/gpio.h b/arch/xtensa/include/asm/gpio.h
index 0763b0763960..a8c9fc46c790 100644
--- a/arch/xtensa/include/asm/gpio.h
+++ b/arch/xtensa/include/asm/gpio.h
@@ -38,14 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio)
         return __gpio_cansleep(gpio);
 }
 
-/*
- * Not implemented, yet.
- */
 static inline int gpio_to_irq(unsigned int gpio)
 {
-        return -ENOSYS;
+        return __gpio_to_irq(gpio);
 }
 
+/*
+ * Not implemented, yet.
+ */
 static inline int irq_to_gpio(unsigned int irq)
 {
         return -EINVAL;
diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h
index dfac82dc52ad..4c0ccc9c4f4c 100644
--- a/arch/xtensa/include/asm/irq.h
+++ b/arch/xtensa/include/asm/irq.h
@@ -11,6 +11,7 @@
 #ifndef _XTENSA_IRQ_H
 #define _XTENSA_IRQ_H
 
+#include <linux/init.h>
 #include <platform/hardware.h>
 #include <variant/core.h>
 
@@ -21,11 +22,20 @@ static inline void variant_irq_enable(unsigned int irq) { }
 static inline void variant_irq_disable(unsigned int irq) { }
 #endif
 
+#ifndef VARIANT_NR_IRQS
+# define VARIANT_NR_IRQS 0
+#endif
 #ifndef PLATFORM_NR_IRQS
 # define PLATFORM_NR_IRQS 0
 #endif
 #define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
-#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS)
+#define NR_IRQS (XTENSA_NR_IRQS + VARIANT_NR_IRQS + PLATFORM_NR_IRQS)
+
+#if VARIANT_NR_IRQS == 0
+static inline void variant_init_irq(void) { }
+#else
+void variant_init_irq(void) __init;
+#endif
 
 static __inline__ int irq_canonicalize(int irq)
 {