1 files changed, 28 insertions, 16 deletions
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h
index 8c194f6af45e..677bfcf4ee5d 100644
--- a/arch/xtensa/include/asm/traps.h
+++ b/arch/xtensa/include/asm/traps.h
@@ -23,25 +23,37 @@ void secondary_trap_init(void);
 static inline void spill_registers(void)
 {
+#if XCHAL_NUM_AREGS > 16
        __asm__ __volatile__ (
-                "movi   a14, "__stringify((1 << PS_EXCM_BIT) | LOCKLEVEL)"\n\t"
+                "       call12  1f\n"
-                "mov    a12, a0\n\t"
+                "       _j      2f\n"
-                "rsr    a13, sar\n\t"
+                "       retw\n"
-                "xsr    a14, ps\n\t"
+                "       .align  4\n"
-                "movi   a0, _spill_registers\n\t"
+                "1:\n"
-                "rsync\n\t"
+                "       _entry  a1, 48\n"
-                "callx0 a0\n\t"
+                "       addi    a12, a0, 3\n"
-                "mov    a0, a12\n\t"
+#if XCHAL_NUM_AREGS > 32
-                "wsr    a13, sar\n\t"
+                "       .rept   (" __stringify(XCHAL_NUM_AREGS) " - 32) / 12\n"
-                "wsr    a14, ps\n\t"
+                "       _entry  a1, 48\n"
-                : :
+                "       mov     a12, a0\n"
-#if defined(CONFIG_FRAME_POINTER)
+                "       .endr\n"
-                : "a2", "a3", "a4",       "a11", "a12", "a13", "a14", "a15",
+#endif
+                "       _entry  a1, 48\n"
+#if XCHAL_NUM_AREGS % 12 == 0
+                "       mov     a8, a8\n"
+#elif XCHAL_NUM_AREGS % 12 == 4
+                "       mov     a12, a12\n"
+#elif XCHAL_NUM_AREGS % 12 == 8
+                "       mov     a4, a4\n"
+#endif
+                "       retw\n"
+                "2:\n"
+                : : : "a12", "a13", "memory");
 #else
-                : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15",
+        __asm__ __volatile__ (
+                "       mov     a12, a12\n"
+                : : : "memory");
 #endif
-                  "memory");
 }
 #endif /* _XTENSA_TRAPS_H */

diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h index 8c194f6af45e..677bfcf4ee5d 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h
@@ -23,25 +23,37 @@ void secondary_trap_init(void);
23		23
24	static inline void spill_registers(void)	24	static inline void spill_registers(void)
25	{	25	{
26		26	#if XCHAL_NUM_AREGS > 16
27	__asm__ __volatile__ (	27	__asm__ __volatile__ (
28	"movi a14, "__stringify((1 << PS_EXCM_BIT) \| LOCKLEVEL)"\n\t"	28	" call12 1f\n"
29	"mov a12, a0\n\t"	29	" _j 2f\n"
30	"rsr a13, sar\n\t"	30	" retw\n"
31	"xsr a14, ps\n\t"	31	" .align 4\n"
32	"movi a0, _spill_registers\n\t"	32	"1:\n"
33	"rsync\n\t"	33	" _entry a1, 48\n"
34	"callx0 a0\n\t"	34	" addi a12, a0, 3\n"
35	"mov a0, a12\n\t"	35	#if XCHAL_NUM_AREGS > 32
36	"wsr a13, sar\n\t"	36	" .rept (" __stringify(XCHAL_NUM_AREGS) " - 32) / 12\n"
37	"wsr a14, ps\n\t"	37	" _entry a1, 48\n"
38	: :	38	" mov a12, a0\n"
39	#if defined(CONFIG_FRAME_POINTER)	39	" .endr\n"
40	: "a2", "a3", "a4", "a11", "a12", "a13", "a14", "a15",	40	#endif
		41	" _entry a1, 48\n"
		42	#if XCHAL_NUM_AREGS % 12 == 0
		43	" mov a8, a8\n"
		44	#elif XCHAL_NUM_AREGS % 12 == 4
		45	" mov a12, a12\n"
		46	#elif XCHAL_NUM_AREGS % 12 == 8
		47	" mov a4, a4\n"
		48	#endif
		49	" retw\n"
		50	"2:\n"
		51	: : : "a12", "a13", "memory");
41	#else	52	#else
42	: "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15",	53	__asm__ __volatile__ (
		54	" mov a12, a12\n"
		55	: : : "memory");
43	#endif	56	#endif
44	"memory");
45	}	57	}
46		58
47	#endif /* _XTENSA_TRAPS_H */	59	#endif /* _XTENSA_TRAPS_H */