3 files changed, 19 insertions, 16 deletions

diff --git a/arch/x86_64/kernel/mce.c b/arch/x86_64/kernel/mce.c
index 08203b07f4bd..69541db5ff2c 100644
--- a/arch/x86_64/kernel/mce.c
+++ b/arch/x86_64/kernel/mce.c
@@ -54,9 +54,12 @@ void mce_log(struct mce *mce)
 {
         unsigned next, entry;
         mce->finished = 0;
-        smp_wmb();
+        wmb();
         for (;;) {
                 entry = rcu_dereference(mcelog.next);
+                /* The rmb forces the compiler to reload next in each
+                    iteration */
+                rmb();
                 for (;;) {
                         /* When the buffer fills up discard new entries. Assume
                            that the earlier errors are the more interesting. */
@@ -69,6 +72,7 @@ void mce_log(struct mce *mce)
                                 entry++;
                                 continue;
                         }
+                        break;
                 }
                 smp_rmb();
                 next = entry + 1;
@@ -76,9 +80,9 @@ void mce_log(struct mce *mce)
                         break;
         }
         memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
-        smp_wmb();
+        wmb();
         mcelog.entry[entry].finished = 1;
-        smp_wmb();
+        wmb();
 
         if (!test_and_set_bit(0, &console_logged))
                 notify_user = 1;
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 238f73e1a834..257f5ba17902 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -831,8 +831,6 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
 #endif
 }
 
-#define HWCR 0xc0010015
-
 static int __init init_amd(struct cpuinfo_x86 *c)
 {
         int r;
@@ -841,14 +839,18 @@ static int __init init_amd(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
         unsigned long value;
 
-        // Disable TLB flush filter by setting HWCR.FFDIS:
-        // bit 6 of msr C001_0015
-        //
-        // Errata 63 for SH-B3 steppings
-        // Errata 122 for all(?) steppings
-        rdmsrl(HWCR, value);
-        value |= 1 << 6;
-        wrmsrl(HWCR, value);
+        /*
+         * Disable TLB flush filter by setting HWCR.FFDIS on K8
+         * bit 6 of msr C001_0015
+         *
+         * Errata 63 for SH-B3 steppings
+         * Errata 122 for all steppings (F+ have it disabled by default)
+         */
+        if (c->x86 == 15) {
+                rdmsrl(MSR_K8_HWCR, value);
+                value |= 1 << 6;
+                wrmsrl(MSR_K8_HWCR, value);
+        }
 #endif
 
         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c
index 2373cb8b8625..703acde2a1a5 100644
--- a/arch/x86_64/kernel/time.c
+++ b/arch/x86_64/kernel/time.c
@@ -959,9 +959,6 @@ static __init int unsynchronized_tsc(void)
            are handled in the OEM check above. */
         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
                 return 0;
-        /* All in a single socket - should be synchronized */
-        if (cpus_weight(cpu_core_map[0]) == num_online_cpus())
-                return 0;
 #endif
         /* Assume multi socket systems are not synchronized */
         return num_online_cpus() > 1;