1 files changed, 557 insertions, 283 deletions

diff --git a/arch/x86_64/kernel/nmi.c b/arch/x86_64/kernel/nmi.c
index 5baa0c726e97..4d6fb047952e 100644
--- a/arch/x86_64/kernel/nmi.c
+++ b/arch/x86_64/kernel/nmi.c
@@ -28,71 +28,138 @@
 #include <asm/mce.h>
 #include <asm/intel_arch_perfmon.h>
 
-/*
- * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
- * - it may be reserved by some other driver, or not
- * - when not reserved by some other driver, it may be used for
- *   the NMI watchdog, or not
- *
- * This is maintained separately from nmi_active because the NMI
- * watchdog may also be driven from the I/O APIC timer.
+/* perfctr_nmi_owner tracks the ownership of the perfctr registers:
+ * evtsel_nmi_owner tracks the ownership of the event selection
+ * - different performance counters/ event selection may be reserved for
+ *   different subsystems this reservation system just tries to coordinate
+ *   things a little
  */
-static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
-static unsigned int lapic_nmi_owner;
-#define LAPIC_NMI_WATCHDOG      (1<<0)
-#define LAPIC_NMI_RESERVED      (1<<1)
+static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
+static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
+
+/* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
+ * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
+ */
+#define NMI_MAX_COUNTER_BITS 66
 
 /* nmi_active:
- * +1: the lapic NMI watchdog is active, but can be disabled
- *  0: the lapic NMI watchdog has not been set up, and cannot
+ * >0: the lapic NMI watchdog is active, but can be disabled
+ * <0: the lapic NMI watchdog has not been set up, and cannot
  *     be enabled
- * -1: the lapic NMI watchdog is disabled, but can be enabled
+ *  0: the lapic NMI watchdog is disabled, but can be enabled
  */
-int nmi_active;         /* oprofile uses this */
+atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
 int panic_on_timeout;
 
 unsigned int nmi_watchdog = NMI_DEFAULT;
 static unsigned int nmi_hz = HZ;
-static unsigned int nmi_perfctr_msr;    /* the MSR to reset in NMI handler */
-static unsigned int nmi_p4_cccr_val;
 
-/* Note that these events don't tick when the CPU idles. This means
-   the frequency varies with CPU load. */
+struct nmi_watchdog_ctlblk {
+        int enabled;
+        u64 check_bit;
+        unsigned int cccr_msr;
+        unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
+        unsigned int evntsel_msr;  /* the MSR to select the events to handle */
+};
+static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
 
-#define K7_EVNTSEL_ENABLE       (1 << 22)
-#define K7_EVNTSEL_INT          (1 << 20)
-#define K7_EVNTSEL_OS           (1 << 17)
-#define K7_EVNTSEL_USR          (1 << 16)
-#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
-#define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
+/* local prototypes */
+static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
 
-#define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
-#define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
+/* converts an msr to an appropriate reservation bit */
+static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
+{
+        /* returns the bit offset of the performance counter register */
+        switch (boot_cpu_data.x86_vendor) {
+        case X86_VENDOR_AMD:
+                return (msr - MSR_K7_PERFCTR0);
+        case X86_VENDOR_INTEL:
+                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
+                        return (msr - MSR_ARCH_PERFMON_PERFCTR0);
+                else
+                        return (msr - MSR_P4_BPU_PERFCTR0);
+        }
+        return 0;
+}
 
-#define MSR_P4_MISC_ENABLE      0x1A0
-#define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
-#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
-#define MSR_P4_PERFCTR0         0x300
-#define MSR_P4_CCCR0            0x360
-#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
-#define P4_ESCR_OS              (1<<3)
-#define P4_ESCR_USR             (1<<2)
-#define P4_CCCR_OVF_PMI0        (1<<26)
-#define P4_CCCR_OVF_PMI1        (1<<27)
-#define P4_CCCR_THRESHOLD(N)    ((N)<<20)
-#define P4_CCCR_COMPLEMENT      (1<<19)
-#define P4_CCCR_COMPARE         (1<<18)
-#define P4_CCCR_REQUIRED        (3<<16)
-#define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
-#define P4_CCCR_ENABLE          (1<<12)
-/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
-   CRU_ESCR0 (with any non-null event selector) through a complemented
-   max threshold. [IA32-Vol3, Section 14.9.9] */
-#define MSR_P4_IQ_COUNTER0      0x30C
-#define P4_NMI_CRU_ESCR0        (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
-#define P4_NMI_IQ_CCCR0 \
-        (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|     \
-         P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
+/* converts an msr to an appropriate reservation bit */
+static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
+{
+        /* returns the bit offset of the event selection register */
+        switch (boot_cpu_data.x86_vendor) {
+        case X86_VENDOR_AMD:
+                return (msr - MSR_K7_EVNTSEL0);
+        case X86_VENDOR_INTEL:
+                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
+                        return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
+                else
+                        return (msr - MSR_P4_BSU_ESCR0);
+        }
+        return 0;
+}
+
+/* checks for a bit availability (hack for oprofile) */
+int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
+{
+        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+
+        return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
+}
+
+/* checks the an msr for availability */
+int avail_to_resrv_perfctr_nmi(unsigned int msr)
+{
+        unsigned int counter;
+
+        counter = nmi_perfctr_msr_to_bit(msr);
+        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+
+        return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
+}
+
+int reserve_perfctr_nmi(unsigned int msr)
+{
+        unsigned int counter;
+
+        counter = nmi_perfctr_msr_to_bit(msr);
+        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+
+        if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
+                return 1;
+        return 0;
+}
+
+void release_perfctr_nmi(unsigned int msr)
+{
+        unsigned int counter;
+
+        counter = nmi_perfctr_msr_to_bit(msr);
+        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+
+        clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
+}
+
+int reserve_evntsel_nmi(unsigned int msr)
+{
+        unsigned int counter;
+
+        counter = nmi_evntsel_msr_to_bit(msr);
+        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+
+        if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
+                return 1;
+        return 0;
+}
+
+void release_evntsel_nmi(unsigned int msr)
+{
+        unsigned int counter;
+
+        counter = nmi_evntsel_msr_to_bit(msr);
+        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
+
+        clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
+}
 
 static __cpuinit inline int nmi_known_cpu(void)
 {
@@ -109,7 +176,7 @@ static __cpuinit inline int nmi_known_cpu(void)
 }
 
 /* Run after command line and cpu_init init, but before all other checks */
-void __cpuinit nmi_watchdog_default(void)
+void nmi_watchdog_default(void)
 {
         if (nmi_watchdog != NMI_DEFAULT)
                 return;
@@ -145,6 +212,12 @@ int __init check_nmi_watchdog (void)
         int *counts;
         int cpu;
 
+        if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
+                return 0;
+
+        if (!atomic_read(&nmi_active))
+                return 0;
+
         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
         if (!counts)
                 return -1;
@@ -162,26 +235,43 @@ int __init check_nmi_watchdog (void)
         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 
         for_each_online_cpu(cpu) {
+                if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
+                        continue;
                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
-                        endflag = 1;
                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
                                cpu,
                                counts[cpu],
                                cpu_pda(cpu)->__nmi_count);
-                        nmi_active = 0;
-                        lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
-                        nmi_perfctr_msr = 0;
-                        kfree(counts);
-                        return -1;
+                        per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
+                        atomic_dec(&nmi_active);
                 }
         }
+        if (!atomic_read(&nmi_active)) {
+                kfree(counts);
+                atomic_set(&nmi_active, -1);
+                return -1;
+        }
         endflag = 1;
         printk("OK.\n");
 
         /* now that we know it works we can reduce NMI frequency to
            something more reasonable; makes a difference in some configs */
-        if (nmi_watchdog == NMI_LOCAL_APIC)
+        if (nmi_watchdog == NMI_LOCAL_APIC) {
+                struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
+
                 nmi_hz = 1;
+                /*
+                 * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
+                 * are writable, with higher bits sign extending from bit 31.
+                 * So, we can only program the counter with 31 bit values and
+                 * 32nd bit should be 1, for 33.. to be 1.
+                 * Find the appropriate nmi_hz
+                 */
+                if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0 &&
+                        ((u64)cpu_khz * 1000) > 0x7fffffffULL) {
+                        nmi_hz = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
+                }
+        }
 
         kfree(counts);
         return 0;
@@ -201,91 +291,65 @@ int __init setup_nmi_watchdog(char *str)
 
         get_option(&str, &nmi);
 
-        if (nmi >= NMI_INVALID)
+        if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
                 return 0;
+
+        if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
+                return 0;  /* no lapic support */
         nmi_watchdog = nmi;
         return 1;
 }
 
 __setup("nmi_watchdog=", setup_nmi_watchdog);
 
-static void disable_intel_arch_watchdog(void);
-
 static void disable_lapic_nmi_watchdog(void)
 {
-        if (nmi_active <= 0)
+        BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
+
+        if (atomic_read(&nmi_active) <= 0)
                 return;
-        switch (boot_cpu_data.x86_vendor) {
-        case X86_VENDOR_AMD:
-                wrmsr(MSR_K7_EVNTSEL0, 0, 0);
-                break;
-        case X86_VENDOR_INTEL:
-                if (boot_cpu_data.x86 == 15) {
-                        wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
-                        wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
-                } else if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
-                        disable_intel_arch_watchdog();
-                }
-                break;
-        }
-        nmi_active = -1;
-        /* tell do_nmi() and others that we're not active any more */
-        nmi_watchdog = 0;
-}
 
-static void enable_lapic_nmi_watchdog(void)
-{
-        if (nmi_active < 0) {
-                nmi_watchdog = NMI_LOCAL_APIC;
-                touch_nmi_watchdog();
-                setup_apic_nmi_watchdog();
-        }
+        on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
+
+        BUG_ON(atomic_read(&nmi_active) != 0);
 }
 
-int reserve_lapic_nmi(void)
+static void enable_lapic_nmi_watchdog(void)
 {
-        unsigned int old_owner;
+        BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 
-        spin_lock(&lapic_nmi_owner_lock);
-        old_owner = lapic_nmi_owner;
-        lapic_nmi_owner |= LAPIC_NMI_RESERVED;
-        spin_unlock(&lapic_nmi_owner_lock);
-        if (old_owner & LAPIC_NMI_RESERVED)
-                return -EBUSY;
-        if (old_owner & LAPIC_NMI_WATCHDOG)
-                disable_lapic_nmi_watchdog();
-        return 0;
-}
+        /* are we already enabled */
+        if (atomic_read(&nmi_active) != 0)
+                return;
 
-void release_lapic_nmi(void)
-{
-        unsigned int new_owner;
+        /* are we lapic aware */
+        if (nmi_known_cpu() <= 0)
+                return;
 
-        spin_lock(&lapic_nmi_owner_lock);
-        new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
-        lapic_nmi_owner = new_owner;
-        spin_unlock(&lapic_nmi_owner_lock);
-        if (new_owner & LAPIC_NMI_WATCHDOG)
-                enable_lapic_nmi_watchdog();
+        on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
+        touch_nmi_watchdog();
 }
 
 void disable_timer_nmi_watchdog(void)
 {
-        if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
+        BUG_ON(nmi_watchdog != NMI_IO_APIC);
+
+        if (atomic_read(&nmi_active) <= 0)
                 return;
 
         disable_irq(0);
-        unset_nmi_callback();
-        nmi_active = -1;
-        nmi_watchdog = NMI_NONE;
+        on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
+
+        BUG_ON(atomic_read(&nmi_active) != 0);
 }
 
 void enable_timer_nmi_watchdog(void)
 {
-        if (nmi_active < 0) {
-                nmi_watchdog = NMI_IO_APIC;
+        BUG_ON(nmi_watchdog != NMI_IO_APIC);
+
+        if (atomic_read(&nmi_active) == 0) {
                 touch_nmi_watchdog();
-                nmi_active = 1;
+                on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
                 enable_irq(0);
         }
 }
@@ -296,15 +360,20 @@ static int nmi_pm_active; /* nmi_active before suspend */
 
 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 {
-        nmi_pm_active = nmi_active;
-        disable_lapic_nmi_watchdog();
+        /* only CPU0 goes here, other CPUs should be offline */
+        nmi_pm_active = atomic_read(&nmi_active);
+        stop_apic_nmi_watchdog(NULL);
+        BUG_ON(atomic_read(&nmi_active) != 0);
         return 0;
 }
 
 static int lapic_nmi_resume(struct sys_device *dev)
 {
-        if (nmi_pm_active > 0)
-        enable_lapic_nmi_watchdog();
+        /* only CPU0 goes here, other CPUs should be offline */
+        if (nmi_pm_active > 0) {
+                setup_apic_nmi_watchdog(NULL);
+                touch_nmi_watchdog();
+        }
         return 0;
 }
 
@@ -323,7 +392,13 @@ static int __init init_lapic_nmi_sysfs(void)
 {
         int error;
 
-        if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
+        /* should really be a BUG_ON but b/c this is an
+         * init call, it just doesn't work.  -dcz
+         */
+        if (nmi_watchdog != NMI_LOCAL_APIC)
+                return 0;
+
+        if ( atomic_read(&nmi_active) < 0 )
                 return 0;
 
         error = sysdev_class_register(&nmi_sysclass);
@@ -341,74 +416,209 @@ late_initcall(init_lapic_nmi_sysfs);
  * Original code written by Keith Owens.
  */
 
-static void clear_msr_range(unsigned int base, unsigned int n)
-{
-        unsigned int i;
+/* Note that these events don't tick when the CPU idles. This means
+   the frequency varies with CPU load. */
 
-        for(i = 0; i < n; ++i)
-                wrmsr(base+i, 0, 0);
-}
+#define K7_EVNTSEL_ENABLE       (1 << 22)
+#define K7_EVNTSEL_INT          (1 << 20)
+#define K7_EVNTSEL_OS           (1 << 17)
+#define K7_EVNTSEL_USR          (1 << 16)
+#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
+#define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 
-static void setup_k7_watchdog(void)
+static int setup_k7_watchdog(void)
 {
-        int i;
+        unsigned int perfctr_msr, evntsel_msr;
         unsigned int evntsel;
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 
-        nmi_perfctr_msr = MSR_K7_PERFCTR0;
+        perfctr_msr = MSR_K7_PERFCTR0;
+        evntsel_msr = MSR_K7_EVNTSEL0;
+        if (!reserve_perfctr_nmi(perfctr_msr))
+                goto fail;
 
-        for(i = 0; i < 4; ++i) {
-                /* Simulator may not support it */
-                if (checking_wrmsrl(MSR_K7_EVNTSEL0+i, 0UL)) {
-                        nmi_perfctr_msr = 0;
-                        return;
-                }
-                wrmsrl(MSR_K7_PERFCTR0+i, 0UL);
-        }
+        if (!reserve_evntsel_nmi(evntsel_msr))
+                goto fail1;
+
+        /* Simulator may not support it */
+        if (checking_wrmsrl(evntsel_msr, 0UL))
+                goto fail2;
+        wrmsrl(perfctr_msr, 0UL);
 
         evntsel = K7_EVNTSEL_INT
                 | K7_EVNTSEL_OS
                 | K7_EVNTSEL_USR
                 | K7_NMI_EVENT;
 
-        wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
-        wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
+        /* setup the timer */
+        wrmsr(evntsel_msr, evntsel, 0);
+        wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
         apic_write(APIC_LVTPC, APIC_DM_NMI);
         evntsel |= K7_EVNTSEL_ENABLE;
-        wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
+        wrmsr(evntsel_msr, evntsel, 0);
+
+        wd->perfctr_msr = perfctr_msr;
+        wd->evntsel_msr = evntsel_msr;
+        wd->cccr_msr = 0;  //unused
+        wd->check_bit = 1ULL<<63;
+        return 1;
+fail2:
+        release_evntsel_nmi(evntsel_msr);
+fail1:
+        release_perfctr_nmi(perfctr_msr);
+fail:
+        return 0;
 }
 
-static void disable_intel_arch_watchdog(void)
+static void stop_k7_watchdog(void)
 {
-        unsigned ebx;
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 
-        /*
-         * Check whether the Architectural PerfMon supports
-         * Unhalted Core Cycles Event or not.
-         * NOTE: Corresponding bit = 0 in ebp indicates event present.
+        wrmsr(wd->evntsel_msr, 0, 0);
+
+        release_evntsel_nmi(wd->evntsel_msr);
+        release_perfctr_nmi(wd->perfctr_msr);
+}
+
+/* Note that these events don't tick when the CPU idles. This means
+   the frequency varies with CPU load. */
+
+#define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
+#define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
+#define P4_ESCR_OS              (1<<3)
+#define P4_ESCR_USR             (1<<2)
+#define P4_CCCR_OVF_PMI0        (1<<26)
+#define P4_CCCR_OVF_PMI1        (1<<27)
+#define P4_CCCR_THRESHOLD(N)    ((N)<<20)
+#define P4_CCCR_COMPLEMENT      (1<<19)
+#define P4_CCCR_COMPARE         (1<<18)
+#define P4_CCCR_REQUIRED        (3<<16)
+#define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
+#define P4_CCCR_ENABLE          (1<<12)
+#define P4_CCCR_OVF             (1<<31)
+/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
+   CRU_ESCR0 (with any non-null event selector) through a complemented
+   max threshold. [IA32-Vol3, Section 14.9.9] */
+
+static int setup_p4_watchdog(void)
+{
+        unsigned int perfctr_msr, evntsel_msr, cccr_msr;
+        unsigned int evntsel, cccr_val;
+        unsigned int misc_enable, dummy;
+        unsigned int ht_num;
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
+
+        rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
+        if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
+                return 0;
+
+#ifdef CONFIG_SMP
+        /* detect which hyperthread we are on */
+        if (smp_num_siblings == 2) {
+                unsigned int ebx, apicid;
+
+                ebx = cpuid_ebx(1);
+                apicid = (ebx >> 24) & 0xff;
+                ht_num = apicid & 1;
+        } else
+#endif
+                ht_num = 0;
+
+        /* performance counters are shared resources
+         * assign each hyperthread its own set
+         * (re-use the ESCR0 register, seems safe
+         * and keeps the cccr_val the same)
          */
-        ebx = cpuid_ebx(10);
-        if (!(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
-                wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, 0, 0);
+        if (!ht_num) {
+                /* logical cpu 0 */
+                perfctr_msr = MSR_P4_IQ_PERFCTR0;
+                evntsel_msr = MSR_P4_CRU_ESCR0;
+                cccr_msr = MSR_P4_IQ_CCCR0;
+                cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
+        } else {
+                /* logical cpu 1 */
+                perfctr_msr = MSR_P4_IQ_PERFCTR1;
+                evntsel_msr = MSR_P4_CRU_ESCR0;
+                cccr_msr = MSR_P4_IQ_CCCR1;
+                cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
+        }
+
+        if (!reserve_perfctr_nmi(perfctr_msr))
+                goto fail;
+
+        if (!reserve_evntsel_nmi(evntsel_msr))
+                goto fail1;
+
+        evntsel = P4_ESCR_EVENT_SELECT(0x3F)
+                | P4_ESCR_OS
+                | P4_ESCR_USR;
+
+        cccr_val |= P4_CCCR_THRESHOLD(15)
+                 | P4_CCCR_COMPLEMENT
+                 | P4_CCCR_COMPARE
+                 | P4_CCCR_REQUIRED;
+
+        wrmsr(evntsel_msr, evntsel, 0);
+        wrmsr(cccr_msr, cccr_val, 0);
+        wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+        apic_write(APIC_LVTPC, APIC_DM_NMI);
+        cccr_val |= P4_CCCR_ENABLE;
+        wrmsr(cccr_msr, cccr_val, 0);
+
+        wd->perfctr_msr = perfctr_msr;
+        wd->evntsel_msr = evntsel_msr;
+        wd->cccr_msr = cccr_msr;
+        wd->check_bit = 1ULL<<39;
+        return 1;
+fail1:
+        release_perfctr_nmi(perfctr_msr);
+fail:
+        return 0;
+}
+
+static void stop_p4_watchdog(void)
+{
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
+
+        wrmsr(wd->cccr_msr, 0, 0);
+        wrmsr(wd->evntsel_msr, 0, 0);
+
+        release_evntsel_nmi(wd->evntsel_msr);
+        release_perfctr_nmi(wd->perfctr_msr);
 }
 
+#define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
+#define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
+
 static int setup_intel_arch_watchdog(void)
 {
+        unsigned int ebx;
+        union cpuid10_eax eax;
+        unsigned int unused;
+        unsigned int perfctr_msr, evntsel_msr;
         unsigned int evntsel;
-        unsigned ebx;
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 
         /*
          * Check whether the Architectural PerfMon supports
          * Unhalted Core Cycles Event or not.
-         * NOTE: Corresponding bit = 0 in ebp indicates event present.
+         * NOTE: Corresponding bit = 0 in ebx indicates event present.
          */
-        ebx = cpuid_ebx(10);
-        if ((ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
-                return 0;
+        cpuid(10, &(eax.full), &ebx, &unused, &unused);
+        if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
+            (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
+                goto fail;
+
+        perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
+        evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
 
-        nmi_perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
+        if (!reserve_perfctr_nmi(perfctr_msr))
+                goto fail;
 
-        clear_msr_range(MSR_ARCH_PERFMON_EVENTSEL0, 2);
-        clear_msr_range(MSR_ARCH_PERFMON_PERFCTR0, 2);
+        if (!reserve_evntsel_nmi(evntsel_msr))
+                goto fail1;
+
+        wrmsrl(perfctr_msr, 0UL);
 
         evntsel = ARCH_PERFMON_EVENTSEL_INT
                 | ARCH_PERFMON_EVENTSEL_OS
@@ -416,84 +626,122 @@ static int setup_intel_arch_watchdog(void)
                 | ARCH_PERFMON_NMI_EVENT_SEL
                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 
-        wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
-        wrmsrl(MSR_ARCH_PERFMON_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
+        /* setup the timer */
+        wrmsr(evntsel_msr, evntsel, 0);
+        wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+
         apic_write(APIC_LVTPC, APIC_DM_NMI);
         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-        wrmsr(MSR_ARCH_PERFMON_EVENTSEL0, evntsel, 0);
+        wrmsr(evntsel_msr, evntsel, 0);
+
+        wd->perfctr_msr = perfctr_msr;
+        wd->evntsel_msr = evntsel_msr;
+        wd->cccr_msr = 0;  //unused
+        wd->check_bit = 1ULL << (eax.split.bit_width - 1);
         return 1;
+fail1:
+        release_perfctr_nmi(perfctr_msr);
+fail:
+        return 0;
 }
 
-
-static int setup_p4_watchdog(void)
+static void stop_intel_arch_watchdog(void)
 {
-        unsigned int misc_enable, dummy;
+        unsigned int ebx;
+        union cpuid10_eax eax;
+        unsigned int unused;
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 
-        rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
-        if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
-                return 0;
+        /*
+         * Check whether the Architectural PerfMon supports
+         * Unhalted Core Cycles Event or not.
+         * NOTE: Corresponding bit = 0 in ebx indicates event present.
+         */
+        cpuid(10, &(eax.full), &ebx, &unused, &unused);
+        if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
+            (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
+                return;
 
-        nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
-        nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
-#ifdef CONFIG_SMP
-        if (smp_num_siblings == 2)
-                nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
-#endif
+        wrmsr(wd->evntsel_msr, 0, 0);
 
-        if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
-                clear_msr_range(0x3F1, 2);
-        /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
-           docs doesn't fully define it, so leave it alone for now. */
-        if (boot_cpu_data.x86_model >= 0x3) {
-                /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
-                clear_msr_range(0x3A0, 26);
-                clear_msr_range(0x3BC, 3);
-        } else {
-                clear_msr_range(0x3A0, 31);
-        }
-        clear_msr_range(0x3C0, 6);
-        clear_msr_range(0x3C8, 6);
-        clear_msr_range(0x3E0, 2);
-        clear_msr_range(MSR_P4_CCCR0, 18);
-        clear_msr_range(MSR_P4_PERFCTR0, 18);
-
-        wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
-        wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
-        Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
-        wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
-        return 1;
+        release_evntsel_nmi(wd->evntsel_msr);
+        release_perfctr_nmi(wd->perfctr_msr);
 }
 
-void setup_apic_nmi_watchdog(void)
+void setup_apic_nmi_watchdog(void *unused)
 {
-        switch (boot_cpu_data.x86_vendor) {
-        case X86_VENDOR_AMD:
-                if (boot_cpu_data.x86 != 15)
-                        return;
-                if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
-                        return;
-                setup_k7_watchdog();
-                break;
-        case X86_VENDOR_INTEL:
-                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
-                        if (!setup_intel_arch_watchdog())
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
+
+        /* only support LOCAL and IO APICs for now */
+        if ((nmi_watchdog != NMI_LOCAL_APIC) &&
+            (nmi_watchdog != NMI_IO_APIC))
+                return;
+
+        if (wd->enabled == 1)
+                return;
+
+        /* cheap hack to support suspend/resume */
+        /* if cpu0 is not active neither should the other cpus */
+        if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
+                return;
+
+        if (nmi_watchdog == NMI_LOCAL_APIC) {
+                switch (boot_cpu_data.x86_vendor) {
+                case X86_VENDOR_AMD:
+                        if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
                                 return;
-                } else if (boot_cpu_data.x86 == 15) {
+                        if (!setup_k7_watchdog())
+                                return;
+                        break;
+                case X86_VENDOR_INTEL:
+                        if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
+                                if (!setup_intel_arch_watchdog())
+                                        return;
+                                break;
+                        }
                         if (!setup_p4_watchdog())
                                 return;
-                } else {
+                        break;
+                default:
                         return;
                 }
+        }
+        wd->enabled = 1;
+        atomic_inc(&nmi_active);
+}
+
+void stop_apic_nmi_watchdog(void *unused)
+{
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 
-                break;
+        /* only support LOCAL and IO APICs for now */
+        if ((nmi_watchdog != NMI_LOCAL_APIC) &&
+            (nmi_watchdog != NMI_IO_APIC))
+                return;
 
-        default:
+        if (wd->enabled == 0)
                 return;
+
+        if (nmi_watchdog == NMI_LOCAL_APIC) {
+                switch (boot_cpu_data.x86_vendor) {
+                case X86_VENDOR_AMD:
+                        if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
+                                return;
+                        stop_k7_watchdog();
+                        break;
+                case X86_VENDOR_INTEL:
+                        if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
+                                stop_intel_arch_watchdog();
+                                break;
+                        }
+                        stop_p4_watchdog();
+                        break;
+                default:
+                        return;
+                }
         }
-        lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
-        nmi_active = 1;
+        wd->enabled = 0;
+        atomic_dec(&nmi_active);
 }
 
 /*
@@ -526,93 +774,109 @@ void touch_nmi_watchdog (void)
         touch_softlockup_watchdog();
 }
 
-void __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
+int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 {
         int sum;
         int touched = 0;
+        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
+        u64 dummy;
+        int rc=0;
+
+        /* check for other users first */
+        if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
+                        == NOTIFY_STOP) {
+                rc = 1;
+                touched = 1;
+        }
 
         sum = read_pda(apic_timer_irqs);
         if (__get_cpu_var(nmi_touch)) {
                 __get_cpu_var(nmi_touch) = 0;
                 touched = 1;
         }
+
 #ifdef CONFIG_X86_MCE
         /* Could check oops_in_progress here too, but it's safer
            not too */
         if (atomic_read(&mce_entry) > 0)
                 touched = 1;
 #endif
+        /* if the apic timer isn't firing, this cpu isn't doing much */
         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
                 /*
                  * Ayiee, looks like this CPU is stuck ...
                  * wait a few IRQs (5 seconds) before doing the oops ...
                  */
                 local_inc(&__get_cpu_var(alert_counter));
-                if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz) {
-                        if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
-                                                        == NOTIFY_STOP) {
-                                local_set(&__get_cpu_var(alert_counter), 0);
-                                return;
-                        }
-                        die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs);
-                }
+                if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
+                        die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
+                                panic_on_timeout);
         } else {
                 __get_cpu_var(last_irq_sum) = sum;
                 local_set(&__get_cpu_var(alert_counter), 0);
         }
-        if (nmi_perfctr_msr) {
-                if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
-                        /*
-                         * P4 quirks:
-                         * - An overflown perfctr will assert its interrupt
-                         *   until the OVF flag in its CCCR is cleared.
-                         * - LVTPC is masked on interrupt and must be
-                         *   unmasked by the LVTPC handler.
-                         */
-                        wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
-                        apic_write(APIC_LVTPC, APIC_DM_NMI);
-                } else if (nmi_perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
-                        /*
-                         * For Intel based architectural perfmon
-                         * - LVTPC is masked on interrupt and must be
-                         *   unmasked by the LVTPC handler.
+
+        /* see if the nmi watchdog went off */
+        if (wd->enabled) {
+                if (nmi_watchdog == NMI_LOCAL_APIC) {
+                        rdmsrl(wd->perfctr_msr, dummy);
+                        if (dummy & wd->check_bit){
+                                /* this wasn't a watchdog timer interrupt */
+                                goto done;
+                        }
+
+                        /* only Intel uses the cccr msr */
+                        if (wd->cccr_msr != 0) {
+                                /*
+                                 * P4 quirks:
+                                 * - An overflown perfctr will assert its interrupt
+                                 *   until the OVF flag in its CCCR is cleared.
+                                 * - LVTPC is masked on interrupt and must be
+                                 *   unmasked by the LVTPC handler.
+                                 */
+                                rdmsrl(wd->cccr_msr, dummy);
+                                dummy &= ~P4_CCCR_OVF;
+                                wrmsrl(wd->cccr_msr, dummy);
+                                apic_write(APIC_LVTPC, APIC_DM_NMI);
+                        } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
+                                /*
+                                 * ArchPerfom/Core Duo needs to re-unmask
+                                 * the apic vector
+                                 */
+                                apic_write(APIC_LVTPC, APIC_DM_NMI);
+                        }
+                        /* start the cycle over again */
+                        wrmsrl(wd->perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+                        rc = 1;
+                } else  if (nmi_watchdog == NMI_IO_APIC) {
+                        /* don't know how to accurately check for this.
+                         * just assume it was a watchdog timer interrupt
+                         * This matches the old behaviour.
                          */
-                        apic_write(APIC_LVTPC, APIC_DM_NMI);
-                }
-                wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
+                        rc = 1;
+                } else
+                        printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
         }
+done:
+        return rc;
 }
 
-static __kprobes int dummy_nmi_callback(struct pt_regs * regs, int cpu)
-{
-        return 0;
-}
- 
-static nmi_callback_t nmi_callback = dummy_nmi_callback;
- 
 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 {
-        int cpu = safe_smp_processor_id();
-
         nmi_enter();
         add_pda(__nmi_count,1);
-        if (!rcu_dereference(nmi_callback)(regs, cpu))
-                default_do_nmi(regs);
+        default_do_nmi(regs);
         nmi_exit();
 }
 
-void set_nmi_callback(nmi_callback_t callback)
+int do_nmi_callback(struct pt_regs * regs, int cpu)
 {
-        vmalloc_sync_all();
-        rcu_assign_pointer(nmi_callback, callback);
-}
-EXPORT_SYMBOL_GPL(set_nmi_callback);
-
-void unset_nmi_callback(void)
-{
-        nmi_callback = dummy_nmi_callback;
+#ifdef CONFIG_SYSCTL
+        if (unknown_nmi_panic)
+                return unknown_nmi_panic_callback(regs, cpu);
+#endif
+        return 0;
 }
-EXPORT_SYMBOL_GPL(unset_nmi_callback);
 
 #ifdef CONFIG_SYSCTL
 
@@ -621,36 +885,42 @@ static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
         unsigned char reason = get_nmi_reason();
         char buf[64];
 
-        if (!(reason & 0xc0)) {
-                sprintf(buf, "NMI received for unknown reason %02x\n", reason);
-                die_nmi(buf,regs);
-        }
+        sprintf(buf, "NMI received for unknown reason %02x\n", reason);
+        die_nmi(buf, regs, 1);  /* Always panic here */
         return 0;
 }
 
 /*
- * proc handler for /proc/sys/kernel/unknown_nmi_panic
+ * proc handler for /proc/sys/kernel/nmi
  */
-int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file,
+int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
                         void __user *buffer, size_t *length, loff_t *ppos)
 {
         int old_state;
 
-        old_state = unknown_nmi_panic;
+        nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
+        old_state = nmi_watchdog_enabled;
         proc_dointvec(table, write, file, buffer, length, ppos);
-        if (!!old_state == !!unknown_nmi_panic)
+        if (!!old_state == !!nmi_watchdog_enabled)
                 return 0;
 
-        if (unknown_nmi_panic) {
-                if (reserve_lapic_nmi() < 0) {
-                        unknown_nmi_panic = 0;
-                        return -EBUSY;
-                } else {
-                        set_nmi_callback(unknown_nmi_panic_callback);
-                }
+        if (atomic_read(&nmi_active) < 0) {
+                printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
+                return -EIO;
+        }
+
+        /* if nmi_watchdog is not set yet, then set it */
+        nmi_watchdog_default();
+
+        if (nmi_watchdog == NMI_LOCAL_APIC) {
+                if (nmi_watchdog_enabled)
+                        enable_lapic_nmi_watchdog();
+                else
+                        disable_lapic_nmi_watchdog();
         } else {
-                release_lapic_nmi();
-                unset_nmi_callback();
+                printk( KERN_WARNING
+                        "NMI watchdog doesn't know what hardware to touch\n");
+                return -EIO;
         }
         return 0;
 }
@@ -659,8 +929,12 @@ int proc_unknown_nmi_panic(struct ctl_table *table, int write, struct file *file
 
 EXPORT_SYMBOL(nmi_active);
 EXPORT_SYMBOL(nmi_watchdog);
-EXPORT_SYMBOL(reserve_lapic_nmi);
-EXPORT_SYMBOL(release_lapic_nmi);
+EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
+EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
+EXPORT_SYMBOL(reserve_perfctr_nmi);
+EXPORT_SYMBOL(release_perfctr_nmi);
+EXPORT_SYMBOL(reserve_evntsel_nmi);
+EXPORT_SYMBOL(release_evntsel_nmi);
 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
 EXPORT_SYMBOL(touch_nmi_watchdog);