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-rw-r--r--arch/x86_64/kernel/mpparse.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
index b17cf3eba359..083da7e606b1 100644
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -968,7 +968,17 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
968 */ 968 */
969 int irq = gsi; 969 int irq = gsi;
970 if (gsi < MAX_GSI_NUM) { 970 if (gsi < MAX_GSI_NUM) {
971 if (gsi > 15) 971 /*
972 * Retain the VIA chipset work-around (gsi > 15), but
973 * avoid a problem where the 8254 timer (IRQ0) is setup
974 * via an override (so it's not on pin 0 of the ioapic),
975 * and at the same time, the pin 0 interrupt is a PCI
976 * type. The gsi > 15 test could cause these two pins
977 * to be shared as IRQ0, and they are not shareable.
978 * So test for this condition, and if necessary, avoid
979 * the pin collision.
980 */
981 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
972 gsi = pci_irq++; 982 gsi = pci_irq++;
973 /* 983 /*
974 * Don't assign IRQ used by ACPI SCI 984 * Don't assign IRQ used by ACPI SCI