1 files changed, 1 insertions, 41 deletions

diff --git a/arch/x86_64/kernel/mpparse.c b/arch/x86_64/kernel/mpparse.c
index b8d53dfa9931..b147ab19fbd4 100644
--- a/arch/x86_64/kernel/mpparse.c
+++ b/arch/x86_64/kernel/mpparse.c
@@ -790,20 +790,11 @@ void __init mp_config_acpi_legacy_irqs(void)
         }
 }
 
-#define MAX_GSI_NUM     4096
-
 int mp_register_gsi(u32 gsi, int triggering, int polarity)
 {
         int ioapic = -1;
         int ioapic_pin = 0;
         int idx, bit = 0;
-        static int pci_irq = 16;
-        /*
-         * Mapping between Global System Interrupts, which
-         * represent all possible interrupts, to the IRQs
-         * assigned to actual devices.
-         */
-        static int gsi_to_irq[MAX_GSI_NUM];
 
         if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
                 return gsi;
@@ -836,42 +827,11 @@ int mp_register_gsi(u32 gsi, int triggering, int polarity)
         if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
                 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
                         mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
-                return gsi_to_irq[gsi];
+                return gsi;
         }
 
         mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 
-        if (triggering == ACPI_LEVEL_SENSITIVE) {
-                /*
-                 * For PCI devices assign IRQs in order, avoiding gaps
-                 * due to unused I/O APIC pins.
-                 */
-                int irq = gsi;
-                if (gsi < MAX_GSI_NUM) {
-                        /*
-                         * Retain the VIA chipset work-around (gsi > 15), but
-                         * avoid a problem where the 8254 timer (IRQ0) is setup
-                         * via an override (so it's not on pin 0 of the ioapic),
-                         * and at the same time, the pin 0 interrupt is a PCI
-                         * type.  The gsi > 15 test could cause these two pins
-                         * to be shared as IRQ0, and they are not shareable.
-                         * So test for this condition, and if necessary, avoid
-                         * the pin collision.
-                         */
-                        if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
-                                gsi = pci_irq++;
-                        /*
-                         * Don't assign IRQ used by ACPI SCI
-                         */
-                        if (gsi == acpi_fadt.sci_int)
-                                gsi = pci_irq++;
-                        gsi_to_irq[irq] = gsi;
-                } else {
-                        printk(KERN_ERR "GSI %u is too high\n", gsi);
-                        return gsi;
-                }
-        }
-
         io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
                 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
                 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);