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Diffstat (limited to 'arch/x86_64/kernel/apic.c')
-rw-r--r--arch/x86_64/kernel/apic.c42
1 files changed, 5 insertions, 37 deletions
diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
index 375d369570ca..b6e7715d877f 100644
--- a/arch/x86_64/kernel/apic.c
+++ b/arch/x86_64/kernel/apic.c
@@ -18,7 +18,6 @@
18#include <linux/init.h> 18#include <linux/init.h>
19 19
20#include <linux/mm.h> 20#include <linux/mm.h>
21#include <linux/irq.h>
22#include <linux/delay.h> 21#include <linux/delay.h>
23#include <linux/bootmem.h> 22#include <linux/bootmem.h>
24#include <linux/smp_lock.h> 23#include <linux/smp_lock.h>
@@ -109,11 +108,8 @@ void clear_local_APIC(void)
109 if (maxlvt >= 4) 108 if (maxlvt >= 4)
110 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); 109 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
111 v = GET_APIC_VERSION(apic_read(APIC_LVR)); 110 v = GET_APIC_VERSION(apic_read(APIC_LVR));
112 if (APIC_INTEGRATED(v)) { /* !82489DX */ 111 apic_write(APIC_ESR, 0);
113 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */ 112 apic_read(APIC_ESR);
114 apic_write(APIC_ESR, 0);
115 apic_read(APIC_ESR);
116 }
117} 113}
118 114
119void __init connect_bsp_APIC(void) 115void __init connect_bsp_APIC(void)
@@ -316,8 +312,6 @@ void __init init_bsp_APIC(void)
316 */ 312 */
317 apic_write_around(APIC_LVT0, APIC_DM_EXTINT); 313 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
318 value = APIC_DM_NMI; 314 value = APIC_DM_NMI;
319 if (!APIC_INTEGRATED(ver)) /* 82489DX */
320 value |= APIC_LVT_LEVEL_TRIGGER;
321 apic_write_around(APIC_LVT1, value); 315 apic_write_around(APIC_LVT1, value);
322} 316}
323 317
@@ -325,14 +319,6 @@ void __cpuinit setup_local_APIC (void)
325{ 319{
326 unsigned int value, ver, maxlvt; 320 unsigned int value, ver, maxlvt;
327 321
328 /* Pound the ESR really hard over the head with a big hammer - mbligh */
329 if (esr_disable) {
330 apic_write(APIC_ESR, 0);
331 apic_write(APIC_ESR, 0);
332 apic_write(APIC_ESR, 0);
333 apic_write(APIC_ESR, 0);
334 }
335
336 value = apic_read(APIC_LVR); 322 value = apic_read(APIC_LVR);
337 ver = GET_APIC_VERSION(value); 323 ver = GET_APIC_VERSION(value);
338 324
@@ -430,15 +416,11 @@ void __cpuinit setup_local_APIC (void)
430 value = APIC_DM_NMI; 416 value = APIC_DM_NMI;
431 else 417 else
432 value = APIC_DM_NMI | APIC_LVT_MASKED; 418 value = APIC_DM_NMI | APIC_LVT_MASKED;
433 if (!APIC_INTEGRATED(ver)) /* 82489DX */
434 value |= APIC_LVT_LEVEL_TRIGGER;
435 apic_write_around(APIC_LVT1, value); 419 apic_write_around(APIC_LVT1, value);
436 420
437 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */ 421 {
438 unsigned oldvalue; 422 unsigned oldvalue;
439 maxlvt = get_maxlvt(); 423 maxlvt = get_maxlvt();
440 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
441 apic_write(APIC_ESR, 0);
442 oldvalue = apic_read(APIC_ESR); 424 oldvalue = apic_read(APIC_ESR);
443 value = ERROR_APIC_VECTOR; // enables sending errors 425 value = ERROR_APIC_VECTOR; // enables sending errors
444 apic_write_around(APIC_LVTERR, value); 426 apic_write_around(APIC_LVTERR, value);
@@ -452,17 +434,6 @@ void __cpuinit setup_local_APIC (void)
452 apic_printk(APIC_VERBOSE, 434 apic_printk(APIC_VERBOSE,
453 "ESR value after enabling vector: %08x, after %08x\n", 435 "ESR value after enabling vector: %08x, after %08x\n",
454 oldvalue, value); 436 oldvalue, value);
455 } else {
456 if (esr_disable)
457 /*
458 * Something untraceble is creating bad interrupts on
459 * secondary quads ... for the moment, just leave the
460 * ESR disabled - we can't do anything useful with the
461 * errors anyway - mbligh
462 */
463 apic_printk(APIC_DEBUG, "Leaving ESR disabled.\n");
464 else
465 apic_printk(APIC_DEBUG, "No ESR for 82489DX.\n");
466 } 437 }
467 438
468 nmi_watchdog_default(); 439 nmi_watchdog_default();
@@ -650,8 +621,7 @@ void __init init_apic_mappings(void)
650 * Fetch the APIC ID of the BSP in case we have a 621 * Fetch the APIC ID of the BSP in case we have a
651 * default configuration (or the MP table is broken). 622 * default configuration (or the MP table is broken).
652 */ 623 */
653 if (boot_cpu_id == -1U) 624 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
654 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
655 625
656#ifdef CONFIG_X86_IO_APIC 626#ifdef CONFIG_X86_IO_APIC
657 { 627 {
@@ -693,8 +663,6 @@ static void __setup_APIC_LVTT(unsigned int clocks)
693 663
694 ver = GET_APIC_VERSION(apic_read(APIC_LVR)); 664 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
695 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR; 665 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
696 if (!APIC_INTEGRATED(ver))
697 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
698 apic_write_around(APIC_LVTT, lvtt_value); 666 apic_write_around(APIC_LVTT, lvtt_value);
699 667
700 /* 668 /*
@@ -1081,7 +1049,7 @@ int __init APIC_init_uniprocessor (void)
1081 1049
1082 connect_bsp_APIC(); 1050 connect_bsp_APIC();
1083 1051
1084 phys_cpu_present_map = physid_mask_of_physid(0); 1052 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
1085 apic_write_around(APIC_ID, boot_cpu_id); 1053 apic_write_around(APIC_ID, boot_cpu_id);
1086 1054
1087 setup_local_APIC(); 1055 setup_local_APIC();