diff options
Diffstat (limited to 'arch/x86')
66 files changed, 3064 insertions, 956 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f5cef3fbf9a5..7fcf85182681 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig | |||
@@ -783,6 +783,11 @@ config X86_MCE_AMD | |||
783 | Additional support for AMD specific MCE features such as | 783 | Additional support for AMD specific MCE features such as |
784 | the DRAM Error Threshold. | 784 | the DRAM Error Threshold. |
785 | 785 | ||
786 | config X86_MCE_THRESHOLD | ||
787 | depends on X86_MCE_AMD || X86_MCE_INTEL | ||
788 | bool | ||
789 | default y | ||
790 | |||
786 | config X86_MCE_NONFATAL | 791 | config X86_MCE_NONFATAL |
787 | tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4" | 792 | tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4" |
788 | depends on X86_32 && X86_MCE | 793 | depends on X86_32 && X86_MCE |
@@ -926,6 +931,12 @@ config X86_CPUID | |||
926 | with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to | 931 | with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to |
927 | /dev/cpu/31/cpuid. | 932 | /dev/cpu/31/cpuid. |
928 | 933 | ||
934 | config X86_CPU_DEBUG | ||
935 | tristate "/sys/kernel/debug/x86/cpu/* - CPU Debug support" | ||
936 | ---help--- | ||
937 | If you select this option, this will provide various x86 CPUs | ||
938 | information through debugfs. | ||
939 | |||
929 | choice | 940 | choice |
930 | prompt "High Memory Support" | 941 | prompt "High Memory Support" |
931 | default HIGHMEM4G if !X86_NUMAQ | 942 | default HIGHMEM4G if !X86_NUMAQ |
@@ -1426,7 +1437,7 @@ config CRASH_DUMP | |||
1426 | config KEXEC_JUMP | 1437 | config KEXEC_JUMP |
1427 | bool "kexec jump (EXPERIMENTAL)" | 1438 | bool "kexec jump (EXPERIMENTAL)" |
1428 | depends on EXPERIMENTAL | 1439 | depends on EXPERIMENTAL |
1429 | depends on KEXEC && HIBERNATION && X86_32 | 1440 | depends on KEXEC && HIBERNATION |
1430 | ---help--- | 1441 | ---help--- |
1431 | Jump between original kernel and kexeced kernel and invoke | 1442 | Jump between original kernel and kexeced kernel and invoke |
1432 | code in physical address mode via KEXEC | 1443 | code in physical address mode via KEXEC |
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile index c70eff69a1fb..57a29fecf6bb 100644 --- a/arch/x86/boot/Makefile +++ b/arch/x86/boot/Makefile | |||
@@ -6,26 +6,23 @@ | |||
6 | # for more details. | 6 | # for more details. |
7 | # | 7 | # |
8 | # Copyright (C) 1994 by Linus Torvalds | 8 | # Copyright (C) 1994 by Linus Torvalds |
9 | # Changed by many, many contributors over the years. | ||
9 | # | 10 | # |
10 | 11 | ||
11 | # ROOT_DEV specifies the default root-device when making the image. | 12 | # ROOT_DEV specifies the default root-device when making the image. |
12 | # This can be either FLOPPY, CURRENT, /dev/xxxx or empty, in which case | 13 | # This can be either FLOPPY, CURRENT, /dev/xxxx or empty, in which case |
13 | # the default of FLOPPY is used by 'build'. | 14 | # the default of FLOPPY is used by 'build'. |
14 | 15 | ||
15 | ROOT_DEV := CURRENT | 16 | ROOT_DEV := CURRENT |
16 | 17 | ||
17 | # If you want to preset the SVGA mode, uncomment the next line and | 18 | # If you want to preset the SVGA mode, uncomment the next line and |
18 | # set SVGA_MODE to whatever number you want. | 19 | # set SVGA_MODE to whatever number you want. |
19 | # Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode. | 20 | # Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode. |
20 | # The number is the same as you would ordinarily press at bootup. | 21 | # The number is the same as you would ordinarily press at bootup. |
21 | 22 | ||
22 | SVGA_MODE := -DSVGA_MODE=NORMAL_VGA | 23 | SVGA_MODE := -DSVGA_MODE=NORMAL_VGA |
23 | 24 | ||
24 | # If you want the RAM disk device, define this to be the size in blocks. | 25 | targets := vmlinux.bin setup.bin setup.elf bzImage |
25 | |||
26 | #RAMDISK := -DRAMDISK=512 | ||
27 | |||
28 | targets := vmlinux.bin setup.bin setup.elf zImage bzImage | ||
29 | subdir- := compressed | 26 | subdir- := compressed |
30 | 27 | ||
31 | setup-y += a20.o cmdline.o copy.o cpu.o cpucheck.o edd.o | 28 | setup-y += a20.o cmdline.o copy.o cpu.o cpucheck.o edd.o |
@@ -71,17 +68,13 @@ KBUILD_CFLAGS := $(LINUXINCLUDE) -g -Os -D_SETUP -D__KERNEL__ \ | |||
71 | KBUILD_CFLAGS += $(call cc-option,-m32) | 68 | KBUILD_CFLAGS += $(call cc-option,-m32) |
72 | KBUILD_AFLAGS := $(KBUILD_CFLAGS) -D__ASSEMBLY__ | 69 | KBUILD_AFLAGS := $(KBUILD_CFLAGS) -D__ASSEMBLY__ |
73 | 70 | ||
74 | $(obj)/zImage: asflags-y := $(SVGA_MODE) $(RAMDISK) | 71 | $(obj)/bzImage: asflags-y := $(SVGA_MODE) |
75 | $(obj)/bzImage: ccflags-y := -D__BIG_KERNEL__ | ||
76 | $(obj)/bzImage: asflags-y := $(SVGA_MODE) $(RAMDISK) -D__BIG_KERNEL__ | ||
77 | $(obj)/bzImage: BUILDFLAGS := -b | ||
78 | 72 | ||
79 | quiet_cmd_image = BUILD $@ | 73 | quiet_cmd_image = BUILD $@ |
80 | cmd_image = $(obj)/tools/build $(BUILDFLAGS) $(obj)/setup.bin \ | 74 | cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin \ |
81 | $(obj)/vmlinux.bin $(ROOT_DEV) > $@ | 75 | $(ROOT_DEV) > $@ |
82 | 76 | ||
83 | $(obj)/zImage $(obj)/bzImage: $(obj)/setup.bin \ | 77 | $(obj)/bzImage: $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/tools/build FORCE |
84 | $(obj)/vmlinux.bin $(obj)/tools/build FORCE | ||
85 | $(call if_changed,image) | 78 | $(call if_changed,image) |
86 | @echo 'Kernel: $@ is ready' ' (#'`cat .version`')' | 79 | @echo 'Kernel: $@ is ready' ' (#'`cat .version`')' |
87 | 80 | ||
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S index 7ccff4884a23..5d84d1c74e4c 100644 --- a/arch/x86/boot/header.S +++ b/arch/x86/boot/header.S | |||
@@ -24,12 +24,8 @@ | |||
24 | #include "boot.h" | 24 | #include "boot.h" |
25 | #include "offsets.h" | 25 | #include "offsets.h" |
26 | 26 | ||
27 | SETUPSECTS = 4 /* default nr of setup-sectors */ | ||
28 | BOOTSEG = 0x07C0 /* original address of boot-sector */ | 27 | BOOTSEG = 0x07C0 /* original address of boot-sector */ |
29 | SYSSEG = DEF_SYSSEG /* system loaded at 0x10000 (65536) */ | 28 | SYSSEG = 0x1000 /* historical load address >> 4 */ |
30 | SYSSIZE = DEF_SYSSIZE /* system size: # of 16-byte clicks */ | ||
31 | /* to be loaded */ | ||
32 | ROOT_DEV = 0 /* ROOT_DEV is now written by "build" */ | ||
33 | 29 | ||
34 | #ifndef SVGA_MODE | 30 | #ifndef SVGA_MODE |
35 | #define SVGA_MODE ASK_VGA | 31 | #define SVGA_MODE ASK_VGA |
@@ -97,12 +93,12 @@ bugger_off_msg: | |||
97 | .section ".header", "a" | 93 | .section ".header", "a" |
98 | .globl hdr | 94 | .globl hdr |
99 | hdr: | 95 | hdr: |
100 | setup_sects: .byte SETUPSECTS | 96 | setup_sects: .byte 0 /* Filled in by build.c */ |
101 | root_flags: .word ROOT_RDONLY | 97 | root_flags: .word ROOT_RDONLY |
102 | syssize: .long SYSSIZE | 98 | syssize: .long 0 /* Filled in by build.c */ |
103 | ram_size: .word RAMDISK | 99 | ram_size: .word 0 /* Obsolete */ |
104 | vid_mode: .word SVGA_MODE | 100 | vid_mode: .word SVGA_MODE |
105 | root_dev: .word ROOT_DEV | 101 | root_dev: .word 0 /* Filled in by build.c */ |
106 | boot_flag: .word 0xAA55 | 102 | boot_flag: .word 0xAA55 |
107 | 103 | ||
108 | # offset 512, entry point | 104 | # offset 512, entry point |
@@ -123,14 +119,15 @@ _start: | |||
123 | # or else old loadlin-1.5 will fail) | 119 | # or else old loadlin-1.5 will fail) |
124 | .globl realmode_swtch | 120 | .globl realmode_swtch |
125 | realmode_swtch: .word 0, 0 # default_switch, SETUPSEG | 121 | realmode_swtch: .word 0, 0 # default_switch, SETUPSEG |
126 | start_sys_seg: .word SYSSEG | 122 | start_sys_seg: .word SYSSEG # obsolete and meaningless, but just |
123 | # in case something decided to "use" it | ||
127 | .word kernel_version-512 # pointing to kernel version string | 124 | .word kernel_version-512 # pointing to kernel version string |
128 | # above section of header is compatible | 125 | # above section of header is compatible |
129 | # with loadlin-1.5 (header v1.5). Don't | 126 | # with loadlin-1.5 (header v1.5). Don't |
130 | # change it. | 127 | # change it. |
131 | 128 | ||
132 | type_of_loader: .byte 0 # = 0, old one (LILO, Loadlin, | 129 | type_of_loader: .byte 0 # 0 means ancient bootloader, newer |
133 | # Bootlin, SYSLX, bootsect...) | 130 | # bootloaders know to change this. |
134 | # See Documentation/i386/boot.txt for | 131 | # See Documentation/i386/boot.txt for |
135 | # assigned ids | 132 | # assigned ids |
136 | 133 | ||
@@ -142,11 +139,7 @@ CAN_USE_HEAP = 0x80 # If set, the loader also has set | |||
142 | # space behind setup.S can be used for | 139 | # space behind setup.S can be used for |
143 | # heap purposes. | 140 | # heap purposes. |
144 | # Only the loader knows what is free | 141 | # Only the loader knows what is free |
145 | #ifndef __BIG_KERNEL__ | ||
146 | .byte 0 | ||
147 | #else | ||
148 | .byte LOADED_HIGH | 142 | .byte LOADED_HIGH |
149 | #endif | ||
150 | 143 | ||
151 | setup_move_size: .word 0x8000 # size to move, when setup is not | 144 | setup_move_size: .word 0x8000 # size to move, when setup is not |
152 | # loaded at 0x90000. We will move setup | 145 | # loaded at 0x90000. We will move setup |
@@ -157,11 +150,7 @@ setup_move_size: .word 0x8000 # size to move, when setup is not | |||
157 | 150 | ||
158 | code32_start: # here loaders can put a different | 151 | code32_start: # here loaders can put a different |
159 | # start address for 32-bit code. | 152 | # start address for 32-bit code. |
160 | #ifndef __BIG_KERNEL__ | ||
161 | .long 0x1000 # 0x1000 = default for zImage | ||
162 | #else | ||
163 | .long 0x100000 # 0x100000 = default for big kernel | 153 | .long 0x100000 # 0x100000 = default for big kernel |
164 | #endif | ||
165 | 154 | ||
166 | ramdisk_image: .long 0 # address of loaded ramdisk image | 155 | ramdisk_image: .long 0 # address of loaded ramdisk image |
167 | # Here the loader puts the 32-bit | 156 | # Here the loader puts the 32-bit |
diff --git a/arch/x86/boot/pm.c b/arch/x86/boot/pm.c index 85a1cd8a8ff8..8062f8915250 100644 --- a/arch/x86/boot/pm.c +++ b/arch/x86/boot/pm.c | |||
@@ -33,47 +33,6 @@ static void realmode_switch_hook(void) | |||
33 | } | 33 | } |
34 | 34 | ||
35 | /* | 35 | /* |
36 | * A zImage kernel is loaded at 0x10000 but wants to run at 0x1000. | ||
37 | * A bzImage kernel is loaded and runs at 0x100000. | ||
38 | */ | ||
39 | static void move_kernel_around(void) | ||
40 | { | ||
41 | /* Note: rely on the compile-time option here rather than | ||
42 | the LOADED_HIGH flag. The Qemu kernel loader unconditionally | ||
43 | sets the loadflags to zero. */ | ||
44 | #ifndef __BIG_KERNEL__ | ||
45 | u16 dst_seg, src_seg; | ||
46 | u32 syssize; | ||
47 | |||
48 | dst_seg = 0x1000 >> 4; | ||
49 | src_seg = 0x10000 >> 4; | ||
50 | syssize = boot_params.hdr.syssize; /* Size in 16-byte paragraphs */ | ||
51 | |||
52 | while (syssize) { | ||
53 | int paras = (syssize >= 0x1000) ? 0x1000 : syssize; | ||
54 | int dwords = paras << 2; | ||
55 | |||
56 | asm volatile("pushw %%es ; " | ||
57 | "pushw %%ds ; " | ||
58 | "movw %1,%%es ; " | ||
59 | "movw %2,%%ds ; " | ||
60 | "xorw %%di,%%di ; " | ||
61 | "xorw %%si,%%si ; " | ||
62 | "rep;movsl ; " | ||
63 | "popw %%ds ; " | ||
64 | "popw %%es" | ||
65 | : "+c" (dwords) | ||
66 | : "r" (dst_seg), "r" (src_seg) | ||
67 | : "esi", "edi"); | ||
68 | |||
69 | syssize -= paras; | ||
70 | dst_seg += paras; | ||
71 | src_seg += paras; | ||
72 | } | ||
73 | #endif | ||
74 | } | ||
75 | |||
76 | /* | ||
77 | * Disable all interrupts at the legacy PIC. | 36 | * Disable all interrupts at the legacy PIC. |
78 | */ | 37 | */ |
79 | static void mask_all_interrupts(void) | 38 | static void mask_all_interrupts(void) |
@@ -147,9 +106,6 @@ void go_to_protected_mode(void) | |||
147 | /* Hook before leaving real mode, also disables interrupts */ | 106 | /* Hook before leaving real mode, also disables interrupts */ |
148 | realmode_switch_hook(); | 107 | realmode_switch_hook(); |
149 | 108 | ||
150 | /* Move the kernel/setup to their final resting places */ | ||
151 | move_kernel_around(); | ||
152 | |||
153 | /* Enable the A20 gate */ | 109 | /* Enable the A20 gate */ |
154 | if (enable_a20()) { | 110 | if (enable_a20()) { |
155 | puts("A20 gate not responding, unable to boot...\n"); | 111 | puts("A20 gate not responding, unable to boot...\n"); |
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c index 44dc1923c0e3..ee3a4ea923ac 100644 --- a/arch/x86/boot/tools/build.c +++ b/arch/x86/boot/tools/build.c | |||
@@ -130,7 +130,7 @@ static void die(const char * str, ...) | |||
130 | 130 | ||
131 | static void usage(void) | 131 | static void usage(void) |
132 | { | 132 | { |
133 | die("Usage: build [-b] setup system [rootdev] [> image]"); | 133 | die("Usage: build setup system [rootdev] [> image]"); |
134 | } | 134 | } |
135 | 135 | ||
136 | int main(int argc, char ** argv) | 136 | int main(int argc, char ** argv) |
@@ -145,11 +145,6 @@ int main(int argc, char ** argv) | |||
145 | void *kernel; | 145 | void *kernel; |
146 | u32 crc = 0xffffffffUL; | 146 | u32 crc = 0xffffffffUL; |
147 | 147 | ||
148 | if (argc > 2 && !strcmp(argv[1], "-b")) | ||
149 | { | ||
150 | is_big_kernel = 1; | ||
151 | argc--, argv++; | ||
152 | } | ||
153 | if ((argc < 3) || (argc > 4)) | 148 | if ((argc < 3) || (argc > 4)) |
154 | usage(); | 149 | usage(); |
155 | if (argc > 3) { | 150 | if (argc > 3) { |
@@ -216,8 +211,6 @@ int main(int argc, char ** argv) | |||
216 | die("Unable to mmap '%s': %m", argv[2]); | 211 | die("Unable to mmap '%s': %m", argv[2]); |
217 | /* Number of 16-byte paragraphs, including space for a 4-byte CRC */ | 212 | /* Number of 16-byte paragraphs, including space for a 4-byte CRC */ |
218 | sys_size = (sz + 15 + 4) / 16; | 213 | sys_size = (sz + 15 + 4) / 16; |
219 | if (!is_big_kernel && sys_size > DEF_SYSSIZE) | ||
220 | die("System is too big. Try using bzImage or modules."); | ||
221 | 214 | ||
222 | /* Patch the setup code with the appropriate size parameters */ | 215 | /* Patch the setup code with the appropriate size parameters */ |
223 | buf[0x1f1] = setup_sectors-1; | 216 | buf[0x1f1] = setup_sectors-1; |
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 4ef949c1972e..394d177d721b 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h | |||
@@ -379,6 +379,7 @@ static inline u32 safe_apic_wait_icr_idle(void) | |||
379 | 379 | ||
380 | static inline void ack_APIC_irq(void) | 380 | static inline void ack_APIC_irq(void) |
381 | { | 381 | { |
382 | #ifdef CONFIG_X86_LOCAL_APIC | ||
382 | /* | 383 | /* |
383 | * ack_APIC_irq() actually gets compiled as a single instruction | 384 | * ack_APIC_irq() actually gets compiled as a single instruction |
384 | * ... yummie. | 385 | * ... yummie. |
@@ -386,6 +387,7 @@ static inline void ack_APIC_irq(void) | |||
386 | 387 | ||
387 | /* Docs say use 0 for future compatibility */ | 388 | /* Docs say use 0 for future compatibility */ |
388 | apic_write(APIC_EOI, 0); | 389 | apic_write(APIC_EOI, 0); |
390 | #endif | ||
389 | } | 391 | } |
390 | 392 | ||
391 | static inline unsigned default_get_apic_id(unsigned long x) | 393 | static inline unsigned default_get_apic_id(unsigned long x) |
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index 63134e31e8b9..bc9514fb3b13 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h | |||
@@ -53,6 +53,7 @@ | |||
53 | #define APIC_ESR_SENDILL 0x00020 | 53 | #define APIC_ESR_SENDILL 0x00020 |
54 | #define APIC_ESR_RECVILL 0x00040 | 54 | #define APIC_ESR_RECVILL 0x00040 |
55 | #define APIC_ESR_ILLREGA 0x00080 | 55 | #define APIC_ESR_ILLREGA 0x00080 |
56 | #define APIC_LVTCMCI 0x2f0 | ||
56 | #define APIC_ICR 0x300 | 57 | #define APIC_ICR 0x300 |
57 | #define APIC_DEST_SELF 0x40000 | 58 | #define APIC_DEST_SELF 0x40000 |
58 | #define APIC_DEST_ALLINC 0x80000 | 59 | #define APIC_DEST_ALLINC 0x80000 |
diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h index 6526cf08b0e4..6ba23dd9fc92 100644 --- a/arch/x86/include/asm/boot.h +++ b/arch/x86/include/asm/boot.h | |||
@@ -1,10 +1,6 @@ | |||
1 | #ifndef _ASM_X86_BOOT_H | 1 | #ifndef _ASM_X86_BOOT_H |
2 | #define _ASM_X86_BOOT_H | 2 | #define _ASM_X86_BOOT_H |
3 | 3 | ||
4 | /* Don't touch these, unless you really know what you're doing. */ | ||
5 | #define DEF_SYSSEG 0x1000 | ||
6 | #define DEF_SYSSIZE 0x7F00 | ||
7 | |||
8 | /* Internal svga startup constants */ | 4 | /* Internal svga startup constants */ |
9 | #define NORMAL_VGA 0xffff /* 80x25 mode */ | 5 | #define NORMAL_VGA 0xffff /* 80x25 mode */ |
10 | #define EXTENDED_VGA 0xfffe /* 80x50 mode */ | 6 | #define EXTENDED_VGA 0xfffe /* 80x50 mode */ |
diff --git a/arch/x86/include/asm/cpu_debug.h b/arch/x86/include/asm/cpu_debug.h new file mode 100755 index 000000000000..d24d64fcee04 --- /dev/null +++ b/arch/x86/include/asm/cpu_debug.h | |||
@@ -0,0 +1,193 @@ | |||
1 | #ifndef _ASM_X86_CPU_DEBUG_H | ||
2 | #define _ASM_X86_CPU_DEBUG_H | ||
3 | |||
4 | /* | ||
5 | * CPU x86 architecture debug | ||
6 | * | ||
7 | * Copyright(C) 2009 Jaswinder Singh Rajput | ||
8 | */ | ||
9 | |||
10 | /* Register flags */ | ||
11 | enum cpu_debug_bit { | ||
12 | /* Model Specific Registers (MSRs) */ | ||
13 | CPU_MC_BIT, /* Machine Check */ | ||
14 | CPU_MONITOR_BIT, /* Monitor */ | ||
15 | CPU_TIME_BIT, /* Time */ | ||
16 | CPU_PMC_BIT, /* Performance Monitor */ | ||
17 | CPU_PLATFORM_BIT, /* Platform */ | ||
18 | CPU_APIC_BIT, /* APIC */ | ||
19 | CPU_POWERON_BIT, /* Power-on */ | ||
20 | CPU_CONTROL_BIT, /* Control */ | ||
21 | CPU_FEATURES_BIT, /* Features control */ | ||
22 | CPU_LBRANCH_BIT, /* Last Branch */ | ||
23 | CPU_BIOS_BIT, /* BIOS */ | ||
24 | CPU_FREQ_BIT, /* Frequency */ | ||
25 | CPU_MTTR_BIT, /* MTRR */ | ||
26 | CPU_PERF_BIT, /* Performance */ | ||
27 | CPU_CACHE_BIT, /* Cache */ | ||
28 | CPU_SYSENTER_BIT, /* Sysenter */ | ||
29 | CPU_THERM_BIT, /* Thermal */ | ||
30 | CPU_MISC_BIT, /* Miscellaneous */ | ||
31 | CPU_DEBUG_BIT, /* Debug */ | ||
32 | CPU_PAT_BIT, /* PAT */ | ||
33 | CPU_VMX_BIT, /* VMX */ | ||
34 | CPU_CALL_BIT, /* System Call */ | ||
35 | CPU_BASE_BIT, /* BASE Address */ | ||
36 | CPU_SMM_BIT, /* System mgmt mode */ | ||
37 | CPU_SVM_BIT, /*Secure Virtual Machine*/ | ||
38 | CPU_OSVM_BIT, /* OS-Visible Workaround*/ | ||
39 | /* Standard Registers */ | ||
40 | CPU_TSS_BIT, /* Task Stack Segment */ | ||
41 | CPU_CR_BIT, /* Control Registers */ | ||
42 | CPU_DT_BIT, /* Descriptor Table */ | ||
43 | /* End of Registers flags */ | ||
44 | CPU_REG_ALL_BIT, /* Select all Registers */ | ||
45 | }; | ||
46 | |||
47 | #define CPU_REG_ALL (~0) /* Select all Registers */ | ||
48 | |||
49 | #define CPU_MC (1 << CPU_MC_BIT) | ||
50 | #define CPU_MONITOR (1 << CPU_MONITOR_BIT) | ||
51 | #define CPU_TIME (1 << CPU_TIME_BIT) | ||
52 | #define CPU_PMC (1 << CPU_PMC_BIT) | ||
53 | #define CPU_PLATFORM (1 << CPU_PLATFORM_BIT) | ||
54 | #define CPU_APIC (1 << CPU_APIC_BIT) | ||
55 | #define CPU_POWERON (1 << CPU_POWERON_BIT) | ||
56 | #define CPU_CONTROL (1 << CPU_CONTROL_BIT) | ||
57 | #define CPU_FEATURES (1 << CPU_FEATURES_BIT) | ||
58 | #define CPU_LBRANCH (1 << CPU_LBRANCH_BIT) | ||
59 | #define CPU_BIOS (1 << CPU_BIOS_BIT) | ||
60 | #define CPU_FREQ (1 << CPU_FREQ_BIT) | ||
61 | #define CPU_MTRR (1 << CPU_MTTR_BIT) | ||
62 | #define CPU_PERF (1 << CPU_PERF_BIT) | ||
63 | #define CPU_CACHE (1 << CPU_CACHE_BIT) | ||
64 | #define CPU_SYSENTER (1 << CPU_SYSENTER_BIT) | ||
65 | #define CPU_THERM (1 << CPU_THERM_BIT) | ||
66 | #define CPU_MISC (1 << CPU_MISC_BIT) | ||
67 | #define CPU_DEBUG (1 << CPU_DEBUG_BIT) | ||
68 | #define CPU_PAT (1 << CPU_PAT_BIT) | ||
69 | #define CPU_VMX (1 << CPU_VMX_BIT) | ||
70 | #define CPU_CALL (1 << CPU_CALL_BIT) | ||
71 | #define CPU_BASE (1 << CPU_BASE_BIT) | ||
72 | #define CPU_SMM (1 << CPU_SMM_BIT) | ||
73 | #define CPU_SVM (1 << CPU_SVM_BIT) | ||
74 | #define CPU_OSVM (1 << CPU_OSVM_BIT) | ||
75 | #define CPU_TSS (1 << CPU_TSS_BIT) | ||
76 | #define CPU_CR (1 << CPU_CR_BIT) | ||
77 | #define CPU_DT (1 << CPU_DT_BIT) | ||
78 | |||
79 | /* Register file flags */ | ||
80 | enum cpu_file_bit { | ||
81 | CPU_INDEX_BIT, /* index */ | ||
82 | CPU_VALUE_BIT, /* value */ | ||
83 | }; | ||
84 | |||
85 | #define CPU_FILE_VALUE (1 << CPU_VALUE_BIT) | ||
86 | |||
87 | /* | ||
88 | * DisplayFamily_DisplayModel Processor Families/Processor Number Series | ||
89 | * -------------------------- ------------------------------------------ | ||
90 | * 05_01, 05_02, 05_04 Pentium, Pentium with MMX | ||
91 | * | ||
92 | * 06_01 Pentium Pro | ||
93 | * 06_03, 06_05 Pentium II Xeon, Pentium II | ||
94 | * 06_07, 06_08, 06_0A, 06_0B Pentium III Xeon, Pentum III | ||
95 | * | ||
96 | * 06_09, 060D Pentium M | ||
97 | * | ||
98 | * 06_0E Core Duo, Core Solo | ||
99 | * | ||
100 | * 06_0F Xeon 3000, 3200, 5100, 5300, 7300 series, | ||
101 | * Core 2 Quad, Core 2 Extreme, Core 2 Duo, | ||
102 | * Pentium dual-core | ||
103 | * 06_17 Xeon 5200, 5400 series, Core 2 Quad Q9650 | ||
104 | * | ||
105 | * 06_1C Atom | ||
106 | * | ||
107 | * 0F_00, 0F_01, 0F_02 Xeon, Xeon MP, Pentium 4 | ||
108 | * 0F_03, 0F_04 Xeon, Xeon MP, Pentium 4, Pentium D | ||
109 | * | ||
110 | * 0F_06 Xeon 7100, 5000 Series, Xeon MP, | ||
111 | * Pentium 4, Pentium D | ||
112 | */ | ||
113 | |||
114 | /* Register processors bits */ | ||
115 | enum cpu_processor_bit { | ||
116 | CPU_NONE, | ||
117 | /* Intel */ | ||
118 | CPU_INTEL_PENTIUM_BIT, | ||
119 | CPU_INTEL_P6_BIT, | ||
120 | CPU_INTEL_PENTIUM_M_BIT, | ||
121 | CPU_INTEL_CORE_BIT, | ||
122 | CPU_INTEL_CORE2_BIT, | ||
123 | CPU_INTEL_ATOM_BIT, | ||
124 | CPU_INTEL_XEON_P4_BIT, | ||
125 | CPU_INTEL_XEON_MP_BIT, | ||
126 | }; | ||
127 | |||
128 | #define CPU_ALL (~0) /* Select all CPUs */ | ||
129 | |||
130 | #define CPU_INTEL_PENTIUM (1 << CPU_INTEL_PENTIUM_BIT) | ||
131 | #define CPU_INTEL_P6 (1 << CPU_INTEL_P6_BIT) | ||
132 | #define CPU_INTEL_PENTIUM_M (1 << CPU_INTEL_PENTIUM_M_BIT) | ||
133 | #define CPU_INTEL_CORE (1 << CPU_INTEL_CORE_BIT) | ||
134 | #define CPU_INTEL_CORE2 (1 << CPU_INTEL_CORE2_BIT) | ||
135 | #define CPU_INTEL_ATOM (1 << CPU_INTEL_ATOM_BIT) | ||
136 | #define CPU_INTEL_XEON_P4 (1 << CPU_INTEL_XEON_P4_BIT) | ||
137 | #define CPU_INTEL_XEON_MP (1 << CPU_INTEL_XEON_MP_BIT) | ||
138 | |||
139 | #define CPU_INTEL_PX (CPU_INTEL_P6 | CPU_INTEL_PENTIUM_M) | ||
140 | #define CPU_INTEL_COREX (CPU_INTEL_CORE | CPU_INTEL_CORE2) | ||
141 | #define CPU_INTEL_XEON (CPU_INTEL_XEON_P4 | CPU_INTEL_XEON_MP) | ||
142 | #define CPU_CO_AT (CPU_INTEL_CORE | CPU_INTEL_ATOM) | ||
143 | #define CPU_C2_AT (CPU_INTEL_CORE2 | CPU_INTEL_ATOM) | ||
144 | #define CPU_CX_AT (CPU_INTEL_COREX | CPU_INTEL_ATOM) | ||
145 | #define CPU_CX_XE (CPU_INTEL_COREX | CPU_INTEL_XEON) | ||
146 | #define CPU_P6_XE (CPU_INTEL_P6 | CPU_INTEL_XEON) | ||
147 | #define CPU_PM_CO_AT (CPU_INTEL_PENTIUM_M | CPU_CO_AT) | ||
148 | #define CPU_C2_AT_XE (CPU_C2_AT | CPU_INTEL_XEON) | ||
149 | #define CPU_CX_AT_XE (CPU_CX_AT | CPU_INTEL_XEON) | ||
150 | #define CPU_P6_CX_AT (CPU_INTEL_P6 | CPU_CX_AT) | ||
151 | #define CPU_P6_CX_XE (CPU_P6_XE | CPU_INTEL_COREX) | ||
152 | #define CPU_P6_CX_AT_XE (CPU_INTEL_P6 | CPU_CX_AT_XE) | ||
153 | #define CPU_PM_CX_AT_XE (CPU_INTEL_PENTIUM_M | CPU_CX_AT_XE) | ||
154 | #define CPU_PM_CX_AT (CPU_INTEL_PENTIUM_M | CPU_CX_AT) | ||
155 | #define CPU_PM_CX_XE (CPU_INTEL_PENTIUM_M | CPU_CX_XE) | ||
156 | #define CPU_PX_CX_AT (CPU_INTEL_PX | CPU_CX_AT) | ||
157 | #define CPU_PX_CX_AT_XE (CPU_INTEL_PX | CPU_CX_AT_XE) | ||
158 | |||
159 | /* Select all Intel CPUs*/ | ||
160 | #define CPU_INTEL_ALL (CPU_INTEL_PENTIUM | CPU_PX_CX_AT_XE) | ||
161 | |||
162 | #define MAX_CPU_FILES 512 | ||
163 | |||
164 | struct cpu_private { | ||
165 | unsigned cpu; | ||
166 | unsigned type; | ||
167 | unsigned reg; | ||
168 | unsigned file; | ||
169 | }; | ||
170 | |||
171 | struct cpu_debug_base { | ||
172 | char *name; /* Register name */ | ||
173 | unsigned flag; /* Register flag */ | ||
174 | }; | ||
175 | |||
176 | struct cpu_cpuX_base { | ||
177 | struct dentry *dentry; /* Register dentry */ | ||
178 | int init; /* Register index file */ | ||
179 | }; | ||
180 | |||
181 | struct cpu_file_base { | ||
182 | char *name; /* Register file name */ | ||
183 | unsigned flag; /* Register file flag */ | ||
184 | }; | ||
185 | |||
186 | struct cpu_debug_range { | ||
187 | unsigned min; /* Register range min */ | ||
188 | unsigned max; /* Register range max */ | ||
189 | unsigned flag; /* Supported flags */ | ||
190 | unsigned model; /* Supported models */ | ||
191 | }; | ||
192 | |||
193 | #endif /* _ASM_X86_CPU_DEBUG_H */ | ||
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h index dc27705f5443..5623c50d67b2 100644 --- a/arch/x86/include/asm/desc.h +++ b/arch/x86/include/asm/desc.h | |||
@@ -91,7 +91,6 @@ static inline int desc_empty(const void *ptr) | |||
91 | #define store_gdt(dtr) native_store_gdt(dtr) | 91 | #define store_gdt(dtr) native_store_gdt(dtr) |
92 | #define store_idt(dtr) native_store_idt(dtr) | 92 | #define store_idt(dtr) native_store_idt(dtr) |
93 | #define store_tr(tr) (tr = native_store_tr()) | 93 | #define store_tr(tr) (tr = native_store_tr()) |
94 | #define store_ldt(ldt) asm("sldt %0":"=m" (ldt)) | ||
95 | 94 | ||
96 | #define load_TLS(t, cpu) native_load_tls(t, cpu) | 95 | #define load_TLS(t, cpu) native_load_tls(t, cpu) |
97 | #define set_ldt native_set_ldt | 96 | #define set_ldt native_set_ldt |
@@ -112,6 +111,8 @@ static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) | |||
112 | } | 111 | } |
113 | #endif /* CONFIG_PARAVIRT */ | 112 | #endif /* CONFIG_PARAVIRT */ |
114 | 113 | ||
114 | #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) | ||
115 | |||
115 | static inline void native_write_idt_entry(gate_desc *idt, int entry, | 116 | static inline void native_write_idt_entry(gate_desc *idt, int entry, |
116 | const gate_desc *gate) | 117 | const gate_desc *gate) |
117 | { | 118 | { |
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h index 854d538ae857..c2e6bedaf258 100644 --- a/arch/x86/include/asm/entry_arch.h +++ b/arch/x86/include/asm/entry_arch.h | |||
@@ -33,6 +33,8 @@ BUILD_INTERRUPT3(invalidate_interrupt7,INVALIDATE_TLB_VECTOR_START+7, | |||
33 | smp_invalidate_interrupt) | 33 | smp_invalidate_interrupt) |
34 | #endif | 34 | #endif |
35 | 35 | ||
36 | BUILD_INTERRUPT(generic_interrupt, GENERIC_INTERRUPT_VECTOR) | ||
37 | |||
36 | /* | 38 | /* |
37 | * every pentium local APIC has two 'local interrupts', with a | 39 | * every pentium local APIC has two 'local interrupts', with a |
38 | * soft-definable vector attached to both interrupts, one of | 40 | * soft-definable vector attached to both interrupts, one of |
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h index dca8f03da5b2..63a79c77d220 100644 --- a/arch/x86/include/asm/fixmap.h +++ b/arch/x86/include/asm/fixmap.h | |||
@@ -24,9 +24,6 @@ | |||
24 | #include <asm/kmap_types.h> | 24 | #include <asm/kmap_types.h> |
25 | #else | 25 | #else |
26 | #include <asm/vsyscall.h> | 26 | #include <asm/vsyscall.h> |
27 | #ifdef CONFIG_EFI | ||
28 | #include <asm/efi.h> | ||
29 | #endif | ||
30 | #endif | 27 | #endif |
31 | 28 | ||
32 | /* | 29 | /* |
@@ -92,13 +89,6 @@ enum fixed_addresses { | |||
92 | FIX_IO_APIC_BASE_0, | 89 | FIX_IO_APIC_BASE_0, |
93 | FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, | 90 | FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, |
94 | #endif | 91 | #endif |
95 | #ifdef CONFIG_X86_64 | ||
96 | #ifdef CONFIG_EFI | ||
97 | FIX_EFI_IO_MAP_LAST_PAGE, | ||
98 | FIX_EFI_IO_MAP_FIRST_PAGE = FIX_EFI_IO_MAP_LAST_PAGE | ||
99 | + MAX_EFI_IO_PAGES - 1, | ||
100 | #endif | ||
101 | #endif | ||
102 | #ifdef CONFIG_X86_VISWS_APIC | 92 | #ifdef CONFIG_X86_VISWS_APIC |
103 | FIX_CO_CPU, /* Cobalt timer */ | 93 | FIX_CO_CPU, /* Cobalt timer */ |
104 | FIX_CO_APIC, /* Cobalt APIC Redirection Table */ | 94 | FIX_CO_APIC, /* Cobalt APIC Redirection Table */ |
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h index 176f058e7159..039db6aa8e02 100644 --- a/arch/x86/include/asm/hardirq.h +++ b/arch/x86/include/asm/hardirq.h | |||
@@ -12,6 +12,7 @@ typedef struct { | |||
12 | unsigned int apic_timer_irqs; /* arch dependent */ | 12 | unsigned int apic_timer_irqs; /* arch dependent */ |
13 | unsigned int irq_spurious_count; | 13 | unsigned int irq_spurious_count; |
14 | #endif | 14 | #endif |
15 | unsigned int generic_irqs; /* arch dependent */ | ||
15 | #ifdef CONFIG_SMP | 16 | #ifdef CONFIG_SMP |
16 | unsigned int irq_resched_count; | 17 | unsigned int irq_resched_count; |
17 | unsigned int irq_call_count; | 18 | unsigned int irq_call_count; |
diff --git a/arch/x86/include/asm/highmem.h b/arch/x86/include/asm/highmem.h index bf9276bea660..014c2b85ae45 100644 --- a/arch/x86/include/asm/highmem.h +++ b/arch/x86/include/asm/highmem.h | |||
@@ -63,6 +63,7 @@ void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot); | |||
63 | void *kmap_atomic(struct page *page, enum km_type type); | 63 | void *kmap_atomic(struct page *page, enum km_type type); |
64 | void kunmap_atomic(void *kvaddr, enum km_type type); | 64 | void kunmap_atomic(void *kvaddr, enum km_type type); |
65 | void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); | 65 | void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); |
66 | void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); | ||
66 | struct page *kmap_atomic_to_page(void *ptr); | 67 | struct page *kmap_atomic_to_page(void *ptr); |
67 | 68 | ||
68 | #ifndef CONFIG_PARAVIRT | 69 | #ifndef CONFIG_PARAVIRT |
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h index 370e1c83bb49..b762ea49bd70 100644 --- a/arch/x86/include/asm/hw_irq.h +++ b/arch/x86/include/asm/hw_irq.h | |||
@@ -27,6 +27,7 @@ | |||
27 | 27 | ||
28 | /* Interrupt handlers registered during init_IRQ */ | 28 | /* Interrupt handlers registered during init_IRQ */ |
29 | extern void apic_timer_interrupt(void); | 29 | extern void apic_timer_interrupt(void); |
30 | extern void generic_interrupt(void); | ||
30 | extern void error_interrupt(void); | 31 | extern void error_interrupt(void); |
31 | extern void spurious_interrupt(void); | 32 | extern void spurious_interrupt(void); |
32 | extern void thermal_interrupt(void); | 33 | extern void thermal_interrupt(void); |
diff --git a/arch/x86/include/asm/init.h b/arch/x86/include/asm/init.h new file mode 100644 index 000000000000..36fb1a6a5109 --- /dev/null +++ b/arch/x86/include/asm/init.h | |||
@@ -0,0 +1,18 @@ | |||
1 | #ifndef _ASM_X86_INIT_32_H | ||
2 | #define _ASM_X86_INIT_32_H | ||
3 | |||
4 | #ifdef CONFIG_X86_32 | ||
5 | extern void __init early_ioremap_page_table_range_init(void); | ||
6 | #endif | ||
7 | |||
8 | extern unsigned long __init | ||
9 | kernel_physical_mapping_init(unsigned long start, | ||
10 | unsigned long end, | ||
11 | unsigned long page_size_mask); | ||
12 | |||
13 | |||
14 | extern unsigned long __initdata e820_table_start; | ||
15 | extern unsigned long __meminitdata e820_table_end; | ||
16 | extern unsigned long __meminitdata e820_table_top; | ||
17 | |||
18 | #endif /* _ASM_X86_INIT_32_H */ | ||
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 107eb2196691..f38481bcd455 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h | |||
@@ -36,6 +36,7 @@ static inline int irq_canonicalize(int irq) | |||
36 | extern void fixup_irqs(void); | 36 | extern void fixup_irqs(void); |
37 | #endif | 37 | #endif |
38 | 38 | ||
39 | extern void (*generic_interrupt_extension)(void); | ||
39 | extern void init_IRQ(void); | 40 | extern void init_IRQ(void); |
40 | extern void native_init_IRQ(void); | 41 | extern void native_init_IRQ(void); |
41 | extern bool handle_irq(unsigned irq, struct pt_regs *regs); | 42 | extern bool handle_irq(unsigned irq, struct pt_regs *regs); |
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h index 8a285f356f8a..3cbd79bbb47c 100644 --- a/arch/x86/include/asm/irq_vectors.h +++ b/arch/x86/include/asm/irq_vectors.h | |||
@@ -112,6 +112,11 @@ | |||
112 | #define LOCAL_PERF_VECTOR 0xee | 112 | #define LOCAL_PERF_VECTOR 0xee |
113 | 113 | ||
114 | /* | 114 | /* |
115 | * Generic system vector for platform specific use | ||
116 | */ | ||
117 | #define GENERIC_INTERRUPT_VECTOR 0xed | ||
118 | |||
119 | /* | ||
115 | * First APIC vector available to drivers: (vectors 0x30-0xee) we | 120 | * First APIC vector available to drivers: (vectors 0x30-0xee) we |
116 | * start at 0x31(0x41) to spread out vectors evenly between priority | 121 | * start at 0x31(0x41) to spread out vectors evenly between priority |
117 | * levels. (0x80 is the syscall vector) | 122 | * levels. (0x80 is the syscall vector) |
diff --git a/arch/x86/include/asm/kexec.h b/arch/x86/include/asm/kexec.h index 0ceb6d19ed30..317ff1703d0b 100644 --- a/arch/x86/include/asm/kexec.h +++ b/arch/x86/include/asm/kexec.h | |||
@@ -9,13 +9,13 @@ | |||
9 | # define PAGES_NR 4 | 9 | # define PAGES_NR 4 |
10 | #else | 10 | #else |
11 | # define PA_CONTROL_PAGE 0 | 11 | # define PA_CONTROL_PAGE 0 |
12 | # define PA_TABLE_PAGE 1 | 12 | # define VA_CONTROL_PAGE 1 |
13 | # define PAGES_NR 2 | 13 | # define PA_TABLE_PAGE 2 |
14 | # define PA_SWAP_PAGE 3 | ||
15 | # define PAGES_NR 4 | ||
14 | #endif | 16 | #endif |
15 | 17 | ||
16 | #ifdef CONFIG_X86_32 | ||
17 | # define KEXEC_CONTROL_CODE_MAX_SIZE 2048 | 18 | # define KEXEC_CONTROL_CODE_MAX_SIZE 2048 |
18 | #endif | ||
19 | 19 | ||
20 | #ifndef __ASSEMBLY__ | 20 | #ifndef __ASSEMBLY__ |
21 | 21 | ||
@@ -136,10 +136,11 @@ relocate_kernel(unsigned long indirection_page, | |||
136 | unsigned int has_pae, | 136 | unsigned int has_pae, |
137 | unsigned int preserve_context); | 137 | unsigned int preserve_context); |
138 | #else | 138 | #else |
139 | NORET_TYPE void | 139 | unsigned long |
140 | relocate_kernel(unsigned long indirection_page, | 140 | relocate_kernel(unsigned long indirection_page, |
141 | unsigned long page_list, | 141 | unsigned long page_list, |
142 | unsigned long start_address) ATTRIB_NORET; | 142 | unsigned long start_address, |
143 | unsigned int preserve_context); | ||
143 | #endif | 144 | #endif |
144 | 145 | ||
145 | #define ARCH_HAS_KIMAGE_ARCH | 146 | #define ARCH_HAS_KIMAGE_ARCH |
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h index 9320e2a8a26a..12d55e773eb6 100644 --- a/arch/x86/include/asm/linkage.h +++ b/arch/x86/include/asm/linkage.h | |||
@@ -1,14 +1,11 @@ | |||
1 | #ifndef _ASM_X86_LINKAGE_H | 1 | #ifndef _ASM_X86_LINKAGE_H |
2 | #define _ASM_X86_LINKAGE_H | 2 | #define _ASM_X86_LINKAGE_H |
3 | 3 | ||
4 | #include <linux/stringify.h> | ||
5 | |||
4 | #undef notrace | 6 | #undef notrace |
5 | #define notrace __attribute__((no_instrument_function)) | 7 | #define notrace __attribute__((no_instrument_function)) |
6 | 8 | ||
7 | #ifdef CONFIG_X86_64 | ||
8 | #define __ALIGN .p2align 4,,15 | ||
9 | #define __ALIGN_STR ".p2align 4,,15" | ||
10 | #endif | ||
11 | |||
12 | #ifdef CONFIG_X86_32 | 9 | #ifdef CONFIG_X86_32 |
13 | #define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0))) | 10 | #define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0))) |
14 | /* | 11 | /* |
@@ -50,16 +47,20 @@ | |||
50 | __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \ | 47 | __asmlinkage_protect_n(ret, "g" (arg1), "g" (arg2), "g" (arg3), \ |
51 | "g" (arg4), "g" (arg5), "g" (arg6)) | 48 | "g" (arg4), "g" (arg5), "g" (arg6)) |
52 | 49 | ||
53 | #endif | 50 | #endif /* CONFIG_X86_32 */ |
51 | |||
52 | #ifdef __ASSEMBLY__ | ||
54 | 53 | ||
55 | #define GLOBAL(name) \ | 54 | #define GLOBAL(name) \ |
56 | .globl name; \ | 55 | .globl name; \ |
57 | name: | 56 | name: |
58 | 57 | ||
59 | #ifdef CONFIG_X86_ALIGNMENT_16 | 58 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_ALIGNMENT_16) |
60 | #define __ALIGN .align 16,0x90 | 59 | #define __ALIGN .p2align 4, 0x90 |
61 | #define __ALIGN_STR ".align 16,0x90" | 60 | #define __ALIGN_STR __stringify(__ALIGN) |
62 | #endif | 61 | #endif |
63 | 62 | ||
63 | #endif /* __ASSEMBLY__ */ | ||
64 | |||
64 | #endif /* _ASM_X86_LINKAGE_H */ | 65 | #endif /* _ASM_X86_LINKAGE_H */ |
65 | 66 | ||
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 32c6e17b960b..563933e06a35 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h | |||
@@ -11,6 +11,8 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ | 13 | #define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */ |
14 | #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ | ||
15 | #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ | ||
14 | 16 | ||
15 | #define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */ | 17 | #define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */ |
16 | #define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */ | 18 | #define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */ |
@@ -90,14 +92,29 @@ extern int mce_disabled; | |||
90 | 92 | ||
91 | #include <asm/atomic.h> | 93 | #include <asm/atomic.h> |
92 | 94 | ||
95 | void mce_setup(struct mce *m); | ||
93 | void mce_log(struct mce *m); | 96 | void mce_log(struct mce *m); |
94 | DECLARE_PER_CPU(struct sys_device, device_mce); | 97 | DECLARE_PER_CPU(struct sys_device, device_mce); |
95 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | 98 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
96 | 99 | ||
100 | /* | ||
101 | * To support more than 128 would need to escape the predefined | ||
102 | * Linux defined extended banks first. | ||
103 | */ | ||
104 | #define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1) | ||
105 | |||
97 | #ifdef CONFIG_X86_MCE_INTEL | 106 | #ifdef CONFIG_X86_MCE_INTEL |
98 | void mce_intel_feature_init(struct cpuinfo_x86 *c); | 107 | void mce_intel_feature_init(struct cpuinfo_x86 *c); |
108 | void cmci_clear(void); | ||
109 | void cmci_reenable(void); | ||
110 | void cmci_rediscover(int dying); | ||
111 | void cmci_recheck(void); | ||
99 | #else | 112 | #else |
100 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } | 113 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } |
114 | static inline void cmci_clear(void) {} | ||
115 | static inline void cmci_reenable(void) {} | ||
116 | static inline void cmci_rediscover(int dying) {} | ||
117 | static inline void cmci_recheck(void) {} | ||
101 | #endif | 118 | #endif |
102 | 119 | ||
103 | #ifdef CONFIG_X86_MCE_AMD | 120 | #ifdef CONFIG_X86_MCE_AMD |
@@ -106,11 +123,23 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c); | |||
106 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } | 123 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } |
107 | #endif | 124 | #endif |
108 | 125 | ||
109 | void mce_log_therm_throt_event(unsigned int cpu, __u64 status); | 126 | extern int mce_available(struct cpuinfo_x86 *c); |
127 | |||
128 | void mce_log_therm_throt_event(__u64 status); | ||
110 | 129 | ||
111 | extern atomic_t mce_entry; | 130 | extern atomic_t mce_entry; |
112 | 131 | ||
113 | extern void do_machine_check(struct pt_regs *, long); | 132 | extern void do_machine_check(struct pt_regs *, long); |
133 | |||
134 | typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); | ||
135 | DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); | ||
136 | |||
137 | enum mcp_flags { | ||
138 | MCP_TIMESTAMP = (1 << 0), /* log time stamp */ | ||
139 | MCP_UC = (1 << 1), /* log uncorrected errors */ | ||
140 | }; | ||
141 | extern void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); | ||
142 | |||
114 | extern int mce_notify_user(void); | 143 | extern int mce_notify_user(void); |
115 | 144 | ||
116 | #endif /* !CONFIG_X86_32 */ | 145 | #endif /* !CONFIG_X86_32 */ |
@@ -120,8 +149,8 @@ extern void mcheck_init(struct cpuinfo_x86 *c); | |||
120 | #else | 149 | #else |
121 | #define mcheck_init(c) do { } while (0) | 150 | #define mcheck_init(c) do { } while (0) |
122 | #endif | 151 | #endif |
123 | extern void stop_mce(void); | 152 | |
124 | extern void restart_mce(void); | 153 | extern void (*mce_threshold_vector)(void); |
125 | 154 | ||
126 | #endif /* __KERNEL__ */ | 155 | #endif /* __KERNEL__ */ |
127 | #endif /* _ASM_X86_MCE_H */ | 156 | #endif /* _ASM_X86_MCE_H */ |
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 358acc59ae04..2dbd2314139e 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h | |||
@@ -77,6 +77,11 @@ | |||
77 | #define MSR_IA32_MC0_ADDR 0x00000402 | 77 | #define MSR_IA32_MC0_ADDR 0x00000402 |
78 | #define MSR_IA32_MC0_MISC 0x00000403 | 78 | #define MSR_IA32_MC0_MISC 0x00000403 |
79 | 79 | ||
80 | /* These are consecutive and not in the normal 4er MCE bank block */ | ||
81 | #define MSR_IA32_MC0_CTL2 0x00000280 | ||
82 | #define CMCI_EN (1ULL << 30) | ||
83 | #define CMCI_THRESHOLD_MASK 0xffffULL | ||
84 | |||
80 | #define MSR_P6_PERFCTR0 0x000000c1 | 85 | #define MSR_P6_PERFCTR0 0x000000c1 |
81 | #define MSR_P6_PERFCTR1 0x000000c2 | 86 | #define MSR_P6_PERFCTR1 0x000000c2 |
82 | #define MSR_P6_EVNTSEL0 0x00000186 | 87 | #define MSR_P6_EVNTSEL0 0x00000186 |
diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_types.h index 2d625da6603c..826ad37006ab 100644 --- a/arch/x86/include/asm/page_types.h +++ b/arch/x86/include/asm/page_types.h | |||
@@ -40,14 +40,8 @@ | |||
40 | 40 | ||
41 | #ifndef __ASSEMBLY__ | 41 | #ifndef __ASSEMBLY__ |
42 | 42 | ||
43 | struct pgprot; | ||
44 | |||
45 | extern int page_is_ram(unsigned long pagenr); | 43 | extern int page_is_ram(unsigned long pagenr); |
46 | extern int devmem_is_allowed(unsigned long pagenr); | 44 | extern int devmem_is_allowed(unsigned long pagenr); |
47 | extern void map_devmem(unsigned long pfn, unsigned long size, | ||
48 | struct pgprot vma_prot); | ||
49 | extern void unmap_devmem(unsigned long pfn, unsigned long size, | ||
50 | struct pgprot vma_prot); | ||
51 | 45 | ||
52 | extern unsigned long max_low_pfn_mapped; | 46 | extern unsigned long max_low_pfn_mapped; |
53 | extern unsigned long max_pfn_mapped; | 47 | extern unsigned long max_pfn_mapped; |
diff --git a/arch/x86/include/asm/pat.h b/arch/x86/include/asm/pat.h index b0e70056838e..2cd07b9422f4 100644 --- a/arch/x86/include/asm/pat.h +++ b/arch/x86/include/asm/pat.h | |||
@@ -2,6 +2,7 @@ | |||
2 | #define _ASM_X86_PAT_H | 2 | #define _ASM_X86_PAT_H |
3 | 3 | ||
4 | #include <linux/types.h> | 4 | #include <linux/types.h> |
5 | #include <asm/pgtable_types.h> | ||
5 | 6 | ||
6 | #ifdef CONFIG_X86_PAT | 7 | #ifdef CONFIG_X86_PAT |
7 | extern int pat_enabled; | 8 | extern int pat_enabled; |
@@ -17,5 +18,9 @@ extern int free_memtype(u64 start, u64 end); | |||
17 | 18 | ||
18 | extern int kernel_map_sync_memtype(u64 base, unsigned long size, | 19 | extern int kernel_map_sync_memtype(u64 base, unsigned long size, |
19 | unsigned long flag); | 20 | unsigned long flag); |
21 | extern void map_devmem(unsigned long pfn, unsigned long size, | ||
22 | struct pgprot vma_prot); | ||
23 | extern void unmap_devmem(unsigned long pfn, unsigned long size, | ||
24 | struct pgprot vma_prot); | ||
20 | 25 | ||
21 | #endif /* _ASM_X86_PAT_H */ | 26 | #endif /* _ASM_X86_PAT_H */ |
diff --git a/arch/x86/include/asm/pgtable_32_types.h b/arch/x86/include/asm/pgtable_32_types.h index bd8df3b2fe04..2733fad45f98 100644 --- a/arch/x86/include/asm/pgtable_32_types.h +++ b/arch/x86/include/asm/pgtable_32_types.h | |||
@@ -25,6 +25,11 @@ | |||
25 | * area for the same reason. ;) | 25 | * area for the same reason. ;) |
26 | */ | 26 | */ |
27 | #define VMALLOC_OFFSET (8 * 1024 * 1024) | 27 | #define VMALLOC_OFFSET (8 * 1024 * 1024) |
28 | |||
29 | #ifndef __ASSEMBLER__ | ||
30 | extern bool __vmalloc_start_set; /* set once high_memory is set */ | ||
31 | #endif | ||
32 | |||
28 | #define VMALLOC_START ((unsigned long)high_memory + VMALLOC_OFFSET) | 33 | #define VMALLOC_START ((unsigned long)high_memory + VMALLOC_OFFSET) |
29 | #ifdef CONFIG_X86_PAE | 34 | #ifdef CONFIG_X86_PAE |
30 | #define LAST_PKMAP 512 | 35 | #define LAST_PKMAP 512 |
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 4d258ad76a0f..b8238dc8786d 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h | |||
@@ -273,6 +273,7 @@ typedef struct page *pgtable_t; | |||
273 | 273 | ||
274 | extern pteval_t __supported_pte_mask; | 274 | extern pteval_t __supported_pte_mask; |
275 | extern int nx_enabled; | 275 | extern int nx_enabled; |
276 | extern void set_nx(void); | ||
276 | 277 | ||
277 | #define pgprot_writecombine pgprot_writecombine | 278 | #define pgprot_writecombine pgprot_writecombine |
278 | extern pgprot_t pgprot_writecombine(pgprot_t prot); | 279 | extern pgprot_t pgprot_writecombine(pgprot_t prot); |
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h index 777327ef05c1..9f4dfba33b28 100644 --- a/arch/x86/include/asm/uv/uv_hub.h +++ b/arch/x86/include/asm/uv/uv_hub.h | |||
@@ -199,6 +199,10 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); | |||
199 | #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ | 199 | #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ |
200 | #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ | 200 | #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ |
201 | 201 | ||
202 | /* Loop through all installed blades */ | ||
203 | #define for_each_possible_blade(bid) \ | ||
204 | for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) | ||
205 | |||
202 | /* | 206 | /* |
203 | * Macros for converting between kernel virtual addresses, socket local physical | 207 | * Macros for converting between kernel virtual addresses, socket local physical |
204 | * addresses, and UV global physical addresses. | 208 | * addresses, and UV global physical addresses. |
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 95f216bbfaf1..339ce35648e6 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile | |||
@@ -111,7 +111,7 @@ obj-$(CONFIG_SWIOTLB) += pci-swiotlb_64.o # NB rename without _64 | |||
111 | ### | 111 | ### |
112 | # 64 bit specific files | 112 | # 64 bit specific files |
113 | ifeq ($(CONFIG_X86_64),y) | 113 | ifeq ($(CONFIG_X86_64),y) |
114 | obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o | 114 | obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o |
115 | obj-$(CONFIG_X86_PM_TIMER) += pmtimer_64.o | 115 | obj-$(CONFIG_X86_PM_TIMER) += pmtimer_64.o |
116 | obj-$(CONFIG_AUDIT) += audit_64.o | 116 | obj-$(CONFIG_AUDIT) += audit_64.o |
117 | 117 | ||
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 6907b8e85d52..4c80f1557433 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c | |||
@@ -414,9 +414,17 @@ void __init alternative_instructions(void) | |||
414 | that might execute the to be patched code. | 414 | that might execute the to be patched code. |
415 | Other CPUs are not running. */ | 415 | Other CPUs are not running. */ |
416 | stop_nmi(); | 416 | stop_nmi(); |
417 | #ifdef CONFIG_X86_MCE | 417 | |
418 | stop_mce(); | 418 | /* |
419 | #endif | 419 | * Don't stop machine check exceptions while patching. |
420 | * MCEs only happen when something got corrupted and in this | ||
421 | * case we must do something about the corruption. | ||
422 | * Ignoring it is worse than a unlikely patching race. | ||
423 | * Also machine checks tend to be broadcast and if one CPU | ||
424 | * goes into machine check the others follow quickly, so we don't | ||
425 | * expect a machine check to cause undue problems during to code | ||
426 | * patching. | ||
427 | */ | ||
420 | 428 | ||
421 | apply_alternatives(__alt_instructions, __alt_instructions_end); | 429 | apply_alternatives(__alt_instructions, __alt_instructions_end); |
422 | 430 | ||
@@ -456,9 +464,6 @@ void __init alternative_instructions(void) | |||
456 | (unsigned long)__smp_locks_end); | 464 | (unsigned long)__smp_locks_end); |
457 | 465 | ||
458 | restart_nmi(); | 466 | restart_nmi(); |
459 | #ifdef CONFIG_X86_MCE | ||
460 | restart_mce(); | ||
461 | #endif | ||
462 | } | 467 | } |
463 | 468 | ||
464 | /** | 469 | /** |
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index f9cecdfd05c5..30909a258d0f 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c | |||
@@ -46,6 +46,7 @@ | |||
46 | #include <asm/idle.h> | 46 | #include <asm/idle.h> |
47 | #include <asm/mtrr.h> | 47 | #include <asm/mtrr.h> |
48 | #include <asm/smp.h> | 48 | #include <asm/smp.h> |
49 | #include <asm/mce.h> | ||
49 | 50 | ||
50 | unsigned int num_processors; | 51 | unsigned int num_processors; |
51 | 52 | ||
@@ -842,6 +843,14 @@ void clear_local_APIC(void) | |||
842 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); | 843 | apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); |
843 | } | 844 | } |
844 | #endif | 845 | #endif |
846 | #ifdef CONFIG_X86_MCE_INTEL | ||
847 | if (maxlvt >= 6) { | ||
848 | v = apic_read(APIC_LVTCMCI); | ||
849 | if (!(v & APIC_LVT_MASKED)) | ||
850 | apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); | ||
851 | } | ||
852 | #endif | ||
853 | |||
845 | /* | 854 | /* |
846 | * Clean APIC state for other OSs: | 855 | * Clean APIC state for other OSs: |
847 | */ | 856 | */ |
@@ -1241,6 +1250,12 @@ void __cpuinit setup_local_APIC(void) | |||
1241 | apic_write(APIC_LVT1, value); | 1250 | apic_write(APIC_LVT1, value); |
1242 | 1251 | ||
1243 | preempt_enable(); | 1252 | preempt_enable(); |
1253 | |||
1254 | #ifdef CONFIG_X86_MCE_INTEL | ||
1255 | /* Recheck CMCI information after local APIC is up on CPU #0 */ | ||
1256 | if (smp_processor_id() == 0) | ||
1257 | cmci_recheck(); | ||
1258 | #endif | ||
1244 | } | 1259 | } |
1245 | 1260 | ||
1246 | void __cpuinit end_local_APIC_setup(void) | 1261 | void __cpuinit end_local_APIC_setup(void) |
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 82db7f45e2de..d4356f8b7522 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile | |||
@@ -14,6 +14,8 @@ obj-y += vmware.o hypervisor.o | |||
14 | obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o | 14 | obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o |
15 | obj-$(CONFIG_X86_64) += bugs_64.o | 15 | obj-$(CONFIG_X86_64) += bugs_64.o |
16 | 16 | ||
17 | obj-$(CONFIG_X86_CPU_DEBUG) += cpu_debug.o | ||
18 | |||
17 | obj-$(CONFIG_CPU_SUP_INTEL) += intel.o | 19 | obj-$(CONFIG_CPU_SUP_INTEL) += intel.o |
18 | obj-$(CONFIG_CPU_SUP_AMD) += amd.o | 20 | obj-$(CONFIG_CPU_SUP_AMD) += amd.o |
19 | obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o | 21 | obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o |
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 25423a5b80ed..f47df59016c5 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c | |||
@@ -5,6 +5,7 @@ | |||
5 | #include <asm/io.h> | 5 | #include <asm/io.h> |
6 | #include <asm/processor.h> | 6 | #include <asm/processor.h> |
7 | #include <asm/apic.h> | 7 | #include <asm/apic.h> |
8 | #include <asm/cpu.h> | ||
8 | 9 | ||
9 | #ifdef CONFIG_X86_64 | 10 | #ifdef CONFIG_X86_64 |
10 | # include <asm/numa_64.h> | 11 | # include <asm/numa_64.h> |
@@ -141,6 +142,55 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) | |||
141 | } | 142 | } |
142 | } | 143 | } |
143 | 144 | ||
145 | static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c) | ||
146 | { | ||
147 | #ifdef CONFIG_SMP | ||
148 | /* calling is from identify_secondary_cpu() ? */ | ||
149 | if (c->cpu_index == boot_cpu_id) | ||
150 | return; | ||
151 | |||
152 | /* | ||
153 | * Certain Athlons might work (for various values of 'work') in SMP | ||
154 | * but they are not certified as MP capable. | ||
155 | */ | ||
156 | /* Athlon 660/661 is valid. */ | ||
157 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | ||
158 | (c->x86_mask == 1))) | ||
159 | goto valid_k7; | ||
160 | |||
161 | /* Duron 670 is valid */ | ||
162 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | ||
163 | goto valid_k7; | ||
164 | |||
165 | /* | ||
166 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | ||
167 | * bit. It's worth noting that the A5 stepping (662) of some | ||
168 | * Athlon XP's have the MP bit set. | ||
169 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | ||
170 | * more. | ||
171 | */ | ||
172 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | ||
173 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | ||
174 | (c->x86_model > 7)) | ||
175 | if (cpu_has_mp) | ||
176 | goto valid_k7; | ||
177 | |||
178 | /* If we get here, not a certified SMP capable AMD system. */ | ||
179 | |||
180 | /* | ||
181 | * Don't taint if we are running SMP kernel on a single non-MP | ||
182 | * approved Athlon | ||
183 | */ | ||
184 | WARN_ONCE(1, "WARNING: This combination of AMD" | ||
185 | "processors is not suitable for SMP.\n"); | ||
186 | if (!test_taint(TAINT_UNSAFE_SMP)) | ||
187 | add_taint(TAINT_UNSAFE_SMP); | ||
188 | |||
189 | valid_k7: | ||
190 | ; | ||
191 | #endif | ||
192 | } | ||
193 | |||
144 | static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) | 194 | static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) |
145 | { | 195 | { |
146 | u32 l, h; | 196 | u32 l, h; |
@@ -175,6 +225,8 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) | |||
175 | } | 225 | } |
176 | 226 | ||
177 | set_cpu_cap(c, X86_FEATURE_K7); | 227 | set_cpu_cap(c, X86_FEATURE_K7); |
228 | |||
229 | amd_k7_smp_check(c); | ||
178 | } | 230 | } |
179 | #endif | 231 | #endif |
180 | 232 | ||
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 826d5c876278..f8869978bbb7 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c | |||
@@ -1078,8 +1078,7 @@ void __cpuinit cpu_init(void) | |||
1078 | 1078 | ||
1079 | atomic_inc(&init_mm.mm_count); | 1079 | atomic_inc(&init_mm.mm_count); |
1080 | me->active_mm = &init_mm; | 1080 | me->active_mm = &init_mm; |
1081 | if (me->mm) | 1081 | BUG_ON(me->mm); |
1082 | BUG(); | ||
1083 | enter_lazy_tlb(&init_mm, me); | 1082 | enter_lazy_tlb(&init_mm, me); |
1084 | 1083 | ||
1085 | load_sp0(t, ¤t->thread); | 1084 | load_sp0(t, ¤t->thread); |
@@ -1145,8 +1144,7 @@ void __cpuinit cpu_init(void) | |||
1145 | */ | 1144 | */ |
1146 | atomic_inc(&init_mm.mm_count); | 1145 | atomic_inc(&init_mm.mm_count); |
1147 | curr->active_mm = &init_mm; | 1146 | curr->active_mm = &init_mm; |
1148 | if (curr->mm) | 1147 | BUG_ON(curr->mm); |
1149 | BUG(); | ||
1150 | enter_lazy_tlb(&init_mm, curr); | 1148 | enter_lazy_tlb(&init_mm, curr); |
1151 | 1149 | ||
1152 | load_sp0(t, thread); | 1150 | load_sp0(t, thread); |
diff --git a/arch/x86/kernel/cpu/cpu_debug.c b/arch/x86/kernel/cpu/cpu_debug.c new file mode 100755 index 000000000000..9abbcbd933cc --- /dev/null +++ b/arch/x86/kernel/cpu/cpu_debug.c | |||
@@ -0,0 +1,785 @@ | |||
1 | /* | ||
2 | * CPU x86 architecture debug code | ||
3 | * | ||
4 | * Copyright(C) 2009 Jaswinder Singh Rajput | ||
5 | * | ||
6 | * For licencing details see kernel-base/COPYING | ||
7 | */ | ||
8 | |||
9 | #include <linux/interrupt.h> | ||
10 | #include <linux/compiler.h> | ||
11 | #include <linux/seq_file.h> | ||
12 | #include <linux/debugfs.h> | ||
13 | #include <linux/kprobes.h> | ||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/percpu.h> | ||
17 | #include <linux/signal.h> | ||
18 | #include <linux/errno.h> | ||
19 | #include <linux/sched.h> | ||
20 | #include <linux/types.h> | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/slab.h> | ||
23 | #include <linux/smp.h> | ||
24 | |||
25 | #include <asm/cpu_debug.h> | ||
26 | #include <asm/paravirt.h> | ||
27 | #include <asm/system.h> | ||
28 | #include <asm/traps.h> | ||
29 | #include <asm/apic.h> | ||
30 | #include <asm/desc.h> | ||
31 | |||
32 | static DEFINE_PER_CPU(struct cpu_cpuX_base, cpu_arr[CPU_REG_ALL_BIT]); | ||
33 | static DEFINE_PER_CPU(struct cpu_private *, priv_arr[MAX_CPU_FILES]); | ||
34 | static DEFINE_PER_CPU(unsigned, cpu_modelflag); | ||
35 | static DEFINE_PER_CPU(int, cpu_priv_count); | ||
36 | static DEFINE_PER_CPU(unsigned, cpu_model); | ||
37 | |||
38 | static DEFINE_MUTEX(cpu_debug_lock); | ||
39 | |||
40 | static struct dentry *cpu_debugfs_dir; | ||
41 | |||
42 | static struct cpu_debug_base cpu_base[] = { | ||
43 | { "mc", CPU_MC }, /* Machine Check */ | ||
44 | { "monitor", CPU_MONITOR }, /* Monitor */ | ||
45 | { "time", CPU_TIME }, /* Time */ | ||
46 | { "pmc", CPU_PMC }, /* Performance Monitor */ | ||
47 | { "platform", CPU_PLATFORM }, /* Platform */ | ||
48 | { "apic", CPU_APIC }, /* APIC */ | ||
49 | { "poweron", CPU_POWERON }, /* Power-on */ | ||
50 | { "control", CPU_CONTROL }, /* Control */ | ||
51 | { "features", CPU_FEATURES }, /* Features control */ | ||
52 | { "lastbranch", CPU_LBRANCH }, /* Last Branch */ | ||
53 | { "bios", CPU_BIOS }, /* BIOS */ | ||
54 | { "freq", CPU_FREQ }, /* Frequency */ | ||
55 | { "mtrr", CPU_MTRR }, /* MTRR */ | ||
56 | { "perf", CPU_PERF }, /* Performance */ | ||
57 | { "cache", CPU_CACHE }, /* Cache */ | ||
58 | { "sysenter", CPU_SYSENTER }, /* Sysenter */ | ||
59 | { "therm", CPU_THERM }, /* Thermal */ | ||
60 | { "misc", CPU_MISC }, /* Miscellaneous */ | ||
61 | { "debug", CPU_DEBUG }, /* Debug */ | ||
62 | { "pat", CPU_PAT }, /* PAT */ | ||
63 | { "vmx", CPU_VMX }, /* VMX */ | ||
64 | { "call", CPU_CALL }, /* System Call */ | ||
65 | { "base", CPU_BASE }, /* BASE Address */ | ||
66 | { "smm", CPU_SMM }, /* System mgmt mode */ | ||
67 | { "svm", CPU_SVM }, /*Secure Virtial Machine*/ | ||
68 | { "osvm", CPU_OSVM }, /* OS-Visible Workaround*/ | ||
69 | { "tss", CPU_TSS }, /* Task Stack Segment */ | ||
70 | { "cr", CPU_CR }, /* Control Registers */ | ||
71 | { "dt", CPU_DT }, /* Descriptor Table */ | ||
72 | { "registers", CPU_REG_ALL }, /* Select all Registers */ | ||
73 | }; | ||
74 | |||
75 | static struct cpu_file_base cpu_file[] = { | ||
76 | { "index", CPU_REG_ALL }, /* index */ | ||
77 | { "value", CPU_REG_ALL }, /* value */ | ||
78 | }; | ||
79 | |||
80 | /* Intel Registers Range */ | ||
81 | static struct cpu_debug_range cpu_intel_range[] = { | ||
82 | { 0x00000000, 0x00000001, CPU_MC, CPU_INTEL_ALL }, | ||
83 | { 0x00000006, 0x00000007, CPU_MONITOR, CPU_CX_AT_XE }, | ||
84 | { 0x00000010, 0x00000010, CPU_TIME, CPU_INTEL_ALL }, | ||
85 | { 0x00000011, 0x00000013, CPU_PMC, CPU_INTEL_PENTIUM }, | ||
86 | { 0x00000017, 0x00000017, CPU_PLATFORM, CPU_PX_CX_AT_XE }, | ||
87 | { 0x0000001B, 0x0000001B, CPU_APIC, CPU_P6_CX_AT_XE }, | ||
88 | |||
89 | { 0x0000002A, 0x0000002A, CPU_POWERON, CPU_PX_CX_AT_XE }, | ||
90 | { 0x0000002B, 0x0000002B, CPU_POWERON, CPU_INTEL_XEON }, | ||
91 | { 0x0000002C, 0x0000002C, CPU_FREQ, CPU_INTEL_XEON }, | ||
92 | { 0x0000003A, 0x0000003A, CPU_CONTROL, CPU_CX_AT_XE }, | ||
93 | |||
94 | { 0x00000040, 0x00000043, CPU_LBRANCH, CPU_PM_CX_AT_XE }, | ||
95 | { 0x00000044, 0x00000047, CPU_LBRANCH, CPU_PM_CO_AT }, | ||
96 | { 0x00000060, 0x00000063, CPU_LBRANCH, CPU_C2_AT }, | ||
97 | { 0x00000064, 0x00000067, CPU_LBRANCH, CPU_INTEL_ATOM }, | ||
98 | |||
99 | { 0x00000079, 0x00000079, CPU_BIOS, CPU_P6_CX_AT_XE }, | ||
100 | { 0x00000088, 0x0000008A, CPU_CACHE, CPU_INTEL_P6 }, | ||
101 | { 0x0000008B, 0x0000008B, CPU_BIOS, CPU_P6_CX_AT_XE }, | ||
102 | { 0x0000009B, 0x0000009B, CPU_MONITOR, CPU_INTEL_XEON }, | ||
103 | |||
104 | { 0x000000C1, 0x000000C2, CPU_PMC, CPU_P6_CX_AT }, | ||
105 | { 0x000000CD, 0x000000CD, CPU_FREQ, CPU_CX_AT }, | ||
106 | { 0x000000E7, 0x000000E8, CPU_PERF, CPU_CX_AT }, | ||
107 | { 0x000000FE, 0x000000FE, CPU_MTRR, CPU_P6_CX_XE }, | ||
108 | |||
109 | { 0x00000116, 0x00000116, CPU_CACHE, CPU_INTEL_P6 }, | ||
110 | { 0x00000118, 0x00000118, CPU_CACHE, CPU_INTEL_P6 }, | ||
111 | { 0x00000119, 0x00000119, CPU_CACHE, CPU_INTEL_PX }, | ||
112 | { 0x0000011A, 0x0000011B, CPU_CACHE, CPU_INTEL_P6 }, | ||
113 | { 0x0000011E, 0x0000011E, CPU_CACHE, CPU_PX_CX_AT }, | ||
114 | |||
115 | { 0x00000174, 0x00000176, CPU_SYSENTER, CPU_P6_CX_AT_XE }, | ||
116 | { 0x00000179, 0x0000017A, CPU_MC, CPU_PX_CX_AT_XE }, | ||
117 | { 0x0000017B, 0x0000017B, CPU_MC, CPU_P6_XE }, | ||
118 | { 0x00000186, 0x00000187, CPU_PMC, CPU_P6_CX_AT }, | ||
119 | { 0x00000198, 0x00000199, CPU_PERF, CPU_PM_CX_AT_XE }, | ||
120 | { 0x0000019A, 0x0000019A, CPU_TIME, CPU_PM_CX_AT_XE }, | ||
121 | { 0x0000019B, 0x0000019D, CPU_THERM, CPU_PM_CX_AT_XE }, | ||
122 | { 0x000001A0, 0x000001A0, CPU_MISC, CPU_PM_CX_AT_XE }, | ||
123 | |||
124 | { 0x000001C9, 0x000001C9, CPU_LBRANCH, CPU_PM_CX_AT }, | ||
125 | { 0x000001D7, 0x000001D8, CPU_LBRANCH, CPU_INTEL_XEON }, | ||
126 | { 0x000001D9, 0x000001D9, CPU_DEBUG, CPU_CX_AT_XE }, | ||
127 | { 0x000001DA, 0x000001DA, CPU_LBRANCH, CPU_INTEL_XEON }, | ||
128 | { 0x000001DB, 0x000001DB, CPU_LBRANCH, CPU_P6_XE }, | ||
129 | { 0x000001DC, 0x000001DC, CPU_LBRANCH, CPU_INTEL_P6 }, | ||
130 | { 0x000001DD, 0x000001DE, CPU_LBRANCH, CPU_PX_CX_AT_XE }, | ||
131 | { 0x000001E0, 0x000001E0, CPU_LBRANCH, CPU_INTEL_P6 }, | ||
132 | |||
133 | { 0x00000200, 0x0000020F, CPU_MTRR, CPU_P6_CX_XE }, | ||
134 | { 0x00000250, 0x00000250, CPU_MTRR, CPU_P6_CX_XE }, | ||
135 | { 0x00000258, 0x00000259, CPU_MTRR, CPU_P6_CX_XE }, | ||
136 | { 0x00000268, 0x0000026F, CPU_MTRR, CPU_P6_CX_XE }, | ||
137 | { 0x00000277, 0x00000277, CPU_PAT, CPU_C2_AT_XE }, | ||
138 | { 0x000002FF, 0x000002FF, CPU_MTRR, CPU_P6_CX_XE }, | ||
139 | |||
140 | { 0x00000300, 0x00000308, CPU_PMC, CPU_INTEL_XEON }, | ||
141 | { 0x00000309, 0x0000030B, CPU_PMC, CPU_C2_AT_XE }, | ||
142 | { 0x0000030C, 0x00000311, CPU_PMC, CPU_INTEL_XEON }, | ||
143 | { 0x00000345, 0x00000345, CPU_PMC, CPU_C2_AT }, | ||
144 | { 0x00000360, 0x00000371, CPU_PMC, CPU_INTEL_XEON }, | ||
145 | { 0x0000038D, 0x00000390, CPU_PMC, CPU_C2_AT }, | ||
146 | { 0x000003A0, 0x000003BE, CPU_PMC, CPU_INTEL_XEON }, | ||
147 | { 0x000003C0, 0x000003CD, CPU_PMC, CPU_INTEL_XEON }, | ||
148 | { 0x000003E0, 0x000003E1, CPU_PMC, CPU_INTEL_XEON }, | ||
149 | { 0x000003F0, 0x000003F0, CPU_PMC, CPU_INTEL_XEON }, | ||
150 | { 0x000003F1, 0x000003F1, CPU_PMC, CPU_C2_AT_XE }, | ||
151 | { 0x000003F2, 0x000003F2, CPU_PMC, CPU_INTEL_XEON }, | ||
152 | |||
153 | { 0x00000400, 0x00000402, CPU_MC, CPU_PM_CX_AT_XE }, | ||
154 | { 0x00000403, 0x00000403, CPU_MC, CPU_INTEL_XEON }, | ||
155 | { 0x00000404, 0x00000406, CPU_MC, CPU_PM_CX_AT_XE }, | ||
156 | { 0x00000407, 0x00000407, CPU_MC, CPU_INTEL_XEON }, | ||
157 | { 0x00000408, 0x0000040A, CPU_MC, CPU_PM_CX_AT_XE }, | ||
158 | { 0x0000040B, 0x0000040B, CPU_MC, CPU_INTEL_XEON }, | ||
159 | { 0x0000040C, 0x0000040E, CPU_MC, CPU_PM_CX_XE }, | ||
160 | { 0x0000040F, 0x0000040F, CPU_MC, CPU_INTEL_XEON }, | ||
161 | { 0x00000410, 0x00000412, CPU_MC, CPU_PM_CX_AT_XE }, | ||
162 | { 0x00000413, 0x00000417, CPU_MC, CPU_CX_AT_XE }, | ||
163 | { 0x00000480, 0x0000048B, CPU_VMX, CPU_CX_AT_XE }, | ||
164 | |||
165 | { 0x00000600, 0x00000600, CPU_DEBUG, CPU_PM_CX_AT_XE }, | ||
166 | { 0x00000680, 0x0000068F, CPU_LBRANCH, CPU_INTEL_XEON }, | ||
167 | { 0x000006C0, 0x000006CF, CPU_LBRANCH, CPU_INTEL_XEON }, | ||
168 | |||
169 | { 0x000107CC, 0x000107D3, CPU_PMC, CPU_INTEL_XEON_MP }, | ||
170 | |||
171 | { 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_INTEL_XEON }, | ||
172 | { 0xC0000081, 0xC0000082, CPU_CALL, CPU_INTEL_XEON }, | ||
173 | { 0xC0000084, 0xC0000084, CPU_CALL, CPU_INTEL_XEON }, | ||
174 | { 0xC0000100, 0xC0000102, CPU_BASE, CPU_INTEL_XEON }, | ||
175 | }; | ||
176 | |||
177 | /* AMD Registers Range */ | ||
178 | static struct cpu_debug_range cpu_amd_range[] = { | ||
179 | { 0x00000010, 0x00000010, CPU_TIME, CPU_ALL, }, | ||
180 | { 0x0000001B, 0x0000001B, CPU_APIC, CPU_ALL, }, | ||
181 | { 0x000000FE, 0x000000FE, CPU_MTRR, CPU_ALL, }, | ||
182 | |||
183 | { 0x00000174, 0x00000176, CPU_SYSENTER, CPU_ALL, }, | ||
184 | { 0x00000179, 0x0000017A, CPU_MC, CPU_ALL, }, | ||
185 | { 0x0000017B, 0x0000017B, CPU_MC, CPU_ALL, }, | ||
186 | { 0x000001D9, 0x000001D9, CPU_DEBUG, CPU_ALL, }, | ||
187 | { 0x000001DB, 0x000001DE, CPU_LBRANCH, CPU_ALL, }, | ||
188 | |||
189 | { 0x00000200, 0x0000020F, CPU_MTRR, CPU_ALL, }, | ||
190 | { 0x00000250, 0x00000250, CPU_MTRR, CPU_ALL, }, | ||
191 | { 0x00000258, 0x00000259, CPU_MTRR, CPU_ALL, }, | ||
192 | { 0x00000268, 0x0000026F, CPU_MTRR, CPU_ALL, }, | ||
193 | { 0x00000277, 0x00000277, CPU_PAT, CPU_ALL, }, | ||
194 | { 0x000002FF, 0x000002FF, CPU_MTRR, CPU_ALL, }, | ||
195 | |||
196 | { 0x00000400, 0x00000417, CPU_MC, CPU_ALL, }, | ||
197 | |||
198 | { 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_ALL, }, | ||
199 | { 0xC0000081, 0xC0000084, CPU_CALL, CPU_ALL, }, | ||
200 | { 0xC0000100, 0xC0000102, CPU_BASE, CPU_ALL, }, | ||
201 | { 0xC0000103, 0xC0000103, CPU_TIME, CPU_ALL, }, | ||
202 | |||
203 | { 0xC0000408, 0xC000040A, CPU_MC, CPU_ALL, }, | ||
204 | |||
205 | { 0xc0010000, 0xc0010007, CPU_PMC, CPU_ALL, }, | ||
206 | { 0xc0010010, 0xc0010010, CPU_MTRR, CPU_ALL, }, | ||
207 | { 0xc0010016, 0xc001001A, CPU_MTRR, CPU_ALL, }, | ||
208 | { 0xc001001D, 0xc001001D, CPU_MTRR, CPU_ALL, }, | ||
209 | { 0xc0010030, 0xc0010035, CPU_BIOS, CPU_ALL, }, | ||
210 | { 0xc0010056, 0xc0010056, CPU_SMM, CPU_ALL, }, | ||
211 | { 0xc0010061, 0xc0010063, CPU_SMM, CPU_ALL, }, | ||
212 | { 0xc0010074, 0xc0010074, CPU_MC, CPU_ALL, }, | ||
213 | { 0xc0010111, 0xc0010113, CPU_SMM, CPU_ALL, }, | ||
214 | { 0xc0010114, 0xc0010118, CPU_SVM, CPU_ALL, }, | ||
215 | { 0xc0010119, 0xc001011A, CPU_SMM, CPU_ALL, }, | ||
216 | { 0xc0010140, 0xc0010141, CPU_OSVM, CPU_ALL, }, | ||
217 | { 0xc0010156, 0xc0010156, CPU_SMM, CPU_ALL, }, | ||
218 | }; | ||
219 | |||
220 | |||
221 | static int get_cpu_modelflag(unsigned cpu) | ||
222 | { | ||
223 | int flag; | ||
224 | |||
225 | switch (per_cpu(cpu_model, cpu)) { | ||
226 | /* Intel */ | ||
227 | case 0x0501: | ||
228 | case 0x0502: | ||
229 | case 0x0504: | ||
230 | flag = CPU_INTEL_PENTIUM; | ||
231 | break; | ||
232 | case 0x0601: | ||
233 | case 0x0603: | ||
234 | case 0x0605: | ||
235 | case 0x0607: | ||
236 | case 0x0608: | ||
237 | case 0x060A: | ||
238 | case 0x060B: | ||
239 | flag = CPU_INTEL_P6; | ||
240 | break; | ||
241 | case 0x0609: | ||
242 | case 0x060D: | ||
243 | flag = CPU_INTEL_PENTIUM_M; | ||
244 | break; | ||
245 | case 0x060E: | ||
246 | flag = CPU_INTEL_CORE; | ||
247 | break; | ||
248 | case 0x060F: | ||
249 | case 0x0617: | ||
250 | flag = CPU_INTEL_CORE2; | ||
251 | break; | ||
252 | case 0x061C: | ||
253 | flag = CPU_INTEL_ATOM; | ||
254 | break; | ||
255 | case 0x0F00: | ||
256 | case 0x0F01: | ||
257 | case 0x0F02: | ||
258 | case 0x0F03: | ||
259 | case 0x0F04: | ||
260 | flag = CPU_INTEL_XEON_P4; | ||
261 | break; | ||
262 | case 0x0F06: | ||
263 | flag = CPU_INTEL_XEON_MP; | ||
264 | break; | ||
265 | default: | ||
266 | flag = CPU_NONE; | ||
267 | break; | ||
268 | } | ||
269 | |||
270 | return flag; | ||
271 | } | ||
272 | |||
273 | static int get_cpu_range_count(unsigned cpu) | ||
274 | { | ||
275 | int index; | ||
276 | |||
277 | switch (per_cpu(cpu_model, cpu) >> 16) { | ||
278 | case X86_VENDOR_INTEL: | ||
279 | index = ARRAY_SIZE(cpu_intel_range); | ||
280 | break; | ||
281 | case X86_VENDOR_AMD: | ||
282 | index = ARRAY_SIZE(cpu_amd_range); | ||
283 | break; | ||
284 | default: | ||
285 | index = 0; | ||
286 | break; | ||
287 | } | ||
288 | |||
289 | return index; | ||
290 | } | ||
291 | |||
292 | static int is_typeflag_valid(unsigned cpu, unsigned flag) | ||
293 | { | ||
294 | unsigned vendor, modelflag; | ||
295 | int i, index; | ||
296 | |||
297 | /* Standard Registers should be always valid */ | ||
298 | if (flag >= CPU_TSS) | ||
299 | return 1; | ||
300 | |||
301 | modelflag = per_cpu(cpu_modelflag, cpu); | ||
302 | vendor = per_cpu(cpu_model, cpu) >> 16; | ||
303 | index = get_cpu_range_count(cpu); | ||
304 | |||
305 | for (i = 0; i < index; i++) { | ||
306 | switch (vendor) { | ||
307 | case X86_VENDOR_INTEL: | ||
308 | if ((cpu_intel_range[i].model & modelflag) && | ||
309 | (cpu_intel_range[i].flag & flag)) | ||
310 | return 1; | ||
311 | break; | ||
312 | case X86_VENDOR_AMD: | ||
313 | if (cpu_amd_range[i].flag & flag) | ||
314 | return 1; | ||
315 | break; | ||
316 | } | ||
317 | } | ||
318 | |||
319 | /* Invalid */ | ||
320 | return 0; | ||
321 | } | ||
322 | |||
323 | static unsigned get_cpu_range(unsigned cpu, unsigned *min, unsigned *max, | ||
324 | int index, unsigned flag) | ||
325 | { | ||
326 | unsigned modelflag; | ||
327 | |||
328 | modelflag = per_cpu(cpu_modelflag, cpu); | ||
329 | *max = 0; | ||
330 | switch (per_cpu(cpu_model, cpu) >> 16) { | ||
331 | case X86_VENDOR_INTEL: | ||
332 | if ((cpu_intel_range[index].model & modelflag) && | ||
333 | (cpu_intel_range[index].flag & flag)) { | ||
334 | *min = cpu_intel_range[index].min; | ||
335 | *max = cpu_intel_range[index].max; | ||
336 | } | ||
337 | break; | ||
338 | case X86_VENDOR_AMD: | ||
339 | if (cpu_amd_range[index].flag & flag) { | ||
340 | *min = cpu_amd_range[index].min; | ||
341 | *max = cpu_amd_range[index].max; | ||
342 | } | ||
343 | break; | ||
344 | } | ||
345 | |||
346 | return *max; | ||
347 | } | ||
348 | |||
349 | /* This function can also be called with seq = NULL for printk */ | ||
350 | static void print_cpu_data(struct seq_file *seq, unsigned type, | ||
351 | u32 low, u32 high) | ||
352 | { | ||
353 | struct cpu_private *priv; | ||
354 | u64 val = high; | ||
355 | |||
356 | if (seq) { | ||
357 | priv = seq->private; | ||
358 | if (priv->file) { | ||
359 | val = (val << 32) | low; | ||
360 | seq_printf(seq, "0x%llx\n", val); | ||
361 | } else | ||
362 | seq_printf(seq, " %08x: %08x_%08x\n", | ||
363 | type, high, low); | ||
364 | } else | ||
365 | printk(KERN_INFO " %08x: %08x_%08x\n", type, high, low); | ||
366 | } | ||
367 | |||
368 | /* This function can also be called with seq = NULL for printk */ | ||
369 | static void print_msr(struct seq_file *seq, unsigned cpu, unsigned flag) | ||
370 | { | ||
371 | unsigned msr, msr_min, msr_max; | ||
372 | struct cpu_private *priv; | ||
373 | u32 low, high; | ||
374 | int i, range; | ||
375 | |||
376 | if (seq) { | ||
377 | priv = seq->private; | ||
378 | if (priv->file) { | ||
379 | if (!rdmsr_safe_on_cpu(priv->cpu, priv->reg, | ||
380 | &low, &high)) | ||
381 | print_cpu_data(seq, priv->reg, low, high); | ||
382 | return; | ||
383 | } | ||
384 | } | ||
385 | |||
386 | range = get_cpu_range_count(cpu); | ||
387 | |||
388 | for (i = 0; i < range; i++) { | ||
389 | if (!get_cpu_range(cpu, &msr_min, &msr_max, i, flag)) | ||
390 | continue; | ||
391 | |||
392 | for (msr = msr_min; msr <= msr_max; msr++) { | ||
393 | if (rdmsr_safe_on_cpu(cpu, msr, &low, &high)) | ||
394 | continue; | ||
395 | print_cpu_data(seq, msr, low, high); | ||
396 | } | ||
397 | } | ||
398 | } | ||
399 | |||
400 | static void print_tss(void *arg) | ||
401 | { | ||
402 | struct pt_regs *regs = task_pt_regs(current); | ||
403 | struct seq_file *seq = arg; | ||
404 | unsigned int seg; | ||
405 | |||
406 | seq_printf(seq, " RAX\t: %016lx\n", regs->ax); | ||
407 | seq_printf(seq, " RBX\t: %016lx\n", regs->bx); | ||
408 | seq_printf(seq, " RCX\t: %016lx\n", regs->cx); | ||
409 | seq_printf(seq, " RDX\t: %016lx\n", regs->dx); | ||
410 | |||
411 | seq_printf(seq, " RSI\t: %016lx\n", regs->si); | ||
412 | seq_printf(seq, " RDI\t: %016lx\n", regs->di); | ||
413 | seq_printf(seq, " RBP\t: %016lx\n", regs->bp); | ||
414 | seq_printf(seq, " ESP\t: %016lx\n", regs->sp); | ||
415 | |||
416 | #ifdef CONFIG_X86_64 | ||
417 | seq_printf(seq, " R08\t: %016lx\n", regs->r8); | ||
418 | seq_printf(seq, " R09\t: %016lx\n", regs->r9); | ||
419 | seq_printf(seq, " R10\t: %016lx\n", regs->r10); | ||
420 | seq_printf(seq, " R11\t: %016lx\n", regs->r11); | ||
421 | seq_printf(seq, " R12\t: %016lx\n", regs->r12); | ||
422 | seq_printf(seq, " R13\t: %016lx\n", regs->r13); | ||
423 | seq_printf(seq, " R14\t: %016lx\n", regs->r14); | ||
424 | seq_printf(seq, " R15\t: %016lx\n", regs->r15); | ||
425 | #endif | ||
426 | |||
427 | asm("movl %%cs,%0" : "=r" (seg)); | ||
428 | seq_printf(seq, " CS\t: %04x\n", seg); | ||
429 | asm("movl %%ds,%0" : "=r" (seg)); | ||
430 | seq_printf(seq, " DS\t: %04x\n", seg); | ||
431 | seq_printf(seq, " SS\t: %04lx\n", regs->ss & 0xffff); | ||
432 | asm("movl %%es,%0" : "=r" (seg)); | ||
433 | seq_printf(seq, " ES\t: %04x\n", seg); | ||
434 | asm("movl %%fs,%0" : "=r" (seg)); | ||
435 | seq_printf(seq, " FS\t: %04x\n", seg); | ||
436 | asm("movl %%gs,%0" : "=r" (seg)); | ||
437 | seq_printf(seq, " GS\t: %04x\n", seg); | ||
438 | |||
439 | seq_printf(seq, " EFLAGS\t: %016lx\n", regs->flags); | ||
440 | |||
441 | seq_printf(seq, " EIP\t: %016lx\n", regs->ip); | ||
442 | } | ||
443 | |||
444 | static void print_cr(void *arg) | ||
445 | { | ||
446 | struct seq_file *seq = arg; | ||
447 | |||
448 | seq_printf(seq, " cr0\t: %016lx\n", read_cr0()); | ||
449 | seq_printf(seq, " cr2\t: %016lx\n", read_cr2()); | ||
450 | seq_printf(seq, " cr3\t: %016lx\n", read_cr3()); | ||
451 | seq_printf(seq, " cr4\t: %016lx\n", read_cr4_safe()); | ||
452 | #ifdef CONFIG_X86_64 | ||
453 | seq_printf(seq, " cr8\t: %016lx\n", read_cr8()); | ||
454 | #endif | ||
455 | } | ||
456 | |||
457 | static void print_desc_ptr(char *str, struct seq_file *seq, struct desc_ptr dt) | ||
458 | { | ||
459 | seq_printf(seq, " %s\t: %016llx\n", str, (u64)(dt.address | dt.size)); | ||
460 | } | ||
461 | |||
462 | static void print_dt(void *seq) | ||
463 | { | ||
464 | struct desc_ptr dt; | ||
465 | unsigned long ldt; | ||
466 | |||
467 | /* IDT */ | ||
468 | store_idt((struct desc_ptr *)&dt); | ||
469 | print_desc_ptr("IDT", seq, dt); | ||
470 | |||
471 | /* GDT */ | ||
472 | store_gdt((struct desc_ptr *)&dt); | ||
473 | print_desc_ptr("GDT", seq, dt); | ||
474 | |||
475 | /* LDT */ | ||
476 | store_ldt(ldt); | ||
477 | seq_printf(seq, " LDT\t: %016lx\n", ldt); | ||
478 | |||
479 | /* TR */ | ||
480 | store_tr(ldt); | ||
481 | seq_printf(seq, " TR\t: %016lx\n", ldt); | ||
482 | } | ||
483 | |||
484 | static void print_dr(void *arg) | ||
485 | { | ||
486 | struct seq_file *seq = arg; | ||
487 | unsigned long dr; | ||
488 | int i; | ||
489 | |||
490 | for (i = 0; i < 8; i++) { | ||
491 | /* Ignore db4, db5 */ | ||
492 | if ((i == 4) || (i == 5)) | ||
493 | continue; | ||
494 | get_debugreg(dr, i); | ||
495 | seq_printf(seq, " dr%d\t: %016lx\n", i, dr); | ||
496 | } | ||
497 | |||
498 | seq_printf(seq, "\n MSR\t:\n"); | ||
499 | } | ||
500 | |||
501 | static void print_apic(void *arg) | ||
502 | { | ||
503 | struct seq_file *seq = arg; | ||
504 | |||
505 | #ifdef CONFIG_X86_LOCAL_APIC | ||
506 | seq_printf(seq, " LAPIC\t:\n"); | ||
507 | seq_printf(seq, " ID\t\t: %08x\n", apic_read(APIC_ID) >> 24); | ||
508 | seq_printf(seq, " LVR\t\t: %08x\n", apic_read(APIC_LVR)); | ||
509 | seq_printf(seq, " TASKPRI\t: %08x\n", apic_read(APIC_TASKPRI)); | ||
510 | seq_printf(seq, " ARBPRI\t\t: %08x\n", apic_read(APIC_ARBPRI)); | ||
511 | seq_printf(seq, " PROCPRI\t: %08x\n", apic_read(APIC_PROCPRI)); | ||
512 | seq_printf(seq, " LDR\t\t: %08x\n", apic_read(APIC_LDR)); | ||
513 | seq_printf(seq, " DFR\t\t: %08x\n", apic_read(APIC_DFR)); | ||
514 | seq_printf(seq, " SPIV\t\t: %08x\n", apic_read(APIC_SPIV)); | ||
515 | seq_printf(seq, " ISR\t\t: %08x\n", apic_read(APIC_ISR)); | ||
516 | seq_printf(seq, " ESR\t\t: %08x\n", apic_read(APIC_ESR)); | ||
517 | seq_printf(seq, " ICR\t\t: %08x\n", apic_read(APIC_ICR)); | ||
518 | seq_printf(seq, " ICR2\t\t: %08x\n", apic_read(APIC_ICR2)); | ||
519 | seq_printf(seq, " LVTT\t\t: %08x\n", apic_read(APIC_LVTT)); | ||
520 | seq_printf(seq, " LVTTHMR\t: %08x\n", apic_read(APIC_LVTTHMR)); | ||
521 | seq_printf(seq, " LVTPC\t\t: %08x\n", apic_read(APIC_LVTPC)); | ||
522 | seq_printf(seq, " LVT0\t\t: %08x\n", apic_read(APIC_LVT0)); | ||
523 | seq_printf(seq, " LVT1\t\t: %08x\n", apic_read(APIC_LVT1)); | ||
524 | seq_printf(seq, " LVTERR\t\t: %08x\n", apic_read(APIC_LVTERR)); | ||
525 | seq_printf(seq, " TMICT\t\t: %08x\n", apic_read(APIC_TMICT)); | ||
526 | seq_printf(seq, " TMCCT\t\t: %08x\n", apic_read(APIC_TMCCT)); | ||
527 | seq_printf(seq, " TDCR\t\t: %08x\n", apic_read(APIC_TDCR)); | ||
528 | #endif /* CONFIG_X86_LOCAL_APIC */ | ||
529 | |||
530 | seq_printf(seq, "\n MSR\t:\n"); | ||
531 | } | ||
532 | |||
533 | static int cpu_seq_show(struct seq_file *seq, void *v) | ||
534 | { | ||
535 | struct cpu_private *priv = seq->private; | ||
536 | |||
537 | if (priv == NULL) | ||
538 | return -EINVAL; | ||
539 | |||
540 | switch (cpu_base[priv->type].flag) { | ||
541 | case CPU_TSS: | ||
542 | smp_call_function_single(priv->cpu, print_tss, seq, 1); | ||
543 | break; | ||
544 | case CPU_CR: | ||
545 | smp_call_function_single(priv->cpu, print_cr, seq, 1); | ||
546 | break; | ||
547 | case CPU_DT: | ||
548 | smp_call_function_single(priv->cpu, print_dt, seq, 1); | ||
549 | break; | ||
550 | case CPU_DEBUG: | ||
551 | if (priv->file == CPU_INDEX_BIT) | ||
552 | smp_call_function_single(priv->cpu, print_dr, seq, 1); | ||
553 | print_msr(seq, priv->cpu, cpu_base[priv->type].flag); | ||
554 | break; | ||
555 | case CPU_APIC: | ||
556 | if (priv->file == CPU_INDEX_BIT) | ||
557 | smp_call_function_single(priv->cpu, print_apic, seq, 1); | ||
558 | print_msr(seq, priv->cpu, cpu_base[priv->type].flag); | ||
559 | break; | ||
560 | |||
561 | default: | ||
562 | print_msr(seq, priv->cpu, cpu_base[priv->type].flag); | ||
563 | break; | ||
564 | } | ||
565 | seq_printf(seq, "\n"); | ||
566 | |||
567 | return 0; | ||
568 | } | ||
569 | |||
570 | static void *cpu_seq_start(struct seq_file *seq, loff_t *pos) | ||
571 | { | ||
572 | if (*pos == 0) /* One time is enough ;-) */ | ||
573 | return seq; | ||
574 | |||
575 | return NULL; | ||
576 | } | ||
577 | |||
578 | static void *cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos) | ||
579 | { | ||
580 | (*pos)++; | ||
581 | |||
582 | return cpu_seq_start(seq, pos); | ||
583 | } | ||
584 | |||
585 | static void cpu_seq_stop(struct seq_file *seq, void *v) | ||
586 | { | ||
587 | } | ||
588 | |||
589 | static const struct seq_operations cpu_seq_ops = { | ||
590 | .start = cpu_seq_start, | ||
591 | .next = cpu_seq_next, | ||
592 | .stop = cpu_seq_stop, | ||
593 | .show = cpu_seq_show, | ||
594 | }; | ||
595 | |||
596 | static int cpu_seq_open(struct inode *inode, struct file *file) | ||
597 | { | ||
598 | struct cpu_private *priv = inode->i_private; | ||
599 | struct seq_file *seq; | ||
600 | int err; | ||
601 | |||
602 | err = seq_open(file, &cpu_seq_ops); | ||
603 | if (!err) { | ||
604 | seq = file->private_data; | ||
605 | seq->private = priv; | ||
606 | } | ||
607 | |||
608 | return err; | ||
609 | } | ||
610 | |||
611 | static const struct file_operations cpu_fops = { | ||
612 | .open = cpu_seq_open, | ||
613 | .read = seq_read, | ||
614 | .llseek = seq_lseek, | ||
615 | .release = seq_release, | ||
616 | }; | ||
617 | |||
618 | static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg, | ||
619 | unsigned file, struct dentry *dentry) | ||
620 | { | ||
621 | struct cpu_private *priv = NULL; | ||
622 | |||
623 | /* Already intialized */ | ||
624 | if (file == CPU_INDEX_BIT) | ||
625 | if (per_cpu(cpu_arr[type].init, cpu)) | ||
626 | return 0; | ||
627 | |||
628 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | ||
629 | if (priv == NULL) | ||
630 | return -ENOMEM; | ||
631 | |||
632 | priv->cpu = cpu; | ||
633 | priv->type = type; | ||
634 | priv->reg = reg; | ||
635 | priv->file = file; | ||
636 | mutex_lock(&cpu_debug_lock); | ||
637 | per_cpu(priv_arr[type], cpu) = priv; | ||
638 | per_cpu(cpu_priv_count, cpu)++; | ||
639 | mutex_unlock(&cpu_debug_lock); | ||
640 | |||
641 | if (file) | ||
642 | debugfs_create_file(cpu_file[file].name, S_IRUGO, | ||
643 | dentry, (void *)priv, &cpu_fops); | ||
644 | else { | ||
645 | debugfs_create_file(cpu_base[type].name, S_IRUGO, | ||
646 | per_cpu(cpu_arr[type].dentry, cpu), | ||
647 | (void *)priv, &cpu_fops); | ||
648 | mutex_lock(&cpu_debug_lock); | ||
649 | per_cpu(cpu_arr[type].init, cpu) = 1; | ||
650 | mutex_unlock(&cpu_debug_lock); | ||
651 | } | ||
652 | |||
653 | return 0; | ||
654 | } | ||
655 | |||
656 | static int cpu_init_regfiles(unsigned cpu, unsigned int type, unsigned reg, | ||
657 | struct dentry *dentry) | ||
658 | { | ||
659 | unsigned file; | ||
660 | int err = 0; | ||
661 | |||
662 | for (file = 0; file < ARRAY_SIZE(cpu_file); file++) { | ||
663 | err = cpu_create_file(cpu, type, reg, file, dentry); | ||
664 | if (err) | ||
665 | return err; | ||
666 | } | ||
667 | |||
668 | return err; | ||
669 | } | ||
670 | |||
671 | static int cpu_init_msr(unsigned cpu, unsigned type, struct dentry *dentry) | ||
672 | { | ||
673 | struct dentry *cpu_dentry = NULL; | ||
674 | unsigned reg, reg_min, reg_max; | ||
675 | int i, range, err = 0; | ||
676 | char reg_dir[12]; | ||
677 | u32 low, high; | ||
678 | |||
679 | range = get_cpu_range_count(cpu); | ||
680 | |||
681 | for (i = 0; i < range; i++) { | ||
682 | if (!get_cpu_range(cpu, ®_min, ®_max, i, | ||
683 | cpu_base[type].flag)) | ||
684 | continue; | ||
685 | |||
686 | for (reg = reg_min; reg <= reg_max; reg++) { | ||
687 | if (rdmsr_safe_on_cpu(cpu, reg, &low, &high)) | ||
688 | continue; | ||
689 | |||
690 | sprintf(reg_dir, "0x%x", reg); | ||
691 | cpu_dentry = debugfs_create_dir(reg_dir, dentry); | ||
692 | err = cpu_init_regfiles(cpu, type, reg, cpu_dentry); | ||
693 | if (err) | ||
694 | return err; | ||
695 | } | ||
696 | } | ||
697 | |||
698 | return err; | ||
699 | } | ||
700 | |||
701 | static int cpu_init_allreg(unsigned cpu, struct dentry *dentry) | ||
702 | { | ||
703 | struct dentry *cpu_dentry = NULL; | ||
704 | unsigned type; | ||
705 | int err = 0; | ||
706 | |||
707 | for (type = 0; type < ARRAY_SIZE(cpu_base) - 1; type++) { | ||
708 | if (!is_typeflag_valid(cpu, cpu_base[type].flag)) | ||
709 | continue; | ||
710 | cpu_dentry = debugfs_create_dir(cpu_base[type].name, dentry); | ||
711 | per_cpu(cpu_arr[type].dentry, cpu) = cpu_dentry; | ||
712 | |||
713 | if (type < CPU_TSS_BIT) | ||
714 | err = cpu_init_msr(cpu, type, cpu_dentry); | ||
715 | else | ||
716 | err = cpu_create_file(cpu, type, 0, CPU_INDEX_BIT, | ||
717 | cpu_dentry); | ||
718 | if (err) | ||
719 | return err; | ||
720 | } | ||
721 | |||
722 | return err; | ||
723 | } | ||
724 | |||
725 | static int cpu_init_cpu(void) | ||
726 | { | ||
727 | struct dentry *cpu_dentry = NULL; | ||
728 | struct cpuinfo_x86 *cpui; | ||
729 | char cpu_dir[12]; | ||
730 | unsigned cpu; | ||
731 | int err = 0; | ||
732 | |||
733 | for (cpu = 0; cpu < nr_cpu_ids; cpu++) { | ||
734 | cpui = &cpu_data(cpu); | ||
735 | if (!cpu_has(cpui, X86_FEATURE_MSR)) | ||
736 | continue; | ||
737 | per_cpu(cpu_model, cpu) = ((cpui->x86_vendor << 16) | | ||
738 | (cpui->x86 << 8) | | ||
739 | (cpui->x86_model)); | ||
740 | per_cpu(cpu_modelflag, cpu) = get_cpu_modelflag(cpu); | ||
741 | |||
742 | sprintf(cpu_dir, "cpu%d", cpu); | ||
743 | cpu_dentry = debugfs_create_dir(cpu_dir, cpu_debugfs_dir); | ||
744 | err = cpu_init_allreg(cpu, cpu_dentry); | ||
745 | |||
746 | pr_info("cpu%d(%d) debug files %d\n", | ||
747 | cpu, nr_cpu_ids, per_cpu(cpu_priv_count, cpu)); | ||
748 | if (per_cpu(cpu_priv_count, cpu) > MAX_CPU_FILES) { | ||
749 | pr_err("Register files count %d exceeds limit %d\n", | ||
750 | per_cpu(cpu_priv_count, cpu), MAX_CPU_FILES); | ||
751 | per_cpu(cpu_priv_count, cpu) = MAX_CPU_FILES; | ||
752 | err = -ENFILE; | ||
753 | } | ||
754 | if (err) | ||
755 | return err; | ||
756 | } | ||
757 | |||
758 | return err; | ||
759 | } | ||
760 | |||
761 | static int __init cpu_debug_init(void) | ||
762 | { | ||
763 | cpu_debugfs_dir = debugfs_create_dir("cpu", arch_debugfs_dir); | ||
764 | |||
765 | return cpu_init_cpu(); | ||
766 | } | ||
767 | |||
768 | static void __exit cpu_debug_exit(void) | ||
769 | { | ||
770 | int i, cpu; | ||
771 | |||
772 | if (cpu_debugfs_dir) | ||
773 | debugfs_remove_recursive(cpu_debugfs_dir); | ||
774 | |||
775 | for (cpu = 0; cpu < nr_cpu_ids; cpu++) | ||
776 | for (i = 0; i < per_cpu(cpu_priv_count, cpu); i++) | ||
777 | kfree(per_cpu(priv_arr[i], cpu)); | ||
778 | } | ||
779 | |||
780 | module_init(cpu_debug_init); | ||
781 | module_exit(cpu_debug_exit); | ||
782 | |||
783 | MODULE_AUTHOR("Jaswinder Singh Rajput"); | ||
784 | MODULE_DESCRIPTION("CPU Debug module"); | ||
785 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 25c559ba8d54..191117f1ad51 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <asm/uaccess.h> | 13 | #include <asm/uaccess.h> |
14 | #include <asm/ds.h> | 14 | #include <asm/ds.h> |
15 | #include <asm/bugs.h> | 15 | #include <asm/bugs.h> |
16 | #include <asm/cpu.h> | ||
16 | 17 | ||
17 | #ifdef CONFIG_X86_64 | 18 | #ifdef CONFIG_X86_64 |
18 | #include <asm/topology.h> | 19 | #include <asm/topology.h> |
@@ -110,6 +111,28 @@ static void __cpuinit trap_init_f00f_bug(void) | |||
110 | } | 111 | } |
111 | #endif | 112 | #endif |
112 | 113 | ||
114 | static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c) | ||
115 | { | ||
116 | #ifdef CONFIG_SMP | ||
117 | /* calling is from identify_secondary_cpu() ? */ | ||
118 | if (c->cpu_index == boot_cpu_id) | ||
119 | return; | ||
120 | |||
121 | /* | ||
122 | * Mask B, Pentium, but not Pentium MMX | ||
123 | */ | ||
124 | if (c->x86 == 5 && | ||
125 | c->x86_mask >= 1 && c->x86_mask <= 4 && | ||
126 | c->x86_model <= 3) { | ||
127 | /* | ||
128 | * Remember we have B step Pentia with bugs | ||
129 | */ | ||
130 | WARN_ONCE(1, "WARNING: SMP operation may be unreliable" | ||
131 | "with B stepping processors.\n"); | ||
132 | } | ||
133 | #endif | ||
134 | } | ||
135 | |||
113 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | 136 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) |
114 | { | 137 | { |
115 | unsigned long lo, hi; | 138 | unsigned long lo, hi; |
@@ -186,6 +209,8 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | |||
186 | #ifdef CONFIG_X86_NUMAQ | 209 | #ifdef CONFIG_X86_NUMAQ |
187 | numaq_tsc_disable(); | 210 | numaq_tsc_disable(); |
188 | #endif | 211 | #endif |
212 | |||
213 | intel_smp_check(c); | ||
189 | } | 214 | } |
190 | #else | 215 | #else |
191 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) | 216 | static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) |
diff --git a/arch/x86/kernel/cpu/mcheck/Makefile b/arch/x86/kernel/cpu/mcheck/Makefile index d7d2323bbb69..b2f89829bbe8 100644 --- a/arch/x86/kernel/cpu/mcheck/Makefile +++ b/arch/x86/kernel/cpu/mcheck/Makefile | |||
@@ -4,3 +4,4 @@ obj-$(CONFIG_X86_32) += k7.o p4.o p5.o p6.o winchip.o | |||
4 | obj-$(CONFIG_X86_MCE_INTEL) += mce_intel_64.o | 4 | obj-$(CONFIG_X86_MCE_INTEL) += mce_intel_64.o |
5 | obj-$(CONFIG_X86_MCE_AMD) += mce_amd_64.o | 5 | obj-$(CONFIG_X86_MCE_AMD) += mce_amd_64.o |
6 | obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o | 6 | obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o |
7 | obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o | ||
diff --git a/arch/x86/kernel/cpu/mcheck/mce_32.c b/arch/x86/kernel/cpu/mcheck/mce_32.c index dfaebce3633e..3552119b091d 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_32.c +++ b/arch/x86/kernel/cpu/mcheck/mce_32.c | |||
@@ -60,20 +60,6 @@ void mcheck_init(struct cpuinfo_x86 *c) | |||
60 | } | 60 | } |
61 | } | 61 | } |
62 | 62 | ||
63 | static unsigned long old_cr4 __initdata; | ||
64 | |||
65 | void __init stop_mce(void) | ||
66 | { | ||
67 | old_cr4 = read_cr4(); | ||
68 | clear_in_cr4(X86_CR4_MCE); | ||
69 | } | ||
70 | |||
71 | void __init restart_mce(void) | ||
72 | { | ||
73 | if (old_cr4 & X86_CR4_MCE) | ||
74 | set_in_cr4(X86_CR4_MCE); | ||
75 | } | ||
76 | |||
77 | static int __init mcheck_disable(char *str) | 63 | static int __init mcheck_disable(char *str) |
78 | { | 64 | { |
79 | mce_disabled = 1; | 65 | mce_disabled = 1; |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c index fe79985ce0f2..ca14604611ec 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_64.c | |||
@@ -3,6 +3,8 @@ | |||
3 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. | 3 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
4 | * Rest from unknown author(s). | 4 | * Rest from unknown author(s). |
5 | * 2004 Andi Kleen. Rewrote most of it. | 5 | * 2004 Andi Kleen. Rewrote most of it. |
6 | * Copyright 2008 Intel Corporation | ||
7 | * Author: Andi Kleen | ||
6 | */ | 8 | */ |
7 | 9 | ||
8 | #include <linux/init.h> | 10 | #include <linux/init.h> |
@@ -24,6 +26,9 @@ | |||
24 | #include <linux/ctype.h> | 26 | #include <linux/ctype.h> |
25 | #include <linux/kmod.h> | 27 | #include <linux/kmod.h> |
26 | #include <linux/kdebug.h> | 28 | #include <linux/kdebug.h> |
29 | #include <linux/kobject.h> | ||
30 | #include <linux/sysfs.h> | ||
31 | #include <linux/ratelimit.h> | ||
27 | #include <asm/processor.h> | 32 | #include <asm/processor.h> |
28 | #include <asm/msr.h> | 33 | #include <asm/msr.h> |
29 | #include <asm/mce.h> | 34 | #include <asm/mce.h> |
@@ -32,7 +37,6 @@ | |||
32 | #include <asm/idle.h> | 37 | #include <asm/idle.h> |
33 | 38 | ||
34 | #define MISC_MCELOG_MINOR 227 | 39 | #define MISC_MCELOG_MINOR 227 |
35 | #define NR_SYSFS_BANKS 6 | ||
36 | 40 | ||
37 | atomic_t mce_entry; | 41 | atomic_t mce_entry; |
38 | 42 | ||
@@ -47,7 +51,7 @@ static int mce_dont_init; | |||
47 | */ | 51 | */ |
48 | static int tolerant = 1; | 52 | static int tolerant = 1; |
49 | static int banks; | 53 | static int banks; |
50 | static unsigned long bank[NR_SYSFS_BANKS] = { [0 ... NR_SYSFS_BANKS-1] = ~0UL }; | 54 | static u64 *bank; |
51 | static unsigned long notify_user; | 55 | static unsigned long notify_user; |
52 | static int rip_msr; | 56 | static int rip_msr; |
53 | static int mce_bootlog = -1; | 57 | static int mce_bootlog = -1; |
@@ -58,6 +62,19 @@ static char *trigger_argv[2] = { trigger, NULL }; | |||
58 | 62 | ||
59 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); | 63 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
60 | 64 | ||
65 | /* MCA banks polled by the period polling timer for corrected events */ | ||
66 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | ||
67 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | ||
68 | }; | ||
69 | |||
70 | /* Do initial initialization of a struct mce */ | ||
71 | void mce_setup(struct mce *m) | ||
72 | { | ||
73 | memset(m, 0, sizeof(struct mce)); | ||
74 | m->cpu = smp_processor_id(); | ||
75 | rdtscll(m->tsc); | ||
76 | } | ||
77 | |||
61 | /* | 78 | /* |
62 | * Lockless MCE logging infrastructure. | 79 | * Lockless MCE logging infrastructure. |
63 | * This avoids deadlocks on printk locks without having to break locks. Also | 80 | * This avoids deadlocks on printk locks without having to break locks. Also |
@@ -119,11 +136,11 @@ static void print_mce(struct mce *m) | |||
119 | print_symbol("{%s}", m->ip); | 136 | print_symbol("{%s}", m->ip); |
120 | printk("\n"); | 137 | printk("\n"); |
121 | } | 138 | } |
122 | printk(KERN_EMERG "TSC %Lx ", m->tsc); | 139 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
123 | if (m->addr) | 140 | if (m->addr) |
124 | printk("ADDR %Lx ", m->addr); | 141 | printk("ADDR %llx ", m->addr); |
125 | if (m->misc) | 142 | if (m->misc) |
126 | printk("MISC %Lx ", m->misc); | 143 | printk("MISC %llx ", m->misc); |
127 | printk("\n"); | 144 | printk("\n"); |
128 | printk(KERN_EMERG "This is not a software problem!\n"); | 145 | printk(KERN_EMERG "This is not a software problem!\n"); |
129 | printk(KERN_EMERG "Run through mcelog --ascii to decode " | 146 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
@@ -149,8 +166,10 @@ static void mce_panic(char *msg, struct mce *backup, unsigned long start) | |||
149 | panic(msg); | 166 | panic(msg); |
150 | } | 167 | } |
151 | 168 | ||
152 | static int mce_available(struct cpuinfo_x86 *c) | 169 | int mce_available(struct cpuinfo_x86 *c) |
153 | { | 170 | { |
171 | if (mce_dont_init) | ||
172 | return 0; | ||
154 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); | 173 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
155 | } | 174 | } |
156 | 175 | ||
@@ -172,7 +191,77 @@ static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) | |||
172 | } | 191 | } |
173 | 192 | ||
174 | /* | 193 | /* |
175 | * The actual machine check handler | 194 | * Poll for corrected events or events that happened before reset. |
195 | * Those are just logged through /dev/mcelog. | ||
196 | * | ||
197 | * This is executed in standard interrupt context. | ||
198 | */ | ||
199 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) | ||
200 | { | ||
201 | struct mce m; | ||
202 | int i; | ||
203 | |||
204 | mce_setup(&m); | ||
205 | |||
206 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | ||
207 | for (i = 0; i < banks; i++) { | ||
208 | if (!bank[i] || !test_bit(i, *b)) | ||
209 | continue; | ||
210 | |||
211 | m.misc = 0; | ||
212 | m.addr = 0; | ||
213 | m.bank = i; | ||
214 | m.tsc = 0; | ||
215 | |||
216 | barrier(); | ||
217 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | ||
218 | if (!(m.status & MCI_STATUS_VAL)) | ||
219 | continue; | ||
220 | |||
221 | /* | ||
222 | * Uncorrected events are handled by the exception handler | ||
223 | * when it is enabled. But when the exception is disabled log | ||
224 | * everything. | ||
225 | * | ||
226 | * TBD do the same check for MCI_STATUS_EN here? | ||
227 | */ | ||
228 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | ||
229 | continue; | ||
230 | |||
231 | if (m.status & MCI_STATUS_MISCV) | ||
232 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | ||
233 | if (m.status & MCI_STATUS_ADDRV) | ||
234 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | ||
235 | |||
236 | if (!(flags & MCP_TIMESTAMP)) | ||
237 | m.tsc = 0; | ||
238 | /* | ||
239 | * Don't get the IP here because it's unlikely to | ||
240 | * have anything to do with the actual error location. | ||
241 | */ | ||
242 | |||
243 | mce_log(&m); | ||
244 | add_taint(TAINT_MACHINE_CHECK); | ||
245 | |||
246 | /* | ||
247 | * Clear state for this bank. | ||
248 | */ | ||
249 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | ||
250 | } | ||
251 | |||
252 | /* | ||
253 | * Don't clear MCG_STATUS here because it's only defined for | ||
254 | * exceptions. | ||
255 | */ | ||
256 | } | ||
257 | |||
258 | /* | ||
259 | * The actual machine check handler. This only handles real | ||
260 | * exceptions when something got corrupted coming in through int 18. | ||
261 | * | ||
262 | * This is executed in NMI context not subject to normal locking rules. This | ||
263 | * implies that most kernel services cannot be safely used. Don't even | ||
264 | * think about putting a printk in there! | ||
176 | */ | 265 | */ |
177 | void do_machine_check(struct pt_regs * regs, long error_code) | 266 | void do_machine_check(struct pt_regs * regs, long error_code) |
178 | { | 267 | { |
@@ -190,17 +279,18 @@ void do_machine_check(struct pt_regs * regs, long error_code) | |||
190 | * error. | 279 | * error. |
191 | */ | 280 | */ |
192 | int kill_it = 0; | 281 | int kill_it = 0; |
282 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); | ||
193 | 283 | ||
194 | atomic_inc(&mce_entry); | 284 | atomic_inc(&mce_entry); |
195 | 285 | ||
196 | if ((regs | 286 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
197 | && notify_die(DIE_NMI, "machine check", regs, error_code, | ||
198 | 18, SIGKILL) == NOTIFY_STOP) | 287 | 18, SIGKILL) == NOTIFY_STOP) |
199 | || !banks) | 288 | goto out2; |
289 | if (!banks) | ||
200 | goto out2; | 290 | goto out2; |
201 | 291 | ||
202 | memset(&m, 0, sizeof(struct mce)); | 292 | mce_setup(&m); |
203 | m.cpu = smp_processor_id(); | 293 | |
204 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | 294 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
205 | /* if the restart IP is not valid, we're done for */ | 295 | /* if the restart IP is not valid, we're done for */ |
206 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | 296 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
@@ -210,18 +300,32 @@ void do_machine_check(struct pt_regs * regs, long error_code) | |||
210 | barrier(); | 300 | barrier(); |
211 | 301 | ||
212 | for (i = 0; i < banks; i++) { | 302 | for (i = 0; i < banks; i++) { |
213 | if (i < NR_SYSFS_BANKS && !bank[i]) | 303 | __clear_bit(i, toclear); |
304 | if (!bank[i]) | ||
214 | continue; | 305 | continue; |
215 | 306 | ||
216 | m.misc = 0; | 307 | m.misc = 0; |
217 | m.addr = 0; | 308 | m.addr = 0; |
218 | m.bank = i; | 309 | m.bank = i; |
219 | m.tsc = 0; | ||
220 | 310 | ||
221 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | 311 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); |
222 | if ((m.status & MCI_STATUS_VAL) == 0) | 312 | if ((m.status & MCI_STATUS_VAL) == 0) |
223 | continue; | 313 | continue; |
224 | 314 | ||
315 | /* | ||
316 | * Non uncorrected errors are handled by machine_check_poll | ||
317 | * Leave them alone. | ||
318 | */ | ||
319 | if ((m.status & MCI_STATUS_UC) == 0) | ||
320 | continue; | ||
321 | |||
322 | /* | ||
323 | * Set taint even when machine check was not enabled. | ||
324 | */ | ||
325 | add_taint(TAINT_MACHINE_CHECK); | ||
326 | |||
327 | __set_bit(i, toclear); | ||
328 | |||
225 | if (m.status & MCI_STATUS_EN) { | 329 | if (m.status & MCI_STATUS_EN) { |
226 | /* if PCC was set, there's no way out */ | 330 | /* if PCC was set, there's no way out */ |
227 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | 331 | no_way_out |= !!(m.status & MCI_STATUS_PCC); |
@@ -235,6 +339,12 @@ void do_machine_check(struct pt_regs * regs, long error_code) | |||
235 | no_way_out = 1; | 339 | no_way_out = 1; |
236 | kill_it = 1; | 340 | kill_it = 1; |
237 | } | 341 | } |
342 | } else { | ||
343 | /* | ||
344 | * Machine check event was not enabled. Clear, but | ||
345 | * ignore. | ||
346 | */ | ||
347 | continue; | ||
238 | } | 348 | } |
239 | 349 | ||
240 | if (m.status & MCI_STATUS_MISCV) | 350 | if (m.status & MCI_STATUS_MISCV) |
@@ -243,10 +353,7 @@ void do_machine_check(struct pt_regs * regs, long error_code) | |||
243 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | 353 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); |
244 | 354 | ||
245 | mce_get_rip(&m, regs); | 355 | mce_get_rip(&m, regs); |
246 | if (error_code >= 0) | 356 | mce_log(&m); |
247 | rdtscll(m.tsc); | ||
248 | if (error_code != -2) | ||
249 | mce_log(&m); | ||
250 | 357 | ||
251 | /* Did this bank cause the exception? */ | 358 | /* Did this bank cause the exception? */ |
252 | /* Assume that the bank with uncorrectable errors did it, | 359 | /* Assume that the bank with uncorrectable errors did it, |
@@ -255,14 +362,8 @@ void do_machine_check(struct pt_regs * regs, long error_code) | |||
255 | panicm = m; | 362 | panicm = m; |
256 | panicm_found = 1; | 363 | panicm_found = 1; |
257 | } | 364 | } |
258 | |||
259 | add_taint(TAINT_MACHINE_CHECK); | ||
260 | } | 365 | } |
261 | 366 | ||
262 | /* Never do anything final in the polling timer */ | ||
263 | if (!regs) | ||
264 | goto out; | ||
265 | |||
266 | /* If we didn't find an uncorrectable error, pick | 367 | /* If we didn't find an uncorrectable error, pick |
267 | the last one (shouldn't happen, just being safe). */ | 368 | the last one (shouldn't happen, just being safe). */ |
268 | if (!panicm_found) | 369 | if (!panicm_found) |
@@ -309,10 +410,11 @@ void do_machine_check(struct pt_regs * regs, long error_code) | |||
309 | /* notify userspace ASAP */ | 410 | /* notify userspace ASAP */ |
310 | set_thread_flag(TIF_MCE_NOTIFY); | 411 | set_thread_flag(TIF_MCE_NOTIFY); |
311 | 412 | ||
312 | out: | ||
313 | /* the last thing we do is clear state */ | 413 | /* the last thing we do is clear state */ |
314 | for (i = 0; i < banks; i++) | 414 | for (i = 0; i < banks; i++) { |
315 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | 415 | if (test_bit(i, toclear)) |
416 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | ||
417 | } | ||
316 | wrmsrl(MSR_IA32_MCG_STATUS, 0); | 418 | wrmsrl(MSR_IA32_MCG_STATUS, 0); |
317 | out2: | 419 | out2: |
318 | atomic_dec(&mce_entry); | 420 | atomic_dec(&mce_entry); |
@@ -332,15 +434,13 @@ void do_machine_check(struct pt_regs * regs, long error_code) | |||
332 | * and historically has been the register value of the | 434 | * and historically has been the register value of the |
333 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | 435 | * MSR_IA32_THERMAL_STATUS (Intel) msr. |
334 | */ | 436 | */ |
335 | void mce_log_therm_throt_event(unsigned int cpu, __u64 status) | 437 | void mce_log_therm_throt_event(__u64 status) |
336 | { | 438 | { |
337 | struct mce m; | 439 | struct mce m; |
338 | 440 | ||
339 | memset(&m, 0, sizeof(m)); | 441 | mce_setup(&m); |
340 | m.cpu = cpu; | ||
341 | m.bank = MCE_THERMAL_BANK; | 442 | m.bank = MCE_THERMAL_BANK; |
342 | m.status = status; | 443 | m.status = status; |
343 | rdtscll(m.tsc); | ||
344 | mce_log(&m); | 444 | mce_log(&m); |
345 | } | 445 | } |
346 | #endif /* CONFIG_X86_MCE_INTEL */ | 446 | #endif /* CONFIG_X86_MCE_INTEL */ |
@@ -353,18 +453,18 @@ void mce_log_therm_throt_event(unsigned int cpu, __u64 status) | |||
353 | 453 | ||
354 | static int check_interval = 5 * 60; /* 5 minutes */ | 454 | static int check_interval = 5 * 60; /* 5 minutes */ |
355 | static int next_interval; /* in jiffies */ | 455 | static int next_interval; /* in jiffies */ |
356 | static void mcheck_timer(struct work_struct *work); | 456 | static void mcheck_timer(unsigned long); |
357 | static DECLARE_DELAYED_WORK(mcheck_work, mcheck_timer); | 457 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
358 | 458 | ||
359 | static void mcheck_check_cpu(void *info) | 459 | static void mcheck_timer(unsigned long data) |
360 | { | 460 | { |
361 | if (mce_available(¤t_cpu_data)) | 461 | struct timer_list *t = &per_cpu(mce_timer, data); |
362 | do_machine_check(NULL, 0); | ||
363 | } | ||
364 | 462 | ||
365 | static void mcheck_timer(struct work_struct *work) | 463 | WARN_ON(smp_processor_id() != data); |
366 | { | 464 | |
367 | on_each_cpu(mcheck_check_cpu, NULL, 1); | 465 | if (mce_available(¤t_cpu_data)) |
466 | machine_check_poll(MCP_TIMESTAMP, | ||
467 | &__get_cpu_var(mce_poll_banks)); | ||
368 | 468 | ||
369 | /* | 469 | /* |
370 | * Alert userspace if needed. If we logged an MCE, reduce the | 470 | * Alert userspace if needed. If we logged an MCE, reduce the |
@@ -377,31 +477,41 @@ static void mcheck_timer(struct work_struct *work) | |||
377 | (int)round_jiffies_relative(check_interval*HZ)); | 477 | (int)round_jiffies_relative(check_interval*HZ)); |
378 | } | 478 | } |
379 | 479 | ||
380 | schedule_delayed_work(&mcheck_work, next_interval); | 480 | t->expires = jiffies + next_interval; |
481 | add_timer(t); | ||
482 | } | ||
483 | |||
484 | static void mce_do_trigger(struct work_struct *work) | ||
485 | { | ||
486 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | ||
381 | } | 487 | } |
382 | 488 | ||
489 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | ||
490 | |||
383 | /* | 491 | /* |
384 | * This is only called from process context. This is where we do | 492 | * Notify the user(s) about new machine check events. |
385 | * anything we need to alert userspace about new MCEs. This is called | 493 | * Can be called from interrupt context, but not from machine check/NMI |
386 | * directly from the poller and also from entry.S and idle, thanks to | 494 | * context. |
387 | * TIF_MCE_NOTIFY. | ||
388 | */ | 495 | */ |
389 | int mce_notify_user(void) | 496 | int mce_notify_user(void) |
390 | { | 497 | { |
498 | /* Not more than two messages every minute */ | ||
499 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | ||
500 | |||
391 | clear_thread_flag(TIF_MCE_NOTIFY); | 501 | clear_thread_flag(TIF_MCE_NOTIFY); |
392 | if (test_and_clear_bit(0, ¬ify_user)) { | 502 | if (test_and_clear_bit(0, ¬ify_user)) { |
393 | static unsigned long last_print; | ||
394 | unsigned long now = jiffies; | ||
395 | |||
396 | wake_up_interruptible(&mce_wait); | 503 | wake_up_interruptible(&mce_wait); |
397 | if (trigger[0]) | ||
398 | call_usermodehelper(trigger, trigger_argv, NULL, | ||
399 | UMH_NO_WAIT); | ||
400 | 504 | ||
401 | if (time_after_eq(now, last_print + (check_interval*HZ))) { | 505 | /* |
402 | last_print = now; | 506 | * There is no risk of missing notifications because |
507 | * work_pending is always cleared before the function is | ||
508 | * executed. | ||
509 | */ | ||
510 | if (trigger[0] && !work_pending(&mce_trigger_work)) | ||
511 | schedule_work(&mce_trigger_work); | ||
512 | |||
513 | if (__ratelimit(&ratelimit)) | ||
403 | printk(KERN_INFO "Machine check events logged\n"); | 514 | printk(KERN_INFO "Machine check events logged\n"); |
404 | } | ||
405 | 515 | ||
406 | return 1; | 516 | return 1; |
407 | } | 517 | } |
@@ -425,63 +535,78 @@ static struct notifier_block mce_idle_notifier = { | |||
425 | 535 | ||
426 | static __init int periodic_mcheck_init(void) | 536 | static __init int periodic_mcheck_init(void) |
427 | { | 537 | { |
428 | next_interval = check_interval * HZ; | 538 | idle_notifier_register(&mce_idle_notifier); |
429 | if (next_interval) | 539 | return 0; |
430 | schedule_delayed_work(&mcheck_work, | ||
431 | round_jiffies_relative(next_interval)); | ||
432 | idle_notifier_register(&mce_idle_notifier); | ||
433 | return 0; | ||
434 | } | 540 | } |
435 | __initcall(periodic_mcheck_init); | 541 | __initcall(periodic_mcheck_init); |
436 | 542 | ||
437 | |||
438 | /* | 543 | /* |
439 | * Initialize Machine Checks for a CPU. | 544 | * Initialize Machine Checks for a CPU. |
440 | */ | 545 | */ |
441 | static void mce_init(void *dummy) | 546 | static int mce_cap_init(void) |
442 | { | 547 | { |
443 | u64 cap; | 548 | u64 cap; |
444 | int i; | 549 | unsigned b; |
445 | 550 | ||
446 | rdmsrl(MSR_IA32_MCG_CAP, cap); | 551 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
447 | banks = cap & 0xff; | 552 | b = cap & 0xff; |
448 | if (banks > MCE_EXTENDED_BANK) { | 553 | if (b > MAX_NR_BANKS) { |
449 | banks = MCE_EXTENDED_BANK; | 554 | printk(KERN_WARNING |
450 | printk(KERN_INFO "MCE: warning: using only %d banks\n", | 555 | "MCE: Using only %u machine check banks out of %u\n", |
451 | MCE_EXTENDED_BANK); | 556 | MAX_NR_BANKS, b); |
557 | b = MAX_NR_BANKS; | ||
452 | } | 558 | } |
559 | |||
560 | /* Don't support asymmetric configurations today */ | ||
561 | WARN_ON(banks != 0 && b != banks); | ||
562 | banks = b; | ||
563 | if (!bank) { | ||
564 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | ||
565 | if (!bank) | ||
566 | return -ENOMEM; | ||
567 | memset(bank, 0xff, banks * sizeof(u64)); | ||
568 | } | ||
569 | |||
453 | /* Use accurate RIP reporting if available. */ | 570 | /* Use accurate RIP reporting if available. */ |
454 | if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) | 571 | if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) |
455 | rip_msr = MSR_IA32_MCG_EIP; | 572 | rip_msr = MSR_IA32_MCG_EIP; |
456 | 573 | ||
457 | /* Log the machine checks left over from the previous reset. | 574 | return 0; |
458 | This also clears all registers */ | 575 | } |
459 | do_machine_check(NULL, mce_bootlog ? -1 : -2); | 576 | |
577 | static void mce_init(void *dummy) | ||
578 | { | ||
579 | u64 cap; | ||
580 | int i; | ||
581 | mce_banks_t all_banks; | ||
582 | |||
583 | /* | ||
584 | * Log the machine checks left over from the previous reset. | ||
585 | */ | ||
586 | bitmap_fill(all_banks, MAX_NR_BANKS); | ||
587 | machine_check_poll(MCP_UC, &all_banks); | ||
460 | 588 | ||
461 | set_in_cr4(X86_CR4_MCE); | 589 | set_in_cr4(X86_CR4_MCE); |
462 | 590 | ||
591 | rdmsrl(MSR_IA32_MCG_CAP, cap); | ||
463 | if (cap & MCG_CTL_P) | 592 | if (cap & MCG_CTL_P) |
464 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | 593 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); |
465 | 594 | ||
466 | for (i = 0; i < banks; i++) { | 595 | for (i = 0; i < banks; i++) { |
467 | if (i < NR_SYSFS_BANKS) | 596 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
468 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); | ||
469 | else | ||
470 | wrmsrl(MSR_IA32_MC0_CTL+4*i, ~0UL); | ||
471 | |||
472 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | 597 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
473 | } | 598 | } |
474 | } | 599 | } |
475 | 600 | ||
476 | /* Add per CPU specific workarounds here */ | 601 | /* Add per CPU specific workarounds here */ |
477 | static void __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c) | 602 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
478 | { | 603 | { |
479 | /* This should be disabled by the BIOS, but isn't always */ | 604 | /* This should be disabled by the BIOS, but isn't always */ |
480 | if (c->x86_vendor == X86_VENDOR_AMD) { | 605 | if (c->x86_vendor == X86_VENDOR_AMD) { |
481 | if(c->x86 == 15) | 606 | if (c->x86 == 15 && banks > 4) |
482 | /* disable GART TBL walk error reporting, which trips off | 607 | /* disable GART TBL walk error reporting, which trips off |
483 | incorrectly with the IOMMU & 3ware & Cerberus. */ | 608 | incorrectly with the IOMMU & 3ware & Cerberus. */ |
484 | clear_bit(10, &bank[4]); | 609 | clear_bit(10, (unsigned long *)&bank[4]); |
485 | if(c->x86 <= 17 && mce_bootlog < 0) | 610 | if(c->x86 <= 17 && mce_bootlog < 0) |
486 | /* Lots of broken BIOS around that don't clear them | 611 | /* Lots of broken BIOS around that don't clear them |
487 | by default and leave crap in there. Don't log. */ | 612 | by default and leave crap in there. Don't log. */ |
@@ -504,20 +629,38 @@ static void mce_cpu_features(struct cpuinfo_x86 *c) | |||
504 | } | 629 | } |
505 | } | 630 | } |
506 | 631 | ||
632 | static void mce_init_timer(void) | ||
633 | { | ||
634 | struct timer_list *t = &__get_cpu_var(mce_timer); | ||
635 | |||
636 | /* data race harmless because everyone sets to the same value */ | ||
637 | if (!next_interval) | ||
638 | next_interval = check_interval * HZ; | ||
639 | if (!next_interval) | ||
640 | return; | ||
641 | setup_timer(t, mcheck_timer, smp_processor_id()); | ||
642 | t->expires = round_jiffies(jiffies + next_interval); | ||
643 | add_timer(t); | ||
644 | } | ||
645 | |||
507 | /* | 646 | /* |
508 | * Called for each booted CPU to set up machine checks. | 647 | * Called for each booted CPU to set up machine checks. |
509 | * Must be called with preempt off. | 648 | * Must be called with preempt off. |
510 | */ | 649 | */ |
511 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) | 650 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
512 | { | 651 | { |
513 | mce_cpu_quirks(c); | 652 | if (!mce_available(c)) |
653 | return; | ||
514 | 654 | ||
515 | if (mce_dont_init || | 655 | if (mce_cap_init() < 0) { |
516 | !mce_available(c)) | 656 | mce_dont_init = 1; |
517 | return; | 657 | return; |
658 | } | ||
659 | mce_cpu_quirks(c); | ||
518 | 660 | ||
519 | mce_init(NULL); | 661 | mce_init(NULL); |
520 | mce_cpu_features(c); | 662 | mce_cpu_features(c); |
663 | mce_init_timer(); | ||
521 | } | 664 | } |
522 | 665 | ||
523 | /* | 666 | /* |
@@ -573,7 +716,7 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, | |||
573 | { | 716 | { |
574 | unsigned long *cpu_tsc; | 717 | unsigned long *cpu_tsc; |
575 | static DEFINE_MUTEX(mce_read_mutex); | 718 | static DEFINE_MUTEX(mce_read_mutex); |
576 | unsigned next; | 719 | unsigned prev, next; |
577 | char __user *buf = ubuf; | 720 | char __user *buf = ubuf; |
578 | int i, err; | 721 | int i, err; |
579 | 722 | ||
@@ -592,25 +735,32 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, | |||
592 | } | 735 | } |
593 | 736 | ||
594 | err = 0; | 737 | err = 0; |
595 | for (i = 0; i < next; i++) { | 738 | prev = 0; |
596 | unsigned long start = jiffies; | 739 | do { |
597 | 740 | for (i = prev; i < next; i++) { | |
598 | while (!mcelog.entry[i].finished) { | 741 | unsigned long start = jiffies; |
599 | if (time_after_eq(jiffies, start + 2)) { | 742 | |
600 | memset(mcelog.entry + i,0, sizeof(struct mce)); | 743 | while (!mcelog.entry[i].finished) { |
601 | goto timeout; | 744 | if (time_after_eq(jiffies, start + 2)) { |
745 | memset(mcelog.entry + i, 0, | ||
746 | sizeof(struct mce)); | ||
747 | goto timeout; | ||
748 | } | ||
749 | cpu_relax(); | ||
602 | } | 750 | } |
603 | cpu_relax(); | 751 | smp_rmb(); |
752 | err |= copy_to_user(buf, mcelog.entry + i, | ||
753 | sizeof(struct mce)); | ||
754 | buf += sizeof(struct mce); | ||
755 | timeout: | ||
756 | ; | ||
604 | } | 757 | } |
605 | smp_rmb(); | ||
606 | err |= copy_to_user(buf, mcelog.entry + i, sizeof(struct mce)); | ||
607 | buf += sizeof(struct mce); | ||
608 | timeout: | ||
609 | ; | ||
610 | } | ||
611 | 758 | ||
612 | memset(mcelog.entry, 0, next * sizeof(struct mce)); | 759 | memset(mcelog.entry + prev, 0, |
613 | mcelog.next = 0; | 760 | (next - prev) * sizeof(struct mce)); |
761 | prev = next; | ||
762 | next = cmpxchg(&mcelog.next, prev, 0); | ||
763 | } while (next != prev); | ||
614 | 764 | ||
615 | synchronize_sched(); | 765 | synchronize_sched(); |
616 | 766 | ||
@@ -680,20 +830,6 @@ static struct miscdevice mce_log_device = { | |||
680 | &mce_chrdev_ops, | 830 | &mce_chrdev_ops, |
681 | }; | 831 | }; |
682 | 832 | ||
683 | static unsigned long old_cr4 __initdata; | ||
684 | |||
685 | void __init stop_mce(void) | ||
686 | { | ||
687 | old_cr4 = read_cr4(); | ||
688 | clear_in_cr4(X86_CR4_MCE); | ||
689 | } | ||
690 | |||
691 | void __init restart_mce(void) | ||
692 | { | ||
693 | if (old_cr4 & X86_CR4_MCE) | ||
694 | set_in_cr4(X86_CR4_MCE); | ||
695 | } | ||
696 | |||
697 | /* | 833 | /* |
698 | * Old style boot options parsing. Only for compatibility. | 834 | * Old style boot options parsing. Only for compatibility. |
699 | */ | 835 | */ |
@@ -703,8 +839,7 @@ static int __init mcheck_disable(char *str) | |||
703 | return 1; | 839 | return 1; |
704 | } | 840 | } |
705 | 841 | ||
706 | /* mce=off disables machine check. Note you can re-enable it later | 842 | /* mce=off disables machine check. |
707 | using sysfs. | ||
708 | mce=TOLERANCELEVEL (number, see above) | 843 | mce=TOLERANCELEVEL (number, see above) |
709 | mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | 844 | mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
710 | mce=nobootlog Don't log MCEs from before booting. */ | 845 | mce=nobootlog Don't log MCEs from before booting. */ |
@@ -728,6 +863,29 @@ __setup("mce=", mcheck_enable); | |||
728 | * Sysfs support | 863 | * Sysfs support |
729 | */ | 864 | */ |
730 | 865 | ||
866 | /* | ||
867 | * Disable machine checks on suspend and shutdown. We can't really handle | ||
868 | * them later. | ||
869 | */ | ||
870 | static int mce_disable(void) | ||
871 | { | ||
872 | int i; | ||
873 | |||
874 | for (i = 0; i < banks; i++) | ||
875 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | ||
876 | return 0; | ||
877 | } | ||
878 | |||
879 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | ||
880 | { | ||
881 | return mce_disable(); | ||
882 | } | ||
883 | |||
884 | static int mce_shutdown(struct sys_device *dev) | ||
885 | { | ||
886 | return mce_disable(); | ||
887 | } | ||
888 | |||
731 | /* On resume clear all MCE state. Don't want to see leftovers from the BIOS. | 889 | /* On resume clear all MCE state. Don't want to see leftovers from the BIOS. |
732 | Only one CPU is active at this time, the others get readded later using | 890 | Only one CPU is active at this time, the others get readded later using |
733 | CPU hotplug. */ | 891 | CPU hotplug. */ |
@@ -738,20 +896,24 @@ static int mce_resume(struct sys_device *dev) | |||
738 | return 0; | 896 | return 0; |
739 | } | 897 | } |
740 | 898 | ||
899 | static void mce_cpu_restart(void *data) | ||
900 | { | ||
901 | del_timer_sync(&__get_cpu_var(mce_timer)); | ||
902 | if (mce_available(¤t_cpu_data)) | ||
903 | mce_init(NULL); | ||
904 | mce_init_timer(); | ||
905 | } | ||
906 | |||
741 | /* Reinit MCEs after user configuration changes */ | 907 | /* Reinit MCEs after user configuration changes */ |
742 | static void mce_restart(void) | 908 | static void mce_restart(void) |
743 | { | 909 | { |
744 | if (next_interval) | ||
745 | cancel_delayed_work(&mcheck_work); | ||
746 | /* Timer race is harmless here */ | ||
747 | on_each_cpu(mce_init, NULL, 1); | ||
748 | next_interval = check_interval * HZ; | 910 | next_interval = check_interval * HZ; |
749 | if (next_interval) | 911 | on_each_cpu(mce_cpu_restart, NULL, 1); |
750 | schedule_delayed_work(&mcheck_work, | ||
751 | round_jiffies_relative(next_interval)); | ||
752 | } | 912 | } |
753 | 913 | ||
754 | static struct sysdev_class mce_sysclass = { | 914 | static struct sysdev_class mce_sysclass = { |
915 | .suspend = mce_suspend, | ||
916 | .shutdown = mce_shutdown, | ||
755 | .resume = mce_resume, | 917 | .resume = mce_resume, |
756 | .name = "machinecheck", | 918 | .name = "machinecheck", |
757 | }; | 919 | }; |
@@ -778,16 +940,26 @@ void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu) __cpuinit | |||
778 | } \ | 940 | } \ |
779 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); | 941 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); |
780 | 942 | ||
781 | /* | 943 | static struct sysdev_attribute *bank_attrs; |
782 | * TBD should generate these dynamically based on number of available banks. | 944 | |
783 | * Have only 6 contol banks in /sysfs until then. | 945 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, |
784 | */ | 946 | char *buf) |
785 | ACCESSOR(bank0ctl,bank[0],mce_restart()) | 947 | { |
786 | ACCESSOR(bank1ctl,bank[1],mce_restart()) | 948 | u64 b = bank[attr - bank_attrs]; |
787 | ACCESSOR(bank2ctl,bank[2],mce_restart()) | 949 | return sprintf(buf, "%llx\n", b); |
788 | ACCESSOR(bank3ctl,bank[3],mce_restart()) | 950 | } |
789 | ACCESSOR(bank4ctl,bank[4],mce_restart()) | 951 | |
790 | ACCESSOR(bank5ctl,bank[5],mce_restart()) | 952 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, |
953 | const char *buf, size_t siz) | ||
954 | { | ||
955 | char *end; | ||
956 | u64 new = simple_strtoull(buf, &end, 0); | ||
957 | if (end == buf) | ||
958 | return -EINVAL; | ||
959 | bank[attr - bank_attrs] = new; | ||
960 | mce_restart(); | ||
961 | return end-buf; | ||
962 | } | ||
791 | 963 | ||
792 | static ssize_t show_trigger(struct sys_device *s, struct sysdev_attribute *attr, | 964 | static ssize_t show_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
793 | char *buf) | 965 | char *buf) |
@@ -814,8 +986,6 @@ static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); | |||
814 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); | 986 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
815 | ACCESSOR(check_interval,check_interval,mce_restart()) | 987 | ACCESSOR(check_interval,check_interval,mce_restart()) |
816 | static struct sysdev_attribute *mce_attributes[] = { | 988 | static struct sysdev_attribute *mce_attributes[] = { |
817 | &attr_bank0ctl, &attr_bank1ctl, &attr_bank2ctl, | ||
818 | &attr_bank3ctl, &attr_bank4ctl, &attr_bank5ctl, | ||
819 | &attr_tolerant.attr, &attr_check_interval, &attr_trigger, | 989 | &attr_tolerant.attr, &attr_check_interval, &attr_trigger, |
820 | NULL | 990 | NULL |
821 | }; | 991 | }; |
@@ -845,11 +1015,22 @@ static __cpuinit int mce_create_device(unsigned int cpu) | |||
845 | if (err) | 1015 | if (err) |
846 | goto error; | 1016 | goto error; |
847 | } | 1017 | } |
1018 | for (i = 0; i < banks; i++) { | ||
1019 | err = sysdev_create_file(&per_cpu(device_mce, cpu), | ||
1020 | &bank_attrs[i]); | ||
1021 | if (err) | ||
1022 | goto error2; | ||
1023 | } | ||
848 | cpu_set(cpu, mce_device_initialized); | 1024 | cpu_set(cpu, mce_device_initialized); |
849 | 1025 | ||
850 | return 0; | 1026 | return 0; |
1027 | error2: | ||
1028 | while (--i >= 0) { | ||
1029 | sysdev_remove_file(&per_cpu(device_mce, cpu), | ||
1030 | &bank_attrs[i]); | ||
1031 | } | ||
851 | error: | 1032 | error: |
852 | while (i--) { | 1033 | while (--i >= 0) { |
853 | sysdev_remove_file(&per_cpu(device_mce,cpu), | 1034 | sysdev_remove_file(&per_cpu(device_mce,cpu), |
854 | mce_attributes[i]); | 1035 | mce_attributes[i]); |
855 | } | 1036 | } |
@@ -868,15 +1049,46 @@ static __cpuinit void mce_remove_device(unsigned int cpu) | |||
868 | for (i = 0; mce_attributes[i]; i++) | 1049 | for (i = 0; mce_attributes[i]; i++) |
869 | sysdev_remove_file(&per_cpu(device_mce,cpu), | 1050 | sysdev_remove_file(&per_cpu(device_mce,cpu), |
870 | mce_attributes[i]); | 1051 | mce_attributes[i]); |
1052 | for (i = 0; i < banks; i++) | ||
1053 | sysdev_remove_file(&per_cpu(device_mce, cpu), | ||
1054 | &bank_attrs[i]); | ||
871 | sysdev_unregister(&per_cpu(device_mce,cpu)); | 1055 | sysdev_unregister(&per_cpu(device_mce,cpu)); |
872 | cpu_clear(cpu, mce_device_initialized); | 1056 | cpu_clear(cpu, mce_device_initialized); |
873 | } | 1057 | } |
874 | 1058 | ||
1059 | /* Make sure there are no machine checks on offlined CPUs. */ | ||
1060 | static void mce_disable_cpu(void *h) | ||
1061 | { | ||
1062 | int i; | ||
1063 | unsigned long action = *(unsigned long *)h; | ||
1064 | |||
1065 | if (!mce_available(¤t_cpu_data)) | ||
1066 | return; | ||
1067 | if (!(action & CPU_TASKS_FROZEN)) | ||
1068 | cmci_clear(); | ||
1069 | for (i = 0; i < banks; i++) | ||
1070 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | ||
1071 | } | ||
1072 | |||
1073 | static void mce_reenable_cpu(void *h) | ||
1074 | { | ||
1075 | int i; | ||
1076 | unsigned long action = *(unsigned long *)h; | ||
1077 | |||
1078 | if (!mce_available(¤t_cpu_data)) | ||
1079 | return; | ||
1080 | if (!(action & CPU_TASKS_FROZEN)) | ||
1081 | cmci_reenable(); | ||
1082 | for (i = 0; i < banks; i++) | ||
1083 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | ||
1084 | } | ||
1085 | |||
875 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ | 1086 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
876 | static int __cpuinit mce_cpu_callback(struct notifier_block *nfb, | 1087 | static int __cpuinit mce_cpu_callback(struct notifier_block *nfb, |
877 | unsigned long action, void *hcpu) | 1088 | unsigned long action, void *hcpu) |
878 | { | 1089 | { |
879 | unsigned int cpu = (unsigned long)hcpu; | 1090 | unsigned int cpu = (unsigned long)hcpu; |
1091 | struct timer_list *t = &per_cpu(mce_timer, cpu); | ||
880 | 1092 | ||
881 | switch (action) { | 1093 | switch (action) { |
882 | case CPU_ONLINE: | 1094 | case CPU_ONLINE: |
@@ -891,6 +1103,21 @@ static int __cpuinit mce_cpu_callback(struct notifier_block *nfb, | |||
891 | threshold_cpu_callback(action, cpu); | 1103 | threshold_cpu_callback(action, cpu); |
892 | mce_remove_device(cpu); | 1104 | mce_remove_device(cpu); |
893 | break; | 1105 | break; |
1106 | case CPU_DOWN_PREPARE: | ||
1107 | case CPU_DOWN_PREPARE_FROZEN: | ||
1108 | del_timer_sync(t); | ||
1109 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); | ||
1110 | break; | ||
1111 | case CPU_DOWN_FAILED: | ||
1112 | case CPU_DOWN_FAILED_FROZEN: | ||
1113 | t->expires = round_jiffies(jiffies + next_interval); | ||
1114 | add_timer_on(t, cpu); | ||
1115 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); | ||
1116 | break; | ||
1117 | case CPU_POST_DEAD: | ||
1118 | /* intentionally ignoring frozen here */ | ||
1119 | cmci_rediscover(cpu); | ||
1120 | break; | ||
894 | } | 1121 | } |
895 | return NOTIFY_OK; | 1122 | return NOTIFY_OK; |
896 | } | 1123 | } |
@@ -899,6 +1126,34 @@ static struct notifier_block mce_cpu_notifier __cpuinitdata = { | |||
899 | .notifier_call = mce_cpu_callback, | 1126 | .notifier_call = mce_cpu_callback, |
900 | }; | 1127 | }; |
901 | 1128 | ||
1129 | static __init int mce_init_banks(void) | ||
1130 | { | ||
1131 | int i; | ||
1132 | |||
1133 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | ||
1134 | GFP_KERNEL); | ||
1135 | if (!bank_attrs) | ||
1136 | return -ENOMEM; | ||
1137 | |||
1138 | for (i = 0; i < banks; i++) { | ||
1139 | struct sysdev_attribute *a = &bank_attrs[i]; | ||
1140 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | ||
1141 | if (!a->attr.name) | ||
1142 | goto nomem; | ||
1143 | a->attr.mode = 0644; | ||
1144 | a->show = show_bank; | ||
1145 | a->store = set_bank; | ||
1146 | } | ||
1147 | return 0; | ||
1148 | |||
1149 | nomem: | ||
1150 | while (--i >= 0) | ||
1151 | kfree(bank_attrs[i].attr.name); | ||
1152 | kfree(bank_attrs); | ||
1153 | bank_attrs = NULL; | ||
1154 | return -ENOMEM; | ||
1155 | } | ||
1156 | |||
902 | static __init int mce_init_device(void) | 1157 | static __init int mce_init_device(void) |
903 | { | 1158 | { |
904 | int err; | 1159 | int err; |
@@ -906,6 +1161,11 @@ static __init int mce_init_device(void) | |||
906 | 1161 | ||
907 | if (!mce_available(&boot_cpu_data)) | 1162 | if (!mce_available(&boot_cpu_data)) |
908 | return -EIO; | 1163 | return -EIO; |
1164 | |||
1165 | err = mce_init_banks(); | ||
1166 | if (err) | ||
1167 | return err; | ||
1168 | |||
909 | err = sysdev_class_register(&mce_sysclass); | 1169 | err = sysdev_class_register(&mce_sysclass); |
910 | if (err) | 1170 | if (err) |
911 | return err; | 1171 | return err; |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c index 9817506dd469..c5a32f92d07e 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c | |||
@@ -79,6 +79,8 @@ static unsigned char shared_bank[NR_BANKS] = { | |||
79 | 79 | ||
80 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ | 80 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ |
81 | 81 | ||
82 | static void amd_threshold_interrupt(void); | ||
83 | |||
82 | /* | 84 | /* |
83 | * CPU Initialization | 85 | * CPU Initialization |
84 | */ | 86 | */ |
@@ -174,6 +176,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) | |||
174 | tr.reset = 0; | 176 | tr.reset = 0; |
175 | tr.old_limit = 0; | 177 | tr.old_limit = 0; |
176 | threshold_restart_bank(&tr); | 178 | threshold_restart_bank(&tr); |
179 | |||
180 | mce_threshold_vector = amd_threshold_interrupt; | ||
177 | } | 181 | } |
178 | } | 182 | } |
179 | } | 183 | } |
@@ -187,19 +191,13 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) | |||
187 | * the interrupt goes off when error_count reaches threshold_limit. | 191 | * the interrupt goes off when error_count reaches threshold_limit. |
188 | * the handler will simply log mcelog w/ software defined bank number. | 192 | * the handler will simply log mcelog w/ software defined bank number. |
189 | */ | 193 | */ |
190 | asmlinkage void mce_threshold_interrupt(void) | 194 | static void amd_threshold_interrupt(void) |
191 | { | 195 | { |
192 | unsigned int bank, block; | 196 | unsigned int bank, block; |
193 | struct mce m; | 197 | struct mce m; |
194 | u32 low = 0, high = 0, address = 0; | 198 | u32 low = 0, high = 0, address = 0; |
195 | 199 | ||
196 | ack_APIC_irq(); | 200 | mce_setup(&m); |
197 | exit_idle(); | ||
198 | irq_enter(); | ||
199 | |||
200 | memset(&m, 0, sizeof(m)); | ||
201 | rdtscll(m.tsc); | ||
202 | m.cpu = smp_processor_id(); | ||
203 | 201 | ||
204 | /* assume first bank caused it */ | 202 | /* assume first bank caused it */ |
205 | for (bank = 0; bank < NR_BANKS; ++bank) { | 203 | for (bank = 0; bank < NR_BANKS; ++bank) { |
@@ -233,7 +231,8 @@ asmlinkage void mce_threshold_interrupt(void) | |||
233 | 231 | ||
234 | /* Log the machine check that caused the threshold | 232 | /* Log the machine check that caused the threshold |
235 | event. */ | 233 | event. */ |
236 | do_machine_check(NULL, 0); | 234 | machine_check_poll(MCP_TIMESTAMP, |
235 | &__get_cpu_var(mce_poll_banks)); | ||
237 | 236 | ||
238 | if (high & MASK_OVERFLOW_HI) { | 237 | if (high & MASK_OVERFLOW_HI) { |
239 | rdmsrl(address, m.misc); | 238 | rdmsrl(address, m.misc); |
@@ -243,13 +242,10 @@ asmlinkage void mce_threshold_interrupt(void) | |||
243 | + bank * NR_BLOCKS | 242 | + bank * NR_BLOCKS |
244 | + block; | 243 | + block; |
245 | mce_log(&m); | 244 | mce_log(&m); |
246 | goto out; | 245 | return; |
247 | } | 246 | } |
248 | } | 247 | } |
249 | } | 248 | } |
250 | out: | ||
251 | inc_irq_stat(irq_threshold_count); | ||
252 | irq_exit(); | ||
253 | } | 249 | } |
254 | 250 | ||
255 | /* | 251 | /* |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c index aa5e287c98e0..aaa7d9730938 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c | |||
@@ -1,6 +1,8 @@ | |||
1 | /* | 1 | /* |
2 | * Intel specific MCE features. | 2 | * Intel specific MCE features. |
3 | * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> | 3 | * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> |
4 | * Copyright (C) 2008, 2009 Intel Corporation | ||
5 | * Author: Andi Kleen | ||
4 | */ | 6 | */ |
5 | 7 | ||
6 | #include <linux/init.h> | 8 | #include <linux/init.h> |
@@ -13,6 +15,7 @@ | |||
13 | #include <asm/hw_irq.h> | 15 | #include <asm/hw_irq.h> |
14 | #include <asm/idle.h> | 16 | #include <asm/idle.h> |
15 | #include <asm/therm_throt.h> | 17 | #include <asm/therm_throt.h> |
18 | #include <asm/apic.h> | ||
16 | 19 | ||
17 | asmlinkage void smp_thermal_interrupt(void) | 20 | asmlinkage void smp_thermal_interrupt(void) |
18 | { | 21 | { |
@@ -25,7 +28,7 @@ asmlinkage void smp_thermal_interrupt(void) | |||
25 | 28 | ||
26 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | 29 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); |
27 | if (therm_throt_process(msr_val & 1)) | 30 | if (therm_throt_process(msr_val & 1)) |
28 | mce_log_therm_throt_event(smp_processor_id(), msr_val); | 31 | mce_log_therm_throt_event(msr_val); |
29 | 32 | ||
30 | inc_irq_stat(irq_thermal_count); | 33 | inc_irq_stat(irq_thermal_count); |
31 | irq_exit(); | 34 | irq_exit(); |
@@ -85,7 +88,209 @@ static void intel_init_thermal(struct cpuinfo_x86 *c) | |||
85 | return; | 88 | return; |
86 | } | 89 | } |
87 | 90 | ||
91 | /* | ||
92 | * Support for Intel Correct Machine Check Interrupts. This allows | ||
93 | * the CPU to raise an interrupt when a corrected machine check happened. | ||
94 | * Normally we pick those up using a regular polling timer. | ||
95 | * Also supports reliable discovery of shared banks. | ||
96 | */ | ||
97 | |||
98 | static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); | ||
99 | |||
100 | /* | ||
101 | * cmci_discover_lock protects against parallel discovery attempts | ||
102 | * which could race against each other. | ||
103 | */ | ||
104 | static DEFINE_SPINLOCK(cmci_discover_lock); | ||
105 | |||
106 | #define CMCI_THRESHOLD 1 | ||
107 | |||
108 | static int cmci_supported(int *banks) | ||
109 | { | ||
110 | u64 cap; | ||
111 | |||
112 | /* | ||
113 | * Vendor check is not strictly needed, but the initial | ||
114 | * initialization is vendor keyed and this | ||
115 | * makes sure none of the backdoors are entered otherwise. | ||
116 | */ | ||
117 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | ||
118 | return 0; | ||
119 | if (!cpu_has_apic || lapic_get_maxlvt() < 6) | ||
120 | return 0; | ||
121 | rdmsrl(MSR_IA32_MCG_CAP, cap); | ||
122 | *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); | ||
123 | return !!(cap & MCG_CMCI_P); | ||
124 | } | ||
125 | |||
126 | /* | ||
127 | * The interrupt handler. This is called on every event. | ||
128 | * Just call the poller directly to log any events. | ||
129 | * This could in theory increase the threshold under high load, | ||
130 | * but doesn't for now. | ||
131 | */ | ||
132 | static void intel_threshold_interrupt(void) | ||
133 | { | ||
134 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); | ||
135 | mce_notify_user(); | ||
136 | } | ||
137 | |||
138 | static void print_update(char *type, int *hdr, int num) | ||
139 | { | ||
140 | if (*hdr == 0) | ||
141 | printk(KERN_INFO "CPU %d MCA banks", smp_processor_id()); | ||
142 | *hdr = 1; | ||
143 | printk(KERN_CONT " %s:%d", type, num); | ||
144 | } | ||
145 | |||
146 | /* | ||
147 | * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks | ||
148 | * on this CPU. Use the algorithm recommended in the SDM to discover shared | ||
149 | * banks. | ||
150 | */ | ||
151 | static void cmci_discover(int banks, int boot) | ||
152 | { | ||
153 | unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned); | ||
154 | int hdr = 0; | ||
155 | int i; | ||
156 | |||
157 | spin_lock(&cmci_discover_lock); | ||
158 | for (i = 0; i < banks; i++) { | ||
159 | u64 val; | ||
160 | |||
161 | if (test_bit(i, owned)) | ||
162 | continue; | ||
163 | |||
164 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | ||
165 | |||
166 | /* Already owned by someone else? */ | ||
167 | if (val & CMCI_EN) { | ||
168 | if (test_and_clear_bit(i, owned) || boot) | ||
169 | print_update("SHD", &hdr, i); | ||
170 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | ||
171 | continue; | ||
172 | } | ||
173 | |||
174 | val |= CMCI_EN | CMCI_THRESHOLD; | ||
175 | wrmsrl(MSR_IA32_MC0_CTL2 + i, val); | ||
176 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | ||
177 | |||
178 | /* Did the enable bit stick? -- the bank supports CMCI */ | ||
179 | if (val & CMCI_EN) { | ||
180 | if (!test_and_set_bit(i, owned) || boot) | ||
181 | print_update("CMCI", &hdr, i); | ||
182 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | ||
183 | } else { | ||
184 | WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); | ||
185 | } | ||
186 | } | ||
187 | spin_unlock(&cmci_discover_lock); | ||
188 | if (hdr) | ||
189 | printk(KERN_CONT "\n"); | ||
190 | } | ||
191 | |||
192 | /* | ||
193 | * Just in case we missed an event during initialization check | ||
194 | * all the CMCI owned banks. | ||
195 | */ | ||
196 | void cmci_recheck(void) | ||
197 | { | ||
198 | unsigned long flags; | ||
199 | int banks; | ||
200 | |||
201 | if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks)) | ||
202 | return; | ||
203 | local_irq_save(flags); | ||
204 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); | ||
205 | local_irq_restore(flags); | ||
206 | } | ||
207 | |||
208 | /* | ||
209 | * Disable CMCI on this CPU for all banks it owns when it goes down. | ||
210 | * This allows other CPUs to claim the banks on rediscovery. | ||
211 | */ | ||
212 | void cmci_clear(void) | ||
213 | { | ||
214 | int i; | ||
215 | int banks; | ||
216 | u64 val; | ||
217 | |||
218 | if (!cmci_supported(&banks)) | ||
219 | return; | ||
220 | spin_lock(&cmci_discover_lock); | ||
221 | for (i = 0; i < banks; i++) { | ||
222 | if (!test_bit(i, __get_cpu_var(mce_banks_owned))) | ||
223 | continue; | ||
224 | /* Disable CMCI */ | ||
225 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | ||
226 | val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK); | ||
227 | wrmsrl(MSR_IA32_MC0_CTL2 + i, val); | ||
228 | __clear_bit(i, __get_cpu_var(mce_banks_owned)); | ||
229 | } | ||
230 | spin_unlock(&cmci_discover_lock); | ||
231 | } | ||
232 | |||
233 | /* | ||
234 | * After a CPU went down cycle through all the others and rediscover | ||
235 | * Must run in process context. | ||
236 | */ | ||
237 | void cmci_rediscover(int dying) | ||
238 | { | ||
239 | int banks; | ||
240 | int cpu; | ||
241 | cpumask_var_t old; | ||
242 | |||
243 | if (!cmci_supported(&banks)) | ||
244 | return; | ||
245 | if (!alloc_cpumask_var(&old, GFP_KERNEL)) | ||
246 | return; | ||
247 | cpumask_copy(old, ¤t->cpus_allowed); | ||
248 | |||
249 | for_each_online_cpu (cpu) { | ||
250 | if (cpu == dying) | ||
251 | continue; | ||
252 | if (set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu))) | ||
253 | continue; | ||
254 | /* Recheck banks in case CPUs don't all have the same */ | ||
255 | if (cmci_supported(&banks)) | ||
256 | cmci_discover(banks, 0); | ||
257 | } | ||
258 | |||
259 | set_cpus_allowed_ptr(current, old); | ||
260 | free_cpumask_var(old); | ||
261 | } | ||
262 | |||
263 | /* | ||
264 | * Reenable CMCI on this CPU in case a CPU down failed. | ||
265 | */ | ||
266 | void cmci_reenable(void) | ||
267 | { | ||
268 | int banks; | ||
269 | if (cmci_supported(&banks)) | ||
270 | cmci_discover(banks, 0); | ||
271 | } | ||
272 | |||
273 | static __cpuinit void intel_init_cmci(void) | ||
274 | { | ||
275 | int banks; | ||
276 | |||
277 | if (!cmci_supported(&banks)) | ||
278 | return; | ||
279 | |||
280 | mce_threshold_vector = intel_threshold_interrupt; | ||
281 | cmci_discover(banks, 1); | ||
282 | /* | ||
283 | * For CPU #0 this runs with still disabled APIC, but that's | ||
284 | * ok because only the vector is set up. We still do another | ||
285 | * check for the banks later for CPU #0 just to make sure | ||
286 | * to not miss any events. | ||
287 | */ | ||
288 | apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED); | ||
289 | cmci_recheck(); | ||
290 | } | ||
291 | |||
88 | void mce_intel_feature_init(struct cpuinfo_x86 *c) | 292 | void mce_intel_feature_init(struct cpuinfo_x86 *c) |
89 | { | 293 | { |
90 | intel_init_thermal(c); | 294 | intel_init_thermal(c); |
295 | intel_init_cmci(); | ||
91 | } | 296 | } |
diff --git a/arch/x86/kernel/cpu/mcheck/threshold.c b/arch/x86/kernel/cpu/mcheck/threshold.c new file mode 100644 index 000000000000..23ee9e730f78 --- /dev/null +++ b/arch/x86/kernel/cpu/mcheck/threshold.c | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * Common corrected MCE threshold handler code: | ||
3 | */ | ||
4 | #include <linux/interrupt.h> | ||
5 | #include <linux/kernel.h> | ||
6 | |||
7 | #include <asm/irq_vectors.h> | ||
8 | #include <asm/apic.h> | ||
9 | #include <asm/idle.h> | ||
10 | #include <asm/mce.h> | ||
11 | |||
12 | static void default_threshold_interrupt(void) | ||
13 | { | ||
14 | printk(KERN_ERR "Unexpected threshold interrupt at vector %x\n", | ||
15 | THRESHOLD_APIC_VECTOR); | ||
16 | } | ||
17 | |||
18 | void (*mce_threshold_vector)(void) = default_threshold_interrupt; | ||
19 | |||
20 | asmlinkage void mce_threshold_interrupt(void) | ||
21 | { | ||
22 | exit_idle(); | ||
23 | irq_enter(); | ||
24 | inc_irq_stat(irq_threshold_count); | ||
25 | mce_threshold_vector(); | ||
26 | irq_exit(); | ||
27 | /* Ack only at the end to avoid potential reentry */ | ||
28 | ack_APIC_irq(); | ||
29 | } | ||
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index 83d1836b9467..7ba4621c0dfa 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S | |||
@@ -984,6 +984,8 @@ apicinterrupt UV_BAU_MESSAGE \ | |||
984 | #endif | 984 | #endif |
985 | apicinterrupt LOCAL_TIMER_VECTOR \ | 985 | apicinterrupt LOCAL_TIMER_VECTOR \ |
986 | apic_timer_interrupt smp_apic_timer_interrupt | 986 | apic_timer_interrupt smp_apic_timer_interrupt |
987 | apicinterrupt GENERIC_INTERRUPT_VECTOR \ | ||
988 | generic_interrupt smp_generic_interrupt | ||
987 | 989 | ||
988 | #ifdef CONFIG_SMP | 990 | #ifdef CONFIG_SMP |
989 | apicinterrupt INVALIDATE_TLB_VECTOR_START+0 \ | 991 | apicinterrupt INVALIDATE_TLB_VECTOR_START+0 \ |
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index f13ca1650aaf..b864341dcc45 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c | |||
@@ -15,6 +15,9 @@ | |||
15 | 15 | ||
16 | atomic_t irq_err_count; | 16 | atomic_t irq_err_count; |
17 | 17 | ||
18 | /* Function pointer for generic interrupt vector handling */ | ||
19 | void (*generic_interrupt_extension)(void) = NULL; | ||
20 | |||
18 | /* | 21 | /* |
19 | * 'what should we do if we get a hw irq event on an illegal vector'. | 22 | * 'what should we do if we get a hw irq event on an illegal vector'. |
20 | * each architecture has to answer this themselves. | 23 | * each architecture has to answer this themselves. |
@@ -56,6 +59,12 @@ static int show_other_interrupts(struct seq_file *p) | |||
56 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); | 59 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); |
57 | seq_printf(p, " Local timer interrupts\n"); | 60 | seq_printf(p, " Local timer interrupts\n"); |
58 | #endif | 61 | #endif |
62 | if (generic_interrupt_extension) { | ||
63 | seq_printf(p, "PLT: "); | ||
64 | for_each_online_cpu(j) | ||
65 | seq_printf(p, "%10u ", irq_stats(j)->generic_irqs); | ||
66 | seq_printf(p, " Platform interrupts\n"); | ||
67 | } | ||
59 | #ifdef CONFIG_SMP | 68 | #ifdef CONFIG_SMP |
60 | seq_printf(p, "RES: "); | 69 | seq_printf(p, "RES: "); |
61 | for_each_online_cpu(j) | 70 | for_each_online_cpu(j) |
@@ -163,6 +172,8 @@ u64 arch_irq_stat_cpu(unsigned int cpu) | |||
163 | #ifdef CONFIG_X86_LOCAL_APIC | 172 | #ifdef CONFIG_X86_LOCAL_APIC |
164 | sum += irq_stats(cpu)->apic_timer_irqs; | 173 | sum += irq_stats(cpu)->apic_timer_irqs; |
165 | #endif | 174 | #endif |
175 | if (generic_interrupt_extension) | ||
176 | sum += irq_stats(cpu)->generic_irqs; | ||
166 | #ifdef CONFIG_SMP | 177 | #ifdef CONFIG_SMP |
167 | sum += irq_stats(cpu)->irq_resched_count; | 178 | sum += irq_stats(cpu)->irq_resched_count; |
168 | sum += irq_stats(cpu)->irq_call_count; | 179 | sum += irq_stats(cpu)->irq_call_count; |
@@ -226,4 +237,27 @@ unsigned int __irq_entry do_IRQ(struct pt_regs *regs) | |||
226 | return 1; | 237 | return 1; |
227 | } | 238 | } |
228 | 239 | ||
240 | /* | ||
241 | * Handler for GENERIC_INTERRUPT_VECTOR. | ||
242 | */ | ||
243 | void smp_generic_interrupt(struct pt_regs *regs) | ||
244 | { | ||
245 | struct pt_regs *old_regs = set_irq_regs(regs); | ||
246 | |||
247 | ack_APIC_irq(); | ||
248 | |||
249 | exit_idle(); | ||
250 | |||
251 | irq_enter(); | ||
252 | |||
253 | inc_irq_stat(generic_irqs); | ||
254 | |||
255 | if (generic_interrupt_extension) | ||
256 | generic_interrupt_extension(); | ||
257 | |||
258 | irq_exit(); | ||
259 | |||
260 | set_irq_regs(old_regs); | ||
261 | } | ||
262 | |||
229 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); | 263 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); |
diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c index 50b8c3a3006c..bc1326105448 100644 --- a/arch/x86/kernel/irqinit_32.c +++ b/arch/x86/kernel/irqinit_32.c | |||
@@ -175,6 +175,9 @@ void __init native_init_IRQ(void) | |||
175 | /* self generated IPI for local APIC timer */ | 175 | /* self generated IPI for local APIC timer */ |
176 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | 176 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); |
177 | 177 | ||
178 | /* generic IPI for platform specific use */ | ||
179 | alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt); | ||
180 | |||
178 | /* IPI vectors for APIC spurious and error interrupts */ | 181 | /* IPI vectors for APIC spurious and error interrupts */ |
179 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | 182 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); |
180 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | 183 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); |
diff --git a/arch/x86/kernel/irqinit_64.c b/arch/x86/kernel/irqinit_64.c index da481a1e3f30..c7a49e0ffbfb 100644 --- a/arch/x86/kernel/irqinit_64.c +++ b/arch/x86/kernel/irqinit_64.c | |||
@@ -147,6 +147,9 @@ static void __init apic_intr_init(void) | |||
147 | /* self generated IPI for local APIC timer */ | 147 | /* self generated IPI for local APIC timer */ |
148 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); | 148 | alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); |
149 | 149 | ||
150 | /* generic IPI for platform specific use */ | ||
151 | alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt); | ||
152 | |||
150 | /* IPI vectors for APIC spurious and error interrupts */ | 153 | /* IPI vectors for APIC spurious and error interrupts */ |
151 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); | 154 | alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); |
152 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); | 155 | alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt); |
diff --git a/arch/x86/kernel/machine_kexec_32.c b/arch/x86/kernel/machine_kexec_32.c index f5fc8c781a62..e7368c1da01d 100644 --- a/arch/x86/kernel/machine_kexec_32.c +++ b/arch/x86/kernel/machine_kexec_32.c | |||
@@ -14,12 +14,12 @@ | |||
14 | #include <linux/ftrace.h> | 14 | #include <linux/ftrace.h> |
15 | #include <linux/suspend.h> | 15 | #include <linux/suspend.h> |
16 | #include <linux/gfp.h> | 16 | #include <linux/gfp.h> |
17 | #include <linux/io.h> | ||
17 | 18 | ||
18 | #include <asm/pgtable.h> | 19 | #include <asm/pgtable.h> |
19 | #include <asm/pgalloc.h> | 20 | #include <asm/pgalloc.h> |
20 | #include <asm/tlbflush.h> | 21 | #include <asm/tlbflush.h> |
21 | #include <asm/mmu_context.h> | 22 | #include <asm/mmu_context.h> |
22 | #include <asm/io.h> | ||
23 | #include <asm/apic.h> | 23 | #include <asm/apic.h> |
24 | #include <asm/cpufeature.h> | 24 | #include <asm/cpufeature.h> |
25 | #include <asm/desc.h> | 25 | #include <asm/desc.h> |
@@ -63,7 +63,7 @@ static void load_segments(void) | |||
63 | "\tmovl %%eax,%%fs\n" | 63 | "\tmovl %%eax,%%fs\n" |
64 | "\tmovl %%eax,%%gs\n" | 64 | "\tmovl %%eax,%%gs\n" |
65 | "\tmovl %%eax,%%ss\n" | 65 | "\tmovl %%eax,%%ss\n" |
66 | ::: "eax", "memory"); | 66 | : : : "eax", "memory"); |
67 | #undef STR | 67 | #undef STR |
68 | #undef __STR | 68 | #undef __STR |
69 | } | 69 | } |
@@ -205,7 +205,8 @@ void machine_kexec(struct kimage *image) | |||
205 | 205 | ||
206 | if (image->preserve_context) { | 206 | if (image->preserve_context) { |
207 | #ifdef CONFIG_X86_IO_APIC | 207 | #ifdef CONFIG_X86_IO_APIC |
208 | /* We need to put APICs in legacy mode so that we can | 208 | /* |
209 | * We need to put APICs in legacy mode so that we can | ||
209 | * get timer interrupts in second kernel. kexec/kdump | 210 | * get timer interrupts in second kernel. kexec/kdump |
210 | * paths already have calls to disable_IO_APIC() in | 211 | * paths already have calls to disable_IO_APIC() in |
211 | * one form or other. kexec jump path also need | 212 | * one form or other. kexec jump path also need |
@@ -227,7 +228,8 @@ void machine_kexec(struct kimage *image) | |||
227 | page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) | 228 | page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) |
228 | << PAGE_SHIFT); | 229 | << PAGE_SHIFT); |
229 | 230 | ||
230 | /* The segment registers are funny things, they have both a | 231 | /* |
232 | * The segment registers are funny things, they have both a | ||
231 | * visible and an invisible part. Whenever the visible part is | 233 | * visible and an invisible part. Whenever the visible part is |
232 | * set to a specific selector, the invisible part is loaded | 234 | * set to a specific selector, the invisible part is loaded |
233 | * with from a table in memory. At no other time is the | 235 | * with from a table in memory. At no other time is the |
@@ -237,11 +239,12 @@ void machine_kexec(struct kimage *image) | |||
237 | * segments, before I zap the gdt with an invalid value. | 239 | * segments, before I zap the gdt with an invalid value. |
238 | */ | 240 | */ |
239 | load_segments(); | 241 | load_segments(); |
240 | /* The gdt & idt are now invalid. | 242 | /* |
243 | * The gdt & idt are now invalid. | ||
241 | * If you want to load them you must set up your own idt & gdt. | 244 | * If you want to load them you must set up your own idt & gdt. |
242 | */ | 245 | */ |
243 | set_gdt(phys_to_virt(0),0); | 246 | set_gdt(phys_to_virt(0), 0); |
244 | set_idt(phys_to_virt(0),0); | 247 | set_idt(phys_to_virt(0), 0); |
245 | 248 | ||
246 | /* now call it */ | 249 | /* now call it */ |
247 | image->start = relocate_kernel_ptr((unsigned long)image->head, | 250 | image->start = relocate_kernel_ptr((unsigned long)image->head, |
diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c index 6993d51b7fd8..89cea4d44679 100644 --- a/arch/x86/kernel/machine_kexec_64.c +++ b/arch/x86/kernel/machine_kexec_64.c | |||
@@ -12,11 +12,47 @@ | |||
12 | #include <linux/reboot.h> | 12 | #include <linux/reboot.h> |
13 | #include <linux/numa.h> | 13 | #include <linux/numa.h> |
14 | #include <linux/ftrace.h> | 14 | #include <linux/ftrace.h> |
15 | #include <linux/io.h> | ||
16 | #include <linux/suspend.h> | ||
15 | 17 | ||
16 | #include <asm/pgtable.h> | 18 | #include <asm/pgtable.h> |
17 | #include <asm/tlbflush.h> | 19 | #include <asm/tlbflush.h> |
18 | #include <asm/mmu_context.h> | 20 | #include <asm/mmu_context.h> |
19 | #include <asm/io.h> | 21 | |
22 | static int init_one_level2_page(struct kimage *image, pgd_t *pgd, | ||
23 | unsigned long addr) | ||
24 | { | ||
25 | pud_t *pud; | ||
26 | pmd_t *pmd; | ||
27 | struct page *page; | ||
28 | int result = -ENOMEM; | ||
29 | |||
30 | addr &= PMD_MASK; | ||
31 | pgd += pgd_index(addr); | ||
32 | if (!pgd_present(*pgd)) { | ||
33 | page = kimage_alloc_control_pages(image, 0); | ||
34 | if (!page) | ||
35 | goto out; | ||
36 | pud = (pud_t *)page_address(page); | ||
37 | memset(pud, 0, PAGE_SIZE); | ||
38 | set_pgd(pgd, __pgd(__pa(pud) | _KERNPG_TABLE)); | ||
39 | } | ||
40 | pud = pud_offset(pgd, addr); | ||
41 | if (!pud_present(*pud)) { | ||
42 | page = kimage_alloc_control_pages(image, 0); | ||
43 | if (!page) | ||
44 | goto out; | ||
45 | pmd = (pmd_t *)page_address(page); | ||
46 | memset(pmd, 0, PAGE_SIZE); | ||
47 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | ||
48 | } | ||
49 | pmd = pmd_offset(pud, addr); | ||
50 | if (!pmd_present(*pmd)) | ||
51 | set_pmd(pmd, __pmd(addr | __PAGE_KERNEL_LARGE_EXEC)); | ||
52 | result = 0; | ||
53 | out: | ||
54 | return result; | ||
55 | } | ||
20 | 56 | ||
21 | static void init_level2_page(pmd_t *level2p, unsigned long addr) | 57 | static void init_level2_page(pmd_t *level2p, unsigned long addr) |
22 | { | 58 | { |
@@ -83,9 +119,8 @@ static int init_level4_page(struct kimage *image, pgd_t *level4p, | |||
83 | } | 119 | } |
84 | level3p = (pud_t *)page_address(page); | 120 | level3p = (pud_t *)page_address(page); |
85 | result = init_level3_page(image, level3p, addr, last_addr); | 121 | result = init_level3_page(image, level3p, addr, last_addr); |
86 | if (result) { | 122 | if (result) |
87 | goto out; | 123 | goto out; |
88 | } | ||
89 | set_pgd(level4p++, __pgd(__pa(level3p) | _KERNPG_TABLE)); | 124 | set_pgd(level4p++, __pgd(__pa(level3p) | _KERNPG_TABLE)); |
90 | addr += PGDIR_SIZE; | 125 | addr += PGDIR_SIZE; |
91 | } | 126 | } |
@@ -156,6 +191,13 @@ static int init_pgtable(struct kimage *image, unsigned long start_pgtable) | |||
156 | result = init_level4_page(image, level4p, 0, max_pfn << PAGE_SHIFT); | 191 | result = init_level4_page(image, level4p, 0, max_pfn << PAGE_SHIFT); |
157 | if (result) | 192 | if (result) |
158 | return result; | 193 | return result; |
194 | /* | ||
195 | * image->start may be outside 0 ~ max_pfn, for example when | ||
196 | * jump back to original kernel from kexeced kernel | ||
197 | */ | ||
198 | result = init_one_level2_page(image, level4p, image->start); | ||
199 | if (result) | ||
200 | return result; | ||
159 | return init_transition_pgtable(image, level4p); | 201 | return init_transition_pgtable(image, level4p); |
160 | } | 202 | } |
161 | 203 | ||
@@ -229,20 +271,45 @@ void machine_kexec(struct kimage *image) | |||
229 | { | 271 | { |
230 | unsigned long page_list[PAGES_NR]; | 272 | unsigned long page_list[PAGES_NR]; |
231 | void *control_page; | 273 | void *control_page; |
274 | int save_ftrace_enabled; | ||
232 | 275 | ||
233 | tracer_disable(); | 276 | #ifdef CONFIG_KEXEC_JUMP |
277 | if (kexec_image->preserve_context) | ||
278 | save_processor_state(); | ||
279 | #endif | ||
280 | |||
281 | save_ftrace_enabled = __ftrace_enabled_save(); | ||
234 | 282 | ||
235 | /* Interrupts aren't acceptable while we reboot */ | 283 | /* Interrupts aren't acceptable while we reboot */ |
236 | local_irq_disable(); | 284 | local_irq_disable(); |
237 | 285 | ||
286 | if (image->preserve_context) { | ||
287 | #ifdef CONFIG_X86_IO_APIC | ||
288 | /* | ||
289 | * We need to put APICs in legacy mode so that we can | ||
290 | * get timer interrupts in second kernel. kexec/kdump | ||
291 | * paths already have calls to disable_IO_APIC() in | ||
292 | * one form or other. kexec jump path also need | ||
293 | * one. | ||
294 | */ | ||
295 | disable_IO_APIC(); | ||
296 | #endif | ||
297 | } | ||
298 | |||
238 | control_page = page_address(image->control_code_page) + PAGE_SIZE; | 299 | control_page = page_address(image->control_code_page) + PAGE_SIZE; |
239 | memcpy(control_page, relocate_kernel, PAGE_SIZE); | 300 | memcpy(control_page, relocate_kernel, KEXEC_CONTROL_CODE_MAX_SIZE); |
240 | 301 | ||
241 | page_list[PA_CONTROL_PAGE] = virt_to_phys(control_page); | 302 | page_list[PA_CONTROL_PAGE] = virt_to_phys(control_page); |
303 | page_list[VA_CONTROL_PAGE] = (unsigned long)control_page; | ||
242 | page_list[PA_TABLE_PAGE] = | 304 | page_list[PA_TABLE_PAGE] = |
243 | (unsigned long)__pa(page_address(image->control_code_page)); | 305 | (unsigned long)__pa(page_address(image->control_code_page)); |
244 | 306 | ||
245 | /* The segment registers are funny things, they have both a | 307 | if (image->type == KEXEC_TYPE_DEFAULT) |
308 | page_list[PA_SWAP_PAGE] = (page_to_pfn(image->swap_page) | ||
309 | << PAGE_SHIFT); | ||
310 | |||
311 | /* | ||
312 | * The segment registers are funny things, they have both a | ||
246 | * visible and an invisible part. Whenever the visible part is | 313 | * visible and an invisible part. Whenever the visible part is |
247 | * set to a specific selector, the invisible part is loaded | 314 | * set to a specific selector, the invisible part is loaded |
248 | * with from a table in memory. At no other time is the | 315 | * with from a table in memory. At no other time is the |
@@ -252,15 +319,25 @@ void machine_kexec(struct kimage *image) | |||
252 | * segments, before I zap the gdt with an invalid value. | 319 | * segments, before I zap the gdt with an invalid value. |
253 | */ | 320 | */ |
254 | load_segments(); | 321 | load_segments(); |
255 | /* The gdt & idt are now invalid. | 322 | /* |
323 | * The gdt & idt are now invalid. | ||
256 | * If you want to load them you must set up your own idt & gdt. | 324 | * If you want to load them you must set up your own idt & gdt. |
257 | */ | 325 | */ |
258 | set_gdt(phys_to_virt(0),0); | 326 | set_gdt(phys_to_virt(0), 0); |
259 | set_idt(phys_to_virt(0),0); | 327 | set_idt(phys_to_virt(0), 0); |
260 | 328 | ||
261 | /* now call it */ | 329 | /* now call it */ |
262 | relocate_kernel((unsigned long)image->head, (unsigned long)page_list, | 330 | image->start = relocate_kernel((unsigned long)image->head, |
263 | image->start); | 331 | (unsigned long)page_list, |
332 | image->start, | ||
333 | image->preserve_context); | ||
334 | |||
335 | #ifdef CONFIG_KEXEC_JUMP | ||
336 | if (kexec_image->preserve_context) | ||
337 | restore_processor_state(); | ||
338 | #endif | ||
339 | |||
340 | __ftrace_enabled_restore(save_ftrace_enabled); | ||
264 | } | 341 | } |
265 | 342 | ||
266 | void arch_crash_save_vmcoreinfo(void) | 343 | void arch_crash_save_vmcoreinfo(void) |
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 37cb1bda1baf..e8192401da47 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c | |||
@@ -558,6 +558,19 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |||
558 | 558 | ||
559 | static struct mpf_intel *mpf_found; | 559 | static struct mpf_intel *mpf_found; |
560 | 560 | ||
561 | static unsigned long __init get_mpc_size(unsigned long physptr) | ||
562 | { | ||
563 | struct mpc_table *mpc; | ||
564 | unsigned long size; | ||
565 | |||
566 | mpc = early_ioremap(physptr, PAGE_SIZE); | ||
567 | size = mpc->length; | ||
568 | early_iounmap(mpc, PAGE_SIZE); | ||
569 | apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); | ||
570 | |||
571 | return size; | ||
572 | } | ||
573 | |||
561 | /* | 574 | /* |
562 | * Scan the memory blocks for an SMP configuration block. | 575 | * Scan the memory blocks for an SMP configuration block. |
563 | */ | 576 | */ |
@@ -611,12 +624,16 @@ static void __init __get_smp_config(unsigned int early) | |||
611 | construct_default_ISA_mptable(mpf->feature1); | 624 | construct_default_ISA_mptable(mpf->feature1); |
612 | 625 | ||
613 | } else if (mpf->physptr) { | 626 | } else if (mpf->physptr) { |
627 | struct mpc_table *mpc; | ||
628 | unsigned long size; | ||
614 | 629 | ||
630 | size = get_mpc_size(mpf->physptr); | ||
631 | mpc = early_ioremap(mpf->physptr, size); | ||
615 | /* | 632 | /* |
616 | * Read the physical hardware table. Anything here will | 633 | * Read the physical hardware table. Anything here will |
617 | * override the defaults. | 634 | * override the defaults. |
618 | */ | 635 | */ |
619 | if (!smp_read_mpc(phys_to_virt(mpf->physptr), early)) { | 636 | if (!smp_read_mpc(mpc, early)) { |
620 | #ifdef CONFIG_X86_LOCAL_APIC | 637 | #ifdef CONFIG_X86_LOCAL_APIC |
621 | smp_found_config = 0; | 638 | smp_found_config = 0; |
622 | #endif | 639 | #endif |
@@ -624,8 +641,10 @@ static void __init __get_smp_config(unsigned int early) | |||
624 | "BIOS bug, MP table errors detected!...\n"); | 641 | "BIOS bug, MP table errors detected!...\n"); |
625 | printk(KERN_ERR "... disabling SMP support. " | 642 | printk(KERN_ERR "... disabling SMP support. " |
626 | "(tell your hw vendor)\n"); | 643 | "(tell your hw vendor)\n"); |
644 | early_iounmap(mpc, size); | ||
627 | return; | 645 | return; |
628 | } | 646 | } |
647 | early_iounmap(mpc, size); | ||
629 | 648 | ||
630 | if (early) | 649 | if (early) |
631 | return; | 650 | return; |
@@ -697,10 +716,10 @@ static int __init smp_scan_config(unsigned long base, unsigned long length, | |||
697 | 716 | ||
698 | if (!reserve) | 717 | if (!reserve) |
699 | return 1; | 718 | return 1; |
700 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE, | 719 | reserve_bootmem_generic(virt_to_phys(mpf), sizeof(*mpf), |
701 | BOOTMEM_DEFAULT); | 720 | BOOTMEM_DEFAULT); |
702 | if (mpf->physptr) { | 721 | if (mpf->physptr) { |
703 | unsigned long size = PAGE_SIZE; | 722 | unsigned long size = get_mpc_size(mpf->physptr); |
704 | #ifdef CONFIG_X86_32 | 723 | #ifdef CONFIG_X86_32 |
705 | /* | 724 | /* |
706 | * We cannot access to MPC table to compute | 725 | * We cannot access to MPC table to compute |
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index 309949e9e1c1..6a5a2970f4c5 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c | |||
@@ -74,8 +74,7 @@ static void ich_force_hpet_resume(void) | |||
74 | if (!force_hpet_address) | 74 | if (!force_hpet_address) |
75 | return; | 75 | return; |
76 | 76 | ||
77 | if (rcba_base == NULL) | 77 | BUG_ON(rcba_base == NULL); |
78 | BUG(); | ||
79 | 78 | ||
80 | /* read the Function Disable register, dword mode only */ | 79 | /* read the Function Disable register, dword mode only */ |
81 | val = readl(rcba_base + 0x3404); | 80 | val = readl(rcba_base + 0x3404); |
diff --git a/arch/x86/kernel/relocate_kernel_32.S b/arch/x86/kernel/relocate_kernel_32.S index 2064d0aa8d28..41235531b11c 100644 --- a/arch/x86/kernel/relocate_kernel_32.S +++ b/arch/x86/kernel/relocate_kernel_32.S | |||
@@ -17,7 +17,8 @@ | |||
17 | 17 | ||
18 | #define PTR(x) (x << 2) | 18 | #define PTR(x) (x << 2) |
19 | 19 | ||
20 | /* control_page + KEXEC_CONTROL_CODE_MAX_SIZE | 20 | /* |
21 | * control_page + KEXEC_CONTROL_CODE_MAX_SIZE | ||
21 | * ~ control_page + PAGE_SIZE are used as data storage and stack for | 22 | * ~ control_page + PAGE_SIZE are used as data storage and stack for |
22 | * jumping back | 23 | * jumping back |
23 | */ | 24 | */ |
@@ -76,8 +77,10 @@ relocate_kernel: | |||
76 | movl %eax, CP_PA_SWAP_PAGE(%edi) | 77 | movl %eax, CP_PA_SWAP_PAGE(%edi) |
77 | movl %ebx, CP_PA_BACKUP_PAGES_MAP(%edi) | 78 | movl %ebx, CP_PA_BACKUP_PAGES_MAP(%edi) |
78 | 79 | ||
79 | /* get physical address of control page now */ | 80 | /* |
80 | /* this is impossible after page table switch */ | 81 | * get physical address of control page now |
82 | * this is impossible after page table switch | ||
83 | */ | ||
81 | movl PTR(PA_CONTROL_PAGE)(%ebp), %edi | 84 | movl PTR(PA_CONTROL_PAGE)(%ebp), %edi |
82 | 85 | ||
83 | /* switch to new set of page tables */ | 86 | /* switch to new set of page tables */ |
@@ -97,7 +100,8 @@ identity_mapped: | |||
97 | /* store the start address on the stack */ | 100 | /* store the start address on the stack */ |
98 | pushl %edx | 101 | pushl %edx |
99 | 102 | ||
100 | /* Set cr0 to a known state: | 103 | /* |
104 | * Set cr0 to a known state: | ||
101 | * - Paging disabled | 105 | * - Paging disabled |
102 | * - Alignment check disabled | 106 | * - Alignment check disabled |
103 | * - Write protect disabled | 107 | * - Write protect disabled |
@@ -113,7 +117,8 @@ identity_mapped: | |||
113 | /* clear cr4 if applicable */ | 117 | /* clear cr4 if applicable */ |
114 | testl %ecx, %ecx | 118 | testl %ecx, %ecx |
115 | jz 1f | 119 | jz 1f |
116 | /* Set cr4 to a known state: | 120 | /* |
121 | * Set cr4 to a known state: | ||
117 | * Setting everything to zero seems safe. | 122 | * Setting everything to zero seems safe. |
118 | */ | 123 | */ |
119 | xorl %eax, %eax | 124 | xorl %eax, %eax |
@@ -132,15 +137,18 @@ identity_mapped: | |||
132 | call swap_pages | 137 | call swap_pages |
133 | addl $8, %esp | 138 | addl $8, %esp |
134 | 139 | ||
135 | /* To be certain of avoiding problems with self-modifying code | 140 | /* |
141 | * To be certain of avoiding problems with self-modifying code | ||
136 | * I need to execute a serializing instruction here. | 142 | * I need to execute a serializing instruction here. |
137 | * So I flush the TLB, it's handy, and not processor dependent. | 143 | * So I flush the TLB, it's handy, and not processor dependent. |
138 | */ | 144 | */ |
139 | xorl %eax, %eax | 145 | xorl %eax, %eax |
140 | movl %eax, %cr3 | 146 | movl %eax, %cr3 |
141 | 147 | ||
142 | /* set all of the registers to known values */ | 148 | /* |
143 | /* leave %esp alone */ | 149 | * set all of the registers to known values |
150 | * leave %esp alone | ||
151 | */ | ||
144 | 152 | ||
145 | testl %esi, %esi | 153 | testl %esi, %esi |
146 | jnz 1f | 154 | jnz 1f |
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S index d32cfb27a479..4de8f5b3d476 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S | |||
@@ -19,29 +19,77 @@ | |||
19 | #define PTR(x) (x << 3) | 19 | #define PTR(x) (x << 3) |
20 | #define PAGE_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) | 20 | #define PAGE_ATTR (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) |
21 | 21 | ||
22 | /* | ||
23 | * control_page + KEXEC_CONTROL_CODE_MAX_SIZE | ||
24 | * ~ control_page + PAGE_SIZE are used as data storage and stack for | ||
25 | * jumping back | ||
26 | */ | ||
27 | #define DATA(offset) (KEXEC_CONTROL_CODE_MAX_SIZE+(offset)) | ||
28 | |||
29 | /* Minimal CPU state */ | ||
30 | #define RSP DATA(0x0) | ||
31 | #define CR0 DATA(0x8) | ||
32 | #define CR3 DATA(0x10) | ||
33 | #define CR4 DATA(0x18) | ||
34 | |||
35 | /* other data */ | ||
36 | #define CP_PA_TABLE_PAGE DATA(0x20) | ||
37 | #define CP_PA_SWAP_PAGE DATA(0x28) | ||
38 | #define CP_PA_BACKUP_PAGES_MAP DATA(0x30) | ||
39 | |||
22 | .text | 40 | .text |
23 | .align PAGE_SIZE | 41 | .align PAGE_SIZE |
24 | .code64 | 42 | .code64 |
25 | .globl relocate_kernel | 43 | .globl relocate_kernel |
26 | relocate_kernel: | 44 | relocate_kernel: |
27 | /* %rdi indirection_page | 45 | /* |
46 | * %rdi indirection_page | ||
28 | * %rsi page_list | 47 | * %rsi page_list |
29 | * %rdx start address | 48 | * %rdx start address |
49 | * %rcx preserve_context | ||
30 | */ | 50 | */ |
31 | 51 | ||
52 | /* Save the CPU context, used for jumping back */ | ||
53 | pushq %rbx | ||
54 | pushq %rbp | ||
55 | pushq %r12 | ||
56 | pushq %r13 | ||
57 | pushq %r14 | ||
58 | pushq %r15 | ||
59 | pushf | ||
60 | |||
61 | movq PTR(VA_CONTROL_PAGE)(%rsi), %r11 | ||
62 | movq %rsp, RSP(%r11) | ||
63 | movq %cr0, %rax | ||
64 | movq %rax, CR0(%r11) | ||
65 | movq %cr3, %rax | ||
66 | movq %rax, CR3(%r11) | ||
67 | movq %cr4, %rax | ||
68 | movq %rax, CR4(%r11) | ||
69 | |||
32 | /* zero out flags, and disable interrupts */ | 70 | /* zero out flags, and disable interrupts */ |
33 | pushq $0 | 71 | pushq $0 |
34 | popfq | 72 | popfq |
35 | 73 | ||
36 | /* get physical address of control page now */ | 74 | /* |
37 | /* this is impossible after page table switch */ | 75 | * get physical address of control page now |
76 | * this is impossible after page table switch | ||
77 | */ | ||
38 | movq PTR(PA_CONTROL_PAGE)(%rsi), %r8 | 78 | movq PTR(PA_CONTROL_PAGE)(%rsi), %r8 |
39 | 79 | ||
40 | /* get physical address of page table now too */ | 80 | /* get physical address of page table now too */ |
41 | movq PTR(PA_TABLE_PAGE)(%rsi), %rcx | 81 | movq PTR(PA_TABLE_PAGE)(%rsi), %r9 |
82 | |||
83 | /* get physical address of swap page now */ | ||
84 | movq PTR(PA_SWAP_PAGE)(%rsi), %r10 | ||
85 | |||
86 | /* save some information for jumping back */ | ||
87 | movq %r9, CP_PA_TABLE_PAGE(%r11) | ||
88 | movq %r10, CP_PA_SWAP_PAGE(%r11) | ||
89 | movq %rdi, CP_PA_BACKUP_PAGES_MAP(%r11) | ||
42 | 90 | ||
43 | /* Switch to the identity mapped page tables */ | 91 | /* Switch to the identity mapped page tables */ |
44 | movq %rcx, %cr3 | 92 | movq %r9, %cr3 |
45 | 93 | ||
46 | /* setup a new stack at the end of the physical control page */ | 94 | /* setup a new stack at the end of the physical control page */ |
47 | lea PAGE_SIZE(%r8), %rsp | 95 | lea PAGE_SIZE(%r8), %rsp |
@@ -55,7 +103,8 @@ identity_mapped: | |||
55 | /* store the start address on the stack */ | 103 | /* store the start address on the stack */ |
56 | pushq %rdx | 104 | pushq %rdx |
57 | 105 | ||
58 | /* Set cr0 to a known state: | 106 | /* |
107 | * Set cr0 to a known state: | ||
59 | * - Paging enabled | 108 | * - Paging enabled |
60 | * - Alignment check disabled | 109 | * - Alignment check disabled |
61 | * - Write protect disabled | 110 | * - Write protect disabled |
@@ -68,7 +117,8 @@ identity_mapped: | |||
68 | orl $(X86_CR0_PG | X86_CR0_PE), %eax | 117 | orl $(X86_CR0_PG | X86_CR0_PE), %eax |
69 | movq %rax, %cr0 | 118 | movq %rax, %cr0 |
70 | 119 | ||
71 | /* Set cr4 to a known state: | 120 | /* |
121 | * Set cr4 to a known state: | ||
72 | * - physical address extension enabled | 122 | * - physical address extension enabled |
73 | */ | 123 | */ |
74 | movq $X86_CR4_PAE, %rax | 124 | movq $X86_CR4_PAE, %rax |
@@ -78,9 +128,87 @@ identity_mapped: | |||
78 | 1: | 128 | 1: |
79 | 129 | ||
80 | /* Flush the TLB (needed?) */ | 130 | /* Flush the TLB (needed?) */ |
81 | movq %rcx, %cr3 | 131 | movq %r9, %cr3 |
132 | |||
133 | movq %rcx, %r11 | ||
134 | call swap_pages | ||
135 | |||
136 | /* | ||
137 | * To be certain of avoiding problems with self-modifying code | ||
138 | * I need to execute a serializing instruction here. | ||
139 | * So I flush the TLB by reloading %cr3 here, it's handy, | ||
140 | * and not processor dependent. | ||
141 | */ | ||
142 | movq %cr3, %rax | ||
143 | movq %rax, %cr3 | ||
144 | |||
145 | /* | ||
146 | * set all of the registers to known values | ||
147 | * leave %rsp alone | ||
148 | */ | ||
149 | |||
150 | testq %r11, %r11 | ||
151 | jnz 1f | ||
152 | xorq %rax, %rax | ||
153 | xorq %rbx, %rbx | ||
154 | xorq %rcx, %rcx | ||
155 | xorq %rdx, %rdx | ||
156 | xorq %rsi, %rsi | ||
157 | xorq %rdi, %rdi | ||
158 | xorq %rbp, %rbp | ||
159 | xorq %r8, %r8 | ||
160 | xorq %r9, %r9 | ||
161 | xorq %r10, %r9 | ||
162 | xorq %r11, %r11 | ||
163 | xorq %r12, %r12 | ||
164 | xorq %r13, %r13 | ||
165 | xorq %r14, %r14 | ||
166 | xorq %r15, %r15 | ||
167 | |||
168 | ret | ||
169 | |||
170 | 1: | ||
171 | popq %rdx | ||
172 | leaq PAGE_SIZE(%r10), %rsp | ||
173 | call *%rdx | ||
174 | |||
175 | /* get the re-entry point of the peer system */ | ||
176 | movq 0(%rsp), %rbp | ||
177 | call 1f | ||
178 | 1: | ||
179 | popq %r8 | ||
180 | subq $(1b - relocate_kernel), %r8 | ||
181 | movq CP_PA_SWAP_PAGE(%r8), %r10 | ||
182 | movq CP_PA_BACKUP_PAGES_MAP(%r8), %rdi | ||
183 | movq CP_PA_TABLE_PAGE(%r8), %rax | ||
184 | movq %rax, %cr3 | ||
185 | lea PAGE_SIZE(%r8), %rsp | ||
186 | call swap_pages | ||
187 | movq $virtual_mapped, %rax | ||
188 | pushq %rax | ||
189 | ret | ||
190 | |||
191 | virtual_mapped: | ||
192 | movq RSP(%r8), %rsp | ||
193 | movq CR4(%r8), %rax | ||
194 | movq %rax, %cr4 | ||
195 | movq CR3(%r8), %rax | ||
196 | movq CR0(%r8), %r8 | ||
197 | movq %rax, %cr3 | ||
198 | movq %r8, %cr0 | ||
199 | movq %rbp, %rax | ||
200 | |||
201 | popf | ||
202 | popq %r15 | ||
203 | popq %r14 | ||
204 | popq %r13 | ||
205 | popq %r12 | ||
206 | popq %rbp | ||
207 | popq %rbx | ||
208 | ret | ||
82 | 209 | ||
83 | /* Do the copies */ | 210 | /* Do the copies */ |
211 | swap_pages: | ||
84 | movq %rdi, %rcx /* Put the page_list in %rcx */ | 212 | movq %rdi, %rcx /* Put the page_list in %rcx */ |
85 | xorq %rdi, %rdi | 213 | xorq %rdi, %rdi |
86 | xorq %rsi, %rsi | 214 | xorq %rsi, %rsi |
@@ -112,36 +240,27 @@ identity_mapped: | |||
112 | movq %rcx, %rsi /* For ever source page do a copy */ | 240 | movq %rcx, %rsi /* For ever source page do a copy */ |
113 | andq $0xfffffffffffff000, %rsi | 241 | andq $0xfffffffffffff000, %rsi |
114 | 242 | ||
243 | movq %rdi, %rdx | ||
244 | movq %rsi, %rax | ||
245 | |||
246 | movq %r10, %rdi | ||
115 | movq $512, %rcx | 247 | movq $512, %rcx |
116 | rep ; movsq | 248 | rep ; movsq |
117 | jmp 0b | ||
118 | 3: | ||
119 | |||
120 | /* To be certain of avoiding problems with self-modifying code | ||
121 | * I need to execute a serializing instruction here. | ||
122 | * So I flush the TLB by reloading %cr3 here, it's handy, | ||
123 | * and not processor dependent. | ||
124 | */ | ||
125 | movq %cr3, %rax | ||
126 | movq %rax, %cr3 | ||
127 | 249 | ||
128 | /* set all of the registers to known values */ | 250 | movq %rax, %rdi |
129 | /* leave %rsp alone */ | 251 | movq %rdx, %rsi |
252 | movq $512, %rcx | ||
253 | rep ; movsq | ||
130 | 254 | ||
131 | xorq %rax, %rax | 255 | movq %rdx, %rdi |
132 | xorq %rbx, %rbx | 256 | movq %r10, %rsi |
133 | xorq %rcx, %rcx | 257 | movq $512, %rcx |
134 | xorq %rdx, %rdx | 258 | rep ; movsq |
135 | xorq %rsi, %rsi | ||
136 | xorq %rdi, %rdi | ||
137 | xorq %rbp, %rbp | ||
138 | xorq %r8, %r8 | ||
139 | xorq %r9, %r9 | ||
140 | xorq %r10, %r9 | ||
141 | xorq %r11, %r11 | ||
142 | xorq %r12, %r12 | ||
143 | xorq %r13, %r13 | ||
144 | xorq %r14, %r14 | ||
145 | xorq %r15, %r15 | ||
146 | 259 | ||
260 | lea PAGE_SIZE(%rax), %rsi | ||
261 | jmp 0b | ||
262 | 3: | ||
147 | ret | 263 | ret |
264 | |||
265 | .globl kexec_control_code_size | ||
266 | .set kexec_control_code_size, . - relocate_kernel | ||
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index b746deb9ebc6..f28c56e6bf94 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c | |||
@@ -202,7 +202,9 @@ struct ist_info ist_info; | |||
202 | #endif | 202 | #endif |
203 | 203 | ||
204 | #else | 204 | #else |
205 | struct cpuinfo_x86 boot_cpu_data __read_mostly; | 205 | struct cpuinfo_x86 boot_cpu_data __read_mostly = { |
206 | .x86_phys_bits = MAX_PHYSMEM_BITS, | ||
207 | }; | ||
206 | EXPORT_SYMBOL(boot_cpu_data); | 208 | EXPORT_SYMBOL(boot_cpu_data); |
207 | #endif | 209 | #endif |
208 | 210 | ||
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 249334f5080a..ef7d10170c30 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c | |||
@@ -114,10 +114,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_info); | |||
114 | 114 | ||
115 | atomic_t init_deasserted; | 115 | atomic_t init_deasserted; |
116 | 116 | ||
117 | |||
118 | /* Set if we find a B stepping CPU */ | ||
119 | static int __cpuinitdata smp_b_stepping; | ||
120 | |||
121 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) | 117 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
122 | 118 | ||
123 | /* which logical CPUs are on which nodes */ | 119 | /* which logical CPUs are on which nodes */ |
@@ -271,8 +267,6 @@ static void __cpuinit smp_callin(void) | |||
271 | cpumask_set_cpu(cpuid, cpu_callin_mask); | 267 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
272 | } | 268 | } |
273 | 269 | ||
274 | static int __cpuinitdata unsafe_smp; | ||
275 | |||
276 | /* | 270 | /* |
277 | * Activate a secondary processor. | 271 | * Activate a secondary processor. |
278 | */ | 272 | */ |
@@ -340,76 +334,6 @@ notrace static void __cpuinit start_secondary(void *unused) | |||
340 | cpu_idle(); | 334 | cpu_idle(); |
341 | } | 335 | } |
342 | 336 | ||
343 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) | ||
344 | { | ||
345 | /* | ||
346 | * Mask B, Pentium, but not Pentium MMX | ||
347 | */ | ||
348 | if (c->x86_vendor == X86_VENDOR_INTEL && | ||
349 | c->x86 == 5 && | ||
350 | c->x86_mask >= 1 && c->x86_mask <= 4 && | ||
351 | c->x86_model <= 3) | ||
352 | /* | ||
353 | * Remember we have B step Pentia with bugs | ||
354 | */ | ||
355 | smp_b_stepping = 1; | ||
356 | |||
357 | /* | ||
358 | * Certain Athlons might work (for various values of 'work') in SMP | ||
359 | * but they are not certified as MP capable. | ||
360 | */ | ||
361 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | ||
362 | |||
363 | if (num_possible_cpus() == 1) | ||
364 | goto valid_k7; | ||
365 | |||
366 | /* Athlon 660/661 is valid. */ | ||
367 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | ||
368 | (c->x86_mask == 1))) | ||
369 | goto valid_k7; | ||
370 | |||
371 | /* Duron 670 is valid */ | ||
372 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | ||
373 | goto valid_k7; | ||
374 | |||
375 | /* | ||
376 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | ||
377 | * bit. It's worth noting that the A5 stepping (662) of some | ||
378 | * Athlon XP's have the MP bit set. | ||
379 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | ||
380 | * more. | ||
381 | */ | ||
382 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | ||
383 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | ||
384 | (c->x86_model > 7)) | ||
385 | if (cpu_has_mp) | ||
386 | goto valid_k7; | ||
387 | |||
388 | /* If we get here, not a certified SMP capable AMD system. */ | ||
389 | unsafe_smp = 1; | ||
390 | } | ||
391 | |||
392 | valid_k7: | ||
393 | ; | ||
394 | } | ||
395 | |||
396 | static void __cpuinit smp_checks(void) | ||
397 | { | ||
398 | if (smp_b_stepping) | ||
399 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | ||
400 | "with B stepping processors.\n"); | ||
401 | |||
402 | /* | ||
403 | * Don't taint if we are running SMP kernel on a single non-MP | ||
404 | * approved Athlon | ||
405 | */ | ||
406 | if (unsafe_smp && num_online_cpus() > 1) { | ||
407 | printk(KERN_INFO "WARNING: This combination of AMD" | ||
408 | "processors is not suitable for SMP.\n"); | ||
409 | add_taint(TAINT_UNSAFE_SMP); | ||
410 | } | ||
411 | } | ||
412 | |||
413 | /* | 337 | /* |
414 | * The bootstrap kernel entry code has set these up. Save them for | 338 | * The bootstrap kernel entry code has set these up. Save them for |
415 | * a given CPU | 339 | * a given CPU |
@@ -423,7 +347,6 @@ void __cpuinit smp_store_cpu_info(int id) | |||
423 | c->cpu_index = id; | 347 | c->cpu_index = id; |
424 | if (id != 0) | 348 | if (id != 0) |
425 | identify_secondary_cpu(c); | 349 | identify_secondary_cpu(c); |
426 | smp_apply_quirks(c); | ||
427 | } | 350 | } |
428 | 351 | ||
429 | 352 | ||
@@ -1193,7 +1116,6 @@ void __init native_smp_cpus_done(unsigned int max_cpus) | |||
1193 | pr_debug("Boot done.\n"); | 1116 | pr_debug("Boot done.\n"); |
1194 | 1117 | ||
1195 | impress_friends(); | 1118 | impress_friends(); |
1196 | smp_checks(); | ||
1197 | #ifdef CONFIG_X86_IO_APIC | 1119 | #ifdef CONFIG_X86_IO_APIC |
1198 | setup_ioapic_dest(); | 1120 | setup_ioapic_dest(); |
1199 | #endif | 1121 | #endif |
diff --git a/arch/x86/kernel/uv_time.c b/arch/x86/kernel/uv_time.c new file mode 100644 index 000000000000..2ffb6c53326e --- /dev/null +++ b/arch/x86/kernel/uv_time.c | |||
@@ -0,0 +1,393 @@ | |||
1 | /* | ||
2 | * SGI RTC clock/timer routines. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | * | ||
18 | * Copyright (c) 2009 Silicon Graphics, Inc. All Rights Reserved. | ||
19 | * Copyright (c) Dimitri Sivanich | ||
20 | */ | ||
21 | #include <linux/clockchips.h> | ||
22 | |||
23 | #include <asm/uv/uv_mmrs.h> | ||
24 | #include <asm/uv/uv_hub.h> | ||
25 | #include <asm/uv/bios.h> | ||
26 | #include <asm/uv/uv.h> | ||
27 | #include <asm/apic.h> | ||
28 | #include <asm/cpu.h> | ||
29 | |||
30 | #define RTC_NAME "sgi_rtc" | ||
31 | |||
32 | static cycle_t uv_read_rtc(void); | ||
33 | static int uv_rtc_next_event(unsigned long, struct clock_event_device *); | ||
34 | static void uv_rtc_timer_setup(enum clock_event_mode, | ||
35 | struct clock_event_device *); | ||
36 | |||
37 | static struct clocksource clocksource_uv = { | ||
38 | .name = RTC_NAME, | ||
39 | .rating = 400, | ||
40 | .read = uv_read_rtc, | ||
41 | .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK, | ||
42 | .shift = 10, | ||
43 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
44 | }; | ||
45 | |||
46 | static struct clock_event_device clock_event_device_uv = { | ||
47 | .name = RTC_NAME, | ||
48 | .features = CLOCK_EVT_FEAT_ONESHOT, | ||
49 | .shift = 20, | ||
50 | .rating = 400, | ||
51 | .irq = -1, | ||
52 | .set_next_event = uv_rtc_next_event, | ||
53 | .set_mode = uv_rtc_timer_setup, | ||
54 | .event_handler = NULL, | ||
55 | }; | ||
56 | |||
57 | static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); | ||
58 | |||
59 | /* There is one of these allocated per node */ | ||
60 | struct uv_rtc_timer_head { | ||
61 | spinlock_t lock; | ||
62 | /* next cpu waiting for timer, local node relative: */ | ||
63 | int next_cpu; | ||
64 | /* number of cpus on this node: */ | ||
65 | int ncpus; | ||
66 | struct { | ||
67 | int lcpu; /* systemwide logical cpu number */ | ||
68 | u64 expires; /* next timer expiration for this cpu */ | ||
69 | } cpu[1]; | ||
70 | }; | ||
71 | |||
72 | /* | ||
73 | * Access to uv_rtc_timer_head via blade id. | ||
74 | */ | ||
75 | static struct uv_rtc_timer_head **blade_info __read_mostly; | ||
76 | |||
77 | static int uv_rtc_enable; | ||
78 | |||
79 | /* | ||
80 | * Hardware interface routines | ||
81 | */ | ||
82 | |||
83 | /* Send IPIs to another node */ | ||
84 | static void uv_rtc_send_IPI(int cpu) | ||
85 | { | ||
86 | unsigned long apicid, val; | ||
87 | int pnode; | ||
88 | |||
89 | apicid = cpu_physical_id(cpu); | ||
90 | pnode = uv_apicid_to_pnode(apicid); | ||
91 | val = (1UL << UVH_IPI_INT_SEND_SHFT) | | ||
92 | (apicid << UVH_IPI_INT_APIC_ID_SHFT) | | ||
93 | (GENERIC_INTERRUPT_VECTOR << UVH_IPI_INT_VECTOR_SHFT); | ||
94 | |||
95 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); | ||
96 | } | ||
97 | |||
98 | /* Check for an RTC interrupt pending */ | ||
99 | static int uv_intr_pending(int pnode) | ||
100 | { | ||
101 | return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) & | ||
102 | UVH_EVENT_OCCURRED0_RTC1_MASK; | ||
103 | } | ||
104 | |||
105 | /* Setup interrupt and return non-zero if early expiration occurred. */ | ||
106 | static int uv_setup_intr(int cpu, u64 expires) | ||
107 | { | ||
108 | u64 val; | ||
109 | int pnode = uv_cpu_to_pnode(cpu); | ||
110 | |||
111 | uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, | ||
112 | UVH_RTC1_INT_CONFIG_M_MASK); | ||
113 | uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L); | ||
114 | |||
115 | uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS, | ||
116 | UVH_EVENT_OCCURRED0_RTC1_MASK); | ||
117 | |||
118 | val = (GENERIC_INTERRUPT_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | | ||
119 | ((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT); | ||
120 | |||
121 | /* Set configuration */ | ||
122 | uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val); | ||
123 | /* Initialize comparator value */ | ||
124 | uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); | ||
125 | |||
126 | return (expires < uv_read_rtc() && !uv_intr_pending(pnode)); | ||
127 | } | ||
128 | |||
129 | /* | ||
130 | * Per-cpu timer tracking routines | ||
131 | */ | ||
132 | |||
133 | static __init void uv_rtc_deallocate_timers(void) | ||
134 | { | ||
135 | int bid; | ||
136 | |||
137 | for_each_possible_blade(bid) { | ||
138 | kfree(blade_info[bid]); | ||
139 | } | ||
140 | kfree(blade_info); | ||
141 | } | ||
142 | |||
143 | /* Allocate per-node list of cpu timer expiration times. */ | ||
144 | static __init int uv_rtc_allocate_timers(void) | ||
145 | { | ||
146 | int cpu; | ||
147 | |||
148 | blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL); | ||
149 | if (!blade_info) | ||
150 | return -ENOMEM; | ||
151 | memset(blade_info, 0, uv_possible_blades * sizeof(void *)); | ||
152 | |||
153 | for_each_present_cpu(cpu) { | ||
154 | int nid = cpu_to_node(cpu); | ||
155 | int bid = uv_cpu_to_blade_id(cpu); | ||
156 | int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; | ||
157 | struct uv_rtc_timer_head *head = blade_info[bid]; | ||
158 | |||
159 | if (!head) { | ||
160 | head = kmalloc_node(sizeof(struct uv_rtc_timer_head) + | ||
161 | (uv_blade_nr_possible_cpus(bid) * | ||
162 | 2 * sizeof(u64)), | ||
163 | GFP_KERNEL, nid); | ||
164 | if (!head) { | ||
165 | uv_rtc_deallocate_timers(); | ||
166 | return -ENOMEM; | ||
167 | } | ||
168 | spin_lock_init(&head->lock); | ||
169 | head->ncpus = uv_blade_nr_possible_cpus(bid); | ||
170 | head->next_cpu = -1; | ||
171 | blade_info[bid] = head; | ||
172 | } | ||
173 | |||
174 | head->cpu[bcpu].lcpu = cpu; | ||
175 | head->cpu[bcpu].expires = ULLONG_MAX; | ||
176 | } | ||
177 | |||
178 | return 0; | ||
179 | } | ||
180 | |||
181 | /* Find and set the next expiring timer. */ | ||
182 | static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode) | ||
183 | { | ||
184 | u64 lowest = ULLONG_MAX; | ||
185 | int c, bcpu = -1; | ||
186 | |||
187 | head->next_cpu = -1; | ||
188 | for (c = 0; c < head->ncpus; c++) { | ||
189 | u64 exp = head->cpu[c].expires; | ||
190 | if (exp < lowest) { | ||
191 | bcpu = c; | ||
192 | lowest = exp; | ||
193 | } | ||
194 | } | ||
195 | if (bcpu >= 0) { | ||
196 | head->next_cpu = bcpu; | ||
197 | c = head->cpu[bcpu].lcpu; | ||
198 | if (uv_setup_intr(c, lowest)) | ||
199 | /* If we didn't set it up in time, trigger */ | ||
200 | uv_rtc_send_IPI(c); | ||
201 | } else { | ||
202 | uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, | ||
203 | UVH_RTC1_INT_CONFIG_M_MASK); | ||
204 | } | ||
205 | } | ||
206 | |||
207 | /* | ||
208 | * Set expiration time for current cpu. | ||
209 | * | ||
210 | * Returns 1 if we missed the expiration time. | ||
211 | */ | ||
212 | static int uv_rtc_set_timer(int cpu, u64 expires) | ||
213 | { | ||
214 | int pnode = uv_cpu_to_pnode(cpu); | ||
215 | int bid = uv_cpu_to_blade_id(cpu); | ||
216 | struct uv_rtc_timer_head *head = blade_info[bid]; | ||
217 | int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; | ||
218 | u64 *t = &head->cpu[bcpu].expires; | ||
219 | unsigned long flags; | ||
220 | int next_cpu; | ||
221 | |||
222 | spin_lock_irqsave(&head->lock, flags); | ||
223 | |||
224 | next_cpu = head->next_cpu; | ||
225 | *t = expires; | ||
226 | /* Will this one be next to go off? */ | ||
227 | if (next_cpu < 0 || bcpu == next_cpu || | ||
228 | expires < head->cpu[next_cpu].expires) { | ||
229 | head->next_cpu = bcpu; | ||
230 | if (uv_setup_intr(cpu, expires)) { | ||
231 | *t = ULLONG_MAX; | ||
232 | uv_rtc_find_next_timer(head, pnode); | ||
233 | spin_unlock_irqrestore(&head->lock, flags); | ||
234 | return 1; | ||
235 | } | ||
236 | } | ||
237 | |||
238 | spin_unlock_irqrestore(&head->lock, flags); | ||
239 | return 0; | ||
240 | } | ||
241 | |||
242 | /* | ||
243 | * Unset expiration time for current cpu. | ||
244 | * | ||
245 | * Returns 1 if this timer was pending. | ||
246 | */ | ||
247 | static int uv_rtc_unset_timer(int cpu) | ||
248 | { | ||
249 | int pnode = uv_cpu_to_pnode(cpu); | ||
250 | int bid = uv_cpu_to_blade_id(cpu); | ||
251 | struct uv_rtc_timer_head *head = blade_info[bid]; | ||
252 | int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; | ||
253 | u64 *t = &head->cpu[bcpu].expires; | ||
254 | unsigned long flags; | ||
255 | int rc = 0; | ||
256 | |||
257 | spin_lock_irqsave(&head->lock, flags); | ||
258 | |||
259 | if (head->next_cpu == bcpu && uv_read_rtc() >= *t) | ||
260 | rc = 1; | ||
261 | |||
262 | *t = ULLONG_MAX; | ||
263 | |||
264 | /* Was the hardware setup for this timer? */ | ||
265 | if (head->next_cpu == bcpu) | ||
266 | uv_rtc_find_next_timer(head, pnode); | ||
267 | |||
268 | spin_unlock_irqrestore(&head->lock, flags); | ||
269 | |||
270 | return rc; | ||
271 | } | ||
272 | |||
273 | |||
274 | /* | ||
275 | * Kernel interface routines. | ||
276 | */ | ||
277 | |||
278 | /* | ||
279 | * Read the RTC. | ||
280 | */ | ||
281 | static cycle_t uv_read_rtc(void) | ||
282 | { | ||
283 | return (cycle_t)uv_read_local_mmr(UVH_RTC); | ||
284 | } | ||
285 | |||
286 | /* | ||
287 | * Program the next event, relative to now | ||
288 | */ | ||
289 | static int uv_rtc_next_event(unsigned long delta, | ||
290 | struct clock_event_device *ced) | ||
291 | { | ||
292 | int ced_cpu = cpumask_first(ced->cpumask); | ||
293 | |||
294 | return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc()); | ||
295 | } | ||
296 | |||
297 | /* | ||
298 | * Setup the RTC timer in oneshot mode | ||
299 | */ | ||
300 | static void uv_rtc_timer_setup(enum clock_event_mode mode, | ||
301 | struct clock_event_device *evt) | ||
302 | { | ||
303 | int ced_cpu = cpumask_first(evt->cpumask); | ||
304 | |||
305 | switch (mode) { | ||
306 | case CLOCK_EVT_MODE_PERIODIC: | ||
307 | case CLOCK_EVT_MODE_ONESHOT: | ||
308 | case CLOCK_EVT_MODE_RESUME: | ||
309 | /* Nothing to do here yet */ | ||
310 | break; | ||
311 | case CLOCK_EVT_MODE_UNUSED: | ||
312 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
313 | uv_rtc_unset_timer(ced_cpu); | ||
314 | break; | ||
315 | } | ||
316 | } | ||
317 | |||
318 | static void uv_rtc_interrupt(void) | ||
319 | { | ||
320 | struct clock_event_device *ced = &__get_cpu_var(cpu_ced); | ||
321 | int cpu = smp_processor_id(); | ||
322 | |||
323 | if (!ced || !ced->event_handler) | ||
324 | return; | ||
325 | |||
326 | if (uv_rtc_unset_timer(cpu) != 1) | ||
327 | return; | ||
328 | |||
329 | ced->event_handler(ced); | ||
330 | } | ||
331 | |||
332 | static int __init uv_enable_rtc(char *str) | ||
333 | { | ||
334 | uv_rtc_enable = 1; | ||
335 | |||
336 | return 1; | ||
337 | } | ||
338 | __setup("uvrtc", uv_enable_rtc); | ||
339 | |||
340 | static __init void uv_rtc_register_clockevents(struct work_struct *dummy) | ||
341 | { | ||
342 | struct clock_event_device *ced = &__get_cpu_var(cpu_ced); | ||
343 | |||
344 | *ced = clock_event_device_uv; | ||
345 | ced->cpumask = cpumask_of(smp_processor_id()); | ||
346 | clockevents_register_device(ced); | ||
347 | } | ||
348 | |||
349 | static __init int uv_rtc_setup_clock(void) | ||
350 | { | ||
351 | int rc; | ||
352 | |||
353 | if (!uv_rtc_enable || !is_uv_system() || generic_interrupt_extension) | ||
354 | return -ENODEV; | ||
355 | |||
356 | generic_interrupt_extension = uv_rtc_interrupt; | ||
357 | |||
358 | clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second, | ||
359 | clocksource_uv.shift); | ||
360 | |||
361 | rc = clocksource_register(&clocksource_uv); | ||
362 | if (rc) { | ||
363 | generic_interrupt_extension = NULL; | ||
364 | return rc; | ||
365 | } | ||
366 | |||
367 | /* Setup and register clockevents */ | ||
368 | rc = uv_rtc_allocate_timers(); | ||
369 | if (rc) { | ||
370 | clocksource_unregister(&clocksource_uv); | ||
371 | generic_interrupt_extension = NULL; | ||
372 | return rc; | ||
373 | } | ||
374 | |||
375 | clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second, | ||
376 | NSEC_PER_SEC, clock_event_device_uv.shift); | ||
377 | |||
378 | clock_event_device_uv.min_delta_ns = NSEC_PER_SEC / | ||
379 | sn_rtc_cycles_per_second; | ||
380 | |||
381 | clock_event_device_uv.max_delta_ns = clocksource_uv.mask * | ||
382 | (NSEC_PER_SEC / sn_rtc_cycles_per_second); | ||
383 | |||
384 | rc = schedule_on_each_cpu(uv_rtc_register_clockevents); | ||
385 | if (rc) { | ||
386 | clocksource_unregister(&clocksource_uv); | ||
387 | generic_interrupt_extension = NULL; | ||
388 | uv_rtc_deallocate_timers(); | ||
389 | } | ||
390 | |||
391 | return rc; | ||
392 | } | ||
393 | arch_initcall(uv_rtc_setup_clock); | ||
diff --git a/arch/x86/kernel/visws_quirks.c b/arch/x86/kernel/visws_quirks.c index 191a876e9e87..31ffc24eec4d 100644 --- a/arch/x86/kernel/visws_quirks.c +++ b/arch/x86/kernel/visws_quirks.c | |||
@@ -578,7 +578,7 @@ static struct irq_chip piix4_virtual_irq_type = { | |||
578 | static irqreturn_t piix4_master_intr(int irq, void *dev_id) | 578 | static irqreturn_t piix4_master_intr(int irq, void *dev_id) |
579 | { | 579 | { |
580 | int realirq; | 580 | int realirq; |
581 | irq_desc_t *desc; | 581 | struct irq_desc *desc; |
582 | unsigned long flags; | 582 | unsigned long flags; |
583 | 583 | ||
584 | spin_lock_irqsave(&i8259A_lock, flags); | 584 | spin_lock_irqsave(&i8259A_lock, flags); |
diff --git a/arch/x86/kernel/vmlinux_64.lds.S b/arch/x86/kernel/vmlinux_64.lds.S index fbfced6f6800..5bf54e40c6ef 100644 --- a/arch/x86/kernel/vmlinux_64.lds.S +++ b/arch/x86/kernel/vmlinux_64.lds.S | |||
@@ -275,3 +275,10 @@ ASSERT((_end - _text <= KERNEL_IMAGE_SIZE), | |||
275 | ASSERT((per_cpu__irq_stack_union == 0), | 275 | ASSERT((per_cpu__irq_stack_union == 0), |
276 | "irq_stack_union is not at start of per-cpu area"); | 276 | "irq_stack_union is not at start of per-cpu area"); |
277 | #endif | 277 | #endif |
278 | |||
279 | #ifdef CONFIG_KEXEC | ||
280 | #include <asm/kexec.h> | ||
281 | |||
282 | ASSERT(kexec_control_code_size <= KEXEC_CONTROL_CODE_MAX_SIZE, | ||
283 | "kexec control code size is too big") | ||
284 | #endif | ||
diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c index 00f127c80b0e..f256e73542d7 100644 --- a/arch/x86/mm/highmem_32.c +++ b/arch/x86/mm/highmem_32.c | |||
@@ -121,23 +121,30 @@ void kunmap_atomic(void *kvaddr, enum km_type type) | |||
121 | pagefault_enable(); | 121 | pagefault_enable(); |
122 | } | 122 | } |
123 | 123 | ||
124 | /* This is the same as kmap_atomic() but can map memory that doesn't | 124 | void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot) |
125 | * have a struct page associated with it. | ||
126 | */ | ||
127 | void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) | ||
128 | { | 125 | { |
129 | enum fixed_addresses idx; | 126 | enum fixed_addresses idx; |
130 | unsigned long vaddr; | 127 | unsigned long vaddr; |
131 | 128 | ||
132 | pagefault_disable(); | 129 | pagefault_disable(); |
133 | 130 | ||
134 | idx = type + KM_TYPE_NR*smp_processor_id(); | 131 | debug_kmap_atomic_prot(type); |
132 | |||
133 | idx = type + KM_TYPE_NR * smp_processor_id(); | ||
135 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | 134 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); |
136 | set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); | 135 | set_pte(kmap_pte - idx, pfn_pte(pfn, prot)); |
137 | arch_flush_lazy_mmu_mode(); | 136 | arch_flush_lazy_mmu_mode(); |
138 | 137 | ||
139 | return (void*) vaddr; | 138 | return (void*) vaddr; |
140 | } | 139 | } |
140 | |||
141 | /* This is the same as kmap_atomic() but can map memory that doesn't | ||
142 | * have a struct page associated with it. | ||
143 | */ | ||
144 | void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) | ||
145 | { | ||
146 | return kmap_atomic_prot_pfn(pfn, type, kmap_prot); | ||
147 | } | ||
141 | EXPORT_SYMBOL_GPL(kmap_atomic_pfn); /* temporarily in use by i915 GEM until vmap */ | 148 | EXPORT_SYMBOL_GPL(kmap_atomic_pfn); /* temporarily in use by i915 GEM until vmap */ |
142 | 149 | ||
143 | struct page *kmap_atomic_to_page(void *ptr) | 150 | struct page *kmap_atomic_to_page(void *ptr) |
@@ -158,7 +165,6 @@ EXPORT_SYMBOL(kunmap); | |||
158 | EXPORT_SYMBOL(kmap_atomic); | 165 | EXPORT_SYMBOL(kmap_atomic); |
159 | EXPORT_SYMBOL(kunmap_atomic); | 166 | EXPORT_SYMBOL(kunmap_atomic); |
160 | 167 | ||
161 | #ifdef CONFIG_NUMA | ||
162 | void __init set_highmem_pages_init(void) | 168 | void __init set_highmem_pages_init(void) |
163 | { | 169 | { |
164 | struct zone *zone; | 170 | struct zone *zone; |
@@ -182,11 +188,3 @@ void __init set_highmem_pages_init(void) | |||
182 | } | 188 | } |
183 | totalram_pages += totalhigh_pages; | 189 | totalram_pages += totalhigh_pages; |
184 | } | 190 | } |
185 | #else | ||
186 | void __init set_highmem_pages_init(void) | ||
187 | { | ||
188 | add_highpages_with_active_regions(0, highstart_pfn, highend_pfn); | ||
189 | |||
190 | totalram_pages += totalhigh_pages; | ||
191 | } | ||
192 | #endif /* CONFIG_NUMA */ | ||
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index ce6a722587d8..15219e0d1243 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c | |||
@@ -1,8 +1,345 @@ | |||
1 | #include <linux/ioport.h> | ||
1 | #include <linux/swap.h> | 2 | #include <linux/swap.h> |
3 | |||
2 | #include <asm/cacheflush.h> | 4 | #include <asm/cacheflush.h> |
5 | #include <asm/e820.h> | ||
6 | #include <asm/init.h> | ||
3 | #include <asm/page.h> | 7 | #include <asm/page.h> |
8 | #include <asm/page_types.h> | ||
4 | #include <asm/sections.h> | 9 | #include <asm/sections.h> |
5 | #include <asm/system.h> | 10 | #include <asm/system.h> |
11 | #include <asm/tlbflush.h> | ||
12 | |||
13 | unsigned long __initdata e820_table_start; | ||
14 | unsigned long __meminitdata e820_table_end; | ||
15 | unsigned long __meminitdata e820_table_top; | ||
16 | |||
17 | int after_bootmem; | ||
18 | |||
19 | int direct_gbpages | ||
20 | #ifdef CONFIG_DIRECT_GBPAGES | ||
21 | = 1 | ||
22 | #endif | ||
23 | ; | ||
24 | |||
25 | static void __init find_early_table_space(unsigned long end, int use_pse, | ||
26 | int use_gbpages) | ||
27 | { | ||
28 | unsigned long puds, pmds, ptes, tables, start; | ||
29 | |||
30 | puds = (end + PUD_SIZE - 1) >> PUD_SHIFT; | ||
31 | tables = roundup(puds * sizeof(pud_t), PAGE_SIZE); | ||
32 | |||
33 | if (use_gbpages) { | ||
34 | unsigned long extra; | ||
35 | |||
36 | extra = end - ((end>>PUD_SHIFT) << PUD_SHIFT); | ||
37 | pmds = (extra + PMD_SIZE - 1) >> PMD_SHIFT; | ||
38 | } else | ||
39 | pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT; | ||
40 | |||
41 | tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE); | ||
42 | |||
43 | if (use_pse) { | ||
44 | unsigned long extra; | ||
45 | |||
46 | extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT); | ||
47 | #ifdef CONFIG_X86_32 | ||
48 | extra += PMD_SIZE; | ||
49 | #endif | ||
50 | ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
51 | } else | ||
52 | ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
53 | |||
54 | tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE); | ||
55 | |||
56 | #ifdef CONFIG_X86_32 | ||
57 | /* for fixmap */ | ||
58 | tables += roundup(__end_of_fixed_addresses * sizeof(pte_t), PAGE_SIZE); | ||
59 | #endif | ||
60 | |||
61 | /* | ||
62 | * RED-PEN putting page tables only on node 0 could | ||
63 | * cause a hotspot and fill up ZONE_DMA. The page tables | ||
64 | * need roughly 0.5KB per GB. | ||
65 | */ | ||
66 | #ifdef CONFIG_X86_32 | ||
67 | start = 0x7000; | ||
68 | e820_table_start = find_e820_area(start, max_pfn_mapped<<PAGE_SHIFT, | ||
69 | tables, PAGE_SIZE); | ||
70 | #else /* CONFIG_X86_64 */ | ||
71 | start = 0x8000; | ||
72 | e820_table_start = find_e820_area(start, end, tables, PAGE_SIZE); | ||
73 | #endif | ||
74 | if (e820_table_start == -1UL) | ||
75 | panic("Cannot find space for the kernel page tables"); | ||
76 | |||
77 | e820_table_start >>= PAGE_SHIFT; | ||
78 | e820_table_end = e820_table_start; | ||
79 | e820_table_top = e820_table_start + (tables >> PAGE_SHIFT); | ||
80 | |||
81 | printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n", | ||
82 | end, e820_table_start << PAGE_SHIFT, e820_table_top << PAGE_SHIFT); | ||
83 | } | ||
84 | |||
85 | struct map_range { | ||
86 | unsigned long start; | ||
87 | unsigned long end; | ||
88 | unsigned page_size_mask; | ||
89 | }; | ||
90 | |||
91 | #ifdef CONFIG_X86_32 | ||
92 | #define NR_RANGE_MR 3 | ||
93 | #else /* CONFIG_X86_64 */ | ||
94 | #define NR_RANGE_MR 5 | ||
95 | #endif | ||
96 | |||
97 | static int save_mr(struct map_range *mr, int nr_range, | ||
98 | unsigned long start_pfn, unsigned long end_pfn, | ||
99 | unsigned long page_size_mask) | ||
100 | { | ||
101 | if (start_pfn < end_pfn) { | ||
102 | if (nr_range >= NR_RANGE_MR) | ||
103 | panic("run out of range for init_memory_mapping\n"); | ||
104 | mr[nr_range].start = start_pfn<<PAGE_SHIFT; | ||
105 | mr[nr_range].end = end_pfn<<PAGE_SHIFT; | ||
106 | mr[nr_range].page_size_mask = page_size_mask; | ||
107 | nr_range++; | ||
108 | } | ||
109 | |||
110 | return nr_range; | ||
111 | } | ||
112 | |||
113 | #ifdef CONFIG_X86_64 | ||
114 | static void __init init_gbpages(void) | ||
115 | { | ||
116 | if (direct_gbpages && cpu_has_gbpages) | ||
117 | printk(KERN_INFO "Using GB pages for direct mapping\n"); | ||
118 | else | ||
119 | direct_gbpages = 0; | ||
120 | } | ||
121 | #else | ||
122 | static inline void init_gbpages(void) | ||
123 | { | ||
124 | } | ||
125 | #endif | ||
126 | |||
127 | /* | ||
128 | * Setup the direct mapping of the physical memory at PAGE_OFFSET. | ||
129 | * This runs before bootmem is initialized and gets pages directly from | ||
130 | * the physical memory. To access them they are temporarily mapped. | ||
131 | */ | ||
132 | unsigned long __init_refok init_memory_mapping(unsigned long start, | ||
133 | unsigned long end) | ||
134 | { | ||
135 | unsigned long page_size_mask = 0; | ||
136 | unsigned long start_pfn, end_pfn; | ||
137 | unsigned long ret = 0; | ||
138 | unsigned long pos; | ||
139 | |||
140 | struct map_range mr[NR_RANGE_MR]; | ||
141 | int nr_range, i; | ||
142 | int use_pse, use_gbpages; | ||
143 | |||
144 | printk(KERN_INFO "init_memory_mapping: %016lx-%016lx\n", start, end); | ||
145 | |||
146 | if (!after_bootmem) | ||
147 | init_gbpages(); | ||
148 | |||
149 | #ifdef CONFIG_DEBUG_PAGEALLOC | ||
150 | /* | ||
151 | * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages. | ||
152 | * This will simplify cpa(), which otherwise needs to support splitting | ||
153 | * large pages into small in interrupt context, etc. | ||
154 | */ | ||
155 | use_pse = use_gbpages = 0; | ||
156 | #else | ||
157 | use_pse = cpu_has_pse; | ||
158 | use_gbpages = direct_gbpages; | ||
159 | #endif | ||
160 | |||
161 | #ifdef CONFIG_X86_32 | ||
162 | #ifdef CONFIG_X86_PAE | ||
163 | set_nx(); | ||
164 | if (nx_enabled) | ||
165 | printk(KERN_INFO "NX (Execute Disable) protection: active\n"); | ||
166 | #endif | ||
167 | |||
168 | /* Enable PSE if available */ | ||
169 | if (cpu_has_pse) | ||
170 | set_in_cr4(X86_CR4_PSE); | ||
171 | |||
172 | /* Enable PGE if available */ | ||
173 | if (cpu_has_pge) { | ||
174 | set_in_cr4(X86_CR4_PGE); | ||
175 | __supported_pte_mask |= _PAGE_GLOBAL; | ||
176 | } | ||
177 | #endif | ||
178 | |||
179 | if (use_gbpages) | ||
180 | page_size_mask |= 1 << PG_LEVEL_1G; | ||
181 | if (use_pse) | ||
182 | page_size_mask |= 1 << PG_LEVEL_2M; | ||
183 | |||
184 | memset(mr, 0, sizeof(mr)); | ||
185 | nr_range = 0; | ||
186 | |||
187 | /* head if not big page alignment ? */ | ||
188 | start_pfn = start >> PAGE_SHIFT; | ||
189 | pos = start_pfn << PAGE_SHIFT; | ||
190 | #ifdef CONFIG_X86_32 | ||
191 | /* | ||
192 | * Don't use a large page for the first 2/4MB of memory | ||
193 | * because there are often fixed size MTRRs in there | ||
194 | * and overlapping MTRRs into large pages can cause | ||
195 | * slowdowns. | ||
196 | */ | ||
197 | if (pos == 0) | ||
198 | end_pfn = 1<<(PMD_SHIFT - PAGE_SHIFT); | ||
199 | else | ||
200 | end_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT) | ||
201 | << (PMD_SHIFT - PAGE_SHIFT); | ||
202 | #else /* CONFIG_X86_64 */ | ||
203 | end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT) | ||
204 | << (PMD_SHIFT - PAGE_SHIFT); | ||
205 | #endif | ||
206 | if (end_pfn > (end >> PAGE_SHIFT)) | ||
207 | end_pfn = end >> PAGE_SHIFT; | ||
208 | if (start_pfn < end_pfn) { | ||
209 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); | ||
210 | pos = end_pfn << PAGE_SHIFT; | ||
211 | } | ||
212 | |||
213 | /* big page (2M) range */ | ||
214 | start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT) | ||
215 | << (PMD_SHIFT - PAGE_SHIFT); | ||
216 | #ifdef CONFIG_X86_32 | ||
217 | end_pfn = (end>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); | ||
218 | #else /* CONFIG_X86_64 */ | ||
219 | end_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) | ||
220 | << (PUD_SHIFT - PAGE_SHIFT); | ||
221 | if (end_pfn > ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT))) | ||
222 | end_pfn = ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT)); | ||
223 | #endif | ||
224 | |||
225 | if (start_pfn < end_pfn) { | ||
226 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | ||
227 | page_size_mask & (1<<PG_LEVEL_2M)); | ||
228 | pos = end_pfn << PAGE_SHIFT; | ||
229 | } | ||
230 | |||
231 | #ifdef CONFIG_X86_64 | ||
232 | /* big page (1G) range */ | ||
233 | start_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) | ||
234 | << (PUD_SHIFT - PAGE_SHIFT); | ||
235 | end_pfn = (end >> PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); | ||
236 | if (start_pfn < end_pfn) { | ||
237 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | ||
238 | page_size_mask & | ||
239 | ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); | ||
240 | pos = end_pfn << PAGE_SHIFT; | ||
241 | } | ||
242 | |||
243 | /* tail is not big page (1G) alignment */ | ||
244 | start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT) | ||
245 | << (PMD_SHIFT - PAGE_SHIFT); | ||
246 | end_pfn = (end >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); | ||
247 | if (start_pfn < end_pfn) { | ||
248 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | ||
249 | page_size_mask & (1<<PG_LEVEL_2M)); | ||
250 | pos = end_pfn << PAGE_SHIFT; | ||
251 | } | ||
252 | #endif | ||
253 | |||
254 | /* tail is not big page (2M) alignment */ | ||
255 | start_pfn = pos>>PAGE_SHIFT; | ||
256 | end_pfn = end>>PAGE_SHIFT; | ||
257 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); | ||
258 | |||
259 | /* try to merge same page size and continuous */ | ||
260 | for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { | ||
261 | unsigned long old_start; | ||
262 | if (mr[i].end != mr[i+1].start || | ||
263 | mr[i].page_size_mask != mr[i+1].page_size_mask) | ||
264 | continue; | ||
265 | /* move it */ | ||
266 | old_start = mr[i].start; | ||
267 | memmove(&mr[i], &mr[i+1], | ||
268 | (nr_range - 1 - i) * sizeof(struct map_range)); | ||
269 | mr[i--].start = old_start; | ||
270 | nr_range--; | ||
271 | } | ||
272 | |||
273 | for (i = 0; i < nr_range; i++) | ||
274 | printk(KERN_DEBUG " %010lx - %010lx page %s\n", | ||
275 | mr[i].start, mr[i].end, | ||
276 | (mr[i].page_size_mask & (1<<PG_LEVEL_1G))?"1G":( | ||
277 | (mr[i].page_size_mask & (1<<PG_LEVEL_2M))?"2M":"4k")); | ||
278 | |||
279 | /* | ||
280 | * Find space for the kernel direct mapping tables. | ||
281 | * | ||
282 | * Later we should allocate these tables in the local node of the | ||
283 | * memory mapped. Unfortunately this is done currently before the | ||
284 | * nodes are discovered. | ||
285 | */ | ||
286 | if (!after_bootmem) | ||
287 | find_early_table_space(end, use_pse, use_gbpages); | ||
288 | |||
289 | #ifdef CONFIG_X86_32 | ||
290 | for (i = 0; i < nr_range; i++) | ||
291 | kernel_physical_mapping_init(mr[i].start, mr[i].end, | ||
292 | mr[i].page_size_mask); | ||
293 | ret = end; | ||
294 | #else /* CONFIG_X86_64 */ | ||
295 | for (i = 0; i < nr_range; i++) | ||
296 | ret = kernel_physical_mapping_init(mr[i].start, mr[i].end, | ||
297 | mr[i].page_size_mask); | ||
298 | #endif | ||
299 | |||
300 | #ifdef CONFIG_X86_32 | ||
301 | early_ioremap_page_table_range_init(); | ||
302 | |||
303 | load_cr3(swapper_pg_dir); | ||
304 | #endif | ||
305 | |||
306 | #ifdef CONFIG_X86_64 | ||
307 | if (!after_bootmem) | ||
308 | mmu_cr4_features = read_cr4(); | ||
309 | #endif | ||
310 | __flush_tlb_all(); | ||
311 | |||
312 | if (!after_bootmem && e820_table_end > e820_table_start) | ||
313 | reserve_early(e820_table_start << PAGE_SHIFT, | ||
314 | e820_table_end << PAGE_SHIFT, "PGTABLE"); | ||
315 | |||
316 | if (!after_bootmem) | ||
317 | early_memtest(start, end); | ||
318 | |||
319 | return ret >> PAGE_SHIFT; | ||
320 | } | ||
321 | |||
322 | |||
323 | /* | ||
324 | * devmem_is_allowed() checks to see if /dev/mem access to a certain address | ||
325 | * is valid. The argument is a physical page number. | ||
326 | * | ||
327 | * | ||
328 | * On x86, access has to be given to the first megabyte of ram because that area | ||
329 | * contains bios code and data regions used by X and dosemu and similar apps. | ||
330 | * Access has to be given to non-kernel-ram areas as well, these contain the PCI | ||
331 | * mmio resources as well as potential bios/acpi data regions. | ||
332 | */ | ||
333 | int devmem_is_allowed(unsigned long pagenr) | ||
334 | { | ||
335 | if (pagenr <= 256) | ||
336 | return 1; | ||
337 | if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) | ||
338 | return 0; | ||
339 | if (!page_is_ram(pagenr)) | ||
340 | return 1; | ||
341 | return 0; | ||
342 | } | ||
6 | 343 | ||
7 | void free_init_pages(char *what, unsigned long begin, unsigned long end) | 344 | void free_init_pages(char *what, unsigned long begin, unsigned long end) |
8 | { | 345 | { |
@@ -47,3 +384,10 @@ void free_initmem(void) | |||
47 | (unsigned long)(&__init_begin), | 384 | (unsigned long)(&__init_begin), |
48 | (unsigned long)(&__init_end)); | 385 | (unsigned long)(&__init_end)); |
49 | } | 386 | } |
387 | |||
388 | #ifdef CONFIG_BLK_DEV_INITRD | ||
389 | void free_initrd_mem(unsigned long start, unsigned long end) | ||
390 | { | ||
391 | free_init_pages("initrd memory", start, end); | ||
392 | } | ||
393 | #endif | ||
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c index 47df0e1bbeb9..db81e9a8556b 100644 --- a/arch/x86/mm/init_32.c +++ b/arch/x86/mm/init_32.c | |||
@@ -49,6 +49,7 @@ | |||
49 | #include <asm/paravirt.h> | 49 | #include <asm/paravirt.h> |
50 | #include <asm/setup.h> | 50 | #include <asm/setup.h> |
51 | #include <asm/cacheflush.h> | 51 | #include <asm/cacheflush.h> |
52 | #include <asm/init.h> | ||
52 | 53 | ||
53 | unsigned long max_low_pfn_mapped; | 54 | unsigned long max_low_pfn_mapped; |
54 | unsigned long max_pfn_mapped; | 55 | unsigned long max_pfn_mapped; |
@@ -58,19 +59,14 @@ unsigned long highstart_pfn, highend_pfn; | |||
58 | 59 | ||
59 | static noinline int do_test_wp_bit(void); | 60 | static noinline int do_test_wp_bit(void); |
60 | 61 | ||
61 | 62 | bool __read_mostly __vmalloc_start_set = false; | |
62 | static unsigned long __initdata table_start; | ||
63 | static unsigned long __meminitdata table_end; | ||
64 | static unsigned long __meminitdata table_top; | ||
65 | |||
66 | static int __initdata after_init_bootmem; | ||
67 | 63 | ||
68 | static __init void *alloc_low_page(void) | 64 | static __init void *alloc_low_page(void) |
69 | { | 65 | { |
70 | unsigned long pfn = table_end++; | 66 | unsigned long pfn = e820_table_end++; |
71 | void *adr; | 67 | void *adr; |
72 | 68 | ||
73 | if (pfn >= table_top) | 69 | if (pfn >= e820_table_top) |
74 | panic("alloc_low_page: ran out of memory"); | 70 | panic("alloc_low_page: ran out of memory"); |
75 | 71 | ||
76 | adr = __va(pfn * PAGE_SIZE); | 72 | adr = __va(pfn * PAGE_SIZE); |
@@ -90,7 +86,7 @@ static pmd_t * __init one_md_table_init(pgd_t *pgd) | |||
90 | 86 | ||
91 | #ifdef CONFIG_X86_PAE | 87 | #ifdef CONFIG_X86_PAE |
92 | if (!(pgd_val(*pgd) & _PAGE_PRESENT)) { | 88 | if (!(pgd_val(*pgd) & _PAGE_PRESENT)) { |
93 | if (after_init_bootmem) | 89 | if (after_bootmem) |
94 | pmd_table = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE); | 90 | pmd_table = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE); |
95 | else | 91 | else |
96 | pmd_table = (pmd_t *)alloc_low_page(); | 92 | pmd_table = (pmd_t *)alloc_low_page(); |
@@ -117,7 +113,7 @@ static pte_t * __init one_page_table_init(pmd_t *pmd) | |||
117 | if (!(pmd_val(*pmd) & _PAGE_PRESENT)) { | 113 | if (!(pmd_val(*pmd) & _PAGE_PRESENT)) { |
118 | pte_t *page_table = NULL; | 114 | pte_t *page_table = NULL; |
119 | 115 | ||
120 | if (after_init_bootmem) { | 116 | if (after_bootmem) { |
121 | #ifdef CONFIG_DEBUG_PAGEALLOC | 117 | #ifdef CONFIG_DEBUG_PAGEALLOC |
122 | page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE); | 118 | page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE); |
123 | #endif | 119 | #endif |
@@ -168,12 +164,12 @@ static pte_t *__init page_table_kmap_check(pte_t *pte, pmd_t *pmd, | |||
168 | if (pmd_idx_kmap_begin != pmd_idx_kmap_end | 164 | if (pmd_idx_kmap_begin != pmd_idx_kmap_end |
169 | && (vaddr >> PMD_SHIFT) >= pmd_idx_kmap_begin | 165 | && (vaddr >> PMD_SHIFT) >= pmd_idx_kmap_begin |
170 | && (vaddr >> PMD_SHIFT) <= pmd_idx_kmap_end | 166 | && (vaddr >> PMD_SHIFT) <= pmd_idx_kmap_end |
171 | && ((__pa(pte) >> PAGE_SHIFT) < table_start | 167 | && ((__pa(pte) >> PAGE_SHIFT) < e820_table_start |
172 | || (__pa(pte) >> PAGE_SHIFT) >= table_end)) { | 168 | || (__pa(pte) >> PAGE_SHIFT) >= e820_table_end)) { |
173 | pte_t *newpte; | 169 | pte_t *newpte; |
174 | int i; | 170 | int i; |
175 | 171 | ||
176 | BUG_ON(after_init_bootmem); | 172 | BUG_ON(after_bootmem); |
177 | newpte = alloc_low_page(); | 173 | newpte = alloc_low_page(); |
178 | for (i = 0; i < PTRS_PER_PTE; i++) | 174 | for (i = 0; i < PTRS_PER_PTE; i++) |
179 | set_pte(newpte + i, pte[i]); | 175 | set_pte(newpte + i, pte[i]); |
@@ -242,11 +238,14 @@ static inline int is_kernel_text(unsigned long addr) | |||
242 | * of max_low_pfn pages, by creating page tables starting from address | 238 | * of max_low_pfn pages, by creating page tables starting from address |
243 | * PAGE_OFFSET: | 239 | * PAGE_OFFSET: |
244 | */ | 240 | */ |
245 | static void __init kernel_physical_mapping_init(pgd_t *pgd_base, | 241 | unsigned long __init |
246 | unsigned long start_pfn, | 242 | kernel_physical_mapping_init(unsigned long start, |
247 | unsigned long end_pfn, | 243 | unsigned long end, |
248 | int use_pse) | 244 | unsigned long page_size_mask) |
249 | { | 245 | { |
246 | int use_pse = page_size_mask == (1<<PG_LEVEL_2M); | ||
247 | unsigned long start_pfn, end_pfn; | ||
248 | pgd_t *pgd_base = swapper_pg_dir; | ||
250 | int pgd_idx, pmd_idx, pte_ofs; | 249 | int pgd_idx, pmd_idx, pte_ofs; |
251 | unsigned long pfn; | 250 | unsigned long pfn; |
252 | pgd_t *pgd; | 251 | pgd_t *pgd; |
@@ -255,6 +254,9 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base, | |||
255 | unsigned pages_2m, pages_4k; | 254 | unsigned pages_2m, pages_4k; |
256 | int mapping_iter; | 255 | int mapping_iter; |
257 | 256 | ||
257 | start_pfn = start >> PAGE_SHIFT; | ||
258 | end_pfn = end >> PAGE_SHIFT; | ||
259 | |||
258 | /* | 260 | /* |
259 | * First iteration will setup identity mapping using large/small pages | 261 | * First iteration will setup identity mapping using large/small pages |
260 | * based on use_pse, with other attributes same as set by | 262 | * based on use_pse, with other attributes same as set by |
@@ -369,26 +371,6 @@ repeat: | |||
369 | mapping_iter = 2; | 371 | mapping_iter = 2; |
370 | goto repeat; | 372 | goto repeat; |
371 | } | 373 | } |
372 | } | ||
373 | |||
374 | /* | ||
375 | * devmem_is_allowed() checks to see if /dev/mem access to a certain address | ||
376 | * is valid. The argument is a physical page number. | ||
377 | * | ||
378 | * | ||
379 | * On x86, access has to be given to the first megabyte of ram because that area | ||
380 | * contains bios code and data regions used by X and dosemu and similar apps. | ||
381 | * Access has to be given to non-kernel-ram areas as well, these contain the PCI | ||
382 | * mmio resources as well as potential bios/acpi data regions. | ||
383 | */ | ||
384 | int devmem_is_allowed(unsigned long pagenr) | ||
385 | { | ||
386 | if (pagenr <= 256) | ||
387 | return 1; | ||
388 | if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) | ||
389 | return 0; | ||
390 | if (!page_is_ram(pagenr)) | ||
391 | return 1; | ||
392 | return 0; | 374 | return 0; |
393 | } | 375 | } |
394 | 376 | ||
@@ -545,8 +527,9 @@ void __init native_pagetable_setup_done(pgd_t *base) | |||
545 | * be partially populated, and so it avoids stomping on any existing | 527 | * be partially populated, and so it avoids stomping on any existing |
546 | * mappings. | 528 | * mappings. |
547 | */ | 529 | */ |
548 | static void __init early_ioremap_page_table_range_init(pgd_t *pgd_base) | 530 | void __init early_ioremap_page_table_range_init(void) |
549 | { | 531 | { |
532 | pgd_t *pgd_base = swapper_pg_dir; | ||
550 | unsigned long vaddr, end; | 533 | unsigned long vaddr, end; |
551 | 534 | ||
552 | /* | 535 | /* |
@@ -641,7 +624,7 @@ static int __init noexec_setup(char *str) | |||
641 | } | 624 | } |
642 | early_param("noexec", noexec_setup); | 625 | early_param("noexec", noexec_setup); |
643 | 626 | ||
644 | static void __init set_nx(void) | 627 | void __init set_nx(void) |
645 | { | 628 | { |
646 | unsigned int v[4], l, h; | 629 | unsigned int v[4], l, h; |
647 | 630 | ||
@@ -793,6 +776,8 @@ void __init initmem_init(unsigned long start_pfn, | |||
793 | #ifdef CONFIG_FLATMEM | 776 | #ifdef CONFIG_FLATMEM |
794 | max_mapnr = num_physpages; | 777 | max_mapnr = num_physpages; |
795 | #endif | 778 | #endif |
779 | __vmalloc_start_set = true; | ||
780 | |||
796 | printk(KERN_NOTICE "%ldMB LOWMEM available.\n", | 781 | printk(KERN_NOTICE "%ldMB LOWMEM available.\n", |
797 | pages_to_mb(max_low_pfn)); | 782 | pages_to_mb(max_low_pfn)); |
798 | 783 | ||
@@ -814,176 +799,66 @@ static void __init zone_sizes_init(void) | |||
814 | free_area_init_nodes(max_zone_pfns); | 799 | free_area_init_nodes(max_zone_pfns); |
815 | } | 800 | } |
816 | 801 | ||
802 | static unsigned long __init setup_node_bootmem(int nodeid, | ||
803 | unsigned long start_pfn, | ||
804 | unsigned long end_pfn, | ||
805 | unsigned long bootmap) | ||
806 | { | ||
807 | unsigned long bootmap_size; | ||
808 | |||
809 | /* don't touch min_low_pfn */ | ||
810 | bootmap_size = init_bootmem_node(NODE_DATA(nodeid), | ||
811 | bootmap >> PAGE_SHIFT, | ||
812 | start_pfn, end_pfn); | ||
813 | printk(KERN_INFO " node %d low ram: %08lx - %08lx\n", | ||
814 | nodeid, start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | ||
815 | printk(KERN_INFO " node %d bootmap %08lx - %08lx\n", | ||
816 | nodeid, bootmap, bootmap + bootmap_size); | ||
817 | free_bootmem_with_active_regions(nodeid, end_pfn); | ||
818 | early_res_to_bootmem(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | ||
819 | |||
820 | return bootmap + bootmap_size; | ||
821 | } | ||
822 | |||
817 | void __init setup_bootmem_allocator(void) | 823 | void __init setup_bootmem_allocator(void) |
818 | { | 824 | { |
819 | int i; | 825 | int nodeid; |
820 | unsigned long bootmap_size, bootmap; | 826 | unsigned long bootmap_size, bootmap; |
821 | /* | 827 | /* |
822 | * Initialize the boot-time allocator (with low memory only): | 828 | * Initialize the boot-time allocator (with low memory only): |
823 | */ | 829 | */ |
824 | bootmap_size = bootmem_bootmap_pages(max_low_pfn)<<PAGE_SHIFT; | 830 | bootmap_size = bootmem_bootmap_pages(max_low_pfn)<<PAGE_SHIFT; |
825 | bootmap = find_e820_area(min_low_pfn<<PAGE_SHIFT, | 831 | bootmap = find_e820_area(0, max_pfn_mapped<<PAGE_SHIFT, bootmap_size, |
826 | max_pfn_mapped<<PAGE_SHIFT, bootmap_size, | ||
827 | PAGE_SIZE); | 832 | PAGE_SIZE); |
828 | if (bootmap == -1L) | 833 | if (bootmap == -1L) |
829 | panic("Cannot find bootmem map of size %ld\n", bootmap_size); | 834 | panic("Cannot find bootmem map of size %ld\n", bootmap_size); |
830 | reserve_early(bootmap, bootmap + bootmap_size, "BOOTMAP"); | 835 | reserve_early(bootmap, bootmap + bootmap_size, "BOOTMAP"); |
831 | 836 | ||
832 | /* don't touch min_low_pfn */ | ||
833 | bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap >> PAGE_SHIFT, | ||
834 | min_low_pfn, max_low_pfn); | ||
835 | printk(KERN_INFO " mapped low ram: 0 - %08lx\n", | 837 | printk(KERN_INFO " mapped low ram: 0 - %08lx\n", |
836 | max_pfn_mapped<<PAGE_SHIFT); | 838 | max_pfn_mapped<<PAGE_SHIFT); |
837 | printk(KERN_INFO " low ram: %08lx - %08lx\n", | 839 | printk(KERN_INFO " low ram: 0 - %08lx\n", max_low_pfn<<PAGE_SHIFT); |
838 | min_low_pfn<<PAGE_SHIFT, max_low_pfn<<PAGE_SHIFT); | ||
839 | printk(KERN_INFO " bootmap %08lx - %08lx\n", | ||
840 | bootmap, bootmap + bootmap_size); | ||
841 | for_each_online_node(i) | ||
842 | free_bootmem_with_active_regions(i, max_low_pfn); | ||
843 | early_res_to_bootmem(0, max_low_pfn<<PAGE_SHIFT); | ||
844 | |||
845 | after_init_bootmem = 1; | ||
846 | } | ||
847 | |||
848 | static void __init find_early_table_space(unsigned long end, int use_pse) | ||
849 | { | ||
850 | unsigned long puds, pmds, ptes, tables, start; | ||
851 | 840 | ||
852 | puds = (end + PUD_SIZE - 1) >> PUD_SHIFT; | 841 | for_each_online_node(nodeid) { |
853 | tables = roundup(puds * sizeof(pud_t), PAGE_SIZE); | 842 | unsigned long start_pfn, end_pfn; |
854 | 843 | ||
855 | pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT; | 844 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
856 | tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE); | 845 | start_pfn = node_start_pfn[nodeid]; |
857 | 846 | end_pfn = node_end_pfn[nodeid]; | |
858 | if (use_pse) { | 847 | if (start_pfn > max_low_pfn) |
859 | unsigned long extra; | 848 | continue; |
860 | 849 | if (end_pfn > max_low_pfn) | |
861 | extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT); | 850 | end_pfn = max_low_pfn; |
862 | extra += PMD_SIZE; | ||
863 | ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
864 | } else | ||
865 | ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
866 | |||
867 | tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE); | ||
868 | |||
869 | /* for fixmap */ | ||
870 | tables += roundup(__end_of_fixed_addresses * sizeof(pte_t), PAGE_SIZE); | ||
871 | |||
872 | /* | ||
873 | * RED-PEN putting page tables only on node 0 could | ||
874 | * cause a hotspot and fill up ZONE_DMA. The page tables | ||
875 | * need roughly 0.5KB per GB. | ||
876 | */ | ||
877 | start = 0x7000; | ||
878 | table_start = find_e820_area(start, max_pfn_mapped<<PAGE_SHIFT, | ||
879 | tables, PAGE_SIZE); | ||
880 | if (table_start == -1UL) | ||
881 | panic("Cannot find space for the kernel page tables"); | ||
882 | |||
883 | table_start >>= PAGE_SHIFT; | ||
884 | table_end = table_start; | ||
885 | table_top = table_start + (tables>>PAGE_SHIFT); | ||
886 | |||
887 | printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n", | ||
888 | end, table_start << PAGE_SHIFT, | ||
889 | (table_start << PAGE_SHIFT) + tables); | ||
890 | } | ||
891 | |||
892 | unsigned long __init_refok init_memory_mapping(unsigned long start, | ||
893 | unsigned long end) | ||
894 | { | ||
895 | pgd_t *pgd_base = swapper_pg_dir; | ||
896 | unsigned long start_pfn, end_pfn; | ||
897 | unsigned long big_page_start; | ||
898 | #ifdef CONFIG_DEBUG_PAGEALLOC | ||
899 | /* | ||
900 | * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages. | ||
901 | * This will simplify cpa(), which otherwise needs to support splitting | ||
902 | * large pages into small in interrupt context, etc. | ||
903 | */ | ||
904 | int use_pse = 0; | ||
905 | #else | 851 | #else |
906 | int use_pse = cpu_has_pse; | 852 | start_pfn = 0; |
853 | end_pfn = max_low_pfn; | ||
907 | #endif | 854 | #endif |
908 | 855 | bootmap = setup_node_bootmem(nodeid, start_pfn, end_pfn, | |
909 | /* | 856 | bootmap); |
910 | * Find space for the kernel direct mapping tables. | ||
911 | */ | ||
912 | if (!after_init_bootmem) | ||
913 | find_early_table_space(end, use_pse); | ||
914 | |||
915 | #ifdef CONFIG_X86_PAE | ||
916 | set_nx(); | ||
917 | if (nx_enabled) | ||
918 | printk(KERN_INFO "NX (Execute Disable) protection: active\n"); | ||
919 | #endif | ||
920 | |||
921 | /* Enable PSE if available */ | ||
922 | if (cpu_has_pse) | ||
923 | set_in_cr4(X86_CR4_PSE); | ||
924 | |||
925 | /* Enable PGE if available */ | ||
926 | if (cpu_has_pge) { | ||
927 | set_in_cr4(X86_CR4_PGE); | ||
928 | __supported_pte_mask |= _PAGE_GLOBAL; | ||
929 | } | ||
930 | |||
931 | /* | ||
932 | * Don't use a large page for the first 2/4MB of memory | ||
933 | * because there are often fixed size MTRRs in there | ||
934 | * and overlapping MTRRs into large pages can cause | ||
935 | * slowdowns. | ||
936 | */ | ||
937 | big_page_start = PMD_SIZE; | ||
938 | |||
939 | if (start < big_page_start) { | ||
940 | start_pfn = start >> PAGE_SHIFT; | ||
941 | end_pfn = min(big_page_start>>PAGE_SHIFT, end>>PAGE_SHIFT); | ||
942 | } else { | ||
943 | /* head is not big page alignment ? */ | ||
944 | start_pfn = start >> PAGE_SHIFT; | ||
945 | end_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT) | ||
946 | << (PMD_SHIFT - PAGE_SHIFT); | ||
947 | } | 857 | } |
948 | if (start_pfn < end_pfn) | ||
949 | kernel_physical_mapping_init(pgd_base, start_pfn, end_pfn, 0); | ||
950 | |||
951 | /* big page range */ | ||
952 | start_pfn = ((start + (PMD_SIZE - 1))>>PMD_SHIFT) | ||
953 | << (PMD_SHIFT - PAGE_SHIFT); | ||
954 | if (start_pfn < (big_page_start >> PAGE_SHIFT)) | ||
955 | start_pfn = big_page_start >> PAGE_SHIFT; | ||
956 | end_pfn = (end>>PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); | ||
957 | if (start_pfn < end_pfn) | ||
958 | kernel_physical_mapping_init(pgd_base, start_pfn, end_pfn, | ||
959 | use_pse); | ||
960 | |||
961 | /* tail is not big page alignment ? */ | ||
962 | start_pfn = end_pfn; | ||
963 | if (start_pfn > (big_page_start>>PAGE_SHIFT)) { | ||
964 | end_pfn = end >> PAGE_SHIFT; | ||
965 | if (start_pfn < end_pfn) | ||
966 | kernel_physical_mapping_init(pgd_base, start_pfn, | ||
967 | end_pfn, 0); | ||
968 | } | ||
969 | |||
970 | early_ioremap_page_table_range_init(pgd_base); | ||
971 | 858 | ||
972 | load_cr3(swapper_pg_dir); | 859 | after_bootmem = 1; |
973 | |||
974 | __flush_tlb_all(); | ||
975 | |||
976 | if (!after_init_bootmem) | ||
977 | reserve_early(table_start << PAGE_SHIFT, | ||
978 | table_end << PAGE_SHIFT, "PGTABLE"); | ||
979 | |||
980 | if (!after_init_bootmem) | ||
981 | early_memtest(start, end); | ||
982 | |||
983 | return end >> PAGE_SHIFT; | ||
984 | } | 860 | } |
985 | 861 | ||
986 | |||
987 | /* | 862 | /* |
988 | * paging_init() sets up the page tables - note that the first 8MB are | 863 | * paging_init() sets up the page tables - note that the first 8MB are |
989 | * already mapped by head.S. | 864 | * already mapped by head.S. |
@@ -1217,13 +1092,6 @@ void mark_rodata_ro(void) | |||
1217 | } | 1092 | } |
1218 | #endif | 1093 | #endif |
1219 | 1094 | ||
1220 | #ifdef CONFIG_BLK_DEV_INITRD | ||
1221 | void free_initrd_mem(unsigned long start, unsigned long end) | ||
1222 | { | ||
1223 | free_init_pages("initrd memory", start, end); | ||
1224 | } | ||
1225 | #endif | ||
1226 | |||
1227 | int __init reserve_bootmem_generic(unsigned long phys, unsigned long len, | 1095 | int __init reserve_bootmem_generic(unsigned long phys, unsigned long len, |
1228 | int flags) | 1096 | int flags) |
1229 | { | 1097 | { |
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c index 07f44d491df1..54efa57d1c03 100644 --- a/arch/x86/mm/init_64.c +++ b/arch/x86/mm/init_64.c | |||
@@ -48,6 +48,7 @@ | |||
48 | #include <asm/kdebug.h> | 48 | #include <asm/kdebug.h> |
49 | #include <asm/numa.h> | 49 | #include <asm/numa.h> |
50 | #include <asm/cacheflush.h> | 50 | #include <asm/cacheflush.h> |
51 | #include <asm/init.h> | ||
51 | 52 | ||
52 | /* | 53 | /* |
53 | * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries. | 54 | * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries. |
@@ -61,12 +62,6 @@ static unsigned long dma_reserve __initdata; | |||
61 | 62 | ||
62 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); | 63 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); |
63 | 64 | ||
64 | int direct_gbpages | ||
65 | #ifdef CONFIG_DIRECT_GBPAGES | ||
66 | = 1 | ||
67 | #endif | ||
68 | ; | ||
69 | |||
70 | static int __init parse_direct_gbpages_off(char *arg) | 65 | static int __init parse_direct_gbpages_off(char *arg) |
71 | { | 66 | { |
72 | direct_gbpages = 0; | 67 | direct_gbpages = 0; |
@@ -87,12 +82,10 @@ early_param("gbpages", parse_direct_gbpages_on); | |||
87 | * around without checking the pgd every time. | 82 | * around without checking the pgd every time. |
88 | */ | 83 | */ |
89 | 84 | ||
90 | int after_bootmem; | ||
91 | |||
92 | pteval_t __supported_pte_mask __read_mostly = ~_PAGE_IOMAP; | 85 | pteval_t __supported_pte_mask __read_mostly = ~_PAGE_IOMAP; |
93 | EXPORT_SYMBOL_GPL(__supported_pte_mask); | 86 | EXPORT_SYMBOL_GPL(__supported_pte_mask); |
94 | 87 | ||
95 | static int do_not_nx __cpuinitdata; | 88 | static int disable_nx __cpuinitdata; |
96 | 89 | ||
97 | /* | 90 | /* |
98 | * noexec=on|off | 91 | * noexec=on|off |
@@ -107,9 +100,9 @@ static int __init nonx_setup(char *str) | |||
107 | return -EINVAL; | 100 | return -EINVAL; |
108 | if (!strncmp(str, "on", 2)) { | 101 | if (!strncmp(str, "on", 2)) { |
109 | __supported_pte_mask |= _PAGE_NX; | 102 | __supported_pte_mask |= _PAGE_NX; |
110 | do_not_nx = 0; | 103 | disable_nx = 0; |
111 | } else if (!strncmp(str, "off", 3)) { | 104 | } else if (!strncmp(str, "off", 3)) { |
112 | do_not_nx = 1; | 105 | disable_nx = 1; |
113 | __supported_pte_mask &= ~_PAGE_NX; | 106 | __supported_pte_mask &= ~_PAGE_NX; |
114 | } | 107 | } |
115 | return 0; | 108 | return 0; |
@@ -121,7 +114,7 @@ void __cpuinit check_efer(void) | |||
121 | unsigned long efer; | 114 | unsigned long efer; |
122 | 115 | ||
123 | rdmsrl(MSR_EFER, efer); | 116 | rdmsrl(MSR_EFER, efer); |
124 | if (!(efer & EFER_NX) || do_not_nx) | 117 | if (!(efer & EFER_NX) || disable_nx) |
125 | __supported_pte_mask &= ~_PAGE_NX; | 118 | __supported_pte_mask &= ~_PAGE_NX; |
126 | } | 119 | } |
127 | 120 | ||
@@ -325,13 +318,9 @@ void __init cleanup_highmap(void) | |||
325 | } | 318 | } |
326 | } | 319 | } |
327 | 320 | ||
328 | static unsigned long __initdata table_start; | ||
329 | static unsigned long __meminitdata table_end; | ||
330 | static unsigned long __meminitdata table_top; | ||
331 | |||
332 | static __ref void *alloc_low_page(unsigned long *phys) | 321 | static __ref void *alloc_low_page(unsigned long *phys) |
333 | { | 322 | { |
334 | unsigned long pfn = table_end++; | 323 | unsigned long pfn = e820_table_end++; |
335 | void *adr; | 324 | void *adr; |
336 | 325 | ||
337 | if (after_bootmem) { | 326 | if (after_bootmem) { |
@@ -341,7 +330,7 @@ static __ref void *alloc_low_page(unsigned long *phys) | |||
341 | return adr; | 330 | return adr; |
342 | } | 331 | } |
343 | 332 | ||
344 | if (pfn >= table_top) | 333 | if (pfn >= e820_table_top) |
345 | panic("alloc_low_page: ran out of memory"); | 334 | panic("alloc_low_page: ran out of memory"); |
346 | 335 | ||
347 | adr = early_memremap(pfn * PAGE_SIZE, PAGE_SIZE); | 336 | adr = early_memremap(pfn * PAGE_SIZE, PAGE_SIZE); |
@@ -581,58 +570,10 @@ phys_pud_update(pgd_t *pgd, unsigned long addr, unsigned long end, | |||
581 | return phys_pud_init(pud, addr, end, page_size_mask); | 570 | return phys_pud_init(pud, addr, end, page_size_mask); |
582 | } | 571 | } |
583 | 572 | ||
584 | static void __init find_early_table_space(unsigned long end, int use_pse, | 573 | unsigned long __init |
585 | int use_gbpages) | 574 | kernel_physical_mapping_init(unsigned long start, |
586 | { | 575 | unsigned long end, |
587 | unsigned long puds, pmds, ptes, tables, start; | 576 | unsigned long page_size_mask) |
588 | |||
589 | puds = (end + PUD_SIZE - 1) >> PUD_SHIFT; | ||
590 | tables = roundup(puds * sizeof(pud_t), PAGE_SIZE); | ||
591 | if (use_gbpages) { | ||
592 | unsigned long extra; | ||
593 | extra = end - ((end>>PUD_SHIFT) << PUD_SHIFT); | ||
594 | pmds = (extra + PMD_SIZE - 1) >> PMD_SHIFT; | ||
595 | } else | ||
596 | pmds = (end + PMD_SIZE - 1) >> PMD_SHIFT; | ||
597 | tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE); | ||
598 | |||
599 | if (use_pse) { | ||
600 | unsigned long extra; | ||
601 | extra = end - ((end>>PMD_SHIFT) << PMD_SHIFT); | ||
602 | ptes = (extra + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
603 | } else | ||
604 | ptes = (end + PAGE_SIZE - 1) >> PAGE_SHIFT; | ||
605 | tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE); | ||
606 | |||
607 | /* | ||
608 | * RED-PEN putting page tables only on node 0 could | ||
609 | * cause a hotspot and fill up ZONE_DMA. The page tables | ||
610 | * need roughly 0.5KB per GB. | ||
611 | */ | ||
612 | start = 0x8000; | ||
613 | table_start = find_e820_area(start, end, tables, PAGE_SIZE); | ||
614 | if (table_start == -1UL) | ||
615 | panic("Cannot find space for the kernel page tables"); | ||
616 | |||
617 | table_start >>= PAGE_SHIFT; | ||
618 | table_end = table_start; | ||
619 | table_top = table_start + (tables >> PAGE_SHIFT); | ||
620 | |||
621 | printk(KERN_DEBUG "kernel direct mapping tables up to %lx @ %lx-%lx\n", | ||
622 | end, table_start << PAGE_SHIFT, table_top << PAGE_SHIFT); | ||
623 | } | ||
624 | |||
625 | static void __init init_gbpages(void) | ||
626 | { | ||
627 | if (direct_gbpages && cpu_has_gbpages) | ||
628 | printk(KERN_INFO "Using GB pages for direct mapping\n"); | ||
629 | else | ||
630 | direct_gbpages = 0; | ||
631 | } | ||
632 | |||
633 | static unsigned long __meminit kernel_physical_mapping_init(unsigned long start, | ||
634 | unsigned long end, | ||
635 | unsigned long page_size_mask) | ||
636 | { | 577 | { |
637 | 578 | ||
638 | unsigned long next, last_map_addr = end; | 579 | unsigned long next, last_map_addr = end; |
@@ -669,176 +610,6 @@ static unsigned long __meminit kernel_physical_mapping_init(unsigned long start, | |||
669 | return last_map_addr; | 610 | return last_map_addr; |
670 | } | 611 | } |
671 | 612 | ||
672 | struct map_range { | ||
673 | unsigned long start; | ||
674 | unsigned long end; | ||
675 | unsigned page_size_mask; | ||
676 | }; | ||
677 | |||
678 | #define NR_RANGE_MR 5 | ||
679 | |||
680 | static int save_mr(struct map_range *mr, int nr_range, | ||
681 | unsigned long start_pfn, unsigned long end_pfn, | ||
682 | unsigned long page_size_mask) | ||
683 | { | ||
684 | |||
685 | if (start_pfn < end_pfn) { | ||
686 | if (nr_range >= NR_RANGE_MR) | ||
687 | panic("run out of range for init_memory_mapping\n"); | ||
688 | mr[nr_range].start = start_pfn<<PAGE_SHIFT; | ||
689 | mr[nr_range].end = end_pfn<<PAGE_SHIFT; | ||
690 | mr[nr_range].page_size_mask = page_size_mask; | ||
691 | nr_range++; | ||
692 | } | ||
693 | |||
694 | return nr_range; | ||
695 | } | ||
696 | |||
697 | /* | ||
698 | * Setup the direct mapping of the physical memory at PAGE_OFFSET. | ||
699 | * This runs before bootmem is initialized and gets pages directly from | ||
700 | * the physical memory. To access them they are temporarily mapped. | ||
701 | */ | ||
702 | unsigned long __init_refok init_memory_mapping(unsigned long start, | ||
703 | unsigned long end) | ||
704 | { | ||
705 | unsigned long last_map_addr = 0; | ||
706 | unsigned long page_size_mask = 0; | ||
707 | unsigned long start_pfn, end_pfn; | ||
708 | unsigned long pos; | ||
709 | |||
710 | struct map_range mr[NR_RANGE_MR]; | ||
711 | int nr_range, i; | ||
712 | int use_pse, use_gbpages; | ||
713 | |||
714 | printk(KERN_INFO "init_memory_mapping: %016lx-%016lx\n", start, end); | ||
715 | |||
716 | /* | ||
717 | * Find space for the kernel direct mapping tables. | ||
718 | * | ||
719 | * Later we should allocate these tables in the local node of the | ||
720 | * memory mapped. Unfortunately this is done currently before the | ||
721 | * nodes are discovered. | ||
722 | */ | ||
723 | if (!after_bootmem) | ||
724 | init_gbpages(); | ||
725 | |||
726 | #ifdef CONFIG_DEBUG_PAGEALLOC | ||
727 | /* | ||
728 | * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages. | ||
729 | * This will simplify cpa(), which otherwise needs to support splitting | ||
730 | * large pages into small in interrupt context, etc. | ||
731 | */ | ||
732 | use_pse = use_gbpages = 0; | ||
733 | #else | ||
734 | use_pse = cpu_has_pse; | ||
735 | use_gbpages = direct_gbpages; | ||
736 | #endif | ||
737 | |||
738 | if (use_gbpages) | ||
739 | page_size_mask |= 1 << PG_LEVEL_1G; | ||
740 | if (use_pse) | ||
741 | page_size_mask |= 1 << PG_LEVEL_2M; | ||
742 | |||
743 | memset(mr, 0, sizeof(mr)); | ||
744 | nr_range = 0; | ||
745 | |||
746 | /* head if not big page alignment ?*/ | ||
747 | start_pfn = start >> PAGE_SHIFT; | ||
748 | pos = start_pfn << PAGE_SHIFT; | ||
749 | end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT) | ||
750 | << (PMD_SHIFT - PAGE_SHIFT); | ||
751 | if (end_pfn > (end >> PAGE_SHIFT)) | ||
752 | end_pfn = end >> PAGE_SHIFT; | ||
753 | if (start_pfn < end_pfn) { | ||
754 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); | ||
755 | pos = end_pfn << PAGE_SHIFT; | ||
756 | } | ||
757 | |||
758 | /* big page (2M) range*/ | ||
759 | start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT) | ||
760 | << (PMD_SHIFT - PAGE_SHIFT); | ||
761 | end_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) | ||
762 | << (PUD_SHIFT - PAGE_SHIFT); | ||
763 | if (end_pfn > ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT))) | ||
764 | end_pfn = ((end>>PMD_SHIFT)<<(PMD_SHIFT - PAGE_SHIFT)); | ||
765 | if (start_pfn < end_pfn) { | ||
766 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | ||
767 | page_size_mask & (1<<PG_LEVEL_2M)); | ||
768 | pos = end_pfn << PAGE_SHIFT; | ||
769 | } | ||
770 | |||
771 | /* big page (1G) range */ | ||
772 | start_pfn = ((pos + (PUD_SIZE - 1))>>PUD_SHIFT) | ||
773 | << (PUD_SHIFT - PAGE_SHIFT); | ||
774 | end_pfn = (end >> PUD_SHIFT) << (PUD_SHIFT - PAGE_SHIFT); | ||
775 | if (start_pfn < end_pfn) { | ||
776 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | ||
777 | page_size_mask & | ||
778 | ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G))); | ||
779 | pos = end_pfn << PAGE_SHIFT; | ||
780 | } | ||
781 | |||
782 | /* tail is not big page (1G) alignment */ | ||
783 | start_pfn = ((pos + (PMD_SIZE - 1))>>PMD_SHIFT) | ||
784 | << (PMD_SHIFT - PAGE_SHIFT); | ||
785 | end_pfn = (end >> PMD_SHIFT) << (PMD_SHIFT - PAGE_SHIFT); | ||
786 | if (start_pfn < end_pfn) { | ||
787 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, | ||
788 | page_size_mask & (1<<PG_LEVEL_2M)); | ||
789 | pos = end_pfn << PAGE_SHIFT; | ||
790 | } | ||
791 | |||
792 | /* tail is not big page (2M) alignment */ | ||
793 | start_pfn = pos>>PAGE_SHIFT; | ||
794 | end_pfn = end>>PAGE_SHIFT; | ||
795 | nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); | ||
796 | |||
797 | /* try to merge same page size and continuous */ | ||
798 | for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { | ||
799 | unsigned long old_start; | ||
800 | if (mr[i].end != mr[i+1].start || | ||
801 | mr[i].page_size_mask != mr[i+1].page_size_mask) | ||
802 | continue; | ||
803 | /* move it */ | ||
804 | old_start = mr[i].start; | ||
805 | memmove(&mr[i], &mr[i+1], | ||
806 | (nr_range - 1 - i) * sizeof (struct map_range)); | ||
807 | mr[i--].start = old_start; | ||
808 | nr_range--; | ||
809 | } | ||
810 | |||
811 | for (i = 0; i < nr_range; i++) | ||
812 | printk(KERN_DEBUG " %010lx - %010lx page %s\n", | ||
813 | mr[i].start, mr[i].end, | ||
814 | (mr[i].page_size_mask & (1<<PG_LEVEL_1G))?"1G":( | ||
815 | (mr[i].page_size_mask & (1<<PG_LEVEL_2M))?"2M":"4k")); | ||
816 | |||
817 | if (!after_bootmem) | ||
818 | find_early_table_space(end, use_pse, use_gbpages); | ||
819 | |||
820 | for (i = 0; i < nr_range; i++) | ||
821 | last_map_addr = kernel_physical_mapping_init( | ||
822 | mr[i].start, mr[i].end, | ||
823 | mr[i].page_size_mask); | ||
824 | |||
825 | if (!after_bootmem) | ||
826 | mmu_cr4_features = read_cr4(); | ||
827 | __flush_tlb_all(); | ||
828 | |||
829 | if (!after_bootmem && table_end > table_start) | ||
830 | reserve_early(table_start << PAGE_SHIFT, | ||
831 | table_end << PAGE_SHIFT, "PGTABLE"); | ||
832 | |||
833 | printk(KERN_INFO "last_map_addr: %lx end: %lx\n", | ||
834 | last_map_addr, end); | ||
835 | |||
836 | if (!after_bootmem) | ||
837 | early_memtest(start, end); | ||
838 | |||
839 | return last_map_addr >> PAGE_SHIFT; | ||
840 | } | ||
841 | |||
842 | #ifndef CONFIG_NUMA | 613 | #ifndef CONFIG_NUMA |
843 | void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn) | 614 | void __init initmem_init(unsigned long start_pfn, unsigned long end_pfn) |
844 | { | 615 | { |
@@ -910,28 +681,6 @@ EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid); | |||
910 | 681 | ||
911 | #endif /* CONFIG_MEMORY_HOTPLUG */ | 682 | #endif /* CONFIG_MEMORY_HOTPLUG */ |
912 | 683 | ||
913 | /* | ||
914 | * devmem_is_allowed() checks to see if /dev/mem access to a certain address | ||
915 | * is valid. The argument is a physical page number. | ||
916 | * | ||
917 | * | ||
918 | * On x86, access has to be given to the first megabyte of ram because that area | ||
919 | * contains bios code and data regions used by X and dosemu and similar apps. | ||
920 | * Access has to be given to non-kernel-ram areas as well, these contain the PCI | ||
921 | * mmio resources as well as potential bios/acpi data regions. | ||
922 | */ | ||
923 | int devmem_is_allowed(unsigned long pagenr) | ||
924 | { | ||
925 | if (pagenr <= 256) | ||
926 | return 1; | ||
927 | if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) | ||
928 | return 0; | ||
929 | if (!page_is_ram(pagenr)) | ||
930 | return 1; | ||
931 | return 0; | ||
932 | } | ||
933 | |||
934 | |||
935 | static struct kcore_list kcore_mem, kcore_vmalloc, kcore_kernel, | 684 | static struct kcore_list kcore_mem, kcore_vmalloc, kcore_kernel, |
936 | kcore_modules, kcore_vsyscall; | 685 | kcore_modules, kcore_vsyscall; |
937 | 686 | ||
@@ -1019,13 +768,6 @@ void mark_rodata_ro(void) | |||
1019 | 768 | ||
1020 | #endif | 769 | #endif |
1021 | 770 | ||
1022 | #ifdef CONFIG_BLK_DEV_INITRD | ||
1023 | void free_initrd_mem(unsigned long start, unsigned long end) | ||
1024 | { | ||
1025 | free_init_pages("initrd memory", start, end); | ||
1026 | } | ||
1027 | #endif | ||
1028 | |||
1029 | int __init reserve_bootmem_generic(unsigned long phys, unsigned long len, | 771 | int __init reserve_bootmem_generic(unsigned long phys, unsigned long len, |
1030 | int flags) | 772 | int flags) |
1031 | { | 773 | { |
diff --git a/arch/x86/mm/iomap_32.c b/arch/x86/mm/iomap_32.c index 04102d42ff42..592984e5496b 100644 --- a/arch/x86/mm/iomap_32.c +++ b/arch/x86/mm/iomap_32.c | |||
@@ -18,6 +18,7 @@ | |||
18 | 18 | ||
19 | #include <asm/iomap.h> | 19 | #include <asm/iomap.h> |
20 | #include <asm/pat.h> | 20 | #include <asm/pat.h> |
21 | #include <asm/highmem.h> | ||
21 | #include <linux/module.h> | 22 | #include <linux/module.h> |
22 | 23 | ||
23 | int is_io_mapping_possible(resource_size_t base, unsigned long size) | 24 | int is_io_mapping_possible(resource_size_t base, unsigned long size) |
@@ -36,11 +37,6 @@ EXPORT_SYMBOL_GPL(is_io_mapping_possible); | |||
36 | void * | 37 | void * |
37 | iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot) | 38 | iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot) |
38 | { | 39 | { |
39 | enum fixed_addresses idx; | ||
40 | unsigned long vaddr; | ||
41 | |||
42 | pagefault_disable(); | ||
43 | |||
44 | /* | 40 | /* |
45 | * For non-PAT systems, promote PAGE_KERNEL_WC to PAGE_KERNEL_UC_MINUS. | 41 | * For non-PAT systems, promote PAGE_KERNEL_WC to PAGE_KERNEL_UC_MINUS. |
46 | * PAGE_KERNEL_WC maps to PWT, which translates to uncached if the | 42 | * PAGE_KERNEL_WC maps to PWT, which translates to uncached if the |
@@ -50,12 +46,7 @@ iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot) | |||
50 | if (!pat_enabled && pgprot_val(prot) == pgprot_val(PAGE_KERNEL_WC)) | 46 | if (!pat_enabled && pgprot_val(prot) == pgprot_val(PAGE_KERNEL_WC)) |
51 | prot = PAGE_KERNEL_UC_MINUS; | 47 | prot = PAGE_KERNEL_UC_MINUS; |
52 | 48 | ||
53 | idx = type + KM_TYPE_NR*smp_processor_id(); | 49 | return kmap_atomic_prot_pfn(pfn, type, prot); |
54 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
55 | set_pte(kmap_pte-idx, pfn_pte(pfn, prot)); | ||
56 | arch_flush_lazy_mmu_mode(); | ||
57 | |||
58 | return (void*) vaddr; | ||
59 | } | 50 | } |
60 | EXPORT_SYMBOL_GPL(iomap_atomic_prot_pfn); | 51 | EXPORT_SYMBOL_GPL(iomap_atomic_prot_pfn); |
61 | 52 | ||
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c index 433f7bd4648a..aca924a30ee6 100644 --- a/arch/x86/mm/ioremap.c +++ b/arch/x86/mm/ioremap.c | |||
@@ -38,8 +38,7 @@ unsigned long __phys_addr(unsigned long x) | |||
38 | } else { | 38 | } else { |
39 | VIRTUAL_BUG_ON(x < PAGE_OFFSET); | 39 | VIRTUAL_BUG_ON(x < PAGE_OFFSET); |
40 | x -= PAGE_OFFSET; | 40 | x -= PAGE_OFFSET; |
41 | VIRTUAL_BUG_ON(system_state == SYSTEM_BOOTING ? x > MAXMEM : | 41 | VIRTUAL_BUG_ON(!phys_addr_valid(x)); |
42 | !phys_addr_valid(x)); | ||
43 | } | 42 | } |
44 | return x; | 43 | return x; |
45 | } | 44 | } |
@@ -56,10 +55,8 @@ bool __virt_addr_valid(unsigned long x) | |||
56 | if (x < PAGE_OFFSET) | 55 | if (x < PAGE_OFFSET) |
57 | return false; | 56 | return false; |
58 | x -= PAGE_OFFSET; | 57 | x -= PAGE_OFFSET; |
59 | if (system_state == SYSTEM_BOOTING ? | 58 | if (!phys_addr_valid(x)) |
60 | x > MAXMEM : !phys_addr_valid(x)) { | ||
61 | return false; | 59 | return false; |
62 | } | ||
63 | } | 60 | } |
64 | 61 | ||
65 | return pfn_valid(x >> PAGE_SHIFT); | 62 | return pfn_valid(x >> PAGE_SHIFT); |
@@ -76,10 +73,9 @@ static inline int phys_addr_valid(unsigned long addr) | |||
76 | #ifdef CONFIG_DEBUG_VIRTUAL | 73 | #ifdef CONFIG_DEBUG_VIRTUAL |
77 | unsigned long __phys_addr(unsigned long x) | 74 | unsigned long __phys_addr(unsigned long x) |
78 | { | 75 | { |
79 | /* VMALLOC_* aren't constants; not available at the boot time */ | 76 | /* VMALLOC_* aren't constants */ |
80 | VIRTUAL_BUG_ON(x < PAGE_OFFSET); | 77 | VIRTUAL_BUG_ON(x < PAGE_OFFSET); |
81 | VIRTUAL_BUG_ON(system_state != SYSTEM_BOOTING && | 78 | VIRTUAL_BUG_ON(__vmalloc_start_set && is_vmalloc_addr((void *) x)); |
82 | is_vmalloc_addr((void *) x)); | ||
83 | return x - PAGE_OFFSET; | 79 | return x - PAGE_OFFSET; |
84 | } | 80 | } |
85 | EXPORT_SYMBOL(__phys_addr); | 81 | EXPORT_SYMBOL(__phys_addr); |
@@ -89,7 +85,9 @@ bool __virt_addr_valid(unsigned long x) | |||
89 | { | 85 | { |
90 | if (x < PAGE_OFFSET) | 86 | if (x < PAGE_OFFSET) |
91 | return false; | 87 | return false; |
92 | if (system_state != SYSTEM_BOOTING && is_vmalloc_addr((void *) x)) | 88 | if (__vmalloc_start_set && is_vmalloc_addr((void *) x)) |
89 | return false; | ||
90 | if (x >= FIXADDR_START) | ||
93 | return false; | 91 | return false; |
94 | return pfn_valid((x - PAGE_OFFSET) >> PAGE_SHIFT); | 92 | return pfn_valid((x - PAGE_OFFSET) >> PAGE_SHIFT); |
95 | } | 93 | } |
@@ -508,13 +506,19 @@ static inline pte_t * __init early_ioremap_pte(unsigned long addr) | |||
508 | return &bm_pte[pte_index(addr)]; | 506 | return &bm_pte[pte_index(addr)]; |
509 | } | 507 | } |
510 | 508 | ||
509 | static unsigned long slot_virt[FIX_BTMAPS_SLOTS] __initdata; | ||
510 | |||
511 | void __init early_ioremap_init(void) | 511 | void __init early_ioremap_init(void) |
512 | { | 512 | { |
513 | pmd_t *pmd; | 513 | pmd_t *pmd; |
514 | int i; | ||
514 | 515 | ||
515 | if (early_ioremap_debug) | 516 | if (early_ioremap_debug) |
516 | printk(KERN_INFO "early_ioremap_init()\n"); | 517 | printk(KERN_INFO "early_ioremap_init()\n"); |
517 | 518 | ||
519 | for (i = 0; i < FIX_BTMAPS_SLOTS; i++) | ||
520 | slot_virt[i] = fix_to_virt(FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*i); | ||
521 | |||
518 | pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)); | 522 | pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)); |
519 | memset(bm_pte, 0, sizeof(bm_pte)); | 523 | memset(bm_pte, 0, sizeof(bm_pte)); |
520 | pmd_populate_kernel(&init_mm, pmd, bm_pte); | 524 | pmd_populate_kernel(&init_mm, pmd, bm_pte); |
@@ -581,6 +585,7 @@ static inline void __init early_clear_fixmap(enum fixed_addresses idx) | |||
581 | 585 | ||
582 | static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata; | 586 | static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata; |
583 | static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata; | 587 | static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata; |
588 | |||
584 | static int __init check_early_ioremap_leak(void) | 589 | static int __init check_early_ioremap_leak(void) |
585 | { | 590 | { |
586 | int count = 0; | 591 | int count = 0; |
@@ -602,7 +607,8 @@ static int __init check_early_ioremap_leak(void) | |||
602 | } | 607 | } |
603 | late_initcall(check_early_ioremap_leak); | 608 | late_initcall(check_early_ioremap_leak); |
604 | 609 | ||
605 | static void __init __iomem *__early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot) | 610 | static void __init __iomem * |
611 | __early_ioremap(unsigned long phys_addr, unsigned long size, pgprot_t prot) | ||
606 | { | 612 | { |
607 | unsigned long offset, last_addr; | 613 | unsigned long offset, last_addr; |
608 | unsigned int nrpages; | 614 | unsigned int nrpages; |
@@ -668,9 +674,9 @@ static void __init __iomem *__early_ioremap(unsigned long phys_addr, unsigned lo | |||
668 | --nrpages; | 674 | --nrpages; |
669 | } | 675 | } |
670 | if (early_ioremap_debug) | 676 | if (early_ioremap_debug) |
671 | printk(KERN_CONT "%08lx + %08lx\n", offset, fix_to_virt(idx0)); | 677 | printk(KERN_CONT "%08lx + %08lx\n", offset, slot_virt[slot]); |
672 | 678 | ||
673 | prev_map[slot] = (void __iomem *)(offset + fix_to_virt(idx0)); | 679 | prev_map[slot] = (void __iomem *)(offset + slot_virt[slot]); |
674 | return prev_map[slot]; | 680 | return prev_map[slot]; |
675 | } | 681 | } |
676 | 682 | ||
@@ -738,8 +744,3 @@ void __init early_iounmap(void __iomem *addr, unsigned long size) | |||
738 | } | 744 | } |
739 | prev_map[slot] = NULL; | 745 | prev_map[slot] = NULL; |
740 | } | 746 | } |
741 | |||
742 | void __this_fixmap_does_not_exist(void) | ||
743 | { | ||
744 | WARN_ON(1); | ||
745 | } | ||
diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c index 6a518dd08a36..4f115e00486b 100644 --- a/arch/x86/mm/kmmio.c +++ b/arch/x86/mm/kmmio.c | |||
@@ -310,7 +310,7 @@ static int post_kmmio_handler(unsigned long condition, struct pt_regs *regs) | |||
310 | struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx); | 310 | struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx); |
311 | 311 | ||
312 | if (!ctx->active) { | 312 | if (!ctx->active) { |
313 | pr_warning("kmmio: spurious debug trap on CPU %d.\n", | 313 | pr_debug("kmmio: spurious debug trap on CPU %d.\n", |
314 | smp_processor_id()); | 314 | smp_processor_id()); |
315 | goto out; | 315 | goto out; |
316 | } | 316 | } |
diff --git a/arch/x86/mm/memtest.c b/arch/x86/mm/memtest.c index 0bcd7883d036..605c8be06217 100644 --- a/arch/x86/mm/memtest.c +++ b/arch/x86/mm/memtest.c | |||
@@ -100,6 +100,9 @@ static int __init parse_memtest(char *arg) | |||
100 | { | 100 | { |
101 | if (arg) | 101 | if (arg) |
102 | memtest_pattern = simple_strtoul(arg, NULL, 0); | 102 | memtest_pattern = simple_strtoul(arg, NULL, 0); |
103 | else | ||
104 | memtest_pattern = ARRAY_SIZE(patterns); | ||
105 | |||
103 | return 0; | 106 | return 0; |
104 | } | 107 | } |
105 | 108 | ||
diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c index 451fe95a0352..3daefa04ace5 100644 --- a/arch/x86/mm/numa_32.c +++ b/arch/x86/mm/numa_32.c | |||
@@ -416,10 +416,11 @@ void __init initmem_init(unsigned long start_pfn, | |||
416 | for_each_online_node(nid) | 416 | for_each_online_node(nid) |
417 | propagate_e820_map_node(nid); | 417 | propagate_e820_map_node(nid); |
418 | 418 | ||
419 | for_each_online_node(nid) | 419 | for_each_online_node(nid) { |
420 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); | 420 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); |
421 | NODE_DATA(nid)->bdata = &bootmem_node_data[nid]; | ||
422 | } | ||
421 | 423 | ||
422 | NODE_DATA(0)->bdata = &bootmem_node_data[0]; | ||
423 | setup_bootmem_allocator(); | 424 | setup_bootmem_allocator(); |
424 | } | 425 | } |
425 | 426 | ||
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 8253bc97587e..9c4294986af7 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c | |||
@@ -522,6 +522,17 @@ static int split_large_page(pte_t *kpte, unsigned long address) | |||
522 | * primary protection behavior: | 522 | * primary protection behavior: |
523 | */ | 523 | */ |
524 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); | 524 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
525 | |||
526 | /* | ||
527 | * Intel Atom errata AAH41 workaround. | ||
528 | * | ||
529 | * The real fix should be in hw or in a microcode update, but | ||
530 | * we also probabilistically try to reduce the window of having | ||
531 | * a large TLB mixed with 4K TLBs while instruction fetches are | ||
532 | * going on. | ||
533 | */ | ||
534 | __flush_tlb_all(); | ||
535 | |||
525 | base = NULL; | 536 | base = NULL; |
526 | 537 | ||
527 | out_unlock: | 538 | out_unlock: |