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-rw-r--r--arch/x86/include/asm/amd_nb.h12
-rw-r--r--arch/x86/kernel/alternative.c7
-rw-r--r--arch/x86/kernel/amd_nb.c18
-rw-r--r--arch/x86/kernel/cpu/amd.c4
-rw-r--r--arch/x86/kernel/early-quirks.c7
5 files changed, 32 insertions, 16 deletions
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index e264ae5a1443..331682231bb4 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -13,7 +13,7 @@ extern const struct pci_device_id amd_nb_misc_ids[];
13extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; 13extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
14struct bootnode; 14struct bootnode;
15 15
16extern int early_is_amd_nb(u32 value); 16extern bool early_is_amd_nb(u32 value);
17extern int amd_cache_northbridges(void); 17extern int amd_cache_northbridges(void);
18extern void amd_flush_garts(void); 18extern void amd_flush_garts(void);
19extern int amd_numa_init(void); 19extern int amd_numa_init(void);
@@ -32,18 +32,18 @@ struct amd_northbridge_info {
32}; 32};
33extern struct amd_northbridge_info amd_northbridges; 33extern struct amd_northbridge_info amd_northbridges;
34 34
35#define AMD_NB_GART 0x1 35#define AMD_NB_GART BIT(0)
36#define AMD_NB_L3_INDEX_DISABLE 0x2 36#define AMD_NB_L3_INDEX_DISABLE BIT(1)
37#define AMD_NB_L3_PARTITIONING 0x4 37#define AMD_NB_L3_PARTITIONING BIT(2)
38 38
39#ifdef CONFIG_AMD_NB 39#ifdef CONFIG_AMD_NB
40 40
41static inline int amd_nb_num(void) 41static inline u16 amd_nb_num(void)
42{ 42{
43 return amd_northbridges.num; 43 return amd_northbridges.num;
44} 44}
45 45
46static inline int amd_nb_has_feature(int feature) 46static inline bool amd_nb_has_feature(unsigned feature)
47{ 47{
48 return ((amd_northbridges.flags & feature) == feature); 48 return ((amd_northbridges.flags & feature) == feature);
49} 49}
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 7038b95d363f..4db35544de73 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -620,7 +620,12 @@ static int __kprobes stop_machine_text_poke(void *data)
620 flush_icache_range((unsigned long)p->addr, 620 flush_icache_range((unsigned long)p->addr,
621 (unsigned long)p->addr + p->len); 621 (unsigned long)p->addr + p->len);
622 } 622 }
623 623 /*
624 * Intel Archiecture Software Developer's Manual section 7.1.3 specifies
625 * that a core serializing instruction such as "cpuid" should be
626 * executed on _each_ core before the new instruction is made visible.
627 */
628 sync_core();
624 return 0; 629 return 0;
625} 630}
626 631
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index ed3c2e5b714a..65634190ffd6 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -48,7 +48,7 @@ static struct pci_dev *next_northbridge(struct pci_dev *dev,
48 48
49int amd_cache_northbridges(void) 49int amd_cache_northbridges(void)
50{ 50{
51 int i = 0; 51 u16 i = 0;
52 struct amd_northbridge *nb; 52 struct amd_northbridge *nb;
53 struct pci_dev *misc, *link; 53 struct pci_dev *misc, *link;
54 54
@@ -103,9 +103,11 @@ int amd_cache_northbridges(void)
103} 103}
104EXPORT_SYMBOL_GPL(amd_cache_northbridges); 104EXPORT_SYMBOL_GPL(amd_cache_northbridges);
105 105
106/* Ignores subdevice/subvendor but as far as I can figure out 106/*
107 they're useless anyways */ 107 * Ignores subdevice/subvendor but as far as I can figure out
108int __init early_is_amd_nb(u32 device) 108 * they're useless anyways
109 */
110bool __init early_is_amd_nb(u32 device)
109{ 111{
110 const struct pci_device_id *id; 112 const struct pci_device_id *id;
111 u32 vendor = device & 0xffff; 113 u32 vendor = device & 0xffff;
@@ -113,8 +115,8 @@ int __init early_is_amd_nb(u32 device)
113 device >>= 16; 115 device >>= 16;
114 for (id = amd_nb_misc_ids; id->vendor; id++) 116 for (id = amd_nb_misc_ids; id->vendor; id++)
115 if (vendor == id->vendor && device == id->device) 117 if (vendor == id->vendor && device == id->device)
116 return 1; 118 return true;
117 return 0; 119 return false;
118} 120}
119 121
120int amd_get_subcaches(int cpu) 122int amd_get_subcaches(int cpu)
@@ -176,9 +178,9 @@ int amd_set_subcaches(int cpu, int mask)
176 return 0; 178 return 0;
177} 179}
178 180
179int amd_cache_gart(void) 181static int amd_cache_gart(void)
180{ 182{
181 int i; 183 u16 i;
182 184
183 if (!amd_nb_has_feature(AMD_NB_GART)) 185 if (!amd_nb_has_feature(AMD_NB_GART))
184 return 0; 186 return 0;
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f771ab6b49e9..3ecece0217ef 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -611,6 +611,10 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
611 } 611 }
612 } 612 }
613#endif 613#endif
614
615 /* As a rule processors have APIC timer running in deep C states */
616 if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400))
617 set_cpu_cap(c, X86_FEATURE_ARAT);
614} 618}
615 619
616#ifdef CONFIG_X86_32 620#ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 9efbdcc56425..3755ef494390 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -159,7 +159,12 @@ static void __init ati_bugs_contd(int num, int slot, int func)
159 if (rev >= 0x40) 159 if (rev >= 0x40)
160 acpi_fix_pin2_polarity = 1; 160 acpi_fix_pin2_polarity = 1;
161 161
162 if (rev > 0x13) 162 /*
163 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
164 * SB700: revisions 0x39, 0x3a, ...
165 * SB800: revisions 0x40, 0x41, ...
166 */
167 if (rev >= 0x39)
163 return; 168 return;
164 169
165 if (acpi_use_timer_override) 170 if (acpi_use_timer_override)