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-rw-r--r--arch/x86/include/asm/cpufeature.h2
-rw-r--r--arch/x86/kernel/cpu/common.c1
-rw-r--r--arch/x86/kernel/e820.c8
3 files changed, 7 insertions, 4 deletions
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index f73e95d75b45..cfdf8c2c5c31 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -91,7 +91,7 @@
91#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ 91#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */
92#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ 92#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
93#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ 93#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */
94#define X86_FEATURE_XTOPOLOGY (3*32+21) /* cpu topology enum extensions */ 94#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
95 95
96/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 96/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
97#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ 97#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 003a65395bd5..b9c9ea0217a9 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -20,6 +20,7 @@
20#include <asm/pat.h> 20#include <asm/pat.h>
21#include <asm/asm.h> 21#include <asm/asm.h>
22#include <asm/numa.h> 22#include <asm/numa.h>
23#include <asm/smp.h>
23#ifdef CONFIG_X86_LOCAL_APIC 24#ifdef CONFIG_X86_LOCAL_APIC
24#include <asm/mpspec.h> 25#include <asm/mpspec.h>
25#include <asm/apic.h> 26#include <asm/apic.h>
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index ce97bf3bed12..7aafeb5263ef 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -1290,15 +1290,17 @@ void __init e820_reserve_resources(void)
1290 res->start = e820.map[i].addr; 1290 res->start = e820.map[i].addr;
1291 res->end = end; 1291 res->end = end;
1292 1292
1293 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 1293 res->flags = IORESOURCE_MEM;
1294 1294
1295 /* 1295 /*
1296 * don't register the region that could be conflicted with 1296 * don't register the region that could be conflicted with
1297 * pci device BAR resource and insert them later in 1297 * pci device BAR resource and insert them later in
1298 * pcibios_resource_survey() 1298 * pcibios_resource_survey()
1299 */ 1299 */
1300 if (e820.map[i].type != E820_RESERVED || res->start < (1ULL<<20)) 1300 if (e820.map[i].type != E820_RESERVED || res->start < (1ULL<<20)) {
1301 res->flags |= IORESOURCE_BUSY;
1301 insert_resource(&iomem_resource, res); 1302 insert_resource(&iomem_resource, res);
1303 }
1302 res++; 1304 res++;
1303 } 1305 }
1304 1306
@@ -1318,7 +1320,7 @@ void __init e820_reserve_resources_late(void)
1318 res = e820_res; 1320 res = e820_res;
1319 for (i = 0; i < e820.nr_map; i++) { 1321 for (i = 0; i < e820.nr_map; i++) {
1320 if (!res->parent && res->end) 1322 if (!res->parent && res->end)
1321 reserve_region_with_split(&iomem_resource, res->start, res->end, res->name); 1323 insert_resource_expand_to_fit(&iomem_resource, res);
1322 res++; 1324 res++;
1323 } 1325 }
1324} 1326}