diff options
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/Kconfig | 2 | ||||
| -rw-r--r-- | arch/x86/include/asm/uv/uv_bau.h | 2 | ||||
| -rw-r--r-- | arch/x86/kernel/apic/x2apic_uv_x.c | 4 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/amd.c | 7 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/common.c | 48 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce.c | 19 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/mcheck/therm_throt.c | 23 | ||||
| -rw-r--r-- | arch/x86/kernel/cpu/perf_counter.c | 40 | ||||
| -rw-r--r-- | arch/x86/kernel/reboot.c | 12 | ||||
| -rw-r--r-- | arch/x86/kernel/setup_percpu.c | 14 | ||||
| -rw-r--r-- | arch/x86/kernel/tlb_uv.c | 1 |
11 files changed, 113 insertions, 59 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 738bdc6b0f8b..13ffa5df37d7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig | |||
| @@ -24,6 +24,7 @@ config X86 | |||
| 24 | select HAVE_UNSTABLE_SCHED_CLOCK | 24 | select HAVE_UNSTABLE_SCHED_CLOCK |
| 25 | select HAVE_IDE | 25 | select HAVE_IDE |
| 26 | select HAVE_OPROFILE | 26 | select HAVE_OPROFILE |
| 27 | select HAVE_PERF_COUNTERS if (!M386 && !M486) | ||
| 27 | select HAVE_IOREMAP_PROT | 28 | select HAVE_IOREMAP_PROT |
| 28 | select HAVE_KPROBES | 29 | select HAVE_KPROBES |
| 29 | select ARCH_WANT_OPTIONAL_GPIOLIB | 30 | select ARCH_WANT_OPTIONAL_GPIOLIB |
| @@ -742,7 +743,6 @@ config X86_UP_IOAPIC | |||
| 742 | config X86_LOCAL_APIC | 743 | config X86_LOCAL_APIC |
| 743 | def_bool y | 744 | def_bool y |
| 744 | depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC | 745 | depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC |
| 745 | select HAVE_PERF_COUNTERS if (!M386 && !M486) | ||
| 746 | 746 | ||
| 747 | config X86_IO_APIC | 747 | config X86_IO_APIC |
| 748 | def_bool y | 748 | def_bool y |
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h index bddd44f2f0ab..80e2984f521c 100644 --- a/arch/x86/include/asm/uv/uv_bau.h +++ b/arch/x86/include/asm/uv/uv_bau.h | |||
| @@ -133,7 +133,7 @@ struct bau_msg_payload { | |||
| 133 | * see table 4.2.3.0.1 in broacast_assist spec. | 133 | * see table 4.2.3.0.1 in broacast_assist spec. |
| 134 | */ | 134 | */ |
| 135 | struct bau_msg_header { | 135 | struct bau_msg_header { |
| 136 | unsigned int dest_subnodeid:6; /* must be zero */ | 136 | unsigned int dest_subnodeid:6; /* must be 0x10, for the LB */ |
| 137 | /* bits 5:0 */ | 137 | /* bits 5:0 */ |
| 138 | unsigned int base_dest_nodeid:15; /* nasid>>1 (pnode) of */ | 138 | unsigned int base_dest_nodeid:15; /* nasid>>1 (pnode) of */ |
| 139 | /* bits 20:6 */ /* first bit in node_map */ | 139 | /* bits 20:6 */ /* first bit in node_map */ |
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index 832e908adcb5..601159374e87 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c | |||
| @@ -46,7 +46,7 @@ static int early_get_nodeid(void) | |||
| 46 | return node_id.s.node_id; | 46 | return node_id.s.node_id; |
| 47 | } | 47 | } |
| 48 | 48 | ||
| 49 | static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | 49 | static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
| 50 | { | 50 | { |
| 51 | if (!strcmp(oem_id, "SGI")) { | 51 | if (!strcmp(oem_id, "SGI")) { |
| 52 | if (!strcmp(oem_table_id, "UVL")) | 52 | if (!strcmp(oem_table_id, "UVL")) |
| @@ -253,7 +253,7 @@ static void uv_send_IPI_self(int vector) | |||
| 253 | apic_write(APIC_SELF_IPI, vector); | 253 | apic_write(APIC_SELF_IPI, vector); |
| 254 | } | 254 | } |
| 255 | 255 | ||
| 256 | struct apic apic_x2apic_uv_x = { | 256 | struct apic __refdata apic_x2apic_uv_x = { |
| 257 | 257 | ||
| 258 | .name = "UV large system", | 258 | .name = "UV large system", |
| 259 | .probe = NULL, | 259 | .probe = NULL, |
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e2485b03f1cf..63fddcd082cd 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c | |||
| @@ -400,6 +400,13 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) | |||
| 400 | level = cpuid_eax(1); | 400 | level = cpuid_eax(1); |
| 401 | if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | 401 | if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) |
| 402 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | 402 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
| 403 | |||
| 404 | /* | ||
| 405 | * Some BIOSes incorrectly force this feature, but only K8 | ||
| 406 | * revision D (model = 0x14) and later actually support it. | ||
| 407 | */ | ||
| 408 | if (c->x86_model < 0x14) | ||
| 409 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | ||
| 403 | } | 410 | } |
| 404 | if (c->x86 == 0x10 || c->x86 == 0x11) | 411 | if (c->x86 == 0x10 || c->x86 == 0x11) |
| 405 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | 412 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f1961c07af9a..5ce60a88027b 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c | |||
| @@ -59,7 +59,30 @@ void __init setup_cpu_local_masks(void) | |||
| 59 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | 59 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); |
| 60 | } | 60 | } |
| 61 | 61 | ||
| 62 | static const struct cpu_dev *this_cpu __cpuinitdata; | 62 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
| 63 | { | ||
| 64 | #ifdef CONFIG_X86_64 | ||
| 65 | display_cacheinfo(c); | ||
| 66 | #else | ||
| 67 | /* Not much we can do here... */ | ||
| 68 | /* Check if at least it has cpuid */ | ||
| 69 | if (c->cpuid_level == -1) { | ||
| 70 | /* No cpuid. It must be an ancient CPU */ | ||
| 71 | if (c->x86 == 4) | ||
| 72 | strcpy(c->x86_model_id, "486"); | ||
| 73 | else if (c->x86 == 3) | ||
| 74 | strcpy(c->x86_model_id, "386"); | ||
| 75 | } | ||
| 76 | #endif | ||
| 77 | } | ||
| 78 | |||
| 79 | static const struct cpu_dev __cpuinitconst default_cpu = { | ||
| 80 | .c_init = default_init, | ||
| 81 | .c_vendor = "Unknown", | ||
| 82 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | ||
| 63 | 86 | ||
| 64 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { | 87 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
| 65 | #ifdef CONFIG_X86_64 | 88 | #ifdef CONFIG_X86_64 |
| @@ -332,29 +355,6 @@ void switch_to_new_gdt(int cpu) | |||
| 332 | 355 | ||
| 333 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; | 356 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
| 334 | 357 | ||
| 335 | static void __cpuinit default_init(struct cpuinfo_x86 *c) | ||
| 336 | { | ||
| 337 | #ifdef CONFIG_X86_64 | ||
| 338 | display_cacheinfo(c); | ||
| 339 | #else | ||
| 340 | /* Not much we can do here... */ | ||
| 341 | /* Check if at least it has cpuid */ | ||
| 342 | if (c->cpuid_level == -1) { | ||
| 343 | /* No cpuid. It must be an ancient CPU */ | ||
| 344 | if (c->x86 == 4) | ||
| 345 | strcpy(c->x86_model_id, "486"); | ||
| 346 | else if (c->x86 == 3) | ||
| 347 | strcpy(c->x86_model_id, "386"); | ||
| 348 | } | ||
| 349 | #endif | ||
| 350 | } | ||
| 351 | |||
| 352 | static const struct cpu_dev __cpuinitconst default_cpu = { | ||
| 353 | .c_init = default_init, | ||
| 354 | .c_vendor = "Unknown", | ||
| 355 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | ||
| 356 | }; | ||
| 357 | |||
| 358 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) | 358 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
| 359 | { | 359 | { |
| 360 | unsigned int *v; | 360 | unsigned int *v; |
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 1cfb623ce11c..01213048f62f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c | |||
| @@ -1226,8 +1226,13 @@ static void mce_init(void) | |||
| 1226 | } | 1226 | } |
| 1227 | 1227 | ||
| 1228 | /* Add per CPU specific workarounds here */ | 1228 | /* Add per CPU specific workarounds here */ |
| 1229 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) | 1229 | static int mce_cpu_quirks(struct cpuinfo_x86 *c) |
| 1230 | { | 1230 | { |
| 1231 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { | ||
| 1232 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | ||
| 1233 | return -EOPNOTSUPP; | ||
| 1234 | } | ||
| 1235 | |||
| 1231 | /* This should be disabled by the BIOS, but isn't always */ | 1236 | /* This should be disabled by the BIOS, but isn't always */ |
| 1232 | if (c->x86_vendor == X86_VENDOR_AMD) { | 1237 | if (c->x86_vendor == X86_VENDOR_AMD) { |
| 1233 | if (c->x86 == 15 && banks > 4) { | 1238 | if (c->x86 == 15 && banks > 4) { |
| @@ -1273,11 +1278,20 @@ static void mce_cpu_quirks(struct cpuinfo_x86 *c) | |||
| 1273 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | 1278 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && |
| 1274 | monarch_timeout < 0) | 1279 | monarch_timeout < 0) |
| 1275 | monarch_timeout = USEC_PER_SEC; | 1280 | monarch_timeout = USEC_PER_SEC; |
| 1281 | |||
| 1282 | /* | ||
| 1283 | * There are also broken BIOSes on some Pentium M and | ||
| 1284 | * earlier systems: | ||
| 1285 | */ | ||
| 1286 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | ||
| 1287 | mce_bootlog = 0; | ||
| 1276 | } | 1288 | } |
| 1277 | if (monarch_timeout < 0) | 1289 | if (monarch_timeout < 0) |
| 1278 | monarch_timeout = 0; | 1290 | monarch_timeout = 0; |
| 1279 | if (mce_bootlog != 0) | 1291 | if (mce_bootlog != 0) |
| 1280 | mce_panic_timeout = 30; | 1292 | mce_panic_timeout = 30; |
| 1293 | |||
| 1294 | return 0; | ||
| 1281 | } | 1295 | } |
| 1282 | 1296 | ||
| 1283 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) | 1297 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
| @@ -1338,11 +1352,10 @@ void __cpuinit mcheck_init(struct cpuinfo_x86 *c) | |||
| 1338 | if (!mce_available(c)) | 1352 | if (!mce_available(c)) |
| 1339 | return; | 1353 | return; |
| 1340 | 1354 | ||
| 1341 | if (mce_cap_init() < 0) { | 1355 | if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) { |
| 1342 | mce_disabled = 1; | 1356 | mce_disabled = 1; |
| 1343 | return; | 1357 | return; |
| 1344 | } | 1358 | } |
| 1345 | mce_cpu_quirks(c); | ||
| 1346 | 1359 | ||
| 1347 | machine_check_vector = do_machine_check; | 1360 | machine_check_vector = do_machine_check; |
| 1348 | 1361 | ||
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c index bff8dd191dd5..5957a93e5173 100644 --- a/arch/x86/kernel/cpu/mcheck/therm_throt.c +++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c | |||
| @@ -36,6 +36,7 @@ | |||
| 36 | 36 | ||
| 37 | static DEFINE_PER_CPU(__u64, next_check) = INITIAL_JIFFIES; | 37 | static DEFINE_PER_CPU(__u64, next_check) = INITIAL_JIFFIES; |
| 38 | static DEFINE_PER_CPU(unsigned long, thermal_throttle_count); | 38 | static DEFINE_PER_CPU(unsigned long, thermal_throttle_count); |
| 39 | static DEFINE_PER_CPU(bool, thermal_throttle_active); | ||
| 39 | 40 | ||
| 40 | static atomic_t therm_throt_en = ATOMIC_INIT(0); | 41 | static atomic_t therm_throt_en = ATOMIC_INIT(0); |
| 41 | 42 | ||
| @@ -96,27 +97,33 @@ static int therm_throt_process(int curr) | |||
| 96 | { | 97 | { |
| 97 | unsigned int cpu = smp_processor_id(); | 98 | unsigned int cpu = smp_processor_id(); |
| 98 | __u64 tmp_jiffs = get_jiffies_64(); | 99 | __u64 tmp_jiffs = get_jiffies_64(); |
| 100 | bool was_throttled = __get_cpu_var(thermal_throttle_active); | ||
| 101 | bool is_throttled = __get_cpu_var(thermal_throttle_active) = curr; | ||
| 99 | 102 | ||
| 100 | if (curr) | 103 | if (is_throttled) |
| 101 | __get_cpu_var(thermal_throttle_count)++; | 104 | __get_cpu_var(thermal_throttle_count)++; |
| 102 | 105 | ||
| 103 | if (time_before64(tmp_jiffs, __get_cpu_var(next_check))) | 106 | if (!(was_throttled ^ is_throttled) && |
| 107 | time_before64(tmp_jiffs, __get_cpu_var(next_check))) | ||
| 104 | return 0; | 108 | return 0; |
| 105 | 109 | ||
| 106 | __get_cpu_var(next_check) = tmp_jiffs + CHECK_INTERVAL; | 110 | __get_cpu_var(next_check) = tmp_jiffs + CHECK_INTERVAL; |
| 107 | 111 | ||
| 108 | /* if we just entered the thermal event */ | 112 | /* if we just entered the thermal event */ |
| 109 | if (curr) { | 113 | if (is_throttled) { |
| 110 | printk(KERN_CRIT "CPU%d: Temperature above threshold, " | 114 | printk(KERN_CRIT "CPU%d: Temperature above threshold, " |
| 111 | "cpu clock throttled (total events = %lu)\n", cpu, | 115 | "cpu clock throttled (total events = %lu)\n", |
| 112 | __get_cpu_var(thermal_throttle_count)); | 116 | cpu, __get_cpu_var(thermal_throttle_count)); |
| 113 | 117 | ||
| 114 | add_taint(TAINT_MACHINE_CHECK); | 118 | add_taint(TAINT_MACHINE_CHECK); |
| 115 | } else { | 119 | return 1; |
| 116 | printk(KERN_CRIT "CPU%d: Temperature/speed normal\n", cpu); | 120 | } |
| 121 | if (was_throttled) { | ||
| 122 | printk(KERN_INFO "CPU%d: Temperature/speed normal\n", cpu); | ||
| 123 | return 1; | ||
| 117 | } | 124 | } |
| 118 | 125 | ||
| 119 | return 1; | 126 | return 0; |
| 120 | } | 127 | } |
| 121 | 128 | ||
| 122 | #ifdef CONFIG_SYSFS | 129 | #ifdef CONFIG_SYSFS |
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index a7aa8f900954..900332b800f8 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c | |||
| @@ -55,6 +55,7 @@ struct x86_pmu { | |||
| 55 | int num_counters_fixed; | 55 | int num_counters_fixed; |
| 56 | int counter_bits; | 56 | int counter_bits; |
| 57 | u64 counter_mask; | 57 | u64 counter_mask; |
| 58 | int apic; | ||
| 58 | u64 max_period; | 59 | u64 max_period; |
| 59 | u64 intel_ctrl; | 60 | u64 intel_ctrl; |
| 60 | }; | 61 | }; |
| @@ -72,8 +73,8 @@ static const u64 p6_perfmon_event_map[] = | |||
| 72 | { | 73 | { |
| 73 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, | 74 | [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, |
| 74 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | 75 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| 75 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0000, | 76 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, |
| 76 | [PERF_COUNT_HW_CACHE_MISSES] = 0x0000, | 77 | [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, |
| 77 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | 78 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
| 78 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | 79 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
| 79 | [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, | 80 | [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, |
| @@ -613,6 +614,7 @@ static DEFINE_MUTEX(pmc_reserve_mutex); | |||
| 613 | 614 | ||
| 614 | static bool reserve_pmc_hardware(void) | 615 | static bool reserve_pmc_hardware(void) |
| 615 | { | 616 | { |
| 617 | #ifdef CONFIG_X86_LOCAL_APIC | ||
| 616 | int i; | 618 | int i; |
| 617 | 619 | ||
| 618 | if (nmi_watchdog == NMI_LOCAL_APIC) | 620 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| @@ -627,9 +629,11 @@ static bool reserve_pmc_hardware(void) | |||
| 627 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) | 629 | if (!reserve_evntsel_nmi(x86_pmu.eventsel + i)) |
| 628 | goto eventsel_fail; | 630 | goto eventsel_fail; |
| 629 | } | 631 | } |
| 632 | #endif | ||
| 630 | 633 | ||
| 631 | return true; | 634 | return true; |
| 632 | 635 | ||
| 636 | #ifdef CONFIG_X86_LOCAL_APIC | ||
| 633 | eventsel_fail: | 637 | eventsel_fail: |
| 634 | for (i--; i >= 0; i--) | 638 | for (i--; i >= 0; i--) |
| 635 | release_evntsel_nmi(x86_pmu.eventsel + i); | 639 | release_evntsel_nmi(x86_pmu.eventsel + i); |
| @@ -644,10 +648,12 @@ perfctr_fail: | |||
| 644 | enable_lapic_nmi_watchdog(); | 648 | enable_lapic_nmi_watchdog(); |
| 645 | 649 | ||
| 646 | return false; | 650 | return false; |
| 651 | #endif | ||
| 647 | } | 652 | } |
| 648 | 653 | ||
| 649 | static void release_pmc_hardware(void) | 654 | static void release_pmc_hardware(void) |
| 650 | { | 655 | { |
| 656 | #ifdef CONFIG_X86_LOCAL_APIC | ||
| 651 | int i; | 657 | int i; |
| 652 | 658 | ||
| 653 | for (i = 0; i < x86_pmu.num_counters; i++) { | 659 | for (i = 0; i < x86_pmu.num_counters; i++) { |
| @@ -657,6 +663,7 @@ static void release_pmc_hardware(void) | |||
| 657 | 663 | ||
| 658 | if (nmi_watchdog == NMI_LOCAL_APIC) | 664 | if (nmi_watchdog == NMI_LOCAL_APIC) |
| 659 | enable_lapic_nmi_watchdog(); | 665 | enable_lapic_nmi_watchdog(); |
| 666 | #endif | ||
| 660 | } | 667 | } |
| 661 | 668 | ||
| 662 | static void hw_perf_counter_destroy(struct perf_counter *counter) | 669 | static void hw_perf_counter_destroy(struct perf_counter *counter) |
| @@ -748,6 +755,15 @@ static int __hw_perf_counter_init(struct perf_counter *counter) | |||
| 748 | hwc->sample_period = x86_pmu.max_period; | 755 | hwc->sample_period = x86_pmu.max_period; |
| 749 | hwc->last_period = hwc->sample_period; | 756 | hwc->last_period = hwc->sample_period; |
| 750 | atomic64_set(&hwc->period_left, hwc->sample_period); | 757 | atomic64_set(&hwc->period_left, hwc->sample_period); |
| 758 | } else { | ||
| 759 | /* | ||
| 760 | * If we have a PMU initialized but no APIC | ||
| 761 | * interrupts, we cannot sample hardware | ||
| 762 | * counters (user-space has to fall back and | ||
| 763 | * sample via a hrtimer based software counter): | ||
| 764 | */ | ||
| 765 | if (!x86_pmu.apic) | ||
| 766 | return -EOPNOTSUPP; | ||
| 751 | } | 767 | } |
| 752 | 768 | ||
| 753 | counter->destroy = hw_perf_counter_destroy; | 769 | counter->destroy = hw_perf_counter_destroy; |
| @@ -1449,18 +1465,22 @@ void smp_perf_pending_interrupt(struct pt_regs *regs) | |||
| 1449 | 1465 | ||
| 1450 | void set_perf_counter_pending(void) | 1466 | void set_perf_counter_pending(void) |
| 1451 | { | 1467 | { |
| 1468 | #ifdef CONFIG_X86_LOCAL_APIC | ||
| 1452 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); | 1469 | apic->send_IPI_self(LOCAL_PENDING_VECTOR); |
| 1470 | #endif | ||
| 1453 | } | 1471 | } |
| 1454 | 1472 | ||
| 1455 | void perf_counters_lapic_init(void) | 1473 | void perf_counters_lapic_init(void) |
| 1456 | { | 1474 | { |
| 1457 | if (!x86_pmu_initialized()) | 1475 | #ifdef CONFIG_X86_LOCAL_APIC |
| 1476 | if (!x86_pmu.apic || !x86_pmu_initialized()) | ||
| 1458 | return; | 1477 | return; |
| 1459 | 1478 | ||
| 1460 | /* | 1479 | /* |
| 1461 | * Always use NMI for PMU | 1480 | * Always use NMI for PMU |
| 1462 | */ | 1481 | */ |
| 1463 | apic_write(APIC_LVTPC, APIC_DM_NMI); | 1482 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 1483 | #endif | ||
| 1464 | } | 1484 | } |
| 1465 | 1485 | ||
| 1466 | static int __kprobes | 1486 | static int __kprobes |
| @@ -1484,7 +1504,9 @@ perf_counter_nmi_handler(struct notifier_block *self, | |||
| 1484 | 1504 | ||
| 1485 | regs = args->regs; | 1505 | regs = args->regs; |
| 1486 | 1506 | ||
| 1507 | #ifdef CONFIG_X86_LOCAL_APIC | ||
| 1487 | apic_write(APIC_LVTPC, APIC_DM_NMI); | 1508 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
| 1509 | #endif | ||
| 1488 | /* | 1510 | /* |
| 1489 | * Can't rely on the handled return value to say it was our NMI, two | 1511 | * Can't rely on the handled return value to say it was our NMI, two |
| 1490 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. | 1512 | * counters could trigger 'simultaneously' raising two back-to-back NMIs. |
| @@ -1515,6 +1537,7 @@ static struct x86_pmu p6_pmu = { | |||
| 1515 | .event_map = p6_pmu_event_map, | 1537 | .event_map = p6_pmu_event_map, |
| 1516 | .raw_event = p6_pmu_raw_event, | 1538 | .raw_event = p6_pmu_raw_event, |
| 1517 | .max_events = ARRAY_SIZE(p6_perfmon_event_map), | 1539 | .max_events = ARRAY_SIZE(p6_perfmon_event_map), |
| 1540 | .apic = 1, | ||
| 1518 | .max_period = (1ULL << 31) - 1, | 1541 | .max_period = (1ULL << 31) - 1, |
| 1519 | .version = 0, | 1542 | .version = 0, |
| 1520 | .num_counters = 2, | 1543 | .num_counters = 2, |
| @@ -1541,6 +1564,7 @@ static struct x86_pmu intel_pmu = { | |||
| 1541 | .event_map = intel_pmu_event_map, | 1564 | .event_map = intel_pmu_event_map, |
| 1542 | .raw_event = intel_pmu_raw_event, | 1565 | .raw_event = intel_pmu_raw_event, |
| 1543 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), | 1566 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
| 1567 | .apic = 1, | ||
| 1544 | /* | 1568 | /* |
| 1545 | * Intel PMCs cannot be accessed sanely above 32 bit width, | 1569 | * Intel PMCs cannot be accessed sanely above 32 bit width, |
| 1546 | * so we install an artificial 1<<31 period regardless of | 1570 | * so we install an artificial 1<<31 period regardless of |
| @@ -1564,6 +1588,7 @@ static struct x86_pmu amd_pmu = { | |||
| 1564 | .num_counters = 4, | 1588 | .num_counters = 4, |
| 1565 | .counter_bits = 48, | 1589 | .counter_bits = 48, |
| 1566 | .counter_mask = (1ULL << 48) - 1, | 1590 | .counter_mask = (1ULL << 48) - 1, |
| 1591 | .apic = 1, | ||
| 1567 | /* use highest bit to detect overflow */ | 1592 | /* use highest bit to detect overflow */ |
| 1568 | .max_period = (1ULL << 47) - 1, | 1593 | .max_period = (1ULL << 47) - 1, |
| 1569 | }; | 1594 | }; |
| @@ -1589,13 +1614,14 @@ static int p6_pmu_init(void) | |||
| 1589 | return -ENODEV; | 1614 | return -ENODEV; |
| 1590 | } | 1615 | } |
| 1591 | 1616 | ||
| 1617 | x86_pmu = p6_pmu; | ||
| 1618 | |||
| 1592 | if (!cpu_has_apic) { | 1619 | if (!cpu_has_apic) { |
| 1593 | pr_info("no Local APIC, try rebooting with lapic"); | 1620 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); |
| 1594 | return -ENODEV; | 1621 | pr_info("no hardware sampling interrupt available.\n"); |
| 1622 | x86_pmu.apic = 0; | ||
| 1595 | } | 1623 | } |
| 1596 | 1624 | ||
| 1597 | x86_pmu = p6_pmu; | ||
| 1598 | |||
| 1599 | return 0; | 1625 | return 0; |
| 1600 | } | 1626 | } |
| 1601 | 1627 | ||
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 9eb897603705..a06e8d101844 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c | |||
| @@ -418,20 +418,20 @@ static int __init set_pci_reboot(const struct dmi_system_id *d) | |||
| 418 | } | 418 | } |
| 419 | 419 | ||
| 420 | static struct dmi_system_id __initdata pci_reboot_dmi_table[] = { | 420 | static struct dmi_system_id __initdata pci_reboot_dmi_table[] = { |
| 421 | { /* Handle problems with rebooting on Apple MacBook5,2 */ | 421 | { /* Handle problems with rebooting on Apple MacBook5 */ |
| 422 | .callback = set_pci_reboot, | 422 | .callback = set_pci_reboot, |
| 423 | .ident = "Apple MacBook", | 423 | .ident = "Apple MacBook5", |
| 424 | .matches = { | 424 | .matches = { |
| 425 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | 425 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
| 426 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBook5,2"), | 426 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBook5"), |
| 427 | }, | 427 | }, |
| 428 | }, | 428 | }, |
| 429 | { /* Handle problems with rebooting on Apple MacBookPro5,1 */ | 429 | { /* Handle problems with rebooting on Apple MacBookPro5 */ |
| 430 | .callback = set_pci_reboot, | 430 | .callback = set_pci_reboot, |
| 431 | .ident = "Apple MacBookPro5,1", | 431 | .ident = "Apple MacBookPro5", |
| 432 | .matches = { | 432 | .matches = { |
| 433 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | 433 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), |
| 434 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5,1"), | 434 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro5"), |
| 435 | }, | 435 | }, |
| 436 | }, | 436 | }, |
| 437 | { } | 437 | { } |
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c index 29a3eef7cf4a..07d81916f212 100644 --- a/arch/x86/kernel/setup_percpu.c +++ b/arch/x86/kernel/setup_percpu.c | |||
| @@ -165,7 +165,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen) | |||
| 165 | 165 | ||
| 166 | if (!chosen) { | 166 | if (!chosen) { |
| 167 | size_t vm_size = VMALLOC_END - VMALLOC_START; | 167 | size_t vm_size = VMALLOC_END - VMALLOC_START; |
| 168 | size_t tot_size = num_possible_cpus() * PMD_SIZE; | 168 | size_t tot_size = nr_cpu_ids * PMD_SIZE; |
| 169 | 169 | ||
| 170 | /* on non-NUMA, embedding is better */ | 170 | /* on non-NUMA, embedding is better */ |
| 171 | if (!pcpu_need_numa()) | 171 | if (!pcpu_need_numa()) |
| @@ -199,7 +199,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen) | |||
| 199 | dyn_size = pcpul_size - static_size - PERCPU_FIRST_CHUNK_RESERVE; | 199 | dyn_size = pcpul_size - static_size - PERCPU_FIRST_CHUNK_RESERVE; |
| 200 | 200 | ||
| 201 | /* allocate pointer array and alloc large pages */ | 201 | /* allocate pointer array and alloc large pages */ |
| 202 | map_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpul_map[0])); | 202 | map_size = PFN_ALIGN(nr_cpu_ids * sizeof(pcpul_map[0])); |
| 203 | pcpul_map = alloc_bootmem(map_size); | 203 | pcpul_map = alloc_bootmem(map_size); |
| 204 | 204 | ||
| 205 | for_each_possible_cpu(cpu) { | 205 | for_each_possible_cpu(cpu) { |
| @@ -228,7 +228,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen) | |||
| 228 | 228 | ||
| 229 | /* allocate address and map */ | 229 | /* allocate address and map */ |
| 230 | pcpul_vm.flags = VM_ALLOC; | 230 | pcpul_vm.flags = VM_ALLOC; |
| 231 | pcpul_vm.size = num_possible_cpus() * PMD_SIZE; | 231 | pcpul_vm.size = nr_cpu_ids * PMD_SIZE; |
| 232 | vm_area_register_early(&pcpul_vm, PMD_SIZE); | 232 | vm_area_register_early(&pcpul_vm, PMD_SIZE); |
| 233 | 233 | ||
| 234 | for_each_possible_cpu(cpu) { | 234 | for_each_possible_cpu(cpu) { |
| @@ -250,8 +250,8 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen) | |||
| 250 | PMD_SIZE, pcpul_vm.addr, NULL); | 250 | PMD_SIZE, pcpul_vm.addr, NULL); |
| 251 | 251 | ||
| 252 | /* sort pcpul_map array for pcpu_lpage_remapped() */ | 252 | /* sort pcpul_map array for pcpu_lpage_remapped() */ |
| 253 | for (i = 0; i < num_possible_cpus() - 1; i++) | 253 | for (i = 0; i < nr_cpu_ids - 1; i++) |
| 254 | for (j = i + 1; j < num_possible_cpus(); j++) | 254 | for (j = i + 1; j < nr_cpu_ids; j++) |
| 255 | if (pcpul_map[i].ptr > pcpul_map[j].ptr) { | 255 | if (pcpul_map[i].ptr > pcpul_map[j].ptr) { |
| 256 | struct pcpul_ent tmp = pcpul_map[i]; | 256 | struct pcpul_ent tmp = pcpul_map[i]; |
| 257 | pcpul_map[i] = pcpul_map[j]; | 257 | pcpul_map[i] = pcpul_map[j]; |
| @@ -288,7 +288,7 @@ void *pcpu_lpage_remapped(void *kaddr) | |||
| 288 | { | 288 | { |
| 289 | void *pmd_addr = (void *)((unsigned long)kaddr & PMD_MASK); | 289 | void *pmd_addr = (void *)((unsigned long)kaddr & PMD_MASK); |
| 290 | unsigned long offset = (unsigned long)kaddr & ~PMD_MASK; | 290 | unsigned long offset = (unsigned long)kaddr & ~PMD_MASK; |
| 291 | int left = 0, right = num_possible_cpus() - 1; | 291 | int left = 0, right = nr_cpu_ids - 1; |
| 292 | int pos; | 292 | int pos; |
| 293 | 293 | ||
| 294 | /* pcpul in use at all? */ | 294 | /* pcpul in use at all? */ |
| @@ -377,7 +377,7 @@ static ssize_t __init setup_pcpu_4k(size_t static_size) | |||
| 377 | pcpu4k_nr_static_pages = PFN_UP(static_size); | 377 | pcpu4k_nr_static_pages = PFN_UP(static_size); |
| 378 | 378 | ||
| 379 | /* unaligned allocations can't be freed, round up to page size */ | 379 | /* unaligned allocations can't be freed, round up to page size */ |
| 380 | pages_size = PFN_ALIGN(pcpu4k_nr_static_pages * num_possible_cpus() | 380 | pages_size = PFN_ALIGN(pcpu4k_nr_static_pages * nr_cpu_ids |
| 381 | * sizeof(pcpu4k_pages[0])); | 381 | * sizeof(pcpu4k_pages[0])); |
| 382 | pcpu4k_pages = alloc_bootmem(pages_size); | 382 | pcpu4k_pages = alloc_bootmem(pages_size); |
| 383 | 383 | ||
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c index 8ccabb8a2f6a..77b9689f8edb 100644 --- a/arch/x86/kernel/tlb_uv.c +++ b/arch/x86/kernel/tlb_uv.c | |||
| @@ -744,6 +744,7 @@ uv_activation_descriptor_init(int node, int pnode) | |||
| 744 | * note that base_dest_nodeid is actually a nasid. | 744 | * note that base_dest_nodeid is actually a nasid. |
| 745 | */ | 745 | */ |
| 746 | ad2->header.base_dest_nodeid = uv_partition_base_pnode << 1; | 746 | ad2->header.base_dest_nodeid = uv_partition_base_pnode << 1; |
| 747 | ad2->header.dest_subnodeid = 0x10; /* the LB */ | ||
| 747 | ad2->header.command = UV_NET_ENDPOINT_INTD; | 748 | ad2->header.command = UV_NET_ENDPOINT_INTD; |
| 748 | ad2->header.int_both = 1; | 749 | ad2->header.int_both = 1; |
| 749 | /* | 750 | /* |