diff options
Diffstat (limited to 'arch/x86')
26 files changed, 135 insertions, 79 deletions
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S index a0559930a180..c85e3ac99bba 100644 --- a/arch/x86/boot/compressed/head_32.S +++ b/arch/x86/boot/compressed/head_32.S | |||
@@ -33,6 +33,9 @@ | |||
33 | __HEAD | 33 | __HEAD |
34 | ENTRY(startup_32) | 34 | ENTRY(startup_32) |
35 | #ifdef CONFIG_EFI_STUB | 35 | #ifdef CONFIG_EFI_STUB |
36 | jmp preferred_addr | ||
37 | |||
38 | .balign 0x10 | ||
36 | /* | 39 | /* |
37 | * We don't need the return address, so set up the stack so | 40 | * We don't need the return address, so set up the stack so |
38 | * efi_main() can find its arugments. | 41 | * efi_main() can find its arugments. |
@@ -41,12 +44,17 @@ ENTRY(startup_32) | |||
41 | 44 | ||
42 | call efi_main | 45 | call efi_main |
43 | cmpl $0, %eax | 46 | cmpl $0, %eax |
44 | je preferred_addr | ||
45 | movl %eax, %esi | 47 | movl %eax, %esi |
46 | call 1f | 48 | jne 2f |
47 | 1: | 49 | 1: |
50 | /* EFI init failed, so hang. */ | ||
51 | hlt | ||
52 | jmp 1b | ||
53 | 2: | ||
54 | call 3f | ||
55 | 3: | ||
48 | popl %eax | 56 | popl %eax |
49 | subl $1b, %eax | 57 | subl $3b, %eax |
50 | subl BP_pref_address(%esi), %eax | 58 | subl BP_pref_address(%esi), %eax |
51 | add BP_code32_start(%esi), %eax | 59 | add BP_code32_start(%esi), %eax |
52 | leal preferred_addr(%eax), %eax | 60 | leal preferred_addr(%eax), %eax |
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S index 558d76ce23bc..87e03a13d8e3 100644 --- a/arch/x86/boot/compressed/head_64.S +++ b/arch/x86/boot/compressed/head_64.S | |||
@@ -200,18 +200,28 @@ ENTRY(startup_64) | |||
200 | * entire text+data+bss and hopefully all of memory. | 200 | * entire text+data+bss and hopefully all of memory. |
201 | */ | 201 | */ |
202 | #ifdef CONFIG_EFI_STUB | 202 | #ifdef CONFIG_EFI_STUB |
203 | pushq %rsi | 203 | /* |
204 | * The entry point for the PE/COFF executable is 0x210, so only | ||
205 | * legacy boot loaders will execute this jmp. | ||
206 | */ | ||
207 | jmp preferred_addr | ||
208 | |||
209 | .org 0x210 | ||
204 | mov %rcx, %rdi | 210 | mov %rcx, %rdi |
205 | mov %rdx, %rsi | 211 | mov %rdx, %rsi |
206 | call efi_main | 212 | call efi_main |
207 | popq %rsi | ||
208 | cmpq $0,%rax | ||
209 | je preferred_addr | ||
210 | movq %rax,%rsi | 213 | movq %rax,%rsi |
211 | call 1f | 214 | cmpq $0,%rax |
215 | jne 2f | ||
212 | 1: | 216 | 1: |
217 | /* EFI init failed, so hang. */ | ||
218 | hlt | ||
219 | jmp 1b | ||
220 | 2: | ||
221 | call 3f | ||
222 | 3: | ||
213 | popq %rax | 223 | popq %rax |
214 | subq $1b, %rax | 224 | subq $3b, %rax |
215 | subq BP_pref_address(%rsi), %rax | 225 | subq BP_pref_address(%rsi), %rax |
216 | add BP_code32_start(%esi), %eax | 226 | add BP_code32_start(%esi), %eax |
217 | leaq preferred_addr(%rax), %rax | 227 | leaq preferred_addr(%rax), %rax |
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c index ed549767a231..24443a332083 100644 --- a/arch/x86/boot/tools/build.c +++ b/arch/x86/boot/tools/build.c | |||
@@ -205,8 +205,13 @@ int main(int argc, char ** argv) | |||
205 | put_unaligned_le32(file_sz, &buf[pe_header + 0x50]); | 205 | put_unaligned_le32(file_sz, &buf[pe_header + 0x50]); |
206 | 206 | ||
207 | #ifdef CONFIG_X86_32 | 207 | #ifdef CONFIG_X86_32 |
208 | /* Address of entry point */ | 208 | /* |
209 | put_unaligned_le32(i, &buf[pe_header + 0x28]); | 209 | * Address of entry point. |
210 | * | ||
211 | * The EFI stub entry point is +16 bytes from the start of | ||
212 | * the .text section. | ||
213 | */ | ||
214 | put_unaligned_le32(i + 16, &buf[pe_header + 0x28]); | ||
210 | 215 | ||
211 | /* .text size */ | 216 | /* .text size */ |
212 | put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]); | 217 | put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]); |
@@ -217,9 +222,11 @@ int main(int argc, char ** argv) | |||
217 | /* | 222 | /* |
218 | * Address of entry point. startup_32 is at the beginning and | 223 | * Address of entry point. startup_32 is at the beginning and |
219 | * the 64-bit entry point (startup_64) is always 512 bytes | 224 | * the 64-bit entry point (startup_64) is always 512 bytes |
220 | * after. | 225 | * after. The EFI stub entry point is 16 bytes after that, as |
226 | * the first instruction allows legacy loaders to jump over | ||
227 | * the EFI stub initialisation | ||
221 | */ | 228 | */ |
222 | put_unaligned_le32(i + 512, &buf[pe_header + 0x28]); | 229 | put_unaligned_le32(i + 528, &buf[pe_header + 0x28]); |
223 | 230 | ||
224 | /* .text size */ | 231 | /* .text size */ |
225 | put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]); | 232 | put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]); |
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index 3427b7798dbc..7ef7c3020e5c 100644 --- a/arch/x86/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h | |||
@@ -7,9 +7,9 @@ | |||
7 | #else | 7 | #else |
8 | # ifdef __i386__ | 8 | # ifdef __i386__ |
9 | # include "posix_types_32.h" | 9 | # include "posix_types_32.h" |
10 | # elif defined(__LP64__) | 10 | # elif defined(__ILP32__) |
11 | # include "posix_types_64.h" | ||
12 | # else | ||
13 | # include "posix_types_x32.h" | 11 | # include "posix_types_x32.h" |
12 | # else | ||
13 | # include "posix_types_64.h" | ||
14 | # endif | 14 | # endif |
15 | #endif | 15 | #endif |
diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h index 4a085383af27..5ca71c065eef 100644 --- a/arch/x86/include/asm/sigcontext.h +++ b/arch/x86/include/asm/sigcontext.h | |||
@@ -257,7 +257,7 @@ struct sigcontext { | |||
257 | __u64 oldmask; | 257 | __u64 oldmask; |
258 | __u64 cr2; | 258 | __u64 cr2; |
259 | struct _fpstate __user *fpstate; /* zero when no FPU context */ | 259 | struct _fpstate __user *fpstate; /* zero when no FPU context */ |
260 | #ifndef __LP64__ | 260 | #ifdef __ILP32__ |
261 | __u32 __fpstate_pad; | 261 | __u32 __fpstate_pad; |
262 | #endif | 262 | #endif |
263 | __u64 reserved1[8]; | 263 | __u64 reserved1[8]; |
diff --git a/arch/x86/include/asm/siginfo.h b/arch/x86/include/asm/siginfo.h index fc1aa5535646..34c47b3341c0 100644 --- a/arch/x86/include/asm/siginfo.h +++ b/arch/x86/include/asm/siginfo.h | |||
@@ -2,7 +2,13 @@ | |||
2 | #define _ASM_X86_SIGINFO_H | 2 | #define _ASM_X86_SIGINFO_H |
3 | 3 | ||
4 | #ifdef __x86_64__ | 4 | #ifdef __x86_64__ |
5 | # define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) | 5 | # ifdef __ILP32__ /* x32 */ |
6 | typedef long long __kernel_si_clock_t __attribute__((aligned(4))); | ||
7 | # define __ARCH_SI_CLOCK_T __kernel_si_clock_t | ||
8 | # define __ARCH_SI_ATTRIBUTES __attribute__((aligned(8))) | ||
9 | # else /* x86-64 */ | ||
10 | # define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) | ||
11 | # endif | ||
6 | #endif | 12 | #endif |
7 | 13 | ||
8 | #include <asm-generic/siginfo.h> | 14 | #include <asm-generic/siginfo.h> |
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h index 37cdc9d99bb1..4437001d8e3d 100644 --- a/arch/x86/include/asm/unistd.h +++ b/arch/x86/include/asm/unistd.h | |||
@@ -63,10 +63,10 @@ | |||
63 | #else | 63 | #else |
64 | # ifdef __i386__ | 64 | # ifdef __i386__ |
65 | # include <asm/unistd_32.h> | 65 | # include <asm/unistd_32.h> |
66 | # elif defined(__LP64__) | 66 | # elif defined(__ILP32__) |
67 | # include <asm/unistd_64.h> | ||
68 | # else | ||
69 | # include <asm/unistd_x32.h> | 67 | # include <asm/unistd_x32.h> |
68 | # else | ||
69 | # include <asm/unistd_64.h> | ||
70 | # endif | 70 | # endif |
71 | #endif | 71 | #endif |
72 | 72 | ||
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index baaca8defec8..764b66a4cf89 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h | |||
@@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi; | |||
195 | 195 | ||
196 | extern void x86_init_noop(void); | 196 | extern void x86_init_noop(void); |
197 | extern void x86_init_uint_noop(unsigned int unused); | 197 | extern void x86_init_uint_noop(unsigned int unused); |
198 | extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node); | ||
199 | 198 | ||
200 | #endif | 199 | #endif |
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c index 103b6ab368d3..146a49c763a4 100644 --- a/arch/x86/kernel/acpi/sleep.c +++ b/arch/x86/kernel/acpi/sleep.c | |||
@@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags; | |||
24 | static char temp_stack[4096]; | 24 | static char temp_stack[4096]; |
25 | #endif | 25 | #endif |
26 | 26 | ||
27 | asmlinkage void acpi_enter_s3(void) | ||
28 | { | ||
29 | acpi_enter_sleep_state(3, wake_sleep_flags); | ||
30 | } | ||
27 | /** | 31 | /** |
28 | * acpi_suspend_lowlevel - save kernel state | 32 | * acpi_suspend_lowlevel - save kernel state |
29 | * | 33 | * |
diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h index 416d4be13fef..d68677a2a010 100644 --- a/arch/x86/kernel/acpi/sleep.h +++ b/arch/x86/kernel/acpi/sleep.h | |||
@@ -3,12 +3,16 @@ | |||
3 | */ | 3 | */ |
4 | 4 | ||
5 | #include <asm/trampoline.h> | 5 | #include <asm/trampoline.h> |
6 | #include <linux/linkage.h> | ||
6 | 7 | ||
7 | extern unsigned long saved_video_mode; | 8 | extern unsigned long saved_video_mode; |
8 | extern long saved_magic; | 9 | extern long saved_magic; |
9 | 10 | ||
10 | extern int wakeup_pmode_return; | 11 | extern int wakeup_pmode_return; |
11 | 12 | ||
13 | extern u8 wake_sleep_flags; | ||
14 | extern asmlinkage void acpi_enter_s3(void); | ||
15 | |||
12 | extern unsigned long acpi_copy_wakeup_routine(unsigned long); | 16 | extern unsigned long acpi_copy_wakeup_routine(unsigned long); |
13 | extern void wakeup_long64(void); | 17 | extern void wakeup_long64(void); |
14 | 18 | ||
diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S index 13ab720573e3..72610839f03b 100644 --- a/arch/x86/kernel/acpi/wakeup_32.S +++ b/arch/x86/kernel/acpi/wakeup_32.S | |||
@@ -74,9 +74,7 @@ restore_registers: | |||
74 | ENTRY(do_suspend_lowlevel) | 74 | ENTRY(do_suspend_lowlevel) |
75 | call save_processor_state | 75 | call save_processor_state |
76 | call save_registers | 76 | call save_registers |
77 | pushl $3 | 77 | call acpi_enter_s3 |
78 | call acpi_enter_sleep_state | ||
79 | addl $4, %esp | ||
80 | 78 | ||
81 | # In case of S3 failure, we'll emerge here. Jump | 79 | # In case of S3 failure, we'll emerge here. Jump |
82 | # to ret_point to recover | 80 | # to ret_point to recover |
diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S index 8ea5164cbd04..014d1d28c397 100644 --- a/arch/x86/kernel/acpi/wakeup_64.S +++ b/arch/x86/kernel/acpi/wakeup_64.S | |||
@@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel) | |||
71 | movq %rsi, saved_rsi | 71 | movq %rsi, saved_rsi |
72 | 72 | ||
73 | addq $8, %rsp | 73 | addq $8, %rsp |
74 | movl $3, %edi | 74 | call acpi_enter_s3 |
75 | xorl %eax, %eax | ||
76 | call acpi_enter_sleep_state | ||
77 | /* in case something went wrong, restore the machine status and go on */ | 75 | /* in case something went wrong, restore the machine status and go on */ |
78 | jmp resume_point | 76 | jmp resume_point |
79 | 77 | ||
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 11544d8f1e97..edc24480469f 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c | |||
@@ -1637,9 +1637,11 @@ static int __init apic_verify(void) | |||
1637 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | 1637 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; |
1638 | 1638 | ||
1639 | /* The BIOS may have set up the APIC at some other address */ | 1639 | /* The BIOS may have set up the APIC at some other address */ |
1640 | rdmsr(MSR_IA32_APICBASE, l, h); | 1640 | if (boot_cpu_data.x86 >= 6) { |
1641 | if (l & MSR_IA32_APICBASE_ENABLE) | 1641 | rdmsr(MSR_IA32_APICBASE, l, h); |
1642 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | 1642 | if (l & MSR_IA32_APICBASE_ENABLE) |
1643 | mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; | ||
1644 | } | ||
1643 | 1645 | ||
1644 | pr_info("Found and enabled local APIC!\n"); | 1646 | pr_info("Found and enabled local APIC!\n"); |
1645 | return 0; | 1647 | return 0; |
@@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr) | |||
1657 | * MSR. This can only be done in software for Intel P6 or later | 1659 | * MSR. This can only be done in software for Intel P6 or later |
1658 | * and AMD K7 (Model > 1) or later. | 1660 | * and AMD K7 (Model > 1) or later. |
1659 | */ | 1661 | */ |
1660 | rdmsr(MSR_IA32_APICBASE, l, h); | 1662 | if (boot_cpu_data.x86 >= 6) { |
1661 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { | 1663 | rdmsr(MSR_IA32_APICBASE, l, h); |
1662 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); | 1664 | if (!(l & MSR_IA32_APICBASE_ENABLE)) { |
1663 | l &= ~MSR_IA32_APICBASE_BASE; | 1665 | pr_info("Local APIC disabled by BIOS -- reenabling.\n"); |
1664 | l |= MSR_IA32_APICBASE_ENABLE | addr; | 1666 | l &= ~MSR_IA32_APICBASE_BASE; |
1665 | wrmsr(MSR_IA32_APICBASE, l, h); | 1667 | l |= MSR_IA32_APICBASE_ENABLE | addr; |
1666 | enabled_via_apicbase = 1; | 1668 | wrmsr(MSR_IA32_APICBASE, l, h); |
1669 | enabled_via_apicbase = 1; | ||
1670 | } | ||
1667 | } | 1671 | } |
1668 | return apic_verify(); | 1672 | return apic_verify(); |
1669 | } | 1673 | } |
@@ -2209,10 +2213,12 @@ static void lapic_resume(void) | |||
2209 | * FIXME! This will be wrong if we ever support suspend on | 2213 | * FIXME! This will be wrong if we ever support suspend on |
2210 | * SMP! We'll need to do this as part of the CPU restore! | 2214 | * SMP! We'll need to do this as part of the CPU restore! |
2211 | */ | 2215 | */ |
2212 | rdmsr(MSR_IA32_APICBASE, l, h); | 2216 | if (boot_cpu_data.x86 >= 6) { |
2213 | l &= ~MSR_IA32_APICBASE_BASE; | 2217 | rdmsr(MSR_IA32_APICBASE, l, h); |
2214 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; | 2218 | l &= ~MSR_IA32_APICBASE_BASE; |
2215 | wrmsr(MSR_IA32_APICBASE, l, h); | 2219 | l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; |
2220 | wrmsr(MSR_IA32_APICBASE, l, h); | ||
2221 | } | ||
2216 | } | 2222 | } |
2217 | 2223 | ||
2218 | maxlvt = lapic_get_maxlvt(); | 2224 | maxlvt = lapic_get_maxlvt(); |
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c index 899803e03214..23e75422e013 100644 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c | |||
@@ -207,8 +207,11 @@ static void __init map_csrs(void) | |||
207 | 207 | ||
208 | static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) | 208 | static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) |
209 | { | 209 | { |
210 | c->phys_proc_id = node; | 210 | |
211 | per_cpu(cpu_llc_id, smp_processor_id()) = node; | 211 | if (c->phys_proc_id != node) { |
212 | c->phys_proc_id = node; | ||
213 | per_cpu(cpu_llc_id, smp_processor_id()) = node; | ||
214 | } | ||
212 | } | 215 | } |
213 | 216 | ||
214 | static int __init numachip_system_init(void) | 217 | static int __init numachip_system_init(void) |
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 8a778db45e3a..991e315f4227 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c | |||
@@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | |||
24 | { | 24 | { |
25 | if (x2apic_phys) | 25 | if (x2apic_phys) |
26 | return x2apic_enabled(); | 26 | return x2apic_enabled(); |
27 | else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) && | ||
28 | (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) && | ||
29 | x2apic_enabled()) { | ||
30 | printk(KERN_DEBUG "System requires x2apic physical mode\n"); | ||
31 | return 1; | ||
32 | } | ||
27 | else | 33 | else |
28 | return 0; | 34 | return 0; |
29 | } | 35 | } |
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 0a44b90602b0..1c67ca100e4c 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c | |||
@@ -26,7 +26,8 @@ | |||
26 | * contact AMD for precise details and a CPU swap. | 26 | * contact AMD for precise details and a CPU swap. |
27 | * | 27 | * |
28 | * See http://www.multimania.com/poulot/k6bug.html | 28 | * See http://www.multimania.com/poulot/k6bug.html |
29 | * http://www.amd.com/K6/k6docs/revgd.html | 29 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" |
30 | * (Publication # 21266 Issue Date: August 1998) | ||
30 | * | 31 | * |
31 | * The following test is erm.. interesting. AMD neglected to up | 32 | * The following test is erm.. interesting. AMD neglected to up |
32 | * the chip setting when fixing the bug but they also tweaked some | 33 | * the chip setting when fixing the bug but they also tweaked some |
@@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) | |||
94 | "system stability may be impaired when more than 32 MB are used.\n"); | 95 | "system stability may be impaired when more than 32 MB are used.\n"); |
95 | else | 96 | else |
96 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); | 97 | printk(KERN_CONT "probably OK (after B9730xxxx).\n"); |
97 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); | ||
98 | } | 98 | } |
99 | 99 | ||
100 | /* K6 with old style WHCR */ | 100 | /* K6 with old style WHCR */ |
@@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c) | |||
353 | node = per_cpu(cpu_llc_id, cpu); | 353 | node = per_cpu(cpu_llc_id, cpu); |
354 | 354 | ||
355 | /* | 355 | /* |
356 | * If core numbers are inconsistent, it's likely a multi-fabric platform, | 356 | * On multi-fabric platform (e.g. Numascale NumaChip) a |
357 | * so invoke platform-specific handler | 357 | * platform-specific handler needs to be called to fixup some |
358 | * IDs of the CPU. | ||
358 | */ | 359 | */ |
359 | if (c->phys_proc_id != node) | 360 | if (x86_cpuinit.fixup_cpu_id) |
360 | x86_cpuinit.fixup_cpu_id(c, node); | 361 | x86_cpuinit.fixup_cpu_id(c, node); |
361 | 362 | ||
362 | if (!node_online(node)) { | 363 | if (!node_online(node)) { |
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 67e258362a3d..cf79302198a6 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c | |||
@@ -1163,15 +1163,6 @@ static void dbg_restore_debug_regs(void) | |||
1163 | #endif /* ! CONFIG_KGDB */ | 1163 | #endif /* ! CONFIG_KGDB */ |
1164 | 1164 | ||
1165 | /* | 1165 | /* |
1166 | * Prints an error where the NUMA and configured core-number mismatch and the | ||
1167 | * platform didn't override this to fix it up | ||
1168 | */ | ||
1169 | void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node) | ||
1170 | { | ||
1171 | pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id); | ||
1172 | } | ||
1173 | |||
1174 | /* | ||
1175 | * cpu_init() initializes state that is per-CPU. Some data is already | 1166 | * cpu_init() initializes state that is per-CPU. Some data is already |
1176 | * initialized (naturally) in the bootstrap process, such as the GDT | 1167 | * initialized (naturally) in the bootstrap process, such as the GDT |
1177 | * and IDT. We reload them nevertheless, this function acts as a | 1168 | * and IDT. We reload them nevertheless, this function acts as a |
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c index 73d08ed98a64..b8f3653dddbc 100644 --- a/arch/x86/kernel/cpu/intel_cacheinfo.c +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c | |||
@@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot, | |||
433 | /* check if @slot is already used or the index is already disabled */ | 433 | /* check if @slot is already used or the index is already disabled */ |
434 | ret = amd_get_l3_disable_slot(nb, slot); | 434 | ret = amd_get_l3_disable_slot(nb, slot); |
435 | if (ret >= 0) | 435 | if (ret >= 0) |
436 | return -EINVAL; | 436 | return -EEXIST; |
437 | 437 | ||
438 | if (index > nb->l3_cache.indices) | 438 | if (index > nb->l3_cache.indices) |
439 | return -EINVAL; | 439 | return -EINVAL; |
440 | 440 | ||
441 | /* check whether the other slot has disabled the same index already */ | 441 | /* check whether the other slot has disabled the same index already */ |
442 | if (index == amd_get_l3_disable_slot(nb, !slot)) | 442 | if (index == amd_get_l3_disable_slot(nb, !slot)) |
443 | return -EINVAL; | 443 | return -EEXIST; |
444 | 444 | ||
445 | amd_l3_disable_index(nb, cpu, slot, index); | 445 | amd_l3_disable_index(nb, cpu, slot, index); |
446 | 446 | ||
@@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf, | |||
468 | err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val); | 468 | err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val); |
469 | if (err) { | 469 | if (err) { |
470 | if (err == -EEXIST) | 470 | if (err == -EEXIST) |
471 | printk(KERN_WARNING "L3 disable slot %d in use!\n", | 471 | pr_warning("L3 slot %d in use/index already disabled!\n", |
472 | slot); | 472 | slot); |
473 | return err; | 473 | return err; |
474 | } | 474 | } |
475 | return count; | 475 | return count; |
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c index 7734bcbb5a3a..2d6e6498c176 100644 --- a/arch/x86/kernel/i387.c +++ b/arch/x86/kernel/i387.c | |||
@@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk) | |||
235 | if (tsk_used_math(tsk)) { | 235 | if (tsk_used_math(tsk)) { |
236 | if (HAVE_HWFP && tsk == current) | 236 | if (HAVE_HWFP && tsk == current) |
237 | unlazy_fpu(tsk); | 237 | unlazy_fpu(tsk); |
238 | tsk->thread.fpu.last_cpu = ~0; | ||
238 | return 0; | 239 | return 0; |
239 | } | 240 | } |
240 | 241 | ||
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c index 73465aab28f8..8a2ce8fd41c0 100644 --- a/arch/x86/kernel/microcode_amd.c +++ b/arch/x86/kernel/microcode_amd.c | |||
@@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) | |||
82 | { | 82 | { |
83 | struct cpuinfo_x86 *c = &cpu_data(cpu); | 83 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
84 | 84 | ||
85 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { | ||
86 | pr_warning("CPU%d: family %d not supported\n", cpu, c->x86); | ||
87 | return -1; | ||
88 | } | ||
89 | |||
90 | csig->rev = c->microcode; | 85 | csig->rev = c->microcode; |
91 | pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); | 86 | pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); |
92 | 87 | ||
@@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = { | |||
380 | 375 | ||
381 | struct microcode_ops * __init init_amd_microcode(void) | 376 | struct microcode_ops * __init init_amd_microcode(void) |
382 | { | 377 | { |
378 | struct cpuinfo_x86 *c = &cpu_data(0); | ||
379 | |||
380 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { | ||
381 | pr_warning("AMD CPU family 0x%x not supported\n", c->x86); | ||
382 | return NULL; | ||
383 | } | ||
384 | |||
383 | patch = (void *)get_zeroed_page(GFP_KERNEL); | 385 | patch = (void *)get_zeroed_page(GFP_KERNEL); |
384 | if (!patch) | 386 | if (!patch) |
385 | return NULL; | 387 | return NULL; |
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index 87a0f8688301..c9bda6d6035c 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c | |||
@@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif) | |||
419 | if (err) | 419 | if (err) |
420 | return err; | 420 | return err; |
421 | 421 | ||
422 | if (microcode_init_cpu(cpu) == UCODE_ERROR) { | 422 | if (microcode_init_cpu(cpu) == UCODE_ERROR) |
423 | sysfs_remove_group(&dev->kobj, &mc_attr_group); | ||
424 | return -EINVAL; | 423 | return -EINVAL; |
425 | } | ||
426 | 424 | ||
427 | return err; | 425 | return err; |
428 | } | 426 | } |
@@ -528,11 +526,11 @@ static int __init microcode_init(void) | |||
528 | microcode_ops = init_intel_microcode(); | 526 | microcode_ops = init_intel_microcode(); |
529 | else if (c->x86_vendor == X86_VENDOR_AMD) | 527 | else if (c->x86_vendor == X86_VENDOR_AMD) |
530 | microcode_ops = init_amd_microcode(); | 528 | microcode_ops = init_amd_microcode(); |
531 | 529 | else | |
532 | if (!microcode_ops) { | ||
533 | pr_err("no support for this CPU vendor\n"); | 530 | pr_err("no support for this CPU vendor\n"); |
531 | |||
532 | if (!microcode_ops) | ||
534 | return -ENODEV; | 533 | return -ENODEV; |
535 | } | ||
536 | 534 | ||
537 | microcode_pdev = platform_device_register_simple("microcode", -1, | 535 | microcode_pdev = platform_device_register_simple("microcode", -1, |
538 | NULL, 0); | 536 | NULL, 0); |
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index e9f265fd79ae..9cf71d0b2d37 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c | |||
@@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = { | |||
93 | struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = { | 93 | struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = { |
94 | .early_percpu_clock_init = x86_init_noop, | 94 | .early_percpu_clock_init = x86_init_noop, |
95 | .setup_percpu_clockev = setup_secondary_APIC_clock, | 95 | .setup_percpu_clockev = setup_secondary_APIC_clock, |
96 | .fixup_cpu_id = x86_default_fixup_cpu_id, | ||
97 | }; | 96 | }; |
98 | 97 | ||
99 | static void default_nmi_init(void) { }; | 98 | static void default_nmi_init(void) { }; |
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index e0a37233c0af..e31bcd8f2eee 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c | |||
@@ -805,7 +805,7 @@ void intel_scu_devices_create(void) | |||
805 | } else | 805 | } else |
806 | i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1); | 806 | i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1); |
807 | } | 807 | } |
808 | intel_scu_notifier_post(SCU_AVAILABLE, 0L); | 808 | intel_scu_notifier_post(SCU_AVAILABLE, NULL); |
809 | } | 809 | } |
810 | EXPORT_SYMBOL_GPL(intel_scu_devices_create); | 810 | EXPORT_SYMBOL_GPL(intel_scu_devices_create); |
811 | 811 | ||
@@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void) | |||
814 | { | 814 | { |
815 | int i; | 815 | int i; |
816 | 816 | ||
817 | intel_scu_notifier_post(SCU_DOWN, 0L); | 817 | intel_scu_notifier_post(SCU_DOWN, NULL); |
818 | 818 | ||
819 | for (i = 0; i < ipc_next_dev; i++) | 819 | for (i = 0; i < ipc_next_dev; i++) |
820 | platform_device_del(ipc_devs[i]); | 820 | platform_device_del(ipc_devs[i]); |
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 4f51bebac02c..a8f8844b8d32 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c | |||
@@ -261,7 +261,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx, | |||
261 | 261 | ||
262 | static bool __init xen_check_mwait(void) | 262 | static bool __init xen_check_mwait(void) |
263 | { | 263 | { |
264 | #ifdef CONFIG_ACPI | 264 | #if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \ |
265 | !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE) | ||
265 | struct xen_platform_op op = { | 266 | struct xen_platform_op op = { |
266 | .cmd = XENPF_set_processor_pminfo, | 267 | .cmd = XENPF_set_processor_pminfo, |
267 | .u.set_pminfo.id = -1, | 268 | .u.set_pminfo.id = -1, |
@@ -349,7 +350,6 @@ static void __init xen_init_cpuid_mask(void) | |||
349 | /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ | 350 | /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ |
350 | if ((cx & xsave_mask) != xsave_mask) | 351 | if ((cx & xsave_mask) != xsave_mask) |
351 | cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */ | 352 | cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */ |
352 | |||
353 | if (xen_check_mwait()) | 353 | if (xen_check_mwait()) |
354 | cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32)); | 354 | cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32)); |
355 | } | 355 | } |
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index 5fac6919b957..0503c0c493a9 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c | |||
@@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void) | |||
178 | static void __init xen_filter_cpu_maps(void) | 178 | static void __init xen_filter_cpu_maps(void) |
179 | { | 179 | { |
180 | int i, rc; | 180 | int i, rc; |
181 | unsigned int subtract = 0; | ||
181 | 182 | ||
182 | if (!xen_initial_domain()) | 183 | if (!xen_initial_domain()) |
183 | return; | 184 | return; |
@@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void) | |||
192 | } else { | 193 | } else { |
193 | set_cpu_possible(i, false); | 194 | set_cpu_possible(i, false); |
194 | set_cpu_present(i, false); | 195 | set_cpu_present(i, false); |
196 | subtract++; | ||
195 | } | 197 | } |
196 | } | 198 | } |
199 | #ifdef CONFIG_HOTPLUG_CPU | ||
200 | /* This is akin to using 'nr_cpus' on the Linux command line. | ||
201 | * Which is OK as when we use 'dom0_max_vcpus=X' we can only | ||
202 | * have up to X, while nr_cpu_ids is greater than X. This | ||
203 | * normally is not a problem, except when CPU hotplugging | ||
204 | * is involved and then there might be more than X CPUs | ||
205 | * in the guest - which will not work as there is no | ||
206 | * hypercall to expand the max number of VCPUs an already | ||
207 | * running guest has. So cap it up to X. */ | ||
208 | if (subtract) | ||
209 | nr_cpu_ids = nr_cpu_ids - subtract; | ||
210 | #endif | ||
211 | |||
197 | } | 212 | } |
198 | 213 | ||
199 | static void __init xen_smp_prepare_boot_cpu(void) | 214 | static void __init xen_smp_prepare_boot_cpu(void) |
diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S index 79d7362ad6d1..3e45aa000718 100644 --- a/arch/x86/xen/xen-asm.S +++ b/arch/x86/xen/xen-asm.S | |||
@@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct) | |||
96 | 96 | ||
97 | /* check for unmasked and pending */ | 97 | /* check for unmasked and pending */ |
98 | cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending | 98 | cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending |
99 | jz 1f | 99 | jnz 1f |
100 | 2: call check_events | 100 | 2: call check_events |
101 | 1: | 101 | 1: |
102 | ENDPATCH(xen_restore_fl_direct) | 102 | ENDPATCH(xen_restore_fl_direct) |