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-rw-r--r--arch/x86/platform/mrst/mrst.c1052
1 files changed, 0 insertions, 1052 deletions
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
deleted file mode 100644
index 3ca5957b7a34..000000000000
--- a/arch/x86/platform/mrst/mrst.c
+++ /dev/null
@@ -1,1052 +0,0 @@
1/*
2 * mrst.c: Intel Moorestown platform specific setup code
3 *
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#define pr_fmt(fmt) "mrst: " fmt
14
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/scatterlist.h>
19#include <linux/sfi.h>
20#include <linux/intel_pmic_gpio.h>
21#include <linux/spi/spi.h>
22#include <linux/i2c.h>
23#include <linux/platform_data/pca953x.h>
24#include <linux/gpio_keys.h>
25#include <linux/input.h>
26#include <linux/platform_device.h>
27#include <linux/irq.h>
28#include <linux/module.h>
29#include <linux/notifier.h>
30#include <linux/mfd/intel_msic.h>
31#include <linux/gpio.h>
32#include <linux/i2c/tc35876x.h>
33
34#include <asm/setup.h>
35#include <asm/mpspec_def.h>
36#include <asm/hw_irq.h>
37#include <asm/apic.h>
38#include <asm/io_apic.h>
39#include <asm/mrst.h>
40#include <asm/mrst-vrtc.h>
41#include <asm/io.h>
42#include <asm/i8259.h>
43#include <asm/intel_scu_ipc.h>
44#include <asm/apb_timer.h>
45#include <asm/reboot.h>
46
47/*
48 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
49 * cmdline option x86_mrst_timer can be used to override the configuration
50 * to prefer one or the other.
51 * at runtime, there are basically three timer configurations:
52 * 1. per cpu apbt clock only
53 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
54 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
55 *
56 * by default (without cmdline option), platform code first detects cpu type
57 * to see if we are on lincroft or penwell, then set up both lapic or apbt
58 * clocks accordingly.
59 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
60 * config #3 is supported but not recommended on medfield.
61 *
62 * rating and feature summary:
63 * lapic (with C3STOP) --------- 100
64 * apbt (always-on) ------------ 110
65 * lapic (always-on,ARAT) ------ 150
66 */
67
68enum mrst_timer_options mrst_timer_options;
69
70static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
71static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
72enum mrst_cpu_type __mrst_cpu_chip;
73EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
74
75int sfi_mtimer_num;
76
77struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
78EXPORT_SYMBOL_GPL(sfi_mrtc_array);
79int sfi_mrtc_num;
80
81static void mrst_power_off(void)
82{
83}
84
85static void mrst_reboot(void)
86{
87 intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
88}
89
90/* parse all the mtimer info to a static mtimer array */
91static int __init sfi_parse_mtmr(struct sfi_table_header *table)
92{
93 struct sfi_table_simple *sb;
94 struct sfi_timer_table_entry *pentry;
95 struct mpc_intsrc mp_irq;
96 int totallen;
97
98 sb = (struct sfi_table_simple *)table;
99 if (!sfi_mtimer_num) {
100 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
101 struct sfi_timer_table_entry);
102 pentry = (struct sfi_timer_table_entry *) sb->pentry;
103 totallen = sfi_mtimer_num * sizeof(*pentry);
104 memcpy(sfi_mtimer_array, pentry, totallen);
105 }
106
107 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
108 pentry = sfi_mtimer_array;
109 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
110 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
111 " irq = %d\n", totallen, (u32)pentry->phys_addr,
112 pentry->freq_hz, pentry->irq);
113 if (!pentry->irq)
114 continue;
115 mp_irq.type = MP_INTSRC;
116 mp_irq.irqtype = mp_INT;
117/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
118 mp_irq.irqflag = 5;
119 mp_irq.srcbus = MP_BUS_ISA;
120 mp_irq.srcbusirq = pentry->irq; /* IRQ */
121 mp_irq.dstapic = MP_APIC_ALL;
122 mp_irq.dstirq = pentry->irq;
123 mp_save_irq(&mp_irq);
124 }
125
126 return 0;
127}
128
129struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
130{
131 int i;
132 if (hint < sfi_mtimer_num) {
133 if (!sfi_mtimer_usage[hint]) {
134 pr_debug("hint taken for timer %d irq %d\n",\
135 hint, sfi_mtimer_array[hint].irq);
136 sfi_mtimer_usage[hint] = 1;
137 return &sfi_mtimer_array[hint];
138 }
139 }
140 /* take the first timer available */
141 for (i = 0; i < sfi_mtimer_num;) {
142 if (!sfi_mtimer_usage[i]) {
143 sfi_mtimer_usage[i] = 1;
144 return &sfi_mtimer_array[i];
145 }
146 i++;
147 }
148 return NULL;
149}
150
151void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
152{
153 int i;
154 for (i = 0; i < sfi_mtimer_num;) {
155 if (mtmr->irq == sfi_mtimer_array[i].irq) {
156 sfi_mtimer_usage[i] = 0;
157 return;
158 }
159 i++;
160 }
161}
162
163/* parse all the mrtc info to a global mrtc array */
164int __init sfi_parse_mrtc(struct sfi_table_header *table)
165{
166 struct sfi_table_simple *sb;
167 struct sfi_rtc_table_entry *pentry;
168 struct mpc_intsrc mp_irq;
169
170 int totallen;
171
172 sb = (struct sfi_table_simple *)table;
173 if (!sfi_mrtc_num) {
174 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
175 struct sfi_rtc_table_entry);
176 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
177 totallen = sfi_mrtc_num * sizeof(*pentry);
178 memcpy(sfi_mrtc_array, pentry, totallen);
179 }
180
181 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
182 pentry = sfi_mrtc_array;
183 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
184 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
185 totallen, (u32)pentry->phys_addr, pentry->irq);
186 mp_irq.type = MP_INTSRC;
187 mp_irq.irqtype = mp_INT;
188 mp_irq.irqflag = 0xf; /* level trigger and active low */
189 mp_irq.srcbus = MP_BUS_ISA;
190 mp_irq.srcbusirq = pentry->irq; /* IRQ */
191 mp_irq.dstapic = MP_APIC_ALL;
192 mp_irq.dstirq = pentry->irq;
193 mp_save_irq(&mp_irq);
194 }
195 return 0;
196}
197
198static unsigned long __init mrst_calibrate_tsc(void)
199{
200 unsigned long fast_calibrate;
201 u32 lo, hi, ratio, fsb;
202
203 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
204 pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
205 ratio = (hi >> 8) & 0x1f;
206 pr_debug("ratio is %d\n", ratio);
207 if (!ratio) {
208 pr_err("read a zero ratio, should be incorrect!\n");
209 pr_err("force tsc ratio to 16 ...\n");
210 ratio = 16;
211 }
212 rdmsr(MSR_FSB_FREQ, lo, hi);
213 if ((lo & 0x7) == 0x7)
214 fsb = PENWELL_FSB_FREQ_83SKU;
215 else
216 fsb = PENWELL_FSB_FREQ_100SKU;
217 fast_calibrate = ratio * fsb;
218 pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
219 lapic_timer_frequency = fsb * 1000 / HZ;
220 /* mark tsc clocksource as reliable */
221 set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
222
223 if (fast_calibrate)
224 return fast_calibrate;
225
226 return 0;
227}
228
229static void __init mrst_time_init(void)
230{
231 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
232 switch (mrst_timer_options) {
233 case MRST_TIMER_APBT_ONLY:
234 break;
235 case MRST_TIMER_LAPIC_APBT:
236 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
237 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
238 break;
239 default:
240 if (!boot_cpu_has(X86_FEATURE_ARAT))
241 break;
242 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
243 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
244 return;
245 }
246 /* we need at least one APB timer */
247 pre_init_apic_IRQ0();
248 apbt_time_init();
249}
250
251static void mrst_arch_setup(void)
252{
253 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
254 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
255 else {
256 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
257 boot_cpu_data.x86, boot_cpu_data.x86_model);
258 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
259 }
260}
261
262/* MID systems don't have i8042 controller */
263static int mrst_i8042_detect(void)
264{
265 return 0;
266}
267
268/*
269 * Moorestown does not have external NMI source nor port 0x61 to report
270 * NMI status. The possible NMI sources are from pmu as a result of NMI
271 * watchdog or lock debug. Reading io port 0x61 results in 0xff which
272 * misled NMI handler.
273 */
274static unsigned char mrst_get_nmi_reason(void)
275{
276 return 0;
277}
278
279/*
280 * Moorestown specific x86_init function overrides and early setup
281 * calls.
282 */
283void __init x86_mrst_early_setup(void)
284{
285 x86_init.resources.probe_roms = x86_init_noop;
286 x86_init.resources.reserve_resources = x86_init_noop;
287
288 x86_init.timers.timer_init = mrst_time_init;
289 x86_init.timers.setup_percpu_clockev = x86_init_noop;
290
291 x86_init.irqs.pre_vector_init = x86_init_noop;
292
293 x86_init.oem.arch_setup = mrst_arch_setup;
294
295 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
296
297 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
298 x86_platform.i8042_detect = mrst_i8042_detect;
299 x86_init.timers.wallclock_init = mrst_rtc_init;
300 x86_platform.get_nmi_reason = mrst_get_nmi_reason;
301
302 x86_init.pci.init = pci_mrst_init;
303 x86_init.pci.fixup_irqs = x86_init_noop;
304
305 legacy_pic = &null_legacy_pic;
306
307 /* Moorestown specific power_off/restart method */
308 pm_power_off = mrst_power_off;
309 machine_ops.emergency_restart = mrst_reboot;
310
311 /* Avoid searching for BIOS MP tables */
312 x86_init.mpparse.find_smp_config = x86_init_noop;
313 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
314 set_bit(MP_BUS_ISA, mp_bus_not_pci);
315}
316
317/*
318 * if user does not want to use per CPU apb timer, just give it a lower rating
319 * than local apic timer and skip the late per cpu timer init.
320 */
321static inline int __init setup_x86_mrst_timer(char *arg)
322{
323 if (!arg)
324 return -EINVAL;
325
326 if (strcmp("apbt_only", arg) == 0)
327 mrst_timer_options = MRST_TIMER_APBT_ONLY;
328 else if (strcmp("lapic_and_apbt", arg) == 0)
329 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
330 else {
331 pr_warning("X86 MRST timer option %s not recognised"
332 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
333 arg);
334 return -EINVAL;
335 }
336 return 0;
337}
338__setup("x86_mrst_timer=", setup_x86_mrst_timer);
339
340/*
341 * Parsing GPIO table first, since the DEVS table will need this table
342 * to map the pin name to the actual pin.
343 */
344static struct sfi_gpio_table_entry *gpio_table;
345static int gpio_num_entry;
346
347static int __init sfi_parse_gpio(struct sfi_table_header *table)
348{
349 struct sfi_table_simple *sb;
350 struct sfi_gpio_table_entry *pentry;
351 int num, i;
352
353 if (gpio_table)
354 return 0;
355 sb = (struct sfi_table_simple *)table;
356 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
357 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
358
359 gpio_table = kmalloc(num * sizeof(*pentry), GFP_KERNEL);
360 if (!gpio_table)
361 return -1;
362 memcpy(gpio_table, pentry, num * sizeof(*pentry));
363 gpio_num_entry = num;
364
365 pr_debug("GPIO pin info:\n");
366 for (i = 0; i < num; i++, pentry++)
367 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
368 " pin = %d\n", i,
369 pentry->controller_name,
370 pentry->pin_name,
371 pentry->pin_no);
372 return 0;
373}
374
375static int get_gpio_by_name(const char *name)
376{
377 struct sfi_gpio_table_entry *pentry = gpio_table;
378 int i;
379
380 if (!pentry)
381 return -1;
382 for (i = 0; i < gpio_num_entry; i++, pentry++) {
383 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
384 return pentry->pin_no;
385 }
386 return -1;
387}
388
389/*
390 * Here defines the array of devices platform data that IAFW would export
391 * through SFI "DEVS" table, we use name and type to match the device and
392 * its platform data.
393 */
394struct devs_id {
395 char name[SFI_NAME_LEN + 1];
396 u8 type;
397 u8 delay;
398 void *(*get_platform_data)(void *info);
399};
400
401/* the offset for the mapping of global gpio pin to irq */
402#define MRST_IRQ_OFFSET 0x100
403
404static void __init *pmic_gpio_platform_data(void *info)
405{
406 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
407 int gpio_base = get_gpio_by_name("pmic_gpio_base");
408
409 if (gpio_base == -1)
410 gpio_base = 64;
411 pmic_gpio_pdata.gpio_base = gpio_base;
412 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
413 pmic_gpio_pdata.gpiointr = 0xffffeff8;
414
415 return &pmic_gpio_pdata;
416}
417
418static void __init *max3111_platform_data(void *info)
419{
420 struct spi_board_info *spi_info = info;
421 int intr = get_gpio_by_name("max3111_int");
422
423 spi_info->mode = SPI_MODE_0;
424 if (intr == -1)
425 return NULL;
426 spi_info->irq = intr + MRST_IRQ_OFFSET;
427 return NULL;
428}
429
430/* we have multiple max7315 on the board ... */
431#define MAX7315_NUM 2
432static void __init *max7315_platform_data(void *info)
433{
434 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
435 static int nr;
436 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
437 struct i2c_board_info *i2c_info = info;
438 int gpio_base, intr;
439 char base_pin_name[SFI_NAME_LEN + 1];
440 char intr_pin_name[SFI_NAME_LEN + 1];
441
442 if (nr == MAX7315_NUM) {
443 pr_err("too many max7315s, we only support %d\n",
444 MAX7315_NUM);
445 return NULL;
446 }
447 /* we have several max7315 on the board, we only need load several
448 * instances of the same pca953x driver to cover them
449 */
450 strcpy(i2c_info->type, "max7315");
451 if (nr++) {
452 sprintf(base_pin_name, "max7315_%d_base", nr);
453 sprintf(intr_pin_name, "max7315_%d_int", nr);
454 } else {
455 strcpy(base_pin_name, "max7315_base");
456 strcpy(intr_pin_name, "max7315_int");
457 }
458
459 gpio_base = get_gpio_by_name(base_pin_name);
460 intr = get_gpio_by_name(intr_pin_name);
461
462 if (gpio_base == -1)
463 return NULL;
464 max7315->gpio_base = gpio_base;
465 if (intr != -1) {
466 i2c_info->irq = intr + MRST_IRQ_OFFSET;
467 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
468 } else {
469 i2c_info->irq = -1;
470 max7315->irq_base = -1;
471 }
472 return max7315;
473}
474
475static void *tca6416_platform_data(void *info)
476{
477 static struct pca953x_platform_data tca6416;
478 struct i2c_board_info *i2c_info = info;
479 int gpio_base, intr;
480 char base_pin_name[SFI_NAME_LEN + 1];
481 char intr_pin_name[SFI_NAME_LEN + 1];
482
483 strcpy(i2c_info->type, "tca6416");
484 strcpy(base_pin_name, "tca6416_base");
485 strcpy(intr_pin_name, "tca6416_int");
486
487 gpio_base = get_gpio_by_name(base_pin_name);
488 intr = get_gpio_by_name(intr_pin_name);
489
490 if (gpio_base == -1)
491 return NULL;
492 tca6416.gpio_base = gpio_base;
493 if (intr != -1) {
494 i2c_info->irq = intr + MRST_IRQ_OFFSET;
495 tca6416.irq_base = gpio_base + MRST_IRQ_OFFSET;
496 } else {
497 i2c_info->irq = -1;
498 tca6416.irq_base = -1;
499 }
500 return &tca6416;
501}
502
503static void *mpu3050_platform_data(void *info)
504{
505 struct i2c_board_info *i2c_info = info;
506 int intr = get_gpio_by_name("mpu3050_int");
507
508 if (intr == -1)
509 return NULL;
510
511 i2c_info->irq = intr + MRST_IRQ_OFFSET;
512 return NULL;
513}
514
515static void __init *emc1403_platform_data(void *info)
516{
517 static short intr2nd_pdata;
518 struct i2c_board_info *i2c_info = info;
519 int intr = get_gpio_by_name("thermal_int");
520 int intr2nd = get_gpio_by_name("thermal_alert");
521
522 if (intr == -1 || intr2nd == -1)
523 return NULL;
524
525 i2c_info->irq = intr + MRST_IRQ_OFFSET;
526 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
527
528 return &intr2nd_pdata;
529}
530
531static void __init *lis331dl_platform_data(void *info)
532{
533 static short intr2nd_pdata;
534 struct i2c_board_info *i2c_info = info;
535 int intr = get_gpio_by_name("accel_int");
536 int intr2nd = get_gpio_by_name("accel_2");
537
538 if (intr == -1 || intr2nd == -1)
539 return NULL;
540
541 i2c_info->irq = intr + MRST_IRQ_OFFSET;
542 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
543
544 return &intr2nd_pdata;
545}
546
547static void __init *no_platform_data(void *info)
548{
549 return NULL;
550}
551
552static struct resource msic_resources[] = {
553 {
554 .start = INTEL_MSIC_IRQ_PHYS_BASE,
555 .end = INTEL_MSIC_IRQ_PHYS_BASE + 64 - 1,
556 .flags = IORESOURCE_MEM,
557 },
558};
559
560static struct intel_msic_platform_data msic_pdata;
561
562static struct platform_device msic_device = {
563 .name = "intel_msic",
564 .id = -1,
565 .dev = {
566 .platform_data = &msic_pdata,
567 },
568 .num_resources = ARRAY_SIZE(msic_resources),
569 .resource = msic_resources,
570};
571
572static inline bool mrst_has_msic(void)
573{
574 return mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL;
575}
576
577static int msic_scu_status_change(struct notifier_block *nb,
578 unsigned long code, void *data)
579{
580 if (code == SCU_DOWN) {
581 platform_device_unregister(&msic_device);
582 return 0;
583 }
584
585 return platform_device_register(&msic_device);
586}
587
588static int __init msic_init(void)
589{
590 static struct notifier_block msic_scu_notifier = {
591 .notifier_call = msic_scu_status_change,
592 };
593
594 /*
595 * We need to be sure that the SCU IPC is ready before MSIC device
596 * can be registered.
597 */
598 if (mrst_has_msic())
599 intel_scu_notifier_add(&msic_scu_notifier);
600
601 return 0;
602}
603arch_initcall(msic_init);
604
605/*
606 * msic_generic_platform_data - sets generic platform data for the block
607 * @info: pointer to the SFI device table entry for this block
608 * @block: MSIC block
609 *
610 * Function sets IRQ number from the SFI table entry for given device to
611 * the MSIC platform data.
612 */
613static void *msic_generic_platform_data(void *info, enum intel_msic_block block)
614{
615 struct sfi_device_table_entry *entry = info;
616
617 BUG_ON(block < 0 || block >= INTEL_MSIC_BLOCK_LAST);
618 msic_pdata.irq[block] = entry->irq;
619
620 return no_platform_data(info);
621}
622
623static void *msic_battery_platform_data(void *info)
624{
625 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_BATTERY);
626}
627
628static void *msic_gpio_platform_data(void *info)
629{
630 static struct intel_msic_gpio_pdata pdata;
631 int gpio = get_gpio_by_name("msic_gpio_base");
632
633 if (gpio < 0)
634 return NULL;
635
636 pdata.gpio_base = gpio;
637 msic_pdata.gpio = &pdata;
638
639 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_GPIO);
640}
641
642static void *msic_audio_platform_data(void *info)
643{
644 struct platform_device *pdev;
645
646 pdev = platform_device_register_simple("sst-platform", -1, NULL, 0);
647 if (IS_ERR(pdev)) {
648 pr_err("failed to create audio platform device\n");
649 return NULL;
650 }
651
652 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_AUDIO);
653}
654
655static void *msic_power_btn_platform_data(void *info)
656{
657 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_POWER_BTN);
658}
659
660static void *msic_ocd_platform_data(void *info)
661{
662 static struct intel_msic_ocd_pdata pdata;
663 int gpio = get_gpio_by_name("ocd_gpio");
664
665 if (gpio < 0)
666 return NULL;
667
668 pdata.gpio = gpio;
669 msic_pdata.ocd = &pdata;
670
671 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_OCD);
672}
673
674static void *msic_thermal_platform_data(void *info)
675{
676 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_THERMAL);
677}
678
679/* tc35876x DSI-LVDS bridge chip and panel platform data */
680static void *tc35876x_platform_data(void *data)
681{
682 static struct tc35876x_platform_data pdata;
683
684 /* gpio pins set to -1 will not be used by the driver */
685 pdata.gpio_bridge_reset = get_gpio_by_name("LCMB_RXEN");
686 pdata.gpio_panel_bl_en = get_gpio_by_name("6S6P_BL_EN");
687 pdata.gpio_panel_vadd = get_gpio_by_name("EN_VREG_LCD_V3P3");
688
689 return &pdata;
690}
691
692static const struct devs_id __initconst device_ids[] = {
693 {"bma023", SFI_DEV_TYPE_I2C, 1, &no_platform_data},
694 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
695 {"pmic_gpio", SFI_DEV_TYPE_IPC, 1, &pmic_gpio_platform_data},
696 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
697 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
698 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
699 {"tca6416", SFI_DEV_TYPE_I2C, 1, &tca6416_platform_data},
700 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
701 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
702 {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
703 {"mpu3050", SFI_DEV_TYPE_I2C, 1, &mpu3050_platform_data},
704 {"i2c_disp_brig", SFI_DEV_TYPE_I2C, 0, &tc35876x_platform_data},
705
706 /* MSIC subdevices */
707 {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data},
708 {"msic_gpio", SFI_DEV_TYPE_IPC, 1, &msic_gpio_platform_data},
709 {"msic_audio", SFI_DEV_TYPE_IPC, 1, &msic_audio_platform_data},
710 {"msic_power_btn", SFI_DEV_TYPE_IPC, 1, &msic_power_btn_platform_data},
711 {"msic_ocd", SFI_DEV_TYPE_IPC, 1, &msic_ocd_platform_data},
712 {"msic_thermal", SFI_DEV_TYPE_IPC, 1, &msic_thermal_platform_data},
713
714 {},
715};
716
717#define MAX_IPCDEVS 24
718static struct platform_device *ipc_devs[MAX_IPCDEVS];
719static int ipc_next_dev;
720
721#define MAX_SCU_SPI 24
722static struct spi_board_info *spi_devs[MAX_SCU_SPI];
723static int spi_next_dev;
724
725#define MAX_SCU_I2C 24
726static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
727static int i2c_bus[MAX_SCU_I2C];
728static int i2c_next_dev;
729
730static void __init intel_scu_device_register(struct platform_device *pdev)
731{
732 if(ipc_next_dev == MAX_IPCDEVS)
733 pr_err("too many SCU IPC devices");
734 else
735 ipc_devs[ipc_next_dev++] = pdev;
736}
737
738static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
739{
740 struct spi_board_info *new_dev;
741
742 if (spi_next_dev == MAX_SCU_SPI) {
743 pr_err("too many SCU SPI devices");
744 return;
745 }
746
747 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
748 if (!new_dev) {
749 pr_err("failed to alloc mem for delayed spi dev %s\n",
750 sdev->modalias);
751 return;
752 }
753 memcpy(new_dev, sdev, sizeof(*sdev));
754
755 spi_devs[spi_next_dev++] = new_dev;
756}
757
758static void __init intel_scu_i2c_device_register(int bus,
759 struct i2c_board_info *idev)
760{
761 struct i2c_board_info *new_dev;
762
763 if (i2c_next_dev == MAX_SCU_I2C) {
764 pr_err("too many SCU I2C devices");
765 return;
766 }
767
768 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
769 if (!new_dev) {
770 pr_err("failed to alloc mem for delayed i2c dev %s\n",
771 idev->type);
772 return;
773 }
774 memcpy(new_dev, idev, sizeof(*idev));
775
776 i2c_bus[i2c_next_dev] = bus;
777 i2c_devs[i2c_next_dev++] = new_dev;
778}
779
780BLOCKING_NOTIFIER_HEAD(intel_scu_notifier);
781EXPORT_SYMBOL_GPL(intel_scu_notifier);
782
783/* Called by IPC driver */
784void intel_scu_devices_create(void)
785{
786 int i;
787
788 for (i = 0; i < ipc_next_dev; i++)
789 platform_device_add(ipc_devs[i]);
790
791 for (i = 0; i < spi_next_dev; i++)
792 spi_register_board_info(spi_devs[i], 1);
793
794 for (i = 0; i < i2c_next_dev; i++) {
795 struct i2c_adapter *adapter;
796 struct i2c_client *client;
797
798 adapter = i2c_get_adapter(i2c_bus[i]);
799 if (adapter) {
800 client = i2c_new_device(adapter, i2c_devs[i]);
801 if (!client)
802 pr_err("can't create i2c device %s\n",
803 i2c_devs[i]->type);
804 } else
805 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
806 }
807 intel_scu_notifier_post(SCU_AVAILABLE, NULL);
808}
809EXPORT_SYMBOL_GPL(intel_scu_devices_create);
810
811/* Called by IPC driver */
812void intel_scu_devices_destroy(void)
813{
814 int i;
815
816 intel_scu_notifier_post(SCU_DOWN, NULL);
817
818 for (i = 0; i < ipc_next_dev; i++)
819 platform_device_del(ipc_devs[i]);
820}
821EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
822
823static void __init install_irq_resource(struct platform_device *pdev, int irq)
824{
825 /* Single threaded */
826 static struct resource __initdata res = {
827 .name = "IRQ",
828 .flags = IORESOURCE_IRQ,
829 };
830 res.start = irq;
831 platform_device_add_resources(pdev, &res, 1);
832}
833
834static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *entry)
835{
836 const struct devs_id *dev = device_ids;
837 struct platform_device *pdev;
838 void *pdata = NULL;
839
840 while (dev->name[0]) {
841 if (dev->type == SFI_DEV_TYPE_IPC &&
842 !strncmp(dev->name, entry->name, SFI_NAME_LEN)) {
843 pdata = dev->get_platform_data(entry);
844 break;
845 }
846 dev++;
847 }
848
849 /*
850 * On Medfield the platform device creation is handled by the MSIC
851 * MFD driver so we don't need to do it here.
852 */
853 if (mrst_has_msic())
854 return;
855
856 pdev = platform_device_alloc(entry->name, 0);
857 if (pdev == NULL) {
858 pr_err("out of memory for SFI platform device '%s'.\n",
859 entry->name);
860 return;
861 }
862 install_irq_resource(pdev, entry->irq);
863
864 pdev->dev.platform_data = pdata;
865 intel_scu_device_register(pdev);
866}
867
868static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
869{
870 const struct devs_id *dev = device_ids;
871 void *pdata = NULL;
872
873 while (dev->name[0]) {
874 if (dev->type == SFI_DEV_TYPE_SPI &&
875 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
876 pdata = dev->get_platform_data(spi_info);
877 break;
878 }
879 dev++;
880 }
881 spi_info->platform_data = pdata;
882 if (dev->delay)
883 intel_scu_spi_device_register(spi_info);
884 else
885 spi_register_board_info(spi_info, 1);
886}
887
888static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
889{
890 const struct devs_id *dev = device_ids;
891 void *pdata = NULL;
892
893 while (dev->name[0]) {
894 if (dev->type == SFI_DEV_TYPE_I2C &&
895 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
896 pdata = dev->get_platform_data(i2c_info);
897 break;
898 }
899 dev++;
900 }
901 i2c_info->platform_data = pdata;
902
903 if (dev->delay)
904 intel_scu_i2c_device_register(bus, i2c_info);
905 else
906 i2c_register_board_info(bus, i2c_info, 1);
907 }
908
909
910static int __init sfi_parse_devs(struct sfi_table_header *table)
911{
912 struct sfi_table_simple *sb;
913 struct sfi_device_table_entry *pentry;
914 struct spi_board_info spi_info;
915 struct i2c_board_info i2c_info;
916 int num, i, bus;
917 int ioapic;
918 struct io_apic_irq_attr irq_attr;
919
920 sb = (struct sfi_table_simple *)table;
921 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
922 pentry = (struct sfi_device_table_entry *)sb->pentry;
923
924 for (i = 0; i < num; i++, pentry++) {
925 int irq = pentry->irq;
926
927 if (irq != (u8)0xff) { /* native RTE case */
928 /* these SPI2 devices are not exposed to system as PCI
929 * devices, but they have separate RTE entry in IOAPIC
930 * so we have to enable them one by one here
931 */
932 ioapic = mp_find_ioapic(irq);
933 irq_attr.ioapic = ioapic;
934 irq_attr.ioapic_pin = irq;
935 irq_attr.trigger = 1;
936 irq_attr.polarity = 1;
937 io_apic_set_pci_routing(NULL, irq, &irq_attr);
938 } else
939 irq = 0; /* No irq */
940
941 switch (pentry->type) {
942 case SFI_DEV_TYPE_IPC:
943 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
944 "irq = 0x%2x\n", i, pentry->name, pentry->irq);
945 sfi_handle_ipc_dev(pentry);
946 break;
947 case SFI_DEV_TYPE_SPI:
948 memset(&spi_info, 0, sizeof(spi_info));
949 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
950 spi_info.irq = irq;
951 spi_info.bus_num = pentry->host_num;
952 spi_info.chip_select = pentry->addr;
953 spi_info.max_speed_hz = pentry->max_freq;
954 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
955 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
956 spi_info.bus_num,
957 spi_info.modalias,
958 spi_info.irq,
959 spi_info.max_speed_hz,
960 spi_info.chip_select);
961 sfi_handle_spi_dev(&spi_info);
962 break;
963 case SFI_DEV_TYPE_I2C:
964 memset(&i2c_info, 0, sizeof(i2c_info));
965 bus = pentry->host_num;
966 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
967 i2c_info.irq = irq;
968 i2c_info.addr = pentry->addr;
969 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
970 "irq = 0x%2x, addr = 0x%x\n", i, bus,
971 i2c_info.type,
972 i2c_info.irq,
973 i2c_info.addr);
974 sfi_handle_i2c_dev(bus, &i2c_info);
975 break;
976 case SFI_DEV_TYPE_UART:
977 case SFI_DEV_TYPE_HSI:
978 default:
979 ;
980 }
981 }
982 return 0;
983}
984
985static int __init mrst_platform_init(void)
986{
987 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
988 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
989 return 0;
990}
991arch_initcall(mrst_platform_init);
992
993/*
994 * we will search these buttons in SFI GPIO table (by name)
995 * and register them dynamically. Please add all possible
996 * buttons here, we will shrink them if no GPIO found.
997 */
998static struct gpio_keys_button gpio_button[] = {
999 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
1000 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
1001 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
1002 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
1003 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
1004 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
1005 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
1006 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
1007 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
1008 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
1009};
1010
1011static struct gpio_keys_platform_data mrst_gpio_keys = {
1012 .buttons = gpio_button,
1013 .rep = 1,
1014 .nbuttons = -1, /* will fill it after search */
1015};
1016
1017static struct platform_device pb_device = {
1018 .name = "gpio-keys",
1019 .id = -1,
1020 .dev = {
1021 .platform_data = &mrst_gpio_keys,
1022 },
1023};
1024
1025/*
1026 * Shrink the non-existent buttons, register the gpio button
1027 * device if there is some
1028 */
1029static int __init pb_keys_init(void)
1030{
1031 struct gpio_keys_button *gb = gpio_button;
1032 int i, num, good = 0;
1033
1034 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
1035 for (i = 0; i < num; i++) {
1036 gb[i].gpio = get_gpio_by_name(gb[i].desc);
1037 pr_debug("info[%2d]: name = %s, gpio = %d\n", i, gb[i].desc, gb[i].gpio);
1038 if (gb[i].gpio == -1)
1039 continue;
1040
1041 if (i != good)
1042 gb[good] = gb[i];
1043 good++;
1044 }
1045
1046 if (good) {
1047 mrst_gpio_keys.nbuttons = good;
1048 return platform_device_register(&pb_device);
1049 }
1050 return 0;
1051}
1052late_initcall(pb_keys_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 11:31:40 -0500