1 files changed, 36 insertions, 3 deletions

diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 527d6d50643d..40955841bb32 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -60,14 +60,27 @@
 
 enum intel_mid_timer_options intel_mid_timer_options;
 
+/* intel_mid_ops to store sub arch ops */
+struct intel_mid_ops *intel_mid_ops;
+/* getter function for sub arch ops*/
+static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT;
 enum intel_mid_cpu_type __intel_mid_cpu_chip;
 EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
 
+static void intel_mid_power_off(void)
+{
+};
+
 static void intel_mid_reboot(void)
 {
         intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
 }
 
+static unsigned long __init intel_mid_calibrate_tsc(void)
+{
+        return 0;
+}
+
 static void __init intel_mid_time_init(void)
 {
         sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
@@ -92,13 +105,33 @@ static void __init intel_mid_time_init(void)
 
 static void intel_mid_arch_setup(void)
 {
-        if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
-                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
-        else {
+        if (boot_cpu_data.x86 != 6) {
                 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n",
                         boot_cpu_data.x86, boot_cpu_data.x86_model);
                 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
+                goto out;
+        }
+
+        switch (boot_cpu_data.x86_model) {
+        case 0x35:
+                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
+                break;
+        case 0x27:
+        default:
+                __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
+                break;
         }
+
+        if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops))
+                intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
+        else {
+                intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
+                pr_info("ARCH: Uknown SoC, assuming PENWELL!\n");
+        }
+
+out:
+        if (intel_mid_ops->arch_setup)
+                intel_mid_ops->arch_setup();
 }
 
 /* MID systems don't have i8042 controller */