5 files changed, 176 insertions, 25 deletions

diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index dbf532369711..6a0fca78c362 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -1,6 +1,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/topology.h>
+#include <linux/cpu.h>
 #include "pci.h"
 
 #ifdef CONFIG_X86_64
@@ -555,15 +556,17 @@ static int __init early_fill_mp_bus_info(void)
         return 0;
 }
 
-postcore_initcall(early_fill_mp_bus_info);
+#else  /* !CONFIG_X86_64 */
 
-#endif
+static int __init early_fill_mp_bus_info(void) { return 0; }
+
+#endif /* !CONFIG_X86_64 */
 
 /* common 32/64 bit code */
 
 #define ENABLE_CF8_EXT_CFG      (1ULL << 46)
 
-static void enable_pci_io_ecs_per_cpu(void *unused)
+static void enable_pci_io_ecs(void *unused)
 {
         u64 reg;
         rdmsrl(MSR_AMD64_NB_CFG, reg);
@@ -573,14 +576,51 @@ static void enable_pci_io_ecs_per_cpu(void *unused)
         }
 }
 
-static int __init enable_pci_io_ecs(void)
+static int __cpuinit amd_cpu_notify(struct notifier_block *self,
+                                    unsigned long action, void *hcpu)
 {
+        int cpu = (long)hcpu;
+        switch(action) {
+        case CPU_ONLINE:
+        case CPU_ONLINE_FROZEN:
+                smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
+                break;
+        default:
+                break;
+        }
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata amd_cpu_notifier = {
+        .notifier_call  = amd_cpu_notify,
+};
+
+static int __init pci_io_ecs_init(void)
+{
+        int cpu;
+
         /* assume all cpus from fam10h have IO ECS */
         if (boot_cpu_data.x86 < 0x10)
                 return 0;
-        on_each_cpu(enable_pci_io_ecs_per_cpu, NULL, 1);
+
+        register_cpu_notifier(&amd_cpu_notifier);
+        for_each_online_cpu(cpu)
+                amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
+                               (void *)(long)cpu);
         pci_probe |= PCI_HAS_IO_ECS;
+
+        return 0;
+}
+
+static int __init amd_postcore_init(void)
+{
+        if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
+                return 0;
+
+        early_fill_mp_bus_info();
+        pci_io_ecs_init();
+
         return 0;
 }
 
-postcore_initcall(enable_pci_io_ecs);
+postcore_initcall(amd_postcore_init);
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 5807d1bc73f7..d765da913842 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -31,8 +31,11 @@
 #include <linux/ioport.h>
 #include <linux/errno.h>
 #include <linux/bootmem.h>
+#include <linux/acpi.h>
 
 #include <asm/pat.h>
+#include <asm/hpet.h>
+#include <asm/io_apic.h>
 
 #include "pci.h"
 
@@ -77,6 +80,77 @@ pcibios_align_resource(void *data, struct resource *res,
 }
 EXPORT_SYMBOL(pcibios_align_resource);
 
+static int check_res_with_valid(struct pci_dev *dev, struct resource *res)
+{
+        unsigned long base;
+        unsigned long size;
+        int i;
+
+        base = res->start;
+        size = (res->start == 0 && res->end == res->start) ? 0 :
+                 (res->end - res->start + 1);
+
+        if (!base || !size)
+                return 0;
+
+#ifdef CONFIG_HPET_TIMER
+        /* for hpet */
+        if (base == hpet_address && (res->flags & IORESOURCE_MEM)) {
+                dev_info(&dev->dev, "BAR has HPET at %08lx-%08lx\n",
+                                 base, base + size - 1);
+                return 1;
+        }
+#endif
+
+#ifdef CONFIG_X86_IO_APIC
+        for (i = 0; i < nr_ioapics; i++) {
+                unsigned long ioapic_phys = mp_ioapics[i].mp_apicaddr;
+
+                if (base == ioapic_phys && (res->flags & IORESOURCE_MEM)) {
+                        dev_info(&dev->dev, "BAR has ioapic at %08lx-%08lx\n",
+                                         base, base + size - 1);
+                        return 1;
+                }
+        }
+#endif
+
+#ifdef CONFIG_PCI_MMCONFIG
+        for (i = 0; i < pci_mmcfg_config_num; i++) {
+                unsigned long addr;
+
+                addr = pci_mmcfg_config[i].address;
+                if (base == addr && (res->flags & IORESOURCE_MEM)) {
+                        dev_info(&dev->dev, "BAR has MMCONFIG at %08lx-%08lx\n",
+                                         base, base + size - 1);
+                        return 1;
+                }
+        }
+#endif
+
+        return 0;
+}
+
+static int check_platform(struct pci_dev *dev, struct resource *res)
+{
+        struct resource *root = NULL;
+
+        /*
+         * forcibly insert it into the
+         * resource tree
+         */
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+        else if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+
+        if (root && check_res_with_valid(dev, res)) {
+                insert_resource(root, res);
+
+                return 1;
+        }
+
+        return 0;
+}
 /*
  *  Handle resources of PCI devices.  If the world were perfect, we could
  *  just allocate all the resource regions and do nothing more.  It isn't.
@@ -128,6 +202,8 @@ static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
                                 pr = pci_find_parent_resource(dev, r);
                                 if (!r->start || !pr ||
                                     request_resource(pr, r) < 0) {
+                                        if (check_platform(dev, r))
+                                                continue;
                                         dev_err(&dev->dev, "BAR %d: can't "
                                                 "allocate resource\n", idx);
                                         /*
@@ -171,6 +247,8 @@ static void __init pcibios_allocate_resources(int pass)
                                         r->flags, disabled, pass);
                                 pr = pci_find_parent_resource(dev, r);
                                 if (!pr || request_resource(pr, r) < 0) {
+                                        if (check_platform(dev, r))
+                                                continue;
                                         dev_err(&dev->dev, "BAR %d: can't "
                                                 "allocate resource\n", idx);
                                         /* We'll assign a new address later */
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index fec0123b33a9..8e077185e185 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -590,6 +590,8 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
         case PCI_DEVICE_ID_INTEL_ICH10_1:
         case PCI_DEVICE_ID_INTEL_ICH10_2:
         case PCI_DEVICE_ID_INTEL_ICH10_3:
+        case PCI_DEVICE_ID_INTEL_PCH_0:
+        case PCI_DEVICE_ID_INTEL_PCH_1:
                 r->name = "PIIX/ICH";
                 r->get = pirq_piix_get;
                 r->set = pirq_piix_set;
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index ec9ce35e44d6..b722dd481b39 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -14,7 +14,7 @@ static void __devinit pcibios_fixup_peer_bridges(void)
         int n, devfn;
         long node;
 
-        if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
+        if (pcibios_last_bus <= 0 || pcibios_last_bus > 0xff)
                 return;
         DBG("PCI: Peer bridge fixup\n");
 
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 23faaa890ffc..d9635764ce3d 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -293,7 +293,7 @@ static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
         return AE_OK;
 }
 
-static int __init is_acpi_reserved(unsigned long start, unsigned long end)
+static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 {
         struct resource mcfg_res;
 
@@ -310,6 +310,41 @@ static int __init is_acpi_reserved(unsigned long start, unsigned long end)
         return mcfg_res.flags;
 }
 
+typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
+
+static int __init is_mmconf_reserved(check_reserved_t is_reserved,
+                u64 addr, u64 size, int i,
+                typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
+{
+        u64 old_size = size;
+        int valid = 0;
+
+        while (!is_reserved(addr, addr + size - 1, E820_RESERVED)) {
+                size >>= 1;
+                if (size < (16UL<<20))
+                        break;
+        }
+
+        if (size >= (16UL<<20) || size == old_size) {
+                printk(KERN_NOTICE
+                       "PCI: MCFG area at %Lx reserved in %s\n",
+                        addr, with_e820?"E820":"ACPI motherboard resources");
+                valid = 1;
+
+                if (old_size != size) {
+                        /* update end_bus_number */
+                        cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
+                        printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
+                               "segment %hu buses %u - %u\n",
+                               i, (unsigned long)cfg->address, cfg->pci_segment,
+                               (unsigned int)cfg->start_bus_number,
+                               (unsigned int)cfg->end_bus_number);
+                }
+        }
+
+        return valid;
+}
+
 static void __init pci_mmcfg_reject_broken(int early)
 {
         typeof(pci_mmcfg_config[0]) *cfg;
@@ -324,21 +359,22 @@ static void __init pci_mmcfg_reject_broken(int early)
 
         for (i = 0; i < pci_mmcfg_config_num; i++) {
                 int valid = 0;
-                u32 size = (cfg->end_bus_number + 1) << 20;
+                u64 addr, size;
+
                 cfg = &pci_mmcfg_config[i];
+                addr = cfg->start_bus_number;
+                addr <<= 20;
+                addr += cfg->address;
+                size = cfg->end_bus_number + 1 - cfg->start_bus_number;
+                size <<= 20;
                 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
                        "segment %hu buses %u - %u\n",
                        i, (unsigned long)cfg->address, cfg->pci_segment,
                        (unsigned int)cfg->start_bus_number,
                        (unsigned int)cfg->end_bus_number);
 
-                if (!early &&
-                    is_acpi_reserved(cfg->address, cfg->address + size - 1)) {
-                        printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved "
-                               "in ACPI motherboard resources\n",
-                               cfg->address);
-                        valid = 1;
-                }
+                if (!early)
+                        valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
 
                 if (valid)
                         continue;
@@ -347,16 +383,11 @@ static void __init pci_mmcfg_reject_broken(int early)
                         printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
                                " reserved in ACPI motherboard resources\n",
                                cfg->address);
+
                 /* Don't try to do this check unless configuration
                    type 1 is available. how about type 2 ?*/
-                if (raw_pci_ops && e820_all_mapped(cfg->address,
-                                                  cfg->address + size - 1,
-                                                  E820_RESERVED)) {
-                        printk(KERN_NOTICE
-                               "PCI: MCFG area at %Lx reserved in E820\n",
-                               cfg->address);
-                        valid = 1;
-                }
+                if (raw_pci_ops)
+                        valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
 
                 if (!valid)
                         goto reject;
@@ -365,7 +396,7 @@ static void __init pci_mmcfg_reject_broken(int early)
         return;
 
 reject:
-        printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
+        printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
         pci_mmcfg_arch_free();
         kfree(pci_mmcfg_config);
         pci_mmcfg_config = NULL;