5 files changed, 160 insertions, 11 deletions

diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 49a5cb55429b..ed2835e148b5 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -416,7 +416,12 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
                 kfree(sd);
         } else {
                 get_current_resources(device, busnum, domain, &resources);
-                if (list_empty(&resources))
+
+                /*
+                 * _CRS with no apertures is normal, so only fall back to
+                 * defaults or native bridge info if we're ignoring _CRS.
+                 */
+                if (!pci_use_crs)
                         x86_pci_root_bus_resources(busnum, &resources);
                 bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
                                           &resources);
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 6dd89555fbfa..d0e6e403b4f6 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -164,11 +164,11 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_
  */
 static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
 {
-        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
-            (dev->device & 0xff00) == 0x2400)
+        if ((dev->device & 0xff00) == 0x2400)
                 dev->transparent = 1;
 }
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
+DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
+                         PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
 
 /*
  * Fixup for C1 Halt Disconnect problem on nForce2 systems.
@@ -322,9 +322,6 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
         struct pci_bus *bus;
         u16 config;
 
-        if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
-                return;
-
         /* Is VGA routed to us? */
         bus = pdev->bus;
         while (bus) {
@@ -353,7 +350,8 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
                 dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n");
         }
 }
-DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+                                PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
 
 
 static const struct dmi_system_id __devinitconst msi_k8t_dmi_table[] = {
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 91821a1a0c3a..831971e731f7 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -39,6 +39,87 @@
 #include <asm/io_apic.h>
 
 
+/*
+ * This list of dynamic mappings is for temporarily maintaining
+ * original BIOS BAR addresses for possible reinstatement.
+ */
+struct pcibios_fwaddrmap {
+        struct list_head list;
+        struct pci_dev *dev;
+        resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
+};
+
+static LIST_HEAD(pcibios_fwaddrmappings);
+static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
+
+/* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
+static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
+{
+        struct pcibios_fwaddrmap *map;
+
+        WARN_ON(!spin_is_locked(&pcibios_fwaddrmap_lock));
+
+        list_for_each_entry(map, &pcibios_fwaddrmappings, list)
+                if (map->dev == dev)
+                        return map;
+
+        return NULL;
+}
+
+static void
+pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *map;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        map = pcibios_fwaddrmap_lookup(dev);
+        if (!map) {
+                spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+                map = kzalloc(sizeof(*map), GFP_KERNEL);
+                if (!map)
+                        return;
+
+                map->dev = pci_dev_get(dev);
+                map->fw_addr[idx] = fw_addr;
+                INIT_LIST_HEAD(&map->list);
+
+                spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+                list_add_tail(&map->list, &pcibios_fwaddrmappings);
+        } else
+                map->fw_addr[idx] = fw_addr;
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+}
+
+resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *map;
+        resource_size_t fw_addr = 0;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        map = pcibios_fwaddrmap_lookup(dev);
+        if (map)
+                fw_addr = map->fw_addr[idx];
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+
+        return fw_addr;
+}
+
+static void pcibios_fw_addr_list_del(void)
+{
+        unsigned long flags;
+        struct pcibios_fwaddrmap *entry, *next;
+
+        spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
+        list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
+                list_del(&entry->list);
+                pci_dev_put(entry->dev);
+                kfree(entry);
+        }
+        spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
+}
+
 static int
 skip_isa_ioresource_align(struct pci_dev *dev) {
 
@@ -182,7 +263,8 @@ static void __init pcibios_allocate_resources(int pass)
                                         idx, r, disabled, pass);
                                 if (pci_claim_resource(dev, idx) < 0) {
                                         /* We'll assign a new address later */
-                                        dev->fw_addr[idx] = r->start;
+                                        pcibios_save_fw_addr(dev,
+                                                        idx, r->start);
                                         r->end -= r->start;
                                         r->start = 0;
                                 }
@@ -228,6 +310,7 @@ static int __init pcibios_assign_resources(void)
         }
 
         pci_assign_unassigned_resources();
+        pcibios_fw_addr_list_del();
 
         return 0;
 }
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index cb29191cee58..140942f66b31 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -43,6 +43,8 @@
 #define PCI_FIXED_BAR_4_SIZE    0x14
 #define PCI_FIXED_BAR_5_SIZE    0x1c
 
+static int pci_soc_mode = 0;
+
 /**
  * fixed_bar_cap - return the offset of the fixed BAR cap if found
  * @bus: PCI bus
@@ -148,7 +150,9 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
          */
         if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
                 return 0;
-        if (bus == 0 && (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(0, 0)))
+        if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
+                                || devfn == PCI_DEVFN(0, 0)
+                                || devfn == PCI_DEVFN(3, 0)))
                 return 1;
         return 0; /* langwell on others */
 }
@@ -231,14 +235,43 @@ struct pci_ops pci_mrst_ops = {
  */
 int __init pci_mrst_init(void)
 {
-        printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n");
+        printk(KERN_INFO "Intel MID platform detected, using MID PCI ops\n");
         pci_mmcfg_late_init();
         pcibios_enable_irq = mrst_pci_irq_enable;
         pci_root_ops = pci_mrst_ops;
+        pci_soc_mode = 1;
         /* Continue with standard init */
         return 1;
 }
 
+/* Langwell devices are not true pci devices, they are not subject to 10 ms
+ * d3 to d0 delay required by pci spec.
+ */
+static void __devinit pci_d3delay_fixup(struct pci_dev *dev)
+{
+        /* PCI fixups are effectively decided compile time. If we have a dual
+           SoC/non-SoC kernel we don't want to mangle d3 on non SoC devices */
+        if (!pci_soc_mode)
+            return;
+        /* true pci devices in lincroft should allow type 1 access, the rest
+         * are langwell fake pci devices.
+         */
+        if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
+                return;
+        dev->d3_delay = 0;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
+
+static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev)
+{
+        pci_set_power_state(dev, PCI_D3cold);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0812, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
+
 /*
  * Langwell devices reside at fixed offsets, don't try to move them.
  */
@@ -248,6 +281,9 @@ static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev)
         u32 size;
         int i;
 
+        if (!pci_soc_mode)
+                return;
+
         /* Must have extended configuration space */
         if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
                 return;
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index d99346ea8fdb..7415aa927913 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -324,6 +324,32 @@ static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 out:
         return ret;
 }
+
+static void xen_initdom_restore_msi_irqs(struct pci_dev *dev, int irq)
+{
+        int ret = 0;
+
+        if (pci_seg_supported) {
+                struct physdev_pci_device restore_ext;
+
+                restore_ext.seg = pci_domain_nr(dev->bus);
+                restore_ext.bus = dev->bus->number;
+                restore_ext.devfn = dev->devfn;
+                ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
+                                        &restore_ext);
+                if (ret == -ENOSYS)
+                        pci_seg_supported = false;
+                WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
+        }
+        if (!pci_seg_supported) {
+                struct physdev_restore_msi restore;
+
+                restore.bus = dev->bus->number;
+                restore.devfn = dev->devfn;
+                ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
+                WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
+        }
+}
 #endif
 
 static void xen_teardown_msi_irqs(struct pci_dev *dev)
@@ -446,6 +472,7 @@ int __init pci_xen_initial_domain(void)
 #ifdef CONFIG_PCI_MSI
         x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
         x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
+        x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
 #endif
         xen_setup_acpi_sci();
         __acpi_register_gsi = acpi_register_gsi_xen;