diff options
Diffstat (limited to 'arch/x86/oprofile')
-rw-r--r-- | arch/x86/oprofile/op_model_athlon.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/x86/oprofile/op_model_athlon.c b/arch/x86/oprofile/op_model_athlon.c index 3057a19e4641..c3ee43333f26 100644 --- a/arch/x86/oprofile/op_model_athlon.c +++ b/arch/x86/oprofile/op_model_athlon.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /** | 1 | /** |
2 | * @file op_model_athlon.h | 2 | * @file op_model_athlon.h |
3 | * athlon / K7 model-specific MSR operations | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
4 | * | 4 | * |
5 | * @remark Copyright 2002 OProfile authors | 5 | * @remark Copyright 2002 OProfile authors |
6 | * @remark Read the file COPYING | 6 | * @remark Read the file COPYING |
@@ -31,12 +31,16 @@ | |||
31 | #define CTRL_WRITE(l,h,msrs,c) do {wrmsr(msrs->controls[(c)].addr, (l), (h));} while (0) | 31 | #define CTRL_WRITE(l,h,msrs,c) do {wrmsr(msrs->controls[(c)].addr, (l), (h));} while (0) |
32 | #define CTRL_SET_ACTIVE(n) (n |= (1<<22)) | 32 | #define CTRL_SET_ACTIVE(n) (n |= (1<<22)) |
33 | #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) | 33 | #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22)) |
34 | #define CTRL_CLEAR(x) (x &= (1<<21)) | 34 | #define CTRL_CLEAR_LO(x) (x &= (1<<21)) |
35 | #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0) | ||
35 | #define CTRL_SET_ENABLE(val) (val |= 1<<20) | 36 | #define CTRL_SET_ENABLE(val) (val |= 1<<20) |
36 | #define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16)) | 37 | #define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16)) |
37 | #define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17)) | 38 | #define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17)) |
38 | #define CTRL_SET_UM(val, m) (val |= (m << 8)) | 39 | #define CTRL_SET_UM(val, m) (val |= (m << 8)) |
39 | #define CTRL_SET_EVENT(val, e) (val |= e) | 40 | #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff)) |
41 | #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf)) | ||
42 | #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9)) | ||
43 | #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8)) | ||
40 | 44 | ||
41 | static unsigned long reset_value[NUM_COUNTERS]; | 45 | static unsigned long reset_value[NUM_COUNTERS]; |
42 | 46 | ||
@@ -70,7 +74,8 @@ static void athlon_setup_ctrs(struct op_msrs const * const msrs) | |||
70 | if (unlikely(!CTRL_IS_RESERVED(msrs,i))) | 74 | if (unlikely(!CTRL_IS_RESERVED(msrs,i))) |
71 | continue; | 75 | continue; |
72 | CTRL_READ(low, high, msrs, i); | 76 | CTRL_READ(low, high, msrs, i); |
73 | CTRL_CLEAR(low); | 77 | CTRL_CLEAR_LO(low); |
78 | CTRL_CLEAR_HI(high); | ||
74 | CTRL_WRITE(low, high, msrs, i); | 79 | CTRL_WRITE(low, high, msrs, i); |
75 | } | 80 | } |
76 | 81 | ||
@@ -89,12 +94,17 @@ static void athlon_setup_ctrs(struct op_msrs const * const msrs) | |||
89 | CTR_WRITE(counter_config[i].count, msrs, i); | 94 | CTR_WRITE(counter_config[i].count, msrs, i); |
90 | 95 | ||
91 | CTRL_READ(low, high, msrs, i); | 96 | CTRL_READ(low, high, msrs, i); |
92 | CTRL_CLEAR(low); | 97 | CTRL_CLEAR_LO(low); |
98 | CTRL_CLEAR_HI(high); | ||
93 | CTRL_SET_ENABLE(low); | 99 | CTRL_SET_ENABLE(low); |
94 | CTRL_SET_USR(low, counter_config[i].user); | 100 | CTRL_SET_USR(low, counter_config[i].user); |
95 | CTRL_SET_KERN(low, counter_config[i].kernel); | 101 | CTRL_SET_KERN(low, counter_config[i].kernel); |
96 | CTRL_SET_UM(low, counter_config[i].unit_mask); | 102 | CTRL_SET_UM(low, counter_config[i].unit_mask); |
97 | CTRL_SET_EVENT(low, counter_config[i].event); | 103 | CTRL_SET_EVENT_LOW(low, counter_config[i].event); |
104 | CTRL_SET_EVENT_HIGH(high, counter_config[i].event); | ||
105 | CTRL_SET_HOST_ONLY(high, 0); | ||
106 | CTRL_SET_GUEST_ONLY(high, 0); | ||
107 | |||
98 | CTRL_WRITE(low, high, msrs, i); | 108 | CTRL_WRITE(low, high, msrs, i); |
99 | } else { | 109 | } else { |
100 | reset_value[i] = 0; | 110 | reset_value[i] = 0; |