diff options
Diffstat (limited to 'arch/x86/oprofile/op_model_amd.c')
-rw-r--r-- | arch/x86/oprofile/op_model_amd.c | 280 |
1 files changed, 127 insertions, 153 deletions
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 090cbbec7dbd..b67a6b5aa8d4 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c | |||
@@ -30,13 +30,10 @@ | |||
30 | #include "op_counter.h" | 30 | #include "op_counter.h" |
31 | 31 | ||
32 | #define NUM_COUNTERS 4 | 32 | #define NUM_COUNTERS 4 |
33 | #define NUM_CONTROLS 4 | ||
34 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX | 33 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
35 | #define NUM_VIRT_COUNTERS 32 | 34 | #define NUM_VIRT_COUNTERS 32 |
36 | #define NUM_VIRT_CONTROLS 32 | ||
37 | #else | 35 | #else |
38 | #define NUM_VIRT_COUNTERS NUM_COUNTERS | 36 | #define NUM_VIRT_COUNTERS NUM_COUNTERS |
39 | #define NUM_VIRT_CONTROLS NUM_CONTROLS | ||
40 | #endif | 37 | #endif |
41 | 38 | ||
42 | #define OP_EVENT_MASK 0x0FFF | 39 | #define OP_EVENT_MASK 0x0FFF |
@@ -105,102 +102,6 @@ static u32 get_ibs_caps(void) | |||
105 | return ibs_caps; | 102 | return ibs_caps; |
106 | } | 103 | } |
107 | 104 | ||
108 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX | ||
109 | |||
110 | static void op_mux_switch_ctrl(struct op_x86_model_spec const *model, | ||
111 | struct op_msrs const * const msrs) | ||
112 | { | ||
113 | u64 val; | ||
114 | int i; | ||
115 | |||
116 | /* enable active counters */ | ||
117 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
118 | int virt = op_x86_phys_to_virt(i); | ||
119 | if (!reset_value[virt]) | ||
120 | continue; | ||
121 | rdmsrl(msrs->controls[i].addr, val); | ||
122 | val &= model->reserved; | ||
123 | val |= op_x86_get_ctrl(model, &counter_config[virt]); | ||
124 | wrmsrl(msrs->controls[i].addr, val); | ||
125 | } | ||
126 | } | ||
127 | |||
128 | #endif | ||
129 | |||
130 | /* functions for op_amd_spec */ | ||
131 | |||
132 | static void op_amd_fill_in_addresses(struct op_msrs * const msrs) | ||
133 | { | ||
134 | int i; | ||
135 | |||
136 | for (i = 0; i < NUM_COUNTERS; i++) { | ||
137 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) | ||
138 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; | ||
139 | } | ||
140 | |||
141 | for (i = 0; i < NUM_CONTROLS; i++) { | ||
142 | if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) | ||
143 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; | ||
144 | } | ||
145 | } | ||
146 | |||
147 | static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, | ||
148 | struct op_msrs const * const msrs) | ||
149 | { | ||
150 | u64 val; | ||
151 | int i; | ||
152 | |||
153 | /* setup reset_value */ | ||
154 | for (i = 0; i < NUM_VIRT_COUNTERS; ++i) { | ||
155 | if (counter_config[i].enabled | ||
156 | && msrs->counters[op_x86_virt_to_phys(i)].addr) | ||
157 | reset_value[i] = counter_config[i].count; | ||
158 | else | ||
159 | reset_value[i] = 0; | ||
160 | } | ||
161 | |||
162 | /* clear all counters */ | ||
163 | for (i = 0; i < NUM_CONTROLS; ++i) { | ||
164 | if (unlikely(!msrs->controls[i].addr)) { | ||
165 | if (counter_config[i].enabled && !smp_processor_id()) | ||
166 | /* | ||
167 | * counter is reserved, this is on all | ||
168 | * cpus, so report only for cpu #0 | ||
169 | */ | ||
170 | op_x86_warn_reserved(i); | ||
171 | continue; | ||
172 | } | ||
173 | rdmsrl(msrs->controls[i].addr, val); | ||
174 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | ||
175 | op_x86_warn_in_use(i); | ||
176 | val &= model->reserved; | ||
177 | wrmsrl(msrs->controls[i].addr, val); | ||
178 | } | ||
179 | |||
180 | /* avoid a false detection of ctr overflows in NMI handler */ | ||
181 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
182 | if (unlikely(!msrs->counters[i].addr)) | ||
183 | continue; | ||
184 | wrmsrl(msrs->counters[i].addr, -1LL); | ||
185 | } | ||
186 | |||
187 | /* enable active counters */ | ||
188 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
189 | int virt = op_x86_phys_to_virt(i); | ||
190 | if (!reset_value[virt]) | ||
191 | continue; | ||
192 | |||
193 | /* setup counter registers */ | ||
194 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); | ||
195 | |||
196 | /* setup control registers */ | ||
197 | rdmsrl(msrs->controls[i].addr, val); | ||
198 | val &= model->reserved; | ||
199 | val |= op_x86_get_ctrl(model, &counter_config[virt]); | ||
200 | wrmsrl(msrs->controls[i].addr, val); | ||
201 | } | ||
202 | } | ||
203 | |||
204 | /* | 105 | /* |
205 | * 16-bit Linear Feedback Shift Register (LFSR) | 106 | * 16-bit Linear Feedback Shift Register (LFSR) |
206 | * | 107 | * |
@@ -365,6 +266,125 @@ static void op_amd_stop_ibs(void) | |||
365 | wrmsrl(MSR_AMD64_IBSOPCTL, 0); | 266 | wrmsrl(MSR_AMD64_IBSOPCTL, 0); |
366 | } | 267 | } |
367 | 268 | ||
269 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX | ||
270 | |||
271 | static void op_mux_switch_ctrl(struct op_x86_model_spec const *model, | ||
272 | struct op_msrs const * const msrs) | ||
273 | { | ||
274 | u64 val; | ||
275 | int i; | ||
276 | |||
277 | /* enable active counters */ | ||
278 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
279 | int virt = op_x86_phys_to_virt(i); | ||
280 | if (!reset_value[virt]) | ||
281 | continue; | ||
282 | rdmsrl(msrs->controls[i].addr, val); | ||
283 | val &= model->reserved; | ||
284 | val |= op_x86_get_ctrl(model, &counter_config[virt]); | ||
285 | wrmsrl(msrs->controls[i].addr, val); | ||
286 | } | ||
287 | } | ||
288 | |||
289 | #endif | ||
290 | |||
291 | /* functions for op_amd_spec */ | ||
292 | |||
293 | static void op_amd_shutdown(struct op_msrs const * const msrs) | ||
294 | { | ||
295 | int i; | ||
296 | |||
297 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
298 | if (!msrs->counters[i].addr) | ||
299 | continue; | ||
300 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); | ||
301 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); | ||
302 | } | ||
303 | } | ||
304 | |||
305 | static int op_amd_fill_in_addresses(struct op_msrs * const msrs) | ||
306 | { | ||
307 | int i; | ||
308 | |||
309 | for (i = 0; i < NUM_COUNTERS; i++) { | ||
310 | if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) | ||
311 | goto fail; | ||
312 | if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) { | ||
313 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); | ||
314 | goto fail; | ||
315 | } | ||
316 | /* both registers must be reserved */ | ||
317 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; | ||
318 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; | ||
319 | continue; | ||
320 | fail: | ||
321 | if (!counter_config[i].enabled) | ||
322 | continue; | ||
323 | op_x86_warn_reserved(i); | ||
324 | op_amd_shutdown(msrs); | ||
325 | return -EBUSY; | ||
326 | } | ||
327 | |||
328 | return 0; | ||
329 | } | ||
330 | |||
331 | static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, | ||
332 | struct op_msrs const * const msrs) | ||
333 | { | ||
334 | u64 val; | ||
335 | int i; | ||
336 | |||
337 | /* setup reset_value */ | ||
338 | for (i = 0; i < NUM_VIRT_COUNTERS; ++i) { | ||
339 | if (counter_config[i].enabled | ||
340 | && msrs->counters[op_x86_virt_to_phys(i)].addr) | ||
341 | reset_value[i] = counter_config[i].count; | ||
342 | else | ||
343 | reset_value[i] = 0; | ||
344 | } | ||
345 | |||
346 | /* clear all counters */ | ||
347 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
348 | if (!msrs->controls[i].addr) | ||
349 | continue; | ||
350 | rdmsrl(msrs->controls[i].addr, val); | ||
351 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | ||
352 | op_x86_warn_in_use(i); | ||
353 | val &= model->reserved; | ||
354 | wrmsrl(msrs->controls[i].addr, val); | ||
355 | /* | ||
356 | * avoid a false detection of ctr overflows in NMI | ||
357 | * handler | ||
358 | */ | ||
359 | wrmsrl(msrs->counters[i].addr, -1LL); | ||
360 | } | ||
361 | |||
362 | /* enable active counters */ | ||
363 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
364 | int virt = op_x86_phys_to_virt(i); | ||
365 | if (!reset_value[virt]) | ||
366 | continue; | ||
367 | |||
368 | /* setup counter registers */ | ||
369 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); | ||
370 | |||
371 | /* setup control registers */ | ||
372 | rdmsrl(msrs->controls[i].addr, val); | ||
373 | val &= model->reserved; | ||
374 | val |= op_x86_get_ctrl(model, &counter_config[virt]); | ||
375 | wrmsrl(msrs->controls[i].addr, val); | ||
376 | } | ||
377 | |||
378 | if (ibs_caps) | ||
379 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0); | ||
380 | } | ||
381 | |||
382 | static void op_amd_cpu_shutdown(void) | ||
383 | { | ||
384 | if (ibs_caps) | ||
385 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); | ||
386 | } | ||
387 | |||
368 | static int op_amd_check_ctrs(struct pt_regs * const regs, | 388 | static int op_amd_check_ctrs(struct pt_regs * const regs, |
369 | struct op_msrs const * const msrs) | 389 | struct op_msrs const * const msrs) |
370 | { | 390 | { |
@@ -425,42 +445,16 @@ static void op_amd_stop(struct op_msrs const * const msrs) | |||
425 | op_amd_stop_ibs(); | 445 | op_amd_stop_ibs(); |
426 | } | 446 | } |
427 | 447 | ||
428 | static void op_amd_shutdown(struct op_msrs const * const msrs) | 448 | static int __init_ibs_nmi(void) |
429 | { | ||
430 | int i; | ||
431 | |||
432 | for (i = 0; i < NUM_COUNTERS; ++i) { | ||
433 | if (msrs->counters[i].addr) | ||
434 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); | ||
435 | } | ||
436 | for (i = 0; i < NUM_CONTROLS; ++i) { | ||
437 | if (msrs->controls[i].addr) | ||
438 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); | ||
439 | } | ||
440 | } | ||
441 | |||
442 | static u8 ibs_eilvt_off; | ||
443 | |||
444 | static inline void apic_init_ibs_nmi_per_cpu(void *arg) | ||
445 | { | ||
446 | ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0); | ||
447 | } | ||
448 | |||
449 | static inline void apic_clear_ibs_nmi_per_cpu(void *arg) | ||
450 | { | ||
451 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); | ||
452 | } | ||
453 | |||
454 | static int init_ibs_nmi(void) | ||
455 | { | 449 | { |
456 | #define IBSCTL_LVTOFFSETVAL (1 << 8) | 450 | #define IBSCTL_LVTOFFSETVAL (1 << 8) |
457 | #define IBSCTL 0x1cc | 451 | #define IBSCTL 0x1cc |
458 | struct pci_dev *cpu_cfg; | 452 | struct pci_dev *cpu_cfg; |
459 | int nodes; | 453 | int nodes; |
460 | u32 value = 0; | 454 | u32 value = 0; |
455 | u8 ibs_eilvt_off; | ||
461 | 456 | ||
462 | /* per CPU setup */ | 457 | ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); |
463 | on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1); | ||
464 | 458 | ||
465 | nodes = 0; | 459 | nodes = 0; |
466 | cpu_cfg = NULL; | 460 | cpu_cfg = NULL; |
@@ -490,22 +484,15 @@ static int init_ibs_nmi(void) | |||
490 | return 0; | 484 | return 0; |
491 | } | 485 | } |
492 | 486 | ||
493 | /* uninitialize the APIC for the IBS interrupts if needed */ | ||
494 | static void clear_ibs_nmi(void) | ||
495 | { | ||
496 | if (ibs_caps) | ||
497 | on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); | ||
498 | } | ||
499 | |||
500 | /* initialize the APIC for the IBS interrupts if available */ | 487 | /* initialize the APIC for the IBS interrupts if available */ |
501 | static void ibs_init(void) | 488 | static void init_ibs(void) |
502 | { | 489 | { |
503 | ibs_caps = get_ibs_caps(); | 490 | ibs_caps = get_ibs_caps(); |
504 | 491 | ||
505 | if (!ibs_caps) | 492 | if (!ibs_caps) |
506 | return; | 493 | return; |
507 | 494 | ||
508 | if (init_ibs_nmi()) { | 495 | if (__init_ibs_nmi()) { |
509 | ibs_caps = 0; | 496 | ibs_caps = 0; |
510 | return; | 497 | return; |
511 | } | 498 | } |
@@ -514,14 +501,6 @@ static void ibs_init(void) | |||
514 | (unsigned)ibs_caps); | 501 | (unsigned)ibs_caps); |
515 | } | 502 | } |
516 | 503 | ||
517 | static void ibs_exit(void) | ||
518 | { | ||
519 | if (!ibs_caps) | ||
520 | return; | ||
521 | |||
522 | clear_ibs_nmi(); | ||
523 | } | ||
524 | |||
525 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); | 504 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); |
526 | 505 | ||
527 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) | 506 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) |
@@ -570,27 +549,22 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) | |||
570 | 549 | ||
571 | static int op_amd_init(struct oprofile_operations *ops) | 550 | static int op_amd_init(struct oprofile_operations *ops) |
572 | { | 551 | { |
573 | ibs_init(); | 552 | init_ibs(); |
574 | create_arch_files = ops->create_files; | 553 | create_arch_files = ops->create_files; |
575 | ops->create_files = setup_ibs_files; | 554 | ops->create_files = setup_ibs_files; |
576 | return 0; | 555 | return 0; |
577 | } | 556 | } |
578 | 557 | ||
579 | static void op_amd_exit(void) | ||
580 | { | ||
581 | ibs_exit(); | ||
582 | } | ||
583 | |||
584 | struct op_x86_model_spec op_amd_spec = { | 558 | struct op_x86_model_spec op_amd_spec = { |
585 | .num_counters = NUM_COUNTERS, | 559 | .num_counters = NUM_COUNTERS, |
586 | .num_controls = NUM_CONTROLS, | 560 | .num_controls = NUM_COUNTERS, |
587 | .num_virt_counters = NUM_VIRT_COUNTERS, | 561 | .num_virt_counters = NUM_VIRT_COUNTERS, |
588 | .reserved = MSR_AMD_EVENTSEL_RESERVED, | 562 | .reserved = MSR_AMD_EVENTSEL_RESERVED, |
589 | .event_mask = OP_EVENT_MASK, | 563 | .event_mask = OP_EVENT_MASK, |
590 | .init = op_amd_init, | 564 | .init = op_amd_init, |
591 | .exit = op_amd_exit, | ||
592 | .fill_in_addresses = &op_amd_fill_in_addresses, | 565 | .fill_in_addresses = &op_amd_fill_in_addresses, |
593 | .setup_ctrs = &op_amd_setup_ctrs, | 566 | .setup_ctrs = &op_amd_setup_ctrs, |
567 | .cpu_down = &op_amd_cpu_shutdown, | ||
594 | .check_ctrs = &op_amd_check_ctrs, | 568 | .check_ctrs = &op_amd_check_ctrs, |
595 | .start = &op_amd_start, | 569 | .start = &op_amd_start, |
596 | .stop = &op_amd_stop, | 570 | .stop = &op_amd_stop, |