1 files changed, 12 insertions, 10 deletions

diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 8ca0d8566fc8..8253bc97587e 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -482,6 +482,13 @@ static int split_large_page(pte_t *kpte, unsigned long address)
         pbase = (pte_t *)page_address(base);
         paravirt_alloc_pte(&init_mm, page_to_pfn(base));
         ref_prot = pte_pgprot(pte_clrhuge(*kpte));
+        /*
+         * If we ever want to utilize the PAT bit, we need to
+         * update this function to make sure it's converted from
+         * bit 12 to bit 7 when we cross from the 2MB level to
+         * the 4K level:
+         */
+        WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE);
 
 #ifdef CONFIG_X86_64
         if (level == PG_LEVEL_1G) {
@@ -508,18 +515,13 @@ static int split_large_page(pte_t *kpte, unsigned long address)
 #endif
 
         /*
-         * Install the new, split up pagetable. Important details here:
-         *
-         * On Intel the NX bit of all levels must be cleared to make a
-         * page executable. See section 4.13.2 of Intel 64 and IA-32
-         * Architectures Software Developer's Manual).
+         * Install the new, split up pagetable.
          *
-         * Mark the entry present. The current mapping might be
-         * set to not present, which we preserved above.
+         * We use the standard kernel pagetable protections for the new
+         * pagetable protections, the actual ptes set above control the
+         * primary protection behavior:
          */
-        ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
-        pgprot_val(ref_prot) |= _PAGE_PRESENT;
-        __set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
+        __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
         base = NULL;
 
 out_unlock: