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-rw-r--r--arch/x86/mach-visws/visws_apic.c296
1 files changed, 0 insertions, 296 deletions
diff --git a/arch/x86/mach-visws/visws_apic.c b/arch/x86/mach-visws/visws_apic.c
deleted file mode 100644
index d8b2cfd85d92..000000000000
--- a/arch/x86/mach-visws/visws_apic.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
3 *
4 * SGI Visual Workstation interrupt controller
5 *
6 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
7 * which serves as the main interrupt controller in the system. Non-legacy
8 * hardware in the system uses this controller directly. Legacy devices
9 * are connected to the PIIX4 which in turn has its 8259(s) connected to
10 * a of the Cobalt APIC entry.
11 *
12 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
13 *
14 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
15 */
16
17#include <linux/kernel_stat.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20
21#include <asm/io.h>
22#include <asm/apic.h>
23#include <asm/i8259.h>
24#include <asm/irq_vectors.h>
25
26#include "cobalt.h"
27
28static DEFINE_SPINLOCK(cobalt_lock);
29
30/*
31 * Set the given Cobalt APIC Redirection Table entry to point
32 * to the given IDT vector/index.
33 */
34static inline void co_apic_set(int entry, int irq)
35{
36 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
37 co_apic_write(CO_APIC_HI(entry), 0);
38}
39
40/*
41 * Cobalt (IO)-APIC functions to handle PCI devices.
42 */
43static inline int co_apic_ide0_hack(void)
44{
45 extern char visws_board_type;
46 extern char visws_board_rev;
47
48 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
49 return 5;
50 return CO_APIC_IDE0;
51}
52
53static int is_co_apic(unsigned int irq)
54{
55 if (IS_CO_APIC(irq))
56 return CO_APIC(irq);
57
58 switch (irq) {
59 case 0: return CO_APIC_CPU;
60 case CO_IRQ_IDE0: return co_apic_ide0_hack();
61 case CO_IRQ_IDE1: return CO_APIC_IDE1;
62 default: return -1;
63 }
64}
65
66
67/*
68 * This is the SGI Cobalt (IO-)APIC:
69 */
70
71static void enable_cobalt_irq(unsigned int irq)
72{
73 co_apic_set(is_co_apic(irq), irq);
74}
75
76static void disable_cobalt_irq(unsigned int irq)
77{
78 int entry = is_co_apic(irq);
79
80 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
81 co_apic_read(CO_APIC_LO(entry));
82}
83
84/*
85 * "irq" really just serves to identify the device. Here is where we
86 * map this to the Cobalt APIC entry where it's physically wired.
87 * This is called via request_irq -> setup_irq -> irq_desc->startup()
88 */
89static unsigned int startup_cobalt_irq(unsigned int irq)
90{
91 unsigned long flags;
92
93 spin_lock_irqsave(&cobalt_lock, flags);
94 if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
95 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
96 enable_cobalt_irq(irq);
97 spin_unlock_irqrestore(&cobalt_lock, flags);
98 return 0;
99}
100
101static void ack_cobalt_irq(unsigned int irq)
102{
103 unsigned long flags;
104
105 spin_lock_irqsave(&cobalt_lock, flags);
106 disable_cobalt_irq(irq);
107 apic_write(APIC_EOI, APIC_EIO_ACK);
108 spin_unlock_irqrestore(&cobalt_lock, flags);
109}
110
111static void end_cobalt_irq(unsigned int irq)
112{
113 unsigned long flags;
114
115 spin_lock_irqsave(&cobalt_lock, flags);
116 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
117 enable_cobalt_irq(irq);
118 spin_unlock_irqrestore(&cobalt_lock, flags);
119}
120
121static struct irq_chip cobalt_irq_type = {
122 .typename = "Cobalt-APIC",
123 .startup = startup_cobalt_irq,
124 .shutdown = disable_cobalt_irq,
125 .enable = enable_cobalt_irq,
126 .disable = disable_cobalt_irq,
127 .ack = ack_cobalt_irq,
128 .end = end_cobalt_irq,
129};
130
131
132/*
133 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
134 * -- not the manner expected by the code in i8259.c.
135 *
136 * there is a 'master' physical interrupt source that gets sent to
137 * the CPU. But in the chipset there are various 'virtual' interrupts
138 * waiting to be handled. We represent this to Linux through a 'master'
139 * interrupt controller type, and through a special virtual interrupt-
140 * controller. Device drivers only see the virtual interrupt sources.
141 */
142static unsigned int startup_piix4_master_irq(unsigned int irq)
143{
144 init_8259A(0);
145
146 return startup_cobalt_irq(irq);
147}
148
149static void end_piix4_master_irq(unsigned int irq)
150{
151 unsigned long flags;
152
153 spin_lock_irqsave(&cobalt_lock, flags);
154 enable_cobalt_irq(irq);
155 spin_unlock_irqrestore(&cobalt_lock, flags);
156}
157
158static struct irq_chip piix4_master_irq_type = {
159 .typename = "PIIX4-master",
160 .startup = startup_piix4_master_irq,
161 .ack = ack_cobalt_irq,
162 .end = end_piix4_master_irq,
163};
164
165
166static struct irq_chip piix4_virtual_irq_type = {
167 .typename = "PIIX4-virtual",
168 .shutdown = disable_8259A_irq,
169 .enable = enable_8259A_irq,
170 .disable = disable_8259A_irq,
171};
172
173
174/*
175 * PIIX4-8259 master/virtual functions to handle interrupt requests
176 * from legacy devices: floppy, parallel, serial, rtc.
177 *
178 * None of these get Cobalt APIC entries, neither do they have IDT
179 * entries. These interrupts are purely virtual and distributed from
180 * the 'master' interrupt source: CO_IRQ_8259.
181 *
182 * When the 8259 interrupts its handler figures out which of these
183 * devices is interrupting and dispatches to its handler.
184 *
185 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
186 * enable_irq gets the right irq. This 'master' irq is never directly
187 * manipulated by any driver.
188 */
189static irqreturn_t piix4_master_intr(int irq, void *dev_id)
190{
191 int realirq;
192 irq_desc_t *desc;
193 unsigned long flags;
194
195 spin_lock_irqsave(&i8259A_lock, flags);
196
197 /* Find out what's interrupting in the PIIX4 master 8259 */
198 outb(0x0c, 0x20); /* OCW3 Poll command */
199 realirq = inb(0x20);
200
201 /*
202 * Bit 7 == 0 means invalid/spurious
203 */
204 if (unlikely(!(realirq & 0x80)))
205 goto out_unlock;
206
207 realirq &= 7;
208
209 if (unlikely(realirq == 2)) {
210 outb(0x0c, 0xa0);
211 realirq = inb(0xa0);
212
213 if (unlikely(!(realirq & 0x80)))
214 goto out_unlock;
215
216 realirq = (realirq & 7) + 8;
217 }
218
219 /* mask and ack interrupt */
220 cached_irq_mask |= 1 << realirq;
221 if (unlikely(realirq > 7)) {
222 inb(0xa1);
223 outb(cached_slave_mask, 0xa1);
224 outb(0x60 + (realirq & 7), 0xa0);
225 outb(0x60 + 2, 0x20);
226 } else {
227 inb(0x21);
228 outb(cached_master_mask, 0x21);
229 outb(0x60 + realirq, 0x20);
230 }
231
232 spin_unlock_irqrestore(&i8259A_lock, flags);
233
234 desc = irq_desc + realirq;
235
236 /*
237 * handle this 'virtual interrupt' as a Cobalt one now.
238 */
239 kstat_cpu(smp_processor_id()).irqs[realirq]++;
240
241 if (likely(desc->action != NULL))
242 handle_IRQ_event(realirq, desc->action);
243
244 if (!(desc->status & IRQ_DISABLED))
245 enable_8259A_irq(realirq);
246
247 return IRQ_HANDLED;
248
249out_unlock:
250 spin_unlock_irqrestore(&i8259A_lock, flags);
251 return IRQ_NONE;
252}
253
254static struct irqaction master_action = {
255 .handler = piix4_master_intr,
256 .name = "PIIX4-8259",
257};
258
259static struct irqaction cascade_action = {
260 .handler = no_action,
261 .name = "cascade",
262};
263
264
265void init_VISWS_APIC_irqs(void)
266{
267 int i;
268
269 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
270 irq_desc[i].status = IRQ_DISABLED;
271 irq_desc[i].action = 0;
272 irq_desc[i].depth = 1;
273
274 if (i == 0) {
275 irq_desc[i].chip = &cobalt_irq_type;
276 }
277 else if (i == CO_IRQ_IDE0) {
278 irq_desc[i].chip = &cobalt_irq_type;
279 }
280 else if (i == CO_IRQ_IDE1) {
281 irq_desc[i].chip = &cobalt_irq_type;
282 }
283 else if (i == CO_IRQ_8259) {
284 irq_desc[i].chip = &piix4_master_irq_type;
285 }
286 else if (i < CO_IRQ_APIC0) {
287 irq_desc[i].chip = &piix4_virtual_irq_type;
288 }
289 else if (IS_CO_APIC(i)) {
290 irq_desc[i].chip = &cobalt_irq_type;
291 }
292 }
293
294 setup_irq(CO_IRQ_8259, &master_action);
295 setup_irq(2, &cascade_action);
296}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 02:41:29 -0500