diff options
Diffstat (limited to 'arch/x86/kvm/vmx.c')
-rw-r--r-- | arch/x86/kvm/vmx.c | 721 |
1 files changed, 388 insertions, 333 deletions
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index bb481330716f..32d6ae8fb60e 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c | |||
@@ -32,26 +32,27 @@ | |||
32 | #include <asm/desc.h> | 32 | #include <asm/desc.h> |
33 | #include <asm/vmx.h> | 33 | #include <asm/vmx.h> |
34 | #include <asm/virtext.h> | 34 | #include <asm/virtext.h> |
35 | #include <asm/mce.h> | ||
35 | 36 | ||
36 | #define __ex(x) __kvm_handle_fault_on_reboot(x) | 37 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
37 | 38 | ||
38 | MODULE_AUTHOR("Qumranet"); | 39 | MODULE_AUTHOR("Qumranet"); |
39 | MODULE_LICENSE("GPL"); | 40 | MODULE_LICENSE("GPL"); |
40 | 41 | ||
41 | static int bypass_guest_pf = 1; | 42 | static int __read_mostly bypass_guest_pf = 1; |
42 | module_param(bypass_guest_pf, bool, 0); | 43 | module_param(bypass_guest_pf, bool, S_IRUGO); |
43 | 44 | ||
44 | static int enable_vpid = 1; | 45 | static int __read_mostly enable_vpid = 1; |
45 | module_param(enable_vpid, bool, 0); | 46 | module_param_named(vpid, enable_vpid, bool, 0444); |
46 | 47 | ||
47 | static int flexpriority_enabled = 1; | 48 | static int __read_mostly flexpriority_enabled = 1; |
48 | module_param(flexpriority_enabled, bool, 0); | 49 | module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); |
49 | 50 | ||
50 | static int enable_ept = 1; | 51 | static int __read_mostly enable_ept = 1; |
51 | module_param(enable_ept, bool, 0); | 52 | module_param_named(ept, enable_ept, bool, S_IRUGO); |
52 | 53 | ||
53 | static int emulate_invalid_guest_state = 0; | 54 | static int __read_mostly emulate_invalid_guest_state = 0; |
54 | module_param(emulate_invalid_guest_state, bool, 0); | 55 | module_param(emulate_invalid_guest_state, bool, S_IRUGO); |
55 | 56 | ||
56 | struct vmcs { | 57 | struct vmcs { |
57 | u32 revision_id; | 58 | u32 revision_id; |
@@ -97,6 +98,7 @@ struct vcpu_vmx { | |||
97 | int soft_vnmi_blocked; | 98 | int soft_vnmi_blocked; |
98 | ktime_t entry_time; | 99 | ktime_t entry_time; |
99 | s64 vnmi_blocked_time; | 100 | s64 vnmi_blocked_time; |
101 | u32 exit_reason; | ||
100 | }; | 102 | }; |
101 | 103 | ||
102 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | 104 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) |
@@ -111,9 +113,10 @@ static DEFINE_PER_CPU(struct vmcs *, vmxarea); | |||
111 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | 113 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); |
112 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); | 114 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
113 | 115 | ||
114 | static struct page *vmx_io_bitmap_a; | 116 | static unsigned long *vmx_io_bitmap_a; |
115 | static struct page *vmx_io_bitmap_b; | 117 | static unsigned long *vmx_io_bitmap_b; |
116 | static struct page *vmx_msr_bitmap; | 118 | static unsigned long *vmx_msr_bitmap_legacy; |
119 | static unsigned long *vmx_msr_bitmap_longmode; | ||
117 | 120 | ||
118 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); | 121 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
119 | static DEFINE_SPINLOCK(vmx_vpid_lock); | 122 | static DEFINE_SPINLOCK(vmx_vpid_lock); |
@@ -213,70 +216,78 @@ static inline int is_external_interrupt(u32 intr_info) | |||
213 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | 216 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); |
214 | } | 217 | } |
215 | 218 | ||
219 | static inline int is_machine_check(u32 intr_info) | ||
220 | { | ||
221 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | ||
222 | INTR_INFO_VALID_MASK)) == | ||
223 | (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK); | ||
224 | } | ||
225 | |||
216 | static inline int cpu_has_vmx_msr_bitmap(void) | 226 | static inline int cpu_has_vmx_msr_bitmap(void) |
217 | { | 227 | { |
218 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | 228 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS; |
219 | } | 229 | } |
220 | 230 | ||
221 | static inline int cpu_has_vmx_tpr_shadow(void) | 231 | static inline int cpu_has_vmx_tpr_shadow(void) |
222 | { | 232 | { |
223 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | 233 | return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW; |
224 | } | 234 | } |
225 | 235 | ||
226 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | 236 | static inline int vm_need_tpr_shadow(struct kvm *kvm) |
227 | { | 237 | { |
228 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | 238 | return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)); |
229 | } | 239 | } |
230 | 240 | ||
231 | static inline int cpu_has_secondary_exec_ctrls(void) | 241 | static inline int cpu_has_secondary_exec_ctrls(void) |
232 | { | 242 | { |
233 | return (vmcs_config.cpu_based_exec_ctrl & | 243 | return vmcs_config.cpu_based_exec_ctrl & |
234 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | 244 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
235 | } | 245 | } |
236 | 246 | ||
237 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) | 247 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
238 | { | 248 | { |
239 | return flexpriority_enabled | 249 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
240 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | 250 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
241 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | 251 | } |
252 | |||
253 | static inline bool cpu_has_vmx_flexpriority(void) | ||
254 | { | ||
255 | return cpu_has_vmx_tpr_shadow() && | ||
256 | cpu_has_vmx_virtualize_apic_accesses(); | ||
242 | } | 257 | } |
243 | 258 | ||
244 | static inline int cpu_has_vmx_invept_individual_addr(void) | 259 | static inline int cpu_has_vmx_invept_individual_addr(void) |
245 | { | 260 | { |
246 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | 261 | return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT); |
247 | } | 262 | } |
248 | 263 | ||
249 | static inline int cpu_has_vmx_invept_context(void) | 264 | static inline int cpu_has_vmx_invept_context(void) |
250 | { | 265 | { |
251 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | 266 | return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT); |
252 | } | 267 | } |
253 | 268 | ||
254 | static inline int cpu_has_vmx_invept_global(void) | 269 | static inline int cpu_has_vmx_invept_global(void) |
255 | { | 270 | { |
256 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | 271 | return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT); |
257 | } | 272 | } |
258 | 273 | ||
259 | static inline int cpu_has_vmx_ept(void) | 274 | static inline int cpu_has_vmx_ept(void) |
260 | { | 275 | { |
261 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | 276 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
262 | SECONDARY_EXEC_ENABLE_EPT); | 277 | SECONDARY_EXEC_ENABLE_EPT; |
263 | } | ||
264 | |||
265 | static inline int vm_need_ept(void) | ||
266 | { | ||
267 | return (cpu_has_vmx_ept() && enable_ept); | ||
268 | } | 278 | } |
269 | 279 | ||
270 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) | 280 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
271 | { | 281 | { |
272 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | 282 | return flexpriority_enabled && |
273 | (irqchip_in_kernel(kvm))); | 283 | (cpu_has_vmx_virtualize_apic_accesses()) && |
284 | (irqchip_in_kernel(kvm)); | ||
274 | } | 285 | } |
275 | 286 | ||
276 | static inline int cpu_has_vmx_vpid(void) | 287 | static inline int cpu_has_vmx_vpid(void) |
277 | { | 288 | { |
278 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | 289 | return vmcs_config.cpu_based_2nd_exec_ctrl & |
279 | SECONDARY_EXEC_ENABLE_VPID); | 290 | SECONDARY_EXEC_ENABLE_VPID; |
280 | } | 291 | } |
281 | 292 | ||
282 | static inline int cpu_has_virtual_nmis(void) | 293 | static inline int cpu_has_virtual_nmis(void) |
@@ -284,6 +295,11 @@ static inline int cpu_has_virtual_nmis(void) | |||
284 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | 295 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; |
285 | } | 296 | } |
286 | 297 | ||
298 | static inline bool report_flexpriority(void) | ||
299 | { | ||
300 | return flexpriority_enabled; | ||
301 | } | ||
302 | |||
287 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) | 303 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
288 | { | 304 | { |
289 | int i; | 305 | int i; |
@@ -381,7 +397,7 @@ static inline void ept_sync_global(void) | |||
381 | 397 | ||
382 | static inline void ept_sync_context(u64 eptp) | 398 | static inline void ept_sync_context(u64 eptp) |
383 | { | 399 | { |
384 | if (vm_need_ept()) { | 400 | if (enable_ept) { |
385 | if (cpu_has_vmx_invept_context()) | 401 | if (cpu_has_vmx_invept_context()) |
386 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | 402 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); |
387 | else | 403 | else |
@@ -391,7 +407,7 @@ static inline void ept_sync_context(u64 eptp) | |||
391 | 407 | ||
392 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | 408 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) |
393 | { | 409 | { |
394 | if (vm_need_ept()) { | 410 | if (enable_ept) { |
395 | if (cpu_has_vmx_invept_individual_addr()) | 411 | if (cpu_has_vmx_invept_individual_addr()) |
396 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | 412 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, |
397 | eptp, gpa); | 413 | eptp, gpa); |
@@ -478,7 +494,7 @@ static void update_exception_bitmap(struct kvm_vcpu *vcpu) | |||
478 | { | 494 | { |
479 | u32 eb; | 495 | u32 eb; |
480 | 496 | ||
481 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); | 497 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR); |
482 | if (!vcpu->fpu_active) | 498 | if (!vcpu->fpu_active) |
483 | eb |= 1u << NM_VECTOR; | 499 | eb |= 1u << NM_VECTOR; |
484 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { | 500 | if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) { |
@@ -488,9 +504,9 @@ static void update_exception_bitmap(struct kvm_vcpu *vcpu) | |||
488 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) | 504 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) |
489 | eb |= 1u << BP_VECTOR; | 505 | eb |= 1u << BP_VECTOR; |
490 | } | 506 | } |
491 | if (vcpu->arch.rmode.active) | 507 | if (vcpu->arch.rmode.vm86_active) |
492 | eb = ~0; | 508 | eb = ~0; |
493 | if (vm_need_ept()) | 509 | if (enable_ept) |
494 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ | 510 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ |
495 | vmcs_write32(EXCEPTION_BITMAP, eb); | 511 | vmcs_write32(EXCEPTION_BITMAP, eb); |
496 | } | 512 | } |
@@ -724,29 +740,50 @@ static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) | |||
724 | 740 | ||
725 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | 741 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
726 | { | 742 | { |
727 | if (vcpu->arch.rmode.active) | 743 | if (vcpu->arch.rmode.vm86_active) |
728 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; | 744 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
729 | vmcs_writel(GUEST_RFLAGS, rflags); | 745 | vmcs_writel(GUEST_RFLAGS, rflags); |
730 | } | 746 | } |
731 | 747 | ||
748 | static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | ||
749 | { | ||
750 | u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | ||
751 | int ret = 0; | ||
752 | |||
753 | if (interruptibility & GUEST_INTR_STATE_STI) | ||
754 | ret |= X86_SHADOW_INT_STI; | ||
755 | if (interruptibility & GUEST_INTR_STATE_MOV_SS) | ||
756 | ret |= X86_SHADOW_INT_MOV_SS; | ||
757 | |||
758 | return ret & mask; | ||
759 | } | ||
760 | |||
761 | static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) | ||
762 | { | ||
763 | u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | ||
764 | u32 interruptibility = interruptibility_old; | ||
765 | |||
766 | interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); | ||
767 | |||
768 | if (mask & X86_SHADOW_INT_MOV_SS) | ||
769 | interruptibility |= GUEST_INTR_STATE_MOV_SS; | ||
770 | if (mask & X86_SHADOW_INT_STI) | ||
771 | interruptibility |= GUEST_INTR_STATE_STI; | ||
772 | |||
773 | if ((interruptibility != interruptibility_old)) | ||
774 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); | ||
775 | } | ||
776 | |||
732 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | 777 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) |
733 | { | 778 | { |
734 | unsigned long rip; | 779 | unsigned long rip; |
735 | u32 interruptibility; | ||
736 | 780 | ||
737 | rip = kvm_rip_read(vcpu); | 781 | rip = kvm_rip_read(vcpu); |
738 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); | 782 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
739 | kvm_rip_write(vcpu, rip); | 783 | kvm_rip_write(vcpu, rip); |
740 | 784 | ||
741 | /* | 785 | /* skipping an emulated instruction also counts */ |
742 | * We emulated an instruction, so temporary interrupt blocking | 786 | vmx_set_interrupt_shadow(vcpu, 0); |
743 | * should be removed, if set. | ||
744 | */ | ||
745 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | ||
746 | if (interruptibility & 3) | ||
747 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | ||
748 | interruptibility & ~3); | ||
749 | vcpu->arch.interrupt_window_open = 1; | ||
750 | } | 787 | } |
751 | 788 | ||
752 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, | 789 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
@@ -760,7 +797,7 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, | |||
760 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; | 797 | intr_info |= INTR_INFO_DELIVER_CODE_MASK; |
761 | } | 798 | } |
762 | 799 | ||
763 | if (vcpu->arch.rmode.active) { | 800 | if (vcpu->arch.rmode.vm86_active) { |
764 | vmx->rmode.irq.pending = true; | 801 | vmx->rmode.irq.pending = true; |
765 | vmx->rmode.irq.vector = nr; | 802 | vmx->rmode.irq.vector = nr; |
766 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | 803 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
@@ -773,8 +810,9 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, | |||
773 | return; | 810 | return; |
774 | } | 811 | } |
775 | 812 | ||
776 | if (nr == BP_VECTOR || nr == OF_VECTOR) { | 813 | if (kvm_exception_is_soft(nr)) { |
777 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | 814 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, |
815 | vmx->vcpu.arch.event_exit_inst_len); | ||
778 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; | 816 | intr_info |= INTR_TYPE_SOFT_EXCEPTION; |
779 | } else | 817 | } else |
780 | intr_info |= INTR_TYPE_HARD_EXCEPTION; | 818 | intr_info |= INTR_TYPE_HARD_EXCEPTION; |
@@ -782,11 +820,6 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, | |||
782 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); | 820 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); |
783 | } | 821 | } |
784 | 822 | ||
785 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | ||
786 | { | ||
787 | return false; | ||
788 | } | ||
789 | |||
790 | /* | 823 | /* |
791 | * Swap MSR entry in host/guest MSR entry array. | 824 | * Swap MSR entry in host/guest MSR entry array. |
792 | */ | 825 | */ |
@@ -812,6 +845,7 @@ static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) | |||
812 | static void setup_msrs(struct vcpu_vmx *vmx) | 845 | static void setup_msrs(struct vcpu_vmx *vmx) |
813 | { | 846 | { |
814 | int save_nmsrs; | 847 | int save_nmsrs; |
848 | unsigned long *msr_bitmap; | ||
815 | 849 | ||
816 | vmx_load_host_state(vmx); | 850 | vmx_load_host_state(vmx); |
817 | save_nmsrs = 0; | 851 | save_nmsrs = 0; |
@@ -847,6 +881,15 @@ static void setup_msrs(struct vcpu_vmx *vmx) | |||
847 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | 881 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
848 | #endif | 882 | #endif |
849 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); | 883 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
884 | |||
885 | if (cpu_has_vmx_msr_bitmap()) { | ||
886 | if (is_long_mode(&vmx->vcpu)) | ||
887 | msr_bitmap = vmx_msr_bitmap_longmode; | ||
888 | else | ||
889 | msr_bitmap = vmx_msr_bitmap_legacy; | ||
890 | |||
891 | vmcs_write64(MSR_BITMAP, __pa(msr_bitmap)); | ||
892 | } | ||
850 | } | 893 | } |
851 | 894 | ||
852 | /* | 895 | /* |
@@ -1034,13 +1077,6 @@ static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg) | |||
1034 | return 0; | 1077 | return 0; |
1035 | } | 1078 | } |
1036 | 1079 | ||
1037 | static int vmx_get_irq(struct kvm_vcpu *vcpu) | ||
1038 | { | ||
1039 | if (!vcpu->arch.interrupt.pending) | ||
1040 | return -1; | ||
1041 | return vcpu->arch.interrupt.nr; | ||
1042 | } | ||
1043 | |||
1044 | static __init int cpu_has_kvm_support(void) | 1080 | static __init int cpu_has_kvm_support(void) |
1045 | { | 1081 | { |
1046 | return cpu_has_vmx(); | 1082 | return cpu_has_vmx(); |
@@ -1294,6 +1330,18 @@ static __init int hardware_setup(void) | |||
1294 | if (boot_cpu_has(X86_FEATURE_NX)) | 1330 | if (boot_cpu_has(X86_FEATURE_NX)) |
1295 | kvm_enable_efer_bits(EFER_NX); | 1331 | kvm_enable_efer_bits(EFER_NX); |
1296 | 1332 | ||
1333 | if (!cpu_has_vmx_vpid()) | ||
1334 | enable_vpid = 0; | ||
1335 | |||
1336 | if (!cpu_has_vmx_ept()) | ||
1337 | enable_ept = 0; | ||
1338 | |||
1339 | if (!cpu_has_vmx_flexpriority()) | ||
1340 | flexpriority_enabled = 0; | ||
1341 | |||
1342 | if (!cpu_has_vmx_tpr_shadow()) | ||
1343 | kvm_x86_ops->update_cr8_intercept = NULL; | ||
1344 | |||
1297 | return alloc_kvm_area(); | 1345 | return alloc_kvm_area(); |
1298 | } | 1346 | } |
1299 | 1347 | ||
@@ -1324,7 +1372,7 @@ static void enter_pmode(struct kvm_vcpu *vcpu) | |||
1324 | struct vcpu_vmx *vmx = to_vmx(vcpu); | 1372 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1325 | 1373 | ||
1326 | vmx->emulation_required = 1; | 1374 | vmx->emulation_required = 1; |
1327 | vcpu->arch.rmode.active = 0; | 1375 | vcpu->arch.rmode.vm86_active = 0; |
1328 | 1376 | ||
1329 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); | 1377 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1330 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | 1378 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); |
@@ -1386,7 +1434,7 @@ static void enter_rmode(struct kvm_vcpu *vcpu) | |||
1386 | struct vcpu_vmx *vmx = to_vmx(vcpu); | 1434 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1387 | 1435 | ||
1388 | vmx->emulation_required = 1; | 1436 | vmx->emulation_required = 1; |
1389 | vcpu->arch.rmode.active = 1; | 1437 | vcpu->arch.rmode.vm86_active = 1; |
1390 | 1438 | ||
1391 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); | 1439 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
1392 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); | 1440 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
@@ -1485,7 +1533,7 @@ static void exit_lmode(struct kvm_vcpu *vcpu) | |||
1485 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) | 1533 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1486 | { | 1534 | { |
1487 | vpid_sync_vcpu_all(to_vmx(vcpu)); | 1535 | vpid_sync_vcpu_all(to_vmx(vcpu)); |
1488 | if (vm_need_ept()) | 1536 | if (enable_ept) |
1489 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); | 1537 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); |
1490 | } | 1538 | } |
1491 | 1539 | ||
@@ -1555,10 +1603,10 @@ static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) | |||
1555 | 1603 | ||
1556 | vmx_fpu_deactivate(vcpu); | 1604 | vmx_fpu_deactivate(vcpu); |
1557 | 1605 | ||
1558 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) | 1606 | if (vcpu->arch.rmode.vm86_active && (cr0 & X86_CR0_PE)) |
1559 | enter_pmode(vcpu); | 1607 | enter_pmode(vcpu); |
1560 | 1608 | ||
1561 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) | 1609 | if (!vcpu->arch.rmode.vm86_active && !(cr0 & X86_CR0_PE)) |
1562 | enter_rmode(vcpu); | 1610 | enter_rmode(vcpu); |
1563 | 1611 | ||
1564 | #ifdef CONFIG_X86_64 | 1612 | #ifdef CONFIG_X86_64 |
@@ -1570,7 +1618,7 @@ static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) | |||
1570 | } | 1618 | } |
1571 | #endif | 1619 | #endif |
1572 | 1620 | ||
1573 | if (vm_need_ept()) | 1621 | if (enable_ept) |
1574 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); | 1622 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); |
1575 | 1623 | ||
1576 | vmcs_writel(CR0_READ_SHADOW, cr0); | 1624 | vmcs_writel(CR0_READ_SHADOW, cr0); |
@@ -1599,7 +1647,7 @@ static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) | |||
1599 | u64 eptp; | 1647 | u64 eptp; |
1600 | 1648 | ||
1601 | guest_cr3 = cr3; | 1649 | guest_cr3 = cr3; |
1602 | if (vm_need_ept()) { | 1650 | if (enable_ept) { |
1603 | eptp = construct_eptp(cr3); | 1651 | eptp = construct_eptp(cr3); |
1604 | vmcs_write64(EPT_POINTER, eptp); | 1652 | vmcs_write64(EPT_POINTER, eptp); |
1605 | ept_sync_context(eptp); | 1653 | ept_sync_context(eptp); |
@@ -1616,11 +1664,11 @@ static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) | |||
1616 | 1664 | ||
1617 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | 1665 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
1618 | { | 1666 | { |
1619 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ? | 1667 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.vm86_active ? |
1620 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | 1668 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); |
1621 | 1669 | ||
1622 | vcpu->arch.cr4 = cr4; | 1670 | vcpu->arch.cr4 = cr4; |
1623 | if (vm_need_ept()) | 1671 | if (enable_ept) |
1624 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); | 1672 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); |
1625 | 1673 | ||
1626 | vmcs_writel(CR4_READ_SHADOW, cr4); | 1674 | vmcs_writel(CR4_READ_SHADOW, cr4); |
@@ -1699,7 +1747,7 @@ static void vmx_set_segment(struct kvm_vcpu *vcpu, | |||
1699 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | 1747 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; |
1700 | u32 ar; | 1748 | u32 ar; |
1701 | 1749 | ||
1702 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { | 1750 | if (vcpu->arch.rmode.vm86_active && seg == VCPU_SREG_TR) { |
1703 | vcpu->arch.rmode.tr.selector = var->selector; | 1751 | vcpu->arch.rmode.tr.selector = var->selector; |
1704 | vcpu->arch.rmode.tr.base = var->base; | 1752 | vcpu->arch.rmode.tr.base = var->base; |
1705 | vcpu->arch.rmode.tr.limit = var->limit; | 1753 | vcpu->arch.rmode.tr.limit = var->limit; |
@@ -1709,7 +1757,7 @@ static void vmx_set_segment(struct kvm_vcpu *vcpu, | |||
1709 | vmcs_writel(sf->base, var->base); | 1757 | vmcs_writel(sf->base, var->base); |
1710 | vmcs_write32(sf->limit, var->limit); | 1758 | vmcs_write32(sf->limit, var->limit); |
1711 | vmcs_write16(sf->selector, var->selector); | 1759 | vmcs_write16(sf->selector, var->selector); |
1712 | if (vcpu->arch.rmode.active && var->s) { | 1760 | if (vcpu->arch.rmode.vm86_active && var->s) { |
1713 | /* | 1761 | /* |
1714 | * Hack real-mode segments into vm86 compatibility. | 1762 | * Hack real-mode segments into vm86 compatibility. |
1715 | */ | 1763 | */ |
@@ -1982,7 +2030,7 @@ static int init_rmode_identity_map(struct kvm *kvm) | |||
1982 | pfn_t identity_map_pfn; | 2030 | pfn_t identity_map_pfn; |
1983 | u32 tmp; | 2031 | u32 tmp; |
1984 | 2032 | ||
1985 | if (!vm_need_ept()) | 2033 | if (!enable_ept) |
1986 | return 1; | 2034 | return 1; |
1987 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | 2035 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { |
1988 | printk(KERN_ERR "EPT: identity-mapping pagetable " | 2036 | printk(KERN_ERR "EPT: identity-mapping pagetable " |
@@ -2071,7 +2119,7 @@ static void allocate_vpid(struct vcpu_vmx *vmx) | |||
2071 | int vpid; | 2119 | int vpid; |
2072 | 2120 | ||
2073 | vmx->vpid = 0; | 2121 | vmx->vpid = 0; |
2074 | if (!enable_vpid || !cpu_has_vmx_vpid()) | 2122 | if (!enable_vpid) |
2075 | return; | 2123 | return; |
2076 | spin_lock(&vmx_vpid_lock); | 2124 | spin_lock(&vmx_vpid_lock); |
2077 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | 2125 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); |
@@ -2082,9 +2130,9 @@ static void allocate_vpid(struct vcpu_vmx *vmx) | |||
2082 | spin_unlock(&vmx_vpid_lock); | 2130 | spin_unlock(&vmx_vpid_lock); |
2083 | } | 2131 | } |
2084 | 2132 | ||
2085 | static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) | 2133 | static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr) |
2086 | { | 2134 | { |
2087 | void *va; | 2135 | int f = sizeof(unsigned long); |
2088 | 2136 | ||
2089 | if (!cpu_has_vmx_msr_bitmap()) | 2137 | if (!cpu_has_vmx_msr_bitmap()) |
2090 | return; | 2138 | return; |
@@ -2094,16 +2142,21 @@ static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) | |||
2094 | * have the write-low and read-high bitmap offsets the wrong way round. | 2142 | * have the write-low and read-high bitmap offsets the wrong way round. |
2095 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | 2143 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. |
2096 | */ | 2144 | */ |
2097 | va = kmap(msr_bitmap); | ||
2098 | if (msr <= 0x1fff) { | 2145 | if (msr <= 0x1fff) { |
2099 | __clear_bit(msr, va + 0x000); /* read-low */ | 2146 | __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */ |
2100 | __clear_bit(msr, va + 0x800); /* write-low */ | 2147 | __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */ |
2101 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | 2148 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { |
2102 | msr &= 0x1fff; | 2149 | msr &= 0x1fff; |
2103 | __clear_bit(msr, va + 0x400); /* read-high */ | 2150 | __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */ |
2104 | __clear_bit(msr, va + 0xc00); /* write-high */ | 2151 | __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */ |
2105 | } | 2152 | } |
2106 | kunmap(msr_bitmap); | 2153 | } |
2154 | |||
2155 | static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only) | ||
2156 | { | ||
2157 | if (!longmode_only) | ||
2158 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr); | ||
2159 | __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr); | ||
2107 | } | 2160 | } |
2108 | 2161 | ||
2109 | /* | 2162 | /* |
@@ -2121,11 +2174,11 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) | |||
2121 | u32 exec_control; | 2174 | u32 exec_control; |
2122 | 2175 | ||
2123 | /* I/O */ | 2176 | /* I/O */ |
2124 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); | 2177 | vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a)); |
2125 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | 2178 | vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b)); |
2126 | 2179 | ||
2127 | if (cpu_has_vmx_msr_bitmap()) | 2180 | if (cpu_has_vmx_msr_bitmap()) |
2128 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | 2181 | vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy)); |
2129 | 2182 | ||
2130 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ | 2183 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
2131 | 2184 | ||
@@ -2141,7 +2194,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) | |||
2141 | CPU_BASED_CR8_LOAD_EXITING; | 2194 | CPU_BASED_CR8_LOAD_EXITING; |
2142 | #endif | 2195 | #endif |
2143 | } | 2196 | } |
2144 | if (!vm_need_ept()) | 2197 | if (!enable_ept) |
2145 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | 2198 | exec_control |= CPU_BASED_CR3_STORE_EXITING | |
2146 | CPU_BASED_CR3_LOAD_EXITING | | 2199 | CPU_BASED_CR3_LOAD_EXITING | |
2147 | CPU_BASED_INVLPG_EXITING; | 2200 | CPU_BASED_INVLPG_EXITING; |
@@ -2154,7 +2207,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx) | |||
2154 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | 2207 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; |
2155 | if (vmx->vpid == 0) | 2208 | if (vmx->vpid == 0) |
2156 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | 2209 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; |
2157 | if (!vm_need_ept()) | 2210 | if (!enable_ept) |
2158 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | 2211 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; |
2159 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); | 2212 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
2160 | } | 2213 | } |
@@ -2273,7 +2326,7 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) | |||
2273 | goto out; | 2326 | goto out; |
2274 | } | 2327 | } |
2275 | 2328 | ||
2276 | vmx->vcpu.arch.rmode.active = 0; | 2329 | vmx->vcpu.arch.rmode.vm86_active = 0; |
2277 | 2330 | ||
2278 | vmx->soft_vnmi_blocked = 0; | 2331 | vmx->soft_vnmi_blocked = 0; |
2279 | 2332 | ||
@@ -2402,14 +2455,16 @@ static void enable_nmi_window(struct kvm_vcpu *vcpu) | |||
2402 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | 2455 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); |
2403 | } | 2456 | } |
2404 | 2457 | ||
2405 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) | 2458 | static void vmx_inject_irq(struct kvm_vcpu *vcpu) |
2406 | { | 2459 | { |
2407 | struct vcpu_vmx *vmx = to_vmx(vcpu); | 2460 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2461 | uint32_t intr; | ||
2462 | int irq = vcpu->arch.interrupt.nr; | ||
2408 | 2463 | ||
2409 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); | 2464 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
2410 | 2465 | ||
2411 | ++vcpu->stat.irq_injections; | 2466 | ++vcpu->stat.irq_injections; |
2412 | if (vcpu->arch.rmode.active) { | 2467 | if (vcpu->arch.rmode.vm86_active) { |
2413 | vmx->rmode.irq.pending = true; | 2468 | vmx->rmode.irq.pending = true; |
2414 | vmx->rmode.irq.vector = irq; | 2469 | vmx->rmode.irq.vector = irq; |
2415 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | 2470 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
@@ -2419,8 +2474,14 @@ static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) | |||
2419 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | 2474 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); |
2420 | return; | 2475 | return; |
2421 | } | 2476 | } |
2422 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | 2477 | intr = irq | INTR_INFO_VALID_MASK; |
2423 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | 2478 | if (vcpu->arch.interrupt.soft) { |
2479 | intr |= INTR_TYPE_SOFT_INTR; | ||
2480 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, | ||
2481 | vmx->vcpu.arch.event_exit_inst_len); | ||
2482 | } else | ||
2483 | intr |= INTR_TYPE_EXT_INTR; | ||
2484 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); | ||
2424 | } | 2485 | } |
2425 | 2486 | ||
2426 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) | 2487 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
@@ -2441,7 +2502,7 @@ static void vmx_inject_nmi(struct kvm_vcpu *vcpu) | |||
2441 | } | 2502 | } |
2442 | 2503 | ||
2443 | ++vcpu->stat.nmi_injections; | 2504 | ++vcpu->stat.nmi_injections; |
2444 | if (vcpu->arch.rmode.active) { | 2505 | if (vcpu->arch.rmode.vm86_active) { |
2445 | vmx->rmode.irq.pending = true; | 2506 | vmx->rmode.irq.pending = true; |
2446 | vmx->rmode.irq.vector = NMI_VECTOR; | 2507 | vmx->rmode.irq.vector = NMI_VECTOR; |
2447 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | 2508 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
@@ -2456,76 +2517,21 @@ static void vmx_inject_nmi(struct kvm_vcpu *vcpu) | |||
2456 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | 2517 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); |
2457 | } | 2518 | } |
2458 | 2519 | ||
2459 | static void vmx_update_window_states(struct kvm_vcpu *vcpu) | 2520 | static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) |
2460 | { | 2521 | { |
2461 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | ||
2462 | |||
2463 | vcpu->arch.nmi_window_open = | ||
2464 | !(guest_intr & (GUEST_INTR_STATE_STI | | ||
2465 | GUEST_INTR_STATE_MOV_SS | | ||
2466 | GUEST_INTR_STATE_NMI)); | ||
2467 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) | 2522 | if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked) |
2468 | vcpu->arch.nmi_window_open = 0; | 2523 | return 0; |
2469 | |||
2470 | vcpu->arch.interrupt_window_open = | ||
2471 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && | ||
2472 | !(guest_intr & (GUEST_INTR_STATE_STI | | ||
2473 | GUEST_INTR_STATE_MOV_SS))); | ||
2474 | } | ||
2475 | |||
2476 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) | ||
2477 | { | ||
2478 | int word_index = __ffs(vcpu->arch.irq_summary); | ||
2479 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | ||
2480 | int irq = word_index * BITS_PER_LONG + bit_index; | ||
2481 | 2524 | ||
2482 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); | 2525 | return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
2483 | if (!vcpu->arch.irq_pending[word_index]) | 2526 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS | |
2484 | clear_bit(word_index, &vcpu->arch.irq_summary); | 2527 | GUEST_INTR_STATE_NMI)); |
2485 | kvm_queue_interrupt(vcpu, irq); | ||
2486 | } | 2528 | } |
2487 | 2529 | ||
2488 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | 2530 | static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) |
2489 | struct kvm_run *kvm_run) | ||
2490 | { | 2531 | { |
2491 | vmx_update_window_states(vcpu); | 2532 | return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2492 | 2533 | !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & | |
2493 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | 2534 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); |
2494 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | ||
2495 | GUEST_INTR_STATE_STI | | ||
2496 | GUEST_INTR_STATE_MOV_SS); | ||
2497 | |||
2498 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { | ||
2499 | if (vcpu->arch.interrupt.pending) { | ||
2500 | enable_nmi_window(vcpu); | ||
2501 | } else if (vcpu->arch.nmi_window_open) { | ||
2502 | vcpu->arch.nmi_pending = false; | ||
2503 | vcpu->arch.nmi_injected = true; | ||
2504 | } else { | ||
2505 | enable_nmi_window(vcpu); | ||
2506 | return; | ||
2507 | } | ||
2508 | } | ||
2509 | if (vcpu->arch.nmi_injected) { | ||
2510 | vmx_inject_nmi(vcpu); | ||
2511 | if (vcpu->arch.nmi_pending) | ||
2512 | enable_nmi_window(vcpu); | ||
2513 | else if (vcpu->arch.irq_summary | ||
2514 | || kvm_run->request_interrupt_window) | ||
2515 | enable_irq_window(vcpu); | ||
2516 | return; | ||
2517 | } | ||
2518 | |||
2519 | if (vcpu->arch.interrupt_window_open) { | ||
2520 | if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending) | ||
2521 | kvm_do_inject_irq(vcpu); | ||
2522 | |||
2523 | if (vcpu->arch.interrupt.pending) | ||
2524 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | ||
2525 | } | ||
2526 | if (!vcpu->arch.interrupt_window_open && | ||
2527 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | ||
2528 | enable_irq_window(vcpu); | ||
2529 | } | 2535 | } |
2530 | 2536 | ||
2531 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) | 2537 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
@@ -2585,6 +2591,31 @@ static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |||
2585 | return 0; | 2591 | return 0; |
2586 | } | 2592 | } |
2587 | 2593 | ||
2594 | /* | ||
2595 | * Trigger machine check on the host. We assume all the MSRs are already set up | ||
2596 | * by the CPU and that we still run on the same CPU as the MCE occurred on. | ||
2597 | * We pass a fake environment to the machine check handler because we want | ||
2598 | * the guest to be always treated like user space, no matter what context | ||
2599 | * it used internally. | ||
2600 | */ | ||
2601 | static void kvm_machine_check(void) | ||
2602 | { | ||
2603 | #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) | ||
2604 | struct pt_regs regs = { | ||
2605 | .cs = 3, /* Fake ring 3 no matter what the guest ran on */ | ||
2606 | .flags = X86_EFLAGS_IF, | ||
2607 | }; | ||
2608 | |||
2609 | do_machine_check(®s, 0); | ||
2610 | #endif | ||
2611 | } | ||
2612 | |||
2613 | static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | ||
2614 | { | ||
2615 | /* already handled by vcpu_run */ | ||
2616 | return 1; | ||
2617 | } | ||
2618 | |||
2588 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | 2619 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2589 | { | 2620 | { |
2590 | struct vcpu_vmx *vmx = to_vmx(vcpu); | 2621 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
@@ -2596,17 +2627,14 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
2596 | vect_info = vmx->idt_vectoring_info; | 2627 | vect_info = vmx->idt_vectoring_info; |
2597 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | 2628 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2598 | 2629 | ||
2630 | if (is_machine_check(intr_info)) | ||
2631 | return handle_machine_check(vcpu, kvm_run); | ||
2632 | |||
2599 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | 2633 | if ((vect_info & VECTORING_INFO_VALID_MASK) && |
2600 | !is_page_fault(intr_info)) | 2634 | !is_page_fault(intr_info)) |
2601 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " | 2635 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
2602 | "intr info 0x%x\n", __func__, vect_info, intr_info); | 2636 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
2603 | 2637 | ||
2604 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { | ||
2605 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; | ||
2606 | set_bit(irq, vcpu->arch.irq_pending); | ||
2607 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | ||
2608 | } | ||
2609 | |||
2610 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) | 2638 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR) |
2611 | return 1; /* already handled by vmx_vcpu_run() */ | 2639 | return 1; /* already handled by vmx_vcpu_run() */ |
2612 | 2640 | ||
@@ -2628,17 +2656,17 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
2628 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); | 2656 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2629 | if (is_page_fault(intr_info)) { | 2657 | if (is_page_fault(intr_info)) { |
2630 | /* EPT won't cause page fault directly */ | 2658 | /* EPT won't cause page fault directly */ |
2631 | if (vm_need_ept()) | 2659 | if (enable_ept) |
2632 | BUG(); | 2660 | BUG(); |
2633 | cr2 = vmcs_readl(EXIT_QUALIFICATION); | 2661 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
2634 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, | 2662 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2635 | (u32)((u64)cr2 >> 32), handler); | 2663 | (u32)((u64)cr2 >> 32), handler); |
2636 | if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending) | 2664 | if (kvm_event_needs_reinjection(vcpu)) |
2637 | kvm_mmu_unprotect_page_virt(vcpu, cr2); | 2665 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
2638 | return kvm_mmu_page_fault(vcpu, cr2, error_code); | 2666 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
2639 | } | 2667 | } |
2640 | 2668 | ||
2641 | if (vcpu->arch.rmode.active && | 2669 | if (vcpu->arch.rmode.vm86_active && |
2642 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, | 2670 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
2643 | error_code)) { | 2671 | error_code)) { |
2644 | if (vcpu->arch.halt_request) { | 2672 | if (vcpu->arch.halt_request) { |
@@ -2753,13 +2781,18 @@ static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
2753 | kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg)); | 2781 | kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg)); |
2754 | skip_emulated_instruction(vcpu); | 2782 | skip_emulated_instruction(vcpu); |
2755 | return 1; | 2783 | return 1; |
2756 | case 8: | 2784 | case 8: { |
2757 | kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg)); | 2785 | u8 cr8_prev = kvm_get_cr8(vcpu); |
2758 | skip_emulated_instruction(vcpu); | 2786 | u8 cr8 = kvm_register_read(vcpu, reg); |
2759 | if (irqchip_in_kernel(vcpu->kvm)) | 2787 | kvm_set_cr8(vcpu, cr8); |
2760 | return 1; | 2788 | skip_emulated_instruction(vcpu); |
2761 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | 2789 | if (irqchip_in_kernel(vcpu->kvm)) |
2762 | return 0; | 2790 | return 1; |
2791 | if (cr8_prev <= cr8) | ||
2792 | return 1; | ||
2793 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; | ||
2794 | return 0; | ||
2795 | } | ||
2763 | }; | 2796 | }; |
2764 | break; | 2797 | break; |
2765 | case 2: /* clts */ | 2798 | case 2: /* clts */ |
@@ -2957,8 +2990,9 @@ static int handle_interrupt_window(struct kvm_vcpu *vcpu, | |||
2957 | * If the user space waits to inject interrupts, exit as soon as | 2990 | * If the user space waits to inject interrupts, exit as soon as |
2958 | * possible | 2991 | * possible |
2959 | */ | 2992 | */ |
2960 | if (kvm_run->request_interrupt_window && | 2993 | if (!irqchip_in_kernel(vcpu->kvm) && |
2961 | !vcpu->arch.irq_summary) { | 2994 | kvm_run->request_interrupt_window && |
2995 | !kvm_cpu_has_interrupt(vcpu)) { | ||
2962 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | 2996 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
2963 | return 0; | 2997 | return 0; |
2964 | } | 2998 | } |
@@ -2980,7 +3014,7 @@ static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
2980 | 3014 | ||
2981 | static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | 3015 | static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2982 | { | 3016 | { |
2983 | u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | 3017 | unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
2984 | 3018 | ||
2985 | kvm_mmu_invlpg(vcpu, exit_qualification); | 3019 | kvm_mmu_invlpg(vcpu, exit_qualification); |
2986 | skip_emulated_instruction(vcpu); | 3020 | skip_emulated_instruction(vcpu); |
@@ -2996,11 +3030,11 @@ static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
2996 | 3030 | ||
2997 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | 3031 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2998 | { | 3032 | { |
2999 | u64 exit_qualification; | 3033 | unsigned long exit_qualification; |
3000 | enum emulation_result er; | 3034 | enum emulation_result er; |
3001 | unsigned long offset; | 3035 | unsigned long offset; |
3002 | 3036 | ||
3003 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | 3037 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
3004 | offset = exit_qualification & 0xffful; | 3038 | offset = exit_qualification & 0xffful; |
3005 | 3039 | ||
3006 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | 3040 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); |
@@ -3019,22 +3053,41 @@ static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
3019 | struct vcpu_vmx *vmx = to_vmx(vcpu); | 3053 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3020 | unsigned long exit_qualification; | 3054 | unsigned long exit_qualification; |
3021 | u16 tss_selector; | 3055 | u16 tss_selector; |
3022 | int reason; | 3056 | int reason, type, idt_v; |
3057 | |||
3058 | idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); | ||
3059 | type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); | ||
3023 | 3060 | ||
3024 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | 3061 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
3025 | 3062 | ||
3026 | reason = (u32)exit_qualification >> 30; | 3063 | reason = (u32)exit_qualification >> 30; |
3027 | if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected && | 3064 | if (reason == TASK_SWITCH_GATE && idt_v) { |
3028 | (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && | 3065 | switch (type) { |
3029 | (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK) | 3066 | case INTR_TYPE_NMI_INTR: |
3030 | == INTR_TYPE_NMI_INTR) { | 3067 | vcpu->arch.nmi_injected = false; |
3031 | vcpu->arch.nmi_injected = false; | 3068 | if (cpu_has_virtual_nmis()) |
3032 | if (cpu_has_virtual_nmis()) | 3069 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
3033 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | 3070 | GUEST_INTR_STATE_NMI); |
3034 | GUEST_INTR_STATE_NMI); | 3071 | break; |
3072 | case INTR_TYPE_EXT_INTR: | ||
3073 | case INTR_TYPE_SOFT_INTR: | ||
3074 | kvm_clear_interrupt_queue(vcpu); | ||
3075 | break; | ||
3076 | case INTR_TYPE_HARD_EXCEPTION: | ||
3077 | case INTR_TYPE_SOFT_EXCEPTION: | ||
3078 | kvm_clear_exception_queue(vcpu); | ||
3079 | break; | ||
3080 | default: | ||
3081 | break; | ||
3082 | } | ||
3035 | } | 3083 | } |
3036 | tss_selector = exit_qualification; | 3084 | tss_selector = exit_qualification; |
3037 | 3085 | ||
3086 | if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && | ||
3087 | type != INTR_TYPE_EXT_INTR && | ||
3088 | type != INTR_TYPE_NMI_INTR)) | ||
3089 | skip_emulated_instruction(vcpu); | ||
3090 | |||
3038 | if (!kvm_task_switch(vcpu, tss_selector, reason)) | 3091 | if (!kvm_task_switch(vcpu, tss_selector, reason)) |
3039 | return 0; | 3092 | return 0; |
3040 | 3093 | ||
@@ -3051,11 +3104,11 @@ static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
3051 | 3104 | ||
3052 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | 3105 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3053 | { | 3106 | { |
3054 | u64 exit_qualification; | 3107 | unsigned long exit_qualification; |
3055 | gpa_t gpa; | 3108 | gpa_t gpa; |
3056 | int gla_validity; | 3109 | int gla_validity; |
3057 | 3110 | ||
3058 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | 3111 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
3059 | 3112 | ||
3060 | if (exit_qualification & (1 << 6)) { | 3113 | if (exit_qualification & (1 << 6)) { |
3061 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | 3114 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); |
@@ -3067,7 +3120,7 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
3067 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | 3120 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); |
3068 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | 3121 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", |
3069 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | 3122 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), |
3070 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | 3123 | vmcs_readl(GUEST_LINEAR_ADDRESS)); |
3071 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | 3124 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", |
3072 | (long unsigned int)exit_qualification); | 3125 | (long unsigned int)exit_qualification); |
3073 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | 3126 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
@@ -3150,6 +3203,7 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |||
3150 | [EXIT_REASON_WBINVD] = handle_wbinvd, | 3203 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
3151 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, | 3204 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
3152 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, | 3205 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
3206 | [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, | ||
3153 | }; | 3207 | }; |
3154 | 3208 | ||
3155 | static const int kvm_vmx_max_exit_handlers = | 3209 | static const int kvm_vmx_max_exit_handlers = |
@@ -3159,10 +3213,10 @@ static const int kvm_vmx_max_exit_handlers = | |||
3159 | * The guest has exited. See if we can fix it or if we need userspace | 3213 | * The guest has exited. See if we can fix it or if we need userspace |
3160 | * assistance. | 3214 | * assistance. |
3161 | */ | 3215 | */ |
3162 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | 3216 | static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
3163 | { | 3217 | { |
3164 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); | ||
3165 | struct vcpu_vmx *vmx = to_vmx(vcpu); | 3218 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3219 | u32 exit_reason = vmx->exit_reason; | ||
3166 | u32 vectoring_info = vmx->idt_vectoring_info; | 3220 | u32 vectoring_info = vmx->idt_vectoring_info; |
3167 | 3221 | ||
3168 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu), | 3222 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu), |
@@ -3178,7 +3232,7 @@ static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |||
3178 | 3232 | ||
3179 | /* Access CR3 don't cause VMExit in paging mode, so we need | 3233 | /* Access CR3 don't cause VMExit in paging mode, so we need |
3180 | * to sync with guest real CR3. */ | 3234 | * to sync with guest real CR3. */ |
3181 | if (vm_need_ept() && is_paging(vcpu)) { | 3235 | if (enable_ept && is_paging(vcpu)) { |
3182 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | 3236 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); |
3183 | ept_load_pdptrs(vcpu); | 3237 | ept_load_pdptrs(vcpu); |
3184 | } | 3238 | } |
@@ -3199,9 +3253,8 @@ static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |||
3199 | __func__, vectoring_info, exit_reason); | 3253 | __func__, vectoring_info, exit_reason); |
3200 | 3254 | ||
3201 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { | 3255 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) { |
3202 | if (vcpu->arch.interrupt_window_open) { | 3256 | if (vmx_interrupt_allowed(vcpu)) { |
3203 | vmx->soft_vnmi_blocked = 0; | 3257 | vmx->soft_vnmi_blocked = 0; |
3204 | vcpu->arch.nmi_window_open = 1; | ||
3205 | } else if (vmx->vnmi_blocked_time > 1000000000LL && | 3258 | } else if (vmx->vnmi_blocked_time > 1000000000LL && |
3206 | vcpu->arch.nmi_pending) { | 3259 | vcpu->arch.nmi_pending) { |
3207 | /* | 3260 | /* |
@@ -3214,7 +3267,6 @@ static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |||
3214 | "state on VCPU %d after 1 s timeout\n", | 3267 | "state on VCPU %d after 1 s timeout\n", |
3215 | __func__, vcpu->vcpu_id); | 3268 | __func__, vcpu->vcpu_id); |
3216 | vmx->soft_vnmi_blocked = 0; | 3269 | vmx->soft_vnmi_blocked = 0; |
3217 | vmx->vcpu.arch.nmi_window_open = 1; | ||
3218 | } | 3270 | } |
3219 | } | 3271 | } |
3220 | 3272 | ||
@@ -3228,122 +3280,107 @@ static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |||
3228 | return 0; | 3280 | return 0; |
3229 | } | 3281 | } |
3230 | 3282 | ||
3231 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) | 3283 | static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) |
3232 | { | 3284 | { |
3233 | int max_irr, tpr; | 3285 | if (irr == -1 || tpr < irr) { |
3234 | |||
3235 | if (!vm_need_tpr_shadow(vcpu->kvm)) | ||
3236 | return; | ||
3237 | |||
3238 | if (!kvm_lapic_enabled(vcpu) || | ||
3239 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | ||
3240 | vmcs_write32(TPR_THRESHOLD, 0); | 3286 | vmcs_write32(TPR_THRESHOLD, 0); |
3241 | return; | 3287 | return; |
3242 | } | 3288 | } |
3243 | 3289 | ||
3244 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | 3290 | vmcs_write32(TPR_THRESHOLD, irr); |
3245 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | ||
3246 | } | 3291 | } |
3247 | 3292 | ||
3248 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) | 3293 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
3249 | { | 3294 | { |
3250 | u32 exit_intr_info; | 3295 | u32 exit_intr_info; |
3251 | u32 idt_vectoring_info; | 3296 | u32 idt_vectoring_info = vmx->idt_vectoring_info; |
3252 | bool unblock_nmi; | 3297 | bool unblock_nmi; |
3253 | u8 vector; | 3298 | u8 vector; |
3254 | int type; | 3299 | int type; |
3255 | bool idtv_info_valid; | 3300 | bool idtv_info_valid; |
3256 | u32 error; | ||
3257 | 3301 | ||
3258 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | 3302 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
3303 | |||
3304 | vmx->exit_reason = vmcs_read32(VM_EXIT_REASON); | ||
3305 | |||
3306 | /* Handle machine checks before interrupts are enabled */ | ||
3307 | if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) | ||
3308 | || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI | ||
3309 | && is_machine_check(exit_intr_info))) | ||
3310 | kvm_machine_check(); | ||
3311 | |||
3312 | /* We need to handle NMIs before interrupts are enabled */ | ||
3313 | if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && | ||
3314 | (exit_intr_info & INTR_INFO_VALID_MASK)) { | ||
3315 | KVMTRACE_0D(NMI, &vmx->vcpu, handler); | ||
3316 | asm("int $2"); | ||
3317 | } | ||
3318 | |||
3319 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | ||
3320 | |||
3259 | if (cpu_has_virtual_nmis()) { | 3321 | if (cpu_has_virtual_nmis()) { |
3260 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | 3322 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; |
3261 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | 3323 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; |
3262 | /* | 3324 | /* |
3263 | * SDM 3: 25.7.1.2 | 3325 | * SDM 3: 27.7.1.2 (September 2008) |
3264 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | 3326 | * Re-set bit "block by NMI" before VM entry if vmexit caused by |
3265 | * a guest IRET fault. | 3327 | * a guest IRET fault. |
3328 | * SDM 3: 23.2.2 (September 2008) | ||
3329 | * Bit 12 is undefined in any of the following cases: | ||
3330 | * If the VM exit sets the valid bit in the IDT-vectoring | ||
3331 | * information field. | ||
3332 | * If the VM exit is due to a double fault. | ||
3266 | */ | 3333 | */ |
3267 | if (unblock_nmi && vector != DF_VECTOR) | 3334 | if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && |
3335 | vector != DF_VECTOR && !idtv_info_valid) | ||
3268 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | 3336 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, |
3269 | GUEST_INTR_STATE_NMI); | 3337 | GUEST_INTR_STATE_NMI); |
3270 | } else if (unlikely(vmx->soft_vnmi_blocked)) | 3338 | } else if (unlikely(vmx->soft_vnmi_blocked)) |
3271 | vmx->vnmi_blocked_time += | 3339 | vmx->vnmi_blocked_time += |
3272 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); | 3340 | ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time)); |
3273 | 3341 | ||
3274 | idt_vectoring_info = vmx->idt_vectoring_info; | 3342 | vmx->vcpu.arch.nmi_injected = false; |
3275 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | 3343 | kvm_clear_exception_queue(&vmx->vcpu); |
3344 | kvm_clear_interrupt_queue(&vmx->vcpu); | ||
3345 | |||
3346 | if (!idtv_info_valid) | ||
3347 | return; | ||
3348 | |||
3276 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; | 3349 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; |
3277 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | 3350 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; |
3278 | if (vmx->vcpu.arch.nmi_injected) { | 3351 | |
3352 | switch (type) { | ||
3353 | case INTR_TYPE_NMI_INTR: | ||
3354 | vmx->vcpu.arch.nmi_injected = true; | ||
3279 | /* | 3355 | /* |
3280 | * SDM 3: 25.7.1.2 | 3356 | * SDM 3: 27.7.1.2 (September 2008) |
3281 | * Clear bit "block by NMI" before VM entry if a NMI delivery | 3357 | * Clear bit "block by NMI" before VM entry if a NMI |
3282 | * faulted. | 3358 | * delivery faulted. |
3283 | */ | 3359 | */ |
3284 | if (idtv_info_valid && type == INTR_TYPE_NMI_INTR) | 3360 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, |
3285 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | 3361 | GUEST_INTR_STATE_NMI); |
3286 | GUEST_INTR_STATE_NMI); | 3362 | break; |
3287 | else | 3363 | case INTR_TYPE_SOFT_EXCEPTION: |
3288 | vmx->vcpu.arch.nmi_injected = false; | 3364 | vmx->vcpu.arch.event_exit_inst_len = |
3289 | } | 3365 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
3290 | kvm_clear_exception_queue(&vmx->vcpu); | 3366 | /* fall through */ |
3291 | if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION || | 3367 | case INTR_TYPE_HARD_EXCEPTION: |
3292 | type == INTR_TYPE_SOFT_EXCEPTION)) { | ||
3293 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { | 3368 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { |
3294 | error = vmcs_read32(IDT_VECTORING_ERROR_CODE); | 3369 | u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE); |
3295 | kvm_queue_exception_e(&vmx->vcpu, vector, error); | 3370 | kvm_queue_exception_e(&vmx->vcpu, vector, err); |
3296 | } else | 3371 | } else |
3297 | kvm_queue_exception(&vmx->vcpu, vector); | 3372 | kvm_queue_exception(&vmx->vcpu, vector); |
3298 | vmx->idt_vectoring_info = 0; | 3373 | break; |
3299 | } | 3374 | case INTR_TYPE_SOFT_INTR: |
3300 | kvm_clear_interrupt_queue(&vmx->vcpu); | 3375 | vmx->vcpu.arch.event_exit_inst_len = |
3301 | if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) { | 3376 | vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
3302 | kvm_queue_interrupt(&vmx->vcpu, vector); | 3377 | /* fall through */ |
3303 | vmx->idt_vectoring_info = 0; | 3378 | case INTR_TYPE_EXT_INTR: |
3304 | } | 3379 | kvm_queue_interrupt(&vmx->vcpu, vector, |
3305 | } | 3380 | type == INTR_TYPE_SOFT_INTR); |
3306 | 3381 | break; | |
3307 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) | 3382 | default: |
3308 | { | 3383 | break; |
3309 | update_tpr_threshold(vcpu); | ||
3310 | |||
3311 | vmx_update_window_states(vcpu); | ||
3312 | |||
3313 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) | ||
3314 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | ||
3315 | GUEST_INTR_STATE_STI | | ||
3316 | GUEST_INTR_STATE_MOV_SS); | ||
3317 | |||
3318 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { | ||
3319 | if (vcpu->arch.interrupt.pending) { | ||
3320 | enable_nmi_window(vcpu); | ||
3321 | } else if (vcpu->arch.nmi_window_open) { | ||
3322 | vcpu->arch.nmi_pending = false; | ||
3323 | vcpu->arch.nmi_injected = true; | ||
3324 | } else { | ||
3325 | enable_nmi_window(vcpu); | ||
3326 | return; | ||
3327 | } | ||
3328 | } | ||
3329 | if (vcpu->arch.nmi_injected) { | ||
3330 | vmx_inject_nmi(vcpu); | ||
3331 | if (vcpu->arch.nmi_pending) | ||
3332 | enable_nmi_window(vcpu); | ||
3333 | else if (kvm_cpu_has_interrupt(vcpu)) | ||
3334 | enable_irq_window(vcpu); | ||
3335 | return; | ||
3336 | } | ||
3337 | if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) { | ||
3338 | if (vcpu->arch.interrupt_window_open) | ||
3339 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu)); | ||
3340 | else | ||
3341 | enable_irq_window(vcpu); | ||
3342 | } | ||
3343 | if (vcpu->arch.interrupt.pending) { | ||
3344 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | ||
3345 | if (kvm_cpu_has_interrupt(vcpu)) | ||
3346 | enable_irq_window(vcpu); | ||
3347 | } | 3384 | } |
3348 | } | 3385 | } |
3349 | 3386 | ||
@@ -3381,7 +3418,6 @@ static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |||
3381 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | 3418 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
3382 | { | 3419 | { |
3383 | struct vcpu_vmx *vmx = to_vmx(vcpu); | 3420 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3384 | u32 intr_info; | ||
3385 | 3421 | ||
3386 | /* Record the guest's net vcpu time for enforced NMI injections. */ | 3422 | /* Record the guest's net vcpu time for enforced NMI injections. */ |
3387 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) | 3423 | if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) |
@@ -3505,20 +3541,9 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |||
3505 | if (vmx->rmode.irq.pending) | 3541 | if (vmx->rmode.irq.pending) |
3506 | fixup_rmode_irq(vmx); | 3542 | fixup_rmode_irq(vmx); |
3507 | 3543 | ||
3508 | vmx_update_window_states(vcpu); | ||
3509 | |||
3510 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); | 3544 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
3511 | vmx->launched = 1; | 3545 | vmx->launched = 1; |
3512 | 3546 | ||
3513 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | ||
3514 | |||
3515 | /* We need to handle NMIs before interrupts are enabled */ | ||
3516 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR && | ||
3517 | (intr_info & INTR_INFO_VALID_MASK)) { | ||
3518 | KVMTRACE_0D(NMI, vcpu, handler); | ||
3519 | asm("int $2"); | ||
3520 | } | ||
3521 | |||
3522 | vmx_complete_interrupts(vmx); | 3547 | vmx_complete_interrupts(vmx); |
3523 | } | 3548 | } |
3524 | 3549 | ||
@@ -3593,7 +3618,7 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) | |||
3593 | if (alloc_apic_access_page(kvm) != 0) | 3618 | if (alloc_apic_access_page(kvm) != 0) |
3594 | goto free_vmcs; | 3619 | goto free_vmcs; |
3595 | 3620 | ||
3596 | if (vm_need_ept()) | 3621 | if (enable_ept) |
3597 | if (alloc_identity_pagetable(kvm) != 0) | 3622 | if (alloc_identity_pagetable(kvm) != 0) |
3598 | goto free_vmcs; | 3623 | goto free_vmcs; |
3599 | 3624 | ||
@@ -3631,9 +3656,32 @@ static int get_ept_level(void) | |||
3631 | return VMX_EPT_DEFAULT_GAW + 1; | 3656 | return VMX_EPT_DEFAULT_GAW + 1; |
3632 | } | 3657 | } |
3633 | 3658 | ||
3634 | static int vmx_get_mt_mask_shift(void) | 3659 | static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) |
3635 | { | 3660 | { |
3636 | return VMX_EPT_MT_EPTE_SHIFT; | 3661 | u64 ret; |
3662 | |||
3663 | /* For VT-d and EPT combination | ||
3664 | * 1. MMIO: always map as UC | ||
3665 | * 2. EPT with VT-d: | ||
3666 | * a. VT-d without snooping control feature: can't guarantee the | ||
3667 | * result, try to trust guest. | ||
3668 | * b. VT-d with snooping control feature: snooping control feature of | ||
3669 | * VT-d engine can guarantee the cache correctness. Just set it | ||
3670 | * to WB to keep consistent with host. So the same as item 3. | ||
3671 | * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep | ||
3672 | * consistent with host MTRR | ||
3673 | */ | ||
3674 | if (is_mmio) | ||
3675 | ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT; | ||
3676 | else if (vcpu->kvm->arch.iommu_domain && | ||
3677 | !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY)) | ||
3678 | ret = kvm_get_guest_memory_type(vcpu, gfn) << | ||
3679 | VMX_EPT_MT_EPTE_SHIFT; | ||
3680 | else | ||
3681 | ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) | ||
3682 | | VMX_EPT_IGMT_BIT; | ||
3683 | |||
3684 | return ret; | ||
3637 | } | 3685 | } |
3638 | 3686 | ||
3639 | static struct kvm_x86_ops vmx_x86_ops = { | 3687 | static struct kvm_x86_ops vmx_x86_ops = { |
@@ -3644,7 +3692,7 @@ static struct kvm_x86_ops vmx_x86_ops = { | |||
3644 | .check_processor_compatibility = vmx_check_processor_compat, | 3692 | .check_processor_compatibility = vmx_check_processor_compat, |
3645 | .hardware_enable = hardware_enable, | 3693 | .hardware_enable = hardware_enable, |
3646 | .hardware_disable = hardware_disable, | 3694 | .hardware_disable = hardware_disable, |
3647 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, | 3695 | .cpu_has_accelerated_tpr = report_flexpriority, |
3648 | 3696 | ||
3649 | .vcpu_create = vmx_create_vcpu, | 3697 | .vcpu_create = vmx_create_vcpu, |
3650 | .vcpu_free = vmx_free_vcpu, | 3698 | .vcpu_free = vmx_free_vcpu, |
@@ -3678,78 +3726,82 @@ static struct kvm_x86_ops vmx_x86_ops = { | |||
3678 | .tlb_flush = vmx_flush_tlb, | 3726 | .tlb_flush = vmx_flush_tlb, |
3679 | 3727 | ||
3680 | .run = vmx_vcpu_run, | 3728 | .run = vmx_vcpu_run, |
3681 | .handle_exit = kvm_handle_exit, | 3729 | .handle_exit = vmx_handle_exit, |
3682 | .skip_emulated_instruction = skip_emulated_instruction, | 3730 | .skip_emulated_instruction = skip_emulated_instruction, |
3731 | .set_interrupt_shadow = vmx_set_interrupt_shadow, | ||
3732 | .get_interrupt_shadow = vmx_get_interrupt_shadow, | ||
3683 | .patch_hypercall = vmx_patch_hypercall, | 3733 | .patch_hypercall = vmx_patch_hypercall, |
3684 | .get_irq = vmx_get_irq, | ||
3685 | .set_irq = vmx_inject_irq, | 3734 | .set_irq = vmx_inject_irq, |
3735 | .set_nmi = vmx_inject_nmi, | ||
3686 | .queue_exception = vmx_queue_exception, | 3736 | .queue_exception = vmx_queue_exception, |
3687 | .exception_injected = vmx_exception_injected, | 3737 | .interrupt_allowed = vmx_interrupt_allowed, |
3688 | .inject_pending_irq = vmx_intr_assist, | 3738 | .nmi_allowed = vmx_nmi_allowed, |
3689 | .inject_pending_vectors = do_interrupt_requests, | 3739 | .enable_nmi_window = enable_nmi_window, |
3740 | .enable_irq_window = enable_irq_window, | ||
3741 | .update_cr8_intercept = update_cr8_intercept, | ||
3690 | 3742 | ||
3691 | .set_tss_addr = vmx_set_tss_addr, | 3743 | .set_tss_addr = vmx_set_tss_addr, |
3692 | .get_tdp_level = get_ept_level, | 3744 | .get_tdp_level = get_ept_level, |
3693 | .get_mt_mask_shift = vmx_get_mt_mask_shift, | 3745 | .get_mt_mask = vmx_get_mt_mask, |
3694 | }; | 3746 | }; |
3695 | 3747 | ||
3696 | static int __init vmx_init(void) | 3748 | static int __init vmx_init(void) |
3697 | { | 3749 | { |
3698 | void *va; | ||
3699 | int r; | 3750 | int r; |
3700 | 3751 | ||
3701 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | 3752 | vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL); |
3702 | if (!vmx_io_bitmap_a) | 3753 | if (!vmx_io_bitmap_a) |
3703 | return -ENOMEM; | 3754 | return -ENOMEM; |
3704 | 3755 | ||
3705 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | 3756 | vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL); |
3706 | if (!vmx_io_bitmap_b) { | 3757 | if (!vmx_io_bitmap_b) { |
3707 | r = -ENOMEM; | 3758 | r = -ENOMEM; |
3708 | goto out; | 3759 | goto out; |
3709 | } | 3760 | } |
3710 | 3761 | ||
3711 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | 3762 | vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL); |
3712 | if (!vmx_msr_bitmap) { | 3763 | if (!vmx_msr_bitmap_legacy) { |
3713 | r = -ENOMEM; | 3764 | r = -ENOMEM; |
3714 | goto out1; | 3765 | goto out1; |
3715 | } | 3766 | } |
3716 | 3767 | ||
3768 | vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL); | ||
3769 | if (!vmx_msr_bitmap_longmode) { | ||
3770 | r = -ENOMEM; | ||
3771 | goto out2; | ||
3772 | } | ||
3773 | |||
3717 | /* | 3774 | /* |
3718 | * Allow direct access to the PC debug port (it is often used for I/O | 3775 | * Allow direct access to the PC debug port (it is often used for I/O |
3719 | * delays, but the vmexits simply slow things down). | 3776 | * delays, but the vmexits simply slow things down). |
3720 | */ | 3777 | */ |
3721 | va = kmap(vmx_io_bitmap_a); | 3778 | memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE); |
3722 | memset(va, 0xff, PAGE_SIZE); | 3779 | clear_bit(0x80, vmx_io_bitmap_a); |
3723 | clear_bit(0x80, va); | ||
3724 | kunmap(vmx_io_bitmap_a); | ||
3725 | 3780 | ||
3726 | va = kmap(vmx_io_bitmap_b); | 3781 | memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE); |
3727 | memset(va, 0xff, PAGE_SIZE); | ||
3728 | kunmap(vmx_io_bitmap_b); | ||
3729 | 3782 | ||
3730 | va = kmap(vmx_msr_bitmap); | 3783 | memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE); |
3731 | memset(va, 0xff, PAGE_SIZE); | 3784 | memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE); |
3732 | kunmap(vmx_msr_bitmap); | ||
3733 | 3785 | ||
3734 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ | 3786 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
3735 | 3787 | ||
3736 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); | 3788 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
3737 | if (r) | 3789 | if (r) |
3738 | goto out2; | 3790 | goto out3; |
3739 | 3791 | ||
3740 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | 3792 | vmx_disable_intercept_for_msr(MSR_FS_BASE, false); |
3741 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | 3793 | vmx_disable_intercept_for_msr(MSR_GS_BASE, false); |
3742 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | 3794 | vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true); |
3743 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | 3795 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false); |
3744 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | 3796 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false); |
3797 | vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false); | ||
3745 | 3798 | ||
3746 | if (vm_need_ept()) { | 3799 | if (enable_ept) { |
3747 | bypass_guest_pf = 0; | 3800 | bypass_guest_pf = 0; |
3748 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | | 3801 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | |
3749 | VMX_EPT_WRITABLE_MASK); | 3802 | VMX_EPT_WRITABLE_MASK); |
3750 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, | 3803 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
3751 | VMX_EPT_EXECUTABLE_MASK, | 3804 | VMX_EPT_EXECUTABLE_MASK); |
3752 | VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); | ||
3753 | kvm_enable_tdp(); | 3805 | kvm_enable_tdp(); |
3754 | } else | 3806 | } else |
3755 | kvm_disable_tdp(); | 3807 | kvm_disable_tdp(); |
@@ -3761,20 +3813,23 @@ static int __init vmx_init(void) | |||
3761 | 3813 | ||
3762 | return 0; | 3814 | return 0; |
3763 | 3815 | ||
3816 | out3: | ||
3817 | free_page((unsigned long)vmx_msr_bitmap_longmode); | ||
3764 | out2: | 3818 | out2: |
3765 | __free_page(vmx_msr_bitmap); | 3819 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
3766 | out1: | 3820 | out1: |
3767 | __free_page(vmx_io_bitmap_b); | 3821 | free_page((unsigned long)vmx_io_bitmap_b); |
3768 | out: | 3822 | out: |
3769 | __free_page(vmx_io_bitmap_a); | 3823 | free_page((unsigned long)vmx_io_bitmap_a); |
3770 | return r; | 3824 | return r; |
3771 | } | 3825 | } |
3772 | 3826 | ||
3773 | static void __exit vmx_exit(void) | 3827 | static void __exit vmx_exit(void) |
3774 | { | 3828 | { |
3775 | __free_page(vmx_msr_bitmap); | 3829 | free_page((unsigned long)vmx_msr_bitmap_legacy); |
3776 | __free_page(vmx_io_bitmap_b); | 3830 | free_page((unsigned long)vmx_msr_bitmap_longmode); |
3777 | __free_page(vmx_io_bitmap_a); | 3831 | free_page((unsigned long)vmx_io_bitmap_b); |
3832 | free_page((unsigned long)vmx_io_bitmap_a); | ||
3778 | 3833 | ||
3779 | kvm_exit(); | 3834 | kvm_exit(); |
3780 | } | 3835 | } |