1 files changed, 246 insertions, 88 deletions

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index ae99d83f81a3..1ae5ceba7eb2 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -32,8 +32,11 @@
 #include <asm/current.h>
 #include <asm/apicdef.h>
 #include <asm/atomic.h>
+#include <asm/apicdef.h>
 #include "kvm_cache_regs.h"
 #include "irq.h"
+#include "trace.h"
+#include "x86.h"
 
 #ifndef CONFIG_X86_64
 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
@@ -141,6 +144,26 @@ static inline int apic_lvt_nmi_mode(u32 lvt_val)
         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 }
 
+void kvm_apic_set_version(struct kvm_vcpu *vcpu)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        struct kvm_cpuid_entry2 *feat;
+        u32 v = APIC_VERSION;
+
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return;
+
+        feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
+        if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
+                v |= APIC_LVR_DIRECTED_EOI;
+        apic_set_reg(apic, APIC_LVR, v);
+}
+
+static inline int apic_x2apic_mode(struct kvm_lapic *apic)
+{
+        return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
+}
+
 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
@@ -165,36 +188,52 @@ static int find_highest_vector(void *bitmap)
 
 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 {
+        apic->irr_pending = true;
         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 }
 
-static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
+static inline int apic_search_irr(struct kvm_lapic *apic)
 {
-        apic_clear_vector(vec, apic->regs + APIC_IRR);
+        return find_highest_vector(apic->regs + APIC_IRR);
 }
 
 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 {
         int result;
 
-        result = find_highest_vector(apic->regs + APIC_IRR);
+        if (!apic->irr_pending)
+                return -1;
+
+        result = apic_search_irr(apic);
         ASSERT(result == -1 || result >= 16);
 
         return result;
 }
 
+static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
+{
+        apic->irr_pending = false;
+        apic_clear_vector(vec, apic->regs + APIC_IRR);
+        if (apic_search_irr(apic) != -1)
+                apic->irr_pending = true;
+}
+
 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
         int highest_irr;
 
+        /* This may race with setting of irr in __apic_accept_irq() and
+         * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
+         * will cause vmexit immediately and the value will be recalculated
+         * on the next vmentry.
+         */
         if (!apic)
                 return 0;
         highest_irr = apic_find_highest_irr(apic);
 
         return highest_irr;
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 
 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                              int vector, int level, int trig_mode);
@@ -251,7 +290,12 @@ int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 {
         int result = 0;
-        u8 logical_id;
+        u32 logical_id;
+
+        if (apic_x2apic_mode(apic)) {
+                logical_id = apic_get_reg(apic, APIC_LDR);
+                return logical_id & mda;
+        }
 
         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 
@@ -331,6 +375,8 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                         break;
 
                 result = !apic_test_and_set_irr(vector, apic);
+                trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
+                                          trig_mode, vector, !result);
                 if (!result) {
                         if (trig_mode)
                                 apic_debug("level trig mode repeatedly for "
@@ -425,7 +471,11 @@ static void apic_set_eoi(struct kvm_lapic *apic)
                 trigger_mode = IOAPIC_LEVEL_TRIG;
         else
                 trigger_mode = IOAPIC_EDGE_TRIG;
-        kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
+        if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)) {
+                mutex_lock(&apic->vcpu->kvm->irq_lock);
+                kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
+                mutex_unlock(&apic->vcpu->kvm->irq_lock);
+        }
 }
 
 static void apic_send_ipi(struct kvm_lapic *apic)
@@ -440,7 +490,12 @@ static void apic_send_ipi(struct kvm_lapic *apic)
         irq.level = icr_low & APIC_INT_ASSERT;
         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
         irq.shorthand = icr_low & APIC_SHORT_MASK;
-        irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
+        if (apic_x2apic_mode(apic))
+                irq.dest_id = icr_high;
+        else
+                irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
+
+        trace_kvm_apic_ipi(icr_low, irq.dest_id);
 
         apic_debug("icr_high 0x%x, icr_low 0x%x, "
                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
@@ -449,7 +504,9 @@ static void apic_send_ipi(struct kvm_lapic *apic)
                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
                    irq.vector);
 
+        mutex_lock(&apic->vcpu->kvm->irq_lock);
         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
+        mutex_unlock(&apic->vcpu->kvm->irq_lock);
 }
 
 static u32 apic_get_tmcct(struct kvm_lapic *apic)
@@ -495,12 +552,16 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 {
         u32 val = 0;
 
-        KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
-
         if (offset >= LAPIC_MMIO_LENGTH)
                 return 0;
 
         switch (offset) {
+        case APIC_ID:
+                if (apic_x2apic_mode(apic))
+                        val = kvm_apic_id(apic);
+                else
+                        val = kvm_apic_id(apic) << 24;
+                break;
         case APIC_ARBPRI:
                 printk(KERN_WARNING "Access APIC ARBPRI register "
                        "which is for P6\n");
@@ -522,21 +583,35 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
         return val;
 }
 
-static void apic_mmio_read(struct kvm_io_device *this,
-                           gpa_t address, int len, void *data)
+static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
+{
+        return container_of(dev, struct kvm_lapic, dev);
+}
+
+static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
+                void *data)
 {
-        struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
-        unsigned int offset = address - apic->base_address;
         unsigned char alignment = offset & 0xf;
         u32 result;
+        /* this bitmask has a bit cleared for each reserver register */
+        static const u64 rmask = 0x43ff01ffffffe70cULL;
 
         if ((alignment + len) > 4) {
-                printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
-                       (unsigned long)address, len);
-                return;
+                apic_debug("KVM_APIC_READ: alignment error %x %d\n",
+                           offset, len);
+                return 1;
         }
+
+        if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
+                apic_debug("KVM_APIC_READ: read reserved register %x\n",
+                           offset);
+                return 1;
+        }
+
         result = __apic_read(apic, offset & ~0xf);
 
+        trace_kvm_apic_read(offset, result);
+
         switch (len) {
         case 1:
         case 2:
@@ -548,6 +623,28 @@ static void apic_mmio_read(struct kvm_io_device *this,
                        "should be 1,2, or 4 instead\n", len);
                 break;
         }
+        return 0;
+}
+
+static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
+{
+        return apic_hw_enabled(apic) &&
+            addr >= apic->base_address &&
+            addr < apic->base_address + LAPIC_MMIO_LENGTH;
+}
+
+static int apic_mmio_read(struct kvm_io_device *this,
+                           gpa_t address, int len, void *data)
+{
+        struct kvm_lapic *apic = to_lapic(this);
+        u32 offset = address - apic->base_address;
+
+        if (!apic_mmio_in_range(apic, address))
+                return -EOPNOTSUPP;
+
+        apic_reg_read(apic, offset, len, data);
+
+        return 0;
 }
 
 static void update_divide_count(struct kvm_lapic *apic)
@@ -573,6 +670,15 @@ static void start_apic_timer(struct kvm_lapic *apic)
 
         if (!apic->lapic_timer.period)
                 return;
+        /*
+         * Do not allow the guest to program periodic timers with small
+         * interval, since the hrtimers are not throttled by the host
+         * scheduler.
+         */
+        if (apic_lvtt_period(apic)) {
+                if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
+                        apic->lapic_timer.period = NSEC_PER_MSEC/2;
+        }
 
         hrtimer_start(&apic->lapic_timer.timer,
                       ktime_add_ns(now, apic->lapic_timer.period),
@@ -603,40 +709,18 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 }
 
-static void apic_mmio_write(struct kvm_io_device *this,
-                            gpa_t address, int len, const void *data)
+static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 {
-        struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
-        unsigned int offset = address - apic->base_address;
-        unsigned char alignment = offset & 0xf;
-        u32 val;
-
-        /*
-         * APIC register must be aligned on 128-bits boundary.
-         * 32/64/128 bits registers must be accessed thru 32 bits.
-         * Refer SDM 8.4.1
-         */
-        if (len != 4 || alignment) {
-                /* Don't shout loud, $infamous_os would cause only noise. */
-                apic_debug("apic write: bad size=%d %lx\n",
-                           len, (long)address);
-                return;
-        }
-
-        val = *(u32 *) data;
-
-        /* too common printing */
-        if (offset != APIC_EOI)
-                apic_debug("%s: offset 0x%x with length 0x%x, and value is "
-                           "0x%x\n", __func__, offset, len, val);
-
-        offset &= 0xff0;
+        int ret = 0;
 
-        KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
+        trace_kvm_apic_write(reg, val);
 
-        switch (offset) {
+        switch (reg) {
         case APIC_ID:           /* Local APIC ID */
-                apic_set_reg(apic, APIC_ID, val);
+                if (!apic_x2apic_mode(apic))
+                        apic_set_reg(apic, APIC_ID, val);
+                else
+                        ret = 1;
                 break;
 
         case APIC_TASKPRI:
@@ -649,15 +733,24 @@ static void apic_mmio_write(struct kvm_io_device *this,
                 break;
 
         case APIC_LDR:
-                apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
+                if (!apic_x2apic_mode(apic))
+                        apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
+                else
+                        ret = 1;
                 break;
 
         case APIC_DFR:
-                apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
+                if (!apic_x2apic_mode(apic))
+                        apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
+                else
+                        ret = 1;
                 break;
 
-        case APIC_SPIV:
-                apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
+        case APIC_SPIV: {
+                u32 mask = 0x3ff;
+                if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
+                        mask |= APIC_SPIV_DIRECTED_EOI;
+                apic_set_reg(apic, APIC_SPIV, val & mask);
                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
                         int i;
                         u32 lvt_val;
@@ -672,7 +765,7 @@ static void apic_mmio_write(struct kvm_io_device *this,
 
                 }
                 break;
-
+        }
         case APIC_ICR:
                 /* No delay here, so we always clear the pending bit */
                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
@@ -680,7 +773,9 @@ static void apic_mmio_write(struct kvm_io_device *this,
                 break;
 
         case APIC_ICR2:
-                apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
+                if (!apic_x2apic_mode(apic))
+                        val &= 0xff000000;
+                apic_set_reg(apic, APIC_ICR2, val);
                 break;
 
         case APIC_LVT0:
@@ -694,8 +789,8 @@ static void apic_mmio_write(struct kvm_io_device *this,
                 if (!apic_sw_enabled(apic))
                         val |= APIC_LVT_MASKED;
 
-                val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
-                apic_set_reg(apic, offset, val);
+                val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
+                apic_set_reg(apic, reg, val);
 
                 break;
 
@@ -703,7 +798,7 @@ static void apic_mmio_write(struct kvm_io_device *this,
                 hrtimer_cancel(&apic->lapic_timer.timer);
                 apic_set_reg(apic, APIC_TMICT, val);
                 start_apic_timer(apic);
-                return;
+                break;
 
         case APIC_TDCR:
                 if (val & 4)
@@ -712,27 +807,59 @@ static void apic_mmio_write(struct kvm_io_device *this,
                 update_divide_count(apic);
                 break;
 
+        case APIC_ESR:
+                if (apic_x2apic_mode(apic) && val != 0) {
+                        printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
+                        ret = 1;
+                }
+                break;
+
+        case APIC_SELF_IPI:
+                if (apic_x2apic_mode(apic)) {
+                        apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
+                } else
+                        ret = 1;
+                break;
         default:
-                apic_debug("Local APIC Write to read-only register %x\n",
-                           offset);
+                ret = 1;
                 break;
         }
-
+        if (ret)
+                apic_debug("Local APIC Write to read-only register %x\n", reg);
+        return ret;
 }
 
-static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
-                           int len, int size)
+static int apic_mmio_write(struct kvm_io_device *this,
+                            gpa_t address, int len, const void *data)
 {
-        struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
-        int ret = 0;
+        struct kvm_lapic *apic = to_lapic(this);
+        unsigned int offset = address - apic->base_address;
+        u32 val;
 
+        if (!apic_mmio_in_range(apic, address))
+                return -EOPNOTSUPP;
 
-        if (apic_hw_enabled(apic) &&
-            (addr >= apic->base_address) &&
-            (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
-                ret = 1;
+        /*
+         * APIC register must be aligned on 128-bits boundary.
+         * 32/64/128 bits registers must be accessed thru 32 bits.
+         * Refer SDM 8.4.1
+         */
+        if (len != 4 || (offset & 0xf)) {
+                /* Don't shout loud, $infamous_os would cause only noise. */
+                apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
+                return 0;
+        }
 
-        return ret;
+        val = *(u32*)data;
+
+        /* too common printing */
+        if (offset != APIC_EOI)
+                apic_debug("%s: offset 0x%x with length 0x%x, and value is "
+                           "0x%x\n", __func__, offset, len, val);
+
+        apic_reg_write(apic, offset & 0xff0, val);
+
+        return 0;
 }
 
 void kvm_free_lapic(struct kvm_vcpu *vcpu)
@@ -763,7 +890,6 @@ void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
 
 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 {
@@ -776,7 +902,6 @@ u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 
         return (tpr & 0xf0) >> 4;
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 
 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 {
@@ -787,10 +912,16 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
                 vcpu->arch.apic_base = value;
                 return;
         }
-        if (apic->vcpu->vcpu_id)
+
+        if (!kvm_vcpu_is_bsp(apic->vcpu))
                 value &= ~MSR_IA32_APICBASE_BSP;
 
         vcpu->arch.apic_base = value;
+        if (apic_x2apic_mode(apic)) {
+                u32 id = kvm_apic_id(apic);
+                u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
+                apic_set_reg(apic, APIC_LDR, ldr);
+        }
         apic->base_address = apic->vcpu->arch.apic_base &
                              MSR_IA32_APICBASE_BASE;
 
@@ -800,12 +931,6 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 
 }
 
-u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
-{
-        return vcpu->arch.apic_base;
-}
-EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
-
 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic;
@@ -821,7 +946,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
         hrtimer_cancel(&apic->lapic_timer.timer);
 
         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
-        apic_set_reg(apic, APIC_LVR, APIC_VERSION);
+        kvm_apic_set_version(apic->vcpu);
 
         for (i = 0; i < APIC_LVT_NUM; i++)
                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
@@ -842,9 +967,10 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
         }
+        apic->irr_pending = false;
         update_divide_count(apic);
         atomic_set(&apic->lapic_timer.pending, 0);
-        if (vcpu->vcpu_id == 0)
+        if (kvm_vcpu_is_bsp(vcpu))
                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
         apic_update_ppr(apic);
 
@@ -855,7 +981,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                    vcpu, kvm_apic_id(apic),
                    vcpu->arch.apic_base, apic->base_address);
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 
 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 {
@@ -866,7 +991,6 @@ int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 {
         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 
 /*
  *----------------------------------------------------------------------
@@ -917,6 +1041,11 @@ static struct kvm_timer_ops lapic_timer_ops = {
         .is_periodic = lapic_is_periodic,
 };
 
+static const struct kvm_io_device_ops apic_mmio_ops = {
+        .read     = apic_mmio_read,
+        .write    = apic_mmio_write,
+};
+
 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic;
@@ -945,16 +1074,13 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu)
         apic->lapic_timer.timer.function = kvm_timer_fn;
         apic->lapic_timer.t_ops = &lapic_timer_ops;
         apic->lapic_timer.kvm = vcpu->kvm;
-        apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
+        apic->lapic_timer.vcpu = vcpu;
 
         apic->base_address = APIC_DEFAULT_PHYS_BASE;
         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
 
         kvm_lapic_reset(vcpu);
-        apic->dev.read = apic_mmio_read;
-        apic->dev.write = apic_mmio_write;
-        apic->dev.in_range = apic_mmio_range;
-        apic->dev.private = apic;
+        kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
 
         return 0;
 nomem_free_apic:
@@ -962,7 +1088,6 @@ nomem_free_apic:
 nomem:
         return -ENOMEM;
 }
-EXPORT_SYMBOL_GPL(kvm_create_lapic);
 
 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
 {
@@ -985,7 +1110,7 @@ int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
         int r = 0;
 
-        if (vcpu->vcpu_id == 0) {
+        if (kvm_vcpu_is_bsp(vcpu)) {
                 if (!apic_hw_enabled(vcpu->arch.apic))
                         r = 1;
                 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
@@ -1025,7 +1150,8 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
 
         apic->base_address = vcpu->arch.apic_base &
                              MSR_IA32_APICBASE_BASE;
-        apic_set_reg(apic, APIC_LVR, APIC_VERSION);
+        kvm_apic_set_version(vcpu);
+
         apic_update_ppr(apic);
         hrtimer_cancel(&apic->lapic_timer.timer);
         update_divide_count(apic);
@@ -1092,3 +1218,35 @@ void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
 
         vcpu->arch.apic->vapic_addr = vapic_addr;
 }
+
+int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        u32 reg = (msr - APIC_BASE_MSR) << 4;
+
+        if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
+                return 1;
+
+        /* if this is ICR write vector before command */
+        if (msr == 0x830)
+                apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
+        return apic_reg_write(apic, reg, (u32)data);
+}
+
+int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
+
+        if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
+                return 1;
+
+        if (apic_reg_read(apic, reg, 4, &low))
+                return 1;
+        if (msr == 0x830)
+                apic_reg_read(apic, APIC_ICR2, 4, &high);
+
+        *data = (((u64)high) << 32) | low;
+
+        return 0;
+}