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-rw-r--r--arch/x86/kvm/lapic.c1085
1 files changed, 1085 insertions, 0 deletions
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
new file mode 100644
index 000000000000..4076331b01ee
--- /dev/null
+++ b/arch/x86/kvm/lapic.c
@@ -0,0 +1,1085 @@
1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
20#include <linux/kvm_host.h>
21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <asm/processor.h>
29#include <asm/msr.h>
30#include <asm/page.h>
31#include <asm/current.h>
32#include <asm/apicdef.h>
33#include <asm/atomic.h>
34#include <asm/div64.h>
35#include "irq.h"
36
37#define PRId64 "d"
38#define PRIx64 "llx"
39#define PRIu64 "u"
40#define PRIo64 "o"
41
42#define APIC_BUS_CYCLE_NS 1
43
44/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
45#define apic_debug(fmt, arg...)
46
47#define APIC_LVT_NUM 6
48/* 14 is the version for Xeon and Pentium 8.4.8*/
49#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
50#define LAPIC_MMIO_LENGTH (1 << 12)
51/* followed define is not in apicdef.h */
52#define APIC_SHORT_MASK 0xc0000
53#define APIC_DEST_NOSHORT 0x0
54#define APIC_DEST_MASK 0x800
55#define MAX_APIC_VECTOR 256
56
57#define VEC_POS(v) ((v) & (32 - 1))
58#define REG_POS(v) (((v) >> 5) << 4)
59
60static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
61{
62 return *((u32 *) (apic->regs + reg_off));
63}
64
65static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
66{
67 *((u32 *) (apic->regs + reg_off)) = val;
68}
69
70static inline int apic_test_and_set_vector(int vec, void *bitmap)
71{
72 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
73}
74
75static inline int apic_test_and_clear_vector(int vec, void *bitmap)
76{
77 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78}
79
80static inline void apic_set_vector(int vec, void *bitmap)
81{
82 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
83}
84
85static inline void apic_clear_vector(int vec, void *bitmap)
86{
87 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
88}
89
90static inline int apic_hw_enabled(struct kvm_lapic *apic)
91{
92 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
93}
94
95static inline int apic_sw_enabled(struct kvm_lapic *apic)
96{
97 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
98}
99
100static inline int apic_enabled(struct kvm_lapic *apic)
101{
102 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
103}
104
105#define LVT_MASK \
106 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
107
108#define LINT_MASK \
109 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
110 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
111
112static inline int kvm_apic_id(struct kvm_lapic *apic)
113{
114 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
115}
116
117static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
118{
119 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
120}
121
122static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
123{
124 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
125}
126
127static inline int apic_lvtt_period(struct kvm_lapic *apic)
128{
129 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
130}
131
132static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
133 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
134 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
135 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
136 LINT_MASK, LINT_MASK, /* LVT0-1 */
137 LVT_MASK /* LVTERR */
138};
139
140static int find_highest_vector(void *bitmap)
141{
142 u32 *word = bitmap;
143 int word_offset = MAX_APIC_VECTOR >> 5;
144
145 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
146 continue;
147
148 if (likely(!word_offset && !word[0]))
149 return -1;
150 else
151 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
152}
153
154static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
155{
156 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
157}
158
159static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
160{
161 apic_clear_vector(vec, apic->regs + APIC_IRR);
162}
163
164static inline int apic_find_highest_irr(struct kvm_lapic *apic)
165{
166 int result;
167
168 result = find_highest_vector(apic->regs + APIC_IRR);
169 ASSERT(result == -1 || result >= 16);
170
171 return result;
172}
173
174int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
175{
176 struct kvm_lapic *apic = vcpu->arch.apic;
177 int highest_irr;
178
179 if (!apic)
180 return 0;
181 highest_irr = apic_find_highest_irr(apic);
182
183 return highest_irr;
184}
185EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
186
187int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig)
188{
189 struct kvm_lapic *apic = vcpu->arch.apic;
190
191 if (!apic_test_and_set_irr(vec, apic)) {
192 /* a new pending irq is set in IRR */
193 if (trig)
194 apic_set_vector(vec, apic->regs + APIC_TMR);
195 else
196 apic_clear_vector(vec, apic->regs + APIC_TMR);
197 kvm_vcpu_kick(apic->vcpu);
198 return 1;
199 }
200 return 0;
201}
202
203static inline int apic_find_highest_isr(struct kvm_lapic *apic)
204{
205 int result;
206
207 result = find_highest_vector(apic->regs + APIC_ISR);
208 ASSERT(result == -1 || result >= 16);
209
210 return result;
211}
212
213static void apic_update_ppr(struct kvm_lapic *apic)
214{
215 u32 tpr, isrv, ppr;
216 int isr;
217
218 tpr = apic_get_reg(apic, APIC_TASKPRI);
219 isr = apic_find_highest_isr(apic);
220 isrv = (isr != -1) ? isr : 0;
221
222 if ((tpr & 0xf0) >= (isrv & 0xf0))
223 ppr = tpr & 0xff;
224 else
225 ppr = isrv & 0xf0;
226
227 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
228 apic, ppr, isr, isrv);
229
230 apic_set_reg(apic, APIC_PROCPRI, ppr);
231}
232
233static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
234{
235 apic_set_reg(apic, APIC_TASKPRI, tpr);
236 apic_update_ppr(apic);
237}
238
239int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
240{
241 return kvm_apic_id(apic) == dest;
242}
243
244int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
245{
246 int result = 0;
247 u8 logical_id;
248
249 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
250
251 switch (apic_get_reg(apic, APIC_DFR)) {
252 case APIC_DFR_FLAT:
253 if (logical_id & mda)
254 result = 1;
255 break;
256 case APIC_DFR_CLUSTER:
257 if (((logical_id >> 4) == (mda >> 0x4))
258 && (logical_id & mda & 0xf))
259 result = 1;
260 break;
261 default:
262 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
263 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
264 break;
265 }
266
267 return result;
268}
269
270static int apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
271 int short_hand, int dest, int dest_mode)
272{
273 int result = 0;
274 struct kvm_lapic *target = vcpu->arch.apic;
275
276 apic_debug("target %p, source %p, dest 0x%x, "
277 "dest_mode 0x%x, short_hand 0x%x",
278 target, source, dest, dest_mode, short_hand);
279
280 ASSERT(!target);
281 switch (short_hand) {
282 case APIC_DEST_NOSHORT:
283 if (dest_mode == 0) {
284 /* Physical mode. */
285 if ((dest == 0xFF) || (dest == kvm_apic_id(target)))
286 result = 1;
287 } else
288 /* Logical mode. */
289 result = kvm_apic_match_logical_addr(target, dest);
290 break;
291 case APIC_DEST_SELF:
292 if (target == source)
293 result = 1;
294 break;
295 case APIC_DEST_ALLINC:
296 result = 1;
297 break;
298 case APIC_DEST_ALLBUT:
299 if (target != source)
300 result = 1;
301 break;
302 default:
303 printk(KERN_WARNING "Bad dest shorthand value %x\n",
304 short_hand);
305 break;
306 }
307
308 return result;
309}
310
311/*
312 * Add a pending IRQ into lapic.
313 * Return 1 if successfully added and 0 if discarded.
314 */
315static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
316 int vector, int level, int trig_mode)
317{
318 int orig_irr, result = 0;
319 struct kvm_vcpu *vcpu = apic->vcpu;
320
321 switch (delivery_mode) {
322 case APIC_DM_FIXED:
323 case APIC_DM_LOWEST:
324 /* FIXME add logic for vcpu on reset */
325 if (unlikely(!apic_enabled(apic)))
326 break;
327
328 orig_irr = apic_test_and_set_irr(vector, apic);
329 if (orig_irr && trig_mode) {
330 apic_debug("level trig mode repeatedly for vector %d",
331 vector);
332 break;
333 }
334
335 if (trig_mode) {
336 apic_debug("level trig mode for vector %d", vector);
337 apic_set_vector(vector, apic->regs + APIC_TMR);
338 } else
339 apic_clear_vector(vector, apic->regs + APIC_TMR);
340
341 if (vcpu->arch.mp_state == VCPU_MP_STATE_RUNNABLE)
342 kvm_vcpu_kick(vcpu);
343 else if (vcpu->arch.mp_state == VCPU_MP_STATE_HALTED) {
344 vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
345 if (waitqueue_active(&vcpu->wq))
346 wake_up_interruptible(&vcpu->wq);
347 }
348
349 result = (orig_irr == 0);
350 break;
351
352 case APIC_DM_REMRD:
353 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
354 break;
355
356 case APIC_DM_SMI:
357 printk(KERN_DEBUG "Ignoring guest SMI\n");
358 break;
359 case APIC_DM_NMI:
360 printk(KERN_DEBUG "Ignoring guest NMI\n");
361 break;
362
363 case APIC_DM_INIT:
364 if (level) {
365 if (vcpu->arch.mp_state == VCPU_MP_STATE_RUNNABLE)
366 printk(KERN_DEBUG
367 "INIT on a runnable vcpu %d\n",
368 vcpu->vcpu_id);
369 vcpu->arch.mp_state = VCPU_MP_STATE_INIT_RECEIVED;
370 kvm_vcpu_kick(vcpu);
371 } else {
372 printk(KERN_DEBUG
373 "Ignoring de-assert INIT to vcpu %d\n",
374 vcpu->vcpu_id);
375 }
376
377 break;
378
379 case APIC_DM_STARTUP:
380 printk(KERN_DEBUG "SIPI to vcpu %d vector 0x%02x\n",
381 vcpu->vcpu_id, vector);
382 if (vcpu->arch.mp_state == VCPU_MP_STATE_INIT_RECEIVED) {
383 vcpu->arch.sipi_vector = vector;
384 vcpu->arch.mp_state = VCPU_MP_STATE_SIPI_RECEIVED;
385 if (waitqueue_active(&vcpu->wq))
386 wake_up_interruptible(&vcpu->wq);
387 }
388 break;
389
390 default:
391 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
392 delivery_mode);
393 break;
394 }
395 return result;
396}
397
398static struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
399 unsigned long bitmap)
400{
401 int last;
402 int next;
403 struct kvm_lapic *apic = NULL;
404
405 last = kvm->arch.round_robin_prev_vcpu;
406 next = last;
407
408 do {
409 if (++next == KVM_MAX_VCPUS)
410 next = 0;
411 if (kvm->vcpus[next] == NULL || !test_bit(next, &bitmap))
412 continue;
413 apic = kvm->vcpus[next]->arch.apic;
414 if (apic && apic_enabled(apic))
415 break;
416 apic = NULL;
417 } while (next != last);
418 kvm->arch.round_robin_prev_vcpu = next;
419
420 if (!apic)
421 printk(KERN_DEBUG "vcpu not ready for apic_round_robin\n");
422
423 return apic;
424}
425
426struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
427 unsigned long bitmap)
428{
429 struct kvm_lapic *apic;
430
431 apic = kvm_apic_round_robin(kvm, vector, bitmap);
432 if (apic)
433 return apic->vcpu;
434 return NULL;
435}
436
437static void apic_set_eoi(struct kvm_lapic *apic)
438{
439 int vector = apic_find_highest_isr(apic);
440
441 /*
442 * Not every write EOI will has corresponding ISR,
443 * one example is when Kernel check timer on setup_IO_APIC
444 */
445 if (vector == -1)
446 return;
447
448 apic_clear_vector(vector, apic->regs + APIC_ISR);
449 apic_update_ppr(apic);
450
451 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
452 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector);
453}
454
455static void apic_send_ipi(struct kvm_lapic *apic)
456{
457 u32 icr_low = apic_get_reg(apic, APIC_ICR);
458 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
459
460 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
461 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
462 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
463 unsigned int level = icr_low & APIC_INT_ASSERT;
464 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
465 unsigned int delivery_mode = icr_low & APIC_MODE_MASK;
466 unsigned int vector = icr_low & APIC_VECTOR_MASK;
467
468 struct kvm_vcpu *target;
469 struct kvm_vcpu *vcpu;
470 unsigned long lpr_map = 0;
471 int i;
472
473 apic_debug("icr_high 0x%x, icr_low 0x%x, "
474 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
475 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
476 icr_high, icr_low, short_hand, dest,
477 trig_mode, level, dest_mode, delivery_mode, vector);
478
479 for (i = 0; i < KVM_MAX_VCPUS; i++) {
480 vcpu = apic->vcpu->kvm->vcpus[i];
481 if (!vcpu)
482 continue;
483
484 if (vcpu->arch.apic &&
485 apic_match_dest(vcpu, apic, short_hand, dest, dest_mode)) {
486 if (delivery_mode == APIC_DM_LOWEST)
487 set_bit(vcpu->vcpu_id, &lpr_map);
488 else
489 __apic_accept_irq(vcpu->arch.apic, delivery_mode,
490 vector, level, trig_mode);
491 }
492 }
493
494 if (delivery_mode == APIC_DM_LOWEST) {
495 target = kvm_get_lowest_prio_vcpu(vcpu->kvm, vector, lpr_map);
496 if (target != NULL)
497 __apic_accept_irq(target->arch.apic, delivery_mode,
498 vector, level, trig_mode);
499 }
500}
501
502static u32 apic_get_tmcct(struct kvm_lapic *apic)
503{
504 u64 counter_passed;
505 ktime_t passed, now;
506 u32 tmcct;
507
508 ASSERT(apic != NULL);
509
510 now = apic->timer.dev.base->get_time();
511 tmcct = apic_get_reg(apic, APIC_TMICT);
512
513 /* if initial count is 0, current count should also be 0 */
514 if (tmcct == 0)
515 return 0;
516
517 if (unlikely(ktime_to_ns(now) <=
518 ktime_to_ns(apic->timer.last_update))) {
519 /* Wrap around */
520 passed = ktime_add(( {
521 (ktime_t) {
522 .tv64 = KTIME_MAX -
523 (apic->timer.last_update).tv64}; }
524 ), now);
525 apic_debug("time elapsed\n");
526 } else
527 passed = ktime_sub(now, apic->timer.last_update);
528
529 counter_passed = div64_64(ktime_to_ns(passed),
530 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
531
532 if (counter_passed > tmcct) {
533 if (unlikely(!apic_lvtt_period(apic))) {
534 /* one-shot timers stick at 0 until reset */
535 tmcct = 0;
536 } else {
537 /*
538 * periodic timers reset to APIC_TMICT when they
539 * hit 0. The while loop simulates this happening N
540 * times. (counter_passed %= tmcct) would also work,
541 * but might be slower or not work on 32-bit??
542 */
543 while (counter_passed > tmcct)
544 counter_passed -= tmcct;
545 tmcct -= counter_passed;
546 }
547 } else {
548 tmcct -= counter_passed;
549 }
550
551 return tmcct;
552}
553
554static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
555{
556 u32 val = 0;
557
558 if (offset >= LAPIC_MMIO_LENGTH)
559 return 0;
560
561 switch (offset) {
562 case APIC_ARBPRI:
563 printk(KERN_WARNING "Access APIC ARBPRI register "
564 "which is for P6\n");
565 break;
566
567 case APIC_TMCCT: /* Timer CCR */
568 val = apic_get_tmcct(apic);
569 break;
570
571 default:
572 apic_update_ppr(apic);
573 val = apic_get_reg(apic, offset);
574 break;
575 }
576
577 return val;
578}
579
580static void apic_mmio_read(struct kvm_io_device *this,
581 gpa_t address, int len, void *data)
582{
583 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
584 unsigned int offset = address - apic->base_address;
585 unsigned char alignment = offset & 0xf;
586 u32 result;
587
588 if ((alignment + len) > 4) {
589 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
590 (unsigned long)address, len);
591 return;
592 }
593 result = __apic_read(apic, offset & ~0xf);
594
595 switch (len) {
596 case 1:
597 case 2:
598 case 4:
599 memcpy(data, (char *)&result + alignment, len);
600 break;
601 default:
602 printk(KERN_ERR "Local APIC read with len = %x, "
603 "should be 1,2, or 4 instead\n", len);
604 break;
605 }
606}
607
608static void update_divide_count(struct kvm_lapic *apic)
609{
610 u32 tmp1, tmp2, tdcr;
611
612 tdcr = apic_get_reg(apic, APIC_TDCR);
613 tmp1 = tdcr & 0xf;
614 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
615 apic->timer.divide_count = 0x1 << (tmp2 & 0x7);
616
617 apic_debug("timer divide count is 0x%x\n",
618 apic->timer.divide_count);
619}
620
621static void start_apic_timer(struct kvm_lapic *apic)
622{
623 ktime_t now = apic->timer.dev.base->get_time();
624
625 apic->timer.last_update = now;
626
627 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
628 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
629 atomic_set(&apic->timer.pending, 0);
630 hrtimer_start(&apic->timer.dev,
631 ktime_add_ns(now, apic->timer.period),
632 HRTIMER_MODE_ABS);
633
634 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
635 PRIx64 ", "
636 "timer initial count 0x%x, period %lldns, "
637 "expire @ 0x%016" PRIx64 ".\n", __FUNCTION__,
638 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
639 apic_get_reg(apic, APIC_TMICT),
640 apic->timer.period,
641 ktime_to_ns(ktime_add_ns(now,
642 apic->timer.period)));
643}
644
645static void apic_mmio_write(struct kvm_io_device *this,
646 gpa_t address, int len, const void *data)
647{
648 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
649 unsigned int offset = address - apic->base_address;
650 unsigned char alignment = offset & 0xf;
651 u32 val;
652
653 /*
654 * APIC register must be aligned on 128-bits boundary.
655 * 32/64/128 bits registers must be accessed thru 32 bits.
656 * Refer SDM 8.4.1
657 */
658 if (len != 4 || alignment) {
659 if (printk_ratelimit())
660 printk(KERN_ERR "apic write: bad size=%d %lx\n",
661 len, (long)address);
662 return;
663 }
664
665 val = *(u32 *) data;
666
667 /* too common printing */
668 if (offset != APIC_EOI)
669 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
670 "0x%x\n", __FUNCTION__, offset, len, val);
671
672 offset &= 0xff0;
673
674 switch (offset) {
675 case APIC_ID: /* Local APIC ID */
676 apic_set_reg(apic, APIC_ID, val);
677 break;
678
679 case APIC_TASKPRI:
680 apic_set_tpr(apic, val & 0xff);
681 break;
682
683 case APIC_EOI:
684 apic_set_eoi(apic);
685 break;
686
687 case APIC_LDR:
688 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
689 break;
690
691 case APIC_DFR:
692 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
693 break;
694
695 case APIC_SPIV:
696 apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
697 if (!(val & APIC_SPIV_APIC_ENABLED)) {
698 int i;
699 u32 lvt_val;
700
701 for (i = 0; i < APIC_LVT_NUM; i++) {
702 lvt_val = apic_get_reg(apic,
703 APIC_LVTT + 0x10 * i);
704 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
705 lvt_val | APIC_LVT_MASKED);
706 }
707 atomic_set(&apic->timer.pending, 0);
708
709 }
710 break;
711
712 case APIC_ICR:
713 /* No delay here, so we always clear the pending bit */
714 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
715 apic_send_ipi(apic);
716 break;
717
718 case APIC_ICR2:
719 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
720 break;
721
722 case APIC_LVTT:
723 case APIC_LVTTHMR:
724 case APIC_LVTPC:
725 case APIC_LVT0:
726 case APIC_LVT1:
727 case APIC_LVTERR:
728 /* TODO: Check vector */
729 if (!apic_sw_enabled(apic))
730 val |= APIC_LVT_MASKED;
731
732 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
733 apic_set_reg(apic, offset, val);
734
735 break;
736
737 case APIC_TMICT:
738 hrtimer_cancel(&apic->timer.dev);
739 apic_set_reg(apic, APIC_TMICT, val);
740 start_apic_timer(apic);
741 return;
742
743 case APIC_TDCR:
744 if (val & 4)
745 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
746 apic_set_reg(apic, APIC_TDCR, val);
747 update_divide_count(apic);
748 break;
749
750 default:
751 apic_debug("Local APIC Write to read-only register %x\n",
752 offset);
753 break;
754 }
755
756}
757
758static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr)
759{
760 struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
761 int ret = 0;
762
763
764 if (apic_hw_enabled(apic) &&
765 (addr >= apic->base_address) &&
766 (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
767 ret = 1;
768
769 return ret;
770}
771
772void kvm_free_lapic(struct kvm_vcpu *vcpu)
773{
774 if (!vcpu->arch.apic)
775 return;
776
777 hrtimer_cancel(&vcpu->arch.apic->timer.dev);
778
779 if (vcpu->arch.apic->regs_page)
780 __free_page(vcpu->arch.apic->regs_page);
781
782 kfree(vcpu->arch.apic);
783}
784
785/*
786 *----------------------------------------------------------------------
787 * LAPIC interface
788 *----------------------------------------------------------------------
789 */
790
791void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
792{
793 struct kvm_lapic *apic = vcpu->arch.apic;
794
795 if (!apic)
796 return;
797 apic_set_tpr(apic, ((cr8 & 0x0f) << 4));
798}
799
800u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
801{
802 struct kvm_lapic *apic = vcpu->arch.apic;
803 u64 tpr;
804
805 if (!apic)
806 return 0;
807 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
808
809 return (tpr & 0xf0) >> 4;
810}
811EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
812
813void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
814{
815 struct kvm_lapic *apic = vcpu->arch.apic;
816
817 if (!apic) {
818 value |= MSR_IA32_APICBASE_BSP;
819 vcpu->arch.apic_base = value;
820 return;
821 }
822 if (apic->vcpu->vcpu_id)
823 value &= ~MSR_IA32_APICBASE_BSP;
824
825 vcpu->arch.apic_base = value;
826 apic->base_address = apic->vcpu->arch.apic_base &
827 MSR_IA32_APICBASE_BASE;
828
829 /* with FSB delivery interrupt, we can restart APIC functionality */
830 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
831 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
832
833}
834
835u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
836{
837 return vcpu->arch.apic_base;
838}
839EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
840
841void kvm_lapic_reset(struct kvm_vcpu *vcpu)
842{
843 struct kvm_lapic *apic;
844 int i;
845
846 apic_debug("%s\n", __FUNCTION__);
847
848 ASSERT(vcpu);
849 apic = vcpu->arch.apic;
850 ASSERT(apic != NULL);
851
852 /* Stop the timer in case it's a reset to an active apic */
853 hrtimer_cancel(&apic->timer.dev);
854
855 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
856 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
857
858 for (i = 0; i < APIC_LVT_NUM; i++)
859 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
860 apic_set_reg(apic, APIC_LVT0,
861 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
862
863 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
864 apic_set_reg(apic, APIC_SPIV, 0xff);
865 apic_set_reg(apic, APIC_TASKPRI, 0);
866 apic_set_reg(apic, APIC_LDR, 0);
867 apic_set_reg(apic, APIC_ESR, 0);
868 apic_set_reg(apic, APIC_ICR, 0);
869 apic_set_reg(apic, APIC_ICR2, 0);
870 apic_set_reg(apic, APIC_TDCR, 0);
871 apic_set_reg(apic, APIC_TMICT, 0);
872 for (i = 0; i < 8; i++) {
873 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
874 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
875 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
876 }
877 update_divide_count(apic);
878 atomic_set(&apic->timer.pending, 0);
879 if (vcpu->vcpu_id == 0)
880 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
881 apic_update_ppr(apic);
882
883 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
884 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __FUNCTION__,
885 vcpu, kvm_apic_id(apic),
886 vcpu->arch.apic_base, apic->base_address);
887}
888EXPORT_SYMBOL_GPL(kvm_lapic_reset);
889
890int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
891{
892 struct kvm_lapic *apic = vcpu->arch.apic;
893 int ret = 0;
894
895 if (!apic)
896 return 0;
897 ret = apic_enabled(apic);
898
899 return ret;
900}
901EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
902
903/*
904 *----------------------------------------------------------------------
905 * timer interface
906 *----------------------------------------------------------------------
907 */
908
909/* TODO: make sure __apic_timer_fn runs in current pCPU */
910static int __apic_timer_fn(struct kvm_lapic *apic)
911{
912 int result = 0;
913 wait_queue_head_t *q = &apic->vcpu->wq;
914
915 atomic_inc(&apic->timer.pending);
916 if (waitqueue_active(q)) {
917 apic->vcpu->arch.mp_state = VCPU_MP_STATE_RUNNABLE;
918 wake_up_interruptible(q);
919 }
920 if (apic_lvtt_period(apic)) {
921 result = 1;
922 apic->timer.dev.expires = ktime_add_ns(
923 apic->timer.dev.expires,
924 apic->timer.period);
925 }
926 return result;
927}
928
929static int __inject_apic_timer_irq(struct kvm_lapic *apic)
930{
931 int vector;
932
933 vector = apic_lvt_vector(apic, APIC_LVTT);
934 return __apic_accept_irq(apic, APIC_DM_FIXED, vector, 1, 0);
935}
936
937static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
938{
939 struct kvm_lapic *apic;
940 int restart_timer = 0;
941
942 apic = container_of(data, struct kvm_lapic, timer.dev);
943
944 restart_timer = __apic_timer_fn(apic);
945
946 if (restart_timer)
947 return HRTIMER_RESTART;
948 else
949 return HRTIMER_NORESTART;
950}
951
952int kvm_create_lapic(struct kvm_vcpu *vcpu)
953{
954 struct kvm_lapic *apic;
955
956 ASSERT(vcpu != NULL);
957 apic_debug("apic_init %d\n", vcpu->vcpu_id);
958
959 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
960 if (!apic)
961 goto nomem;
962
963 vcpu->arch.apic = apic;
964
965 apic->regs_page = alloc_page(GFP_KERNEL);
966 if (apic->regs_page == NULL) {
967 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
968 vcpu->vcpu_id);
969 goto nomem_free_apic;
970 }
971 apic->regs = page_address(apic->regs_page);
972 memset(apic->regs, 0, PAGE_SIZE);
973 apic->vcpu = vcpu;
974
975 hrtimer_init(&apic->timer.dev, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
976 apic->timer.dev.function = apic_timer_fn;
977 apic->base_address = APIC_DEFAULT_PHYS_BASE;
978 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
979
980 kvm_lapic_reset(vcpu);
981 apic->dev.read = apic_mmio_read;
982 apic->dev.write = apic_mmio_write;
983 apic->dev.in_range = apic_mmio_range;
984 apic->dev.private = apic;
985
986 return 0;
987nomem_free_apic:
988 kfree(apic);
989nomem:
990 return -ENOMEM;
991}
992EXPORT_SYMBOL_GPL(kvm_create_lapic);
993
994int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
995{
996 struct kvm_lapic *apic = vcpu->arch.apic;
997 int highest_irr;
998
999 if (!apic || !apic_enabled(apic))
1000 return -1;
1001
1002 apic_update_ppr(apic);
1003 highest_irr = apic_find_highest_irr(apic);
1004 if ((highest_irr == -1) ||
1005 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1006 return -1;
1007 return highest_irr;
1008}
1009
1010int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1011{
1012 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1013 int r = 0;
1014
1015 if (vcpu->vcpu_id == 0) {
1016 if (!apic_hw_enabled(vcpu->arch.apic))
1017 r = 1;
1018 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1019 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1020 r = 1;
1021 }
1022 return r;
1023}
1024
1025void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1026{
1027 struct kvm_lapic *apic = vcpu->arch.apic;
1028
1029 if (apic && apic_lvt_enabled(apic, APIC_LVTT) &&
1030 atomic_read(&apic->timer.pending) > 0) {
1031 if (__inject_apic_timer_irq(apic))
1032 atomic_dec(&apic->timer.pending);
1033 }
1034}
1035
1036void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1037{
1038 struct kvm_lapic *apic = vcpu->arch.apic;
1039
1040 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1041 apic->timer.last_update = ktime_add_ns(
1042 apic->timer.last_update,
1043 apic->timer.period);
1044}
1045
1046int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1047{
1048 int vector = kvm_apic_has_interrupt(vcpu);
1049 struct kvm_lapic *apic = vcpu->arch.apic;
1050
1051 if (vector == -1)
1052 return -1;
1053
1054 apic_set_vector(vector, apic->regs + APIC_ISR);
1055 apic_update_ppr(apic);
1056 apic_clear_irr(vector, apic);
1057 return vector;
1058}
1059
1060void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1061{
1062 struct kvm_lapic *apic = vcpu->arch.apic;
1063
1064 apic->base_address = vcpu->arch.apic_base &
1065 MSR_IA32_APICBASE_BASE;
1066 apic_set_reg(apic, APIC_LVR, APIC_VERSION);
1067 apic_update_ppr(apic);
1068 hrtimer_cancel(&apic->timer.dev);
1069 update_divide_count(apic);
1070 start_apic_timer(apic);
1071}
1072
1073void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1074{
1075 struct kvm_lapic *apic = vcpu->arch.apic;
1076 struct hrtimer *timer;
1077
1078 if (!apic)
1079 return;
1080
1081 timer = &apic->timer.dev;
1082 if (hrtimer_cancel(timer))
1083 hrtimer_start(timer, timer->expires, HRTIMER_MODE_ABS);
1084}
1085EXPORT_SYMBOL_GPL(kvm_migrate_apic_timer);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 13:19:35 -0400