2 files changed, 11 insertions, 5 deletions

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index b3eeb66c0a51..95962a93f99a 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -340,6 +340,10 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
              (boot_cpu_data.x86_mask  < 0x1)))
                 return;
 
+        /* not in virtualized environments */
+        if (num_k8_northbridges == 0)
+                return;
+
         this_leaf->can_disable = true;
         this_leaf->l3_indices  = amd_calc_l3_indices();
 }
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 28ad9f4d8b94..0415c3ef91b5 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -546,11 +546,13 @@ static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
                  * check OSVW bit for CPUs that are not affected
                  * by erratum #400
                  */
-                rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
-                if (val >= 2) {
-                        rdmsrl(MSR_AMD64_OSVW_STATUS, val);
-                        if (!(val & BIT(1)))
-                                goto no_c1e_idle;
+                if (cpu_has(c, X86_FEATURE_OSVW)) {
+                        rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val);
+                        if (val >= 2) {
+                                rdmsrl(MSR_AMD64_OSVW_STATUS, val);
+                                if (!(val & BIT(1)))
+                                        goto no_c1e_idle;
+                        }
                 }
                 return 1;
         }