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-rw-r--r--arch/x86/kernel/apic_32.c3
-rw-r--r--arch/x86/kernel/apic_64.c3
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
index d6c898358371..fad94b0decc1 100644
--- a/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@ -646,6 +646,9 @@ int setup_profiling_timer(unsigned int multiplier)
646 * 646 *
647 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 647 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
648 * MCE interrupts are supported. Thus MCE offset must be set to 0. 648 * MCE interrupts are supported. Thus MCE offset must be set to 0.
649 *
650 * If mask=1, the LVT entry does not generate interrupts while mask=0
651 * enables the vector. See also the BKDGs.
649 */ 652 */
650 653
651#define APIC_EILVT_LVTOFF_MCE 0 654#define APIC_EILVT_LVTOFF_MCE 0
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index 7f1f030da7ee..42bf69f8bc8e 100644
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -205,6 +205,9 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
205 * 205 *
206 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 206 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
207 * MCE interrupts are supported. Thus MCE offset must be set to 0. 207 * MCE interrupts are supported. Thus MCE offset must be set to 0.
208 *
209 * If mask=1, the LVT entry does not generate interrupts while mask=0
210 * enables the vector. See also the BKDGs.
208 */ 211 */
209 212
210#define APIC_EILVT_LVTOFF_MCE 0 213#define APIC_EILVT_LVTOFF_MCE 0