diff options
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_intel.c | 9 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_intel_64.c | 2 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/p4.c | 2 |
3 files changed, 7 insertions, 6 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index bad3cbb0e566..2b011d2d8579 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c | |||
@@ -32,13 +32,13 @@ void intel_init_thermal(struct cpuinfo_x86 *c) | |||
32 | */ | 32 | */ |
33 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | 33 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); |
34 | h = apic_read(APIC_LVTTHMR); | 34 | h = apic_read(APIC_LVTTHMR); |
35 | if ((l & (1 << 3)) && (h & APIC_DM_SMI)) { | 35 | if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { |
36 | printk(KERN_DEBUG | 36 | printk(KERN_DEBUG |
37 | "CPU%d: Thermal monitoring handled by SMI\n", cpu); | 37 | "CPU%d: Thermal monitoring handled by SMI\n", cpu); |
38 | return; | 38 | return; |
39 | } | 39 | } |
40 | 40 | ||
41 | if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13))) | 41 | if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2)) |
42 | tm2 = 1; | 42 | tm2 = 1; |
43 | 43 | ||
44 | /* Check whether a vector already exists */ | 44 | /* Check whether a vector already exists */ |
@@ -54,12 +54,13 @@ void intel_init_thermal(struct cpuinfo_x86 *c) | |||
54 | apic_write(APIC_LVTTHMR, h); | 54 | apic_write(APIC_LVTTHMR, h); |
55 | 55 | ||
56 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); | 56 | rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); |
57 | wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h); | 57 | wrmsr(MSR_IA32_THERM_INTERRUPT, |
58 | l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); | ||
58 | 59 | ||
59 | intel_set_thermal_handler(); | 60 | intel_set_thermal_handler(); |
60 | 61 | ||
61 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); | 62 | rdmsr(MSR_IA32_MISC_ENABLE, l, h); |
62 | wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h); | 63 | wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); |
63 | 64 | ||
64 | /* Unmask the thermal vector: */ | 65 | /* Unmask the thermal vector: */ |
65 | l = apic_read(APIC_LVTTHMR); | 66 | l = apic_read(APIC_LVTTHMR); |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c index 38f9632306fa..13abafcb72e4 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c | |||
@@ -29,7 +29,7 @@ asmlinkage void smp_thermal_interrupt(void) | |||
29 | irq_enter(); | 29 | irq_enter(); |
30 | 30 | ||
31 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | 31 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); |
32 | if (therm_throt_process(msr_val & 1)) | 32 | if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT)) |
33 | mce_log_therm_throt_event(msr_val); | 33 | mce_log_therm_throt_event(msr_val); |
34 | 34 | ||
35 | inc_irq_stat(irq_thermal_count); | 35 | inc_irq_stat(irq_thermal_count); |
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c index f979ffea330b..82cee108a2d3 100644 --- a/arch/x86/kernel/cpu/mcheck/p4.c +++ b/arch/x86/kernel/cpu/mcheck/p4.c | |||
@@ -51,7 +51,7 @@ static void intel_thermal_interrupt(struct pt_regs *regs) | |||
51 | ack_APIC_irq(); | 51 | ack_APIC_irq(); |
52 | 52 | ||
53 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); | 53 | rdmsrl(MSR_IA32_THERM_STATUS, msr_val); |
54 | therm_throt_process(msr_val & 0x1); | 54 | therm_throt_process(msr_val & THERM_STATUS_PROCHOT); |
55 | } | 55 | } |
56 | 56 | ||
57 | /* Thermal interrupt handler for this CPU setup: */ | 57 | /* Thermal interrupt handler for this CPU setup: */ |