diff options
Diffstat (limited to 'arch/x86/kernel/tsc.c')
-rw-r--r-- | arch/x86/kernel/tsc.c | 122 |
1 files changed, 70 insertions, 52 deletions
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 599e58168631..08afa1579e6d 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c | |||
@@ -17,20 +17,21 @@ | |||
17 | #include <asm/delay.h> | 17 | #include <asm/delay.h> |
18 | #include <asm/hypervisor.h> | 18 | #include <asm/hypervisor.h> |
19 | 19 | ||
20 | unsigned int cpu_khz; /* TSC clocks / usec, not used here */ | 20 | unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ |
21 | EXPORT_SYMBOL(cpu_khz); | 21 | EXPORT_SYMBOL(cpu_khz); |
22 | unsigned int tsc_khz; | 22 | |
23 | unsigned int __read_mostly tsc_khz; | ||
23 | EXPORT_SYMBOL(tsc_khz); | 24 | EXPORT_SYMBOL(tsc_khz); |
24 | 25 | ||
25 | /* | 26 | /* |
26 | * TSC can be unstable due to cpufreq or due to unsynced TSCs | 27 | * TSC can be unstable due to cpufreq or due to unsynced TSCs |
27 | */ | 28 | */ |
28 | static int tsc_unstable; | 29 | static int __read_mostly tsc_unstable; |
29 | 30 | ||
30 | /* native_sched_clock() is called before tsc_init(), so | 31 | /* native_sched_clock() is called before tsc_init(), so |
31 | we must start with the TSC soft disabled to prevent | 32 | we must start with the TSC soft disabled to prevent |
32 | erroneous rdtsc usage on !cpu_has_tsc processors */ | 33 | erroneous rdtsc usage on !cpu_has_tsc processors */ |
33 | static int tsc_disabled = -1; | 34 | static int __read_mostly tsc_disabled = -1; |
34 | 35 | ||
35 | static int tsc_clocksource_reliable; | 36 | static int tsc_clocksource_reliable; |
36 | /* | 37 | /* |
@@ -273,30 +274,43 @@ static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) | |||
273 | * use the TSC value at the transitions to calculate a pretty | 274 | * use the TSC value at the transitions to calculate a pretty |
274 | * good value for the TSC frequencty. | 275 | * good value for the TSC frequencty. |
275 | */ | 276 | */ |
276 | static inline int pit_expect_msb(unsigned char val) | 277 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
277 | { | 278 | { |
278 | int count = 0; | 279 | int count; |
280 | u64 tsc = 0; | ||
279 | 281 | ||
280 | for (count = 0; count < 50000; count++) { | 282 | for (count = 0; count < 50000; count++) { |
281 | /* Ignore LSB */ | 283 | /* Ignore LSB */ |
282 | inb(0x42); | 284 | inb(0x42); |
283 | if (inb(0x42) != val) | 285 | if (inb(0x42) != val) |
284 | break; | 286 | break; |
287 | tsc = get_cycles(); | ||
285 | } | 288 | } |
286 | return count > 50; | 289 | *deltap = get_cycles() - tsc; |
290 | *tscp = tsc; | ||
291 | |||
292 | /* | ||
293 | * We require _some_ success, but the quality control | ||
294 | * will be based on the error terms on the TSC values. | ||
295 | */ | ||
296 | return count > 5; | ||
287 | } | 297 | } |
288 | 298 | ||
289 | /* | 299 | /* |
290 | * How many MSB values do we want to see? We aim for a | 300 | * How many MSB values do we want to see? We aim for |
291 | * 15ms calibration, which assuming a 2us counter read | 301 | * a maximum error rate of 500ppm (in practice the |
292 | * error should give us roughly 150 ppm precision for | 302 | * real error is much smaller), but refuse to spend |
293 | * the calibration. | 303 | * more than 25ms on it. |
294 | */ | 304 | */ |
295 | #define QUICK_PIT_MS 15 | 305 | #define MAX_QUICK_PIT_MS 25 |
296 | #define QUICK_PIT_ITERATIONS (QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) | 306 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
297 | 307 | ||
298 | static unsigned long quick_pit_calibrate(void) | 308 | static unsigned long quick_pit_calibrate(void) |
299 | { | 309 | { |
310 | int i; | ||
311 | u64 tsc, delta; | ||
312 | unsigned long d1, d2; | ||
313 | |||
300 | /* Set the Gate high, disable speaker */ | 314 | /* Set the Gate high, disable speaker */ |
301 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | 315 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
302 | 316 | ||
@@ -315,45 +329,52 @@ static unsigned long quick_pit_calibrate(void) | |||
315 | outb(0xff, 0x42); | 329 | outb(0xff, 0x42); |
316 | outb(0xff, 0x42); | 330 | outb(0xff, 0x42); |
317 | 331 | ||
318 | if (pit_expect_msb(0xff)) { | 332 | /* |
319 | int i; | 333 | * The PIT starts counting at the next edge, so we |
320 | u64 t1, t2, delta; | 334 | * need to delay for a microsecond. The easiest way |
321 | unsigned char expect = 0xfe; | 335 | * to do that is to just read back the 16-bit counter |
322 | 336 | * once from the PIT. | |
323 | t1 = get_cycles(); | 337 | */ |
324 | for (i = 0; i < QUICK_PIT_ITERATIONS; i++, expect--) { | 338 | inb(0x42); |
325 | if (!pit_expect_msb(expect)) | 339 | inb(0x42); |
326 | goto failed; | 340 | |
341 | if (pit_expect_msb(0xff, &tsc, &d1)) { | ||
342 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | ||
343 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | ||
344 | break; | ||
345 | |||
346 | /* | ||
347 | * Iterate until the error is less than 500 ppm | ||
348 | */ | ||
349 | delta -= tsc; | ||
350 | if (d1+d2 < delta >> 11) | ||
351 | goto success; | ||
327 | } | 352 | } |
328 | t2 = get_cycles(); | ||
329 | |||
330 | /* | ||
331 | * Make sure we can rely on the second TSC timestamp: | ||
332 | */ | ||
333 | if (!pit_expect_msb(expect)) | ||
334 | goto failed; | ||
335 | |||
336 | /* | ||
337 | * Ok, if we get here, then we've seen the | ||
338 | * MSB of the PIT decrement QUICK_PIT_ITERATIONS | ||
339 | * times, and each MSB had many hits, so we never | ||
340 | * had any sudden jumps. | ||
341 | * | ||
342 | * As a result, we can depend on there not being | ||
343 | * any odd delays anywhere, and the TSC reads are | ||
344 | * reliable. | ||
345 | * | ||
346 | * kHz = ticks / time-in-seconds / 1000; | ||
347 | * kHz = (t2 - t1) / (QPI * 256 / PIT_TICK_RATE) / 1000 | ||
348 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (QPI * 256 * 1000) | ||
349 | */ | ||
350 | delta = (t2 - t1)*PIT_TICK_RATE; | ||
351 | do_div(delta, QUICK_PIT_ITERATIONS*256*1000); | ||
352 | printk("Fast TSC calibration using PIT\n"); | ||
353 | return delta; | ||
354 | } | 353 | } |
355 | failed: | 354 | printk("Fast TSC calibration failed\n"); |
356 | return 0; | 355 | return 0; |
356 | |||
357 | success: | ||
358 | /* | ||
359 | * Ok, if we get here, then we've seen the | ||
360 | * MSB of the PIT decrement 'i' times, and the | ||
361 | * error has shrunk to less than 500 ppm. | ||
362 | * | ||
363 | * As a result, we can depend on there not being | ||
364 | * any odd delays anywhere, and the TSC reads are | ||
365 | * reliable (within the error). We also adjust the | ||
366 | * delta to the middle of the error bars, just | ||
367 | * because it looks nicer. | ||
368 | * | ||
369 | * kHz = ticks / time-in-seconds / 1000; | ||
370 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | ||
371 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | ||
372 | */ | ||
373 | delta += (long)(d2 - d1)/2; | ||
374 | delta *= PIT_TICK_RATE; | ||
375 | do_div(delta, i*256*1000); | ||
376 | printk("Fast TSC calibration using PIT\n"); | ||
377 | return delta; | ||
357 | } | 378 | } |
358 | 379 | ||
359 | /** | 380 | /** |
@@ -523,8 +544,6 @@ unsigned long native_calibrate_tsc(void) | |||
523 | return tsc_pit_min; | 544 | return tsc_pit_min; |
524 | } | 545 | } |
525 | 546 | ||
526 | #ifdef CONFIG_X86_32 | ||
527 | /* Only called from the Powernow K7 cpu freq driver */ | ||
528 | int recalibrate_cpu_khz(void) | 547 | int recalibrate_cpu_khz(void) |
529 | { | 548 | { |
530 | #ifndef CONFIG_SMP | 549 | #ifndef CONFIG_SMP |
@@ -546,7 +565,6 @@ int recalibrate_cpu_khz(void) | |||
546 | 565 | ||
547 | EXPORT_SYMBOL(recalibrate_cpu_khz); | 566 | EXPORT_SYMBOL(recalibrate_cpu_khz); |
548 | 567 | ||
549 | #endif /* CONFIG_X86_32 */ | ||
550 | 568 | ||
551 | /* Accelerators for sched_clock() | 569 | /* Accelerators for sched_clock() |
552 | * convert from cycles(64bits) => nanoseconds (64bits) | 570 | * convert from cycles(64bits) => nanoseconds (64bits) |